From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/top/Makefile.common | 59 + fpga/usrp3/top/b200/.gitignore | 5 + fpga/usrp3/top/b200/Makefile | 97 + fpga/usrp3/top/b200/Makefile.b200.inc | 143 + fpga/usrp3/top/b200/S6CLK2PIN.v | 23 + fpga/usrp3/top/b200/b200.ucf | 245 + fpga/usrp3/top/b200/b200.v | 365 + fpga/usrp3/top/b200/b200_core.v | 423 + fpga/usrp3/top/b200/b200_io.v | 554 + fpga/usrp3/top/b200/check.sh | 1 + fpga/usrp3/top/b200/core_compile | 1 + fpga/usrp3/top/b200/coregen/.gitignore | 5 + .../usrp3/top/b200/coregen/b200_chipscope_icon.asy | 9 + .../b200_chipscope_icon.ucf | 9 + .../b200_chipscope_icon.xdc | 7 + .../usrp3/top/b200/coregen/b200_chipscope_icon.ncf | 0 .../usrp3/top/b200/coregen/b200_chipscope_icon.ngc | 3 + .../usrp3/top/b200/coregen/b200_chipscope_icon.ucf | 9 + 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fpga/usrp3/top/x300/x300_sfpp_io_core.v create mode 100644 fpga/usrp3/top/x300/x300_static_router.hex create mode 100644 fpga/usrp3/top/x300/x300_zpu_config.vhd create mode 100644 fpga/usrp3/top/x300/x310_rfnoc_image_core.v create mode 100644 fpga/usrp3/top/x300/x310_rfnoc_image_core.yml create mode 100644 fpga/usrp3/top/x300/x310_static_router.hex create mode 100644 fpga/usrp3/top/x300/x3x0_base.lvbitx (limited to 'fpga/usrp3/top') diff --git a/fpga/usrp3/top/Makefile.common b/fpga/usrp3/top/Makefile.common new file mode 100644 index 000000000..e005fcb8a --- /dev/null +++ b/fpga/usrp3/top/Makefile.common @@ -0,0 +1,59 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +################################################## +# Constants +################################################## +ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) +ifeq ($(ISE_VER),10) + ISE_EXT = ise +else + ISE_EXT = xise +endif +BASE_DIR = $(abspath ..) +ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit +TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr + +################################################## +# Global Targets +################################################## +all: bin + +proj: $(ISE_FILE) + +check: $(ISE_FILE) + #$(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf + $(ISE_HELPER) "Check Syntax" + +synth: $(ISE_FILE) + $(ISE_HELPER) "Synthesize - XST" + +#bin: check $(BIN_FILE) +bin: $(BIN_FILE) $(BIT_FILE) + $(TIMING_CHECKER) $(TWR_FILE) + +clean: + $(RM) -r $(BUILD_DIR) + +.PHONY: all proj check synth bin mcs clean + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: +$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "" + +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "Generate Programming File" 2>&1 | tee $(BUILD_DIR)/build.log + touch $@ + +.EXPORT_ALL_VARIABLES: diff --git a/fpga/usrp3/top/b200/.gitignore b/fpga/usrp3/top/b200/.gitignore new file mode 100644 index 000000000..376246b05 --- /dev/null +++ b/fpga/usrp3/top/b200/.gitignore @@ -0,0 +1,5 @@ +build* +catcap_tb +catgen_tb +fuse* +isim* diff --git a/fpga/usrp3/top/b200/Makefile b/fpga/usrp3/top/b200/Makefile new file mode 100644 index 000000000..8a3569e00 --- /dev/null +++ b/fpga/usrp3/top/b200/Makefile @@ -0,0 +1,97 @@ +# +# Copyright 2012-2014 Ettus Research LLC +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP B2X0 FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga.bit: Configuration bitstream with header +## build/usrp__fpga.bin: Configuration bitstream without header +## build/usrp__fpga.syr: Xilinx system report +## build/usrp__fpga.twr: Xilinx timing report + +# Build USRP B2x0 design with a debug UART on J400 +ifeq ($(DEBUG_UART),1) +OPTIONS += DEBUG_UART=1 +endif + +print_report = \ + echo "========================================================================"; \ + cat $(1)/b200.syr | grep "Device utilization summary:" -A 30; \ + echo "========================================================================"; \ + echo "Timing Summary:\n"; \ + cat $(1)/b200.twr | grep constraint | grep met | grep -v "*"; \ + echo "========================================================================"; + +# pre_build($1=Device) +ifeq ($(EXPORT_ONLY),1) + pre_build = @test -s build-$(1)/b200.bit || { echo "EXPORT_ONLY requires the project in build-$(1) to be fully built."; false; } +else + pre_build = @echo "ISE Version: $(shell xtclsh -h | head -n1)" +endif + +# ise_build($1=Device, $2=Definitions) +ifeq ($(PROJECT_ONLY),1) + ise_build = make -f Makefile.b200.inc proj NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)" +else ifeq ($(EXPORT_ONLY),1) + ise_build = @echo "Skipping ISE build and exporting pre-built files."; +else + ise_build = make -f Makefile.b200.inc bin NAME=$@ DEVICE=$1 EXTRA_DEFS="$2 $(OPTIONS)" +endif + +# post_build($1=Device) +ifeq ($(PROJECT_ONLY),1) + post_build = \ + @echo "Generated $(shell pwd)/build-$(1)/b200.xise"; \ + echo "\nProject Generation DONE ... $(1)\n"; +else + post_build = \ + @$(call print_report,build-$(1)) \ + mkdir -p build; \ + echo "Exporting bitstream files..."; \ + cp build-$(1)/b200.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \ + cp build-$(1)/b200.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bit; \ + echo "Exporting logs..."; \ + cp build-$(1)/b200.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \ + cp build-$(1)/b200.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \ + echo "\nBuild DONE ... $(1)\n"; +endif + +## +##Supported Targets +##----------------- + +all: B200 B210 ##(Default target) + +B200: ##Build USRP B200 design. + $(call pre_build,B200) + $(call ise_build,XC6SLX75,) + $(call post_build,B200) + +B210: ##Build USRP B210 design. + $(call pre_build,B210) + $(call ise_build,XC6SLX150,TARGET_B210=1) + $(call post_build,B210) + +clean: ##Clean up all build output. + rm -rf build-* + rm -rf build + +help: ## Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##PROJECT_ONLY=1 Only create a Xilinx project for the specified target(s). +## Useful for use with the ISE GUI. +##EXPORT_ONLY=1 Export build targets from a GUI build to the build directory. +## Requires the project in build-*_* to be built. +##DEBUG_UART=1 Build USRP B2x0 design with a debug UART on J400 + +.PHONY: all clean help diff --git a/fpga/usrp3/top/b200/Makefile.b200.inc b/fpga/usrp3/top/b200/Makefile.b200.inc new file mode 100644 index 000000000..788280c6a --- /dev/null +++ b/fpga/usrp3/top/b200/Makefile.b200.inc @@ -0,0 +1,143 @@ +# +# Copyright 2012-2013 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE := b200 +BUILD_DIR := build-$(NAME)/ +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +include ../Makefile.common +include ../../lib/gpif2/Makefile.srcs +include ../../lib/fifo/Makefile.srcs +include ../../lib/fifo_200/Makefile.srcs +include ../../lib/dsp/Makefile.srcs +include ../../lib/control/Makefile.srcs +include ../../lib/control_200/Makefile.srcs +include ../../lib/packet_proc/Makefile.srcs +include ../../lib/packet_proc_200/Makefile.srcs +include ../../lib/timing/Makefile.srcs +include ../../lib/vita_200/Makefile.srcs +include ../../lib/wishbone/Makefile.srcs +include ../../lib/axi/Makefile.srcs +include ../../lib/radio_200/Makefile.srcs +include ../../lib/io_cap_gen/Makefile.srcs +include coregen_dsp/Makefile.srcs + + +B200_COREGEN_SRCS = \ +coregen/b200_clk_gen.v \ +coregen/fifo_4k_2clk.xco \ +coregen/fifo_short_2clk.xco \ +coregen/chipscope_icon.v \ +coregen/chipscope_icon.xco \ +coregen/chipscope_ila_32.v \ +coregen/chipscope_ila_32.xco \ +coregen/chipscope_ila_128.v \ +coregen/chipscope_ila_128.xco \ +coregen/chipscope_ila_256.v \ +coregen/chipscope_ila_256.xco + + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan6" \ +device $(DEVICE) \ +package fgg484 \ +speed -3 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +b200.v \ +b200_core.v \ +b200_io.v \ +b200.ucf \ +timing.ucf \ +S6CLK2PIN.v \ +$(B200_COREGEN_SRCS) + +# GPIO only available for B210 +# The LX75 on the B200 is missing the connection from the balls to the internal fabric +ifeq ($(NAME),B210) +TOP_SRCS+=gpio.ucf +endif + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \ +$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \ +$(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) \ +$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \ +$(WISHBONE_SRCS) \ +$(TIMING_SRCS) \ +$(DSP_SRCS) \ +$(VITA_200_SRCS) \ +$(AXI_SRCS) \ +$(RADIO_200_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(COREGEN_DSP_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \ +"Other XST Command Line Options" "-loop_iteration_limit 16385" + +#"Number of Clock Buffers" 8 \ + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Unused IOB Pins" "Pull Up" + +#"Configuration Rate" 6 \ +#"Enable Outputs (Output Events)" 6 \ + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp3/top/b200/S6CLK2PIN.v b/fpga/usrp3/top/b200/S6CLK2PIN.v new file mode 100644 index 000000000..a9d6332ef --- /dev/null +++ b/fpga/usrp3/top/b200/S6CLK2PIN.v @@ -0,0 +1,23 @@ +module S6CLK2PIN +( + input I, + output O +); + + ODDR2 #( + .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1" + .INIT(1'b0), // output to 1'b0 or 1'b1 + .SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC" + + ODDR2_S6CLK2PIN + ( + .Q(O), // 1-bit DDR output data + .C0(I), // 1-bit clock input + .C1(~I), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b1), // 1-bit data input (associated with C0) + .D1(1'b0), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) );// 1-bit set input + +endmodule //S6CLK2PIN diff --git a/fpga/usrp3/top/b200/b200.ucf b/fpga/usrp3/top/b200/b200.ucf new file mode 100644 index 000000000..501b06c33 --- /dev/null +++ b/fpga/usrp3/top/b200/b200.ucf @@ -0,0 +1,245 @@ +## SPI Nets + +NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = "H20" | IOSTANDARD = LVCMOS18 ; +NET "fx3_miso" LOC = "G20" | IOSTANDARD = LVCMOS18 ; +NET "fx3_mosi" LOC = "AA20" | IOSTANDARD = LVCMOS18 ; +#NET "fx3_mosi" LOC = "A9" | IOSTANDARD = LVCMOS33 ; +NET "fx3_sclk" LOC = "Y21" | IOSTANDARD = LVCMOS18 ; + +NET "pll_ce" LOC = "W11" | IOSTANDARD = LVCMOS18 ; +NET "pll_mosi" LOC = "AB11" | IOSTANDARD = LVCMOS18 ; +NET "pll_sclk" LOC = "Y12" | IOSTANDARD = LVCMOS18 ; + +## UART header not always connected so has pullups. Can also be GPIO as build option. +NET "FPGA_RXD0" LOC = "AB8" | IOSTANDARD = LVCMOS18 | PULLUP ; +NET "FPGA_TXD0" LOC = "AB7" | IOSTANDARD = LVCMOS18 | PULLUP ; + +## Catalina Controls + +NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18; + +## Catalina Data TX + +NET "tx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 ; +NET "tx_codec_d*" DRIVE = 2; + +## Catalina Data RX + +NET "rx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<2>" LOC = "K2" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<3>" LOC = "G3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<4>" LOC = "M2" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<6>" LOC = "L3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<8>" LOC = "L4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d<11>" LOC = "M4" | IOSTANDARD = LVCMOS18 ; +NET "rx_codec_d*" DRIVE = 2; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ; +NET "codec_main_clk_p" LOC = "K5" | IOSTANDARD = LVDS_25; +NET "codec_main_clk_n" LOC = "K4" | IOSTANDARD = LVDS_25; + +NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 ; + +## Debug Bus + +NET "debug<0>" LOC = "D10" | IOSTANDARD = LVCMOS33 ; +NET "debug<1>" LOC = "D9" | IOSTANDARD = LVCMOS33 ; +NET "debug<2>" LOC = "A8" | IOSTANDARD = LVCMOS33 ; +NET "debug<3>" LOC = "B8" | IOSTANDARD = LVCMOS33 ; +NET "debug<4>" LOC = "C8" | IOSTANDARD = LVCMOS33 ; +NET "debug<5>" LOC = "D8" | IOSTANDARD = LVCMOS33 ; +NET "debug<6>" LOC = "A7" | IOSTANDARD = LVCMOS33 ; +NET "debug<7>" LOC = "D7" | IOSTANDARD = LVCMOS33 ; +NET "debug<8>" LOC = "A6" | IOSTANDARD = LVCMOS33 ; +NET "debug<9>" LOC = "B6" | IOSTANDARD = LVCMOS33 ; +NET "debug<10>" LOC = "C6" | IOSTANDARD = LVCMOS33 ; +NET "debug<11>" LOC = "D6" | IOSTANDARD = LVCMOS33 ; +NET "debug<12>" LOC = "A5" | IOSTANDARD = LVCMOS33 ; +NET "debug<13>" LOC = "A4" | IOSTANDARD = LVCMOS33 ; +NET "debug<14>" LOC = "C5" | IOSTANDARD = LVCMOS33 ; +NET "debug<15>" LOC = "A3" | IOSTANDARD = LVCMOS33 ; +NET "debug<16>" LOC = "A18" | IOSTANDARD = LVCMOS33 ; +NET "debug<17>" LOC = "B18" | IOSTANDARD = LVCMOS33 ; +NET "debug<18>" LOC = "A17" | IOSTANDARD = LVCMOS33 ; +NET "debug<19>" LOC = "C17" | IOSTANDARD = LVCMOS33 ; +NET "debug<20>" LOC = "C14" | IOSTANDARD = LVCMOS33 ; +NET "debug<21>" LOC = "D12" | IOSTANDARD = LVCMOS33 ; +NET "debug<22>" LOC = "C10" | IOSTANDARD = LVCMOS33 ; +NET "debug<23>" LOC = "F15" | IOSTANDARD = LVCMOS33 ; +NET "debug<24>" LOC = "E14" | IOSTANDARD = LVCMOS33 ; +NET "debug<25>" LOC = "F14" | IOSTANDARD = LVCMOS33 ; +NET "debug<26>" LOC = "H14" | IOSTANDARD = LVCMOS33 ; +NET "debug<27>" LOC = "D13" | IOSTANDARD = LVCMOS33 ; +NET "debug<28>" LOC = "F13" | IOSTANDARD = LVCMOS33 ; +NET "debug<29>" LOC = "G13" | IOSTANDARD = LVCMOS33 ; +NET "debug<30>" LOC = "E12" | IOSTANDARD = LVCMOS33 ; +NET "debug<31>" LOC = "H13" | IOSTANDARD = LVCMOS33 ; + +NET "debug_clk<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 ; +NET "debug_clk<1>" LOC = "C12" | IOSTANDARD = LVCMOS33 ; + +NET "debug*" DRIVE = 2; + +## GPIF + +NET "IFCLK" LOC = "H21" | IOSTANDARD = LVCMOS18 ; +NET "FX3_EXTINT" LOC = "U20" | IOSTANDARD = LVCMOS18 ; + +NET "IFCLK" DRIVE = 8; +NET "IFCLK" SLEW = SLOW; + +NET "GPIF_CTL0" LOC = "P22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL1" LOC = "N22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL2" LOC = "AA18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL3" LOC = "AB18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL4" LOC = "P19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL5" LOC = "AA2" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL6" LOC = "M22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL7" LOC = "AB19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL8" LOC = "M19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL9" LOC = "R20" | IOSTANDARD = LVCMOS18 ; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = "M21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_CTL12" LOC = "M20" | IOSTANDARD = LVCMOS18 ; + +NET "GPIF_D<0>" LOC = "T17" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<1>" LOC = "U14" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<2>" LOC = "U13" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<3>" LOC = "AA6" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<4>" LOC = "AB6" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<5>" LOC = "Y3" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<6>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<7>" LOC = "AA4" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<8>" LOC = "V20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<9>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<10>" LOC = "V21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<11>" LOC = "T22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<12>" LOC = "U22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<13>" LOC = "R22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<14>" LOC = "AA12" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<15>" LOC = "AB12" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<16>" LOC = "Y13" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<17>" LOC = "N20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<18>" LOC = "T21" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<19>" LOC = "K18" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<20>" LOC = "H22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<21>" LOC = "J20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<22>" LOC = "K19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<23>" LOC = "L19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<24>" LOC = "N19" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<25>" LOC = "K22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<26>" LOC = "L22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<27>" LOC = "L20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<28>" LOC = "J22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<29>" LOC = "K20" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<30>" LOC = "G22" | IOSTANDARD = LVCMOS18 ; +NET "GPIF_D<31>" LOC = "F22" | IOSTANDARD = LVCMOS18 ; + +NET "GPIF_*" DRIVE = 2; +NET "GPIF_*" SLEW = SLOW; + +## GPS + +NET "gps_lock" LOC = "B14" | IOSTANDARD = LVCMOS33 ; +NET "gps_rxd" LOC = "A15" | IOSTANDARD = LVCMOS33 ; +NET "gps_txd" LOC = "A14" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "gps_txd_nmea" LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP ; + +## LEDS + +NET "LED_RX1" LOC = "C22" | IOSTANDARD = LVCMOS18 ; +NET "LED_RX2" LOC = "L15" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX1_TX" LOC = "C20" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX2_RX" LOC = "D21" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX1_RX" LOC = "K16" | IOSTANDARD = LVCMOS18 ; +NET "LED_TXRX2_TX" LOC = "D22" | IOSTANDARD = LVCMOS18 ; + +## Misc Hardware Control +NET "ref_sel" LOC = "AA14" | IOSTANDARD = LVCMOS18 ; +NET "pll_lock" LOC = "AB10" | IOSTANDARD = LVCMOS18 ; +NET "AUX_PWR_ON" LOC = "B16" | IOSTANDARD = LVCMOS33 ; +#NET "RFUSE" LOC = "P15" | IOSTANDARD = LVCMOS33 ; + +## PPS + +NET "PPS_IN_EXT" LOC = "B10" | IOSTANDARD = LVCMOS33 ; +NET "PPS_IN_INT" LOC = "A10" | IOSTANDARD = LVCMOS33 ; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = "A16" | IOSTANDARD = LVCMOS33 ; +NET "SFDX1_TX" LOC = "D14" | IOSTANDARD = LVCMOS33 ; +NET "SFDX2_RX" LOC = "C11" | IOSTANDARD = LVCMOS33 ; +NET "SFDX2_TX" LOC = "A11" | IOSTANDARD = LVCMOS33 ; +NET "SRX1_RX" LOC = "D15" | IOSTANDARD = LVCMOS33 ; +NET "SRX1_TX" LOC = "C16" | IOSTANDARD = LVCMOS33 ; +NET "SRX2_RX" LOC = "B12" | IOSTANDARD = LVCMOS33 ; +NET "SRX2_TX" LOC = "D11" | IOSTANDARD = LVCMOS33 ; +NET "tx_bandsel_a" LOC = "C13" | IOSTANDARD = LVCMOS33 ; +NET "tx_bandsel_b" LOC = "D17" | IOSTANDARD = LVCMOS33 ; +NET "tx_enable1" LOC = "Y4" | IOSTANDARD = LVCMOS18 ; +NET "tx_enable2" LOC = "R19" | IOSTANDARD = LVCMOS18 ; +NET "rx_bandsel_a" LOC = "C9" | IOSTANDARD = LVCMOS33 ; +NET "rx_bandsel_b" LOC = "A13" | IOSTANDARD = LVCMOS33 ; +NET "rx_bandsel_c" LOC = "E16" | IOSTANDARD = LVCMOS33 ; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_DONE" LOC = "Y22" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_M0" LOC = "AA22" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_M1" LOC = "U15" | IOSTANDARD = LVCMOS18 ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" | IOSTANDARD = LVCMOS18 ; + +## Special Pins + +#NET "VFS" LOC = "P16" | IOSTANDARD = LVCMOS33 ; +#NET "TMS" LOC = "C18" | IOSTANDARD = LVCMOS33 ; +#NET "TDO" LOC = "A19" | IOSTANDARD = LVCMOS33 ; +#NET "TDI" LOC = "E18" | IOSTANDARD = LVCMOS33 ; +#NET "TCK" LOC = "G15" | IOSTANDARD = LVCMOS33 ; +#NET "GND" LOC = "N15" | IOSTANDARD = LVCMOS33 ; diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v new file mode 100644 index 000000000..811842f32 --- /dev/null +++ b/fpga/usrp3/top/b200/b200.v @@ -0,0 +1,365 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + + +/*********************************************************** + * B200 Module Declaration + **********************************************************/ +module b200 ( + // SPI Interfaces + output cat_ce, + input cat_miso, + output cat_mosi, + output cat_sclk, + + input fx3_ce, + output fx3_miso, + input fx3_mosi, + input fx3_sclk, + + output pll_ce, + output pll_mosi, + output pll_sclk, + + // UART + // By default these provide an FX3 UART console output. Under compile time control they can alternatively + // provide 2 (1.8V) GPIO pins which are logically bits [9:8] of the fp_gpio bus. + // Used as a UART RXD is an input and TXD an output electrically. + // input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and + // output FPGA_TXD0, // carry FX3 UART. + inout FPGA_RXD0, // These pins goto 3 pin 0.1" header J400 on B2x0 and + inout FPGA_TXD0, // carry FX3 UART. + + // Catalina Controls + output codec_enable, + output codec_en_agc, + output codec_reset, + output codec_sync, + output codec_txrx, + output [3:0] codec_ctrl_in, // These should be outputs + input [7:0] codec_ctrl_out, // MUST BE INPUT + + // Catalina Data + input codec_data_clk_p, // Clock from CAT (RX) + output codec_fb_clk_p, // Clock to CAT (TX) + input [11:0] rx_codec_d, + output [11:0] tx_codec_d, + input rx_frame_p, + output tx_frame_p, + + input cat_clkout_fpga, + + //always on 40MHz clock + input codec_main_clk_p, + input codec_main_clk_n, + + // Debug Bus + output [31:0] debug, + output [1:0] debug_clk, + + // GPIF, FX3 Slave FIFO + output IFCLK, // pclk + input FX3_EXTINT, + output GPIF_CTL0, // n_slcs + output GPIF_CTL1, // n_slwr + output GPIF_CTL2, // n_sloe + output GPIF_CTL3, // n_slrd + output GPIF_CTL7, // n_pktend + input GPIF_CTL4, // slfifo_flags[0] + input GPIF_CTL5, // slfifo_flags[1] + input GPIF_CTL6, // Serial settings bus from FX3. SDA + input GPIF_CTL8, // Serial settings bus from FX3. SCL + output GPIF_CTL11, // slfifo_addr[1] + output GPIF_CTL12, // slfifo_addr[0] + inout [31:0] GPIF_D, + input GPIF_CTL9, // global_reset + + // GPS + input gps_lock, + output gps_rxd, + input gps_txd, // FPGA has pullup for unpopulated GPS + input gps_txd_nmea, // FPGA has pullup for unpopulated GPS + + // LEDS + output LED_RX1, + output LED_RX2, + output LED_TXRX1_RX, + output LED_TXRX1_TX, + output LED_TXRX2_RX, + output LED_TXRX2_TX, + + // GPIO Header J504 - 10 pin 0.1" 3.3V. + // Only present on Rev6 and later boards...these pins unused on Rev5 and earlier. + // NOTE: These pins are allocated from complimentry pairs and could potentially be used + // as differential style I/O. + `ifdef TARGET_B210 + inout [7:0] fp_gpio, + `endif + // Misc Hardware Control + output ref_sel, + input pll_lock, + input FPGA_CFG_CS, // Driven by FX3 gpio. + input AUX_PWR_ON, // Driven by FX3 gpio. + + // PPS + input PPS_IN_EXT, + input PPS_IN_INT, + + // RF Hardware Control + output SFDX1_RX, + output SFDX1_TX, + output SFDX2_RX, + output SFDX2_TX, + output SRX1_RX, + output SRX1_TX, + output SRX2_RX, + output SRX2_TX, + output tx_bandsel_a, + output tx_bandsel_b, + output tx_enable1, + output tx_enable2, + output rx_bandsel_a, + output rx_bandsel_b, + output rx_bandsel_c + ); + + wire reset_global = GPIF_CTL9; + + /////////////////////////////////////////////////////////////////////// + // generate clocks from always on codec main clk + /////////////////////////////////////////////////////////////////////// + wire bus_clk, gpif_clk, radio_clk; + wire locked; + b200_clk_gen gen_clks + ( + .CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n), + .CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(), + .RESET(reset_global), .LOCKED(locked) + ); + + // Bus Clock and GPIF Clock both same 100MHz clock. + assign bus_clk = gpif_clk; + + + //hold-off logic for clocks ready + reg [15:0] clocks_ready_count; + reg clocks_ready; + always @(posedge bus_clk or posedge reset_global or negedge locked) begin + if (reset_global | !locked) begin + clocks_ready_count <= 16'b0; + clocks_ready <= 1'b0; + end + else if (!clocks_ready) begin + clocks_ready_count <= clocks_ready_count + 1'b1; + clocks_ready <= (clocks_ready_count == 16'hffff); + end + end + + /////////////////////////////////////////////////////////////////////// + // drive output clocks + /////////////////////////////////////////////////////////////////////// + wire [1:0] debug_clk_int; + //S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0])); + //S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1])); + assign debug_clk[1:0] = 2'b0; + S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK)); + + /////////////////////////////////////////////////////////////////////// + // Create sync reset signals + /////////////////////////////////////////////////////////////////////// + wire gpif_rst, bus_rst, radio_rst; + reset_sync gpif_sync(.clk(gpif_clk), .reset_in(!clocks_ready), .reset_out(gpif_rst)); + reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); + reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst)); + + /////////////////////////////////////////////////////////////////////// + // I/O + /////////////////////////////////////////////////////////////////////// + wire [31:0] rx_data0, rx_data1; + wire [31:0] tx_data0, tx_data1; + wire mimo; + + b200_io b200_io_i0 + ( + .reset(reset), + .mimo(mimo), + + // Baseband sample interface + .radio_clk(radio_clk), + + .rx_i0(rx_data0[31:20]), + .rx_q0(rx_data0[15:4]), + .rx_i1(rx_data1[31:20]), + .rx_q1(rx_data1[15:4]), + + .tx_i0(tx_data0[31:20]), + .tx_q0(tx_data0[15:4]), + .tx_i1(tx_data1[31:20]), + .tx_q1(tx_data1[15:4]), + + // Catalina interface + .rx_clk(codec_data_clk_p), + .rx_frame(rx_frame_p), + .rx_data(rx_codec_d), + + .tx_clk(codec_fb_clk_p), + .tx_frame(tx_frame_p), + .tx_data(tx_codec_d) + ); + + assign {rx_data0[19:16],rx_data0[3:0],rx_data1[19:16],rx_data1[3:0]} = 16'h0; + + /////////////////////////////////////////////////////////////////////// + // SPI connections + /////////////////////////////////////////////////////////////////////// + wire mosi, miso, sclk; + wire [7:0] sen; + + //AD9361 Slave + assign cat_ce = sen[0]; + assign cat_mosi = ~sen[0] & mosi; + assign cat_sclk = ~sen[0] & sclk; + assign miso = cat_miso; //PLL does not have a miso + + //ADF4001 Slave + assign pll_ce = sen[1]; + assign pll_mosi = ~sen[1] & mosi; + assign pll_sclk = ~sen[1] & sclk; + + //FX3 Master + //The following signals are routed to the FX3 and were used by an obsolete + //bit-banging SPI engine. + // fx3_ce, fx3_sclk, fx3_mosi + assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the + //direction of this pin in the FX3 + + /////////////////////////////////////////////////////////////////////// + // bus signals + /////////////////////////////////////////////////////////////////////// + wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata; + wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast; + wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid; + wire ctrl_tready, resp_tready, rx_tready, tx_tready; + + + /////////////////////////////////////////////////////////////////////// + // frontend assignments + // Most B2x0's have frontends swapped (radio0 to FE2), but some hardware revisions do not. + // The ATR pins are mapped from radio to frontend here based on the swap_atr_n bit. + /////////////////////////////////////////////////////////////////////// + wire swap_atr_n; + wire [7:0] radio0_gpio, radio1_gpio; + reg [7:0] fe0_gpio, fe1_gpio; + always @(posedge radio_clk) begin //Registers in the IOB + fe0_gpio <= swap_atr_n ? radio1_gpio : radio0_gpio; + fe1_gpio <= swap_atr_n ? radio0_gpio : radio1_gpio; + end + assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe0_gpio; + assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe1_gpio; + + wire [31:0] misc_outs; reg [31:0] misc_outs_r; + + always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop + + wire codec_arst; + + assign { swap_atr_n, tx_bandsel_a, tx_bandsel_b, rx_bandsel_a, rx_bandsel_b, rx_bandsel_c, codec_arst, mimo, ref_sel } = misc_outs_r[8:0]; + + assign codec_ctrl_in = 4'b1; + assign codec_en_agc = 1'b1; + assign codec_txrx = 1'b1; + assign codec_enable = 1'b1; + assign codec_reset = ~codec_arst; // Codec Reset // RESETB // Operates active-low + assign codec_sync = 1'b0; + + /////////////////////////////////////////////////////////////////////// + // b200 core + /////////////////////////////////////////////////////////////////////// + wire [9:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr; + + b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core + ( + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx0(rx_data0), .rx1(rx_data1), + .tx0(tx_data0), .tx1(tx_data1), + .fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + + .pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT), + + .rxd(gps_txd), .txd(gps_rxd), + .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso), + .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs), + + .debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6), +`ifdef DEBUG_UART + .debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0), +`else + .debug_txd(), .debug_rxd(1'b0), +`endif + + .lock_signals(codec_ctrl_out[7:6]), + .debug() + ); + +`ifdef TARGET_B210 + `ifdef DEBUG_UART + gpio_atr_io #(.WIDTH(8)) gpio_atr_io_inst ( // B210 with UART + .clk(radio_clk), .gpio_pins(fp_gpio), + .gpio_ddr(fp_gpio_ddr[7:0]), .gpio_out(fp_gpio_out[7:0]), .gpio_in(fp_gpio_in[7:0]) + ); + assign fp_gpio_in[9:8] = 2'b00; + `else + gpio_atr_io #(.WIDTH(10)) gpio_atr_io_inst ( // B210 no UART + .clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0, fp_gpio}), + .gpio_ddr(fp_gpio_ddr), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in) + ); + `endif +`else + `ifdef DEBUG_UART + assign fp_gpio_in = 10'h000; // B200 with UART + `else + gpio_atr_io #(.WIDTH(2)) gpio_atr_io_inst ( // B200 no UART + .clk(radio_clk), .gpio_pins({FPGA_RXD0, FPGA_TXD0}), + .gpio_ddr(fp_gpio_ddr[9:8]), .gpio_out(fp_gpio_out[9:8]), .gpio_in(fp_gpio_in[9:8]) + ); + assign fp_gpio_in[7:0] = 8'h00; + `endif +`endif + + /////////////////////////////////////////////////////////////////////// + // GPIF2 + /////////////////////////////////////////////////////////////////////// + + gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(13), .DATA_TX_FIFO_SIZE(13)) slave_fifo32 + ( + .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1), + .gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}), + .slwr(GPIF_CTL1), .sloe(GPIF_CTL2), .slcs(GPIF_CTL0), .slrd(GPIF_CTL3), .pktend(GPIF_CTL7), + .gpif_d(GPIF_D), + + .fifo_clk(bus_clk), .fifo_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .debug() + ); + + /////////////////////////////////////////////////////////////////////// + // Debug port + /////////////////////////////////////////////////////////////////////// + assign debug = 0; + +endmodule // B200 diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v new file mode 100644 index 000000000..f03c5ea1f --- /dev/null +++ b/fpga/usrp3/top/b200/b200_core.v @@ -0,0 +1,423 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + + +/*********************************************************** + * B200 Core Guts + **********************************************************/ +module b200_core +#( + parameter R0_CTRL_SID = 8'h10, + parameter R1_CTRL_SID = 8'h20, + parameter U0_CTRL_SID = 8'h30, + parameter L0_CTRL_SID = 8'h40, + parameter R0_DATA_SID = 8'h50, + parameter R1_DATA_SID = 8'h60, + parameter DEMUX_SID_MASK = 8'hf0, + parameter EXTRA_BUFF_SIZE = 0, + parameter RADIO_FIFO_SIZE = 11, + parameter SAMPLE_FIFO_SIZE = 11 + +) +( + //////////////////////////////////////////////////////////////////// + // bus interfaces + //////////////////////////////////////////////////////////////////// + input bus_clk, + input bus_rst, + + input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, + output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, + input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready, + output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready, + + //////////////////////////////////////////////////////////////////// + // radio interfaces + //////////////////////////////////////////////////////////////////// + input radio_clk, + input radio_rst, + + input [31:0] rx0, input [31:0] rx1, + output [31:0] tx0, output [31:0] tx1, + output [7:0] fe0_gpio_out, output [7:0] fe1_gpio_out, + input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr, + input pps_int, input pps_ext, + + //////////////////////////////////////////////////////////////////// + // gpsdo uart + //////////////////////////////////////////////////////////////////// + input rxd, + output txd, + + //////////////////////////////////////////////////////////////////// + // core interfaces + //////////////////////////////////////////////////////////////////// + output [7:0] sen, output sclk, output mosi, input miso, + input [31:0] rb_misc, + output [31:0] misc_outs, + //////////////////////////////////////////////////////////////////// + // debug UART + //////////////////////////////////////////////////////////////////// + output debug_txd, input debug_rxd, + input debug_scl, input debug_sda, + + //////////////////////////////////////////////////////////////////// + // fe lock signals + //////////////////////////////////////////////////////////////////// + input [1:0] lock_signals, + + //////////////////////////////////////////////////////////////////// + // debug signals + //////////////////////////////////////////////////////////////////// + output [63:0] debug +); + localparam SR_CORE_SPI = 8'd8; + localparam SR_CORE_MISC = 8'd16; + localparam SR_CORE_COMPAT = 8'd24; + localparam SR_CORE_READBACK = 8'd32; + localparam SR_CORE_GPSDO_ST = 8'd40; + localparam SR_CORE_SYNC = 8'd48; + localparam COMPAT_MAJOR = 16'h0010; + localparam COMPAT_MINOR = 16'h0000; + + reg [1:0] lock_state; + reg [1:0] lock_state_r; + + always @(posedge bus_clk) + if (bus_rst) + {lock_state_r, lock_state} <= 4'h0; + else + {lock_state_r, lock_state} <= {lock_state, lock_signals}; + + + /******************************************************************* + * PPS Timing stuff + ******************************************************************/ + + // Generate an internal PPS signal + wire int_pps; + pps_generator #(.CLK_FREQ(100000000)) pps_gen + (.clk(bus_clk), .reset(1'b0), .pps(int_pps)); + + // Flop PPS signals into radio clock domain + reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del; + always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext}; + always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int}; + always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps}; + + // PPS mux + wire [1:0] pps_select; + wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] : + (pps_select == 2'b01)? ext_pps_del[1] : + (pps_select == 2'b10)? int_pps_del[1] : + 1'b0; + + /******************************************************************* + * Response mux Routing logic + ******************************************************************/ + wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready; + wire [63:0] r1_resp_tdata; wire r1_resp_tlast, r1_resp_tvalid, r1_resp_tready; + wire [63:0] u0_resp_tdata; wire u0_resp_tlast, u0_resp_tvalid, u0_resp_tready; + wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready; + + axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready), + .i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp_tready), + .i2_tdata(u0_resp_tdata), .i2_tlast(u0_resp_tlast), .i2_tvalid(u0_resp_tvalid), .i2_tready(u0_resp_tready), + .i3_tdata(l0_resp_tdata), .i3_tlast(l0_resp_tlast), .i3_tvalid(l0_resp_tvalid), .i3_tready(l0_resp_tready), + .o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready)); + + /******************************************************************* + * Control demux Routing logic + ******************************************************************/ + wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready; + wire [63:0] r1_ctrl_tdata; wire r1_ctrl_tlast, r1_ctrl_tvalid, r1_ctrl_tready; + wire [63:0] u0_ctrl_tdata; wire u0_ctrl_tlast, u0_ctrl_tvalid, u0_ctrl_tready; + wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready; + + wire [63:0] ctrl_hdr; + wire [1:0] ctrl_dst = + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R1_CTRL_SID)? 1 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == U0_CTRL_SID)? 2 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 3 : ( + 3)))); + axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .header(ctrl_hdr), .dest(ctrl_dst), + .i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), + .o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready), + .o1_tdata(r1_ctrl_tdata), .o1_tlast(r1_ctrl_tlast), .o1_tvalid(r1_ctrl_tvalid), .o1_tready(r1_ctrl_tready), + .o2_tdata(u0_ctrl_tdata), .o2_tlast(u0_ctrl_tlast), .o2_tvalid(u0_ctrl_tvalid), .o2_tready(u0_ctrl_tready), + .o3_tdata(l0_ctrl_tdata), .o3_tlast(l0_ctrl_tlast), .o3_tvalid(l0_ctrl_tvalid), .o3_tready(l0_ctrl_tready)); + + /******************************************************************* + * UART + ******************************************************************/ + wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready; + + axi_fifo #(.WIDTH(65), .SIZE(5)) uart_timing_fifo + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(), + .o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied() + ); + + cvita_uart #(.SIZE(7)) uart + ( + .clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd), + .i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready), + .o_tdata(u0_resp_tdata), .o_tlast(u0_resp_tlast), .o_tvalid(u0_resp_tvalid), .o_tready(u0_resp_tready) + ); + + /******************************************************************* + * Misc controls + ******************************************************************/ + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire spi_ready; + wire [31:0] spi_readback; + + wire [7:0] gpsdo_st; + wire [7:0] radio_st; + + wire [1:0] rb_addr; + reg [63:0] rb_data; + + wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready; + + wire time_sync, time_sync_r; + + axi_fifo #(.WIDTH(65), .SIZE(5)) radio_ctrl_proc_timing_fifo + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(), + .o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied() + ); + + radio_ctrl_proc radio_ctrl_proc + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready), + .resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready), + .vita_time(64'b0), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .ready(spi_ready), .readback(rb_data), + .debug()); + + setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(misc_outs), .changed()); + + setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(rb_addr), .changed()); + + setting_reg #(.my_addr(SR_CORE_GPSDO_ST), .awidth(8), .width(8)) sr_gpsdo_st + (.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(gpsdo_st), .changed()); + + setting_reg #(.my_addr(SR_CORE_SYNC), .awidth(8), .width(3)) sr_sync + (.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out({time_sync,pps_select}), .changed()); + + synchronizer time_sync_synchronizer + (.clk(radio_clk), .rst(radio_rst), .in(time_sync), .out(time_sync_r)); + + simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi + (.clock(bus_clk), .reset(bus_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(spi_readback), .ready(spi_ready), + .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso), + .debug()); + + always @* + case(rb_addr) + 2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR }; + 2'd1 : rb_data <= { 32'b0, spi_readback }; + 2'd2 : rb_data <= { 16'b0, radio_st, gpsdo_st, rb_misc }; + 2'd3 : rb_data <= { 30'h0, lock_state_r }; + default : rb_data <= 64'd0; + endcase // case (rb_addr) + + /******************************************************************* + * RX Data mux Routing logic + ******************************************************************/ + wire [63:0] r0_rx_tdata; wire r0_rx_tlast, r0_rx_tvalid, r0_rx_tready; + wire [63:0] r1_rx_tdata; wire r1_rx_tlast, r1_rx_tvalid, r1_rx_tready; + wire [63:0] rx_tdata_int; wire rx_tlast_int, rx_tvalid_int, rx_tready_int; + + axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_rx + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready), + .i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready), + .i2_tdata(64'b0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), + .i3_tdata(64'b0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata(rx_tdata_int), .o_tlast(rx_tlast_int), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int)); + + axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_rx_buff + (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), + .i_tdata({rx_tlast_int, rx_tdata_int}), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int), + .o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready)); + + /******************************************************************* + * TX Data mux Routing logic + ******************************************************************/ + wire [63:0] r0_tx_tdata; wire r0_tx_tlast, r0_tx_tvalid, r0_tx_tready; + wire [63:0] r1_tx_tdata; wire r1_tx_tlast, r1_tx_tvalid, r1_tx_tready; + wire [63:0] tx_tdata_int; wire tx_tlast_int, tx_tvalid_int, tx_tready_int; + + axi_fifo #(.WIDTH(65), .SIZE(EXTRA_BUFF_SIZE)) extra_tx_buff + (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), + .i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), + .o_tdata({tx_tlast_int, tx_tdata_int}), .o_tvalid(tx_tvalid_int), .o_tready(tx_tready_int)); + + wire [63:0] tx_hdr; + wire [1:0] tx_dst = + ((tx_hdr[7:0] & DEMUX_SID_MASK) == R0_DATA_SID)? 0 : ( + ((tx_hdr[7:0] & DEMUX_SID_MASK) == R1_DATA_SID)? 1 : ( + 3)); + axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_for_tx + (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .header(tx_hdr), .dest(tx_dst), + .i_tdata(tx_tdata_int), .i_tlast(tx_tlast_int), .i_tvalid(tx_tvalid_int), .i_tready(tx_tready_int), + .o0_tdata(r0_tx_tdata), .o0_tlast(r0_tx_tlast), .o0_tvalid(r0_tx_tvalid), .o0_tready(r0_tx_tready), + .o1_tdata(r1_tx_tdata), .o1_tlast(r1_tx_tlast), .o1_tvalid(r1_tx_tvalid), .o1_tready(r1_tx_tready), + .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), + .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)); + + /******************************************************************* + * Radio 0 + ******************************************************************/ + wire [63:0] radio0_debug; + wire [31:0] fe0_gpio_out32; + assign fe0_gpio_out = fe0_gpio_out32[7:0]; + + radio_legacy #( + .RADIO_FIFO_SIZE(RADIO_FIFO_SIZE), + .SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE), + .FP_GPIO(1), + .NEW_HB_INTERP(1), + .NEW_HB_DECIM(1), + .SOURCE_FLOW_CONTROL(0), + .USER_SETTINGS(0), + .DEVICE("SPARTAN6") + ) radio_0 ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r), + .fe_gpio_in(32'h00000000), .fe_gpio_out(fe0_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(r0_tx_tdata), .tx_tlast(r0_tx_tlast), .tx_tvalid(r0_tx_tvalid), .tx_tready(r0_tx_tready), + .rx_tdata(r0_rx_tdata), .rx_tlast(r0_rx_tlast), .rx_tvalid(r0_rx_tvalid), .rx_tready(r0_rx_tready), + .ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready), + .resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready), + .debug(radio0_debug) + ); + + /******************************************************************* + * Radio 1 + ******************************************************************/ +`ifdef TARGET_B210 // B210 Has two radio instances. + assign radio_st = 8'h2; + + wire [63:0] radio1_debug; + wire [31:0] fe1_gpio_out32; + assign fe1_gpio_out = fe1_gpio_out32[7:0]; + + radio_legacy #( + .RADIO_FIFO_SIZE(RADIO_FIFO_SIZE), + .SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE), + .FP_GPIO(0), + .NEW_HB_INTERP(1), + .NEW_HB_DECIM(1), + .SOURCE_FLOW_CONTROL(0), + .USER_SETTINGS(0), + .DEVICE("SPARTAN6") + ) radio_1 ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx(rx1), .tx(tx1), .pps(pps), .time_sync(time_sync_r), + .fe_gpio_in(32'h00000000), .fe_gpio_out(fe1_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */), + .fp_gpio_in(32'h00000000), .fp_gpio_out(), .fp_gpio_ddr(), + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(r1_tx_tdata), .tx_tlast(r1_tx_tlast), .tx_tvalid(r1_tx_tvalid), .tx_tready(r1_tx_tready), + .rx_tdata(r1_rx_tdata), .rx_tlast(r1_rx_tlast), .rx_tvalid(r1_rx_tvalid), .rx_tready(r1_rx_tready), + .ctrl_tdata(r1_ctrl_tdata), .ctrl_tlast(r1_ctrl_tlast), .ctrl_tvalid(r1_ctrl_tvalid), .ctrl_tready(r1_ctrl_tready), + .resp_tdata(r1_resp_tdata), .resp_tlast(r1_resp_tlast), .resp_tvalid(r1_resp_tvalid), .resp_tready(r1_resp_tready), + .debug(radio1_debug) + ); +`else + assign radio_st = 8'h1; + + //assign undriven outputs + assign fe1_gpio_out = 32'b0; //Always assumed to be outputs + assign tx1 = 32'b0; + + //unused control signals -- leave in loopback + assign r1_resp_tdata = r1_ctrl_tdata; + assign r1_resp_tlast = r1_ctrl_tlast; + assign r1_resp_tvalid = r1_ctrl_tvalid; + assign r1_ctrl_tready = r1_resp_tready; + + //unused data signals -- leave in loopback + assign r1_rx_tdata = r1_tx_tdata; + assign r1_rx_tlast = r1_tx_tlast; + assign r1_rx_tvalid = r1_tx_tvalid; + assign r1_tx_tready = r1_tx_tready; + +`endif // !`ifdef TARGET_B210 + + /******************************************************************* + * Debug UART for FX3 + ******************************************************************/ + + wire debug_stb; + wire [31:0] debug_data; + wire [7:0] debug_addr; + wire [31:0] debug_serial; + + + serial_to_settings serial_to_settings_i1 + ( + .clk(bus_clk), + .reset(bus_rst), + .scl(debug_scl), + .sda(debug_sda), + .set_stb(debug_stb), + .set_addr(debug_addr), + .set_data(debug_data), + .debug(debug_serial) + ); + + // Nasty Hack to convert settings to wishbone crudely. + reg wb_stb; + wire wb_ack_o; + + always @(posedge bus_clk) + wb_stb <= debug_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb); + + simple_uart debug_uart + ( + .clk_i(bus_clk), + .rst_i(bus_rst), + .we_i(wb_stb), + .stb_i(wb_stb), + .cyc_i(wb_stb), + .ack_o(wb_ack_o), + .adr_i(debug_addr[2:0]), + .dat_i(debug_data[31:0]), + .dat_o(), + .rx_int_o(), + .tx_int_o(), + .tx_o(debug_txd), + .rx_i(debug_rxd), + .baud_o() + ); + +endmodule // b200_core diff --git a/fpga/usrp3/top/b200/b200_io.v b/fpga/usrp3/top/b200/b200_io.v new file mode 100644 index 000000000..1c6ea2dc9 --- /dev/null +++ b/fpga/usrp3/top/b200/b200_io.v @@ -0,0 +1,554 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// +//------------------------------------------------------------------ +// +// In SISO mode, we output a clock thats 1x the frequency of the Catalina +// source-synchronous bus clock to be used as the radio_clk. +// In MIMO mode, we output a clock thats 1/2 the frequency of the Catalina +// source-synchronous bus clock to be used as the radio_clk. +// +//------------------------------------------------------------------ + +module b200_io + ( + input reset, + input mimo, + + // Baseband sample interface + output radio_clk, + output [11:0] rx_i0, + output [11:0] rx_q0, + output [11:0] rx_i1, + output [11:0] rx_q1, + input [11:0] tx_i0, + input [11:0] tx_q0, + input [11:0] tx_i1, + input [11:0] tx_q1, + + // Catalina interface + input rx_clk, + input rx_frame, + input [11:0] rx_data, + output tx_clk, + output tx_frame, + output [11:0] tx_data + ); + + + genvar z; + + //------------------------------------------------------------------ + // + // Synchronize MIMO signal from bus_clk to siso_clk. + // + //------------------------------------------------------------------ + reg mimo_sync, mimo_sync2; + + always @(posedge siso_clk) begin + mimo_sync <= mimo_sync2; + mimo_sync2 <= mimo; + end + + + //------------------------------------------------------------------ + // Clock Buffering. + // BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3. + // Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks. + //------------------------------------------------------------------ + wire rx_clk_buf; + wire mimo_clk_unbuf; + wire siso_clk_unbuf; + wire siso2_clk_unbuf; + + IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk)); + + //------------------------------------------------------------------ + // + // Buffers for LEFT TOP half bank pins + // BUFIO2_X0Y22 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(4), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("TRUE")) + clk_bufio_lt + ( + .IOCLK(io_clk_lt), + .DIVCLK(mimo_clk_unbuf), // Non-inverted source of 1/2x interface clock for radio_clk + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X0Y23 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lt_b + ( + .IOCLK(io_clk_lt_b), + .DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // + // Buffers for LEFT BOTTOM half bank pins + // BUFIO2_X1Y14 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb + ( + .IOCLK(io_clk_lb), + .DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X1Y15 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb_b + ( + .IOCLK(io_clk_lb_b), + .DIVCLK(), + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // Always-on SISO clk needed to load/unload DDR2 I/O Regs + //------------------------------------------------------------------ + BUFG siso_clk_bufg ( + .I(siso_clk_unbuf), + .O(siso_clk) + ); + + //------------------------------------------------------------------ + // 2-1 mux combined with BUFG to drive global radio_clk. + // Note: Not addressed setup/hold constraints of S input ...unsure if anything "bad" can happen here. + //------------------------------------------------------------------ + BUFGMUX #( + .CLK_SEL_TYPE("SYNC")) + radio_clk_bufg ( + .I0(siso_clk2_unbuf), + .I1(mimo_clk_unbuf), + .S(mimo_sync), + .O(radio_clk) + ); + + //------------------------------------------------------------------ + // RX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + wire rx_frame_0, rx_frame_1; + + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_frame ( + .Q0(rx_frame_1), + .Q1(rx_frame_0), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_frame), + .R(1'b0), + .S(1'b0)); + + reg rx_frame_d1, rx_frame_d2; + always @(posedge siso_clk) + if(~mimo_sync) + { rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 }; + else + { rx_frame_d2, rx_frame_d1 } <= { rx_frame_d1, rx_frame_1 }; + + //------------------------------------------------------------------ + // RX Data Bus - In bank3 both LT and LB + //------------------------------------------------------------------ + wire [11:0] rx_i,rx_q; + + // Bit0 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i0 ( + .Q0(rx_q[0]), + .Q1(rx_i[0]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[0]), + .R(1'b0), + .S(1'b0)); + + // Bit1 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i1 ( + .Q0(rx_q[1]), + .Q1(rx_i[1]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[1]), + .R(1'b0), + .S(1'b0)); + + // Bit2 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i2 ( + .Q0(rx_q[2]), + .Q1(rx_i[2]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[2]), + .R(1'b0), + .S(1'b0)); + + // Bit3 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i3 ( + .Q0(rx_q[3]), + .Q1(rx_i[3]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[3]), + .R(1'b0), + .S(1'b0)); + + // Bit4 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i4 ( + .Q0(rx_q[4]), + .Q1(rx_i[4]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[4]), + .R(1'b0), + .S(1'b0)); + + // Bit5 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i5 ( + .Q0(rx_q[5]), + .Q1(rx_i[5]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[5]), + .R(1'b0), + .S(1'b0)); + + // Bit6 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i6 ( + .Q0(rx_q[6]), + .Q1(rx_i[6]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[6]), + .R(1'b0), + .S(1'b0)); + + // Bit7 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i7 ( + .Q0(rx_q[7]), + .Q1(rx_i[7]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[7]), + .R(1'b0), + .S(1'b0)); + + // Bit8 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i8 ( + .Q0(rx_q[8]), + .Q1(rx_i[8]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[8]), + .R(1'b0), + .S(1'b0)); + + // Bit9 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i9 ( + .Q0(rx_q[9]), + .Q1(rx_i[9]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[9]), + .R(1'b0), + .S(1'b0)); + + // Bit10 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i10 ( + .Q0(rx_q[10]), + .Q1(rx_i[10]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[10]), + .R(1'b0), + .S(1'b0)); + + // Bit11 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i11 ( + .Q0(rx_q[11]), + .Q1(rx_i[11]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[11]), + .R(1'b0), + .S(1'b0)); + + //------------------------------------------------------------------ + // + // De-mux I & Q, Ch A & B onto fullrate clock. + // + // In all modes we grab data from the IDDR2 using negedge of siso_clk. + // IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase + // with siso_clk...siso_clk is always a little more delayed than io_clk. + // This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs + // with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register). + // + // In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's. + // + //------------------------------------------------------------------ + reg [11:0] rx_i_del, rx_q_del; + reg [11:0] rx_i0_siso_pos; + reg [11:0] rx_q0_siso_pos; + reg [11:0] rx_i1_siso_pos; + reg [11:0] rx_q1_siso_pos; + reg [11:0] rx_i0_siso_neg; + reg [11:0] rx_q0_siso_neg; + reg [11:0] rx_i1_siso_neg; + reg [11:0] rx_q1_siso_neg; + reg [11:0] rx_i0_siso; + reg [11:0] rx_q0_siso; + reg [11:0] rx_i1_siso; + reg [11:0] rx_q1_siso; + + + always @(negedge siso_clk) + if(mimo_sync) + // rx_frame_0 was sampled by same falling io_clk edge as rx_i[x] + // rx_frame_0 == 0 causes I & Q to be allocated to CH0 + if(rx_frame_0) begin + rx_i_del[11:0] <= rx_i[11:0]; + rx_q_del[11:0] <= rx_q[11:0]; + end + else begin + // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. + rx_i0_siso[11:0] <= rx_i[11:0]; + rx_q0_siso[11:0] <= rx_q[11:0]; + rx_i1_siso[11:0] <= rx_i_del[11:0]; + rx_q1_siso[11:0] <= rx_q_del[11:0]; + end + else begin + rx_i0_siso[11:0] <= rx_i[11:0]; + rx_q0_siso[11:0] <= rx_q[11:0]; + rx_i1_siso[11:0] <= rx_i[11:0]; + rx_q1_siso[11:0] <= rx_q[11:0]; + end // else: !if(rx_frame_0) + + //------------------------------------------------------------------ + // + // Now prepare data for crossing into radio_clk domain which can be for SISO mode (inverted) siso_clk or for MIMO mode siso_clk/2. + // In MIMO mode tx_strobe is used to maintain a known phase relationship betwwen siso_clk and radio_clk. + // (Note: Negedge or posedge is used conditionally so that we have massive margin against a fast-path race condition + // betwwen siso_clk and radio_clk). This kind of arrangement could still lead to confusion in timing analysis + // even if it works in the real world depending on how well the STA tool can do automatic case analysis. + // + //------------------------------------------------------------------ + // This code lock only relevent in MIMO mode. + always @(negedge siso_clk) + if (tx_strobe) + begin + rx_i0_siso_neg[11:0] <= rx_i0_siso[11:0]; + rx_q0_siso_neg[11:0] <= rx_q0_siso[11:0]; + rx_i1_siso_neg[11:0] <= rx_i1_siso[11:0]; + rx_q1_siso_neg[11:0] <= rx_q1_siso[11:0]; + end + // This code block only relevent in SISO mode. + always @(posedge siso_clk) + begin + rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0]; + rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0]; + rx_i1_siso_pos[11:0] <= rx_i1_siso[11:0]; + rx_q1_siso_pos[11:0] <= rx_q1_siso[11:0]; + end + + assign rx_i0 = (mimo_sync) ? rx_i0_siso_neg : rx_i0_siso_pos; + assign rx_q0 = (mimo_sync) ? rx_q0_siso_neg : rx_q0_siso_pos; + assign rx_i1 = (mimo_sync) ? rx_i1_siso_neg : rx_i1_siso_pos; + assign rx_q1 = (mimo_sync) ? rx_q1_siso_neg : rx_q1_siso_pos; + + + //------------------------------------------------------------------ + // TX Data Bus - In bank3 LB + //------------------------------------------------------------------ + reg [11:0] tx_i,tx_q; + reg tx_strobe_del; + + generate + for(z = 0; z < 12; z = z + 1) + begin : gen_pins + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2 ( + .Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0)); + end + endgenerate + + //------------------------------------------------------------------ + // TX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_frame ( + .Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(tx_strobe_del), .D1(mimo_sync & tx_strobe_del), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // TX Clock Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_clk ( + .Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // + // Mux I & Q, Ch A & B onto fullrate clockTX bus to AD9361 + // + //------------------------------------------------------------------ + wire tx_strobe; + reg [11:0] tx_i_del, tx_q_del; + + reg find_radio_clk_phase = 1'b0; + reg find_radio_clk_phase_del; + + + always @(posedge radio_clk) + find_radio_clk_phase <= ~find_radio_clk_phase; + + always @(negedge radio_clk) + find_radio_clk_phase_del <= find_radio_clk_phase; + + assign tx_strobe = mimo_sync ? (find_radio_clk_phase_del ^ find_radio_clk_phase) : 1'b1; + + always @(posedge siso_clk) + tx_strobe_del <= tx_strobe; + + // This strange piece of logic allows either USRP DUC to drive the AD9361 in SISO mode. + // This is principly used in the CODEC loopback test. + wire [11:0] tx_im = (mimo_sync || tx_i0 != 12'h0) ? tx_i0 : tx_i1; + wire [11:0] tx_qm = (mimo_sync || tx_q0 != 12'h0) ? tx_q0 : tx_q1; + + + // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. + // (Except on B200 based on AD9364 where only the true Ch A is stuffed) + always @(posedge siso_clk) + if(tx_strobe) + begin + {tx_i,tx_q} <= mimo_sync ? {tx_i1,tx_q1} : {tx_im,tx_qm}; + {tx_i_del,tx_q_del} <= {tx_i0,tx_q0}; + end + else + {tx_i,tx_q} <= {tx_i_del,tx_q_del}; + // + // Debug + // +/* -----\/----- EXCLUDED -----\/----- + wire [35:0] CONTROL0; + reg [11:0] tx_i_del_debug, tx_q_del_debug; + reg [11:0] tx_i_debug,tx_q_debug; + reg [11:0] tx_i0_debug,tx_q0_debug; + reg find_radio_clk_phase_debug; + reg find_radio_clk_phase_del_debug; + reg tx_strobe_debug; + reg tx_strobe_del_debug; + + + always @(posedge siso_clk) begin + tx_i_del_debug <= tx_i_del; + tx_q_del_debug <= tx_q_del; + tx_i_debug <= tx_i; + tx_q_debug <= tx_q; + tx_i0_debug <=tx_i0; + tx_q0_debug <= tx_q0; + find_radio_clk_phase_debug <= find_radio_clk_phase; + find_radio_clk_phase_del_debug <= find_radio_clk_phase_del; + tx_strobe_debug <= tx_strobe; + tx_strobe_del_debug <= tx_strobe_del; + end + + + + chipscope_icon chipscope_icon_i0 + ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] + ); + + chipscope_ila_128 chipscope_ila_i0 + ( + .CONTROL(CONTROL0), // INOUT BUS [35:0] + .CLK(siso_clk), // IN + .TRIG0( + { + tx_i_del_debug[11:0], + tx_q_del_debug[11:0], + tx_i_debug[11:0], + tx_q_debug[11:0], + tx_i0_debug[11:0], + tx_q0_debug[11:0], + find_radio_clk_phase_debug, + find_radio_clk_phase_del_debug, + tx_strobe_debug, + tx_strobe_del_debug + } + ) + + ); + -----/\----- EXCLUDED -----/\----- */ +endmodule diff --git a/fpga/usrp3/top/b200/check.sh b/fpga/usrp3/top/b200/check.sh new file mode 100644 index 000000000..5935de883 --- /dev/null +++ b/fpga/usrp3/top/b200/check.sh @@ -0,0 +1 @@ +iverilog ../top/b200/b200.v -y control/ -y timing/ -y fifo/ -y vita/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ -y ../top/b200/ -y ../top/b200/coregen/ -y gpif2/ -y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/XilinxCoreLib/ -Wall | grep -v timescale diff --git a/fpga/usrp3/top/b200/core_compile b/fpga/usrp3/top/b200/core_compile new file mode 100755 index 000000000..553e9c8ad --- /dev/null +++ b/fpga/usrp3/top/b200/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif2/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B200.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp3/top/b200/coregen/.gitignore b/fpga/usrp3/top/b200/coregen/.gitignore new file mode 100644 index 000000000..bdeac28ca --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/.gitignore @@ -0,0 +1,5 @@ +/tmp +/_xmsgs +/*.log +/*.gise +/*.xise diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy new file mode 100644 index 000000000..eb4747f81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc new file mode 100644 index 000000000..d43ee8b57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=<2.357?n1:k5=?6=3`j0;66a72;29?xdfn3:197>50z&:e?1>3A;3>6F>7e9'<6<6j?1/:k4<;h4:>5<>o1k3:17b6=:188ygg?290>6=4?{%;b>2?<@8297E?8d:&;7?7e>2.=j7<4i7;94?=n>h0;66g9b;29?l0d2900c5<50;9~fgc=83?1<7>t$8c93<=O9180D<9k;%:0>4d13-h0;66g9b;29?l0d2900c5<50;9~fgb=83?1<7>t$8c93<=O9180D<9k;%:0>4d13-h0;66g9b;29?l0d2900c5<50;9~fge=83?1<7>t$8c93<=O9180D<9k;%:0>4d13-h0;66g9b;29?l0d2900c5<50;9~fgd=83?1<7>t$8c93<=O9180D<9k;%:0>4d13-4i7;94?=n>h0;66g9b;29?l0d2900c5<50;9~fgg=83?1<7>t$8c93<=O9180D<9k;%:0>4d13->o1i3:17d8m:188m3e=831d4?4?::af<<72<0;6=u+9`84=>N60;1C=:j4$9195g0<,?l1h6g99;29?l0f2900e;l50;9j2f<722e3>7>5;|``3?6==3:1o0h7d86:188m3g=831b:o4?::k5g?6=3f296=44}ca5>5<2290;w)7n:6;8L4>53A;"1n3k0e;750;9j2d<722c=n7>5;h4`>5<0<729q/5l489:J2<7=O9>n0(5=51c48 3`=02c=57>5;h4b>5<>i?:3:17pll3;291?6=8r.2m796;I3;6>N6?m1/4>4>b79'2c<03`<26=44i7c94?=n>k0;66g9c;29?j>52900qom=:186>5<7s-3j6:74H0:1?M70l2.3?7?m6:&5b?0>o1j3:17d8l:188k=4=831vnn?50;794?6|,0k1;45G1908L41c3-2860=n>00;66g9a;29?l0e2900e;m50;9l<7<722wio=4?:483>5}#1h0<56F>839K52b<,191=o84$7d90>o113:17d8n:188m3d=831b:n4?::m;6?6=3thij7>55;294~">i3=27E?72:J23a=#0:0:n;5+6g80?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<30D<6=;I34`>"?;3;i:6*9f;08m3?=831b:l4?::k5f?6=3`428h=7)8i:0;8 =?=9h80e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90:0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90;0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9080e;750;9j2d<722c=n7>5;h4`>5<1<7;50;2x 428h=7)8i:0;8 =?=9090e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90>0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90?0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=90=0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9020e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9030e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=9h90e;750;9j2d<722c=n7>5;h4`>5<1<7;50;2x 428h=7)8i:0;8 =?=9h>0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=91i0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=91n0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=91o0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:0;8 =?=91l0e;750;9j2d<722c=n7>5;h4`>5<428h=7)8i:008 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v new file mode 100644 index 000000000..30b31cca5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.v +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo new file mode 100644 index 000000000..6c82410b6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_icon.veo +// /___/ /\ Timestamp : Tue Feb 19 14:28:40 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco new file mode 100644 index 000000000..2b7395488 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Tue Feb 19 22:27:58 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=b200_chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 729764e8 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt new file mode 100644 index 000000000..97a36c09d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_flist.txt @@ -0,0 +1,15 @@ +# Output products list for +b200_chipscope_icon.asy +b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +b200_chipscope_icon.gise +b200_chipscope_icon.ngc +b200_chipscope_icon.ucf +b200_chipscope_icon.v +b200_chipscope_icon.veo +b200_chipscope_icon.xco +b200_chipscope_icon.xdc +b200_chipscope_icon.xise +b200_chipscope_icon_flist.txt +b200_chipscope_icon_readme.txt +b200_chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt new file mode 100644 index 000000000..c3b896f44 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'b200_chipscope_icon' in directory +/home/bhilburn/xilinx/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_icon.constraints/b200_chipscope_icon.ucf + * b200_chipscope_icon.constraints/b200_chipscope_icon.xdc + * b200_chipscope_icon.ngc + * b200_chipscope_icon.ucf + * b200_chipscope_icon.v + * b200_chipscope_icon.veo + * b200_chipscope_icon.xdc + * b200_chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * b200_chipscope_icon.gise + * b200_chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..c9d1c0b14 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is _xmdf +package provide b200_chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_icon +} +# ::b200_chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.constraints/b200_chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy new file mode 100644 index 000000000..fcca7f4e0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_chipscope_ila +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName data[63:0] +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[7:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc new file mode 100644 index 000000000..985834f8d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.cdc @@ -0,0 +1,83 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Feb 19 16:52:47 PST 2013 +SignalExport.clockChannel=CLK +SignalExport.dataChannel<0000>=DATA[0] +SignalExport.dataChannel<0001>=DATA[1] +SignalExport.dataChannel<0002>=DATA[2] +SignalExport.dataChannel<0003>=DATA[3] +SignalExport.dataChannel<0004>=DATA[4] +SignalExport.dataChannel<0005>=DATA[5] +SignalExport.dataChannel<0006>=DATA[6] +SignalExport.dataChannel<0007>=DATA[7] +SignalExport.dataChannel<0008>=DATA[8] +SignalExport.dataChannel<0009>=DATA[9] +SignalExport.dataChannel<0010>=DATA[10] +SignalExport.dataChannel<0011>=DATA[11] +SignalExport.dataChannel<0012>=DATA[12] +SignalExport.dataChannel<0013>=DATA[13] +SignalExport.dataChannel<0014>=DATA[14] +SignalExport.dataChannel<0015>=DATA[15] +SignalExport.dataChannel<0016>=DATA[16] +SignalExport.dataChannel<0017>=DATA[17] +SignalExport.dataChannel<0018>=DATA[18] +SignalExport.dataChannel<0019>=DATA[19] +SignalExport.dataChannel<0020>=DATA[20] +SignalExport.dataChannel<0021>=DATA[21] +SignalExport.dataChannel<0022>=DATA[22] +SignalExport.dataChannel<0023>=DATA[23] +SignalExport.dataChannel<0024>=DATA[24] +SignalExport.dataChannel<0025>=DATA[25] +SignalExport.dataChannel<0026>=DATA[26] +SignalExport.dataChannel<0027>=DATA[27] +SignalExport.dataChannel<0028>=DATA[28] +SignalExport.dataChannel<0029>=DATA[29] +SignalExport.dataChannel<0030>=DATA[30] +SignalExport.dataChannel<0031>=DATA[31] +SignalExport.dataChannel<0032>=DATA[32] +SignalExport.dataChannel<0033>=DATA[33] +SignalExport.dataChannel<0034>=DATA[34] +SignalExport.dataChannel<0035>=DATA[35] +SignalExport.dataChannel<0036>=DATA[36] +SignalExport.dataChannel<0037>=DATA[37] +SignalExport.dataChannel<0038>=DATA[38] +SignalExport.dataChannel<0039>=DATA[39] +SignalExport.dataChannel<0040>=DATA[40] +SignalExport.dataChannel<0041>=DATA[41] +SignalExport.dataChannel<0042>=DATA[42] +SignalExport.dataChannel<0043>=DATA[43] +SignalExport.dataChannel<0044>=DATA[44] +SignalExport.dataChannel<0045>=DATA[45] +SignalExport.dataChannel<0046>=DATA[46] +SignalExport.dataChannel<0047>=DATA[47] +SignalExport.dataChannel<0048>=DATA[48] +SignalExport.dataChannel<0049>=DATA[49] +SignalExport.dataChannel<0050>=DATA[50] +SignalExport.dataChannel<0051>=DATA[51] +SignalExport.dataChannel<0052>=DATA[52] +SignalExport.dataChannel<0053>=DATA[53] +SignalExport.dataChannel<0054>=DATA[54] +SignalExport.dataChannel<0055>=DATA[55] +SignalExport.dataChannel<0056>=DATA[56] +SignalExport.dataChannel<0057>=DATA[57] +SignalExport.dataChannel<0058>=DATA[58] +SignalExport.dataChannel<0059>=DATA[59] +SignalExport.dataChannel<0060>=DATA[60] +SignalExport.dataChannel<0061>=DATA[61] +SignalExport.dataChannel<0062>=DATA[62] +SignalExport.dataChannel<0063>=DATA[63] +SignalExport.dataEqualsTrigger=false +SignalExport.dataPortWidth=64 +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=false +SignalExport.triggerPortWidth<0000>=8 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.constraints/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc new file mode 100644 index 000000000..82baab030 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf new file mode 100644 index 000000000..e1ce12a9d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.ucf @@ -0,0 +1,17 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_b200_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_b200_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; +NET "DATA<*" S; +NET "DATA<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v new file mode 100644 index 000000000..a9abb90e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.v @@ -0,0 +1,33 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.v +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module b200_chipscope_ila( + CONTROL, + CLK, + DATA, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [63 : 0] DATA; +input [7 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo new file mode 100644 index 000000000..f72d6853c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.veo @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : b200_chipscope_ila.veo +// /___/ /\ Timestamp : Tue Feb 19 16:52:47 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +b200_chipscope_ila YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .DATA(DATA), // IN BUS [63:0] + .TRIG0(TRIG0) // IN BUS [7:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco new file mode 100644 index 000000000..ecae96127 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Feb 20 00:50:54 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=b200_chipscope_ila +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=64 +CSET data_same_as_trigger=false +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=true +CSET exclude_from_data_storage_10=true +CSET exclude_from_data_storage_11=true +CSET exclude_from_data_storage_12=true +CSET exclude_from_data_storage_13=true +CSET exclude_from_data_storage_14=true +CSET exclude_from_data_storage_15=true +CSET exclude_from_data_storage_16=true +CSET exclude_from_data_storage_2=true +CSET exclude_from_data_storage_3=true +CSET exclude_from_data_storage_4=true +CSET exclude_from_data_storage_5=true +CSET exclude_from_data_storage_6=true +CSET exclude_from_data_storage_7=true +CSET exclude_from_data_storage_8=true +CSET exclude_from_data_storage_9=true +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=8192 +CSET sample_on=Rising +CSET trigger_port_width_1=8 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: 92d75d38 diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt new file mode 100644 index 000000000..4dfd1b082 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +b200_chipscope_ila.asy +b200_chipscope_ila.cdc +b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +b200_chipscope_ila.gise +b200_chipscope_ila.ncf +b200_chipscope_ila.ngc +b200_chipscope_ila.ucf +b200_chipscope_ila.v +b200_chipscope_ila.veo +b200_chipscope_ila.xco +b200_chipscope_ila.xdc +b200_chipscope_ila.xise +b200_chipscope_ila_flist.txt +b200_chipscope_ila_readme.txt +b200_chipscope_ila_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt new file mode 100644 index 000000000..28176abfb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'b200_chipscope_ila' in directory +/home/bhilburn/code/ettus/b200_dev/fpgapriv.git/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * b200_chipscope_ila.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * b200_chipscope_ila.cdc + * b200_chipscope_ila.constraints/b200_chipscope_ila.ucf + * b200_chipscope_ila.constraints/b200_chipscope_ila.xdc + * b200_chipscope_ila.ncf + * b200_chipscope_ila.ngc + * b200_chipscope_ila.ucf + * b200_chipscope_ila.v + * b200_chipscope_ila.veo + * b200_chipscope_ila.xdc + * b200_chipscope_ila_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * b200_chipscope_ila.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * b200_chipscope_ila.gise + * b200_chipscope_ila.xise + +Deliver Readme: + Readme file for the IP. + + * b200_chipscope_ila_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * b200_chipscope_ila_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl new file mode 100755 index 000000000..a0922f3ec --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_chipscope_ila_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide b200_chipscope_ila_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_chipscope_ila_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_chipscope_ila_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_chipscope_ila +} +# ::b200_chipscope_ila_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_chipscope_ila_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.constraints/b200_chipscope_ila.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_chipscope_ila_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_chipscope_ila +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy new file mode 100644 index 000000000..aad58f8d2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b200_clk_gen +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk_in1_p +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName clk_in1_n +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf new file mode 100755 index 000000000..e3776c72b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.ucf @@ -0,0 +1,72 @@ +# file: b200_clk_gen.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v new file mode 100755 index 000000000..bb9a57dc2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.v @@ -0,0 +1,163 @@ +// file: b200_clk_gen.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module b200_clk_gen + (// Clock in ports + input CLK_IN1_40_P, + input CLK_IN1_40_N, + // Clock out ports + output CLK_OUT1_40_int, + output CLK_OUT2_100_gpif, + output CLK_OUT3_100_bus, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFGDS clkin1_buf + (.O (clkin1), + .I (CLK_IN1_40_P), + .IB (CLK_IN1_40_N)); + + + // Clocking primitive + //------------------------------------ + + // Instantiation of the DCM primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire psdone_unused; + wire locked_int; + wire [7:0] status_int; + wire clkfb; + wire clk0; + wire clkfx; + + DCM_SP + #(.CLKDV_DIVIDE (2.000), + .CLKFX_DIVIDE (2), + .CLKFX_MULTIPLY (5), + .CLKIN_DIVIDE_BY_2 ("FALSE"), + .CLKIN_PERIOD (25.0), + .CLKOUT_PHASE_SHIFT ("NONE"), + .CLK_FEEDBACK ("1X"), + .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"), + .PHASE_SHIFT (0), + .STARTUP_WAIT ("FALSE")) + dcm_sp_inst + // Input clock + (.CLKIN (clkin1), + .CLKFB (clkfb), + // Output clocks + .CLK0 (clk0), + .CLK90 (), + .CLK180 (), + .CLK270 (), + .CLK2X (), + .CLK2X180 (), + .CLKFX (clkfx), + .CLKFX180 (), + .CLKDV (), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_int), + .STATUS (status_int), + + .RST (RESET), + // Unused pin- tie low + .DSSEN (1'b0)); + + assign LOCKED = locked_int; + + // Output buffering + //----------------------------------- + assign clkfb = CLK_OUT1_40_int; + + BUFG clkout1_buf + (.O (CLK_OUT1_40_int), + .I (clk0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2_100_gpif), + .I (clkfx)); + + BUFG clkout3_buf + (.O (CLK_OUT3_100_bus), + .I (clkfx)); + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo new file mode 100755 index 000000000..111c02991 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.veo @@ -0,0 +1,83 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______200.000____150.000 +// CLK_OUT2___100.000______0.000______50.0______400.000____150.000 +// CLK_OUT3___100.000______0.000______50.0______400.000____150.000 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + b200_clk_gen instance_name + (// Clock in ports + .CLK_IN1_40_P(CLK_IN1_40_P), // IN + .CLK_IN1_40_N(CLK_IN1_40_N), // IN + // Clock out ports + .CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT + .CLK_OUT2_100_gpif(CLK_OUT2_100_gpif), // OUT + .CLK_OUT3_100_bus(CLK_OUT3_100_bus), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco new file mode 100644 index 000000000..96c8193b3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 20:00:48 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1_40_int +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2_100_gpif +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3_100_bus +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4 +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=250.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=40.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=b200_clk_gen +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLK0 +CSET dcm_clk_out2_port=CLKFX +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=25.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=4 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=10.000 +CSET pll_clkout0_divide=1 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=1 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=1 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=40.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Differential_clock_capable_pin +CSET primary_port=CLK_IN1_40 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: af7323ea diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc new file mode 100755 index 000000000..d57c7eec7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen.xdc @@ -0,0 +1,68 @@ +# file: b200_clk_gen.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..19c5b73c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,181 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: July 25, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 000000000..7176ddb81 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,192 @@ + + +clk_wiz_v3_6_vinfo + + + +

+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: July 25, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf new file mode 100644 index 000000000..a7daa6089 Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/b200_clk_gen/doc/pg065_clk_wiz.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf new file mode 100755 index 000000000..62c243978 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.ucf @@ -0,0 +1,73 @@ +# file: b200_clk_gen_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +NET "CLK_IN1_P" TNM_NET = "CLK_IN1_P"; +TIMESPEC "TS_CLK_IN1_P" = PERIOD "CLK_IN1_P" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- +# NET "clk_int[1]" TNM_NET = "CLK_OUT1"; +# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 40.000 MHz; + +# NET "clk_int[2]" TNM_NET = "CLK_OUT2"; +# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 100.000 MHz; +# NET "clk_int[3]" TNM_NET = "CLK_OUT3"; +# TIMESPEC "TS_CLK_OUT3" = PERIOD "CLK_OUT3" 100.000 MHz; + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v new file mode 100755 index 000000000..e22b83072 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.v @@ -0,0 +1,180 @@ +// file: b200_clk_gen_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module b200_clk_gen_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1_P, + input CLK_IN1_N, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [3:1] CLK_OUT, + // High bits of counters driven by clocks + output [3:1] COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Number of counters + localparam NUM_C = 3; + genvar count_gen; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + b200_clk_gen clknetwork + (// Clock in ports + .CLK_IN1_40_P (CLK_IN1_P), + .CLK_IN1_40_N (CLK_IN1_N), + // Clock out ports + .CLK_OUT1_40_int (clk_int[1]), + .CLK_OUT2_100_gpif (clk_int[2]), + .CLK_OUT3_100_bus (clk_int[3]), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins1]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + assign clk[3] = clk_int[3]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc new file mode 100755 index 000000000..dc0aad84c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/example_design/b200_clk_gen_exdes.xdc @@ -0,0 +1,70 @@ +# file: b200_clk_gen_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +# Differential clock only needs one constraint +create_clock -name CLK_IN1_P -period 25.0 [get_ports CLK_IN1_P] +set_propagated_clock CLK_IN1_P +set_input_jitter CLK_IN1_P 0.25 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat new file mode 100755 index 000000000..32e315065 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move b200_clk_gen_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\b200_clk_gen_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing -pr b b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v +cd .. + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh new file mode 100755 index 000000000..d33e6c5f5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv b200_clk_gen_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/b200_clk_gen_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b200_clk_gen_exdes.ucf b200_clk_gen_exdes + +echo 'Running map' +map -timing b200_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b200_clk_gen_exdes -w routed.ncd routed.v + +cd .. diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat new file mode 100755 index 000000000..8ac771810 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh new file mode 100755 index 000000000..6c8c837d3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl new file mode 100755 index 000000000..b87b6e4d5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName b200_clk_gen +set topName b200_clk_gen_exdes +set device xc6slx75csg484-2 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b200_clk_gen.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b200_clk_gen_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat new file mode 100755 index 000000000..42273f5d4 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh new file mode 100755 index 000000000..f4c14729e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl new file mode 100755 index 000000000..5449fa5fb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx75csg484-2 +set projName b200_clk_gen +set design b200_clk_gen +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module b200_clk_gen_exdes +set_property top b200_clk_gen_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../b200_clk_gen.v} +add_files -norecurse {../../example_design/b200_clk_gen_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b200_clk_gen_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module b200_clk_gen_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b200_clk_gen_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj new file mode 100755 index 000000000..51a950151 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../b200_clk_gen.v +verilog work ../example_design/b200_clk_gen_exdes.v diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr new file mode 100755 index 000000000..ae0a09163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top b200_clk_gen_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-ofn b200_clk_gen_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v new file mode 100755 index 000000000..f7dba4105 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/b200_clk_gen_tb.v @@ -0,0 +1,146 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl new file mode 100755 index 000000000..f22f9e447 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..227a07e0c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\b200_clk_gen.v +vlogcomp -work work ..\..\example_design\b200_clk_gen_exdes.v +vlogcomp -work work ..\b200_clk_gen_tb.v + +REM compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +REM run the simulation script +.\b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..db1b8cc4b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../b200_clk_gen.v +vlogcomp -work work ../../example_design/b200_clk_gen_exdes.v +vlogcomp -work work ../b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L unisims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..86e433ecb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\b200_clk_gen.v +vlog -work work ..\..\example_design\b200_clk_gen_exdes.v +vlog -work work ..\b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..fbb4124b9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.b200_clk_gen_tb work.glbl +do wave.do +log b200_clk_gen_tb/dut/counter +log -r /* +run 50000ns diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..1d9455134 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../b200_clk_gen.v +vlog -work work ../../example_design/b200_clk_gen_exdes.v +vlog -work work ../b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..eeb5b9712 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../b200_clk_gen.v +ncvlog -work work ../../example_design/b200_clk_gen_exdes.v +ncvlog -work work ../b200_clk_gen_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.b200_clk_gen_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b200_clk_gen_tb diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..66b2cfb09 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../b200_clk_gen.v \ + ../../example_design/b200_clk_gen_exdes.v \ + ../b200_clk_gen_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug b200_clk_gen_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..d35a8a813 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(b200_clk_gen_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b751d0624 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave +gui_sg_create b200_clk_gen_group +gui_list_add_group -id Wave.1 {b200_clk_gen_group} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.test_phase} +gui_set_radix -radix {ascii} -signals {b200_clk_gen_tb.test_phase} +gui_sg_addsignal -group b200_clk_gen_group {{Input_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.CLK_IN1} +gui_sg_addsignal -group b200_clk_gen_group {{Output_clocks}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.clk} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.clk +gui_sg_addsignal -group b200_clk_gen_group {{Status_control}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.RESET} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.LOCKED} +gui_sg_addsignal -group b200_clk_gen_group {{Counters}} -divider +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.COUNT} +gui_sg_addsignal -group b200_clk_gen_group {b200_clk_gen_tb.dut.counter} +gui_list_expand -id Wave.1 b200_clk_gen_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do new file mode 100755 index 000000000..f05bb5c2e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /b200_clk_gen_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /b200_clk_gen_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /b200_clk_gen_tb/RESET +add wave -noupdate -format Logic /b200_clk_gen_tb/LOCKED +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /b200_clk_gen_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /b200_clk_gen_tb/dut/counter diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv new file mode 100755 index 000000000..4bce3bcba --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/wave.sv @@ -0,0 +1,119 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::b200_clk_gen_tb +browser yview see nc::b200_clk_gen_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.clk[1]} \ + {b200_clk_gen_tb.dut.clk[2]} \ {b200_clk_gen_tb.dut.clk[3]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b200_clk_gen_tb.dut.counter[1]} \ + {b200_clk_gen_tb.dut.counter[2]} \ {b200_clk_gen_tb.dut.counter[3]} +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::b200_clk_gen_tb.RESET} {nc::b200_clk_gen_tb.LOCKED} + + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::b200_clk_gen_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v new file mode 100755 index 000000000..4d0d01cb0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/b200_clk_gen_tb.v @@ -0,0 +1,160 @@ +// file: b200_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b200_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + wire CLK_IN1_P = CLK_IN1; + wire CLK_IN1_N = ~CLK_IN1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b200_clk_gen_exdes + dut + (// Clock in ports + .CLK_IN1_P (CLK_IN1_P), + .CLK_IN1_N (CLK_IN1_N), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file new file mode 100755 index 000000000..0e8696ce6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = b200_clk_gen_tb.dut; diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl new file mode 100755 index 000000000..00e00dd03 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b200_clk_gen_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..edf149164 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work b200_clk_gen_tb.v + +# compile the project +fuse work.b200_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b200_clk_gen_isim.exe + +# run the simulation script +./b200_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b200_clk_gen_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./b200_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..b759f9529 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work b200_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..cfe22dc41 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..497db4bbd --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b200_clk_gen_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b200_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b200_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..8dd610f57 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work b200_clk_gen_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b200_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b200_clk_gen_tb + diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..3566700b2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + b200_clk_gen_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:b200_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug b200_clk_gen_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..0548d1733 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..1438f6bed --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do new file mode 100755 index 000000000..048ce6aa6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/wave.do @@ -0,0 +1,72 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /b200_clk_gen_tb/CLK_IN1 +add wave -noupdate /b200_clk_gen_tb/COUNT +add wave -noupdate /b200_clk_gen_tb/LOCKED +add wave -noupdate /b200_clk_gen_tb/RESET +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt new file mode 100644 index 000000000..044c06a12 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_flist.txt @@ -0,0 +1,53 @@ +# Output products list for +b200_clk_gen/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_readme.txt +b200_clk_gen/doc/clk_wiz_v3_6_vinfo.html +b200_clk_gen/doc/pg065_clk_wiz.pdf +b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +b200_clk_gen/example_design/b200_clk_gen_exdes.v +b200_clk_gen/example_design/b200_clk_gen_exdes.xdc +b200_clk_gen/implement/implement.bat +b200_clk_gen/implement/implement.sh +b200_clk_gen/implement/planAhead_ise.bat +b200_clk_gen/implement/planAhead_ise.sh +b200_clk_gen/implement/planAhead_ise.tcl +b200_clk_gen/implement/planAhead_rdn.bat +b200_clk_gen/implement/planAhead_rdn.sh +b200_clk_gen/implement/planAhead_rdn.tcl +b200_clk_gen/implement/xst.prj +b200_clk_gen/implement/xst.scr +b200_clk_gen/simulation/b200_clk_gen_tb.v +b200_clk_gen/simulation/functional/simcmds.tcl +b200_clk_gen/simulation/functional/simulate_isim.bat +b200_clk_gen/simulation/functional/simulate_isim.sh +b200_clk_gen/simulation/functional/simulate_mti.bat +b200_clk_gen/simulation/functional/simulate_mti.do +b200_clk_gen/simulation/functional/simulate_mti.sh +b200_clk_gen/simulation/functional/simulate_ncsim.sh +b200_clk_gen/simulation/functional/simulate_vcs.sh +b200_clk_gen/simulation/functional/ucli_commands.key +b200_clk_gen/simulation/functional/vcs_session.tcl +b200_clk_gen/simulation/functional/wave.do +b200_clk_gen/simulation/functional/wave.sv +b200_clk_gen/simulation/timing/b200_clk_gen_tb.v +b200_clk_gen/simulation/timing/sdf_cmd_file +b200_clk_gen/simulation/timing/simcmds.tcl +b200_clk_gen/simulation/timing/simulate_isim.sh +b200_clk_gen/simulation/timing/simulate_mti.bat +b200_clk_gen/simulation/timing/simulate_mti.do +b200_clk_gen/simulation/timing/simulate_mti.sh +b200_clk_gen/simulation/timing/simulate_ncsim.sh +b200_clk_gen/simulation/timing/simulate_vcs.sh +b200_clk_gen/simulation/timing/ucli_commands.key +b200_clk_gen/simulation/timing/vcs_session.tcl +b200_clk_gen/simulation/timing/wave.do +b200_clk_gen.asy +b200_clk_gen.gise +b200_clk_gen.ucf +b200_clk_gen.v +b200_clk_gen.veo +b200_clk_gen.xco +b200_clk_gen.xdc +b200_clk_gen.xise +b200_clk_gen_flist.txt +b200_clk_gen_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl new file mode 100755 index 000000000..58f510c56 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/b200_clk_gen_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is _xmdf +package provide b200_clk_gen_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b200_clk_gen_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b200_clk_gen_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b200_clk_gen +} +# ::b200_clk_gen_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b200_clk_gen_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/example_design/b200_clk_gen_exdes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/b200_clk_gen_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b200_clk_gen_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b200_clk_gen +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.asy b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy new file mode 100644 index 000000000..a0153d32c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc new file mode 100644 index 000000000..db921aaf5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=l2.357?6d:k5=?6=3`j0;66a72;29?xde?3:197>50z&:e?1>3A;3>6F>7e9'<6<6j<1/:k4l;%::>4?b3`<26=44i7c94?=n>k0;66g9c;29?j>52900qol9:186>5<7s-3j6:74H0:1?M70l2.3?7?m5:&5b?g<,131=4k4i7;94?=n>h0;66g9b;29?l0d2900c5<50;9~fg3=83?1<7>t$8c93<=O9180D<9k;%:0>4d23-00;66g9a;29?l0e2900e;m50;9l<7<722win94?:483>5}#1h0<56F>839K52b<,191=o;4$7d9<>"?13;2j6g99;29?l0f2900e;l50;9j2f<722e3>7>5;|`a7?6==3:1o0<7)66:0c3?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<30D<6=;I34`>"?;3;i96*9f;48 =?=9h:0e;750;9j2d<722c=n7>5;h4`>5<a09j2<<722c=m7>5;h4a>5<>{ej90;684?:1y'=d<012B:4?5G16f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.v b/fpga/usrp3/top/b200/coregen/chipscope_icon.v new file mode 100644 index 000000000..fe9223442 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.v +// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.veo b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo new file mode 100644 index 000000000..cf73c9226 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.veo +// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xco b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco new file mode 100644 index 000000000..3d4beaaa0 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Oct 23 00:04:31 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:25Z +# END Extra information +GENERATE +# CRC: 5ccf4baf diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt new file mode 100644 index 000000000..435dc80e2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_flist.txt @@ -0,0 +1,16 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_icon.asy +chipscope_icon.constraints/chipscope_icon.ucf +chipscope_icon.constraints/chipscope_icon.xdc +chipscope_icon.gise +chipscope_icon.ngc +chipscope_icon.ucf +chipscope_icon.v +chipscope_icon.veo +chipscope_icon.xco +chipscope_icon.xdc +chipscope_icon.xise +chipscope_icon_flist.txt +chipscope_icon_readme.txt +chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt new file mode 100644 index 000000000..88118d782 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_readme.txt @@ -0,0 +1,46 @@ +The following files were generated for 'chipscope_icon' in directory +/home/ianb/fpgadev/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_icon.constraints/chipscope_icon.ucf + * chipscope_icon.constraints/chipscope_icon.xdc + * chipscope_icon.ngc + * chipscope_icon.ucf + * chipscope_icon.v + * chipscope_icon.veo + * chipscope_icon.xdc + * chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_icon.gise + * chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..241f4d5ae --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is _xmdf +package provide chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon +} +# ::chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy new file mode 100644 index 000000000..5342fbe4f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_128 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[127:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc new file mode 100644 index 000000000..9b29ca86f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.cdc @@ -0,0 +1,144 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Oct 22 15:45:46 PDT 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] 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+SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] +SignalExport.triggerChannel<0000><0126>=TRIG0[126] +SignalExport.triggerChannel<0000><0127>=TRIG0[127] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=128 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf new file mode 100644 index 000000000..736db76a7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_128 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_128 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.constraints/chipscope_ila_128.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc new file mode 100644 index 000000000..278d4f046 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+_xmsgs/pn_parser.xmsgs +chipscope_ila_128.asy +chipscope_ila_128.cdc +chipscope_ila_128.constraints/chipscope_ila_128.ucf +chipscope_ila_128.constraints/chipscope_ila_128.xdc +chipscope_ila_128.gise +chipscope_ila_128.ncf +chipscope_ila_128.ngc +chipscope_ila_128.ucf +chipscope_ila_128.v +chipscope_ila_128.veo +chipscope_ila_128.xco +chipscope_ila_128.xdc +chipscope_ila_128.xise +chipscope_ila_128_flist.txt +chipscope_ila_128_readme.txt +chipscope_ila_128_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt new file mode 100644 index 000000000..fbcd6cbfb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_128' in directory +/home/ianb/fpgadev/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_128.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_128.cdc + * chipscope_ila_128.constraints/chipscope_ila_128.ucf + * chipscope_ila_128.constraints/chipscope_ila_128.xdc + * chipscope_ila_128.ncf + * chipscope_ila_128.ngc + * chipscope_ila_128.ucf + * chipscope_ila_128.v + * chipscope_ila_128.veo + * chipscope_ila_128.xdc + * chipscope_ila_128_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_128.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_128.gise + * chipscope_ila_128.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_128_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_128_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl new file mode 100755 index 000000000..e4af2b327 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_128_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_128_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_128_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_128_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_128 +} +# ::chipscope_ila_128_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_128_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.constraints/chipscope_ila_128.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_128_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_128 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy new file mode 100644 index 000000000..3eef48558 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_256 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[255:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc new file mode 100644 index 000000000..562f53ff9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.cdc @@ -0,0 +1,272 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 16:13:02 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] 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+SignalExport.triggerChannel<0000><0050>=TRIG0[50] +SignalExport.triggerChannel<0000><0051>=TRIG0[51] +SignalExport.triggerChannel<0000><0052>=TRIG0[52] +SignalExport.triggerChannel<0000><0053>=TRIG0[53] +SignalExport.triggerChannel<0000><0054>=TRIG0[54] +SignalExport.triggerChannel<0000><0055>=TRIG0[55] +SignalExport.triggerChannel<0000><0056>=TRIG0[56] +SignalExport.triggerChannel<0000><0057>=TRIG0[57] +SignalExport.triggerChannel<0000><0058>=TRIG0[58] +SignalExport.triggerChannel<0000><0059>=TRIG0[59] +SignalExport.triggerChannel<0000><0060>=TRIG0[60] +SignalExport.triggerChannel<0000><0061>=TRIG0[61] +SignalExport.triggerChannel<0000><0062>=TRIG0[62] +SignalExport.triggerChannel<0000><0063>=TRIG0[63] +SignalExport.triggerChannel<0000><0064>=TRIG0[64] +SignalExport.triggerChannel<0000><0065>=TRIG0[65] +SignalExport.triggerChannel<0000><0066>=TRIG0[66] +SignalExport.triggerChannel<0000><0067>=TRIG0[67] +SignalExport.triggerChannel<0000><0068>=TRIG0[68] +SignalExport.triggerChannel<0000><0069>=TRIG0[69] +SignalExport.triggerChannel<0000><0070>=TRIG0[70] +SignalExport.triggerChannel<0000><0071>=TRIG0[71] +SignalExport.triggerChannel<0000><0072>=TRIG0[72] +SignalExport.triggerChannel<0000><0073>=TRIG0[73] +SignalExport.triggerChannel<0000><0074>=TRIG0[74] +SignalExport.triggerChannel<0000><0075>=TRIG0[75] +SignalExport.triggerChannel<0000><0076>=TRIG0[76] +SignalExport.triggerChannel<0000><0077>=TRIG0[77] +SignalExport.triggerChannel<0000><0078>=TRIG0[78] +SignalExport.triggerChannel<0000><0079>=TRIG0[79] +SignalExport.triggerChannel<0000><0080>=TRIG0[80] +SignalExport.triggerChannel<0000><0081>=TRIG0[81] +SignalExport.triggerChannel<0000><0082>=TRIG0[82] +SignalExport.triggerChannel<0000><0083>=TRIG0[83] +SignalExport.triggerChannel<0000><0084>=TRIG0[84] +SignalExport.triggerChannel<0000><0085>=TRIG0[85] +SignalExport.triggerChannel<0000><0086>=TRIG0[86] +SignalExport.triggerChannel<0000><0087>=TRIG0[87] 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+SignalExport.triggerChannel<0000><0107>=TRIG0[107] +SignalExport.triggerChannel<0000><0108>=TRIG0[108] +SignalExport.triggerChannel<0000><0109>=TRIG0[109] +SignalExport.triggerChannel<0000><0110>=TRIG0[110] +SignalExport.triggerChannel<0000><0111>=TRIG0[111] +SignalExport.triggerChannel<0000><0112>=TRIG0[112] +SignalExport.triggerChannel<0000><0113>=TRIG0[113] +SignalExport.triggerChannel<0000><0114>=TRIG0[114] +SignalExport.triggerChannel<0000><0115>=TRIG0[115] +SignalExport.triggerChannel<0000><0116>=TRIG0[116] +SignalExport.triggerChannel<0000><0117>=TRIG0[117] +SignalExport.triggerChannel<0000><0118>=TRIG0[118] +SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] 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+SignalExport.triggerChannel<0000><0240>=TRIG0[240] +SignalExport.triggerChannel<0000><0241>=TRIG0[241] +SignalExport.triggerChannel<0000><0242>=TRIG0[242] +SignalExport.triggerChannel<0000><0243>=TRIG0[243] +SignalExport.triggerChannel<0000><0244>=TRIG0[244] +SignalExport.triggerChannel<0000><0245>=TRIG0[245] +SignalExport.triggerChannel<0000><0246>=TRIG0[246] +SignalExport.triggerChannel<0000><0247>=TRIG0[247] +SignalExport.triggerChannel<0000><0248>=TRIG0[248] +SignalExport.triggerChannel<0000><0249>=TRIG0[249] +SignalExport.triggerChannel<0000><0250>=TRIG0[250] +SignalExport.triggerChannel<0000><0251>=TRIG0[251] +SignalExport.triggerChannel<0000><0252>=TRIG0[252] +SignalExport.triggerChannel<0000><0253>=TRIG0[253] +SignalExport.triggerChannel<0000><0254>=TRIG0[254] +SignalExport.triggerChannel<0000><0255>=TRIG0[255] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=256 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.constraints/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc new file mode 100644 index 000000000..e6dfef4e8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf new file mode 100644 index 000000000..b458eed9c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_256 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_256 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v new file mode 100644 index 000000000..2f0ec9349 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.v +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_256( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [255 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo new file mode 100644 index 000000000..201512ffb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_256.veo +// /___/ /\ Timestamp : Fri Mar 08 16:13:02 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_256 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [255:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco new file mode 100644 index 000000000..4272296fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Sat Mar 9 00:11:24 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_256 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=256 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: b8a8f4bd diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt new file mode 100644 index 000000000..da4f99bbe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_ila_256.asy +chipscope_ila_256.cdc +chipscope_ila_256.constraints/chipscope_ila_256.ucf +chipscope_ila_256.constraints/chipscope_ila_256.xdc +chipscope_ila_256.gise +chipscope_ila_256.ncf +chipscope_ila_256.ngc +chipscope_ila_256.ucf +chipscope_ila_256.v +chipscope_ila_256.veo +chipscope_ila_256.xco +chipscope_ila_256.xdc +chipscope_ila_256.xise +chipscope_ila_256_flist.txt +chipscope_ila_256_readme.txt +chipscope_ila_256_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt new file mode 100644 index 000000000..764247d3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_readme.txt @@ -0,0 +1,53 @@ +The following files were generated for 'chipscope_ila_256' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +ISE file generator: + Add description here... + + * chipscope_ila_32_flist.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_256.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_256.cdc + * chipscope_ila_256.constraints/chipscope_ila_256.ucf + * chipscope_ila_256.constraints/chipscope_ila_256.xdc + * chipscope_ila_256.ncf + * chipscope_ila_256.ngc + * chipscope_ila_256.ucf + * chipscope_ila_256.v + * chipscope_ila_256.veo + * chipscope_ila_256.xdc + * chipscope_ila_256_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_256.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_256.gise + * chipscope_ila_256.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_256_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_256_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl new file mode 100755 index 000000000..1fb67dd98 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_256_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_256_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_256_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_256_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_256 +} +# ::chipscope_ila_256_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_256_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.constraints/chipscope_ila_256.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_256_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_256 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy new file mode 100644 index 000000000..69e989c04 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila_32 +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[31:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc new file mode 100644 index 000000000..d0ba2170c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.cdc @@ -0,0 +1,48 @@ +#ChipScope Core Generator Project File Version 3.0 +#Fri Mar 08 11:59:29 PST 2013 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] +SignalExport.triggerChannel<0000><0031>=TRIG0[31] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=32 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.constraints/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc new file mode 100644 index 000000000..29677d942 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf new file mode 100644 index 000000000..228071c37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila_32 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila_32 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v new file mode 100644 index 000000000..5c409080b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.v +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila_32( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [31 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo new file mode 100644 index 000000000..c949fbe7f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.4 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila_32.veo +// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila_32 YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [31:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco new file mode 100644 index 000000000..15047431b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 19:57:57 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila_32 +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=32 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T02:47:40Z +# END Extra information +GENERATE +# CRC: aad58d16 diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt new file mode 100644 index 000000000..0a88237f8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_ila_32.asy +chipscope_ila_32.cdc +chipscope_ila_32.constraints/chipscope_ila_32.ucf +chipscope_ila_32.constraints/chipscope_ila_32.xdc +chipscope_ila_32.gise +chipscope_ila_32.ncf +chipscope_ila_32.ngc +chipscope_ila_32.ucf +chipscope_ila_32.v +chipscope_ila_32.veo +chipscope_ila_32.xco +chipscope_ila_32.xdc +chipscope_ila_32.xise +chipscope_ila_32_flist.txt +chipscope_ila_32_readme.txt +chipscope_ila_32_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt new file mode 100644 index 000000000..231b5d1ad --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila_32' in directory +/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila_32.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila_32.cdc + * chipscope_ila_32.constraints/chipscope_ila_32.ucf + * chipscope_ila_32.constraints/chipscope_ila_32.xdc + * chipscope_ila_32.ncf + * chipscope_ila_32.ngc + * chipscope_ila_32.ucf + * chipscope_ila_32.v + * chipscope_ila_32.veo + * chipscope_ila_32.xdc + * chipscope_ila_32_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila_32.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila_32.gise + * chipscope_ila_32.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_32_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_32_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl new file mode 100755 index 000000000..f3617c66c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/chipscope_ila_32_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_32_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_32_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_32_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila_32 +} +# ::chipscope_ila_32_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_32_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.constraints/chipscope_ila_32.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_32_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila_32 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b200/coregen/coregen.cgp b/fpga/usrp3/top/b200/coregen/coregen.cgp new file mode 100644 index 000000000..24f6041a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET package = fgg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy new file mode 100644 index 000000000..fd6eef6f7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_4k_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[9:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[9:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..b379066c6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v new file mode 100644 index 000000000..5724dd553 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_4k_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [9 : 0] rd_data_count; +output [9 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(10), + .C_WR_DEPTH(512), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo new file mode 100644 index 000000000..12c025d5d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_4k_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [9 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [9 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_4k_2clk.v when simulating +// the core, fifo_4k_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco new file mode 100644 index 000000000..f617ee440 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 25 19:58:19 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_4k_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=510 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=512 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 372c204f diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ + + +fifo_generator_v9_3_vinfo + + + +


+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd new file mode 100755 index 000000000..2674443c8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_4k_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_4k_2clk_exdes; + + + +architecture xilinx of fifo_4k_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_4k_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_4k_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat new file mode 100755 index 000000000..f5fcf0a2b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_4k_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh new file mode 100755 index 000000000..9cb53f5c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_4k_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..9d99aaa5c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..db245edbb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-2 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..a48fea790 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_4k_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..7171a0e5e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_4k_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..6af923b85 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75csg484-2 +set projName fifo_4k_2clk +set design fifo_4k_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_4k_2clk_exdes +add_files -norecurse {../../example_design/fifo_4k_2clk_exdes.vhd} +add_files -norecurse {./fifo_4k_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_4k_2clk_exdes.xdc} +set_property top fifo_4k_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_4k_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_4k_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj new file mode 100755 index 000000000..573a1716f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_4k_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr new file mode 100755 index 000000000..bff287f78 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_4k_2clk_exdes +-p xc6slx75-csg484-2 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_4k_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd new file mode 100755 index 000000000..d14bb7a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd new file mode 100755 index 000000000..0a7c2aa87 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd new file mode 100755 index 000000000..fa32e4781 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_4k_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd new file mode 100755 index 000000000..46d4ac9cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_4k_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_4k_2clk_pkg; + + + +PACKAGE BODY fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_4k_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd new file mode 100755 index 000000000..bed58d88e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_4k_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_4k_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd new file mode 100755 index 000000000..4149735c5 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_4k_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_4k_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_4k_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_4k_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 9, + C_RD_PNTR_WIDTH => 9, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_4k_2clk_inst : fifo_4k_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd new file mode 100755 index 000000000..51d699e21 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_4k_2clk_arch OF fifo_4k_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_4k_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_4k_2clk_synth + + fifo_4k_2clk_synth_inst:fifo_4k_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 76 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..3d0783055 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_4k_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..c3abd5a51 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_4k_2clk.v +vhpcomp -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..af53abefb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_4k_2clk.v +vcom -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..0d3376452 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_4k_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..8c26af20c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_4k_2clk.v +vhdlan ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b9ef9837a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..a6f8ce91f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..f5ad36b7e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..74e930a13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..a1967adcf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_4k_2clk_synth_inst:fifo_4k_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..f62f540be --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..28ebc1163 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt new file mode 100644 index 000000000..e33a4de1c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_flist.txt @@ -0,0 +1,56 @@ +# Output products list for +fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_4k_2clk/doc/pg057-fifo-generator.pdf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +fifo_4k_2clk/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/implement/implement.bat +fifo_4k_2clk/implement/implement.sh +fifo_4k_2clk/implement/implement_synplify.bat +fifo_4k_2clk/implement/implement_synplify.sh +fifo_4k_2clk/implement/planAhead_ise.bat +fifo_4k_2clk/implement/planAhead_ise.sh +fifo_4k_2clk/implement/planAhead_ise.tcl +fifo_4k_2clk/implement/xst.prj +fifo_4k_2clk/implement/xst.scr +fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +fifo_4k_2clk/simulation/functional/simulate_isim.bat +fifo_4k_2clk/simulation/functional/simulate_isim.sh +fifo_4k_2clk/simulation/functional/simulate_mti.bat +fifo_4k_2clk/simulation/functional/simulate_mti.do +fifo_4k_2clk/simulation/functional/simulate_mti.sh +fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +fifo_4k_2clk/simulation/functional/simulate_vcs.sh +fifo_4k_2clk/simulation/functional/ucli_commands.key +fifo_4k_2clk/simulation/functional/vcs_session.tcl +fifo_4k_2clk/simulation/functional/wave_isim.tcl +fifo_4k_2clk/simulation/functional/wave_mti.do +fifo_4k_2clk/simulation/functional/wave_ncsim.sv +fifo_4k_2clk/simulation/timing/simulate_isim.bat +fifo_4k_2clk/simulation/timing/simulate_isim.sh +fifo_4k_2clk/simulation/timing/simulate_mti.bat +fifo_4k_2clk/simulation/timing/simulate_mti.do +fifo_4k_2clk/simulation/timing/simulate_mti.sh +fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +fifo_4k_2clk/simulation/timing/simulate_vcs.sh +fifo_4k_2clk/simulation/timing/ucli_commands.key +fifo_4k_2clk/simulation/timing/vcs_session.tcl +fifo_4k_2clk/simulation/timing/wave_isim.tcl +fifo_4k_2clk/simulation/timing/wave_mti.do +fifo_4k_2clk/simulation/timing/wave_ncsim.sv +fifo_4k_2clk.asy +fifo_4k_2clk.gise +fifo_4k_2clk.ngc +fifo_4k_2clk.v +fifo_4k_2clk.veo +fifo_4k_2clk.xco +fifo_4k_2clk.xise +fifo_4k_2clk_flist.txt +fifo_4k_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl new file mode 100644 index 000000000..bdc5c355d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_4k_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_4k_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_4k_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_4k_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_4k_2clk +} +# ::fifo_4k_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_4k_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_4k_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy new file mode 100644 index 000000000..1c03599f3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_short_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[5:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[5:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc new file mode 100644 index 000000000..ec6b0ff10 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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f1=<080bn853`98k136290/o:4;939mg3<4j21d88>50;&`3?2>:2dh:7=l;:m70c<72-i<697=;oa5>6b<3f>2:7>5$b590<45<#k>0?5?5ac780b>=h<0>1<7*l7;6:6>hd>3>;76a;9183>!e02=397cm9:538?j2?=3:1(n954808jf0=<;10c99n:18'g2<31;1eo;4;3:9l03`=83.h;7:62:l`2?2332e?:94?:%a4>1?53gi=69;4;n66=?6=,j=184<4nb4903=n6=4+c687=7=ik?0?;65`4`f94?"d?3>jo6`l6;28?j2fj3:1(n954`a8jf0=921d8lo50;&`3?2fk2dh:7<4;n6b=?6=,j=18lm4nb497>=hhd>3>07b:n7;29 f1=io7>5$b590gbih6`l6;08?j2ei3:1(n954cf8jf0=;21d8o750;&`3?2el2dh:7:4;n6a=hN4l01/m948;h7f>5<=1<75fc883>>idj3:17pl>b283>1<729q/h>468:J0``=O;m30(l:57:k6a?6=3`=<6=44ib;94?=hkk0;66sm1c094?2=83:p(i=5999K7ac<@:n27)o;:69j1`<722c<;7>5;ha:>5<5<3290;w)j<:848L6bb3A9o56*n4;08m0c=831b;>4?::k43?6=3fii6=44}c1``?6=<3:1i7>5;h54>5<>{e;m91<7:50;2x a5=111C?ik4H2f:?M3f3-h96i<4i4g94?=n?>0;66gl9;29?jee2900qo=l2;290?6=8r.o?777;I1ga>N4l01C9l5+b38g6>"f<3=0e8k50;9j32<722ch57>5;naa>5<53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4>idj3:17pl6<729q/h>465:J0``=O;m30D8o4$c09`7=#i=097d;j:188m21=831doo4?::a7f7=83>1<7>t$e19===O;mo0D>j6;I7b?!d52m80(l:57:k6a?6=3`=<6=44ib;94?=hkk0;66sm3b:94?2=83:p(i=5999K7ac<@:n27)o;:69j1`<722c<;7>5;ha:>5<5<3290;w)j<:8:8L6bb3A9o56*n4;58m0c=831b;:4?::k`=?6=3fii6=44}c1`2?6=<3:15;|`0gc<72:0;6=u+d28:1>N4ll1C?i74H4c8 g4=l;1/m94=;h7f>5<=1<75`cc83>>{e;ji1<7:50;2x a5=111C?ik4H2f:?!g32>1b9h4?::k43?6=3`i26=44ob`94?=zj:ii6=4;:183!b42020D>jj;I1g=>"f<3=0e8k50;9j32<722ch57>5;naa>5<53;294~"c;33>7E=ke:J0`<=O=h1/n?4k2:&b0?4>idj3:17pl1<729q/h>468:J0``=O;m30D8o4$c09`7=#i=0<7d;j:188m21=831bo44?::m`f?6=3th94o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9454?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9494?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94=4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`133<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`131<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`134<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;=4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:h4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:n4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9::4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`123<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`121<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`127<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9:<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`125<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99n4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`11<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9954?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`112<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`110<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9994?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`116<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`115<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10d<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9844?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`10=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th94i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`1N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9444?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`13`<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th9;>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`12=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th99i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`117<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th98:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`103<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th95=4?:3494?6|,m91on5G3eg8L6b>3S?o6nu>8;3:>4g=9k0i6n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a5=kj1C?ik4H2f:?_3c2jq:47?6:0c95g6=#i>087)o7:29j7ad=831b?im50;9j3g<72-i<6:o4nb494>=n?00;6)m8:6c8jf0=921b;h4?:%a4>2b!e02>n0bn851:9j<4<72-i<65>4nb494>=n?o0;6)m8:928jf0=921b494?:%a4>=5!e02190bn851:9j00<72-i<69:4nb494>=n<:0;6)m8:568jf0=921b8?4?:%a4>1265f4083>!e02=>0bn853:9j05<72-i<69:4nb490>=n1g!e02=k0bn852:9j02<72-i<69o4nb497>=n06!e02<:0bn851:9j0`<72-i<68>4nb496>=n06!e02<<0bn850:9j10<72-i<6884nb495>=n==0;6)m8:448jf0=:21b9>4?:%a4>00!e02<<0bn854:9l<2<72-i<6584nb494>=h0<0;6)m8:948jf0=921d4l4?:%a4>=?!e02130bn851:9l=h0k0;6)m8:9a8jf0=921d5=4?:%a4>=`!e021l0bn851:9~f7?42909:7>50z&g7?ed3A9oi6Fa;3a>g0;32>44=u-k>6>5+a780?!g02:1/m54<;h1gf?6=3`9oo7>5;h5a>5<#k>0290/o:48a:l`2?7<3`=n6=4+c684`>hd>3:07d9l:18'g2<0l2dh:7?4;h:2>5<#k>03<6`l6;28?l1a290/o:470:l`2?7<3`2?6=4+c68;7>hd>3:07d6=:18'g25<#k>0?86`l6;28?l24290/o:4;4:l`2?7<3`>96=4+c6870>hd>3807d:>:18'g2<3<2dh:7=4;h63>5<#k>0?86`l6;68?l2e290/o:4;a:l`2?6<3`>26=4+c687e>hd>3;07d:7:18'g2<3i2dh:7<4;h64>5<#k>0?m6`l6;18?l21290/o:4;a:l`2?2<3`?:6=4+c6864>hd>3:07d:i:18'g2<282dh:7?4;h6f>5<#k>0><6`l6;08?l2c290/o:4:0:l`2?5<3`>h6=4+c6864>hd>3>07d;8:18'g2<2>2dh:7>4;h76>5<#k>0>:6`l6;38?l33290/o:4:6:l`2?4<3`?86=4+c6862>hd>3907d;=:18'g2<2>2dh:7:4;n:4>5<#k>03:6`l6;28?j>2290/o:476:l`2?7<3f2j6=4+c68;=>hd>3:07b67:18'g25<#k>03o6`l6;28?j>e290/o:47c:l`2?7<3f3;6=4+c68;b>hd>3:07b6j:18'g2N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0ea<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8mo4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8m:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e0<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8m>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0e4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8584?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0=6<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th84i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8444?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<2<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8484?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<4<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`03a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`03<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`030<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8;>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`034<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`02g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`022<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`026<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th89i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8944?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`010<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th89>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`014<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88k4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00a<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88o4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`00<<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88:4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`000<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88>4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`07g<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?44?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`072<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?84?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`076<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8?<4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06c<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>i4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8n;4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0f5<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th85l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`0<1<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8:h4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`01=<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th88?4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`06f<72<0;6=u+d28:3>N4ll1C?i74$`696>o2m3:17d8?:188m25=831b;:4?::m`f?6=3th8>l4?:483>5}#l:02;6F1>6g:e;29?l072900e:=50;9j32<722ehn7>5;|`234<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a526=83>1<7>t$e19=3=O;mo0D>j6;%c7>7=n=l0;66g83;29?l102900cnl50;9~f40a290?6=4?{%f0><0<@:nn7E=k9:&b0?4>o0?3:17bmm:188yg71m3:187>50z&g7??13A9oi6F0;66alb;29?xd6>m0;694?:1y'`6<>>2B8hh5G3e;8 d2=:2c>i7>5;h50>5<=1<75`cc83>>{e9?i1<7:50;2x a5=1?1C?ik4H2f:?!g32;1b9h4?::k47?6=3`=<6=44ob`94?=zj8k26=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj8k>6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj83n6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj83h6=4::183!b420=0D>jj;I1g=>"f<380e8k50;9j25<722c5;h54>5<5<2290;w)j<:858L6bb3A9o56*n4;08m0c=831b:=4?::k47?6=3`=<6=44ob`94?=zj8326=4::183!b42030D>jj;I1g=>"f<3=0e8k50;9j25<722c<;7>5;ha:>5<5<3290;w)j<:848L6bb3A9o56*n4;08m0c=831b;>4?::k43?6=3fii6=44}c343?6=<3:15;|`2<4<72=0;6=u+d28:2>N4ll1C?i74$`696>o2m3:17d9<:188m21=831doo4?::a52b=83>1<7>t$e19===O;mo0D>j6;%c7>2=n=l0;66g87;29?le>2900cnl50;9~f41d290?6=4?{%f0><><@:nn7E=k9:&b0?1>od13:17bmm:188yg7c03:187>50z&g7??13A9oi6F0;66alb;29?xd6l>0;694?:1y'`6<>>2B8hh5G3e;8 d2=:2c>i7>5;h50>5<=1<75`cc83>>{e9m<1<7:50;2x a5=1?1C?ik4H2f:?!g32;1b9h4?::k47?6=3`=<6=44ob`94?=zj8n>6=4;:183!b420<0D>jj;I1g=>"f<380e8k50;9j36<722c<;7>5;naa>5<54;294~"c;33=7E=ke:J0`<=#i=097d;j:188m25=831b;:4?::m`f?6=3th:h>4?:583>5}#l:02:6F1>6g:e;29?l142900e:950;9lgg<722wi=k750;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c>=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k950;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c5=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k<50;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5c7=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=k>50;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5``=83?1<7>t$e19=<=O;mo0D>j6;%c7>2=n=l0;66g90;29?l102900en750;9lgg<722wi=h750;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5`>=83?1<7>t$e19=2=O;mo0D>j6;%c7>7=n=l0;66g90;29?l142900e:950;9lgg<722wi=h950;794?6|,m915:5G3eg8L6b>3-k?6?5f5d83>>o183:17d9<:188m21=831doo4?::a5`0=83?1<7>t$e19=<=O;mo0D>j6;%c7>2=n=l0;66g90;29?l102900en750;9lgg<722wij>4?:583>5}#l:02:6F0;66alb;29?xda<3:187>50z&g7??13A9oi6F6*n4;08m0c=831b;>4?::k43?6=3fii6=44}cd6>5<3290;w)j<:848L6bb3A9o56F:a:&a6?b53-k?6?5f5d83>>o0;3:17d98:188kfd=831vnk850;694?6|,m915;5G3eg8L6b>3A?j7)l=:e08 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v new file mode 100644 index 000000000..82200a502 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.v @@ -0,0 +1,491 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module fifo_short_2clk( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + rd_data_count, + wr_data_count +); + +input rst; +input wr_clk; +input rd_clk; +input [71 : 0] din; +input wr_en; +input rd_en; +output [71 : 0] dout; +output full; +output empty; +output [5 : 0] rd_data_count; +output [5 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V9_3 #( + .C_ADD_NGC_CONSTRAINT(0), + .C_APPLICATION_TYPE_AXIS(0), + .C_APPLICATION_TYPE_RACH(0), + .C_APPLICATION_TYPE_RDCH(0), + .C_APPLICATION_TYPE_WACH(0), + .C_APPLICATION_TYPE_WDCH(0), + .C_APPLICATION_TYPE_WRCH(0), + .C_AXI_ADDR_WIDTH(32), + .C_AXI_ARUSER_WIDTH(1), + .C_AXI_AWUSER_WIDTH(1), + .C_AXI_BUSER_WIDTH(1), + .C_AXI_DATA_WIDTH(64), + .C_AXI_ID_WIDTH(4), + .C_AXI_RUSER_WIDTH(1), + .C_AXI_TYPE(0), + .C_AXI_WUSER_WIDTH(1), + .C_AXIS_TDATA_WIDTH(64), + .C_AXIS_TDEST_WIDTH(4), + .C_AXIS_TID_WIDTH(8), + .C_AXIS_TKEEP_WIDTH(4), + .C_AXIS_TSTRB_WIDTH(4), + .C_AXIS_TUSER_WIDTH(4), + .C_AXIS_TYPE(0), + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(5), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(72), + .C_DIN_WIDTH_AXIS(1), + .C_DIN_WIDTH_RACH(32), + .C_DIN_WIDTH_RDCH(64), + .C_DIN_WIDTH_WACH(32), + .C_DIN_WIDTH_WDCH(64), + .C_DIN_WIDTH_WRCH(2), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(72), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_ERROR_INJECTION_TYPE_AXIS(0), + .C_ERROR_INJECTION_TYPE_RACH(0), + .C_ERROR_INJECTION_TYPE_RDCH(0), + .C_ERROR_INJECTION_TYPE_WACH(0), + .C_ERROR_INJECTION_TYPE_WDCH(0), + .C_ERROR_INJECTION_TYPE_WRCH(0), + .C_FAMILY("spartan6"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_AXI_ARUSER(0), + .C_HAS_AXI_AWUSER(0), + .C_HAS_AXI_BUSER(0), + .C_HAS_AXI_RD_CHANNEL(0), + .C_HAS_AXI_RUSER(0), + .C_HAS_AXI_WR_CHANNEL(0), + .C_HAS_AXI_WUSER(0), + .C_HAS_AXIS_TDATA(0), + .C_HAS_AXIS_TDEST(0), + .C_HAS_AXIS_TID(0), + .C_HAS_AXIS_TKEEP(0), + .C_HAS_AXIS_TLAST(0), + .C_HAS_AXIS_TREADY(1), + .C_HAS_AXIS_TSTRB(0), + .C_HAS_AXIS_TUSER(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_DATA_COUNTS_AXIS(0), + .C_HAS_DATA_COUNTS_RACH(0), + .C_HAS_DATA_COUNTS_RDCH(0), + .C_HAS_DATA_COUNTS_WACH(0), + .C_HAS_DATA_COUNTS_WDCH(0), + .C_HAS_DATA_COUNTS_WRCH(0), + .C_HAS_INT_CLK(0), + .C_HAS_MASTER_CE(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_PROG_FLAGS_AXIS(0), + .C_HAS_PROG_FLAGS_RACH(0), + .C_HAS_PROG_FLAGS_RDCH(0), + .C_HAS_PROG_FLAGS_WACH(0), + .C_HAS_PROG_FLAGS_WDCH(0), + .C_HAS_PROG_FLAGS_WRCH(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SLAVE_CE(0), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_IMPLEMENTATION_TYPE_AXIS(1), + .C_IMPLEMENTATION_TYPE_RACH(1), + .C_IMPLEMENTATION_TYPE_RDCH(1), + .C_IMPLEMENTATION_TYPE_WACH(1), + .C_IMPLEMENTATION_TYPE_WDCH(1), + .C_IMPLEMENTATION_TYPE_WRCH(1), + .C_INIT_WR_PNTR_VAL(0), + .C_INTERFACE_TYPE(0), + .C_MEMORY_TYPE(2), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x72"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022), + .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_EMPTY_TYPE_AXIS(0), + .C_PROG_EMPTY_TYPE_RACH(0), + .C_PROG_EMPTY_TYPE_RDCH(0), + .C_PROG_EMPTY_TYPE_WACH(0), + .C_PROG_EMPTY_TYPE_WDCH(0), + .C_PROG_EMPTY_TYPE_WRCH(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(31), + .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), + .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(30), + .C_PROG_FULL_TYPE(0), + .C_PROG_FULL_TYPE_AXIS(0), + .C_PROG_FULL_TYPE_RACH(0), + .C_PROG_FULL_TYPE_RDCH(0), + .C_PROG_FULL_TYPE_WACH(0), + .C_PROG_FULL_TYPE_WDCH(0), + .C_PROG_FULL_TYPE_WRCH(0), + .C_RACH_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(6), + .C_RD_DEPTH(32), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(5), + .C_RDCH_TYPE(0), + .C_REG_SLICE_MODE_AXIS(0), + .C_REG_SLICE_MODE_RACH(0), + .C_REG_SLICE_MODE_RDCH(0), + .C_REG_SLICE_MODE_WACH(0), + .C_REG_SLICE_MODE_WDCH(0), + .C_REG_SLICE_MODE_WRCH(0), + .C_SYNCHRONIZER_STAGE(2), + .C_UNDERFLOW_LOW(0), + .C_USE_COMMON_OVERFLOW(0), + .C_USE_COMMON_UNDERFLOW(0), + .C_USE_DEFAULT_SETTINGS(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_ECC_AXIS(0), + .C_USE_ECC_RACH(0), + .C_USE_ECC_RDCH(0), + .C_USE_ECC_WACH(0), + .C_USE_ECC_WDCH(0), + .C_USE_ECC_WRCH(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(1), + .C_VALID_LOW(0), + .C_WACH_TYPE(0), + .C_WDCH_TYPE(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(6), + .C_WR_DEPTH(32), + .C_WR_DEPTH_AXIS(1024), + .C_WR_DEPTH_RACH(16), + .C_WR_DEPTH_RDCH(1024), + .C_WR_DEPTH_WACH(16), + .C_WR_DEPTH_WDCH(1024), + .C_WR_DEPTH_WRCH(16), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(5), + .C_WR_PNTR_WIDTH_AXIS(10), + .C_WR_PNTR_WIDTH_RACH(4), + .C_WR_PNTR_WIDTH_RDCH(10), + .C_WR_PNTR_WIDTH_WACH(4), + .C_WR_PNTR_WIDTH_WDCH(10), + .C_WR_PNTR_WIDTH_WRCH(4), + .C_WR_RESPONSE_LATENCY(1), + .C_WRCH_TYPE(0) + ) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR(), + .M_ACLK(), + .S_ACLK(), + .S_ARESETN(), + .M_ACLK_EN(), + .S_ACLK_EN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWLOCK(), + .S_AXI_AWCACHE(), + .S_AXI_AWPROT(), + .S_AXI_AWQOS(), + .S_AXI_AWREGION(), + .S_AXI_AWUSER(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WID(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WUSER(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BUSER(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .M_AXI_AWID(), + .M_AXI_AWADDR(), + .M_AXI_AWLEN(), + .M_AXI_AWSIZE(), + .M_AXI_AWBURST(), + .M_AXI_AWLOCK(), + .M_AXI_AWCACHE(), + .M_AXI_AWPROT(), + .M_AXI_AWQOS(), + .M_AXI_AWREGION(), + .M_AXI_AWUSER(), + .M_AXI_AWVALID(), + .M_AXI_AWREADY(), + .M_AXI_WID(), + .M_AXI_WDATA(), + .M_AXI_WSTRB(), + .M_AXI_WLAST(), + .M_AXI_WUSER(), + .M_AXI_WVALID(), + .M_AXI_WREADY(), + .M_AXI_BID(), + .M_AXI_BRESP(), + .M_AXI_BUSER(), + .M_AXI_BVALID(), + .M_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARLOCK(), + .S_AXI_ARCACHE(), + .S_AXI_ARPROT(), + .S_AXI_ARQOS(), + .S_AXI_ARREGION(), + .S_AXI_ARUSER(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RUSER(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .M_AXI_ARID(), + .M_AXI_ARADDR(), + .M_AXI_ARLEN(), + .M_AXI_ARSIZE(), + .M_AXI_ARBURST(), + .M_AXI_ARLOCK(), + .M_AXI_ARCACHE(), + .M_AXI_ARPROT(), + .M_AXI_ARQOS(), + .M_AXI_ARREGION(), + .M_AXI_ARUSER(), + .M_AXI_ARVALID(), + .M_AXI_ARREADY(), + .M_AXI_RID(), + .M_AXI_RDATA(), + .M_AXI_RRESP(), + .M_AXI_RLAST(), + .M_AXI_RUSER(), + .M_AXI_RVALID(), + .M_AXI_RREADY(), + .S_AXIS_TVALID(), + .S_AXIS_TREADY(), + .S_AXIS_TDATA(), + .S_AXIS_TSTRB(), + .S_AXIS_TKEEP(), + .S_AXIS_TLAST(), + .S_AXIS_TID(), + .S_AXIS_TDEST(), + .S_AXIS_TUSER(), + .M_AXIS_TVALID(), + .M_AXIS_TREADY(), + .M_AXIS_TDATA(), + .M_AXIS_TSTRB(), + .M_AXIS_TKEEP(), + .M_AXIS_TLAST(), + .M_AXIS_TID(), + .M_AXIS_TDEST(), + .M_AXIS_TUSER(), + .AXI_AW_INJECTSBITERR(), + .AXI_AW_INJECTDBITERR(), + .AXI_AW_PROG_FULL_THRESH(), + .AXI_AW_PROG_EMPTY_THRESH(), + .AXI_AW_DATA_COUNT(), + .AXI_AW_WR_DATA_COUNT(), + .AXI_AW_RD_DATA_COUNT(), + .AXI_AW_SBITERR(), + .AXI_AW_DBITERR(), + .AXI_AW_OVERFLOW(), + .AXI_AW_UNDERFLOW(), + .AXI_AW_PROG_FULL(), + .AXI_AW_PROG_EMPTY(), + .AXI_W_INJECTSBITERR(), + .AXI_W_INJECTDBITERR(), + .AXI_W_PROG_FULL_THRESH(), + .AXI_W_PROG_EMPTY_THRESH(), + .AXI_W_DATA_COUNT(), + .AXI_W_WR_DATA_COUNT(), + .AXI_W_RD_DATA_COUNT(), + .AXI_W_SBITERR(), + .AXI_W_DBITERR(), + .AXI_W_OVERFLOW(), + .AXI_W_UNDERFLOW(), + .AXI_B_INJECTSBITERR(), + .AXI_W_PROG_FULL(), + .AXI_W_PROG_EMPTY(), + .AXI_B_INJECTDBITERR(), + .AXI_B_PROG_FULL_THRESH(), + .AXI_B_PROG_EMPTY_THRESH(), + .AXI_B_DATA_COUNT(), + .AXI_B_WR_DATA_COUNT(), + .AXI_B_RD_DATA_COUNT(), + .AXI_B_SBITERR(), + .AXI_B_DBITERR(), + .AXI_B_OVERFLOW(), + .AXI_B_UNDERFLOW(), + .AXI_AR_INJECTSBITERR(), + .AXI_B_PROG_FULL(), + .AXI_B_PROG_EMPTY(), + .AXI_AR_INJECTDBITERR(), + .AXI_AR_PROG_FULL_THRESH(), + .AXI_AR_PROG_EMPTY_THRESH(), + .AXI_AR_DATA_COUNT(), + .AXI_AR_WR_DATA_COUNT(), + .AXI_AR_RD_DATA_COUNT(), + .AXI_AR_SBITERR(), + .AXI_AR_DBITERR(), + .AXI_AR_OVERFLOW(), + .AXI_AR_UNDERFLOW(), + .AXI_AR_PROG_FULL(), + .AXI_AR_PROG_EMPTY(), + .AXI_R_INJECTSBITERR(), + .AXI_R_INJECTDBITERR(), + .AXI_R_PROG_FULL_THRESH(), + .AXI_R_PROG_EMPTY_THRESH(), + .AXI_R_DATA_COUNT(), + .AXI_R_WR_DATA_COUNT(), + .AXI_R_RD_DATA_COUNT(), + .AXI_R_SBITERR(), + .AXI_R_DBITERR(), + .AXI_R_OVERFLOW(), + .AXI_R_UNDERFLOW(), + .AXIS_INJECTSBITERR(), + .AXI_R_PROG_FULL(), + .AXI_R_PROG_EMPTY(), + .AXIS_INJECTDBITERR(), + .AXIS_PROG_FULL_THRESH(), + .AXIS_PROG_EMPTY_THRESH(), + .AXIS_DATA_COUNT(), + .AXIS_WR_DATA_COUNT(), + .AXIS_RD_DATA_COUNT(), + .AXIS_SBITERR(), + .AXIS_DBITERR(), + .AXIS_OVERFLOW(), + .AXIS_UNDERFLOW(), + .AXIS_PROG_FULL(), + .AXIS_PROG_EMPTY() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo new file mode 100644 index 000000000..06d74a77c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2013 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 * +* * +* Rev 1. The FIFO Generator is a parameterizable first-in/first-out * +* memory queue generator. Use it to generate resource and performance * +* optimized FIFOs with common or independent read/write clock domains, * +* and optional fixed or programmable full and empty flags and * +* handshaking signals. Choose from a selection of memory resource * +* types for implementation. Optional Hamming code based error * +* detection and correction as well as error injection capability for * +* system test help to insure data integrity. FIFO width and depth are * +* parameterizable, and for native interface FIFOs, asymmetric read and * +* write port widths are also supported. * +*******************************************************************************/ + +// Interfaces: +// AXI4Stream_MASTER_M_AXIS +// AXI4Stream_SLAVE_S_AXIS +// AXI4_MASTER_M_AXI +// AXI4_SLAVE_S_AXI +// AXI4Lite_MASTER_M_AXI +// AXI4Lite_SLAVE_S_AXI +// master_aclk +// slave_aclk +// slave_aresetn + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_short_2clk your_instance_name ( + .rst(rst), // input rst + .wr_clk(wr_clk), // input wr_clk + .rd_clk(rd_clk), // input rd_clk + .din(din), // input [71 : 0] din + .wr_en(wr_en), // input wr_en + .rd_en(rd_en), // input rd_en + .dout(dout), // output [71 : 0] dout + .full(full), // output full + .empty(empty), // output empty + .rd_data_count(rd_data_count), // output [5 : 0] rd_data_count + .wr_data_count(wr_data_count) // output [5 : 0] wr_data_count +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_short_2clk.v when simulating +// the core, fifo_short_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco new file mode 100644 index 000000000..0f256d496 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Mar 8 18:15:07 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=fifo_short_2clk +CSET data_count=false +CSET data_count_width=5 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Distributed_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=31 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=30 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=72 +CSET input_depth=32 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=72 +CSET output_depth=32 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=6 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=true +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=6 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 8cc2c19d diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html new file mode 100644 index 000000000..fefce62a3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html @@ -0,0 +1,247 @@ + + +fifo_generator_v9_3_vinfo + + + +

+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd new file mode 100755 index 000000000..9e38bcb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_short_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_short_2clk_exdes; + + + +architecture xilinx of fifo_short_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_short_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_short_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat new file mode 100755 index 000000000..f846d4485 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_short_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh new file mode 100755 index 000000000..e2453c4a1 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_short_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..4fe498bff --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..882036474 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-fgg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..49053fd63 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_short_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..42916c2bc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_short_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..9f39b3e13 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75fgg484-3 +set projName fifo_short_2clk +set design fifo_short_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_short_2clk_exdes +add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd} +add_files -norecurse {./fifo_short_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc} +set_property top fifo_short_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj new file mode 100755 index 000000000..f16af4308 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_short_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr new file mode 100755 index 000000000..b5a9091c7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_short_2clk_exdes +-p xc6slx75-fgg484-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_short_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd new file mode 100755 index 000000000..bc7a1b525 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd new file mode 100755 index 000000000..b0465d84f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_short_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd new file mode 100755 index 000000000..5d6506398 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_short_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd new file mode 100755 index 000000000..4c0e4035b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_short_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_short_2clk_pkg; + + + +PACKAGE BODY fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_short_2clk_pkg; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd new file mode 100755 index 000000000..80c201c3b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_short_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_short_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd new file mode 100755 index 000000000..e9139fc96 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_short_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_short_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_short_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 5, + C_RD_PNTR_WIDTH => 5, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_short_2clk_inst : fifo_short_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd new file mode 100755 index 000000000..6d86157db --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_short_2clk_arch OF fifo_short_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_short_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_short_2clk_synth + + fifo_short_2clk_synth_inst:fifo_short_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 108 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..d40cb85cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_short_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..78f9ce588 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_short_2clk.v +vhpcomp -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..8deb52187 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_short_2clk.v +vcom -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..749f9db06 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_short_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..71a568e24 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_short_2clk.v +vhdlan ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..7f3170d74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..536a7cfee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..2d9404294 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..7ec785533 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..e9dc952cf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_short_2clk_synth_inst:fifo_short_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..bbd548a74 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..e27baa9d8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt new file mode 100644 index 000000000..4ab119a52 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_flist.txt @@ -0,0 +1,57 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_short_2clk/doc/pg057-fifo-generator.pdf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +fifo_short_2clk/fifo_generator_v9_3_readme.txt +fifo_short_2clk/implement/implement.bat +fifo_short_2clk/implement/implement.sh +fifo_short_2clk/implement/implement_synplify.bat +fifo_short_2clk/implement/implement_synplify.sh +fifo_short_2clk/implement/planAhead_ise.bat +fifo_short_2clk/implement/planAhead_ise.sh +fifo_short_2clk/implement/planAhead_ise.tcl +fifo_short_2clk/implement/xst.prj +fifo_short_2clk/implement/xst.scr +fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +fifo_short_2clk/simulation/functional/simulate_isim.bat +fifo_short_2clk/simulation/functional/simulate_isim.sh +fifo_short_2clk/simulation/functional/simulate_mti.bat +fifo_short_2clk/simulation/functional/simulate_mti.do +fifo_short_2clk/simulation/functional/simulate_mti.sh +fifo_short_2clk/simulation/functional/simulate_ncsim.sh +fifo_short_2clk/simulation/functional/simulate_vcs.sh +fifo_short_2clk/simulation/functional/ucli_commands.key +fifo_short_2clk/simulation/functional/vcs_session.tcl +fifo_short_2clk/simulation/functional/wave_isim.tcl +fifo_short_2clk/simulation/functional/wave_mti.do +fifo_short_2clk/simulation/functional/wave_ncsim.sv +fifo_short_2clk/simulation/timing/simulate_isim.bat +fifo_short_2clk/simulation/timing/simulate_isim.sh +fifo_short_2clk/simulation/timing/simulate_mti.bat +fifo_short_2clk/simulation/timing/simulate_mti.do +fifo_short_2clk/simulation/timing/simulate_mti.sh +fifo_short_2clk/simulation/timing/simulate_ncsim.sh +fifo_short_2clk/simulation/timing/simulate_vcs.sh +fifo_short_2clk/simulation/timing/ucli_commands.key +fifo_short_2clk/simulation/timing/vcs_session.tcl +fifo_short_2clk/simulation/timing/wave_isim.tcl +fifo_short_2clk/simulation/timing/wave_mti.do +fifo_short_2clk/simulation/timing/wave_ncsim.sv +fifo_short_2clk.asy +fifo_short_2clk.gise +fifo_short_2clk.ngc +fifo_short_2clk.v +fifo_short_2clk.veo +fifo_short_2clk.xco +fifo_short_2clk.xise +fifo_short_2clk_flist.txt +fifo_short_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl new file mode 100644 index 000000000..0abe2bb7c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen/fifo_short_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_short_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_short_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_short_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_short_2clk +} +# ::fifo_short_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_short_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_short_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/.gitignore b/fpga/usrp3/top/b200/coregen_dsp/.gitignore new file mode 100644 index 000000000..f9823bca9 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/.gitignore @@ -0,0 +1,6 @@ +_xmsgs +*.log +*.ncf +*.xise +*.gise + diff --git a/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..180686b89 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/Makefile.srcs @@ -0,0 +1,15 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/b200/coregen_dsp/, \ +hbdec1.v \ +hbdec1.xco \ +hbdec2.v \ +hbdec2.xco \ +)) + diff --git a/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp b/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp new file mode 100644 index 000000000..52a3a53e7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = fgg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b200/coregen_dsp/filt2.coe b/fpga/usrp3/top/b200/coregen_dsp/filt2.coe new file mode 100644 index 000000000..e18b5daa7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/filt2.coe @@ -0,0 +1,36 @@ + Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb31.coe b/fpga/usrp3/top/b200/coregen_dsp/hb31.coe new file mode 100644 index 000000000..37f5a180e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb31.coe @@ -0,0 +1,32 @@ +Radix=10; +CoefData = -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb35.coe b/fpga/usrp3/top/b200/coregen_dsp/hb35.coe new file mode 100644 index 000000000..18078085d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb35.coe @@ -0,0 +1,36 @@ +Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb39.coe b/fpga/usrp3/top/b200/coregen_dsp/hb39.coe new file mode 100644 index 000000000..1d99fa946 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb39.coe @@ -0,0 +1,40 @@ +Radix=10; +CoefData = -102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb43.coe b/fpga/usrp3/top/b200/coregen_dsp/hb43.coe new file mode 100644 index 000000000..c56c4c928 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb43.coe @@ -0,0 +1,44 @@ +Radix=10; +CoefData = 100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb47.coe b/fpga/usrp3/top/b200/coregen_dsp/hb47.coe new file mode 100644 index 000000000..85b9a0f3d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0, + 194, + 0, +-62; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb51.coe b/fpga/usrp3/top/b200/coregen_dsp/hb51.coe new file mode 100644 index 000000000..ebfddb7fb --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb51.coe @@ -0,0 +1,52 @@ +Radix=10; +CoefData = 300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb55.coe b/fpga/usrp3/top/b200/coregen_dsp/hb55.coe new file mode 100644 index 000000000..07f861818 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb55.coe @@ -0,0 +1,56 @@ +Radix=10; +CoefData = -400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb59.coe b/fpga/usrp3/top/b200/coregen_dsp/hb59.coe new file mode 100644 index 000000000..79f1e362b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb59.coe @@ -0,0 +1,60 @@ +Radix=10; +CoefData = 500, +0, +-400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400, +0 +500; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hb63.coe b/fpga/usrp3/top/b200/coregen_dsp/hb63.coe new file mode 100644 index 000000000..3b312036d --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hb63.coe @@ -0,0 +1,67 @@ +; Generated with round((2^18-2)*halfgen_test(.22,16,1)) +; 88% effective BW, 64dB to 87dB rolloff +Radix=10; +CoefData = +-35, + 0, + 95, + 0, +-195, + 0, + 352, + 0, +-582, + 0, + 907, + 0, +-1354, + 0, + 1953, + 0, +-2751, + 0, + 3813, + 0, +-5249, + 0, + 7264, + 0, +-10296, + 0, + 15494, + 0, +-27083, + 0, + 83196, + 131071, + 83196, + 0, +-27083, + 0, + 15494, + 0, +-10296, + 0, + 7264, + 0, +-5249, + 0, + 3813, + 0, +-2751, + 0, + 1953, + 0, +-1354, + 0, + 907, + 0, +-582, + 0, + 352, + 0, + -195, + 0 + 95, + 0 +-35; diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy new file mode 100644 index 000000000..7644e7bbe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec1 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..68581229e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$26b<~753-Xnzd}foo8#5+421).97 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v new file mode 100644 index 000000000..24069fbac --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.v @@ -0,0 +1,45924 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec1.v +// /___/ /\ Timestamp: Fri Jan 9 12:44:22 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec1.ngc ./tmp/_cg/hbdec1.v +// Device : 6slx150tfgg484-3 +// Input file : ./tmp/_cg/hbdec1.ngc +// Output file : ./tmp/_cg/hbdec1.v +// # of Modules : 1 +// Design Name : hbdec1 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec1 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000e8e ; + wire \blk00000003/sig00000e8d ; + wire \blk00000003/sig00000e8c ; + wire \blk00000003/sig00000e8b ; + wire \blk00000003/sig00000e8a ; + wire \blk00000003/sig00000e89 ; + wire \blk00000003/sig00000e88 ; + wire \blk00000003/sig00000e87 ; + wire \blk00000003/sig00000e86 ; + wire \blk00000003/sig00000e85 ; + wire \blk00000003/sig00000e84 ; + wire \blk00000003/sig00000e83 ; + wire \blk00000003/sig00000e82 ; + wire \blk00000003/sig00000e81 ; + wire \blk00000003/sig00000e80 ; + wire \blk00000003/sig00000e7f ; + wire \blk00000003/sig00000e7e ; + wire \blk00000003/sig00000e7d ; + wire \blk00000003/sig00000e7c ; + wire \blk00000003/sig00000e7b ; + wire \blk00000003/sig00000e7a ; + wire \blk00000003/sig00000e79 ; + wire \blk00000003/sig00000e78 ; + wire \blk00000003/sig00000e77 ; + wire \blk00000003/sig00000e76 ; + wire \blk00000003/sig00000e75 ; + wire \blk00000003/sig00000e74 ; + wire \blk00000003/sig00000e73 ; + wire \blk00000003/sig00000e72 ; + wire \blk00000003/sig00000e71 ; + wire \blk00000003/sig00000e70 ; + wire \blk00000003/sig00000e6f ; + wire \blk00000003/sig00000e6e ; + wire \blk00000003/sig00000e6d ; + wire \blk00000003/sig00000e6c ; + wire \blk00000003/sig00000e6b ; + wire \blk00000003/sig00000e6a ; + wire \blk00000003/sig00000e69 ; + wire \blk00000003/sig00000e68 ; + wire \blk00000003/sig00000e67 ; + wire \blk00000003/sig00000e66 ; + wire \blk00000003/sig00000e65 ; + wire \blk00000003/sig00000e64 ; + wire \blk00000003/sig00000e63 ; + wire \blk00000003/sig00000e62 ; + wire \blk00000003/sig00000e61 ; + wire \blk00000003/sig00000e60 ; + wire \blk00000003/sig00000e5f ; + wire \blk00000003/sig00000e5e ; + wire \blk00000003/sig00000e5d ; + wire \blk00000003/sig00000e5c ; + wire \blk00000003/sig00000e5b ; + wire \blk00000003/sig00000e5a ; + wire \blk00000003/sig00000e59 ; + wire \blk00000003/sig00000e58 ; + wire \blk00000003/sig00000e57 ; + wire \blk00000003/sig00000e56 ; + wire \blk00000003/sig00000e55 ; + wire \blk00000003/sig00000e54 ; + wire \blk00000003/sig00000e53 ; + wire \blk00000003/sig00000e52 ; + wire \blk00000003/sig00000e51 ; + wire \blk00000003/sig00000e50 ; + wire \blk00000003/sig00000e4f ; + wire \blk00000003/sig00000e4e ; + wire \blk00000003/sig00000e4d ; + wire \blk00000003/sig00000e4c ; + wire \blk00000003/sig00000e4b ; + wire \blk00000003/sig00000e4a ; + wire \blk00000003/sig00000e49 ; + wire \blk00000003/sig00000e48 ; + wire \blk00000003/sig00000e47 ; + wire \blk00000003/sig00000e46 ; + wire \blk00000003/sig00000e45 ; + wire \blk00000003/sig00000e44 ; + wire \blk00000003/sig00000e43 ; + wire \blk00000003/sig00000e42 ; + wire \blk00000003/sig00000e41 ; + wire \blk00000003/sig00000e40 ; + wire \blk00000003/sig00000e3f ; + wire \blk00000003/sig00000e3e ; + wire \blk00000003/sig00000e3d ; + wire \blk00000003/sig00000e3c ; + wire \blk00000003/sig00000e3b ; + wire \blk00000003/sig00000e3a ; + wire \blk00000003/sig00000e39 ; + wire \blk00000003/sig00000e38 ; + wire \blk00000003/sig00000e37 ; + wire \blk00000003/sig00000e36 ; + wire \blk00000003/sig00000e35 ; + wire \blk00000003/sig00000e34 ; + wire \blk00000003/sig00000e33 ; + wire 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\NLW_blk00000003/blk00000c77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000add_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000999_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000997_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000995_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000993_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000991_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000989_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000987_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000985_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000983_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000981_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000979_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000977_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000975_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000973_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000971_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000969_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000967_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000965_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000963_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000961_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000959_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000957_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000955_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000953_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000951_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000de_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b5_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b3_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000aa_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000027_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000023_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000021_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8e ), + .Q(\blk00000003/sig00000bc2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000cc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8d ), + .Q(\blk00000003/sig00000bc1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000cc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8c ), + .Q(\blk00000003/sig00000bc0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000cbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbe ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8b ), + .Q(\blk00000003/sig00000bbf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000cbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbc ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8a ), + .Q(\blk00000003/sig00000bbe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000cbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cba ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e89 ), + .Q(\blk00000003/sig00000bbc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000cb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e88 ), + .Q(\blk00000003/sig00000bbb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000cb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e87 ), + .Q(\blk00000003/sig00000bbd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000cb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e86 ), + .Q(\blk00000003/sig00000bd2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000cb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e85 ), + .Q(\blk00000003/sig00000bd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000cb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e84 ), + .Q(\blk00000003/sig00000bd0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000caf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000caf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cae ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e83 ), + .Q(\blk00000003/sig00000bcf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000cad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cac ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e82 ), + .Q(\blk00000003/sig00000bce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000cab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000caa ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e81 ), + .Q(\blk00000003/sig00000bcd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000ca9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e80 ), + .Q(\blk00000003/sig00000bcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/sig00000e80 ), + .Q15(\NLW_blk00000003/blk00000ca7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e7f ), + .Q(\blk00000003/sig00000bcc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/sig00000e7f ), + .Q15(\NLW_blk00000003/blk00000ca5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca4 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7e ), + .Q(\blk00000003/sig00000ad6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig00000e7e ), + .Q15(\NLW_blk00000003/blk00000ca3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca2 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7d ), + .Q(\blk00000003/sig00000ad5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig00000e7d ), + .Q15(\NLW_blk00000003/blk00000ca1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca0 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7c ), + .Q(\blk00000003/sig00000ad4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig00000e7c ), + .Q15(\NLW_blk00000003/blk00000c9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7b ), + .Q(\blk00000003/sig00000ad3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig00000e7b ), + .Q15(\NLW_blk00000003/blk00000c9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7a ), + .Q(\blk00000003/sig00000ad1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig00000e7a ), + .Q15(\NLW_blk00000003/blk00000c9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e79 ), + .Q(\blk00000003/sig00000ad0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c99 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig00000e79 ), + .Q15(\NLW_blk00000003/blk00000c99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c98 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e78 ), + .Q(\blk00000003/sig00000ad2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c97 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig00000e78 ), + .Q15(\NLW_blk00000003/blk00000c97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c96 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e77 ), + .Q(\blk00000003/sig00000acf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c95 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig00000e77 ), + .Q15(\NLW_blk00000003/blk00000c95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c94 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e76 ), + .Q(\blk00000003/sig00000ace ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c93 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig00000e76 ), + .Q15(\NLW_blk00000003/blk00000c93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c92 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e75 ), + .Q(\blk00000003/sig00000acd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c91 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig00000e75 ), + .Q15(\NLW_blk00000003/blk00000c91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c90 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e74 ), + .Q(\blk00000003/sig00000acc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000e74 ), + .Q15(\NLW_blk00000003/blk00000c8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e73 ), + .Q(\blk00000003/sig00000aca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000e73 ), + .Q15(\NLW_blk00000003/blk00000c8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e72 ), + .Q(\blk00000003/sig00000ac9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000e72 ), + .Q15(\NLW_blk00000003/blk00000c8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e71 ), + .Q(\blk00000003/sig00000acb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c89 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig00000e71 ), + .Q15(\NLW_blk00000003/blk00000c89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c88 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e70 ), + .Q(\blk00000003/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c87 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000e70 ), + .Q15(\NLW_blk00000003/blk00000c87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c86 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e6f ), + .Q(\blk00000003/sig00000ac8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c85 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000e6f ), + .Q15(\NLW_blk00000003/blk00000c85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c84 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6e ), + .Q(\blk00000003/sig00000af5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c83 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig00000e6e ), + .Q15(\NLW_blk00000003/blk00000c83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c82 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6d ), + .Q(\blk00000003/sig00000af4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c81 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig00000e6d ), + .Q15(\NLW_blk00000003/blk00000c81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c80 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6c ), + .Q(\blk00000003/sig00000af6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig00000e6c ), + .Q15(\NLW_blk00000003/blk00000c7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6b ), + .Q(\blk00000003/sig00000af3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000c7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6a ), + .Q(\blk00000003/sig00000af2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000c7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e69 ), + .Q(\blk00000003/sig00000af1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000c79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c78 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e68 ), + .Q(\blk00000003/sig00000af0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000c77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c76 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e67 ), + .Q(\blk00000003/sig00000aee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000c75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c74 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e66 ), + .Q(\blk00000003/sig00000aed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000c73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c72 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e65 ), + .Q(\blk00000003/sig00000aef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000c71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c70 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e64 ), + .Q(\blk00000003/sig00000aec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000c6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e63 ), + .Q(\blk00000003/sig00000aeb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig00000e63 ), + .Q15(\NLW_blk00000003/blk00000c6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e62 ), + .Q(\blk00000003/sig00000aea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig00000e62 ), + .Q15(\NLW_blk00000003/blk00000c6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e61 ), + .Q(\blk00000003/sig00000ae9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig00000e61 ), + .Q15(\NLW_blk00000003/blk00000c69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c68 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e60 ), + .Q(\blk00000003/sig00000ae7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig00000e60 ), + .Q15(\NLW_blk00000003/blk00000c67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c66 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e5f ), + .Q(\blk00000003/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig00000e5f ), + .Q15(\NLW_blk00000003/blk00000c65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c64 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5e ), + .Q(\blk00000003/sig00000baa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/sig00000e5e ), + .Q15(\NLW_blk00000003/blk00000c63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c62 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5d ), + .Q(\blk00000003/sig00000ba9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/sig00000e5d ), + .Q15(\NLW_blk00000003/blk00000c61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c60 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5c ), + .Q(\blk00000003/sig00000ba8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/sig00000e5c ), + .Q15(\NLW_blk00000003/blk00000c5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5b ), + .Q(\blk00000003/sig00000ba7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/sig00000e5b ), + .Q15(\NLW_blk00000003/blk00000c5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5a ), + .Q(\blk00000003/sig00000ba5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/sig00000e5a ), + .Q15(\NLW_blk00000003/blk00000c5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e59 ), + .Q(\blk00000003/sig00000ba4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/sig00000e59 ), + .Q15(\NLW_blk00000003/blk00000c59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c58 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e58 ), + .Q(\blk00000003/sig00000ba6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/sig00000e58 ), + .Q15(\NLW_blk00000003/blk00000c57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c56 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e57 ), + .Q(\blk00000003/sig00000ba3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/sig00000e57 ), + .Q15(\NLW_blk00000003/blk00000c55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c54 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e56 ), + .Q(\blk00000003/sig00000bb2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/sig00000e56 ), + .Q15(\NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c52 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e55 ), + .Q(\blk00000003/sig00000bb1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/sig00000e55 ), + .Q15(\NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e54 ), + .Q(\blk00000003/sig00000bb0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/sig00000e54 ), + .Q15(\NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e53 ), + .Q(\blk00000003/sig00000baf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/sig00000e53 ), + .Q15(\NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e52 ), + .Q(\blk00000003/sig00000bae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/sig00000e52 ), + .Q15(\NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e51 ), + .Q(\blk00000003/sig00000bac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/sig00000e51 ), + .Q15(\NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c48 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e50 ), + .Q(\blk00000003/sig00000bab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/sig00000e50 ), + .Q15(\NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c46 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e4f ), + .Q(\blk00000003/sig00000bad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/sig00000e4f ), + .Q15(\NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c44 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4e ), + .Q(\blk00000003/sig00000aa6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000e4e ), + .Q15(\NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c42 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4d ), + .Q(\blk00000003/sig00000aa4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000e4d ), + .Q15(\NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c40 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4c ), + .Q(\blk00000003/sig00000aa3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000e4c ), + .Q15(\NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4b ), + .Q(\blk00000003/sig00000aa5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000e4b ), + .Q15(\NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4a ), + .Q(\blk00000003/sig00000aa2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e49 ), + .Q(\blk00000003/sig00000aa1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c38 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e48 ), + .Q(\blk00000003/sig00000aa0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c36 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e47 ), + .Q(\blk00000003/sig00000a9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c34 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e46 ), + .Q(\blk00000003/sig00000a9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c32 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e45 ), + .Q(\blk00000003/sig00000a9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c30 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e44 ), + .Q(\blk00000003/sig00000a9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e43 ), + .Q(\blk00000003/sig00000a9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e42 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e41 ), + .Q(\blk00000003/sig00000a99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c28 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e40 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c26 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e3f ), + .Q(\blk00000003/sig00000a97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c24 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3e ), + .Q(\blk00000003/sig00000ab6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c22 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3d ), + .Q(\blk00000003/sig00000ab5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c20 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3c ), + .Q(\blk00000003/sig00000ab4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3b ), + .Q(\blk00000003/sig00000ab3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3a ), + .Q(\blk00000003/sig00000ab2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e39 ), + .Q(\blk00000003/sig00000ab0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c18 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e38 ), + .Q(\blk00000003/sig00000aaf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c16 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e37 ), + .Q(\blk00000003/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c14 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e36 ), + .Q(\blk00000003/sig00000aae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c12 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e35 ), + .Q(\blk00000003/sig00000aad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e34 ), + .Q(\blk00000003/sig00000aac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e33 ), + .Q(\blk00000003/sig00000aab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e32 ), + .Q(\blk00000003/sig00000aa9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000e32 ), + .Q15(\NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e31 ), + .Q(\blk00000003/sig00000aa8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000e31 ), + .Q15(\NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c08 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e30 ), + .Q(\blk00000003/sig00000aaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000e30 ), + .Q15(\NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c06 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e2f ), + .Q(\blk00000003/sig00000aa7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000e2f ), + .Q15(\NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000e2e ), + .Q(\blk00000003/sig00000c61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c03 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig00000e2e ), + .Q15(\NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c02 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2d ), + .Q(\blk00000003/sig00000b9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig00000e2d ), + .Q15(\NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c00 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2c ), + .Q(\blk00000003/sig00000b99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig00000e2c ), + .Q15(\NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfe ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2b ), + .Q(\blk00000003/sig00000b97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000e2b ), + .Q15(\NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfc ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2a ), + .Q(\blk00000003/sig00000b96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000e2a ), + .Q15(\NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfa ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e29 ), + .Q(\blk00000003/sig00000b98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig00000e29 ), + .Q15(\NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e28 ), + .Q(\blk00000003/sig00000b95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig00000e28 ), + .Q15(\NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e27 ), + .Q(\blk00000003/sig00000b94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000e27 ), + .Q15(\NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e26 ), + .Q(\blk00000003/sig00000b93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000e26 ), + .Q15(\NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf2 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e25 ), + .Q(\blk00000003/sig00000ba2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/sig00000e25 ), + .Q15(\NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf0 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e24 ), + .Q(\blk00000003/sig00000ba1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/sig00000e24 ), + .Q15(\NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bee ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e23 ), + .Q(\blk00000003/sig00000ba0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/sig00000e23 ), + .Q15(\NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bec ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e22 ), + .Q(\blk00000003/sig00000b9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000beb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/sig00000e22 ), + .Q15(\NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bea ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e21 ), + .Q(\blk00000003/sig00000b9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000e21 ), + .Q15(\NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e20 ), + .Q(\blk00000003/sig00000b9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig00000e20 ), + .Q15(\NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1f ), + .Q(\blk00000003/sig00000b9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000e1f ), + .Q15(\NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1e ), + .Q(\blk00000003/sig00000b9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig00000e1e ), + .Q15(\NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1d ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000e1d ), + .Q15(\NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1c ), + .Q(\blk00000003/sig00000a85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000e1c ), + .Q15(\NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bde ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1b ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000e1b ), + .Q15(\NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1a ), + .Q(\blk00000003/sig00000a83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000e1a ), + .Q15(\NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bda ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e19 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000e19 ), + .Q15(\NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e18 ), + .Q(\blk00000003/sig00000a81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000e18 ), + .Q15(\NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e17 ), + .Q(\blk00000003/sig00000a7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000e17 ), + .Q15(\NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e16 ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000e16 ), + .Q15(\NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e15 ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000e15 ), + .Q15(\NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e14 ), + .Q(\blk00000003/sig00000a7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000e14 ), + .Q15(\NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bce ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e13 ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000e13 ), + .Q15(\NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e12 ), + .Q(\blk00000003/sig00000a7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000e12 ), + .Q15(\NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bca ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e11 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000e11 ), + .Q15(\NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e10 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000e10 ), + .Q15(\NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0f ), + .Q(\blk00000003/sig00000a77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000e0f ), + .Q15(\NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0e ), + .Q(\blk00000003/sig00000a79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000e0e ), + .Q15(\NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0d ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000e0d ), + .Q15(\NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0c ), + .Q(\blk00000003/sig00000a95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000e0c ), + .Q15(\NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbe ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0b ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000e0b ), + .Q15(\NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbc ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0a ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000e0a ), + .Q15(\NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bba ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e09 ), + .Q(\blk00000003/sig00000a91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000e09 ), + .Q15(\NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e08 ), + .Q(\blk00000003/sig00000a93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000e08 ), + .Q15(\NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e07 ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000e07 ), + .Q15(\NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e06 ), + .Q(\blk00000003/sig00000a8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000e06 ), + .Q15(\NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e05 ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000e05 ), + .Q15(\NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e04 ), + .Q(\blk00000003/sig00000a8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000e04 ), + .Q15(\NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bae ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e03 ), + .Q(\blk00000003/sig00000a8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000e03 ), + .Q15(\NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bac ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e02 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000e02 ), + .Q15(\NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baa ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e01 ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000e01 ), + .Q15(\NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e00 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000e00 ), + .Q15(\NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dff ), + .Q(\blk00000003/sig00000a87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000dff ), + .Q15(\NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dfe ), + .Q(\blk00000003/sig00000a89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000dfe ), + .Q15(\NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfd ), + .Q(\blk00000003/sig000002ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig00000dfd ), + .Q15(\NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfc ), + .Q(\blk00000003/sig00000258 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d98 ), + .Q(\blk00000003/sig00000dfc ), + .Q15(\NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfb ), + .Q(\blk00000003/sig00000257 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d96 ), + .Q(\blk00000003/sig00000dfb ), + .Q15(\NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfa ), + .Q(\blk00000003/sig00000259 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d9a ), + .Q(\blk00000003/sig00000dfa ), + .Q15(\NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df9 ), + .Q(\blk00000003/sig00000255 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b99 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8e ), + .Q(\blk00000003/sig00000df9 ), + .Q15(\NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b98 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df8 ), + .Q(\blk00000003/sig00000254 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b97 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d92 ), + .Q(\blk00000003/sig00000df8 ), + .Q15(\NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b96 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df7 ), + .Q(\blk00000003/sig00000256 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b95 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d94 ), + .Q(\blk00000003/sig00000df7 ), + .Q15(\NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b94 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df6 ), + .Q(\blk00000003/sig00000253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b93 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d90 ), + .Q(\blk00000003/sig00000df6 ), + .Q15(\NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b92 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df5 ), + .Q(\blk00000003/sig00000252 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b91 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8c ), + .Q(\blk00000003/sig00000df5 ), + .Q15(\NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b90 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df4 ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8a ), + .Q(\blk00000003/sig00000df4 ), + .Q15(\NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df3 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d88 ), + .Q(\blk00000003/sig00000df3 ), + .Q15(\NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df2 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d80 ), + .Q(\blk00000003/sig00000df2 ), + .Q15(\NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df1 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b89 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d84 ), + .Q(\blk00000003/sig00000df1 ), + .Q15(\NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b88 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df0 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b87 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d86 ), + .Q(\blk00000003/sig00000df0 ), + .Q15(\NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b86 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000def ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b85 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d82 ), + .Q(\blk00000003/sig00000def ), + .Q15(\NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b84 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dee ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b83 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7e ), + .Q(\blk00000003/sig00000dee ), + .Q15(\NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b82 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ded ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b81 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7c ), + .Q(\blk00000003/sig00000ded ), + .Q15(\NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b80 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dec ), + .Q(\blk00000003/sig00000219 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7a ), + .Q(\blk00000003/sig00000dec ), + .Q15(\NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000deb ), + .Q(\blk00000003/sig00000217 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d72 ), + .Q(\blk00000003/sig00000deb ), + .Q15(\NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dea ), + .Q(\blk00000003/sig00000216 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d76 ), + .Q(\blk00000003/sig00000dea ), + .Q15(\NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de9 ), + .Q(\blk00000003/sig00000218 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b79 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d78 ), + .Q(\blk00000003/sig00000de9 ), + .Q15(\NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b78 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de8 ), + .Q(\blk00000003/sig00000215 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b77 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d74 ), + .Q(\blk00000003/sig00000de8 ), + .Q15(\NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b76 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de7 ), + .Q(\blk00000003/sig00000214 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b75 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d70 ), + .Q(\blk00000003/sig00000de7 ), + .Q15(\NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b74 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de6 ), + .Q(\blk00000003/sig00000213 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b73 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6e ), + .Q(\blk00000003/sig00000de6 ), + .Q15(\NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b72 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de5 ), + .Q(\blk00000003/sig00000212 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b71 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6c ), + .Q(\blk00000003/sig00000de5 ), + .Q15(\NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b70 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de4 ), + .Q(\blk00000003/sig000001d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d64 ), + .Q(\blk00000003/sig00000de4 ), + .Q15(\NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de3 ), + .Q(\blk00000003/sig000001cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d68 ), + .Q(\blk00000003/sig00000de3 ), + .Q15(\NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de2 ), + .Q(\blk00000003/sig000001d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6a ), + .Q(\blk00000003/sig00000de2 ), + .Q15(\NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de1 ), + .Q(\blk00000003/sig000001ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b69 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d66 ), + .Q(\blk00000003/sig00000de1 ), + .Q15(\NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b68 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de0 ), + .Q(\blk00000003/sig000001cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b67 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d62 ), + .Q(\blk00000003/sig00000de0 ), + .Q15(\NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b66 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddf ), + .Q(\blk00000003/sig000001cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b65 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d60 ), + .Q(\blk00000003/sig00000ddf ), + .Q15(\NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b64 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dde ), + .Q(\blk00000003/sig000001cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b63 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5e ), + .Q(\blk00000003/sig00000dde ), + .Q15(\NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b62 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddd ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b61 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d56 ), + .Q(\blk00000003/sig00000ddd ), + .Q15(\NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b60 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5a ), + .Q(\blk00000003/sig00000ddc ), + .Q15(\NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddb ), + .Q(\blk00000003/sig000001ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5c ), + .Q(\blk00000003/sig00000ddb ), + .Q15(\NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dda ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d58 ), + .Q(\blk00000003/sig00000dda ), + .Q15(\NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd9 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b59 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d54 ), + .Q(\blk00000003/sig00000dd9 ), + .Q15(\NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd8 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b57 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d52 ), + .Q(\blk00000003/sig00000dd8 ), + .Q15(\NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd7 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b55 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d50 ), + .Q(\blk00000003/sig00000dd7 ), + .Q15(\NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b53 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d48 ), + .Q(\blk00000003/sig00000dd6 ), + .Q15(\NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd5 ), + .Q(\blk00000003/sig0000017f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b51 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4c ), + .Q(\blk00000003/sig00000dd5 ), + .Q15(\NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4e ), + .Q(\blk00000003/sig00000dd4 ), + .Q15(\NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd3 ), + .Q(\blk00000003/sig0000017e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4a ), + .Q(\blk00000003/sig00000dd3 ), + .Q15(\NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd2 ), + .Q(\blk00000003/sig0000017d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d46 ), + .Q(\blk00000003/sig00000dd2 ), + .Q15(\NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd1 ), + .Q(\blk00000003/sig0000017c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b49 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d44 ), + .Q(\blk00000003/sig00000dd1 ), + .Q15(\NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd0 ), + .Q(\blk00000003/sig0000017b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b47 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d42 ), + .Q(\blk00000003/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcf ), + .Q(\blk00000003/sig00000179 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b45 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3c ), + .Q(\blk00000003/sig00000dcf ), + .Q15(\NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dce ), + .Q(\blk00000003/sig00000178 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b43 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3e ), + .Q(\blk00000003/sig00000dce ), + .Q15(\NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcd ), + .Q(\blk00000003/sig0000017a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b41 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d40 ), + .Q(\blk00000003/sig00000dcd ), + .Q15(\NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b40 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcc ), + .Q(\blk00000003/sig00000b8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig00000dcc ), + .Q15(\NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcb ), + .Q(\blk00000003/sig00000b88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig00000dcb ), + .Q15(\NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dca ), + .Q(\blk00000003/sig00000b87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig00000dca ), + .Q15(\NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc9 ), + .Q(\blk00000003/sig00000b89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b38 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc8 ), + .Q(\blk00000003/sig00000b86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig00000dc8 ), + .Q15(\NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b36 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc7 ), + .Q(\blk00000003/sig00000b85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig00000dc7 ), + .Q15(\NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b34 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc6 ), + .Q(\blk00000003/sig00000b84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig00000dc6 ), + .Q15(\NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b32 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc5 ), + .Q(\blk00000003/sig00000b83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig00000dc5 ), + .Q15(\NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b30 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc4 ), + .Q(\blk00000003/sig00000b92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000dc4 ), + .Q15(\NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc3 ), + .Q(\blk00000003/sig00000b91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000dc3 ), + .Q15(\NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc2 ), + .Q(\blk00000003/sig00000b90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000dc2 ), + .Q15(\NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc1 ), + .Q(\blk00000003/sig00000b8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000dc1 ), + .Q15(\NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b28 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc0 ), + .Q(\blk00000003/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig00000dc0 ), + .Q15(\NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b26 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbf ), + .Q(\blk00000003/sig00000b8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000dbf ), + .Q15(\NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b24 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbe ), + .Q(\blk00000003/sig00000b8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000dbe ), + .Q15(\NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b22 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbd ), + .Q(\blk00000003/sig00000b8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig00000dbd ), + .Q15(\NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b20 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbc ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000dbc ), + .Q15(\NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbb ), + .Q(\blk00000003/sig00000a65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000dbb ), + .Q15(\NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dba ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000dba ), + .Q15(\NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db9 ), + .Q(\blk00000003/sig00000a63 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000db9 ), + .Q15(\NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b18 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db8 ), + .Q(\blk00000003/sig00000a61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000db8 ), + .Q15(\NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b16 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db7 ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000db7 ), + .Q15(\NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b14 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db6 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000db6 ), + .Q15(\NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b12 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db5 ), + .Q(\blk00000003/sig00000a5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000db5 ), + .Q15(\NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b10 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db4 ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000db4 ), + .Q15(\NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db3 ), + .Q(\blk00000003/sig00000a5d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000db3 ), + .Q15(\NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db2 ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000db2 ), + .Q15(\NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db1 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig00000db1 ), + .Q15(\NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b08 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db0 ), + .Q(\blk00000003/sig00000a59 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig00000db0 ), + .Q15(\NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b06 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000daf ), + .Q(\blk00000003/sig00000a5b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000daf ), + .Q15(\NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b04 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dae ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig00000dae ), + .Q15(\NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b02 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dad ), + .Q(\blk00000003/sig00000a57 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig00000dad ), + .Q15(\NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b00 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dac ), + .Q(\blk00000003/sig00000a75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000dac ), + .Q15(\NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afe ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dab ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000dab ), + .Q15(\NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afc ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000daa ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000daa ), + .Q15(\NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afa ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da9 ), + .Q(\blk00000003/sig00000a73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000da9 ), + .Q15(\NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da8 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000da8 ), + .Q15(\NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da7 ), + .Q(\blk00000003/sig00000a71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000da7 ), + .Q15(\NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da6 ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000da6 ), + .Q15(\NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da5 ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000da5 ), + .Q15(\NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af0 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da4 ), + .Q(\blk00000003/sig00000a6d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000da4 ), + .Q15(\NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aee ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da3 ), + .Q(\blk00000003/sig00000a6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000da3 ), + .Q15(\NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aec ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da2 ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aeb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000da2 ), + .Q15(\NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aea ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da1 ), + .Q(\blk00000003/sig00000a6b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000da1 ), + .Q15(\NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da0 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000da0 ), + .Q15(\NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9f ), + .Q(\blk00000003/sig00000a69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000d9f ), + .Q15(\NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9e ), + .Q(\blk00000003/sig00000a67 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000d9e ), + .Q15(\NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9d ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000d9d ), + .Q15(\NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9c ), + .Q(\blk00000003/sig00000a16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002af ), + .Q(\blk00000003/sig00000d9c ), + .Q15(\NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ade ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9b ), + .Q(\blk00000003/sig00000c62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000add ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029c ), + .Q(\blk00000003/sig00000d9b ), + .Q15(\NLW_blk00000003/blk00000add_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d99 ), + .Q(\blk00000003/sig00000d9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000d99 ), + .Q15(\NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ada ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d97 ), + .Q(\blk00000003/sig00000d98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000d97 ), + .Q15(\NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d95 ), + .Q(\blk00000003/sig00000d96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000d95 ), + .Q15(\NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d93 ), + .Q(\blk00000003/sig00000d94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000d93 ), + .Q15(\NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d91 ), + .Q(\blk00000003/sig00000d92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000d91 ), + .Q15(\NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8f ), + .Q(\blk00000003/sig00000d90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000d8f ), + .Q15(\NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8d ), + .Q(\blk00000003/sig00000d8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000d8d ), + .Q15(\NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ace ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8b ), + .Q(\blk00000003/sig00000d8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000d8b ), + .Q15(\NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d89 ), + .Q(\blk00000003/sig00000d8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000d89 ), + .Q15(\NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aca ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d87 ), + .Q(\blk00000003/sig00000d88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000d87 ), + .Q15(\NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d85 ), + .Q(\blk00000003/sig00000d86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000d85 ), + .Q15(\NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d83 ), + .Q(\blk00000003/sig00000d84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000d83 ), + .Q15(\NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d81 ), + .Q(\blk00000003/sig00000d82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000d81 ), + .Q15(\NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7f ), + .Q(\blk00000003/sig00000d80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000d7f ), + .Q15(\NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7d ), + .Q(\blk00000003/sig00000d7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000d7d ), + .Q15(\NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abe ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7b ), + .Q(\blk00000003/sig00000d7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000d7b ), + .Q15(\NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d79 ), + .Q(\blk00000003/sig00000d7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000d79 ), + .Q15(\NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aba ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d77 ), + .Q(\blk00000003/sig00000d78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000d77 ), + .Q15(\NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d75 ), + .Q(\blk00000003/sig00000d76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000d75 ), + .Q15(\NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d73 ), + .Q(\blk00000003/sig00000d74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000d73 ), + .Q15(\NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d71 ), + .Q(\blk00000003/sig00000d72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000d71 ), + .Q15(\NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6f ), + .Q(\blk00000003/sig00000d70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000d6f ), + .Q15(\NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6d ), + .Q(\blk00000003/sig00000d6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000d6d ), + .Q15(\NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aae ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6b ), + .Q(\blk00000003/sig00000d6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aad ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000d6b ), + .Q15(\NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aac ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d69 ), + .Q(\blk00000003/sig00000d6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aab ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000d69 ), + .Q15(\NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaa ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d67 ), + .Q(\blk00000003/sig00000d68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000d67 ), + .Q15(\NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d65 ), + .Q(\blk00000003/sig00000d66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000d65 ), + .Q15(\NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d63 ), + .Q(\blk00000003/sig00000d64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000d63 ), + .Q15(\NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d61 ), + .Q(\blk00000003/sig00000d62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000d61 ), + .Q15(\NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5f ), + .Q(\blk00000003/sig00000d60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000d5f ), + .Q15(\NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5d ), + .Q(\blk00000003/sig00000d5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000d5d ), + .Q15(\NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5b ), + .Q(\blk00000003/sig00000d5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000d5b ), + .Q15(\NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d59 ), + .Q(\blk00000003/sig00000d5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000d59 ), + .Q15(\NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d57 ), + .Q(\blk00000003/sig00000d58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a99 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000d57 ), + .Q15(\NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a98 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d55 ), + .Q(\blk00000003/sig00000d56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a97 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000d55 ), + .Q15(\NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a96 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d53 ), + .Q(\blk00000003/sig00000d54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a95 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000d53 ), + .Q15(\NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a94 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d51 ), + .Q(\blk00000003/sig00000d52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a93 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000d51 ), + .Q15(\NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a92 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4f ), + .Q(\blk00000003/sig00000d50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000d4f ), + .Q15(\NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a90 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4d ), + .Q(\blk00000003/sig00000d4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000d4d ), + .Q15(\NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4b ), + .Q(\blk00000003/sig00000d4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000d4b ), + .Q15(\NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d49 ), + .Q(\blk00000003/sig00000d4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000d49 ), + .Q15(\NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d47 ), + .Q(\blk00000003/sig00000d48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a89 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000d47 ), + .Q15(\NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a88 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d45 ), + .Q(\blk00000003/sig00000d46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a87 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000d45 ), + .Q15(\NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a86 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d43 ), + .Q(\blk00000003/sig00000d44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a85 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000d43 ), + .Q15(\NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a84 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d41 ), + .Q(\blk00000003/sig00000d42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a83 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000d41 ), + .Q15(\NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a82 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3f ), + .Q(\blk00000003/sig00000d40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a81 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000d3f ), + .Q15(\NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a80 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3d ), + .Q(\blk00000003/sig00000d3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000d3d ), + .Q15(\NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3b ), + .Q(\blk00000003/sig00000d3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000d3b ), + .Q15(\NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d3a ), + .Q(\blk00000003/sig00000b79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig00000d3a ), + .Q15(\NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d39 ), + .Q(\blk00000003/sig00000b78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig00000d39 ), + .Q15(\NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a78 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d38 ), + .Q(\blk00000003/sig00000b7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig00000d38 ), + .Q15(\NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a76 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d37 ), + .Q(\blk00000003/sig00000b77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig00000d37 ), + .Q15(\NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a74 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d36 ), + .Q(\blk00000003/sig00000b76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig00000d36 ), + .Q15(\NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a72 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d35 ), + .Q(\blk00000003/sig00000b75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig00000d35 ), + .Q15(\NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a70 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d34 ), + .Q(\blk00000003/sig00000b74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig00000d34 ), + .Q15(\NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d33 ), + .Q(\blk00000003/sig00000b73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig00000d33 ), + .Q15(\NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d32 ), + .Q(\blk00000003/sig00000b82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig00000d32 ), + .Q15(\NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d31 ), + .Q(\blk00000003/sig00000b81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig00000d31 ), + .Q15(\NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a68 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d30 ), + .Q(\blk00000003/sig00000b7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig00000d30 ), + .Q15(\NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a66 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2f ), + .Q(\blk00000003/sig00000b7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig00000d2f ), + .Q15(\NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a64 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2e ), + .Q(\blk00000003/sig00000b80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig00000d2e ), + .Q15(\NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a62 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2d ), + .Q(\blk00000003/sig00000b7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig00000d2d ), + .Q15(\NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a60 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2c ), + .Q(\blk00000003/sig00000b7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig00000d2c ), + .Q15(\NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2b ), + .Q(\blk00000003/sig00000b7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig00000d2b ), + .Q15(\NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d2a ), + .Q(\blk00000003/sig00000c6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000299 ), + .Q(\blk00000003/sig00000d2a ), + .Q15(\NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d29 ), + .Q(\blk00000003/sig00000c6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000297 ), + .Q(\blk00000003/sig00000d29 ), + .Q15(\NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d28 ), + .Q(\blk00000003/sig00000c71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000296 ), + .Q(\blk00000003/sig00000d28 ), + .Q15(\NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d27 ), + .Q(\blk00000003/sig00000c70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000298 ), + .Q(\blk00000003/sig00000d27 ), + .Q15(\NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d26 ), + .Q(\blk00000003/sig00000c73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000295 ), + .Q(\blk00000003/sig00000d26 ), + .Q15(\NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d25 ), + .Q(\blk00000003/sig00000c72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig00000d25 ), + .Q15(\NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d24 ), + .Q(\blk00000003/sig00000c74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000293 ), + .Q(\blk00000003/sig00000d24 ), + .Q15(\NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d23 ), + .Q(\blk00000003/sig00000c76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000292 ), + .Q(\blk00000003/sig00000d23 ), + .Q15(\NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d22 ), + .Q(\blk00000003/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000d22 ), + .Q15(\NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d21 ), + .Q(\blk00000003/sig00000c79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000d21 ), + .Q15(\NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d20 ), + .Q(\blk00000003/sig00000c75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000d20 ), + .Q15(\NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1f ), + .Q(\blk00000003/sig00000c78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000d1f ), + .Q15(\NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1e ), + .Q(\blk00000003/sig00000c7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000d1e ), + .Q15(\NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1d ), + .Q(\blk00000003/sig00000c7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000d1d ), + .Q15(\NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a40 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1c ), + .Q(\blk00000003/sig00000c7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000d1c ), + .Q15(\NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1b ), + .Q(\blk00000003/sig00000c7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000d1b ), + .Q15(\NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1a ), + .Q(\blk00000003/sig00000c7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000d1a ), + .Q15(\NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d19 ), + .Q(\blk00000003/sig00000c7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000d19 ), + .Q15(\NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a38 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d18 ), + .Q(\blk00000003/sig00000c80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000d18 ), + .Q15(\NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a36 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d17 ), + .Q(\blk00000003/sig00000c82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000d17 ), + .Q15(\NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a34 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d16 ), + .Q(\blk00000003/sig00000c81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000d16 ), + .Q15(\NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a32 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d15 ), + .Q(\blk00000003/sig00000c83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000d15 ), + .Q15(\NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a30 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d14 ), + .Q(\blk00000003/sig00000c84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000d14 ), + .Q15(\NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d13 ), + .Q(\blk00000003/sig00000c86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000d13 ), + .Q15(\NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d12 ), + .Q(\blk00000003/sig00000c85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d11 ), + .Q(\blk00000003/sig00000c88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a28 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d10 ), + .Q(\blk00000003/sig00000c87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a26 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0f ), + .Q(\blk00000003/sig00000c89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a24 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0e ), + .Q(\blk00000003/sig00000c8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a22 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0d ), + .Q(\blk00000003/sig00000c8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a20 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0c ), + .Q(\blk00000003/sig00000c8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0b ), + .Q(\blk00000003/sig00000c8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d0a ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d09 ), + .Q(\blk00000003/sig00000a45 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a18 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d08 ), + .Q(\blk00000003/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a16 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d07 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a14 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d06 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a12 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d05 ), + .Q(\blk00000003/sig00000a41 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a10 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d04 ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0e ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d03 ), + .Q(\blk00000003/sig00000a3f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d02 ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d01 ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a08 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d00 ), + .Q(\blk00000003/sig00000a3b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a06 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cff ), + .Q(\blk00000003/sig00000a3d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a04 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfe ), + .Q(\blk00000003/sig00000a3a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a02 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfd ), + .Q(\blk00000003/sig00000a39 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a00 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfc ), + .Q(\blk00000003/sig00000a38 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig00000cfc ), + .Q15(\NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fe ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfb ), + .Q(\blk00000003/sig00000a37 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig00000cfb ), + .Q15(\NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fc ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cfa ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig00000cfa ), + .Q15(\NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fa ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf9 ), + .Q(\blk00000003/sig00000a55 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig00000cf9 ), + .Q15(\NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf8 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig00000cf8 ), + .Q15(\NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf7 ), + .Q(\blk00000003/sig00000a53 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig00000cf7 ), + .Q15(\NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf6 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig00000cf6 ), + .Q15(\NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf5 ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig00000cf5 ), + .Q15(\NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf4 ), + .Q(\blk00000003/sig00000a4f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig00000cf4 ), + .Q15(\NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ee ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf3 ), + .Q(\blk00000003/sig00000a51 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig00000cf3 ), + .Q15(\NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ec ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf2 ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig00000cf2 ), + .Q15(\NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ea ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf1 ), + .Q(\blk00000003/sig00000a4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig00000cf1 ), + .Q15(\NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf0 ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig00000cf0 ), + .Q15(\NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cef ), + .Q(\blk00000003/sig00000a4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000cef ), + .Q15(\NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cee ), + .Q(\blk00000003/sig00000a49 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000cee ), + .Q15(\NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ced ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000ced ), + .Q15(\NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cec ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig00000cec ), + .Q15(\NLW_blk00000003/blk000009df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009de ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ceb ), + .Q(\blk00000003/sig00000a47 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000ceb ), + .Q15(\NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cea ), + .Q(\blk00000003/sig00000ac6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009db ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000cea ), + .Q15(\NLW_blk00000003/blk000009db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce9 ), + .Q(\blk00000003/sig00000ac5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000ce9 ), + .Q15(\NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce8 ), + .Q(\blk00000003/sig00000ac4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000ce8 ), + .Q15(\NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce7 ), + .Q(\blk00000003/sig00000ac2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000ce7 ), + .Q15(\NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce6 ), + .Q(\blk00000003/sig00000ac1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000ce6 ), + .Q15(\NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce5 ), + .Q(\blk00000003/sig00000ac3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000ce5 ), + .Q15(\NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce4 ), + .Q(\blk00000003/sig00000ac0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000ce4 ), + .Q15(\NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce3 ), + .Q(\blk00000003/sig00000abf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000ce3 ), + .Q15(\NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce2 ), + .Q(\blk00000003/sig00000abe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000ce2 ), + .Q15(\NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce1 ), + .Q(\blk00000003/sig00000abd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000ce1 ), + .Q15(\NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce0 ), + .Q(\blk00000003/sig00000abb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000ce0 ), + .Q15(\NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdf ), + .Q(\blk00000003/sig00000aba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000cdf ), + .Q15(\NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cde ), + .Q(\blk00000003/sig00000abc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000cde ), + .Q15(\NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdd ), + .Q(\blk00000003/sig00000ab9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000cdd ), + .Q15(\NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdc ), + .Q(\blk00000003/sig00000ab8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000cdc ), + .Q15(\NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdb ), + .Q(\blk00000003/sig00000ab7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000cdb ), + .Q15(\NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cda ), + .Q(\blk00000003/sig00000bba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000cda ), + .Q15(\NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd9 ), + .Q(\blk00000003/sig00000bb8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000cd9 ), + .Q15(\NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd8 ), + .Q(\blk00000003/sig00000bb7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000cd8 ), + .Q15(\NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd7 ), + .Q(\blk00000003/sig00000bb9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000cd7 ), + .Q15(\NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd6 ), + .Q(\blk00000003/sig00000bb6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000cd6 ), + .Q15(\NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd5 ), + .Q(\blk00000003/sig00000bb5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000cd5 ), + .Q15(\NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd4 ), + .Q(\blk00000003/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009af ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000cd4 ), + .Q15(\NLW_blk00000003/blk000009af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd3 ), + .Q(\blk00000003/sig00000bb3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ad ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000cd3 ), + .Q15(\NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd2 ), + .Q(\blk00000003/sig00000ae5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ab ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000cd2 ), + .Q15(\NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd1 ), + .Q(\blk00000003/sig00000ae4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000cd1 ), + .Q15(\NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd0 ), + .Q(\blk00000003/sig00000ae6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000cd0 ), + .Q15(\NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccf ), + .Q(\blk00000003/sig00000ae3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000ccf ), + .Q15(\NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cce ), + .Q(\blk00000003/sig00000ae2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000cce ), + .Q15(\NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccd ), + .Q(\blk00000003/sig00000ae1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000ccd ), + .Q15(\NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccc ), + .Q(\blk00000003/sig00000ae0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000ccc ), + .Q15(\NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccb ), + .Q(\blk00000003/sig00000ade ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000ccb ), + .Q15(\NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cca ), + .Q(\blk00000003/sig00000add ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000cca ), + .Q15(\NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc9 ), + .Q(\blk00000003/sig00000adf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000999 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000cc9 ), + .Q15(\NLW_blk00000003/blk00000999_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000998 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc8 ), + .Q(\blk00000003/sig00000adc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000997 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000cc8 ), + .Q15(\NLW_blk00000003/blk00000997_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000996 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc7 ), + .Q(\blk00000003/sig00000adb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000995 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000cc7 ), + .Q15(\NLW_blk00000003/blk00000995_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000994 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc6 ), + .Q(\blk00000003/sig00000ada ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000993 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000cc6 ), + .Q15(\NLW_blk00000003/blk00000993_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000992 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc5 ), + .Q(\blk00000003/sig00000ad9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000991 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000cc5 ), + .Q15(\NLW_blk00000003/blk00000991_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000990 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc4 ), + .Q(\blk00000003/sig00000ad7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc3 ), + .Q(\blk00000003/sig00000bca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc2 ), + .Q(\blk00000003/sig00000ad8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc1 ), + .Q(\blk00000003/sig00000bc9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000989 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000989_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000988 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc0 ), + .Q(\blk00000003/sig00000bc8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000987 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000987_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000986 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbf ), + .Q(\blk00000003/sig00000bc7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000985 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000985_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000984 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbe ), + .Q(\blk00000003/sig00000bc6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000983 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000983_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000982 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbd ), + .Q(\blk00000003/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000981 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000981_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000980 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbc ), + .Q(\blk00000003/sig00000bc3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000cbc ), + .Q15(\NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbb ), + .Q(\blk00000003/sig00000bc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000cbb ), + .Q15(\NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cba ), + .Q(\blk00000003/sig00000378 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a6 ), + .Q(\blk00000003/sig00000cba ), + .Q15(\NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb9 ), + .Q(\blk00000003/sig00000379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000979 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000373 ), + .Q(\blk00000003/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000979_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000978 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb8 ), + .Q(\blk00000003/sig00000c66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000977 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a2 ), + .Q(\blk00000003/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000977_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000976 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb7 ), + .Q(\blk00000003/sig00000b08 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000975 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000975_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000974 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb6 ), + .Q(\blk00000003/sig00000b06 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000973 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000973_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000972 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb5 ), + .Q(\blk00000003/sig00000b05 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000971 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000971_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000970 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb4 ), + .Q(\blk00000003/sig00000b07 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb3 ), + .Q(\blk00000003/sig00000b04 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb2 ), + .Q(\blk00000003/sig00000b03 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb1 ), + .Q(\blk00000003/sig00000b02 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000969 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000969_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000968 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb0 ), + .Q(\blk00000003/sig00000b01 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000967 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000967_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000966 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caf ), + .Q(\blk00000003/sig00000aff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000965 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000965_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000964 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cae ), + .Q(\blk00000003/sig00000afe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000963 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000963_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000962 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cad ), + .Q(\blk00000003/sig00000b00 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000961_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000960 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cac ), + .Q(\blk00000003/sig00000afd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000cac ), + .Q15(\NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cab ), + .Q(\blk00000003/sig00000afc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000cab ), + .Q15(\NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caa ), + .Q(\blk00000003/sig00000afb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000caa ), + .Q15(\NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca9 ), + .Q(\blk00000003/sig00000afa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000959 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000ca9 ), + .Q15(\NLW_blk00000003/blk00000959_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000958 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca8 ), + .Q(\blk00000003/sig00000af8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000957 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000ca8 ), + .Q15(\NLW_blk00000003/blk00000957_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000956 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca7 ), + .Q(\blk00000003/sig00000af7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000955 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000ca7 ), + .Q15(\NLW_blk00000003/blk00000955_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000954 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca6 ), + .Q(\blk00000003/sig00000af9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000953 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000ca6 ), + .Q15(\NLW_blk00000003/blk00000953_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000952 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca5 ), + .Q(\blk00000003/sig000002af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000951 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000ca5 ), + .Q15(\NLW_blk00000003/blk00000951_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000950 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca4 ), + .Q(\blk00000003/sig00000a15 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig00000ca4 ), + .Q15(\NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca3 ), + .Q(\blk00000003/sig00000bd5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a0 ), + .Q(\blk00000003/sig00000ca3 ), + .Q15(\NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk0000094c ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000034a ) + ); + INV \blk00000003/blk0000094b ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000306 ) + ); + INV \blk00000003/blk0000094a ( + .I(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000343 ) + ); + INV \blk00000003/blk00000949 ( + .I(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000349 ) + ); + INV \blk00000003/blk00000948 ( + .I(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig00000358 ) + ); + INV \blk00000003/blk00000947 ( + .I(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c60 ) + ); + INV \blk00000003/blk00000946 ( + .I(\blk00000003/sig0000031c ), + .O(\blk00000003/sig0000035b ) + ); + INV \blk00000003/blk00000945 ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000344 ) + ); + INV \blk00000003/blk00000944 ( + .I(\blk00000003/sig000002ee ), + .O(\blk00000003/sig0000031d ) + ); + INV \blk00000003/blk00000943 ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000304 ) + ); + INV \blk00000003/blk00000942 ( + .I(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016e ) + ); + INV \blk00000003/blk00000941 ( + .I(\blk00000003/sig00000161 ), + .O(\blk00000003/sig0000029d ) + ); + INV \blk00000003/blk00000940 ( + .I(\blk00000003/sig0000016b ), + .O(\blk00000003/sig0000016c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093f ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093e ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093c ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093b ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000ca0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093a ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c9f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000939 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000938 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000937 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000936 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000935 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c9a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000934 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c99 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000933 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000325 ), + .I2(coef_ld), + .O(\blk00000003/sig00000321 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000932 ( + .I0(\blk00000003/sig00000322 ), + .I1(\blk00000003/sig00000316 ), + .I2(\blk00000003/sig00000325 ), + .I3(coef_ld), + .I4(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000319 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000931 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000320 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000930 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig00000325 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092f ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000c90 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092e ( + .I0(\blk00000003/sig00000353 ), + .I1(ce), + .I2(\blk00000003/sig00000316 ), + .I3(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000c98 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092d ( + .I0(\blk00000003/sig0000035a ), + .I1(ce), + .I2(\blk00000003/sig00000314 ), + .I3(\blk00000003/sig0000034b ), + .O(\blk00000003/sig00000c97 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092c ( + .I0(\blk00000003/sig00000c64 ), + .I1(ce), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000c92 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092b ( + .I0(ce), + .I1(\blk00000003/sig00000325 ), + .I2(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000c8f ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk0000092a ( + .I0(\blk00000003/sig000002b3 ), + .I1(\blk00000003/sig000002a8 ), + .I2(\blk00000003/sig00000c94 ), + .I3(ce), + .O(\blk00000003/sig00000c96 ) + ); + LUT5 #( + .INIT ( 32'h7FFF8000 )) + \blk00000003/blk00000929 ( + .I0(nd), + .I1(ce), + .I2(\blk00000003/sig00000159 ), + .I3(\blk00000003/sig00000c63 ), + .I4(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000c95 ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk00000928 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig00000c94 ), + .I2(ce), + .O(\blk00000003/sig00000c93 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk00000927 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig00000159 ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig00000c91 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000926 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032a ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000925 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032d ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000924 ( + .C(clk), + .D(\blk00000003/sig00000c98 ), + .Q(\blk00000003/sig00000353 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000923 ( + .C(clk), + .D(\blk00000003/sig00000c97 ), + .Q(\blk00000003/sig0000035a ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000922 ( + .C(clk), + .D(\blk00000003/sig00000c96 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .D(\blk00000003/sig00000c95 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000920 ( + .C(clk), + .D(\blk00000003/sig00000c93 ), + .R(sclr), + .Q(\blk00000003/sig00000c94 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .D(\blk00000003/sig00000c92 ), + .R(sclr), + .Q(\blk00000003/sig00000c64 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091e ( + .C(clk), + .D(\blk00000003/sig00000c91 ), + .R(sclr), + .Q(\blk00000003/sig00000c63 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091d ( + .I0(\blk00000003/sig00000beb ), + .O(\blk00000003/sig00000be5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091c ( + .I0(\blk00000003/sig00000bea ), + .O(\blk00000003/sig00000be2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091b ( + .I0(\blk00000003/sig00000be9 ), + .O(\blk00000003/sig00000bdf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091a ( + .I0(\blk00000003/sig00000be8 ), + .O(\blk00000003/sig00000bdc ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000919 ( + .I0(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd9 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000918 ( + .I0(\blk00000003/sig00000375 ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000917 ( + .I0(\blk00000003/sig00000369 ), + .O(\blk00000003/sig00000363 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000916 ( + .I0(\blk00000003/sig00000334 ), + .O(\blk00000003/sig00000335 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000915 ( + .I0(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000914 ( + .I0(\blk00000003/sig00000c63 ), + .O(\blk00000003/sig00000160 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c5a ), + .R(sclr), + .Q(\blk00000003/sig00000c5f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000912 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c57 ), + .R(sclr), + .Q(\blk00000003/sig00000c5e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c54 ), + .R(sclr), + .Q(\blk00000003/sig00000c5d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000910 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c51 ), + .R(sclr), + .Q(\blk00000003/sig00000c5c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4e ), + .R(sclr), + .Q(\blk00000003/sig00000c5b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bd7 ), + .S(sclr), + .Q(\blk00000003/sig00000bec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be6 ), + .R(sclr), + .Q(\blk00000003/sig00000beb ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be3 ), + .S(sclr), + .Q(\blk00000003/sig00000bea ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be0 ), + .S(sclr), + .Q(\blk00000003/sig00000be9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bdd ), + .R(sclr), + .Q(\blk00000003/sig00000be8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bda ), + .S(sclr), + .Q(\blk00000003/sig00000be7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000908 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .R(\blk00000003/sig0000037a ), + .Q(\blk00000003/sig00000375 ) + ); + FDR \blk00000003/blk00000907 ( + .C(clk), + .D(\blk00000003/sig00000c90 ), + .R(ce), + .Q(\blk00000003/sig00000c67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000906 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036c ), + .S(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000904 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000364 ), + .S(sclr), + .Q(\blk00000003/sig00000369 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000367 ), + .R(sclr), + .Q(\blk00000003/sig00000368 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000902 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000035e ), + .R(sclr), + .Q(\blk00000003/sig000002ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000361 ), + .R(sclr), + .Q(\blk00000003/sig000002b9 ) + ); + FDR \blk00000003/blk00000900 ( + .C(clk), + .D(\blk00000003/sig00000c8f ), + .R(ce), + .Q(\blk00000003/sig00000c65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000336 ), + .R(\blk00000003/sig00000339 ), + .Q(\blk00000003/sig00000334 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000328 ), + .R(coef_ld), + .Q(\blk00000003/sig00000332 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032e ), + .R(coef_ld), + .Q(\blk00000003/sig00000331 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032b ), + .R(coef_ld), + .Q(\blk00000003/sig00000330 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f4 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk000008fa ( + .I0(\blk00000003/sig0000016b ), + .I1(sclr), + .O(\blk00000003/sig00000c8e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008f9 ( + .C(clk), + .D(\blk00000003/sig00000c8e ), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000163 ), + .R(sclr), + .Q(\blk00000003/sig00000161 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f7 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f6 ( + .I0(\blk00000003/sig00000c5c ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c50 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f5 ( + .I0(\blk00000003/sig00000c5d ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c53 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f4 ( + .I0(\blk00000003/sig00000c5e ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c56 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000008f3 ( + .I0(\blk00000003/sig00000c5f ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000c59 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000008f2 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000c49 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000dd ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000c4a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ef ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000c48 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ee ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000c46 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ed ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000c47 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ec ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000c45 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008eb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig00000c43 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ea ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig00000c44 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000c42 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000c40 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000c41 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000c3f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000c3d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000c3e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000c3c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000c3a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000c3b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000c39 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008df ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000c37 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008de ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000c38 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000c36 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig00000c34 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008db ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000c35 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008da ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig00000c33 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000c31 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000c32 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000c30 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000c2e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000c2f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000c2d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8d ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000c2b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000c2c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000c2a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8b ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000c28 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8a ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000c29 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ce ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c89 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000c27 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c88 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000c25 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c87 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000c26 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c86 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig00000c24 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c85 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000c22 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c84 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig00000c23 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c83 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000c21 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c82 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000c1f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c81 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000c20 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c80 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000c1e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7f ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000c1d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000c1b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7e ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000c1c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000c1a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000c18 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000c19 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008be ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000c17 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000c15 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000c16 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig00000c14 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ba ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000c12 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000c13 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000c11 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000c0f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000c10 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000c0e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000c0c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000c0d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000c0b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000c09 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000c0a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000c08 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000c06 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ad ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000c07 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ac ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000c05 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ab ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000c03 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008aa ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig00000c04 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000c02 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000c00 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000c01 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000bff ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000bfd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000bfe ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7d ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000bfc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7c ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000bfa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7b ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000bfb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7a ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000bf9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089f ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c79 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000bf7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089e ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c78 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000bf8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089d ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c77 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000bf6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089c ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c76 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig00000bf4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089b ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c75 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000bf5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089a ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c74 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000bf3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000899 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c73 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000bf1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000898 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c72 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000bf2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000897 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c71 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000bf0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000896 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c70 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000bee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000895 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6f ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000bef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000894 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6e ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000bed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig00000bec ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000892 ( + .I0(ce), + .I1(\blk00000003/sig000002af ), + .O(\blk00000003/sig00000c6d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000891 ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c6c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000890 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c6b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088f ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088e ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000c68 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000088c ( + .I0(sclr), + .I1(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000372 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .O(\blk00000003/sig0000036d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig0000036a ), + .I1(\blk00000003/sig00000378 ), + .O(\blk00000003/sig0000036b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .I2(\blk00000003/sig0000036f ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000366 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000887 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .O(\blk00000003/sig00000362 ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000886 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002b9 ), + .O(\blk00000003/sig00000360 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000885 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000035d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000359 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000356 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000354 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig0000031a ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig0000031a ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig0000031c ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000312 ), + .O(\blk00000003/sig00000341 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000033d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig00000316 ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000033f ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000338 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000002f8 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032f ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig00000332 ), + .I1(\blk00000003/sig000002f8 ), + .I2(\blk00000003/sig00000302 ), + .I3(coef_we), + .O(\blk00000003/sig00000327 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000877 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000325 ), + .O(\blk00000003/sig0000031b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000876 ( + .I0(coef_we), + .I1(\blk00000003/sig00000302 ), + .O(\blk00000003/sig000002f9 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000875 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000323 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig00000331 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fe ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig00000330 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fc ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig0000030e ), + .I2(coef_ld), + .O(\blk00000003/sig000002f3 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig0000030e ), + .O(\blk00000003/sig000002f0 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000002f4 ), + .I1(coef_we), + .O(\blk00000003/sig000002f5 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .I3(\blk00000003/sig000002f8 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030f ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig0000030d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig00000159 ), + .I1(nd), + .O(\blk00000003/sig000002b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002b5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000174 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000086a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig000002ae ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000c5c ), + .I2(\blk00000003/sig00000c5d ), + .I3(\blk00000003/sig00000c5e ), + .I4(\blk00000003/sig00000c5f ), + .O(\blk00000003/sig00000177 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig0000029c ), + .I2(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig00000369 ), + .I1(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002a9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000866 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000169 ), + .O(\blk00000003/sig00000168 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000865 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000167 ), + .O(\blk00000003/sig00000166 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig00000161 ), + .I1(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000162 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig0000029c ), + .I1(\blk00000003/sig000002b6 ), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .I4(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig00000c64 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig000002b9 ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000015d ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig00000369 ), + .I2(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002ab ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000085e ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000c62 ), + .I3(\blk00000003/sig00000165 ), + .O(\blk00000003/sig00000164 ) + ); + MUXCY \blk00000003/blk0000085d ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000c60 ), + .O(\blk00000003/sig00000c58 ) + ); + MUXCY_L \blk00000003/blk0000085c ( + .CI(\blk00000003/sig00000c58 ), + .DI(\blk00000003/sig00000c5f ), + .S(\blk00000003/sig00000c59 ), + .LO(\blk00000003/sig00000c55 ) + ); + MUXCY_L \blk00000003/blk0000085b ( + .CI(\blk00000003/sig00000c55 ), + .DI(\blk00000003/sig00000c5e ), + .S(\blk00000003/sig00000c56 ), + .LO(\blk00000003/sig00000c52 ) + ); + MUXCY_L \blk00000003/blk0000085a ( + .CI(\blk00000003/sig00000c52 ), + .DI(\blk00000003/sig00000c5d ), + .S(\blk00000003/sig00000c53 ), + .LO(\blk00000003/sig00000c4f ) + ); + MUXCY_L \blk00000003/blk00000859 ( + .CI(\blk00000003/sig00000c4f ), + .DI(\blk00000003/sig00000c5c ), + .S(\blk00000003/sig00000c50 ), + .LO(\blk00000003/sig00000c4c ) + ); + MUXCY_D \blk00000003/blk00000858 ( + .CI(\blk00000003/sig00000c4c ), + .DI(\blk00000003/sig00000c5b ), + .S(\blk00000003/sig00000c4d ), + .O(\NLW_blk00000003/blk00000858_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000858_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000857 ( + .CI(\blk00000003/sig00000c58 ), + .LI(\blk00000003/sig00000c59 ), + .O(\blk00000003/sig00000c5a ) + ); + XORCY \blk00000003/blk00000856 ( + .CI(\blk00000003/sig00000c55 ), + .LI(\blk00000003/sig00000c56 ), + .O(\blk00000003/sig00000c57 ) + ); + XORCY \blk00000003/blk00000855 ( + .CI(\blk00000003/sig00000c52 ), + .LI(\blk00000003/sig00000c53 ), + .O(\blk00000003/sig00000c54 ) + ); + XORCY \blk00000003/blk00000854 ( + .CI(\blk00000003/sig00000c4f ), + .LI(\blk00000003/sig00000c50 ), + .O(\blk00000003/sig00000c51 ) + ); + XORCY \blk00000003/blk00000853 ( + .CI(\blk00000003/sig00000c4c ), + .LI(\blk00000003/sig00000c4d ), + .O(\blk00000003/sig00000c4e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000852 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4b ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000851 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000850 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c49 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c48 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c47 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c46 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c45 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c44 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c43 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000849 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c42 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000848 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c41 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000847 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c40 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000846 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000845 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000844 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000843 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000842 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000841 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000840 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c39 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c38 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c37 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c36 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c35 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c34 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c33 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000839 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c32 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000838 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c31 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000837 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c30 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000836 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000835 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000834 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000833 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000832 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000831 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000830 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c29 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c28 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c27 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c26 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c25 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c24 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c23 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000829 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c22 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000828 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c21 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000827 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c20 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000826 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000825 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000824 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000823 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000822 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000821 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000820 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c19 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c18 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c17 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c16 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c15 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c14 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c13 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000819 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c12 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000818 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c11 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000817 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c10 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000816 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000815 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000814 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000813 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000812 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000811 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000810 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c09 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c08 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c07 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c06 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c05 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c04 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c03 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000809 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c02 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000808 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c01 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c00 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000806 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bff ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000805 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfe ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000804 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000803 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000802 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000801 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000bec ), + .S(\blk00000003/sig00000bd6 ), + .LO(\blk00000003/sig00000be4 ) + ); + MUXCY_L \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig00000be4 ), + .DI(\blk00000003/sig00000beb ), + .S(\blk00000003/sig00000be5 ), + .LO(\blk00000003/sig00000be1 ) + ); + MUXCY_L \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig00000be1 ), + .DI(\blk00000003/sig00000bea ), + .S(\blk00000003/sig00000be2 ), + .LO(\blk00000003/sig00000bde ) + ); + MUXCY_L \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig00000bde ), + .DI(\blk00000003/sig00000be9 ), + .S(\blk00000003/sig00000bdf ), + .LO(\blk00000003/sig00000bdb ) + ); + MUXCY_L \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000bdb ), + .DI(\blk00000003/sig00000be8 ), + .S(\blk00000003/sig00000bdc ), + .LO(\blk00000003/sig00000bd8 ) + ); + MUXCY_D \blk00000003/blk000007ee ( + .CI(\blk00000003/sig00000bd8 ), + .DI(\blk00000003/sig00000be7 ), + .S(\blk00000003/sig00000bd9 ), + .O(\NLW_blk00000003/blk000007ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007ed ( + .CI(\blk00000003/sig00000be4 ), + .LI(\blk00000003/sig00000be5 ), + .O(\blk00000003/sig00000be6 ) + ); + XORCY \blk00000003/blk000007ec ( + .CI(\blk00000003/sig00000be1 ), + .LI(\blk00000003/sig00000be2 ), + .O(\blk00000003/sig00000be3 ) + ); + XORCY \blk00000003/blk000007eb ( + .CI(\blk00000003/sig00000bde ), + .LI(\blk00000003/sig00000bdf ), + .O(\blk00000003/sig00000be0 ) + ); + XORCY \blk00000003/blk000007ea ( + .CI(\blk00000003/sig00000bdb ), + .LI(\blk00000003/sig00000bdc ), + .O(\blk00000003/sig00000bdd ) + ); + XORCY \blk00000003/blk000007e9 ( + .CI(\blk00000003/sig00000bd8 ), + .LI(\blk00000003/sig00000bd9 ), + .O(\blk00000003/sig00000bda ) + ); + XORCY \blk00000003/blk000007e8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000bd6 ), + .O(\blk00000003/sig00000bd7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000777 ), + .R(sclr), + .Q(\blk00000003/sig00000a26 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000776 ), + .R(sclr), + .Q(\blk00000003/sig00000a25 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000775 ), + .R(sclr), + .Q(\blk00000003/sig00000a24 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000774 ), + .R(sclr), + .Q(\blk00000003/sig00000a23 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000773 ), + .R(sclr), + .Q(\blk00000003/sig00000a22 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000772 ), + .R(sclr), + .Q(\blk00000003/sig00000a21 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000771 ), + .R(sclr), + .Q(\blk00000003/sig00000a20 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000770 ), + .R(sclr), + .Q(\blk00000003/sig00000a1f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076f ), + .R(sclr), + .Q(\blk00000003/sig00000a1e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076e ), + .R(sclr), + .Q(\blk00000003/sig00000a1d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076d ), + .R(sclr), + .Q(\blk00000003/sig00000a1c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076c ), + .R(sclr), + .Q(\blk00000003/sig00000a1b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076b ), + .R(sclr), + .Q(\blk00000003/sig00000a1a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076a ), + .R(sclr), + .Q(\blk00000003/sig00000a19 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000769 ), + .R(sclr), + .Q(\blk00000003/sig00000a18 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000768 ), + .R(sclr), + .Q(\blk00000003/sig00000a17 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig00000b6a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ec ), + .R(sclr), + .Q(\blk00000003/sig00000b69 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig00000b68 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ea ), + .R(sclr), + .Q(\blk00000003/sig00000b67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig00000b66 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e8 ), + .R(sclr), + .Q(\blk00000003/sig00000b65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig00000b64 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e6 ), + .R(sclr), + .Q(\blk00000003/sig00000b63 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(\blk00000003/sig00000a36 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(\blk00000003/sig00000a35 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(\blk00000003/sig00000a34 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(\blk00000003/sig00000a33 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(\blk00000003/sig00000a32 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(\blk00000003/sig00000a31 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(\blk00000003/sig00000a30 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(\blk00000003/sig00000a2f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(\blk00000003/sig00000a2e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(\blk00000003/sig00000a2d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(\blk00000003/sig00000a2c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(\blk00000003/sig00000a2b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(\blk00000003/sig00000a2a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(\blk00000003/sig00000a29 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(\blk00000003/sig00000a28 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(\blk00000003/sig00000a27 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(\blk00000003/sig00000b72 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(\blk00000003/sig00000b71 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(\blk00000003/sig00000b70 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(\blk00000003/sig00000b6f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(\blk00000003/sig00000b6e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(\blk00000003/sig00000b6d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(\blk00000003/sig00000b6c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(\blk00000003/sig00000b6b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000375 ), + .R(sclr), + .Q(\blk00000003/sig00000a12 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037b ), + .R(sclr), + .Q(\blk00000003/sig00000a11 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036a ), + .R(sclr), + .Q(\blk00000003/sig00000a14 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a16 ), + .R(sclr), + .Q(\blk00000003/sig00000a10 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a15 ), + .R(sclr), + .Q(\blk00000003/sig00000a0f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036f ), + .R(sclr), + .Q(\blk00000003/sig00000a13 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a14 ), + .R(sclr), + .Q(\blk00000003/sig00000a0d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a13 ), + .R(sclr), + .Q(\blk00000003/sig00000a0e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a12 ), + .R(sclr), + .Q(\blk00000003/sig00000a0c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a11 ), + .R(sclr), + .Q(\blk00000003/sig00000a0b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a10 ), + .R(sclr), + .Q(\blk00000003/sig00000a09 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0f ), + .R(sclr), + .Q(\blk00000003/sig00000a0a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0e ), + .R(sclr), + .Q(\blk00000003/sig00000a08 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0d ), + .R(sclr), + .Q(\blk00000003/sig00000a07 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0c ), + .R(sclr), + .Q(\blk00000003/sig00000a05 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .R(sclr), + .Q(\blk00000003/sig00000a04 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0a ), + .R(sclr), + .Q(\blk00000003/sig00000a03 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .R(sclr), + .Q(\blk00000003/sig00000a06 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .R(sclr), + .Q(\blk00000003/sig00000a01 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .R(sclr), + .Q(\blk00000003/sig000009ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .R(sclr), + .Q(\blk00000003/sig000009f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .R(sclr), + .Q(\blk00000003/sig000009fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .R(sclr), + .Q(\blk00000003/sig000009fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .R(sclr), + .Q(\blk00000003/sig000009f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .R(sclr), + .Q(\blk00000003/sig00000a02 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .R(sclr), + .Q(\blk00000003/sig00000a00 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .R(sclr), + .Q(\blk00000003/sig000009fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .R(sclr), + .Q(\blk00000003/sig000009fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .R(sclr), + .Q(\blk00000003/sig000009fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .R(sclr), + .Q(\blk00000003/sig000009f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000337 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e8 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000009c8 , \blk00000003/sig000009c9 , \blk00000003/sig000009ca , +\blk00000003/sig000009cb , \blk00000003/sig000009cc , \blk00000003/sig000009cd , \blk00000003/sig000009ce , \blk00000003/sig000009cf , +\blk00000003/sig000009d0 , \blk00000003/sig000009d1 , \blk00000003/sig000009d2 , \blk00000003/sig000009d3 , \blk00000003/sig000009d4 , +\blk00000003/sig000009d5 , \blk00000003/sig000009d6 , \blk00000003/sig000009d7 }), + .BCOUT({\NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .C({\NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , 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\blk00000003/sig000009e6 , \blk00000003/sig000009e7 }), + .PCOUT({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , 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.RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000978 , \blk00000003/sig00000979 , \blk00000003/sig0000097a , +\blk00000003/sig0000097b , \blk00000003/sig0000097c , \blk00000003/sig0000097d , \blk00000003/sig0000097e , \blk00000003/sig0000097f , +\blk00000003/sig00000980 , \blk00000003/sig00000981 , \blk00000003/sig00000982 , \blk00000003/sig00000983 , \blk00000003/sig00000984 , +\blk00000003/sig00000985 , \blk00000003/sig00000986 , \blk00000003/sig00000987 }), + .BCOUT({\NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , 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\NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000988 , \blk00000003/sig00000989 , \blk00000003/sig0000098a , +\blk00000003/sig0000098b , \blk00000003/sig0000098c , \blk00000003/sig0000098d , \blk00000003/sig0000098e , \blk00000003/sig0000098f , +\blk00000003/sig00000990 , \blk00000003/sig00000991 , \blk00000003/sig00000992 , \blk00000003/sig00000993 , \blk00000003/sig00000994 , +\blk00000003/sig00000995 , \blk00000003/sig00000996 , \blk00000003/sig00000997 }), + .PCOUT({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000928 , \blk00000003/sig00000929 , \blk00000003/sig0000092a , +\blk00000003/sig0000092b , \blk00000003/sig0000092c , \blk00000003/sig0000092d , \blk00000003/sig0000092e , \blk00000003/sig0000092f , +\blk00000003/sig00000930 , \blk00000003/sig00000931 , \blk00000003/sig00000932 , \blk00000003/sig00000933 , \blk00000003/sig00000934 , +\blk00000003/sig00000935 , \blk00000003/sig00000936 , \blk00000003/sig00000937 }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000008f8 , \blk00000003/sig000008f9 , \blk00000003/sig000008fa , \blk00000003/sig000008fb , \blk00000003/sig000008fc , +\blk00000003/sig000008fd , \blk00000003/sig000008fe , \blk00000003/sig000008ff , \blk00000003/sig00000900 , \blk00000003/sig00000901 , +\blk00000003/sig00000902 , \blk00000003/sig00000903 , \blk00000003/sig00000904 , \blk00000003/sig00000905 , \blk00000003/sig00000906 , +\blk00000003/sig00000907 , \blk00000003/sig00000908 , \blk00000003/sig00000909 , \blk00000003/sig0000090a , \blk00000003/sig0000090b , +\blk00000003/sig0000090c , \blk00000003/sig0000090d , \blk00000003/sig0000090e , \blk00000003/sig0000090f , \blk00000003/sig00000910 , +\blk00000003/sig00000911 , \blk00000003/sig00000912 , \blk00000003/sig00000913 , \blk00000003/sig00000914 , \blk00000003/sig00000915 , +\blk00000003/sig00000916 , \blk00000003/sig00000917 , \blk00000003/sig00000918 , \blk00000003/sig00000919 , \blk00000003/sig0000091a , +\blk00000003/sig0000091b , \blk00000003/sig0000091c , \blk00000003/sig0000091d , \blk00000003/sig0000091e , \blk00000003/sig0000091f , +\blk00000003/sig00000920 , \blk00000003/sig00000921 , \blk00000003/sig00000922 , \blk00000003/sig00000923 , \blk00000003/sig00000924 , +\blk00000003/sig00000925 , \blk00000003/sig00000926 , \blk00000003/sig00000927 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000938 , \blk00000003/sig00000939 , \blk00000003/sig0000093a , +\blk00000003/sig0000093b , \blk00000003/sig0000093c , \blk00000003/sig0000093d , \blk00000003/sig0000093e , \blk00000003/sig0000093f , +\blk00000003/sig00000940 , \blk00000003/sig00000941 , \blk00000003/sig00000942 , \blk00000003/sig00000943 , \blk00000003/sig00000944 , +\blk00000003/sig00000945 , \blk00000003/sig00000946 , \blk00000003/sig00000947 }), + .PCOUT({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , \blk00000003/sig0000096a , +\blk00000003/sig0000096b , \blk00000003/sig0000096c , \blk00000003/sig0000096d , \blk00000003/sig0000096e , \blk00000003/sig0000096f , +\blk00000003/sig00000970 , \blk00000003/sig00000971 , \blk00000003/sig00000972 , \blk00000003/sig00000973 , \blk00000003/sig00000974 , +\blk00000003/sig00000975 , \blk00000003/sig00000976 , \blk00000003/sig00000977 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008d8 , \blk00000003/sig000008d9 , \blk00000003/sig000008da , +\blk00000003/sig000008db , \blk00000003/sig000008dc , \blk00000003/sig000008dd , \blk00000003/sig000008de , \blk00000003/sig000008df , +\blk00000003/sig000008e0 , \blk00000003/sig000008e1 , \blk00000003/sig000008e2 , \blk00000003/sig000008e3 , \blk00000003/sig000008e4 , +\blk00000003/sig000008e5 , \blk00000003/sig000008e6 , \blk00000003/sig000008e7 }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , 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\blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad }), + .C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED , 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+\NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , 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.A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008b8 , \blk00000003/sig000008b9 , \blk00000003/sig000008ba , +\blk00000003/sig000008bb , \blk00000003/sig000008bc , \blk00000003/sig000008bd , \blk00000003/sig000008be , \blk00000003/sig000008bf , +\blk00000003/sig000008c0 , \blk00000003/sig000008c1 , \blk00000003/sig000008c2 , \blk00000003/sig000008c3 , \blk00000003/sig000008c4 , +\blk00000003/sig000008c5 , \blk00000003/sig000008c6 , \blk00000003/sig000008c7 }), + .BCOUT({\NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .C({\NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED , 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\NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008c8 , \blk00000003/sig000008c9 , \blk00000003/sig000008ca , +\blk00000003/sig000008cb , \blk00000003/sig000008cc , \blk00000003/sig000008cd , \blk00000003/sig000008ce , \blk00000003/sig000008cf , +\blk00000003/sig000008d0 , \blk00000003/sig000008d1 , \blk00000003/sig000008d2 , \blk00000003/sig000008d3 , \blk00000003/sig000008d4 , +\blk00000003/sig000008d5 , \blk00000003/sig000008d6 , \blk00000003/sig000008d7 }), + .PCOUT({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , 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\NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010a ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000868 , \blk00000003/sig00000869 , \blk00000003/sig0000086a , +\blk00000003/sig0000086b , \blk00000003/sig0000086c , \blk00000003/sig0000086d , \blk00000003/sig0000086e , \blk00000003/sig0000086f , +\blk00000003/sig00000870 , \blk00000003/sig00000871 , \blk00000003/sig00000872 , \blk00000003/sig00000873 , \blk00000003/sig00000874 , +\blk00000003/sig00000875 , \blk00000003/sig00000876 , \blk00000003/sig00000877 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000878 , \blk00000003/sig00000879 , \blk00000003/sig0000087a , +\blk00000003/sig0000087b , \blk00000003/sig0000087c , \blk00000003/sig0000087d , \blk00000003/sig0000087e , \blk00000003/sig0000087f , +\blk00000003/sig00000880 , \blk00000003/sig00000881 , \blk00000003/sig00000882 , \blk00000003/sig00000883 , \blk00000003/sig00000884 , +\blk00000003/sig00000885 , \blk00000003/sig00000886 , \blk00000003/sig00000887 }), + .PCOUT({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000109 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000818 , \blk00000003/sig00000819 , \blk00000003/sig0000081a , +\blk00000003/sig0000081b , \blk00000003/sig0000081c , \blk00000003/sig0000081d , \blk00000003/sig0000081e , \blk00000003/sig0000081f , +\blk00000003/sig00000820 , \blk00000003/sig00000821 , \blk00000003/sig00000822 , \blk00000003/sig00000823 , \blk00000003/sig00000824 , +\blk00000003/sig00000825 , \blk00000003/sig00000826 , \blk00000003/sig00000827 }), + .BCOUT({\NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000007e8 , \blk00000003/sig000007e9 , \blk00000003/sig000007ea , \blk00000003/sig000007eb , \blk00000003/sig000007ec , +\blk00000003/sig000007ed , \blk00000003/sig000007ee , \blk00000003/sig000007ef , \blk00000003/sig000007f0 , \blk00000003/sig000007f1 , +\blk00000003/sig000007f2 , \blk00000003/sig000007f3 , \blk00000003/sig000007f4 , \blk00000003/sig000007f5 , \blk00000003/sig000007f6 , +\blk00000003/sig000007f7 , \blk00000003/sig000007f8 , \blk00000003/sig000007f9 , \blk00000003/sig000007fa , \blk00000003/sig000007fb , +\blk00000003/sig000007fc , \blk00000003/sig000007fd , \blk00000003/sig000007fe , \blk00000003/sig000007ff , \blk00000003/sig00000800 , +\blk00000003/sig00000801 , \blk00000003/sig00000802 , \blk00000003/sig00000803 , \blk00000003/sig00000804 , \blk00000003/sig00000805 , +\blk00000003/sig00000806 , \blk00000003/sig00000807 , \blk00000003/sig00000808 , \blk00000003/sig00000809 , \blk00000003/sig0000080a , +\blk00000003/sig0000080b , \blk00000003/sig0000080c , \blk00000003/sig0000080d , \blk00000003/sig0000080e , \blk00000003/sig0000080f , +\blk00000003/sig00000810 , \blk00000003/sig00000811 , \blk00000003/sig00000812 , \blk00000003/sig00000813 , \blk00000003/sig00000814 , +\blk00000003/sig00000815 , \blk00000003/sig00000816 , \blk00000003/sig00000817 }), + .C({\NLW_blk00000003/blk00000109_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000109_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000828 , \blk00000003/sig00000829 , \blk00000003/sig0000082a , +\blk00000003/sig0000082b , \blk00000003/sig0000082c , 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\blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk00000109_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000108 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007c8 , \blk00000003/sig000007c9 , \blk00000003/sig000007ca , +\blk00000003/sig000007cb , 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+\NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , 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\NLW_blk00000003/blk00000108_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED , 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\blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000108_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000107 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000778 , \blk00000003/sig00000779 , \blk00000003/sig0000077a , +\blk00000003/sig0000077b , \blk00000003/sig0000077c , \blk00000003/sig0000077d , \blk00000003/sig0000077e , \blk00000003/sig0000077f , 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+\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , \blk00000003/sig000007aa , +\blk00000003/sig000007ab , \blk00000003/sig000007ac , \blk00000003/sig000007ad , \blk00000003/sig000007ae , \blk00000003/sig000007af , +\blk00000003/sig000007b0 , \blk00000003/sig000007b1 , \blk00000003/sig000007b2 , \blk00000003/sig000007b3 , \blk00000003/sig000007b4 , +\blk00000003/sig000007b5 , \blk00000003/sig000007b6 , \blk00000003/sig000007b7 }), + .C({\NLW_blk00000003/blk00000107_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007b8 , \blk00000003/sig000007b9 , \blk00000003/sig000007ba , +\blk00000003/sig000007bb , \blk00000003/sig000007bc , \blk00000003/sig000007bd , \blk00000003/sig000007be , \blk00000003/sig000007bf , +\blk00000003/sig000007c0 , \blk00000003/sig000007c1 , \blk00000003/sig000007c2 , \blk00000003/sig000007c3 , \blk00000003/sig000007c4 , +\blk00000003/sig000007c5 , \blk00000003/sig000007c6 , \blk00000003/sig000007c7 }), + .PCOUT({\blk00000003/sig000001d2 , \blk00000003/sig000001d3 , \blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , +\blk00000003/sig000001d7 , \blk00000003/sig000001d8 , \blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , +\blk00000003/sig000001dc , \blk00000003/sig000001dd , \blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , +\blk00000003/sig000001e1 , \blk00000003/sig000001e2 , \blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , +\blk00000003/sig000001e6 , \blk00000003/sig000001e7 , \blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , +\blk00000003/sig000001eb , \blk00000003/sig000001ec , \blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , +\blk00000003/sig000001f0 , \blk00000003/sig000001f1 , \blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , +\blk00000003/sig000001f5 , \blk00000003/sig000001f6 , \blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000107_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000106 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000728 , \blk00000003/sig00000729 , \blk00000003/sig0000072a , +\blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , \blk00000003/sig0000072e , \blk00000003/sig0000072f , +\blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 , \blk00000003/sig00000733 , \blk00000003/sig00000734 , +\blk00000003/sig00000735 , \blk00000003/sig00000736 , \blk00000003/sig00000737 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , \blk00000003/sig00000748 , \blk00000003/sig00000749 , \blk00000003/sig0000074a , \blk00000003/sig0000074b , +\blk00000003/sig0000074c , \blk00000003/sig0000074d , \blk00000003/sig0000074e , \blk00000003/sig0000074f , \blk00000003/sig00000750 , +\blk00000003/sig00000751 , \blk00000003/sig00000752 , \blk00000003/sig00000753 , \blk00000003/sig00000754 , \blk00000003/sig00000755 , +\blk00000003/sig00000756 , \blk00000003/sig00000757 , \blk00000003/sig00000758 , \blk00000003/sig00000759 , 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\NLW_blk00000003/blk00000106_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000768 , \blk00000003/sig00000769 , \blk00000003/sig0000076a , +\blk00000003/sig0000076b , \blk00000003/sig0000076c , \blk00000003/sig0000076d , \blk00000003/sig0000076e , \blk00000003/sig0000076f , +\blk00000003/sig00000770 , \blk00000003/sig00000771 , \blk00000003/sig00000772 , \blk00000003/sig00000773 , \blk00000003/sig00000774 , +\blk00000003/sig00000775 , \blk00000003/sig00000776 , \blk00000003/sig00000777 }), + .PCOUT({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000106_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000105 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a , \blk00000003/sig0000071b , \blk00000003/sig0000071c , +\blk00000003/sig0000071d , \blk00000003/sig0000071e , \blk00000003/sig0000071f }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , \blk00000003/sig000006f6 , +\blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , \blk00000003/sig000006fb , +\blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , \blk00000003/sig00000700 , +\blk00000003/sig00000701 , \blk00000003/sig00000702 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , +\blk00000003/sig00000706 , \blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , +\blk00000003/sig0000070b , \blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , +\blk00000003/sig00000710 , \blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , +\blk00000003/sig00000715 , \blk00000003/sig00000716 , \blk00000003/sig00000717 }), + .C({\NLW_blk00000003/blk00000105_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , \blk00000003/sig00000724 , +\blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 }), + .PCOUT({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .A({\blk00000003/sig00000646 , \blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , +\blk00000003/sig0000064b , \blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , +\blk00000003/sig00000650 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , +\blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 }), + .M({\NLW_blk00000003/blk00000105_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000104 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , 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\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , +\blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 }), + .C({\NLW_blk00000003/blk00000104_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e1 , \blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , +\blk00000003/sig000006e5 , \blk00000003/sig000006e6 , \blk00000003/sig000006e7 }), + .PCOUT({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , 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.A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk00000104_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000103 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , \blk00000003/sig0000069b , \blk00000003/sig0000069c , +\blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f }), + .BCOUT({\NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , 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\blk00000003/sig00000697 }), + .C({\NLW_blk00000003/blk00000103_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<9>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , +\blk00000003/sig000006a5 , \blk00000003/sig000006a6 , \blk00000003/sig000006a7 }), + .PCOUT({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , \blk00000003/sig000006b1 , +\blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , \blk00000003/sig000006b6 , +\blk00000003/sig000006b7 , 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.RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , +\blk00000003/sig0000065d , \blk00000003/sig0000065e , \blk00000003/sig0000065f }), + .BCOUT({\NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk00000102_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , \blk00000003/sig00000664 , +\blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 }), + .PCOUT({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , \blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , +\blk00000003/sig00000677 , \blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , +\blk00000003/sig0000067c , \blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , +\blk00000003/sig00000681 , \blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , +\blk00000003/sig00000686 , \blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , +\blk00000003/sig0000068b , \blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , +\blk00000003/sig00000690 , \blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , +\blk00000003/sig00000695 , \blk00000003/sig00000696 , \blk00000003/sig00000697 }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000102_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000101 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d }), + .BCOUT({\NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005f4 , \blk00000003/sig000005f5 , \blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , +\blk00000003/sig000005f9 , \blk00000003/sig000005fa , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , +\blk00000003/sig000005fe , \blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , +\blk00000003/sig00000603 , \blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , +\blk00000003/sig00000608 , \blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , +\blk00000003/sig0000060d , \blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , +\blk00000003/sig00000612 , \blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , +\blk00000003/sig00000617 , \blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , +\blk00000003/sig0000061c , \blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , +\blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 }), + .C({\NLW_blk00000003/blk00000101_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000101_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 , +\blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 }), + .PCOUT({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , 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\blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .C({\NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED , 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\blk00000003/sig000005a0 , \blk00000003/sig000005a1 }), + .PCOUT({\blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , \blk00000003/sig000005a6 , +\blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , \blk00000003/sig000005ab , +\blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , \blk00000003/sig000005b0 , +\blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , +\blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , +\blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , +\blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , +\blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , +\blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fe ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , 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\NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , +\blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , +\blk00000003/sig00000396 , \blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , +\blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , 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+\NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000549 , \blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , +\blk00000003/sig0000054d , \blk00000003/sig0000054e , \blk00000003/sig0000054f }), + .PCOUT({\blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , \blk00000003/sig00000554 , +\blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 , \blk00000003/sig00000559 , +\blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , \blk00000003/sig0000055d , \blk00000003/sig0000055e , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , \blk00000003/sig00000567 , \blk00000003/sig00000568 , +\blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , \blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fd ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , \blk00000003/sig00000504 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 }), + .BCOUT({\NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .C({\NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , +\blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f }), + .PCOUT({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fc ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , +\blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , 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\blk00000003/sig000004e1 , \blk00000003/sig000004e2 , +\blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 }), + .C({\NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed }), + .PCOUT({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , 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.A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED , 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\NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fb ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , +\blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , +\blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d }), + .PCOUT({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , +\blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , +\blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , +\blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f9 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , +\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .PCOUT({\blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , +\blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , +\blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec , +\blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 , \blk00000003/sig000003f6 , +\blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , \blk00000003/sig000003fa , \blk00000003/sig000003fb , +\blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , +\blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , +\blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , +\blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f8 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , +\blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , +\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , 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\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , +\blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , +\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000378 ), + .Q(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig00000374 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000374 ), + .DI(\blk00000003/sig00000375 ), + .S(\blk00000003/sig00000376 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000372 ), + .Q(\blk00000003/sig00000373 ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig0000036e ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + MUXCY_D \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036e ), + .DI(\blk00000003/sig0000036f ), + .S(\blk00000003/sig00000370 ), + .O(\NLW_blk00000003/blk000000f0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000036d ), + .O(\blk00000003/sig0000036e ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000036b ), + .O(\blk00000003/sig0000036c ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000036a ), + .S(\blk00000003/sig0000036b ), + .O(\NLW_blk00000003/blk000000ed_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000369 ), + .S(\blk00000003/sig00000363 ), + .LO(\blk00000003/sig00000365 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000365 ), + .DI(\blk00000003/sig00000368 ), + .S(\blk00000003/sig00000366 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000365 ), + .LI(\blk00000003/sig00000366 ), + .O(\blk00000003/sig00000367 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000364 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig0000035c ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig0000035d ), + .LO(\blk00000003/sig0000035f ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig0000035f ), + .DI(\blk00000003/sig000002b9 ), + .S(\blk00000003/sig00000360 ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035c ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig0000035f ), + .LI(\blk00000003/sig00000360 ), + .O(\blk00000003/sig00000361 ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035c ), + .LI(\blk00000003/sig0000035d ), + .O(\blk00000003/sig0000035e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034d ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ef ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig0000035a ), + .S(\blk00000003/sig0000035b ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig00000358 ), + .S(\blk00000003/sig00000359 ), + .O(\blk00000003/sig00000355 ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000355 ), + .DI(\blk00000003/sig0000034b ), + .S(\blk00000003/sig00000356 ), + .O(\blk00000003/sig00000352 ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000352 ), + .DI(\blk00000003/sig00000353 ), + .S(\blk00000003/sig00000354 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000de_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000031e ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig000002ec ), + .S(\blk00000003/sig0000034f ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\blk00000003/sig0000034c ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000034d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000034b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029f ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig00000349 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig00000348 ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000342 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000342 ), + .DI(\blk00000003/sig00000343 ), + .S(\blk00000003/sig00000344 ), + .O(\blk00000003/sig00000340 ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig00000340 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig00000341 ), + .O(\blk00000003/sig0000033c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000033e ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig0000033f ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000033a ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033c ), + .DI(\blk00000003/sig00000313 ), + .S(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033a ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000033b ) + ); + FDE \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000324 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000333 ) + ); + XORCY \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000333 ), + .LI(\blk00000003/sig00000335 ), + .O(\blk00000003/sig00000336 ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000333 ), + .DI(\blk00000003/sig00000334 ), + .S(\blk00000003/sig00000335 ), + .O(\NLW_blk00000003/blk000000cc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000326 ), + .DI(\blk00000003/sig00000332 ), + .S(\blk00000003/sig00000327 ), + .LO(\blk00000003/sig0000032c ) + ); + MUXCY_L \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032c ), + .DI(\blk00000003/sig00000331 ), + .S(\blk00000003/sig0000032d ), + .LO(\blk00000003/sig00000329 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000329 ), + .DI(\blk00000003/sig00000330 ), + .S(\blk00000003/sig0000032a ), + .O(\NLW_blk00000003/blk000000c9_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000032f ), + .O(\blk00000003/sig00000326 ) + ); + XORCY \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig0000032c ), + .LI(\blk00000003/sig0000032d ), + .O(\blk00000003/sig0000032e ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000329 ), + .LI(\blk00000003/sig0000032a ), + .O(\blk00000003/sig0000032b ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000326 ), + .LI(\blk00000003/sig00000327 ), + .O(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/sig0000030b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030e ), + .Q(\blk00000003/sig00000312 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b5_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000305 ), + .R(coef_ld), + .Q(\blk00000003/sig00000302 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b3_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000311 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000310 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030a ) + ); + XORCY \blk00000003/blk000000ac ( + .CI(\blk00000003/sig00000307 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000308 ) + ); + MUXCY \blk00000003/blk000000ab ( + .CI(\blk00000003/sig00000307 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002fd ) + ); + MUXCY_D \blk00000003/blk000000aa ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000306 ), + .O(\blk00000003/sig00000307 ), + .LO(\NLW_blk00000003/blk000000aa_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000303 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000305 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000303 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000304 ), + .O(\blk00000003/sig00000301 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig00000301 ), + .DI(\blk00000003/sig00000302 ), + .S(coef_we), + .O(\blk00000003/sig00000303 ), + .LO(\NLW_blk00000003/blk000000a6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002ff ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a4 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a4_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000002fd ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fe ), + .O(\blk00000003/sig000002ff ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a2 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f7 ), + .LO(\NLW_blk00000003/blk000000a2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a0_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000002f7 ), + .DI(\blk00000003/sig000002f8 ), + .S(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002f5 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY_D \blk00000003/blk0000009d ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002f4 ), + .S(\blk00000003/sig000002f5 ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000009d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002ed ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002f1 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig000002f3 ), + .O(\NLW_blk00000003/blk0000009b_O_UNCONNECTED ), + .LO(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ee ), + .DI(\blk00000003/sig000002ef ), + .S(\blk00000003/sig000002f0 ), + .O(\blk00000003/sig000002f1 ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ee ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(\blk00000003/sig000002ae ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .R(sclr), + .Q(\blk00000003/sig000002b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000002b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ad ), + .R(\blk00000003/sig000002ae ), + .Q(rdy) + ); + FDRE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(sclr), + .Q(\blk00000003/sig000002ac ) + ); + FDSE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a9 ), + .S(sclr), + .Q(\blk00000003/sig000002aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .R(sclr), + .Q(\blk00000003/sig0000029c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a5 ), + .R(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .R(sclr), + .Q(\blk00000003/sig000002a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000027_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000176 ), + .R(sclr), + .Q(\blk00000003/sig00000173 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000170 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000023_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000171 ), + .S(sclr), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk00000021 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029a ), + .LO(\NLW_blk00000003/blk00000021_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000020 ( + .CI(\blk00000003/sig0000029a ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk00000020_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000001f ( + .CI(\blk00000003/sig0000029a ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029b ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001e ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000024a , \blk00000003/sig0000024b , \blk00000003/sig0000024c , +\blk00000003/sig0000024d , \blk00000003/sig0000024e , \blk00000003/sig0000024f , \blk00000003/sig00000250 , \blk00000003/sig00000251 , +\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 }), + .BCOUT({\NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED , +\blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , +\blk00000003/sig00000157 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , +\blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , +\blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , +\blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig0000028a , +\blk00000003/sig0000028b , \blk00000003/sig0000028c , \blk00000003/sig0000028d , \blk00000003/sig0000028e , \blk00000003/sig0000028f , +\blk00000003/sig00000290 , \blk00000003/sig00000291 , \blk00000003/sig00000292 , \blk00000003/sig00000293 , \blk00000003/sig00000294 , +\blk00000003/sig00000295 , \blk00000003/sig00000296 , \blk00000003/sig00000297 , \blk00000003/sig00000298 , \blk00000003/sig00000299 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 }), + .BCOUT({\NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , \blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , +\blk00000003/sig00000229 , \blk00000003/sig0000022a , \blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , +\blk00000003/sig0000022e , \blk00000003/sig0000022f , \blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , +\blk00000003/sig00000233 , \blk00000003/sig00000234 , \blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , +\blk00000003/sig00000238 , \blk00000003/sig00000239 , \blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , +\blk00000003/sig0000023d , \blk00000003/sig0000023e , \blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 , +\blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , \blk00000003/sig00000245 , \blk00000003/sig00000246 , +\blk00000003/sig00000247 , \blk00000003/sig00000248 , \blk00000003/sig00000249 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED , 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+\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 , +\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 }), + .BCOUT({\NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001d2 , 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\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , 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\NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , +\blk00000003/sig000000b0 , \blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b5 , \blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , +\blk00000003/sig000000ba , \blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig00000202 , +\blk00000003/sig00000203 , \blk00000003/sig00000204 , \blk00000003/sig00000205 , \blk00000003/sig00000206 , \blk00000003/sig00000207 , +\blk00000003/sig00000208 , \blk00000003/sig00000209 , \blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , +\blk00000003/sig0000020d , \blk00000003/sig0000020e , \blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED , 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+\NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f }), + .BCOUT({\NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED , +\blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , +\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED }) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000177 ), + .O(\blk00000003/sig00000172 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000175 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000176 ) + ); + MUXCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000175 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000016a ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig00000172 ), + .DI(\blk00000003/sig00000173 ), + .S(\blk00000003/sig00000174 ), + .O(\blk00000003/sig00000175 ), + .LO(\NLW_blk00000003/blk00000017_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000016 ( + .CI(\blk00000003/sig00000170 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000171 ) + ); + MUXCY_D \blk00000003/blk00000015 ( + .CI(\blk00000003/sig0000016d ), + .DI(\blk00000003/sig0000016e ), + .S(\blk00000003/sig0000016f ), + .O(\NLW_blk00000003/blk00000015_O_UNCONNECTED ), + .LO(\blk00000003/sig00000170 ) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(\blk00000003/sig0000016a ), + .DI(\blk00000003/sig0000016b ), + .S(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000013 ( + .C(clk), + .D(\blk00000003/sig00000168 ), + .Q(\blk00000003/sig00000169 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000012 ( + .C(clk), + .D(\blk00000003/sig00000166 ), + .Q(\blk00000003/sig00000167 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000011 ( + .C(clk), + .D(\blk00000003/sig00000164 ), + .Q(\blk00000003/sig00000165 ) + ); + XORCY \blk00000003/blk00000010 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000162 ), + .O(\blk00000003/sig00000163 ) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000161 ), + .S(\blk00000003/sig00000162 ), + .O(\NLW_blk00000003/blk0000000f_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig0000015c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000160 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig0000015e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015e ), + .R(sclr), + .Q(\blk00000003/sig0000015f ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015a ), + .LO(\NLW_blk00000003/blk0000000c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig0000015b ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000158 ) + ); + MUXCY \blk00000003/blk0000000a ( + .CI(\blk00000003/sig0000015b ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000015c ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig0000015a ), + .DI(\blk00000003/sig00000159 ), + .S(nd), + .O(\blk00000003/sig0000015b ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000158 ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000007 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , +\blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , +\blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , +\blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 }), + .BCOUT({\NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 }), + .P({\NLW_blk00000003/blk00000007_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED , +\blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , +\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , +\blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 }), + .M({\NLW_blk00000003/blk00000007_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000006 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , \blk00000003/sig000000b0 , +\blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd }), + .BCOUT({\NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , +\blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , +\blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , +\blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , +\blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , +\blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , +\blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc }), + .P({\NLW_blk00000003/blk00000006_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED , +\blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , +\blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , +\blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , +\blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , +\blk00000003/sig000000f1 , \blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , +\blk00000003/sig000000f6 , \blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , +\blk00000003/sig000000fb }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc }), + .PCOUT({\NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000035/blk00000097 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000035/sig00000f29 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000096 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f27 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000095 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f26 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000094 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f28 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000093 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000092 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000091 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000090 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000089 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000088 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000087 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000086 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000085 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000084 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f15 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000083 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000082 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000081 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f12 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000080 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f11 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f10 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000079 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000078 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f09 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000077 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f08 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000076 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000075 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f06 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000074 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f05 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000073 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f07 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000072 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f03 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000071 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f02 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000070 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f04 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f00 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000eff ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f01 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efe ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000069 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000068 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000ef9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000067 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000066 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f28 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f27 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f26 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f25 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f24 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f23 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f22 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f21 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f20 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1f ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1e ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1d ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1c ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1b ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1a ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f19 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f18 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f17 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f16 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f15 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f14 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f13 ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f12 ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f11 ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f10 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0f ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0e ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0d ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0c ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0b ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0a ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f09 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f08 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f07 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f06 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f05 ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f04 ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f03 ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f02 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f01 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f00 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000eff ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efe ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efd ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efc ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efb ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efa ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000ef9 ), + .Q(\blk00000003/sig000002ea ) + ); + GND \blk00000003/blk00000035/blk00000036 ( + .G(\blk00000003/blk00000035/sig00000ef8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000013d/blk0000015f ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk0000013d/sig00000f5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/blk0000013d/sig00000f5e ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/blk0000013d/sig00000f5d ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/blk0000013d/sig00000f5c ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/blk0000013d/sig00000f5b ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/blk0000013d/sig00000f5a ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000159 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/blk0000013d/sig00000f59 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000158 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/blk0000013d/sig00000f58 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000157 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/blk0000013d/sig00000f57 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000156 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/blk0000013d/sig00000f56 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000155 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/blk0000013d/sig00000f55 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000154 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/blk0000013d/sig00000f54 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000153 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/blk0000013d/sig00000f53 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000152 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/blk0000013d/sig00000f52 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000151 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/blk0000013d/sig00000f51 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000150 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/blk0000013d/sig00000f50 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000014f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/blk0000013d/sig00000f4f ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5e ), + .Q(\blk00000003/sig00000768 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5d ), + .Q(\blk00000003/sig00000769 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5c ), + .Q(\blk00000003/sig0000076a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5b ), + .Q(\blk00000003/sig0000076b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5a ), + .Q(\blk00000003/sig0000076c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000149 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f59 ), + .Q(\blk00000003/sig0000076d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000148 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f58 ), + .Q(\blk00000003/sig0000076e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000147 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f57 ), + .Q(\blk00000003/sig0000076f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000146 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f56 ), + .Q(\blk00000003/sig00000770 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000145 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f55 ), + .Q(\blk00000003/sig00000771 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000144 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f54 ), + .Q(\blk00000003/sig00000772 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000143 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f53 ), + .Q(\blk00000003/sig00000773 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000142 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f52 ), + .Q(\blk00000003/sig00000774 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f51 ), + .Q(\blk00000003/sig00000775 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f50 ), + .Q(\blk00000003/sig00000776 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f4f ), + .Q(\blk00000003/sig00000777 ) + ); + GND \blk00000003/blk0000013d/blk0000013e ( + .G(\blk00000003/blk0000013d/sig00000f4e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000160/blk00000182 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000160/sig00000f95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000181 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/blk00000160/sig00000f94 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000180 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/blk00000160/sig00000f93 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/blk00000160/sig00000f92 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/blk00000160/sig00000f91 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/blk00000160/sig00000f90 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/blk00000160/sig00000f8f ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017b ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/blk00000160/sig00000f8e ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017a ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/blk00000160/sig00000f8d ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000179 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/blk00000160/sig00000f8c ), + .Q15(\NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000178 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/blk00000160/sig00000f8b ), + .Q15(\NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000177 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/blk00000160/sig00000f8a ), + .Q15(\NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000176 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/blk00000160/sig00000f89 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000175 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/blk00000160/sig00000f88 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000174 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/blk00000160/sig00000f87 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000173 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/blk00000160/sig00000f86 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000172 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/blk00000160/sig00000f85 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000171 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f94 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000170 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f93 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f92 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f91 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f90 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8f ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8e ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8d ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8c ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8b ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8a ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f89 ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f88 ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f87 ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f86 ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f85 ), + .Q(\blk00000003/sig00000737 ) + ); + GND \blk00000003/blk00000160/blk00000161 ( + .G(\blk00000003/blk00000160/sig00000f84 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000183/blk000001a5 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk00000183/sig00000fcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/blk00000183/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/blk00000183/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a2 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/blk00000183/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a1 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/blk00000183/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a0 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/blk00000183/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/blk00000183/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/blk00000183/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/blk00000183/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/blk00000183/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/blk00000183/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/blk00000183/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000199 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/blk00000183/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000198 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/blk00000183/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000197 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/blk00000183/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000196 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/blk00000183/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000195 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/blk00000183/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fca ), + .Q(\blk00000003/sig000007b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc9 ), + .Q(\blk00000003/sig000007b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc8 ), + .Q(\blk00000003/sig000007ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc7 ), + .Q(\blk00000003/sig000007bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc6 ), + .Q(\blk00000003/sig000007bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc5 ), + .Q(\blk00000003/sig000007bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc4 ), + .Q(\blk00000003/sig000007be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc3 ), + .Q(\blk00000003/sig000007bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc2 ), + .Q(\blk00000003/sig000007c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc1 ), + .Q(\blk00000003/sig000007c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc0 ), + .Q(\blk00000003/sig000007c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbf ), + .Q(\blk00000003/sig000007c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbe ), + .Q(\blk00000003/sig000007c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbd ), + .Q(\blk00000003/sig000007c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbc ), + .Q(\blk00000003/sig000007c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbb ), + .Q(\blk00000003/sig000007c7 ) + ); + GND \blk00000003/blk00000183/blk00000184 ( + .G(\blk00000003/blk00000183/sig00000fba ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001a6/blk000001c8 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000001a6/sig00001001 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/blk000001a6/sig00001000 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/blk000001a6/sig00000fff ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c5 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/blk000001a6/sig00000ffe ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c4 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/blk000001a6/sig00000ffd ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c3 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/blk000001a6/sig00000ffc ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c2 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/blk000001a6/sig00000ffb ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c1 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/blk000001a6/sig00000ffa ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c0 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/blk000001a6/sig00000ff9 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bf ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/blk000001a6/sig00000ff8 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001be ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/blk000001a6/sig00000ff7 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bd ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/blk000001a6/sig00000ff6 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bc ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/blk000001a6/sig00000ff5 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/blk000001a6/sig00000ff4 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001ba ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/blk000001a6/sig00000ff3 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/blk000001a6/sig00000ff2 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/blk000001a6/sig00000ff1 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00001000 ), + .Q(\blk00000003/sig00000778 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000fff ), + .Q(\blk00000003/sig00000779 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffe ), + .Q(\blk00000003/sig0000077a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffd ), + .Q(\blk00000003/sig0000077b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffc ), + .Q(\blk00000003/sig0000077c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffb ), + .Q(\blk00000003/sig0000077d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffa ), + .Q(\blk00000003/sig0000077e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff9 ), + .Q(\blk00000003/sig0000077f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff8 ), + .Q(\blk00000003/sig00000780 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff7 ), + .Q(\blk00000003/sig00000781 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff6 ), + .Q(\blk00000003/sig00000782 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff5 ), + .Q(\blk00000003/sig00000783 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff4 ), + .Q(\blk00000003/sig00000784 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff3 ), + .Q(\blk00000003/sig00000785 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff2 ), + .Q(\blk00000003/sig00000786 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff1 ), + .Q(\blk00000003/sig00000787 ) + ); + GND \blk00000003/blk000001a6/blk000001a7 ( + .G(\blk00000003/blk000001a6/sig00000ff0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001c9/blk000001eb ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk000001c9/sig00001037 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001ea ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk000001c9/sig00001036 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e9 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk000001c9/sig00001035 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e8 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk000001c9/sig00001034 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e7 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk000001c9/sig00001033 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e6 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk000001c9/sig00001032 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e5 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk000001c9/sig00001031 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e4 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk000001c9/sig00001030 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e3 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk000001c9/sig0000102f ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e2 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk000001c9/sig0000102e ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e1 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk000001c9/sig0000102d ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e0 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk000001c9/sig0000102c ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001df ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk000001c9/sig0000102b ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001de ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk000001c9/sig0000102a ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dd ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk000001c9/sig00001029 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dc ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk000001c9/sig00001028 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001db ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk000001c9/sig00001027 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001036 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001035 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001034 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001033 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001032 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001031 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001030 ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102f ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102e ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102d ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102c ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102b ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102a ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001029 ), + .Q(\blk00000003/sig000008d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001028 ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001027 ), + .Q(\blk00000003/sig000008d7 ) + ); + GND \blk00000003/blk000001c9/blk000001ca ( + .G(\blk00000003/blk000001c9/sig00001026 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000020e ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk000001ec/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/blk000001ec/sig0000106c ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/blk000001ec/sig0000106b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/blk000001ec/sig0000106a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/blk000001ec/sig00001069 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/blk000001ec/sig00001068 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/blk000001ec/sig00001067 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/blk000001ec/sig00001066 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/blk000001ec/sig00001065 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000205 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/blk000001ec/sig00001064 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000204 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/blk000001ec/sig00001063 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000203 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/blk000001ec/sig00001062 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000202 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/blk000001ec/sig00001061 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000201 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/blk000001ec/sig00001060 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000200 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/blk000001ec/sig0000105f ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001ff ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/blk000001ec/sig0000105e ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001fe ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/blk000001ec/sig0000105d ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106c ), + .Q(\blk00000003/sig000008b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106b ), + .Q(\blk00000003/sig000008b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106a ), + .Q(\blk00000003/sig000008ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001069 ), + .Q(\blk00000003/sig000008bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001068 ), + .Q(\blk00000003/sig000008bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001067 ), + .Q(\blk00000003/sig000008bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001066 ), + .Q(\blk00000003/sig000008be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001065 ), + .Q(\blk00000003/sig000008bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001064 ), + .Q(\blk00000003/sig000008c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001063 ), + .Q(\blk00000003/sig000008c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001062 ), + .Q(\blk00000003/sig000008c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001061 ), + .Q(\blk00000003/sig000008c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001060 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105f ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105e ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105d ), + .Q(\blk00000003/sig000008c7 ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig0000105c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000020f/blk00000231 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000020f/sig000010a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000230 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000988 ), + .Q(\blk00000003/blk0000020f/sig000010a2 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000989 ), + .Q(\blk00000003/blk0000020f/sig000010a1 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022e ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098a ), + .Q(\blk00000003/blk0000020f/sig000010a0 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022d ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098b ), + .Q(\blk00000003/blk0000020f/sig0000109f ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098c ), + .Q(\blk00000003/blk0000020f/sig0000109e ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098d ), + .Q(\blk00000003/blk0000020f/sig0000109d ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098e ), + .Q(\blk00000003/blk0000020f/sig0000109c ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000229 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098f ), + .Q(\blk00000003/blk0000020f/sig0000109b ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000228 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000990 ), + .Q(\blk00000003/blk0000020f/sig0000109a ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000227 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000991 ), + .Q(\blk00000003/blk0000020f/sig00001099 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000226 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000992 ), + .Q(\blk00000003/blk0000020f/sig00001098 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000225 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000993 ), + .Q(\blk00000003/blk0000020f/sig00001097 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000224 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000994 ), + .Q(\blk00000003/blk0000020f/sig00001096 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000223 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000995 ), + .Q(\blk00000003/blk0000020f/sig00001095 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000222 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000996 ), + .Q(\blk00000003/blk0000020f/sig00001094 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000221 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000997 ), + .Q(\blk00000003/blk0000020f/sig00001093 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a2 ), + .Q(\blk00000003/sig000009d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a1 ), + .Q(\blk00000003/sig000009d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a0 ), + .Q(\blk00000003/sig000009da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109f ), + .Q(\blk00000003/sig000009db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109e ), + .Q(\blk00000003/sig000009dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109d ), + .Q(\blk00000003/sig000009dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109c ), + .Q(\blk00000003/sig000009de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109b ), + .Q(\blk00000003/sig000009df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109a ), + .Q(\blk00000003/sig000009e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000217 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001099 ), + .Q(\blk00000003/sig000009e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000216 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001098 ), + .Q(\blk00000003/sig000009e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000215 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001097 ), + .Q(\blk00000003/sig000009e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000214 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001096 ), + .Q(\blk00000003/sig000009e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001095 ), + .Q(\blk00000003/sig000009e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001094 ), + .Q(\blk00000003/sig000009e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001093 ), + .Q(\blk00000003/sig000009e7 ) + ); + GND \blk00000003/blk0000020f/blk00000210 ( + .G(\blk00000003/blk0000020f/sig00001092 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000232/blk00000254 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000232/sig000010d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000253 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/blk00000232/sig000010d8 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000252 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/blk00000232/sig000010d7 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000251 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/blk00000232/sig000010d6 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000250 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/blk00000232/sig000010d5 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/blk00000232/sig000010d4 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/blk00000232/sig000010d3 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/blk00000232/sig000010d2 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/blk00000232/sig000010d1 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/blk00000232/sig000010d0 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/blk00000232/sig000010cf ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000249 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/blk00000232/sig000010ce ), + .Q15(\NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000248 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/blk00000232/sig000010cd ), + .Q15(\NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000247 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/blk00000232/sig000010cc ), + .Q15(\NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000246 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/blk00000232/sig000010cb ), + .Q15(\NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000245 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/blk00000232/sig000010ca ), + .Q15(\NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000244 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/blk00000232/sig000010c9 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000243 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d8 ), + .Q(\blk00000003/sig000009c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000242 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d7 ), + .Q(\blk00000003/sig000009c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000241 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d6 ), + .Q(\blk00000003/sig000009ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000240 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d5 ), + .Q(\blk00000003/sig000009cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d4 ), + .Q(\blk00000003/sig000009cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d3 ), + .Q(\blk00000003/sig000009cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d2 ), + .Q(\blk00000003/sig000009ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d1 ), + .Q(\blk00000003/sig000009cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d0 ), + .Q(\blk00000003/sig000009d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cf ), + .Q(\blk00000003/sig000009d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000239 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ce ), + .Q(\blk00000003/sig000009d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cd ), + .Q(\blk00000003/sig000009d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cc ), + .Q(\blk00000003/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cb ), + .Q(\blk00000003/sig000009d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ca ), + .Q(\blk00000003/sig000009d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010c9 ), + .Q(\blk00000003/sig000009d7 ) + ); + GND \blk00000003/blk00000232/blk00000233 ( + .G(\blk00000003/blk00000232/sig000010c8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000255/blk00000277 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000255/sig0000110f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000276 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000255/sig0000110e ), + .Q15(\NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000275 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000255/sig0000110d ), + .Q15(\NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000274 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000255/sig0000110c ), + .Q15(\NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000273 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000255/sig0000110b ), + .Q15(\NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000272 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000255/sig0000110a ), + .Q15(\NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000271 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000255/sig00001109 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000270 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000255/sig00001108 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000255/sig00001107 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000255/sig00001106 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000255/sig00001105 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000255/sig00001104 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000255/sig00001103 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026a ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000255/sig00001102 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000269 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000255/sig00001101 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000268 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000255/sig00001100 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000267 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000255/sig000010ff ), + .Q15(\NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110e ), + .Q(\blk00000003/sig00000878 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110d ), + .Q(\blk00000003/sig00000879 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110c ), + .Q(\blk00000003/sig0000087a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110b ), + .Q(\blk00000003/sig0000087b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110a ), + .Q(\blk00000003/sig0000087c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001109 ), + .Q(\blk00000003/sig0000087d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001108 ), + .Q(\blk00000003/sig0000087e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001107 ), + .Q(\blk00000003/sig0000087f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001106 ), + .Q(\blk00000003/sig00000880 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001105 ), + .Q(\blk00000003/sig00000881 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001104 ), + .Q(\blk00000003/sig00000882 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001103 ), + .Q(\blk00000003/sig00000883 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001102 ), + .Q(\blk00000003/sig00000884 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001101 ), + .Q(\blk00000003/sig00000885 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001100 ), + .Q(\blk00000003/sig00000886 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig000010ff ), + .Q(\blk00000003/sig00000887 ) + ); + GND \blk00000003/blk00000255/blk00000256 ( + .G(\blk00000003/blk00000255/sig000010fe ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000278/blk0000029a ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000278/sig00001145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000299 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/blk00000278/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000298 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/blk00000278/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000297 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/blk00000278/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000296 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/blk00000278/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000295 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/blk00000278/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000294 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/blk00000278/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000293 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/blk00000278/sig0000113e ), + .Q15(\NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000292 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/blk00000278/sig0000113d ), + .Q15(\NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000291 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/blk00000278/sig0000113c ), + .Q15(\NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000290 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/blk00000278/sig0000113b ), + .Q15(\NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/blk00000278/sig0000113a ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/blk00000278/sig00001139 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028d ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/blk00000278/sig00001138 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028c ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/blk00000278/sig00001137 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028b ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/blk00000278/sig00001136 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028a ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/blk00000278/sig00001135 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001144 ), + .Q(\blk00000003/sig00000868 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001143 ), + .Q(\blk00000003/sig00000869 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001142 ), + .Q(\blk00000003/sig0000086a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001141 ), + .Q(\blk00000003/sig0000086b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001140 ), + .Q(\blk00000003/sig0000086c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113f ), + .Q(\blk00000003/sig0000086d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113e ), + .Q(\blk00000003/sig0000086e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113d ), + .Q(\blk00000003/sig0000086f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113c ), + .Q(\blk00000003/sig00000870 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113b ), + .Q(\blk00000003/sig00000871 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113a ), + .Q(\blk00000003/sig00000872 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001139 ), + .Q(\blk00000003/sig00000873 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001138 ), + .Q(\blk00000003/sig00000874 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001137 ), + .Q(\blk00000003/sig00000875 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001136 ), + .Q(\blk00000003/sig00000876 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001135 ), + .Q(\blk00000003/sig00000877 ) + ); + GND \blk00000003/blk00000278/blk00000279 ( + .G(\blk00000003/blk00000278/sig00001134 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000029b/blk000002bd ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk0000029b/sig0000117b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bc ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/blk0000029b/sig0000117a ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bb ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/blk0000029b/sig00001179 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ba ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/blk0000029b/sig00001178 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b9 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/blk0000029b/sig00001177 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b8 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/blk0000029b/sig00001176 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b7 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093d ), + .Q(\blk00000003/blk0000029b/sig00001175 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b6 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093e ), + .Q(\blk00000003/blk0000029b/sig00001174 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b5 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093f ), + .Q(\blk00000003/blk0000029b/sig00001173 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b4 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000940 ), + .Q(\blk00000003/blk0000029b/sig00001172 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b3 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000941 ), + .Q(\blk00000003/blk0000029b/sig00001171 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b2 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000942 ), + .Q(\blk00000003/blk0000029b/sig00001170 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b1 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000943 ), + .Q(\blk00000003/blk0000029b/sig0000116f ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b0 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000944 ), + .Q(\blk00000003/blk0000029b/sig0000116e ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002af ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000945 ), + .Q(\blk00000003/blk0000029b/sig0000116d ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ae ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000946 ), + .Q(\blk00000003/blk0000029b/sig0000116c ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ad ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000947 ), + .Q(\blk00000003/blk0000029b/sig0000116b ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000117a ), + .Q(\blk00000003/sig00000988 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001179 ), + .Q(\blk00000003/sig00000989 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001178 ), + .Q(\blk00000003/sig0000098a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001177 ), + .Q(\blk00000003/sig0000098b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001176 ), + .Q(\blk00000003/sig0000098c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001175 ), + .Q(\blk00000003/sig0000098d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001174 ), + .Q(\blk00000003/sig0000098e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001173 ), + .Q(\blk00000003/sig0000098f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001172 ), + .Q(\blk00000003/sig00000990 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001171 ), + .Q(\blk00000003/sig00000991 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001170 ), + .Q(\blk00000003/sig00000992 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116f ), + .Q(\blk00000003/sig00000993 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116e ), + .Q(\blk00000003/sig00000994 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116d ), + .Q(\blk00000003/sig00000995 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116c ), + .Q(\blk00000003/sig00000996 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116b ), + .Q(\blk00000003/sig00000997 ) + ); + GND \blk00000003/blk0000029b/blk0000029c ( + .G(\blk00000003/blk0000029b/sig0000116a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002be/blk000002e0 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk000002be/sig000011b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002df ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/blk000002be/sig000011b0 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002de ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/blk000002be/sig000011af ), + .Q15(\NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dd ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/blk000002be/sig000011ae ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dc ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/blk000002be/sig000011ad ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002db ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/blk000002be/sig000011ac ), + .Q15(\NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002da ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/blk000002be/sig000011ab ), + .Q15(\NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/blk000002be/sig000011aa ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/blk000002be/sig000011a9 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/blk000002be/sig000011a8 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/blk000002be/sig000011a7 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/blk000002be/sig000011a6 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/blk000002be/sig000011a5 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d3 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/blk000002be/sig000011a4 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d2 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/blk000002be/sig000011a3 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d1 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/blk000002be/sig000011a2 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d0 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/blk000002be/sig000011a1 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011b0 ), + .Q(\blk00000003/sig00000978 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011af ), + .Q(\blk00000003/sig00000979 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ae ), + .Q(\blk00000003/sig0000097a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ad ), + .Q(\blk00000003/sig0000097b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ac ), + .Q(\blk00000003/sig0000097c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ab ), + .Q(\blk00000003/sig0000097d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011aa ), + .Q(\blk00000003/sig0000097e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a9 ), + .Q(\blk00000003/sig0000097f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a8 ), + .Q(\blk00000003/sig00000980 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a7 ), + .Q(\blk00000003/sig00000981 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a6 ), + .Q(\blk00000003/sig00000982 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a5 ), + .Q(\blk00000003/sig00000983 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a4 ), + .Q(\blk00000003/sig00000984 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a3 ), + .Q(\blk00000003/sig00000985 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a2 ), + .Q(\blk00000003/sig00000986 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a1 ), + .Q(\blk00000003/sig00000987 ) + ); + GND \blk00000003/blk000002be/blk000002bf ( + .G(\blk00000003/blk000002be/sig000011a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e1/blk00000303 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000002e1/sig000011e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000302 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002e1/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000301 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002e1/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000300 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk000002e1/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002ff ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk000002e1/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fe ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk000002e1/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk000002e1/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk000002e1/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk000002e1/sig000011df ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fa ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk000002e1/sig000011de ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk000002e1/sig000011dd ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk000002e1/sig000011dc ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk000002e1/sig000011db ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f6 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk000002e1/sig000011da ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f5 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk000002e1/sig000011d9 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk000002e1/sig000011d8 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk000002e1/sig000011d7 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e6 ), + .Q(\blk00000003/sig00000828 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e5 ), + .Q(\blk00000003/sig00000829 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e4 ), + .Q(\blk00000003/sig0000082a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e3 ), + .Q(\blk00000003/sig0000082b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e2 ), + .Q(\blk00000003/sig0000082c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e1 ), + .Q(\blk00000003/sig0000082d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e0 ), + .Q(\blk00000003/sig0000082e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011df ), + .Q(\blk00000003/sig0000082f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011de ), + .Q(\blk00000003/sig00000830 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dd ), + .Q(\blk00000003/sig00000831 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dc ), + .Q(\blk00000003/sig00000832 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011db ), + .Q(\blk00000003/sig00000833 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011da ), + .Q(\blk00000003/sig00000834 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d9 ), + .Q(\blk00000003/sig00000835 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d8 ), + .Q(\blk00000003/sig00000836 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d7 ), + .Q(\blk00000003/sig00000837 ) + ); + GND \blk00000003/blk000002e1/blk000002e2 ( + .G(\blk00000003/blk000002e1/sig000011d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000304/blk00000326 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk00000304/sig0000121d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000325 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/blk00000304/sig0000121c ), + .Q15(\NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000324 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/blk00000304/sig0000121b ), + .Q15(\NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000323 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/blk00000304/sig0000121a ), + .Q15(\NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000322 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/blk00000304/sig00001219 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000321 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/blk00000304/sig00001218 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000320 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/blk00000304/sig00001217 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/blk00000304/sig00001216 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/blk00000304/sig00001215 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/blk00000304/sig00001214 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/blk00000304/sig00001213 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/blk00000304/sig00001212 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/blk00000304/sig00001211 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000319 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/blk00000304/sig00001210 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000318 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/blk00000304/sig0000120f ), + .Q15(\NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000317 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/blk00000304/sig0000120e ), + .Q15(\NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000316 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/blk00000304/sig0000120d ), + .Q15(\NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121c ), + .Q(\blk00000003/sig00000818 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121b ), + .Q(\blk00000003/sig00000819 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121a ), + .Q(\blk00000003/sig0000081a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001219 ), + .Q(\blk00000003/sig0000081b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001218 ), + .Q(\blk00000003/sig0000081c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001217 ), + .Q(\blk00000003/sig0000081d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001216 ), + .Q(\blk00000003/sig0000081e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001215 ), + .Q(\blk00000003/sig0000081f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001214 ), + .Q(\blk00000003/sig00000820 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001213 ), + .Q(\blk00000003/sig00000821 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001212 ), + .Q(\blk00000003/sig00000822 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001211 ), + .Q(\blk00000003/sig00000823 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000309 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001210 ), + .Q(\blk00000003/sig00000824 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000308 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120f ), + .Q(\blk00000003/sig00000825 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000307 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120e ), + .Q(\blk00000003/sig00000826 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000306 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120d ), + .Q(\blk00000003/sig00000827 ) + ); + GND \blk00000003/blk00000304/blk00000305 ( + .G(\blk00000003/blk00000304/sig0000120c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000327/blk00000349 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk00000327/sig00001253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000348 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/blk00000327/sig00001252 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000347 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/blk00000327/sig00001251 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000346 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/blk00000327/sig00001250 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000345 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/blk00000327/sig0000124f ), + .Q15(\NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000344 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/blk00000327/sig0000124e ), + .Q15(\NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000343 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/blk00000327/sig0000124d ), + .Q15(\NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000342 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/blk00000327/sig0000124c ), + .Q15(\NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000341 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/blk00000327/sig0000124b ), + .Q15(\NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000340 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/blk00000327/sig0000124a ), + .Q15(\NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033f ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/blk00000327/sig00001249 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033e ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/blk00000327/sig00001248 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033d ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/blk00000327/sig00001247 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033c ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/blk00000327/sig00001246 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033b ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/blk00000327/sig00001245 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033a ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/blk00000327/sig00001244 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000339 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/blk00000327/sig00001243 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000338 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001252 ), + .Q(\blk00000003/sig00000938 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001251 ), + .Q(\blk00000003/sig00000939 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001250 ), + .Q(\blk00000003/sig0000093a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124f ), + .Q(\blk00000003/sig0000093b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124e ), + .Q(\blk00000003/sig0000093c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124d ), + .Q(\blk00000003/sig0000093d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124c ), + .Q(\blk00000003/sig0000093e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124b ), + .Q(\blk00000003/sig0000093f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124a ), + .Q(\blk00000003/sig00000940 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001249 ), + .Q(\blk00000003/sig00000941 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001248 ), + .Q(\blk00000003/sig00000942 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001247 ), + .Q(\blk00000003/sig00000943 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001246 ), + .Q(\blk00000003/sig00000944 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001245 ), + .Q(\blk00000003/sig00000945 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001244 ), + .Q(\blk00000003/sig00000946 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001243 ), + .Q(\blk00000003/sig00000947 ) + ); + GND \blk00000003/blk00000327/blk00000328 ( + .G(\blk00000003/blk00000327/sig00001242 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000034a/blk0000036c ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk0000034a/sig00001289 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/blk0000034a/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/blk0000034a/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000369 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/blk0000034a/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000368 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/blk0000034a/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000367 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/blk0000034a/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000366 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/blk0000034a/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000365 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/blk0000034a/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000364 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/blk0000034a/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000363 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/blk0000034a/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000362 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/blk0000034a/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000361 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/blk0000034a/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000360 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/blk0000034a/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/blk0000034a/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/blk0000034a/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/blk0000034a/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/blk0000034a/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001288 ), + .Q(\blk00000003/sig00000928 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001287 ), + .Q(\blk00000003/sig00000929 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001286 ), + .Q(\blk00000003/sig0000092a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001285 ), + .Q(\blk00000003/sig0000092b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001284 ), + .Q(\blk00000003/sig0000092c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001283 ), + .Q(\blk00000003/sig0000092d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001282 ), + .Q(\blk00000003/sig0000092e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001281 ), + .Q(\blk00000003/sig0000092f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001280 ), + .Q(\blk00000003/sig00000930 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127f ), + .Q(\blk00000003/sig00000931 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127e ), + .Q(\blk00000003/sig00000932 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127d ), + .Q(\blk00000003/sig00000933 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127c ), + .Q(\blk00000003/sig00000934 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127b ), + .Q(\blk00000003/sig00000935 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127a ), + .Q(\blk00000003/sig00000936 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001279 ), + .Q(\blk00000003/sig00000937 ) + ); + GND \blk00000003/blk0000034a/blk0000034b ( + .G(\blk00000003/blk0000034a/sig00001278 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000036d/blk0000038f ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000036d/sig000012bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041e ), + .Q(\blk00000003/blk0000036d/sig000012be ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041f ), + .Q(\blk00000003/blk0000036d/sig000012bd ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000420 ), + .Q(\blk00000003/blk0000036d/sig000012bc ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000421 ), + .Q(\blk00000003/blk0000036d/sig000012bb ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000422 ), + .Q(\blk00000003/blk0000036d/sig000012ba ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000389 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000423 ), + .Q(\blk00000003/blk0000036d/sig000012b9 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000388 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000424 ), + .Q(\blk00000003/blk0000036d/sig000012b8 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000387 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000425 ), + .Q(\blk00000003/blk0000036d/sig000012b7 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000386 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000426 ), + .Q(\blk00000003/blk0000036d/sig000012b6 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000385 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000427 ), + .Q(\blk00000003/blk0000036d/sig000012b5 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000384 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000428 ), + .Q(\blk00000003/blk0000036d/sig000012b4 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000383 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000429 ), + .Q(\blk00000003/blk0000036d/sig000012b3 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000382 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042a ), + .Q(\blk00000003/blk0000036d/sig000012b2 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000381 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042b ), + .Q(\blk00000003/blk0000036d/sig000012b1 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000380 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042c ), + .Q(\blk00000003/blk0000036d/sig000012b0 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000037f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042d ), + .Q(\blk00000003/blk0000036d/sig000012af ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012be ), + .Q(\blk00000003/sig000007d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bd ), + .Q(\blk00000003/sig000007d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bc ), + .Q(\blk00000003/sig000007da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bb ), + .Q(\blk00000003/sig000007db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012ba ), + .Q(\blk00000003/sig000007dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b9 ), + .Q(\blk00000003/sig000007dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b8 ), + .Q(\blk00000003/sig000007de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b7 ), + .Q(\blk00000003/sig000007df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b6 ), + .Q(\blk00000003/sig000007e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b5 ), + .Q(\blk00000003/sig000007e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b4 ), + .Q(\blk00000003/sig000007e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b3 ), + .Q(\blk00000003/sig000007e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000372 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b2 ), + .Q(\blk00000003/sig000007e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000371 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b1 ), + .Q(\blk00000003/sig000007e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000370 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b0 ), + .Q(\blk00000003/sig000007e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000036f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012af ), + .Q(\blk00000003/sig000007e7 ) + ); + GND \blk00000003/blk0000036d/blk0000036e ( + .G(\blk00000003/blk0000036d/sig000012ae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000390/blk000003b2 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000390/sig000012f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/blk00000390/sig000012f4 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/blk00000390/sig000012f3 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003af ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/blk00000390/sig000012f2 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ae ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/blk00000390/sig000012f1 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ad ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/blk00000390/sig000012f0 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ac ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/blk00000390/sig000012ef ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ab ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/blk00000390/sig000012ee ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003aa ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/blk00000390/sig000012ed ), + .Q15(\NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/blk00000390/sig000012ec ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/blk00000390/sig000012eb ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/blk00000390/sig000012ea ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/blk00000390/sig000012e9 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/blk00000390/sig000012e8 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/blk00000390/sig000012e7 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/blk00000390/sig000012e6 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/blk00000390/sig000012e5 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f4 ), + .Q(\blk00000003/sig000007c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f3 ), + .Q(\blk00000003/sig000007c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f2 ), + .Q(\blk00000003/sig000007ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f1 ), + .Q(\blk00000003/sig000007cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f0 ), + .Q(\blk00000003/sig000007cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ef ), + .Q(\blk00000003/sig000007cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ee ), + .Q(\blk00000003/sig000007ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ed ), + .Q(\blk00000003/sig000007cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ec ), + .Q(\blk00000003/sig000007d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012eb ), + .Q(\blk00000003/sig000007d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ea ), + .Q(\blk00000003/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e9 ), + .Q(\blk00000003/sig000007d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e8 ), + .Q(\blk00000003/sig000007d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e7 ), + .Q(\blk00000003/sig000007d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e6 ), + .Q(\blk00000003/sig000007d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e5 ), + .Q(\blk00000003/sig000007d7 ) + ); + GND \blk00000003/blk00000390/blk00000391 ( + .G(\blk00000003/blk00000390/sig000012e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b3/blk000003d5 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000003b3/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d4 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000003b3/sig0000132a ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d3 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000003b3/sig00001329 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d2 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000003b3/sig00001328 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d1 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000003b3/sig00001327 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d0 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000003b3/sig00001326 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cf ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000003b3/sig00001325 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ce ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000003b3/sig00001324 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cd ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000003b3/sig00001323 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cc ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000003b3/sig00001322 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cb ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000003b3/sig00001321 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ca ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000003b3/sig00001320 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c9 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000003b3/sig0000131f ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c8 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000003b3/sig0000131e ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c7 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000003b3/sig0000131d ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c6 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000003b3/sig0000131c ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c5 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000003b3/sig0000131b ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000132a ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001329 ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001328 ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001327 ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001326 ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001325 ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001324 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001323 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001322 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001321 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001320 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131f ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131e ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131d ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131c ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131b ), + .Q(\blk00000003/sig000008f7 ) + ); + GND \blk00000003/blk000003b3/blk000003b4 ( + .G(\blk00000003/blk000003b3/sig0000131a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d6/blk000003f8 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk000003d6/sig00001361 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/blk000003d6/sig00001360 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/blk000003d6/sig0000135f ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/blk000003d6/sig0000135e ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/blk000003d6/sig0000135d ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/blk000003d6/sig0000135c ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/blk000003d6/sig0000135b ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/blk000003d6/sig0000135a ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/blk000003d6/sig00001359 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ef ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/blk000003d6/sig00001358 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ee ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/blk000003d6/sig00001357 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ed ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/blk000003d6/sig00001356 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ec ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/blk000003d6/sig00001355 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003eb ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/blk000003d6/sig00001354 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ea ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/blk000003d6/sig00001353 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/blk000003d6/sig00001352 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/blk000003d6/sig00001351 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001360 ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135f ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135e ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135d ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135c ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135b ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135a ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001359 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001358 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001357 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001356 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001355 ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001354 ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001353 ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001352 ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001351 ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk000003d6/blk000003d7 ( + .G(\blk00000003/blk000003d6/sig00001350 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000041b ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00001397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000041a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/blk000003f9/sig00001396 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000419 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/blk000003f9/sig00001395 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000418 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/blk000003f9/sig00001394 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000417 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/blk000003f9/sig00001393 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000416 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/blk000003f9/sig00001392 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000415 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/blk000003f9/sig00001391 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000414 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/blk000003f9/sig00001390 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000413 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/blk000003f9/sig0000138f ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000412 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/blk000003f9/sig0000138e ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000411 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/blk000003f9/sig0000138d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000410 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/blk000003f9/sig0000138c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/blk000003f9/sig0000138b ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/blk000003f9/sig0000138a ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/blk000003f9/sig00001389 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/blk000003f9/sig00001388 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/blk000003f9/sig00001387 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk0000040a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001396 ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000409 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001395 ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000408 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001394 ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000407 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001393 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000406 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001392 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000405 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001391 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000404 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001390 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138f ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138e ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138d ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138c ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138b ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138a ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001389 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001388 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001387 ), + .Q(\blk00000003/sig0000042d ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00001386 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041c/blk0000043e ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000041c/sig000013cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/blk0000041c/sig000013cc ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/blk0000041c/sig000013cb ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/blk0000041c/sig000013ca ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/blk0000041c/sig000013c9 ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000439 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/blk0000041c/sig000013c8 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000438 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/blk0000041c/sig000013c7 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000437 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/blk0000041c/sig000013c6 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000436 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/blk0000041c/sig000013c5 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000435 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/blk0000041c/sig000013c4 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000434 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/blk0000041c/sig000013c3 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000433 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/blk0000041c/sig000013c2 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000432 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/blk0000041c/sig000013c1 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000431 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/blk0000041c/sig000013c0 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000430 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/blk0000041c/sig000013bf ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/blk0000041c/sig000013be ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/blk0000041c/sig000013bd ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cc ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cb ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013ca ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c9 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c8 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c7 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c6 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c5 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c4 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c3 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c2 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c1 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c0 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bf ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013be ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bd ), + .Q(\blk00000003/sig0000041d ) + ); + GND \blk00000003/blk0000041c/blk0000041d ( + .G(\blk00000003/blk0000041c/sig000013bc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043f/blk00000461 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000043f/sig00001403 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000460 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/blk0000043f/sig00001402 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/blk0000043f/sig00001401 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/blk0000043f/sig00001400 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/blk0000043f/sig000013ff ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/blk0000043f/sig000013fe ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/blk0000043f/sig000013fd ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/blk0000043f/sig000013fc ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000459 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/blk0000043f/sig000013fb ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000458 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/blk0000043f/sig000013fa ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000457 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/blk0000043f/sig000013f9 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000456 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/blk0000043f/sig000013f8 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000455 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/blk0000043f/sig000013f7 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000454 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/blk0000043f/sig000013f6 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000453 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/blk0000043f/sig000013f5 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000452 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/blk0000043f/sig000013f4 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000451 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/blk0000043f/sig000013f3 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001402 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001401 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001400 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013ff ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fe ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fd ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fc ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fb ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fa ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f9 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000446 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f8 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000445 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f7 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000444 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f6 ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000443 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f5 ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000442 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f4 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000441 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f3 ), + .Q(\blk00000003/sig0000047d ) + ); + GND \blk00000003/blk0000043f/blk00000440 ( + .G(\blk00000003/blk0000043f/sig000013f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000462/blk00000484 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000462/sig00001439 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000483 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/blk00000462/sig00001438 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000482 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/blk00000462/sig00001437 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000481 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/blk00000462/sig00001436 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000480 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/blk00000462/sig00001435 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/blk00000462/sig00001434 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/blk00000462/sig00001433 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/blk00000462/sig00001432 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/blk00000462/sig00001431 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/blk00000462/sig00001430 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/blk00000462/sig0000142f ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000479 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/blk00000462/sig0000142e ), + .Q15(\NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000478 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/blk00000462/sig0000142d ), + .Q15(\NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000477 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/blk00000462/sig0000142c ), + .Q15(\NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000476 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/blk00000462/sig0000142b ), + .Q15(\NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000475 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/blk00000462/sig0000142a ), + .Q15(\NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000474 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/blk00000462/sig00001429 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001438 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001437 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001436 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001435 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001434 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001433 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001432 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001431 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001430 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142f ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142e ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001429 ), + .Q(\blk00000003/sig0000046d ) + ); + GND \blk00000003/blk00000462/blk00000463 ( + .G(\blk00000003/blk00000462/sig00001428 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000485/blk000004bd ( + .I0(\blk00000003/sig0000030c ), + .I1(ce), + .O(\blk00000003/blk00000485/sig0000149c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bc ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001489 ), + .DPO(\blk00000003/blk00000485/sig0000149b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bb ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001488 ), + .DPO(\blk00000003/blk00000485/sig0000149a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004ba ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001487 ), + .DPO(\blk00000003/blk00000485/sig00001499 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b9 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001486 ), + .DPO(\blk00000003/blk00000485/sig00001498 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b8 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001485 ), + .DPO(\blk00000003/blk00000485/sig00001497 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b7 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001484 ), + .DPO(\blk00000003/blk00000485/sig00001496 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b6 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001482 ), + .DPO(\blk00000003/blk00000485/sig00001494 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b5 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001481 ), + .DPO(\blk00000003/blk00000485/sig00001493 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b4 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001483 ), + .DPO(\blk00000003/blk00000485/sig00001495 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b3 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001480 ), + .DPO(\blk00000003/blk00000485/sig00001492 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b2 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147f ), + .DPO(\blk00000003/blk00000485/sig00001491 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b1 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147e ), + .DPO(\blk00000003/blk00000485/sig00001490 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004b0 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147d ), + .DPO(\blk00000003/blk00000485/sig0000148f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004af ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147c ), + .DPO(\blk00000003/blk00000485/sig0000148e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ae ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147b ), + .DPO(\blk00000003/blk00000485/sig0000148d ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004ad ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001479 ), + .DPO(\blk00000003/blk00000485/sig0000148b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ac ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001478 ), + .DPO(\blk00000003/blk00000485/sig0000148a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ab ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147a ), + .DPO(\blk00000003/blk00000485/sig0000148c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149b ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149a ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001499 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001498 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001497 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001496 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001495 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001494 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001493 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001492 ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001491 ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001490 ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148f ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148e ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148d ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148c ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148b ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148a ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001489 ), + .Q(\blk00000003/sig00000b09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001488 ), + .Q(\blk00000003/sig00000b0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001487 ), + .Q(\blk00000003/sig00000b0b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001486 ), + .Q(\blk00000003/sig00000b0c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001485 ), + .Q(\blk00000003/sig00000b0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001484 ), + .Q(\blk00000003/sig00000b0e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001483 ), + .Q(\blk00000003/sig00000b0f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001482 ), + .Q(\blk00000003/sig00000b10 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001481 ), + .Q(\blk00000003/sig00000b11 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001480 ), + .Q(\blk00000003/sig00000b12 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147f ), + .Q(\blk00000003/sig00000b13 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147e ), + .Q(\blk00000003/sig00000b14 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147d ), + .Q(\blk00000003/sig00000b15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147c ), + .Q(\blk00000003/sig00000b16 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147b ), + .Q(\blk00000003/sig00000b17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147a ), + .Q(\blk00000003/sig00000b18 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001479 ), + .Q(\blk00000003/sig00000b19 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001478 ), + .Q(\blk00000003/sig00000b1a ) + ); + GND \blk00000003/blk00000485/blk00000486 ( + .G(\blk00000003/blk00000485/sig00001477 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004be/blk000004f6 ( + .I0(\blk00000003/sig000009f2 ), + .I1(ce), + .O(\blk00000003/blk000004be/sig000014ff ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b09 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ec ), + .DPO(\blk00000003/blk000004be/sig000014fe ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014eb ), + .DPO(\blk00000003/blk000004be/sig000014fd ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f3 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0b ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ea ), + .DPO(\blk00000003/blk000004be/sig000014fc ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f2 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0c ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e9 ), + .DPO(\blk00000003/blk000004be/sig000014fb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f1 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0d ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e8 ), + .DPO(\blk00000003/blk000004be/sig000014fa ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f0 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0e ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e7 ), + .DPO(\blk00000003/blk000004be/sig000014f9 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ef ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b10 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e5 ), + .DPO(\blk00000003/blk000004be/sig000014f7 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ee ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b11 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e4 ), + .DPO(\blk00000003/blk000004be/sig000014f6 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ed ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0f ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e6 ), + .DPO(\blk00000003/blk000004be/sig000014f8 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004ec ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b12 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e3 ), + .DPO(\blk00000003/blk000004be/sig000014f5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004eb ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b13 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e2 ), + .DPO(\blk00000003/blk000004be/sig000014f4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ea ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b14 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e1 ), + .DPO(\blk00000003/blk000004be/sig000014f3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004e9 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b15 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e0 ), + .DPO(\blk00000003/blk000004be/sig000014f2 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e8 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b16 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014df ), + .DPO(\blk00000003/blk000004be/sig000014f1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004e7 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b17 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014de ), + .DPO(\blk00000003/blk000004be/sig000014f0 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e6 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b19 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dc ), + .DPO(\blk00000003/blk000004be/sig000014ee ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b1a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014db ), + .DPO(\blk00000003/blk000004be/sig000014ed ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b18 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dd ), + .DPO(\blk00000003/blk000004be/sig000014ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fe ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fd ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fc ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fb ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fa ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f9 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f8 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f7 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f6 ), + .Q(\blk00000003/sig00000588 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f5 ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f4 ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f3 ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f2 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f1 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f0 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ef ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ee ), + .Q(\blk00000003/sig00000590 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ed ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ec ), + .Q(\blk00000003/sig00000b1b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014eb ), + .Q(\blk00000003/sig00000b1c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ea ), + .Q(\blk00000003/sig00000b1d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e9 ), + .Q(\blk00000003/sig00000b1e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e8 ), + .Q(\blk00000003/sig00000b1f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e7 ), + .Q(\blk00000003/sig00000b20 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e6 ), + .Q(\blk00000003/sig00000b21 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e5 ), + .Q(\blk00000003/sig00000b22 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e4 ), + .Q(\blk00000003/sig00000b23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e3 ), + .Q(\blk00000003/sig00000b24 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e2 ), + .Q(\blk00000003/sig00000b25 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e1 ), + .Q(\blk00000003/sig00000b26 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e0 ), + .Q(\blk00000003/sig00000b27 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014df ), + .Q(\blk00000003/sig00000b28 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014de ), + .Q(\blk00000003/sig00000b29 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dd ), + .Q(\blk00000003/sig00000b2a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dc ), + .Q(\blk00000003/sig00000b2b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014db ), + .Q(\blk00000003/sig00000b2c ) + ); + GND \blk00000003/blk000004be/blk000004bf ( + .G(\blk00000003/blk000004be/sig000014da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004f7/blk0000052f ( + .I0(\blk00000003/sig000009f3 ), + .I1(ce), + .O(\blk00000003/blk000004f7/sig00001562 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154f ), + .DPO(\blk00000003/blk000004f7/sig00001561 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154e ), + .DPO(\blk00000003/blk000004f7/sig00001560 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052c ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1d ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154d ), + .DPO(\blk00000003/blk000004f7/sig0000155f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052b ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1e ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154c ), + .DPO(\blk00000003/blk000004f7/sig0000155e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052a ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1f ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154b ), + .DPO(\blk00000003/blk000004f7/sig0000155d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000529 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b20 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154a ), + .DPO(\blk00000003/blk000004f7/sig0000155c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000528 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b22 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001548 ), + .DPO(\blk00000003/blk000004f7/sig0000155a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000527 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b23 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001547 ), + .DPO(\blk00000003/blk000004f7/sig00001559 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000526 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b21 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001549 ), + .DPO(\blk00000003/blk000004f7/sig0000155b ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000525 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b24 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001546 ), + .DPO(\blk00000003/blk000004f7/sig00001558 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000524 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b25 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001545 ), + .DPO(\blk00000003/blk000004f7/sig00001557 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000523 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b26 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001544 ), + .DPO(\blk00000003/blk000004f7/sig00001556 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000522 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b27 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001543 ), + .DPO(\blk00000003/blk000004f7/sig00001555 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000521 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b28 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001542 ), + .DPO(\blk00000003/blk000004f7/sig00001554 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000520 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b29 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001541 ), + .DPO(\blk00000003/blk000004f7/sig00001553 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051f ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153f ), + .DPO(\blk00000003/blk000004f7/sig00001551 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000051e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153e ), + .DPO(\blk00000003/blk000004f7/sig00001550 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2a ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001540 ), + .DPO(\blk00000003/blk000004f7/sig00001552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001561 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001560 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155f ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155e ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155d ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155c ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155b ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155a ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001559 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001558 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001557 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001556 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001555 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001554 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001553 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001552 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001551 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001550 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154f ), + .Q(\blk00000003/sig00000b2d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154e ), + .Q(\blk00000003/sig00000b2e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154d ), + .Q(\blk00000003/sig00000b2f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154c ), + .Q(\blk00000003/sig00000b30 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154b ), + .Q(\blk00000003/sig00000b31 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154a ), + .Q(\blk00000003/sig00000b32 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001549 ), + .Q(\blk00000003/sig00000b33 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001548 ), + .Q(\blk00000003/sig00000b34 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001547 ), + .Q(\blk00000003/sig00000b35 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001546 ), + .Q(\blk00000003/sig00000b36 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001545 ), + .Q(\blk00000003/sig00000b37 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001544 ), + .Q(\blk00000003/sig00000b38 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001543 ), + .Q(\blk00000003/sig00000b39 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001542 ), + .Q(\blk00000003/sig00000b3a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001541 ), + .Q(\blk00000003/sig00000b3b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001540 ), + .Q(\blk00000003/sig00000b3c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153f ), + .Q(\blk00000003/sig00000b3d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153e ), + .Q(\blk00000003/sig00000b3e ) + ); + GND \blk00000003/blk000004f7/blk000004f8 ( + .G(\blk00000003/blk000004f7/sig0000153d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000530/blk00000568 ( + .I0(\blk00000003/sig000009f4 ), + .I1(ce), + .O(\blk00000003/blk00000530/sig000015c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000567 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b2 ), + .DPO(\blk00000003/blk00000530/sig000015c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000566 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b1 ), + .DPO(\blk00000003/blk00000530/sig000015c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000565 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2f ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b0 ), + .DPO(\blk00000003/blk00000530/sig000015c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000564 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b30 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015af ), + .DPO(\blk00000003/blk00000530/sig000015c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000563 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b31 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ae ), + .DPO(\blk00000003/blk00000530/sig000015c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000562 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b32 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ad ), + .DPO(\blk00000003/blk00000530/sig000015bf ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000561 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b34 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ab ), + .DPO(\blk00000003/blk00000530/sig000015bd ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000560 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b35 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015aa ), + .DPO(\blk00000003/blk00000530/sig000015bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055f ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b33 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ac ), + .DPO(\blk00000003/blk00000530/sig000015be ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055e ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b36 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a9 ), + .DPO(\blk00000003/blk00000530/sig000015bb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk0000055d ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b37 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a8 ), + .DPO(\blk00000003/blk00000530/sig000015ba ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk0000055c ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b38 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a7 ), + .DPO(\blk00000003/blk00000530/sig000015b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055b ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b39 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a6 ), + .DPO(\blk00000003/blk00000530/sig000015b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055a ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3a ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a5 ), + .DPO(\blk00000003/blk00000530/sig000015b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000559 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3b ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a4 ), + .DPO(\blk00000003/blk00000530/sig000015b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000558 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a2 ), + .DPO(\blk00000003/blk00000530/sig000015b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000557 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a1 ), + .DPO(\blk00000003/blk00000530/sig000015b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000556 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3c ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a3 ), + .DPO(\blk00000003/blk00000530/sig000015b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c4 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c3 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c2 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c1 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c0 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bf ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015be ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bd ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bc ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bb ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ba ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b9 ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b8 ), + .Q(\blk00000003/sig00000630 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b7 ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b6 ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b5 ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b4 ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b3 ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b2 ), + .Q(\blk00000003/sig00000b3f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b1 ), + .Q(\blk00000003/sig00000b40 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b0 ), + .Q(\blk00000003/sig00000b41 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015af ), + .Q(\blk00000003/sig00000b42 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ae ), + .Q(\blk00000003/sig00000b43 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ad ), + .Q(\blk00000003/sig00000b44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ac ), + .Q(\blk00000003/sig00000b45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ab ), + .Q(\blk00000003/sig00000b46 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015aa ), + .Q(\blk00000003/sig00000b47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a9 ), + .Q(\blk00000003/sig00000b48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a8 ), + .Q(\blk00000003/sig00000b49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a7 ), + .Q(\blk00000003/sig00000b4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a6 ), + .Q(\blk00000003/sig00000b4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a5 ), + .Q(\blk00000003/sig00000b4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a4 ), + .Q(\blk00000003/sig00000b4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a3 ), + .Q(\blk00000003/sig00000b4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a2 ), + .Q(\blk00000003/sig00000b4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a1 ), + .Q(\blk00000003/sig00000b50 ) + ); + GND \blk00000003/blk00000530/blk00000531 ( + .G(\blk00000003/blk00000530/sig000015a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000569/blk000005a1 ( + .I0(\blk00000003/sig000009f5 ), + .I1(ce), + .O(\blk00000003/blk00000569/sig00001628 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk000005a0 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b3f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001615 ), + .DPO(\blk00000003/blk00000569/sig00001627 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b40 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001614 ), + .DPO(\blk00000003/blk00000569/sig00001626 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059e ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b41 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001613 ), + .DPO(\blk00000003/blk00000569/sig00001625 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059d ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b42 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001612 ), + .DPO(\blk00000003/blk00000569/sig00001624 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk0000059c ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b43 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001611 ), + .DPO(\blk00000003/blk00000569/sig00001623 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk0000059b ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b44 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001610 ), + .DPO(\blk00000003/blk00000569/sig00001622 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059a ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b46 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160e ), + .DPO(\blk00000003/blk00000569/sig00001620 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000599 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b47 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160d ), + .DPO(\blk00000003/blk00000569/sig0000161f ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000598 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b45 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160f ), + .DPO(\blk00000003/blk00000569/sig00001621 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000597 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b48 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160c ), + .DPO(\blk00000003/blk00000569/sig0000161e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000596 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b49 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160b ), + .DPO(\blk00000003/blk00000569/sig0000161d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000595 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4a ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160a ), + .DPO(\blk00000003/blk00000569/sig0000161c ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000594 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4b ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001609 ), + .DPO(\blk00000003/blk00000569/sig0000161b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000593 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4c ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001608 ), + .DPO(\blk00000003/blk00000569/sig0000161a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000592 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4d ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001607 ), + .DPO(\blk00000003/blk00000569/sig00001619 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000591 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001605 ), + .DPO(\blk00000003/blk00000569/sig00001617 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000590 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b50 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001604 ), + .DPO(\blk00000003/blk00000569/sig00001616 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000058f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4e ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001606 ), + .DPO(\blk00000003/blk00000569/sig00001618 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001627 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001626 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001625 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001624 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001623 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001622 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001621 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001620 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161f ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161e ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161d ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000582 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000580 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001619 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001618 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001617 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001616 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001615 ), + .Q(\blk00000003/sig00000b51 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001614 ), + .Q(\blk00000003/sig00000b52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001613 ), + .Q(\blk00000003/sig00000b53 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001612 ), + .Q(\blk00000003/sig00000b54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000578 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001611 ), + .Q(\blk00000003/sig00000b55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001610 ), + .Q(\blk00000003/sig00000b56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000576 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160f ), + .Q(\blk00000003/sig00000b57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160e ), + .Q(\blk00000003/sig00000b58 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000574 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160d ), + .Q(\blk00000003/sig00000b59 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160c ), + .Q(\blk00000003/sig00000b5a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000572 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160b ), + .Q(\blk00000003/sig00000b5b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160a ), + .Q(\blk00000003/sig00000b5c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001609 ), + .Q(\blk00000003/sig00000b5d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001608 ), + .Q(\blk00000003/sig00000b5e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001607 ), + .Q(\blk00000003/sig00000b5f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001606 ), + .Q(\blk00000003/sig00000b60 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001605 ), + .Q(\blk00000003/sig00000b61 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001604 ), + .Q(\blk00000003/sig00000b62 ) + ); + GND \blk00000003/blk00000569/blk0000056a ( + .G(\blk00000003/blk00000569/sig00001603 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a2/blk000005c8 ( + .I0(\blk00000003/sig000009f6 ), + .I1(ce), + .O(\blk00000003/blk000005a2/sig00001667 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b51 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001666 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005c6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b52 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001665 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c5 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b53 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001664 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c4 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b54 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001663 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c3 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b55 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001662 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c2 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b56 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001661 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c1 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b58 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c0 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b59 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005bf ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b57 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001660 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005be ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5a ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bd ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5b ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165c ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005bc ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5c ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bb ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5d ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005ba ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5e ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001659 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005b9 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5f ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001658 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b8 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b61 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001656 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005b7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b62 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001655 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b60 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001666 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001665 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001664 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001663 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001662 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001661 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001660 ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165f ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165e ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165d ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165c ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165b ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165a ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001659 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001658 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001657 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001656 ), + .Q(\blk00000003/sig000004fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001655 ), + .Q(\blk00000003/sig000004ff ) + ); + GND \blk00000003/blk000005a2/blk000005a3 ( + .G(\blk00000003/blk000005a2/sig00001654 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005c9/blk000005db ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005c9/sig00001685 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005da ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/blk000005c9/sig00001684 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/blk000005c9/sig00001683 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d8 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/blk000005c9/sig00001682 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d7 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk000005c9/sig00001681 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d6 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk000005c9/sig00001680 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d5 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk000005c9/sig0000167f ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk000005c9/sig0000167e ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk000005c9/sig0000167d ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001684 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001683 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001682 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001681 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001680 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167f ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167e ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167d ), + .Q(\blk00000003/sig000004ed ) + ); + GND \blk00000003/blk000005c9/blk000005ca ( + .G(\blk00000003/blk000005c9/sig0000167c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005dc/blk000005ee ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000005dc/sig000016a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ed ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/blk000005dc/sig000016a2 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ec ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/blk000005dc/sig000016a1 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005eb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/blk000005dc/sig000016a0 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ea ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/blk000005dc/sig0000169f ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/blk000005dc/sig0000169e ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/blk000005dc/sig0000169d ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/blk000005dc/sig0000169c ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/blk000005dc/sig0000169b ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a2 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a1 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a0 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169f ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169e ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169d ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169c ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169b ), + .Q(\blk00000003/sig000004b5 ) + ); + GND \blk00000003/blk000005dc/blk000005dd ( + .G(\blk00000003/blk000005dc/sig0000169a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005ef/blk00000601 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005ef/sig000016c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk00000600 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/blk000005ef/sig000016c0 ), + .Q15(\NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005ff ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/blk000005ef/sig000016bf ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fe ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/blk000005ef/sig000016be ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fd ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/blk000005ef/sig000016bd ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fc ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/blk000005ef/sig000016bc ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fb ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/blk000005ef/sig000016bb ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fa ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/blk000005ef/sig000016ba ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005f9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/blk000005ef/sig000016b9 ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016c0 ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bf ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016be ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bd ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bc ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bb ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016ba ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016b9 ), + .Q(\blk00000003/sig0000053f ) + ); + GND \blk00000003/blk000005ef/blk000005f0 ( + .G(\blk00000003/blk000005ef/sig000016b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000602/blk00000614 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000602/sig000016df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000613 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/blk00000602/sig000016de ), + .Q15(\NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000612 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/blk00000602/sig000016dd ), + .Q15(\NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000611 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/blk00000602/sig000016dc ), + .Q15(\NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000610 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/blk00000602/sig000016db ), + .Q15(\NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/blk00000602/sig000016da ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/blk00000602/sig000016d9 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/blk00000602/sig000016d8 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/blk00000602/sig000016d7 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016de ), + .Q(\blk00000003/sig00000500 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dd ), + .Q(\blk00000003/sig00000501 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dc ), + .Q(\blk00000003/sig00000502 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016db ), + .Q(\blk00000003/sig00000503 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016da ), + .Q(\blk00000003/sig00000504 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d9 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d8 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d7 ), + .Q(\blk00000003/sig00000507 ) + ); + GND \blk00000003/blk00000602/blk00000603 ( + .G(\blk00000003/blk00000602/sig000016d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000615/blk00000627 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk00000615/sig000016fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000626 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk00000615/sig000016fc ), + .Q15(\NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000625 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk00000615/sig000016fb ), + .Q15(\NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000624 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk00000615/sig000016fa ), + .Q15(\NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000623 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk00000615/sig000016f9 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000622 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk00000615/sig000016f8 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000621 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk00000615/sig000016f7 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000620 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk00000615/sig000016f6 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk0000061f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk00000615/sig000016f5 ), + .Q15(\NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fc ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fb ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fa ), + .Q(\blk00000003/sig00000640 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f9 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f8 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f7 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000618 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f6 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f5 ), + .Q(\blk00000003/sig00000645 ) + ); + GND \blk00000003/blk00000615/blk00000616 ( + .G(\blk00000003/blk00000615/sig000016f4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000628/blk0000063a ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000628/sig0000171b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000639 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/blk00000628/sig0000171a ), + .Q15(\NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000638 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/blk00000628/sig00001719 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000637 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/blk00000628/sig00001718 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000636 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/blk00000628/sig00001717 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000635 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/blk00000628/sig00001716 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000634 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/blk00000628/sig00001715 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000633 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/blk00000628/sig00001714 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000632 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/blk00000628/sig00001713 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig0000171a ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001719 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001718 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001717 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001716 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001715 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001714 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001713 ), + .Q(\blk00000003/sig0000063d ) + ); + GND \blk00000003/blk00000628/blk00000629 ( + .G(\blk00000003/blk00000628/sig00001712 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000063b/blk0000064d ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000063b/sig00001739 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000063b/sig00001738 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000063b/sig00001737 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000063b/sig00001736 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000649 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000063b/sig00001735 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000648 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000063b/sig00001734 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000647 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000063b/sig00001733 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000646 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000063b/sig00001732 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000645 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000063b/sig00001731 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001738 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001737 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001736 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001735 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001734 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001733 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001732 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001731 ), + .Q(\blk00000003/sig00000727 ) + ); + GND \blk00000003/blk0000063b/blk0000063c ( + .G(\blk00000003/blk0000063b/sig00001730 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000064e/blk00000660 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk0000064e/sig00001757 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/blk0000064e/sig00001756 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/blk0000064e/sig00001755 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/blk0000064e/sig00001754 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/blk0000064e/sig00001753 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/blk0000064e/sig00001752 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/blk0000064e/sig00001751 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000659 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/blk0000064e/sig00001750 ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000658 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/blk0000064e/sig0000174f ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001756 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000656 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001755 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001754 ), + .Q(\blk00000003/sig0000071a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000654 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001753 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001752 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000652 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001751 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001750 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000650 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig0000174f ), + .Q(\blk00000003/sig0000071f ) + ); + GND \blk00000003/blk0000064e/blk0000064f ( + .G(\blk00000003/blk0000064e/sig0000174e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000661/blk00000673 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000661/sig00001775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000672 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000661/sig00001774 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000671 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000661/sig00001773 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000670 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000661/sig00001772 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000661/sig00001771 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000661/sig00001770 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000661/sig0000176f ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000661/sig0000176e ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000661/sig0000176d ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001774 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001773 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001772 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001771 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001770 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176f ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176e ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176d ), + .Q(\blk00000003/sig000005f3 ) + ); + GND \blk00000003/blk00000661/blk00000662 ( + .G(\blk00000003/blk00000661/sig0000176c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000674/blk00000686 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000674/sig00001793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000685 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/blk00000674/sig00001792 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000684 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/blk00000674/sig00001791 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000683 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/blk00000674/sig00001790 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000682 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/blk00000674/sig0000178f ), + .Q15(\NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000681 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/blk00000674/sig0000178e ), + .Q15(\NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000680 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/blk00000674/sig0000178d ), + .Q15(\NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/blk00000674/sig0000178c ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/blk00000674/sig0000178b ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001792 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001791 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001790 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178b ), + .Q(\blk00000003/sig000005eb ) + ); + GND \blk00000003/blk00000674/blk00000675 ( + .G(\blk00000003/blk00000674/sig0000178a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000687/blk00000699 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000687/sig000017b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000698 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000687/sig000017b0 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000697 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000687/sig000017af ), + .Q15(\NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000696 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000687/sig000017ae ), + .Q15(\NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000695 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000687/sig000017ad ), + .Q15(\NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000694 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000687/sig000017ac ), + .Q15(\NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000693 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000687/sig000017ab ), + .Q15(\NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000692 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000687/sig000017aa ), + .Q15(\NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000691 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000687/sig000017a9 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017b0 ), + .Q(\blk00000003/sig000006e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017af ), + .Q(\blk00000003/sig000006e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ae ), + .Q(\blk00000003/sig000006e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ad ), + .Q(\blk00000003/sig000006e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ac ), + .Q(\blk00000003/sig000006e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ab ), + .Q(\blk00000003/sig000006e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017aa ), + .Q(\blk00000003/sig000006e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017a9 ), + .Q(\blk00000003/sig000006e7 ) + ); + GND \blk00000003/blk00000687/blk00000688 ( + .G(\blk00000003/blk00000687/sig000017a8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000069a/blk000006ac ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk0000069a/sig000017cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006ab ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/blk0000069a/sig000017ce ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006aa ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/blk0000069a/sig000017cd ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/blk0000069a/sig000017cc ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/blk0000069a/sig000017cb ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/blk0000069a/sig000017ca ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/blk0000069a/sig000017c9 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/blk0000069a/sig000017c8 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/blk0000069a/sig000017c7 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ce ), + .Q(\blk00000003/sig000006d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cd ), + .Q(\blk00000003/sig000006d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cc ), + .Q(\blk00000003/sig000006da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cb ), + .Q(\blk00000003/sig000006db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ca ), + .Q(\blk00000003/sig000006dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c9 ), + .Q(\blk00000003/sig000006dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c8 ), + .Q(\blk00000003/sig000006de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c7 ), + .Q(\blk00000003/sig000006df ) + ); + GND \blk00000003/blk0000069a/blk0000069b ( + .G(\blk00000003/blk0000069a/sig000017c6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006ad/blk000006bf ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006ad/sig000017ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006be ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000006ad/sig000017ec ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000006ad/sig000017eb ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000006ad/sig000017ea ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000006ad/sig000017e9 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006ba ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000006ad/sig000017e8 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000006ad/sig000017e7 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000006ad/sig000017e6 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000006ad/sig000017e5 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ec ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017eb ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ea ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e9 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e8 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e7 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e6 ), + .Q(\blk00000003/sig000005a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e5 ), + .Q(\blk00000003/sig000005a1 ) + ); + GND \blk00000003/blk000006ad/blk000006ae ( + .G(\blk00000003/blk000006ad/sig000017e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006c0/blk000006d2 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006c0/sig0000180b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/blk000006c0/sig0000180a ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/blk000006c0/sig00001809 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cf ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/blk000006c0/sig00001808 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ce ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/blk000006c0/sig00001807 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cd ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/blk000006c0/sig00001806 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cc ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/blk000006c0/sig00001805 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cb ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/blk000006c0/sig00001804 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ca ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/blk000006c0/sig00001803 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig0000180a ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001809 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001808 ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001807 ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001806 ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001805 ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001804 ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001803 ), + .Q(\blk00000003/sig00000599 ) + ); + GND \blk00000003/blk000006c0/blk000006c1 ( + .G(\blk00000003/blk000006c0/sig00001802 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006d3/blk000006e5 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006d3/sig00001829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/blk000006d3/sig00001828 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk000006d3/sig00001827 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e2 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk000006d3/sig00001826 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e1 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk000006d3/sig00001825 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e0 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk000006d3/sig00001824 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006df ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk000006d3/sig00001823 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006de ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk000006d3/sig00001822 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006dd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk000006d3/sig00001821 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001828 ), + .Q(\blk00000003/sig000006a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001827 ), + .Q(\blk00000003/sig000006a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001826 ), + .Q(\blk00000003/sig000006a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001825 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001824 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001823 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001822 ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001821 ), + .Q(\blk00000003/sig000006a7 ) + ); + GND \blk00000003/blk000006d3/blk000006d4 ( + .G(\blk00000003/blk000006d3/sig00001820 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006e6/blk000006f8 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006e6/sig00001847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f7 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/blk000006e6/sig00001846 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f6 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/blk000006e6/sig00001845 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f5 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/blk000006e6/sig00001844 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f4 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/blk000006e6/sig00001843 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f3 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/blk000006e6/sig00001842 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f2 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/blk000006e6/sig00001841 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/blk000006e6/sig00001840 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/blk000006e6/sig0000183f ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001846 ), + .Q(\blk00000003/sig00000698 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001845 ), + .Q(\blk00000003/sig00000699 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001844 ), + .Q(\blk00000003/sig0000069a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001843 ), + .Q(\blk00000003/sig0000069b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001842 ), + .Q(\blk00000003/sig0000069c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001841 ), + .Q(\blk00000003/sig0000069d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001840 ), + .Q(\blk00000003/sig0000069e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig0000183f ), + .Q(\blk00000003/sig0000069f ) + ); + GND \blk00000003/blk000006e6/blk000006e7 ( + .G(\blk00000003/blk000006e6/sig0000183e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006f9/blk0000070b ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000006f9/sig00001865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk0000070a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000384 ), + .Q(\blk00000003/blk000006f9/sig00001864 ), + .Q15(\NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000709 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000385 ), + .Q(\blk00000003/blk000006f9/sig00001863 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000708 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000386 ), + .Q(\blk00000003/blk000006f9/sig00001862 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000707 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000387 ), + .Q(\blk00000003/blk000006f9/sig00001861 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000706 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000388 ), + .Q(\blk00000003/blk000006f9/sig00001860 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000705 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000389 ), + .Q(\blk00000003/blk000006f9/sig0000185f ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000704 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038a ), + .Q(\blk00000003/blk000006f9/sig0000185e ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000703 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038b ), + .Q(\blk00000003/blk000006f9/sig0000185d ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000702 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001864 ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000701 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001863 ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000700 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001862 ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001861 ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001860 ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185f ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185e ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185d ), + .Q(\blk00000003/sig0000054f ) + ); + GND \blk00000003/blk000006f9/blk000006fa ( + .G(\blk00000003/blk000006f9/sig0000185c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000070c/blk0000071e ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk0000070c/sig00001883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/blk0000070c/sig00001882 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/blk0000070c/sig00001881 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071b ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/blk0000070c/sig00001880 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071a ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/blk0000070c/sig0000187f ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000719 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/blk0000070c/sig0000187e ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000718 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/blk0000070c/sig0000187d ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000717 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/blk0000070c/sig0000187c ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000716 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/blk0000070c/sig0000187b ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001882 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001881 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001880 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187f ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187e ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187d ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187c ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187b ), + .Q(\blk00000003/sig00000547 ) + ); + GND \blk00000003/blk0000070c/blk0000070d ( + .G(\blk00000003/blk0000070c/sig0000187a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000071f/blk00000731 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000071f/sig000018a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000730 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d6 ), + .Q(\blk00000003/blk0000071f/sig000018a0 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d7 ), + .Q(\blk00000003/blk0000071f/sig0000189f ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d8 ), + .Q(\blk00000003/blk0000071f/sig0000189e ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d9 ), + .Q(\blk00000003/blk0000071f/sig0000189d ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003da ), + .Q(\blk00000003/blk0000071f/sig0000189c ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003db ), + .Q(\blk00000003/blk0000071f/sig0000189b ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dc ), + .Q(\blk00000003/blk0000071f/sig0000189a ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000729 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dd ), + .Q(\blk00000003/blk0000071f/sig00001899 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000728 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig000018a0 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189f ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000726 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189e ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189d ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000724 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189c ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189b ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000722 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189a ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig00001899 ), + .Q(\blk00000003/sig00000667 ) + ); + GND \blk00000003/blk0000071f/blk00000720 ( + .G(\blk00000003/blk0000071f/sig00001898 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000732/blk00000744 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000732/sig000018bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000743 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/blk00000732/sig000018be ), + .Q15(\NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000742 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/blk00000732/sig000018bd ), + .Q15(\NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000741 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/blk00000732/sig000018bc ), + .Q15(\NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000740 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/blk00000732/sig000018bb ), + .Q15(\NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073f ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/blk00000732/sig000018ba ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073e ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/blk00000732/sig000018b9 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/blk00000732/sig000018b8 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/blk00000732/sig000018b7 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018be ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bd ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bc ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000738 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bb ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018ba ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000736 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b9 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b8 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000734 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b7 ), + .Q(\blk00000003/sig0000065f ) + ); + GND \blk00000003/blk00000732/blk00000733 ( + .G(\blk00000003/blk00000732/sig000018b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000745/blk00000757 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk00000745/sig000018dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000756 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb3 ), + .Q(\blk00000003/blk00000745/sig000018dc ), + .Q15(\NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000755 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb4 ), + .Q(\blk00000003/blk00000745/sig000018db ), + .Q15(\NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000754 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb5 ), + .Q(\blk00000003/blk00000745/sig000018da ), + .Q15(\NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000753 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb6 ), + .Q(\blk00000003/blk00000745/sig000018d9 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000752 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb7 ), + .Q(\blk00000003/blk00000745/sig000018d8 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000751 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb8 ), + .Q(\blk00000003/blk00000745/sig000018d7 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000750 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb9 ), + .Q(\blk00000003/blk00000745/sig000018d6 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk0000074f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bba ), + .Q(\blk00000003/blk00000745/sig000018d5 ), + .Q15(\NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018dc ), + .Q(\blk00000003/sig00000384 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018db ), + .Q(\blk00000003/sig00000385 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018da ), + .Q(\blk00000003/sig00000386 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d9 ), + .Q(\blk00000003/sig00000387 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d8 ), + .Q(\blk00000003/sig00000388 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d7 ), + .Q(\blk00000003/sig00000389 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000748 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d6 ), + .Q(\blk00000003/sig0000038a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d5 ), + .Q(\blk00000003/sig0000038b ) + ); + GND \blk00000003/blk00000745/blk00000746 ( + .G(\blk00000003/blk00000745/sig000018d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000758/blk0000076a ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000758/sig000018fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000769 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbb ), + .Q(\blk00000003/blk00000758/sig000018fa ), + .Q15(\NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000768 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbc ), + .Q(\blk00000003/blk00000758/sig000018f9 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000767 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbd ), + .Q(\blk00000003/blk00000758/sig000018f8 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000766 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbe ), + .Q(\blk00000003/blk00000758/sig000018f7 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000765 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbf ), + .Q(\blk00000003/blk00000758/sig000018f6 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000764 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc0 ), + .Q(\blk00000003/blk00000758/sig000018f5 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000763 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc1 ), + .Q(\blk00000003/blk00000758/sig000018f4 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000762 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc2 ), + .Q(\blk00000003/blk00000758/sig000018f3 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018fa ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f9 ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f8 ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f7 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f6 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f5 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f4 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f3 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk00000758/blk00000759 ( + .G(\blk00000003/blk00000758/sig000018f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000076b/blk0000077d ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000076b/sig00001919 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc3 ), + .Q(\blk00000003/blk0000076b/sig00001918 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc4 ), + .Q(\blk00000003/blk0000076b/sig00001917 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc5 ), + .Q(\blk00000003/blk0000076b/sig00001916 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000779 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc6 ), + .Q(\blk00000003/blk0000076b/sig00001915 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000778 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc7 ), + .Q(\blk00000003/blk0000076b/sig00001914 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000777 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc8 ), + .Q(\blk00000003/blk0000076b/sig00001913 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000776 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc9 ), + .Q(\blk00000003/blk0000076b/sig00001912 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000775 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bca ), + .Q(\blk00000003/blk0000076b/sig00001911 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001918 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001917 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001916 ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001915 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001914 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001913 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001912 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001911 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk0000076b/blk0000076c ( + .G(\blk00000003/blk0000076b/sig00001910 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000077e/blk00000790 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000077e/sig00001937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcb ), + .Q(\blk00000003/blk0000077e/sig00001936 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcc ), + .Q(\blk00000003/blk0000077e/sig00001935 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcd ), + .Q(\blk00000003/blk0000077e/sig00001934 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bce ), + .Q(\blk00000003/blk0000077e/sig00001933 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcf ), + .Q(\blk00000003/blk0000077e/sig00001932 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd0 ), + .Q(\blk00000003/blk0000077e/sig00001931 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000789 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd1 ), + .Q(\blk00000003/blk0000077e/sig00001930 ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000788 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd2 ), + .Q(\blk00000003/blk0000077e/sig0000192f ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000787 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001936 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001935 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000785 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001934 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001933 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001932 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001931 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001930 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig0000192f ), + .Q(\blk00000003/sig000003d5 ) + ); + GND \blk00000003/blk0000077e/blk0000077f ( + .G(\blk00000003/blk0000077e/sig0000192e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000007c1/blk000007e7 ( + .I0(\blk00000003/sig0000030a ), + .I1(ce), + .O(\blk00000003/blk000007c1/sig00001974 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1/blk000007e6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001973 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001972 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e4 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001971 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e3 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001970 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e2 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e1 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e0 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007df ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007de ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dd ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dc ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001969 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007db ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001968 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007da ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001967 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d9 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001966 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d8 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001965 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d7 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001963 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001962 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001964 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001973 ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001972 ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001971 ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001970 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196f ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196e ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196d ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196c ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196b ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196a ), + .Q(\blk00000003/sig000001b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001969 ), + .Q(\blk00000003/sig000001ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001968 ), + .Q(\blk00000003/sig000001bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001967 ), + .Q(\blk00000003/sig000001bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001966 ), + .Q(\blk00000003/sig000001bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001965 ), + .Q(\blk00000003/sig000001be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001964 ), + .Q(\blk00000003/sig000001bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001963 ), + .Q(\blk00000003/sig000001c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001962 ), + .Q(\blk00000003/sig000001c1 ) + ); + GND \blk00000003/blk000007c1/blk000007c2 ( + .G(\blk00000003/blk000007c1/sig00001961 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo new file mode 100644 index 000000000..eb615e1ee --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec1 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec1.v when simulating +// the core, hbdec1. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco new file mode 100644 index 000000000..5487ee44b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 9 20:43:38 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx150t +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=7 +CSET component_name=hbdec1 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=64 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 3310ee85 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif new file mode 100644 index 000000000..f19636daf --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_0.mif @@ -0,0 +1,5 @@ +111111111111000010 +000000000011000010 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif new file mode 100644 index 000000000..07e316dd3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_1.mif @@ -0,0 +1,5 @@ +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif new file mode 100644 index 000000000..da84300d6 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_2.mif @@ -0,0 +1,5 @@ +111111101000011111 +000000100110101110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif new file mode 100644 index 000000000..ea92ca6c2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_3.mif @@ -0,0 +1,5 @@ +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif new file mode 100644 index 000000000..9e9303211 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_4.mif @@ -0,0 +1,5 @@ +111101110000011101 +000011100100101000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif new file mode 100644 index 000000000..e0c3f05fe --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto0_5.mif @@ -0,0 +1,5 @@ +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt new file mode 100644 index 000000000..2bd535f92 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_flist.txt @@ -0,0 +1,22 @@ +# Output products list for +hbdec1.asy +hbdec1.gise +hbdec1.mif +hbdec1.ngc +hbdec1.v +hbdec1.veo +hbdec1.xco +hbdec1.xise +hbdec1COEFF_auto0_0.mif +hbdec1COEFF_auto0_1.mif +hbdec1COEFF_auto0_2.mif +hbdec1COEFF_auto0_3.mif +hbdec1COEFF_auto0_4.mif +hbdec1COEFF_auto0_5.mif +hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +hbdec1_flist.txt +hbdec1_readme.txt +hbdec1_reload_addrfilt_decode_rom.mif +hbdec1_reload_order.txt +hbdec1_xmdf.tcl +hbdec1filt_decode_rom.mif diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt new file mode 100644 index 000000000..0398bd92f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_readme.txt @@ -0,0 +1,78 @@ +The following files were generated for 'hbdec1' in directory +/disk2/ianb/ettus/fpgadev2/fpgadev/usrp3/top/b200/coregen_dsp/ + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec1_flist.txt + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec1.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec1.ngc + * hbdec1.v + * hbdec1.veo + * hbdec1COEFF_auto0_0.mif + * hbdec1COEFF_auto0_1.mif + * hbdec1COEFF_auto0_2.mif + * hbdec1COEFF_auto0_3.mif + * hbdec1COEFF_auto0_4.mif + * hbdec1COEFF_auto0_5.mif + * hbdec1COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec1_reload_addrfilt_decode_rom.mif + * hbdec1filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec1.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec1.asy + * hbdec1.mif + * hbdec1_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec1_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec1.gise + * hbdec1.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec1_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec1_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt new file mode 100644 index 000000000..11f12084f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 20 +Reload index 1 = Index 22 +Reload index 2 = Index 16 +Reload index 3 = Index 18 +Reload index 4 = Index 12 +Reload index 5 = Index 14 +Reload index 6 = Index 8 +Reload index 7 = Index 10 +Reload index 8 = Index 4 +Reload index 9 = Index 6 +Reload index 10 = Index 0 +Reload index 11 = Index 2 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl new file mode 100644 index 000000000..7aa8f91c3 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1_xmdf.tcl @@ -0,0 +1,111 @@ +# The package naming convention is _xmdf +package provide hbdec1_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec1_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec1_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1 +} +# ::hbdec1_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec1_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec1filt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy new file mode 100644 index 000000000..e9bd5ec37 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec2 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..ba9528546 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$37:2~753-Xnzd}foo8#5+421).97 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2we84o=:182M5c82we84o<:182M5c82we84o;:182M5c82we8l:i:182M5c82we8l;?:182M5c82we8l;>:182M5c82we8l;=:182M5c82we8l;<:182M5c82we8l;;:182M5c82we8l;::182M5c82we8l;9:182M5c82we8l;8:182M5c82we8l;7:182M5c82we8o><:182M5c82we8o>;:182M5c82we8o>::182M5c82we8o>9:182M5c82we8o>8:182M5c82we8o>7:182M5c82we8o>6:182M5c82we8o>n:182M5c82we8o>m:182M5c82we8o>l:182M5c82we8ol8:182M5c82we8ol7:182M5c82we8ol6:182M5c82we8oln:182M5c82we8olm:182M5c82we8oll:182M5c82we8olk:182M5c82we8olj:182M5c82we8oli:182M5c82we8om?:182M5c82we8k8<:182M5c82we8k8;:182M5c82we8k8::182M5c82we8k89:182M5c82we8k88:182M5c82we8k87:182M5c82we8k86:182M5c82we8k8n:182M5c82we8k8m:182M5c82we8k8l:182M5c82we8k8k:182M5c82we8k8j:182M5c82we8k8i:182M5c82we8k9?:182M5c82we8k9>:182M5c82we8k9=:182M5c82we8k9<:182M5c82we8k9;:182M5c82we8k9::182M5c82we8k99:182M5c82wvqpNOCz5;40_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000024_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000013_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig0000093c ), + .Q15(\NLW_blk00000003/blk000007ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/sig000002ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig0000093b ), + .Q15(\NLW_blk00000003/blk000007fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e4 ), + .Q(\blk00000003/sig0000093a ), + .Q15(\NLW_blk00000003/blk000007fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/sig00000939 ), + .Q15(\NLW_blk00000003/blk000007f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e6 ), + .Q(\blk00000003/sig00000938 ), + .Q15(\NLW_blk00000003/blk000007f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e0 ), + .Q(\blk00000003/sig00000937 ), + .Q15(\NLW_blk00000003/blk000007f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000936 ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008de ), + .Q(\blk00000003/sig00000936 ), + .Q15(\NLW_blk00000003/blk000007f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000935 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e2 ), + .Q(\blk00000003/sig00000935 ), + .Q15(\NLW_blk00000003/blk000007f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000934 ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/sig00000934 ), + .Q15(\NLW_blk00000003/blk000007ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000933 ), + .Q(\blk00000003/sig00000249 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008da ), + .Q(\blk00000003/sig00000933 ), + .Q15(\NLW_blk00000003/blk000007ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000932 ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008dc ), + .Q(\blk00000003/sig00000932 ), + .Q15(\NLW_blk00000003/blk000007eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000931 ), + .Q(\blk00000003/sig00000247 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/sig00000931 ), + .Q15(\NLW_blk00000003/blk000007e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .Q(\blk00000003/sig00000246 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/sig00000930 ), + .Q15(\NLW_blk00000003/blk000007e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092f ), + .Q(\blk00000003/sig00000248 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d8 ), + .Q(\blk00000003/sig0000092f ), + .Q15(\NLW_blk00000003/blk000007e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092e ), + .Q(\blk00000003/sig00000245 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/sig0000092e ), + .Q15(\NLW_blk00000003/blk000007e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .Q(\blk00000003/sig00000244 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/sig0000092d ), + .Q15(\NLW_blk00000003/blk000007e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092c ), + .Q(\blk00000003/sig00000243 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/sig0000092c ), + .Q15(\NLW_blk00000003/blk000007df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092b ), + .Q(\blk00000003/sig00000242 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/sig0000092b ), + .Q15(\NLW_blk00000003/blk000007dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .Q(\blk00000003/sig00000210 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007db ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c6 ), + .Q(\blk00000003/sig0000092a ), + .Q15(\NLW_blk00000003/blk000007db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000929 ), + .Q(\blk00000003/sig0000020f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c4 ), + .Q(\blk00000003/sig00000929 ), + .Q15(\NLW_blk00000003/blk000007d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000928 ), + .Q(\blk00000003/sig00000211 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/sig00000928 ), + .Q15(\NLW_blk00000003/blk000007d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .Q(\blk00000003/sig0000020d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008bc ), + .Q(\blk00000003/sig00000927 ), + .Q15(\NLW_blk00000003/blk000007d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000926 ), + .Q(\blk00000003/sig0000020c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c0 ), + .Q(\blk00000003/sig00000926 ), + .Q15(\NLW_blk00000003/blk000007d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000925 ), + .Q(\blk00000003/sig0000020e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c2 ), + .Q(\blk00000003/sig00000925 ), + .Q15(\NLW_blk00000003/blk000007d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .Q(\blk00000003/sig0000020a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b6 ), + .Q(\blk00000003/sig00000924 ), + .Q15(\NLW_blk00000003/blk000007cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000923 ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ba ), + .Q(\blk00000003/sig00000923 ), + .Q15(\NLW_blk00000003/blk000007cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000922 ), + .Q(\blk00000003/sig0000020b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008be ), + .Q(\blk00000003/sig00000922 ), + .Q15(\NLW_blk00000003/blk000007cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b8 ), + .Q(\blk00000003/sig00000921 ), + .Q15(\NLW_blk00000003/blk000007c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000920 ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/sig00000920 ), + .Q15(\NLW_blk00000003/blk000007c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091f ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b4 ), + .Q(\blk00000003/sig0000091f ), + .Q15(\NLW_blk00000003/blk000007c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091e ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b2 ), + .Q(\blk00000003/sig0000091e ), + .Q15(\NLW_blk00000003/blk000007c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091d ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/sig0000091d ), + .Q15(\NLW_blk00000003/blk000007c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091c ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/sig0000091c ), + .Q15(\NLW_blk00000003/blk000007bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091b ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/sig0000091b ), + .Q15(\NLW_blk00000003/blk000007bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091a ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/sig0000091a ), + .Q15(\NLW_blk00000003/blk000007bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000919 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/sig00000919 ), + .Q15(\NLW_blk00000003/blk000007b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000918 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/sig00000918 ), + .Q15(\NLW_blk00000003/blk000007b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000917 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/sig00000917 ), + .Q15(\NLW_blk00000003/blk000007b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000916 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/sig00000916 ), + .Q15(\NLW_blk00000003/blk000007b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000915 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/sig00000915 ), + .Q15(\NLW_blk00000003/blk000007b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000914 ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007af ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/sig00000914 ), + .Q15(\NLW_blk00000003/blk000007af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000913 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/sig00000913 ), + .Q15(\NLW_blk00000003/blk000007ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000912 ), + .Q(\blk00000003/sig00000177 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/sig00000912 ), + .Q15(\NLW_blk00000003/blk000007ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000911 ), + .Q(\blk00000003/sig00000176 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/sig00000911 ), + .Q15(\NLW_blk00000003/blk000007a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000910 ), + .Q(\blk00000003/sig00000174 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/sig00000910 ), + .Q15(\NLW_blk00000003/blk000007a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090f ), + .Q(\blk00000003/sig00000173 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/sig0000090f ), + .Q15(\NLW_blk00000003/blk000007a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090e ), + .Q(\blk00000003/sig00000175 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/sig0000090e ), + .Q15(\NLW_blk00000003/blk000007a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090d ), + .Q(\blk00000003/sig00000171 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/sig0000090d ), + .Q15(\NLW_blk00000003/blk000007a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090c ), + .Q(\blk00000003/sig00000170 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/sig0000090c ), + .Q15(\NLW_blk00000003/blk0000079f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090b ), + .Q(\blk00000003/sig00000172 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/sig0000090b ), + .Q15(\NLW_blk00000003/blk0000079d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090a ), + .Q(\blk00000003/sig0000068c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig0000090a ), + .Q15(\NLW_blk00000003/blk0000079b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000909 ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000799 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000909 ), + .Q15(\NLW_blk00000003/blk00000799_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000908 ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000797 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000908 ), + .Q15(\NLW_blk00000003/blk00000797_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000907 ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000795 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000907 ), + .Q15(\NLW_blk00000003/blk00000795_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000906 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000793 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000906 ), + .Q15(\NLW_blk00000003/blk00000793_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000905 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000791 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000905 ), + .Q15(\NLW_blk00000003/blk00000791_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000904 ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000904 ), + .Q15(\NLW_blk00000003/blk0000078f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000903 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000903 ), + .Q15(\NLW_blk00000003/blk0000078d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000902 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000289 ), + .Q(\blk00000003/sig00000902 ), + .Q15(\NLW_blk00000003/blk0000078b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000901 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000789 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000901 ), + .Q15(\NLW_blk00000003/blk00000789_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000788 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000900 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000787 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000287 ), + .Q(\blk00000003/sig00000900 ), + .Q15(\NLW_blk00000003/blk00000787_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ff ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000785 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000286 ), + .Q(\blk00000003/sig000008ff ), + .Q15(\NLW_blk00000003/blk00000785_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fe ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000783 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000288 ), + .Q(\blk00000003/sig000008fe ), + .Q15(\NLW_blk00000003/blk00000783_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fd ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000781 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000284 ), + .Q(\blk00000003/sig000008fd ), + .Q15(\NLW_blk00000003/blk00000781_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fc ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000283 ), + .Q(\blk00000003/sig000008fc ), + .Q15(\NLW_blk00000003/blk0000077f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fb ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000285 ), + .Q(\blk00000003/sig000008fb ), + .Q15(\NLW_blk00000003/blk0000077d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fa ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000008fa ), + .Q15(\NLW_blk00000003/blk0000077b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f9 ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000779 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000008f9 ), + .Q15(\NLW_blk00000003/blk00000779_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000778 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f8 ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000777 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000282 ), + .Q(\blk00000003/sig000008f8 ), + .Q15(\NLW_blk00000003/blk00000777_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000776 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000775 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000008f7 ), + .Q15(\NLW_blk00000003/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000773 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000008f6 ), + .Q15(\NLW_blk00000003/blk00000773_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000771 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000008f5 ), + .Q15(\NLW_blk00000003/blk00000771_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000008f4 ), + .Q15(\NLW_blk00000003/blk0000076f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000008f3 ), + .Q15(\NLW_blk00000003/blk0000076d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000008f2 ), + .Q15(\NLW_blk00000003/blk0000076b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000769 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000008f1 ), + .Q15(\NLW_blk00000003/blk00000769_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000767 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000008f0 ), + .Q15(\NLW_blk00000003/blk00000767_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000765 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000008ef ), + .Q15(\NLW_blk00000003/blk00000765_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000763 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000008ee ), + .Q15(\NLW_blk00000003/blk00000763_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000761 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000008ed ), + .Q15(\NLW_blk00000003/blk00000761_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000075f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000075d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000075b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000759 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig000008e9 ), + .Q15(\NLW_blk00000003/blk00000759_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e7 ), + .Q(\blk00000003/sig000008e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000757 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig000008e7 ), + .Q15(\NLW_blk00000003/blk00000757_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e5 ), + .Q(\blk00000003/sig000008e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000755 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig000008e5 ), + .Q15(\NLW_blk00000003/blk00000755_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e3 ), + .Q(\blk00000003/sig000008e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000753 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig000008e3 ), + .Q15(\NLW_blk00000003/blk00000753_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e1 ), + .Q(\blk00000003/sig000008e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000751 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig000008e1 ), + .Q15(\NLW_blk00000003/blk00000751_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008df ), + .Q(\blk00000003/sig000008e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig000008df ), + .Q15(\NLW_blk00000003/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008dd ), + .Q(\blk00000003/sig000008de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000074d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008db ), + .Q(\blk00000003/sig000008dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig000008db ), + .Q15(\NLW_blk00000003/blk0000074b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d9 ), + .Q(\blk00000003/sig000008da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000749 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000749_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/sig000008d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000747 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000747_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/sig000008d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000745_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/sig000008d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000743 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000743_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/sig000008d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000741 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000741_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/sig000008d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000008cf ), + .Q15(\NLW_blk00000003/blk0000073f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/sig000008ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig000008cd ), + .Q15(\NLW_blk00000003/blk0000073d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/sig000008cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig000008cb ), + .Q15(\NLW_blk00000003/blk0000073b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/sig000008ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000739 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000739_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c7 ), + .Q(\blk00000003/sig000008c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000737 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000737_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c5 ), + .Q(\blk00000003/sig000008c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000735 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000735_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c3 ), + .Q(\blk00000003/sig000008c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000733 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig000008c3 ), + .Q15(\NLW_blk00000003/blk00000733_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c1 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000731 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig000008c1 ), + .Q15(\NLW_blk00000003/blk00000731_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bf ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig000008bf ), + .Q15(\NLW_blk00000003/blk0000072f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bd ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig000008bd ), + .Q15(\NLW_blk00000003/blk0000072d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bb ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig000008bb ), + .Q15(\NLW_blk00000003/blk0000072b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b9 ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000729 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig000008b9 ), + .Q15(\NLW_blk00000003/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000728 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b7 ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000727 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig000008b7 ), + .Q15(\NLW_blk00000003/blk00000727_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000726 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b5 ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000725 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig000008b5 ), + .Q15(\NLW_blk00000003/blk00000725_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000724 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b3 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000723 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig000008b3 ), + .Q15(\NLW_blk00000003/blk00000723_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000722 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000721 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig000008b1 ), + .Q15(\NLW_blk00000003/blk00000721_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000720 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig000008af ), + .Q15(\NLW_blk00000003/blk0000071f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig000008ad ), + .Q15(\NLW_blk00000003/blk0000071d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig000008ab ), + .Q15(\NLW_blk00000003/blk0000071b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000719 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig000008a9 ), + .Q15(\NLW_blk00000003/blk00000719_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000718 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000717 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig000008a7 ), + .Q15(\NLW_blk00000003/blk00000717_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000716 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000715 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig000008a5 ), + .Q15(\NLW_blk00000003/blk00000715_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000714 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000713 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig000008a3 ), + .Q15(\NLW_blk00000003/blk00000713_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000712 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000711 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig000008a1 ), + .Q15(\NLW_blk00000003/blk00000711_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000710 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000089f ), + .Q15(\NLW_blk00000003/blk0000070f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000070d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000070b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000709 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000899 ), + .Q15(\NLW_blk00000003/blk00000709_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000708 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000707 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000897 ), + .Q15(\NLW_blk00000003/blk00000707_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000706 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000705 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000895 ), + .Q15(\NLW_blk00000003/blk00000705_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000704 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000703 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000893 ), + .Q15(\NLW_blk00000003/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000702 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000701 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000891 ), + .Q15(\NLW_blk00000003/blk00000701_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000700 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000088f ), + .Q15(\NLW_blk00000003/blk000006ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fe ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig0000088d ), + .Q15(\NLW_blk00000003/blk000006fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fc ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000088b ), + .Q15(\NLW_blk00000003/blk000006fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fa ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000889 ), + .Q15(\NLW_blk00000003/blk000006f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067b ), + .Q(\blk00000003/sig00000888 ), + .Q15(\NLW_blk00000003/blk000006f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/sig000006dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000887 ), + .Q15(\NLW_blk00000003/blk000006f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067c ), + .Q(\blk00000003/sig00000886 ), + .Q15(\NLW_blk00000003/blk000006f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/sig000006da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000885 ), + .Q15(\NLW_blk00000003/blk000006f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ef ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000884 ), + .Q15(\NLW_blk00000003/blk000006ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ed ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000883 ), + .Q15(\NLW_blk00000003/blk000006ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/sig000006d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006eb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000882 ), + .Q15(\NLW_blk00000003/blk000006eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000881 ), + .Q15(\NLW_blk00000003/blk000006e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/sig000006d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000880 ), + .Q15(\NLW_blk00000003/blk000006e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig0000087f ), + .Q15(\NLW_blk00000003/blk000006e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/sig000006d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig0000087e ), + .Q15(\NLW_blk00000003/blk000006e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/sig000006d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig0000087d ), + .Q15(\NLW_blk00000003/blk000006e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/sig000006d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006df ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig0000087c ), + .Q15(\NLW_blk00000003/blk000006df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/sig000006d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig0000087b ), + .Q15(\NLW_blk00000003/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/sig000006cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006db ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig0000087a ), + .Q15(\NLW_blk00000003/blk000006db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/sig000006d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000879 ), + .Q15(\NLW_blk00000003/blk000006d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/sig000006cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000878 ), + .Q15(\NLW_blk00000003/blk000006d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/sig0000076c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000877 ), + .Q15(\NLW_blk00000003/blk000006d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/sig000006ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000876 ), + .Q15(\NLW_blk00000003/blk000006d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/sig0000076b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000875 ), + .Q15(\NLW_blk00000003/blk000006d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/sig0000076a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000874 ), + .Q15(\NLW_blk00000003/blk000006cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/sig00000769 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000873 ), + .Q15(\NLW_blk00000003/blk000006cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/sig00000768 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000872 ), + .Q15(\NLW_blk00000003/blk000006cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/sig00000766 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000871 ), + .Q15(\NLW_blk00000003/blk000006c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/sig00000765 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000870 ), + .Q15(\NLW_blk00000003/blk000006c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/sig00000767 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig0000086f ), + .Q15(\NLW_blk00000003/blk000006c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig0000086e ), + .Q15(\NLW_blk00000003/blk000006c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/sig000006fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig0000086d ), + .Q15(\NLW_blk00000003/blk000006c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/sig000006fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig0000086c ), + .Q15(\NLW_blk00000003/blk000006bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/sig000006f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig0000086b ), + .Q15(\NLW_blk00000003/blk000006bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig0000086a ), + .Q15(\NLW_blk00000003/blk000006bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000869 ), + .Q15(\NLW_blk00000003/blk000006b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/sig000006f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000868 ), + .Q15(\NLW_blk00000003/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000867 ), + .Q15(\NLW_blk00000003/blk000006b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/sig000006f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000866 ), + .Q15(\NLW_blk00000003/blk000006b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000865 ), + .Q15(\NLW_blk00000003/blk000006b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006af ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000864 ), + .Q15(\NLW_blk00000003/blk000006af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/sig000006f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000863 ), + .Q15(\NLW_blk00000003/blk000006ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/sig000006f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ab ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000862 ), + .Q15(\NLW_blk00000003/blk000006ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/sig000006ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000861 ), + .Q15(\NLW_blk00000003/blk000006a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000860 ), + .Q15(\NLW_blk00000003/blk000006a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000085f ), + .Q15(\NLW_blk00000003/blk000006a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/sig0000077b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig0000085e ), + .Q15(\NLW_blk00000003/blk000006a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/sig0000077a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig0000085d ), + .Q15(\NLW_blk00000003/blk000006a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/sig0000077c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069f ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig0000085c ), + .Q15(\NLW_blk00000003/blk0000069f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/sig00000779 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069d ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig0000085b ), + .Q15(\NLW_blk00000003/blk0000069d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/sig00000778 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069b ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000085a ), + .Q15(\NLW_blk00000003/blk0000069b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/sig00000777 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000699 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000859 ), + .Q15(\NLW_blk00000003/blk00000699_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/sig00000776 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000697 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig00000858 ), + .Q15(\NLW_blk00000003/blk00000697_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/sig00000397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000695 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig00000857 ), + .Q15(\NLW_blk00000003/blk00000695_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000694 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/sig00000398 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000693 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000037e ), + .Q(\blk00000003/sig00000856 ), + .Q15(\NLW_blk00000003/blk00000693_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000692 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/sig00000775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000691 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig00000855 ), + .Q15(\NLW_blk00000003/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/sig0000071e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000854 ), + .Q15(\NLW_blk00000003/blk0000068f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000853 ), + .Q15(\NLW_blk00000003/blk0000068d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a1 ), + .Q(\blk00000003/sig00000852 ), + .Q15(\NLW_blk00000003/blk0000068b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000689 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000851 ), + .Q15(\NLW_blk00000003/blk00000689_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000688 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig0000071a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000850 ), + .Q15(\NLW_blk00000003/blk00000687_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000686 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig0000071c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000685 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000084f ), + .Q15(\NLW_blk00000003/blk00000685_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000684 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000683 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000683_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000682 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000718 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000681 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000681_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000680 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig0000084c ), + .Q15(\NLW_blk00000003/blk0000067f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000716 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig0000084b ), + .Q15(\NLW_blk00000003/blk0000067d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000714 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig0000084a ), + .Q15(\NLW_blk00000003/blk0000067b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000679 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000679_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000677 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000677_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000675 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000675_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000710 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000673 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000673_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000712 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000671 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000671_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig0000070e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000844 ), + .Q15(\NLW_blk00000003/blk0000066f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000843 ), + .Q15(\NLW_blk00000003/blk0000066d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000842 ), + .Q15(\NLW_blk00000003/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig000002b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000669 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b2 ), + .Q(\blk00000003/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000669_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig0000068b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000667 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000667_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000786 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000665 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000665_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000664 ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000353 ) + ); + INV \blk00000003/blk00000663 ( + .I(\blk00000003/sig0000035c ), + .O(\blk00000003/sig0000034c ) + ); + INV \blk00000003/blk00000662 ( + .I(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000352 ) + ); + INV \blk00000003/blk00000661 ( + .I(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000361 ) + ); + INV \blk00000003/blk00000660 ( + .I(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000080d ) + ); + INV \blk00000003/blk0000065f ( + .I(\blk00000003/sig00000317 ), + .O(\blk00000003/sig00000364 ) + ); + INV \blk00000003/blk0000065e ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000034d ) + ); + INV \blk00000003/blk0000065d ( + .I(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000318 ) + ); + INV \blk00000003/blk0000065c ( + .I(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000166 ) + ); + INV \blk00000003/blk0000065b ( + .I(\blk00000003/sig00000159 ), + .O(\blk00000003/sig00000297 ) + ); + INV \blk00000003/blk0000065a ( + .I(\blk00000003/sig00000163 ), + .O(\blk00000003/sig00000164 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000659 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig0000031c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000658 ( + .I0(\blk00000003/sig0000031d ), + .I1(\blk00000003/sig00000311 ), + .I2(\blk00000003/sig00000320 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000309 ), + .O(\blk00000003/sig00000314 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000657 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000309 ), + .O(\blk00000003/sig0000031b ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000656 ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000320 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031a ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000655 ( + .I0(\blk00000003/sig0000035c ), + .I1(ce), + .I2(\blk00000003/sig00000311 ), + .I3(\blk00000003/sig000002ea ), + .O(\blk00000003/sig0000083e ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000654 ( + .I0(\blk00000003/sig00000363 ), + .I1(ce), + .I2(\blk00000003/sig0000030f ), + .I3(\blk00000003/sig00000354 ), + .O(\blk00000003/sig0000083d ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000653 ( + .I0(\blk00000003/sig00000810 ), + .I1(ce), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig0000083b ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000652 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000083a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000651 ( + .I0(ce), + .I1(\blk00000003/sig00000320 ), + .I2(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000839 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000650 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig00000366 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000083c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064f ( + .C(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig0000035c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064e ( + .C(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000363 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .D(\blk00000003/sig0000083c ), + .R(sclr), + .Q(\blk00000003/sig00000812 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064c ( + .C(clk), + .D(\blk00000003/sig0000083b ), + .R(sclr), + .Q(\blk00000003/sig00000810 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064b ( + .I0(\blk00000003/sig00000798 ), + .O(\blk00000003/sig00000793 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064a ( + .I0(\blk00000003/sig00000797 ), + .O(\blk00000003/sig00000790 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000649 ( + .I0(\blk00000003/sig00000796 ), + .O(\blk00000003/sig0000078d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000648 ( + .I0(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000078a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000647 ( + .I0(\blk00000003/sig00000394 ), + .O(\blk00000003/sig00000395 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000646 ( + .I0(\blk00000003/sig00000390 ), + .O(\blk00000003/sig00000391 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000645 ( + .I0(\blk00000003/sig0000037c ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000644 ( + .I0(\blk00000003/sig00000812 ), + .O(\blk00000003/sig0000036c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000643 ( + .I0(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000642 ( + .I0(\blk00000003/sig00000339 ), + .O(\blk00000003/sig0000033a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000641 ( + .I0(\blk00000003/sig0000032b ), + .O(\blk00000003/sig00000329 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000640 ( + .I0(\blk00000003/sig00000324 ), + .O(\blk00000003/sig00000322 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000063f ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000063e ( + .I0(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000167 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000807 ), + .R(sclr), + .Q(\blk00000003/sig0000080c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000804 ), + .R(sclr), + .Q(\blk00000003/sig0000080b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000801 ), + .R(sclr), + .Q(\blk00000003/sig0000080a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fe ), + .R(sclr), + .Q(\blk00000003/sig00000809 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fb ), + .R(sclr), + .Q(\blk00000003/sig00000808 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000788 ), + .R(sclr), + .Q(\blk00000003/sig00000799 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000794 ), + .R(sclr), + .Q(\blk00000003/sig00000798 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000791 ), + .R(sclr), + .Q(\blk00000003/sig00000797 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078e ), + .R(sclr), + .Q(\blk00000003/sig00000796 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078b ), + .S(sclr), + .Q(\blk00000003/sig00000795 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000396 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000394 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000393 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000390 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000389 ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038c ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000381 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000387 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000384 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000386 ) + ); + FDR \blk00000003/blk0000062d ( + .C(clk), + .D(\blk00000003/sig0000083a ), + .R(ce), + .Q(\blk00000003/sig00000813 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .S(sclr), + .Q(\blk00000003/sig0000037c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037a ), + .R(sclr), + .Q(\blk00000003/sig0000037b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000374 ), + .R(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDR \blk00000003/blk00000628 ( + .C(clk), + .D(\blk00000003/sig00000839 ), + .R(ce), + .Q(\blk00000003/sig00000811 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033f ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig0000033d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033c ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000331 ), + .R(coef_ld), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(coef_ld), + .Q(\blk00000003/sig00000336 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032d ), + .R(sclr), + .Q(\blk00000003/sig0000032e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000622 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032a ), + .R(sclr), + .Q(\blk00000003/sig0000032b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000326 ), + .R(coef_ld), + .Q(\blk00000003/sig00000327 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000620 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .R(coef_ld), + .Q(\blk00000003/sig00000324 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000061f ( + .I0(\blk00000003/sig00000163 ), + .I1(sclr), + .O(\blk00000003/sig00000838 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000061e ( + .C(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000163 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015b ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061c ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig00000809 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fd ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig0000080a ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000800 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000619 ( + .I0(\blk00000003/sig0000080b ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000803 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig0000080c ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig00000806 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig000002ae ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007f8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig000007f6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig000007f7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000614 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig000007f5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000613 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig000007f3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig000007f4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000611 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig000007f2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000610 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig000007f0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060f ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig000007f1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060e ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig000007ef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig000007ed ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig000007ee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig000007ec ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig000007ea ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig000007eb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig000007e9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig000007e7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig000007e8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig000007e6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig000007e4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig000007e5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig000007e3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig000007e1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig000007e2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ff ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig000007e0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fe ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig000007de ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig000007df ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig000007dd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig000007db ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fa ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig000007dc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig000007da ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000837 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig000007d8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fc ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig000007d9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000836 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig000007d7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000835 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig000007d5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000834 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig000007d6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000833 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig000007d4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000832 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig000007d2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000831 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig000007d3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000830 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig000007d1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ef ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082f ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig000007cf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ee ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082e ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig000007d0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ed ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082d ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig000007ce ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ec ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082c ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig000007cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005eb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082b ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig000007cd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ea ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082a ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig000007cb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000829 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig000007ca ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig000007c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000828 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig000007c9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig000007c7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig000007c5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig000007c6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig000007c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig000007c2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig000007c3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig000007c1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig000007bf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig000007c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig000007be ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig000007bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig000007bd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig000007bb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig000007b9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig000007ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig000007b8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig000007b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig000007b7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig000007b5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig000007b3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig000007b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig000007b2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig000007b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig000007b1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig000007af ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig000007ad ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig000007ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig000007ac ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000152 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig000007aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig000007ab ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000827 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig000007a9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000826 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig000007a7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000825 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig000007a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000824 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig000007a6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000823 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig000007a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000822 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig000007a5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000821 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig000007a3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000820 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig000007a1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081f ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig000007a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081e ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig000007a0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081d ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000079e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081c ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000079f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081b ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000079d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081a ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig0000079b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000819 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000079c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000818 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig0000079a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig00000799 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000787 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b7 ( + .I0(ce), + .I1(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig00000817 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b6 ( + .I0(ce), + .I1(\blk00000003/sig0000067a ), + .O(\blk00000003/sig00000785 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5 ( + .I0(ce), + .I1(\blk00000003/sig00000816 ), + .O(\blk00000003/sig00000744 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000815 ), + .O(\blk00000003/sig00000743 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig0000038d ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig0000038b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig0000038e ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000388 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig00000397 ), + .I1(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000385 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig00000386 ), + .I1(\blk00000003/sig00000397 ), + .I2(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000383 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig00000387 ), + .I1(\blk00000003/sig00000814 ), + .I2(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000380 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005ae ( + .I0(sclr), + .I1(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000037d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig00000379 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig0000036e ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000375 ) + ); + LUT4 #( + .INIT ( 16'hFF80 )) + \blk00000003/blk000005ab ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig00000373 ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk000005aa ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a9 ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000368 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig0000036b ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000362 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000035f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000035d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000315 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000358 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig00000315 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig00000317 ), + .O(\blk00000003/sig0000035a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000030d ), + .O(\blk00000003/sig0000034a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig00000312 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig00000311 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000341 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000002f3 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig00000335 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig00000336 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .O(\blk00000003/sig00000333 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig000002f3 ), + .I2(\blk00000003/sig000002f9 ), + .I3(coef_we), + .O(\blk00000003/sig00000330 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig0000032e ), + .I1(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000032c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig00000327 ), + .I1(coef_we), + .O(\blk00000003/sig00000325 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000597 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000320 ), + .O(\blk00000003/sig00000316 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000596 ( + .I0(coef_we), + .I1(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002f4 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000595 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig0000030b ), + .O(\blk00000003/sig0000031e ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig00000336 ), + .I1(\blk00000003/sig00000337 ), + .O(\blk00000003/sig00000301 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fc ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig00000336 ), + .O(\blk00000003/sig000002f7 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig000002f1 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig00000309 ), + .O(\blk00000003/sig000002ee ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000308 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk0000058d ( + .I0(nd), + .I1(\blk00000003/sig00000366 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig0000016c ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000058a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000002af ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk00000589 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig0000032b ), + .I1(\blk00000003/sig0000032e ), + .O(\blk00000003/sig00000295 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000809 ), + .I2(\blk00000003/sig0000080a ), + .I3(\blk00000003/sig0000080b ), + .I4(\blk00000003/sig0000080c ), + .O(\blk00000003/sig0000016f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000002a7 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig0000037c ), + .I1(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002ac ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000584 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig00000161 ), + .O(\blk00000003/sig00000160 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000583 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000015f ), + .O(\blk00000003/sig0000015e ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000582 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000002a9 ), + .I3(\blk00000003/sig00000296 ), + .O(\blk00000003/sig000002a8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig00000159 ), + .I1(\blk00000003/sig00000296 ), + .O(\blk00000003/sig0000015a ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000002b5 ), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .I4(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig00000810 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000002b5 ), + .I1(\blk00000003/sig000002a5 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig0000037c ), + .I2(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002aa ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000057c ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000080f ), + .I3(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015c ) + ); + MUXCY \blk00000003/blk0000057b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000080d ), + .O(\blk00000003/sig00000805 ) + ); + MUXCY_L \blk00000003/blk0000057a ( + .CI(\blk00000003/sig00000805 ), + .DI(\blk00000003/sig0000080c ), + .S(\blk00000003/sig00000806 ), + .LO(\blk00000003/sig00000802 ) + ); + MUXCY_L \blk00000003/blk00000579 ( + .CI(\blk00000003/sig00000802 ), + .DI(\blk00000003/sig0000080b ), + .S(\blk00000003/sig00000803 ), + .LO(\blk00000003/sig000007ff ) + ); + MUXCY_L \blk00000003/blk00000578 ( + .CI(\blk00000003/sig000007ff ), + .DI(\blk00000003/sig0000080a ), + .S(\blk00000003/sig00000800 ), + .LO(\blk00000003/sig000007fc ) + ); + MUXCY_L \blk00000003/blk00000577 ( + .CI(\blk00000003/sig000007fc ), + .DI(\blk00000003/sig00000809 ), + .S(\blk00000003/sig000007fd ), + .LO(\blk00000003/sig000007f9 ) + ); + MUXCY_D \blk00000003/blk00000576 ( + .CI(\blk00000003/sig000007f9 ), + .DI(\blk00000003/sig00000808 ), + .S(\blk00000003/sig000007fa ), + .O(\NLW_blk00000003/blk00000576_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000576_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000575 ( + .CI(\blk00000003/sig00000805 ), + .LI(\blk00000003/sig00000806 ), + .O(\blk00000003/sig00000807 ) + ); + XORCY \blk00000003/blk00000574 ( + .CI(\blk00000003/sig00000802 ), + .LI(\blk00000003/sig00000803 ), + .O(\blk00000003/sig00000804 ) + ); + XORCY \blk00000003/blk00000573 ( + .CI(\blk00000003/sig000007ff ), + .LI(\blk00000003/sig00000800 ), + .O(\blk00000003/sig00000801 ) + ); + XORCY \blk00000003/blk00000572 ( + .CI(\blk00000003/sig000007fc ), + .LI(\blk00000003/sig000007fd ), + .O(\blk00000003/sig000007fe ) + ); + XORCY \blk00000003/blk00000571 ( + .CI(\blk00000003/sig000007f9 ), + .LI(\blk00000003/sig000007fa ), + .O(\blk00000003/sig000007fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f8 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ec ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007eb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ea ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007df ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007de ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007db ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007da ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ce ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ca ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007af ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ae ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ad ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ac ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ab ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007aa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk00000511 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000799 ), + .S(\blk00000003/sig00000787 ), + .LO(\blk00000003/sig00000792 ) + ); + MUXCY_L \blk00000003/blk00000510 ( + .CI(\blk00000003/sig00000792 ), + .DI(\blk00000003/sig00000798 ), + .S(\blk00000003/sig00000793 ), + .LO(\blk00000003/sig0000078f ) + ); + MUXCY_L \blk00000003/blk0000050f ( + .CI(\blk00000003/sig0000078f ), + .DI(\blk00000003/sig00000797 ), + .S(\blk00000003/sig00000790 ), + .LO(\blk00000003/sig0000078c ) + ); + MUXCY_L \blk00000003/blk0000050e ( + .CI(\blk00000003/sig0000078c ), + .DI(\blk00000003/sig00000796 ), + .S(\blk00000003/sig0000078d ), + .LO(\blk00000003/sig00000789 ) + ); + MUXCY_D \blk00000003/blk0000050d ( + .CI(\blk00000003/sig00000789 ), + .DI(\blk00000003/sig00000795 ), + .S(\blk00000003/sig0000078a ), + .O(\NLW_blk00000003/blk0000050d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000050d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000050c ( + .CI(\blk00000003/sig00000792 ), + .LI(\blk00000003/sig00000793 ), + .O(\blk00000003/sig00000794 ) + ); + XORCY \blk00000003/blk0000050b ( + .CI(\blk00000003/sig0000078f ), + .LI(\blk00000003/sig00000790 ), + .O(\blk00000003/sig00000791 ) + ); + XORCY \blk00000003/blk0000050a ( + .CI(\blk00000003/sig0000078c ), + .LI(\blk00000003/sig0000078d ), + .O(\blk00000003/sig0000078e ) + ); + XORCY \blk00000003/blk00000509 ( + .CI(\blk00000003/sig00000789 ), + .LI(\blk00000003/sig0000078a ), + .O(\blk00000003/sig0000078b ) + ); + XORCY \blk00000003/blk00000508 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000787 ), + .O(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005e0 ), + .R(sclr), + .Q(\blk00000003/sig0000069c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005df ), + .R(sclr), + .Q(\blk00000003/sig0000069b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005de ), + .R(sclr), + .Q(\blk00000003/sig0000069a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dd ), + .R(sclr), + .Q(\blk00000003/sig00000699 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dc ), + .R(sclr), + .Q(\blk00000003/sig00000698 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005db ), + .R(sclr), + .Q(\blk00000003/sig00000697 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005da ), + .R(sclr), + .Q(\blk00000003/sig00000696 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d9 ), + .R(sclr), + .Q(\blk00000003/sig00000695 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d8 ), + .R(sclr), + .Q(\blk00000003/sig00000694 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d7 ), + .R(sclr), + .Q(\blk00000003/sig00000693 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d6 ), + .R(sclr), + .Q(\blk00000003/sig00000692 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d5 ), + .R(sclr), + .Q(\blk00000003/sig00000691 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d4 ), + .R(sclr), + .Q(\blk00000003/sig00000690 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d3 ), + .R(sclr), + .Q(\blk00000003/sig0000068f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d2 ), + .R(sclr), + .Q(\blk00000003/sig0000068e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d1 ), + .R(sclr), + .Q(\blk00000003/sig0000068d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(\blk00000003/sig000006ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(\blk00000003/sig000006ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(\blk00000003/sig000006aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(\blk00000003/sig000006a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(\blk00000003/sig000006a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(\blk00000003/sig000006a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(\blk00000003/sig000006a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(\blk00000003/sig000006a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(\blk00000003/sig000006a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(\blk00000003/sig000006a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(\blk00000003/sig000006a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(\blk00000003/sig000006a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(\blk00000003/sig000006a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(\blk00000003/sig0000069f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(\blk00000003/sig0000069e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(\blk00000003/sig0000069d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004af ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000565 ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ae ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000564 ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ad ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ac ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ab ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004aa ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a9 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a8 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a7 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a6 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a5 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000588 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000587 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000584 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000583 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000582 ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000581 ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(\blk00000003/sig00000761 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(\blk00000003/sig00000760 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000385 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(\blk00000003/sig000006ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(\blk00000003/sig000006eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000383 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(\blk00000003/sig000006ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000382 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(\blk00000003/sig000006e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000381 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(\blk00000003/sig000006e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000380 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(\blk00000003/sig000006e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(\blk00000003/sig000006e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(\blk00000003/sig000006e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(\blk00000003/sig000006e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(\blk00000003/sig000006e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(\blk00000003/sig000006e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(\blk00000003/sig000006e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000379 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(\blk00000003/sig000006e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000378 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(\blk00000003/sig000006df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000377 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(\blk00000003/sig000006de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000376 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(\blk00000003/sig000006dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000375 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005a0 ), + .R(sclr), + .Q(\blk00000003/sig000006bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000374 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059f ), + .R(sclr), + .Q(\blk00000003/sig000006bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000373 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059e ), + .R(sclr), + .Q(\blk00000003/sig000006ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000372 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059d ), + .R(sclr), + .Q(\blk00000003/sig000006b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059c ), + .R(sclr), + .Q(\blk00000003/sig000006b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059b ), + .R(sclr), + .Q(\blk00000003/sig000006b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059a ), + .R(sclr), + .Q(\blk00000003/sig000006b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000599 ), + .R(sclr), + .Q(\blk00000003/sig000006b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000598 ), + .R(sclr), + .Q(\blk00000003/sig000006b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000597 ), + .R(sclr), + .Q(\blk00000003/sig000006b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000596 ), + .R(sclr), + .Q(\blk00000003/sig000006b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000595 ), + .R(sclr), + .Q(\blk00000003/sig000006b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000594 ), + .R(sclr), + .Q(\blk00000003/sig000006b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000593 ), + .R(sclr), + .Q(\blk00000003/sig000006af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000592 ), + .R(sclr), + .Q(\blk00000003/sig000006ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000591 ), + .R(sclr), + .Q(\blk00000003/sig000006ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(\blk00000003/sig0000070c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(\blk00000003/sig0000070b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(\blk00000003/sig0000070a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(\blk00000003/sig00000709 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(\blk00000003/sig00000708 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(\blk00000003/sig00000707 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(\blk00000003/sig00000706 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(\blk00000003/sig00000705 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(\blk00000003/sig00000704 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(\blk00000003/sig00000703 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(\blk00000003/sig00000702 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(\blk00000003/sig00000701 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(\blk00000003/sig00000700 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(\blk00000003/sig000006ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(\blk00000003/sig000006fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(\blk00000003/sig000006fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005f0 ), + .R(sclr), + .Q(\blk00000003/sig000006cc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ef ), + .R(sclr), + .Q(\blk00000003/sig000006cb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ee ), + .R(sclr), + .Q(\blk00000003/sig000006ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ed ), + .R(sclr), + .Q(\blk00000003/sig000006c9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ec ), + .R(sclr), + .Q(\blk00000003/sig000006c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005eb ), + .R(sclr), + .Q(\blk00000003/sig000006c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ea ), + .R(sclr), + .Q(\blk00000003/sig000006c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e9 ), + .R(sclr), + .Q(\blk00000003/sig000006c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e8 ), + .R(sclr), + .Q(\blk00000003/sig000006c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e7 ), + .R(sclr), + .Q(\blk00000003/sig000006c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e6 ), + .R(sclr), + .Q(\blk00000003/sig000006c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e5 ), + .R(sclr), + .Q(\blk00000003/sig000006c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e4 ), + .R(sclr), + .Q(\blk00000003/sig000006c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e3 ), + .R(sclr), + .Q(\blk00000003/sig000006bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e2 ), + .R(sclr), + .Q(\blk00000003/sig000006be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e1 ), + .R(sclr), + .Q(\blk00000003/sig000006bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038e ), + .R(sclr), + .Q(\blk00000003/sig00000685 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038d ), + .R(sclr), + .Q(\blk00000003/sig00000683 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000390 ), + .R(sclr), + .Q(\blk00000003/sig00000681 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000394 ), + .R(sclr), + .Q(\blk00000003/sig0000067f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000039a ), + .R(sclr), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .R(sclr), + .Q(\blk00000003/sig00000679 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000387 ), + .R(sclr), + .Q(\blk00000003/sig00000689 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000386 ), + .R(sclr), + .Q(\blk00000003/sig00000687 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000689 ), + .R(sclr), + .Q(\blk00000003/sig0000068a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig00000688 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000685 ), + .R(sclr), + .Q(\blk00000003/sig00000686 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000683 ), + .R(sclr), + .Q(\blk00000003/sig00000684 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000681 ), + .R(sclr), + .Q(\blk00000003/sig00000682 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067f ), + .R(sclr), + .Q(\blk00000003/sig00000680 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067d ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067b ), + .R(sclr), + .Q(\blk00000003/sig0000067c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000679 ), + .R(sclr), + .Q(\blk00000003/sig0000067a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000677 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000678 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000307 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000673 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000671 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000340 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000672 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000339 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000671 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000115 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000115_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000115_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , +\blk00000003/sig00000654 , \blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , +\blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , +\blk00000003/sig0000065e , \blk00000003/sig0000065f , \blk00000003/sig00000660 }), + .BCOUT({\NLW_blk00000003/blk00000115_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , +\blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , +\blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 , +\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc }), + .C({\NLW_blk00000003/blk00000115_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000115_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 }), + .PCOUT({\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa , +\blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , \blk00000003/sig000005ff , +\blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , \blk00000003/sig00000604 , +\blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , \blk00000003/sig00000609 , +\blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , \blk00000003/sig0000060e , +\blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 , \blk00000003/sig00000613 , +\blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , \blk00000003/sig00000618 , +\blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , \blk00000003/sig0000061d , +\blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 }), + .A({\blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , +\blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , +\blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , +\blk00000003/sig0000057e , \blk00000003/sig0000057f , \blk00000003/sig00000580 }), + .M({\NLW_blk00000003/blk00000115_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000114 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , +\blk00000003/sig00000634 , \blk00000003/sig00000635 , \blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , +\blk00000003/sig00000639 , \blk00000003/sig0000063a , \blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 }), + .BCOUT({\NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 , +\blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , \blk00000003/sig00000479 , +\blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c }), + .C({\NLW_blk00000003/blk00000114_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED , 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\NLW_blk00000003/blk00000114_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000114_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED , 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\NLW_blk00000003/blk00000113_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000113_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 , +\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 }), + .PCOUT({\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 , \blk00000003/sig000001d2 , \blk00000003/sig000001d3 , +\blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , \blk00000003/sig000001e6 , \blk00000003/sig000001e7 , +\blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , \blk00000003/sig000001eb , \blk00000003/sig000001ec , +\blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , \blk00000003/sig000001f0 , \blk00000003/sig000001f1 , +\blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , \blk00000003/sig000001f5 , \blk00000003/sig000001f6 , +\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000113_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000112 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .BCOUT({\NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , +\blk00000003/sig000005b5 , \blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , +\blk00000003/sig000005ba , \blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , +\blk00000003/sig000005bf , \blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , +\blk00000003/sig000005c4 , \blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , +\blk00000003/sig000005c9 , \blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , +\blk00000003/sig000005ce , \blk00000003/sig000005cf , \blk00000003/sig000005d0 }), + .C({\NLW_blk00000003/blk00000112_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000112_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 }), + .PCOUT({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , \blk00000003/sig0000026e , \blk00000003/sig0000026f , +\blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , \blk00000003/sig00000273 , \blk00000003/sig00000274 , +\blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , \blk00000003/sig00000278 , \blk00000003/sig00000279 , +\blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , \blk00000003/sig0000027d , \blk00000003/sig0000027e , +\blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000112_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<15>_UNCONNECTED , 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\blk00000003/blk00000111 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , \blk00000003/sig00000585 , +\blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 }), + .BCOUT({\NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , +\blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , +\blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , +\blk00000003/sig0000040c , \blk00000003/sig0000040d , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , +\blk00000003/sig00000411 , \blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , +\blk00000003/sig00000416 , \blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , +\blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , +\blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , +\blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , +\blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c }), + .C({\NLW_blk00000003/blk00000111_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED , 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\NLW_blk00000003/blk00000111_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , +\blk00000003/sig0000058e , \blk00000003/sig0000058f , \blk00000003/sig00000590 }), + .PCOUT({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , \blk00000003/sig00000530 , +\blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , \blk00000003/sig00000535 , +\blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , +\blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , 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.RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 }), + .BCOUT({\NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , +\blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da }), + .C({\NLW_blk00000003/blk00000110_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000110_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , +\blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , \blk00000003/sig00000567 , +\blk00000003/sig00000567 , \blk00000003/sig00000568 , \blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , +\blk00000003/sig0000056c , \blk00000003/sig0000056d , \blk00000003/sig0000056e }), + .PCOUT({\blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , 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+\NLW_blk00000003/blk00000110_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , +\blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , \blk00000003/sig0000051f , +\blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , +\blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 }), + .BCOUT({\NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , 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\NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , +\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , +\blk00000003/sig00000557 , \blk00000003/sig00000558 , \blk00000003/sig00000559 , \blk00000003/sig0000055a , \blk00000003/sig0000055b , +\blk00000003/sig0000055c , \blk00000003/sig0000055d , \blk00000003/sig0000055e }), + .PCOUT({\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , +\blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , +\blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , +\blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , +\blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , +\blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , +\blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , +\blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , +\blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010e ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , +\blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , \blk00000003/sig000004cd , +\blk00000003/sig000004cd , \blk00000003/sig000004ce , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , \blk00000003/sig000004d1 , +\blk00000003/sig000004d2 , \blk00000003/sig000004d3 , \blk00000003/sig000004d4 }), + .BCOUT({\NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , \blk00000003/sig000004d9 , +\blk00000003/sig000004da , \blk00000003/sig000004db , \blk00000003/sig000004dc , \blk00000003/sig000004dd , \blk00000003/sig000004de , +\blk00000003/sig000004df , \blk00000003/sig000004e0 , \blk00000003/sig000004e1 , \blk00000003/sig000004e2 , \blk00000003/sig000004e3 , +\blk00000003/sig000004e4 , \blk00000003/sig000004e5 , \blk00000003/sig000004e6 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , +\blk00000003/sig000004e9 , \blk00000003/sig000004ea , \blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed , +\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , +\blk00000003/sig00000502 , \blk00000003/sig00000503 , \blk00000003/sig00000504 }), + .C({\NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , \blk00000003/sig00000509 , +\blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c }), + .PCOUT({\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 , \blk00000003/sig0000021a , \blk00000003/sig0000021b , +\blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , \blk00000003/sig0000021f , \blk00000003/sig00000220 , +\blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , \blk00000003/sig00000224 , \blk00000003/sig00000225 , +\blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , \blk00000003/sig00000229 , \blk00000003/sig0000022a , +\blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , \blk00000003/sig0000022e , \blk00000003/sig0000022f , +\blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , \blk00000003/sig00000233 , \blk00000003/sig00000234 , +\blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , \blk00000003/sig00000238 , \blk00000003/sig00000239 , +\blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , \blk00000003/sig0000023d , \blk00000003/sig0000023e , +\blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000047d , \blk00000003/sig0000047e , \blk00000003/sig0000047f , +\blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , \blk00000003/sig00000484 , +\blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , \blk00000003/sig00000489 , +\blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , 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\blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , 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\NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , +\blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , +\blk00000003/sig00000495 , \blk00000003/sig00000496 , \blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , +\blk00000003/sig0000049a , \blk00000003/sig0000049b , \blk00000003/sig0000049c }), + .PCOUT({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , 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+\NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , +\blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , +\blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , +\blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED , 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.C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , 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\NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED , 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\blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , +\blk00000003/sig00000440 , \blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , +\blk00000003/sig00000445 , \blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , +\blk00000003/sig0000044a , \blk00000003/sig0000044b , \blk00000003/sig0000044c }), + .PCOUT({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , 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\NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc }), + .PCOUT({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , +\blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , +\blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , +\blk00000003/sig0000040c , \blk00000003/sig0000040d , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , +\blk00000003/sig00000411 , \blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , +\blk00000003/sig00000416 , \blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , +\blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , +\blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , +\blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , +\blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010a ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , +\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa }), + .PCOUT({\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , +\blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000039a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000399 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000397 ), + .Q(\blk00000003/sig0000038f ) + ); + XORCY \blk00000003/blk00000106 ( + .CI(\blk00000003/sig00000392 ), + .LI(\blk00000003/sig00000395 ), + .O(\blk00000003/sig00000396 ) + ); + MUXCY_D \blk00000003/blk00000105 ( + .CI(\blk00000003/sig00000392 ), + .DI(\blk00000003/sig00000394 ), + .S(\blk00000003/sig00000395 ), + .O(\NLW_blk00000003/blk00000105_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000105_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000104 ( + .CI(\blk00000003/sig0000038f ), + .LI(\blk00000003/sig00000391 ), + .O(\blk00000003/sig00000393 ) + ); + MUXCY_L \blk00000003/blk00000103 ( + .CI(\blk00000003/sig0000038f ), + .DI(\blk00000003/sig00000390 ), + .S(\blk00000003/sig00000391 ), + .LO(\blk00000003/sig00000392 ) + ); + MUXCY_L \blk00000003/blk00000102 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000038e ), + .S(\blk00000003/sig00000388 ), + .LO(\blk00000003/sig0000038a ) + ); + MUXCY_D \blk00000003/blk00000101 ( + .CI(\blk00000003/sig0000038a ), + .DI(\blk00000003/sig0000038d ), + .S(\blk00000003/sig0000038b ), + .O(\NLW_blk00000003/blk00000101_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000101_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig0000038a ), + .LI(\blk00000003/sig0000038b ), + .O(\blk00000003/sig0000038c ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000388 ), + .O(\blk00000003/sig00000389 ) + ); + MUXCY_L \blk00000003/blk000000fe ( + .CI(\blk00000003/sig0000037f ), + .DI(\blk00000003/sig00000387 ), + .S(\blk00000003/sig00000380 ), + .LO(\blk00000003/sig00000382 ) + ); + MUXCY_D \blk00000003/blk000000fd ( + .CI(\blk00000003/sig00000382 ), + .DI(\blk00000003/sig00000386 ), + .S(\blk00000003/sig00000383 ), + .O(\NLW_blk00000003/blk000000fd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000385 ), + .O(\blk00000003/sig0000037f ) + ); + XORCY \blk00000003/blk000000fb ( + .CI(\blk00000003/sig00000382 ), + .LI(\blk00000003/sig00000383 ), + .O(\blk00000003/sig00000384 ) + ); + XORCY \blk00000003/blk000000fa ( + .CI(\blk00000003/sig0000037f ), + .LI(\blk00000003/sig00000380 ), + .O(\blk00000003/sig00000381 ) + ); + FDE \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037d ), + .Q(\blk00000003/sig0000037e ) + ); + MUXCY_L \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000037c ), + .S(\blk00000003/sig00000376 ), + .LO(\blk00000003/sig00000378 ) + ); + MUXCY_D \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig00000378 ), + .DI(\blk00000003/sig0000037b ), + .S(\blk00000003/sig00000379 ), + .O(\NLW_blk00000003/blk000000f7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig00000378 ), + .LI(\blk00000003/sig00000379 ), + .O(\blk00000003/sig0000037a ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig0000036f ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig00000370 ), + .LO(\blk00000003/sig00000372 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000372 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig00000373 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000375 ), + .O(\blk00000003/sig0000036f ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000372 ), + .LI(\blk00000003/sig00000373 ), + .O(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036f ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036d ), + .R(sclr), + .Q(\blk00000003/sig0000036e ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig0000036a ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036c ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\blk00000003/sig0000036d ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036b ), + .O(\blk00000003/sig00000367 ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000369 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000365 ) + ); + MUXCY \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000369 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000036a ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000367 ), + .DI(\blk00000003/sig00000366 ), + .S(\blk00000003/sig00000368 ), + .O(\blk00000003/sig00000369 ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000365 ), + .R(sclr), + .Q(\blk00000003/sig00000366 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000356 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000355 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig000002ed ), + .DI(\blk00000003/sig00000363 ), + .S(\blk00000003/sig00000364 ), + .O(\blk00000003/sig00000360 ), + .LO(\NLW_blk00000003/blk000000e6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000360 ), + .DI(\blk00000003/sig00000361 ), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035e ), + .LO(\NLW_blk00000003/blk000000e5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035e ), + .DI(\blk00000003/sig00000354 ), + .S(\blk00000003/sig0000035f ), + .O(\blk00000003/sig0000035b ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000035b ), + .DI(\blk00000003/sig0000035c ), + .S(\blk00000003/sig0000035d ), + .O(\blk00000003/sig00000359 ), + .LO(\NLW_blk00000003/blk000000e3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000359 ), + .DI(\blk00000003/sig00000319 ), + .S(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig000002ea ), + .S(\blk00000003/sig00000358 ), + .O(\NLW_blk00000003/blk000000e1_O_UNCONNECTED ), + .LO(\blk00000003/sig00000355 ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000355 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000356 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000344 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000354 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000343 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029e ), + .DI(\blk00000003/sig00000352 ), + .S(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig0000029e ), + .S(\blk00000003/sig0000034f ), + .O(\blk00000003/sig0000034b ), + .LO(\NLW_blk00000003/blk000000db_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig0000034b ), + .DI(\blk00000003/sig0000034c ), + .S(\blk00000003/sig0000034d ), + .O(\blk00000003/sig00000349 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000349 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig00000348 ), + .O(\NLW_blk00000003/blk000000d8_O_UNCONNECTED ), + .LO(\blk00000003/sig00000343 ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000030e ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000343 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000344 ) + ); + FDE \blk00000003/blk000000d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/sig00000342 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000340 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000338 ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033b ), + .LI(\blk00000003/sig0000033e ), + .O(\blk00000003/sig0000033f ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033b ), + .DI(\blk00000003/sig0000033d ), + .S(\blk00000003/sig0000033e ), + .O(\NLW_blk00000003/blk000000d1_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000338 ), + .LI(\blk00000003/sig0000033a ), + .O(\blk00000003/sig0000033c ) + ); + MUXCY_L \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000338 ), + .DI(\blk00000003/sig00000339 ), + .S(\blk00000003/sig0000033a ), + .LO(\blk00000003/sig0000033b ) + ); + MUXCY_L \blk00000003/blk000000ce ( + .CI(\blk00000003/sig0000032f ), + .DI(\blk00000003/sig00000337 ), + .S(\blk00000003/sig00000330 ), + .LO(\blk00000003/sig00000332 ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000332 ), + .DI(\blk00000003/sig00000336 ), + .S(\blk00000003/sig00000333 ), + .O(\NLW_blk00000003/blk000000cd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000335 ), + .O(\blk00000003/sig0000032f ) + ); + XORCY \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000332 ), + .LI(\blk00000003/sig00000333 ), + .O(\blk00000003/sig00000334 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032f ), + .LI(\blk00000003/sig00000330 ), + .O(\blk00000003/sig00000331 ) + ); + MUXCY_L \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000032e ), + .S(\blk00000003/sig0000032c ), + .LO(\blk00000003/sig00000328 ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000032c ), + .O(\blk00000003/sig0000032d ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000328 ), + .DI(\blk00000003/sig0000032b ), + .S(\blk00000003/sig00000329 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000328 ), + .LI(\blk00000003/sig00000329 ), + .O(\blk00000003/sig0000032a ) + ); + MUXCY_L \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000327 ), + .S(\blk00000003/sig00000325 ), + .LO(\blk00000003/sig00000321 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000325 ), + .O(\blk00000003/sig00000326 ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig00000321 ), + .DI(\blk00000003/sig00000324 ), + .S(\blk00000003/sig00000322 ), + .O(\NLW_blk00000003/blk000000c3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000321 ), + .LI(\blk00000003/sig00000322 ), + .O(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000313 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000311 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/sig0000030d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000303 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000309 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000306 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000307 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000304 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000305 ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000302 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000303 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000302 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000301 ), + .O(\blk00000003/sig00000302 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig000002fe ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002fe ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002ff ) + ); + MUXCY_D \blk00000003/blk000000a4 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fd ), + .O(\blk00000003/sig000002fe ), + .LO(\NLW_blk00000003/blk000000a4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f8 ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a2 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a1_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002f8 ), + .DI(\blk00000003/sig000002f9 ), + .S(coef_we), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk000000a0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002f7 ), + .O(\blk00000003/sig000002f2 ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig000002f5 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY \blk00000003/blk0000009d ( + .CI(\blk00000003/sig000002f5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002f2 ), + .DI(\blk00000003/sig000002f3 ), + .S(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig000002f5 ), + .LO(\NLW_blk00000003/blk0000009c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002eb ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002e9 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig000002f1 ), + .O(\NLW_blk00000003/blk0000009a_O_UNCONNECTED ), + .LO(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig000002ec ), + .DI(\blk00000003/sig000002ed ), + .S(\blk00000003/sig000002ee ), + .O(\blk00000003/sig000002ef ), + .LO(\NLW_blk00000003/blk00000099_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000097 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e9 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b4 ), + .R(\blk00000003/sig000002af ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002af ), + .Q(rdy) + ); + FDSE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .S(sclr), + .Q(\blk00000003/sig000002ad ) + ); + FDRE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002aa ), + .R(sclr), + .Q(\blk00000003/sig000002ab ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig00000296 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000293 ), + .R(sclr), + .Q(\blk00000003/sig000002a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(sclr), + .Q(\blk00000003/sig000002a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000024_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig000002a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig0000029f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000016e ), + .R(sclr), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000168 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000020_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000169 ), + .S(sclr), + .Q(\blk00000003/sig0000029d ) + ); + MUXCY \blk00000003/blk0000001e ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + XORCY \blk00000003/blk0000001d ( + .CI(\blk00000003/sig00000298 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029a ) + ); + MUXCY \blk00000003/blk0000001c ( + .CI(\blk00000003/sig00000298 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000299 ) + ); + MUXCY_D \blk00000003/blk0000001b ( + .CI(\blk00000003/sig00000296 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000298 ), + .LO(\NLW_blk00000003/blk0000001b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk00000019_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000292 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000293 ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000017 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , +\blk00000003/sig00000245 , \blk00000003/sig00000246 , \blk00000003/sig00000247 , \blk00000003/sig00000248 , \blk00000003/sig00000249 , +\blk00000003/sig0000024a , \blk00000003/sig0000024b , \blk00000003/sig0000024c , \blk00000003/sig0000024d , \blk00000003/sig0000024e , +\blk00000003/sig0000024f , \blk00000003/sig00000250 , \blk00000003/sig00000251 }), + .BCOUT({\NLW_blk00000003/blk00000017_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , \blk00000003/sig0000026e , \blk00000003/sig0000026f , +\blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , \blk00000003/sig00000273 , \blk00000003/sig00000274 , +\blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , \blk00000003/sig00000278 , \blk00000003/sig00000279 , +\blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , \blk00000003/sig0000027d , \blk00000003/sig0000027e , +\blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000017_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000017_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000017_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000017_P<40>_UNCONNECTED , +\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , +\blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , +\blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , +\blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000282 , +\blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , \blk00000003/sig00000287 , +\blk00000003/sig00000288 , \blk00000003/sig00000289 , \blk00000003/sig0000028a , \blk00000003/sig0000028b , \blk00000003/sig0000028c , +\blk00000003/sig0000028d , \blk00000003/sig0000028e , \blk00000003/sig0000028f , \blk00000003/sig00000290 , \blk00000003/sig00000291 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000017_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED , 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.RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000016_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000016_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , \blk00000003/sig0000020d , \blk00000003/sig0000020e , +\blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED }), + 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+\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 , \blk00000003/sig000001d2 , \blk00000003/sig000001d3 , +\blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , \blk00000003/sig000001e6 , \blk00000003/sig000001e7 , +\blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , \blk00000003/sig000001eb , \blk00000003/sig000001ec , +\blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , \blk00000003/sig000001f0 , \blk00000003/sig000001f1 , +\blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , \blk00000003/sig000001f5 , \blk00000003/sig000001f6 , +\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000015_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000015_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_P<40>_UNCONNECTED , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , \blk00000003/sig000000b0 , +\blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig000000be , \blk00000003/sig000001fa , +\blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , \blk00000003/sig000001ff , +\blk00000003/sig00000200 , \blk00000003/sig00000201 , \blk00000003/sig00000202 , \blk00000003/sig00000203 , \blk00000003/sig00000204 , +\blk00000003/sig00000205 , \blk00000003/sig00000206 , \blk00000003/sig00000207 , \blk00000003/sig00000208 , \blk00000003/sig00000209 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + .M({\NLW_blk00000003/blk00000015_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED , 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\NLW_blk00000003/blk00000015_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000014 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , +\blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 }), + .BCOUT({\NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , +\blk00000003/sig00000182 , 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\blk00000003/sig000001a7 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000014_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED , +\blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , +\blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , +\blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , +\blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , +\blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , +\blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , +\blk00000003/sig000000dd }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED , 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\NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + 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.LO(\NLW_blk00000003/blk00000013_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig0000016d ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000016e ) + ); + MUXCY \blk00000003/blk00000011 ( + .CI(\blk00000003/sig0000016d ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000162 ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig0000016a ), + .DI(\blk00000003/sig0000016b ), + .S(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000168 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000169 ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig00000165 ), + .DI(\blk00000003/sig00000166 ), + .S(\blk00000003/sig00000167 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig00000168 ) + ); + MUXCY_D \blk00000003/blk0000000d ( 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\NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , 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\NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , +\blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000034/blk00000096 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000034/sig000009d5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000095 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000094 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000093 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000092 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000091 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000090 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ce ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ca ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000089 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000088 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000087 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000086 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000085 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000084 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000083 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000082 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000081 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000080 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009be ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ba ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000079 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000078 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000077 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000076 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000075 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000074 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000073 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000072 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000071 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009af ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000070 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ae ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ac ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ab ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ad ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000069 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009aa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000068 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000067 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000066 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d4 ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d2 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d1 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d0 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cf ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ce ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cd ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cc ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cb ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ca ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c9 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c8 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c7 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c6 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c5 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c4 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c3 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c2 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c1 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c0 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bf ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009be ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bd ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bb ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ba ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009af ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ae ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ad ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ac ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ab ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009aa ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk00000034/blk00000035 ( + .G(\blk00000003/blk00000034/sig000009a4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000130/blk00000152 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000130/sig00000a0c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000151 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk00000130/sig00000a0b ), + .Q15(\NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000150 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk00000130/sig00000a0a ), + .Q15(\NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk00000130/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk00000130/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk00000130/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk00000130/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk00000130/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk00000130/sig00000a04 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000149 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk00000130/sig00000a03 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000148 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk00000130/sig00000a02 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000147 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk00000130/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000146 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk00000130/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000145 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk00000130/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000144 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk00000130/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000143 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk00000130/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000142 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk00000130/sig000009fc ), + .Q15(\NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0b ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0a ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a09 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a08 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a07 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a06 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a05 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a04 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a03 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a02 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a01 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a00 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009ff ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fe ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fd ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fc ), + .Q(\blk00000003/sig000005e0 ) + ); + GND \blk00000003/blk00000130/blk00000131 ( + .G(\blk00000003/blk00000130/sig000009fb ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000175 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000153/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/blk00000153/sig00000a42 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/blk00000153/sig00000a41 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/blk00000153/sig00000a40 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/blk00000153/sig00000a3f ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/blk00000153/sig00000a3e ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/blk00000153/sig00000a3d ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/blk00000153/sig00000a3c ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/blk00000153/sig00000a3b ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016c ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/blk00000153/sig00000a3a ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016b ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/blk00000153/sig00000a39 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016a ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/blk00000153/sig00000a38 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000169 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/blk00000153/sig00000a37 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000168 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/blk00000153/sig00000a36 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000167 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/blk00000153/sig00000a35 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000166 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/blk00000153/sig00000a34 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000165 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/blk00000153/sig00000a33 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a42 ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a41 ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a40 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3f ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3e ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3d ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3c ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3b ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3a ), + .Q(\blk00000003/sig00000599 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a39 ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a38 ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a37 ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a36 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a35 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a34 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a33 ), + .Q(\blk00000003/sig000005a0 ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000a32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000176/blk00000198 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000176/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000197 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk00000176/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000196 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk00000176/sig00000a78 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000195 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk00000176/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000194 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk00000176/sig00000a76 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000193 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk00000176/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000192 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk00000176/sig00000a74 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000191 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk00000176/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000190 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000668 ), + .Q(\blk00000003/blk00000176/sig00000a72 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000669 ), + .Q(\blk00000003/blk00000176/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066a ), + .Q(\blk00000003/blk00000176/sig00000a70 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066b ), + .Q(\blk00000003/blk00000176/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066c ), + .Q(\blk00000003/blk00000176/sig00000a6e ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066d ), + .Q(\blk00000003/blk00000176/sig00000a6d ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066e ), + .Q(\blk00000003/blk00000176/sig00000a6c ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000189 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066f ), + .Q(\blk00000003/blk00000176/sig00000a6b ), + .Q15(\NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000188 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000670 ), + .Q(\blk00000003/blk00000176/sig00000a6a ), + .Q15(\NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a79 ), + .Q(\blk00000003/sig00000621 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a78 ), + .Q(\blk00000003/sig00000622 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a77 ), + .Q(\blk00000003/sig00000623 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a76 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a75 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a74 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a73 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a72 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a71 ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a70 ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6f ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6e ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6d ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6c ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000179 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6b ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000178 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6a ), + .Q(\blk00000003/sig00000630 ) + ); + GND \blk00000003/blk00000176/blk00000177 ( + .G(\blk00000003/blk00000176/sig00000a69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000199/blk000001bb ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000199/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ba ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/blk00000199/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b9 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/blk00000199/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b8 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/blk00000199/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000199/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000199/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000199/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000199/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000199/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000199/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000199/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000199/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001af ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000199/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ae ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000199/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ad ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000199/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ac ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000199/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ab ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000199/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000ab0 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaf ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aae ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aad ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aac ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aab ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaa ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa9 ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa8 ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa7 ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa6 ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa5 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa4 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa3 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa2 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa1 ), + .Q(\blk00000003/sig000005f0 ) + ); + GND \blk00000003/blk00000199/blk0000019a ( + .G(\blk00000003/blk00000199/sig00000aa0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001bc/blk000001de ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000001bc/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dd ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk000001bc/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dc ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk000001bc/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001db ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk000001bc/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001da ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk000001bc/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d9 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk000001bc/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d8 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk000001bc/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d7 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk000001bc/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d6 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk000001bc/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d5 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk000001bc/sig00000adf ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d4 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk000001bc/sig00000ade ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d3 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk000001bc/sig00000add ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d2 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk000001bc/sig00000adc ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d1 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk000001bc/sig00000adb ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d0 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk000001bc/sig00000ada ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001cf ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk000001bc/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001ce ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk000001bc/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae7 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae6 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae5 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae4 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae3 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae2 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae1 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae0 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adf ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ade ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000add ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adc ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adb ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ada ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad9 ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad8 ), + .Q(\blk00000003/sig00000650 ) + ); + GND \blk00000003/blk000001bc/blk000001bd ( + .G(\blk00000003/blk000001bc/sig00000ad7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001df/blk00000201 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk000001df/sig00000b1f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk00000200 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk000001df/sig00000b1e ), + .Q15(\NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001ff ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk000001df/sig00000b1d ), + .Q15(\NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fe ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk000001df/sig00000b1c ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fd ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk000001df/sig00000b1b ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fc ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk000001df/sig00000b1a ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fb ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk000001df/sig00000b19 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fa ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk000001df/sig00000b18 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f9 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk000001df/sig00000b17 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f8 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk000001df/sig00000b16 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f7 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk000001df/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f6 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk000001df/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f5 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk000001df/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f4 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk000001df/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f3 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk000001df/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f2 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/blk000001df/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f1 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/blk000001df/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1e ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1d ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1c ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1b ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1a ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b19 ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b18 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b17 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b16 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b15 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b14 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b13 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b12 ), + .Q(\blk00000003/sig0000063d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b11 ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b10 ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b0f ), + .Q(\blk00000003/sig00000640 ) + ); + GND \blk00000003/blk000001df/blk000001e0 ( + .G(\blk00000003/blk000001df/sig00000b0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000202/blk00000224 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk00000202/sig00000b56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000223 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000202/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000222 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000202/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000221 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000202/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000220 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000202/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000202/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000202/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000202/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000202/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000202/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000202/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000219 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000202/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000218 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000202/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000217 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk00000202/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000216 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk00000202/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000215 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk00000202/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000214 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk00000202/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b55 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b54 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b53 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000210 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b52 ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b51 ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b50 ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4f ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4e ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4d ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4c ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000209 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4b ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000208 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4a ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000207 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b49 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000206 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b48 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b47 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b46 ), + .Q(\blk00000003/sig00000670 ) + ); + GND \blk00000003/blk00000202/blk00000203 ( + .G(\blk00000003/blk00000202/sig00000b45 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000225/blk00000247 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000225/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000246 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/blk00000225/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000245 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/blk00000225/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000244 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/blk00000225/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000243 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/blk00000225/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000242 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/blk00000225/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000241 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/blk00000225/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000240 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/blk00000225/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/blk00000225/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/blk00000225/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/blk00000225/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/blk00000225/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/blk00000225/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/blk00000225/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000239 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/blk00000225/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000238 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/blk00000225/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000237 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/blk00000225/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b89 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b88 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b87 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b86 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b85 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b84 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b83 ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b82 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b81 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b80 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7f ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7e ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7d ), + .Q(\blk00000003/sig00000660 ) + ); + GND \blk00000003/blk00000225/blk00000226 ( + .G(\blk00000003/blk00000225/sig00000b7c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000248/blk0000026a ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000248/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000269 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/blk00000248/sig00000bc3 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000268 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/blk00000248/sig00000bc2 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000267 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/blk00000248/sig00000bc1 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000266 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/blk00000248/sig00000bc0 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000265 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/blk00000248/sig00000bbf ), + .Q15(\NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000264 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/blk00000248/sig00000bbe ), + .Q15(\NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000263 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/blk00000248/sig00000bbd ), + .Q15(\NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000262 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/blk00000248/sig00000bbc ), + .Q15(\NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000261 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/blk00000248/sig00000bbb ), + .Q15(\NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000260 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/blk00000248/sig00000bba ), + .Q15(\NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/blk00000248/sig00000bb9 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025e ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/blk00000248/sig00000bb8 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025d ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/blk00000248/sig00000bb7 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/blk00000248/sig00000bb6 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/blk00000248/sig00000bb5 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/blk00000248/sig00000bb4 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc3 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc2 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc1 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc0 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbf ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbe ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbd ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbc ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbb ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bba ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb9 ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb8 ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb7 ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb6 ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb5 ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb4 ), + .Q(\blk00000003/sig0000044c ) + ); + GND \blk00000003/blk00000248/blk00000249 ( + .G(\blk00000003/blk00000248/sig00000bb3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000026b/blk0000028d ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000026b/sig00000bfb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/blk0000026b/sig00000bfa ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/blk0000026b/sig00000bf9 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/blk0000026b/sig00000bf8 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000289 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000026b/sig00000bf7 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000288 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000026b/sig00000bf6 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000287 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000026b/sig00000bf5 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000286 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000026b/sig00000bf4 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000285 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000026b/sig00000bf3 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000284 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000026b/sig00000bf2 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000283 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000026b/sig00000bf1 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000282 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000026b/sig00000bf0 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000281 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/blk0000026b/sig00000bef ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000280 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/blk0000026b/sig00000bee ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/blk0000026b/sig00000bed ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/blk0000026b/sig00000bec ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/blk0000026b/sig00000beb ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bfa ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf9 ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf8 ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000279 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf7 ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000278 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf6 ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000277 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf5 ), + .Q(\blk00000003/sig00000432 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000276 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf4 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000275 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf3 ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000274 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf2 ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000273 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf1 ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000272 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf0 ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000271 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bef ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000270 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bee ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bed ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bec ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000beb ), + .Q(\blk00000003/sig0000043c ) + ); + GND \blk00000003/blk0000026b/blk0000026c ( + .G(\blk00000003/blk0000026b/sig00000bea ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000028e/blk000002b0 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000028e/sig00000c32 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002af ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/blk0000028e/sig00000c31 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ae ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/blk0000028e/sig00000c30 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ad ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/blk0000028e/sig00000c2f ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ac ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/blk0000028e/sig00000c2e ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ab ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/blk0000028e/sig00000c2d ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002aa ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/blk0000028e/sig00000c2c ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a9 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/blk0000028e/sig00000c2b ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a8 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/blk0000028e/sig00000c2a ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a7 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/blk0000028e/sig00000c29 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a6 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/blk0000028e/sig00000c28 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a5 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/blk0000028e/sig00000c27 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a4 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/blk0000028e/sig00000c26 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a3 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/blk0000028e/sig00000c25 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a2 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/blk0000028e/sig00000c24 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a1 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/blk0000028e/sig00000c23 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a0 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/blk0000028e/sig00000c22 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c31 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c30 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2f ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2e ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2d ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2c ), + .Q(\blk00000003/sig00000492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2b ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2a ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c29 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c28 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c27 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c26 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c25 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c24 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c23 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c22 ), + .Q(\blk00000003/sig0000049c ) + ); + GND \blk00000003/blk0000028e/blk0000028f ( + .G(\blk00000003/blk0000028e/sig00000c21 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002d3 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk000002b1/sig00000c69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d2 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/blk000002b1/sig00000c68 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d1 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/blk000002b1/sig00000c67 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d0 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/blk000002b1/sig00000c66 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cf ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/blk000002b1/sig00000c65 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ce ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/blk000002b1/sig00000c64 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cd ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/blk000002b1/sig00000c63 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cc ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk000002b1/sig00000c62 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cb ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk000002b1/sig00000c61 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ca ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk000002b1/sig00000c60 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c9 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk000002b1/sig00000c5f ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c8 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk000002b1/sig00000c5e ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c7 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk000002b1/sig00000c5d ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c6 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk000002b1/sig00000c5c ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c5 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk000002b1/sig00000c5b ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c4 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk000002b1/sig00000c5a ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c3 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk000002b1/sig00000c59 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c68 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c67 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c66 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c65 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c64 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c63 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c62 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c61 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c60 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c59 ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig00000c58 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002d4/blk0000030c ( + .I0(\blk00000003/sig00000307 ), + .I1(ce), + .O(\blk00000003/blk000002d4/sig00000cce ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030b ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cbb ), + .DPO(\blk00000003/blk000002d4/sig00000ccd ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030a ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cba ), + .DPO(\blk00000003/blk000002d4/sig00000ccc ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000309 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb9 ), + .DPO(\blk00000003/blk000002d4/sig00000ccb ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000308 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb8 ), + .DPO(\blk00000003/blk000002d4/sig00000cca ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000307 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb7 ), + .DPO(\blk00000003/blk000002d4/sig00000cc9 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000306 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb6 ), + .DPO(\blk00000003/blk000002d4/sig00000cc8 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000305 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb4 ), + .DPO(\blk00000003/blk000002d4/sig00000cc6 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk000002d4/blk00000304 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb3 ), + .DPO(\blk00000003/blk000002d4/sig00000cc5 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000303 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb5 ), + .DPO(\blk00000003/blk000002d4/sig00000cc7 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk000002d4/blk00000302 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb2 ), + .DPO(\blk00000003/blk000002d4/sig00000cc4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000002d4/blk00000301 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb1 ), + .DPO(\blk00000003/blk000002d4/sig00000cc3 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk000002d4/blk00000300 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb0 ), + .DPO(\blk00000003/blk000002d4/sig00000cc2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002d4/blk000002ff ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caf ), + .DPO(\blk00000003/blk000002d4/sig00000cc1 ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fe ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cae ), + .DPO(\blk00000003/blk000002d4/sig00000cc0 ) + ); + RAM16X1D #( + .INIT ( 16'h0004 )) + \blk00000003/blk000002d4/blk000002fd ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cad ), + .DPO(\blk00000003/blk000002d4/sig00000cbf ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk000002d4/blk000002fc ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cab ), + .DPO(\blk00000003/blk000002d4/sig00000cbd ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fb ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caa ), + .DPO(\blk00000003/blk000002d4/sig00000cbc ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fa ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cac ), + .DPO(\blk00000003/blk000002d4/sig00000cbe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccd ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccc ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccb ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cca ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc9 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc8 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc7 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc6 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc5 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc4 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc3 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc2 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc1 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc0 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbf ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbe ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbd ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbc ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbb ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cba ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb9 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb8 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb7 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb6 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb5 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb4 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb3 ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb2 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb1 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb0 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caf ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cae ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cad ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cac ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cab ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caa ), + .Q(\blk00000003/sig00000730 ) + ); + GND \blk00000003/blk000002d4/blk000002d5 ( + .G(\blk00000003/blk000002d4/sig00000ca9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000030d/blk00000345 ( + .I0(\blk00000003/sig00000677 ), + .I1(ce), + .O(\blk00000003/blk0000030d/sig00000d33 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000344 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000071f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d20 ), + .DPO(\blk00000003/blk0000030d/sig00000d32 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000343 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000720 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1f ), + .DPO(\blk00000003/blk0000030d/sig00000d31 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000342 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000721 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1e ), + .DPO(\blk00000003/blk0000030d/sig00000d30 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000341 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000722 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1d ), + .DPO(\blk00000003/blk0000030d/sig00000d2f ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000340 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000723 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1c ), + .DPO(\blk00000003/blk0000030d/sig00000d2e ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk0000030d/blk0000033f ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000724 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1b ), + .DPO(\blk00000003/blk0000030d/sig00000d2d ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk0000030d/blk0000033e ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000726 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d19 ), + .DPO(\blk00000003/blk0000030d/sig00000d2b ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk0000030d/blk0000033d ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000727 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d18 ), + .DPO(\blk00000003/blk0000030d/sig00000d2a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk0000033c ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000725 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1a ), + .DPO(\blk00000003/blk0000030d/sig00000d2c ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk0000033b ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000728 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d17 ), + .DPO(\blk00000003/blk0000030d/sig00000d29 ) + ); + RAM16X1D #( + .INIT ( 16'h0006 )) + \blk00000003/blk0000030d/blk0000033a ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000729 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d16 ), + .DPO(\blk00000003/blk0000030d/sig00000d28 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk0000030d/blk00000339 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072a ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d15 ), + .DPO(\blk00000003/blk0000030d/sig00000d27 ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk00000338 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072b ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d14 ), + .DPO(\blk00000003/blk0000030d/sig00000d26 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000337 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072c ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d13 ), + .DPO(\blk00000003/blk0000030d/sig00000d25 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk00000336 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072d ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d12 ), + .DPO(\blk00000003/blk0000030d/sig00000d24 ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk0000030d/blk00000335 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d10 ), + .DPO(\blk00000003/blk0000030d/sig00000d22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000334 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000730 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d0f ), + .DPO(\blk00000003/blk0000030d/sig00000d21 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk0000030d/blk00000333 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072e ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d11 ), + .DPO(\blk00000003/blk0000030d/sig00000d23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d32 ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d31 ), + .Q(\blk00000003/sig00000570 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d30 ), + .Q(\blk00000003/sig00000571 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2f ), + .Q(\blk00000003/sig00000572 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2e ), + .Q(\blk00000003/sig00000573 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2d ), + .Q(\blk00000003/sig00000574 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2c ), + .Q(\blk00000003/sig00000575 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2b ), + .Q(\blk00000003/sig00000576 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2a ), + .Q(\blk00000003/sig00000577 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d29 ), + .Q(\blk00000003/sig00000578 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d28 ), + .Q(\blk00000003/sig00000579 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d27 ), + .Q(\blk00000003/sig0000057a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d26 ), + .Q(\blk00000003/sig0000057b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d25 ), + .Q(\blk00000003/sig0000057c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d24 ), + .Q(\blk00000003/sig0000057d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d23 ), + .Q(\blk00000003/sig0000057e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d22 ), + .Q(\blk00000003/sig0000057f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d21 ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d20 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1f ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1e ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1d ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1c ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1b ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1a ), + .Q(\blk00000003/sig00000737 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d19 ), + .Q(\blk00000003/sig00000738 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d18 ), + .Q(\blk00000003/sig00000739 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d17 ), + .Q(\blk00000003/sig0000073a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000316 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d16 ), + .Q(\blk00000003/sig0000073b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d15 ), + .Q(\blk00000003/sig0000073c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d14 ), + .Q(\blk00000003/sig0000073d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d13 ), + .Q(\blk00000003/sig0000073e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d12 ), + .Q(\blk00000003/sig0000073f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d11 ), + .Q(\blk00000003/sig00000740 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d10 ), + .Q(\blk00000003/sig00000741 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d0f ), + .Q(\blk00000003/sig00000742 ) + ); + GND \blk00000003/blk0000030d/blk0000030e ( + .G(\blk00000003/blk0000030d/sig00000d0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000386/blk000003ac ( + .I0(\blk00000003/sig00000678 ), + .I1(ce), + .O(\blk00000003/blk00000386/sig00000d74 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003ab ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000731 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d73 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk00000386/blk000003aa ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000732 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d72 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003a9 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000733 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d71 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a8 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000734 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d70 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a7 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000735 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6f ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a6 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000736 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6e ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a5 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000738 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a4 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000739 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6b ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a3 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000737 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6d ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a2 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073a ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a1 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073b ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d69 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk00000386/blk000003a0 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073c ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d68 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk0000039f ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073d ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d67 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk0000039e ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073e ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d66 ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk0000039d ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073f ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d65 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk0000039c ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000741 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d63 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk0000039b ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000742 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d62 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000386/blk0000039a ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000740 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d64 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d73 ), + .Q(\blk00000003/sig0000050d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d72 ), + .Q(\blk00000003/sig0000050e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d71 ), + .Q(\blk00000003/sig0000050f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d70 ), + .Q(\blk00000003/sig00000510 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6f ), + .Q(\blk00000003/sig00000511 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6e ), + .Q(\blk00000003/sig00000512 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6d ), + .Q(\blk00000003/sig00000513 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6c ), + .Q(\blk00000003/sig00000514 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6b ), + .Q(\blk00000003/sig00000515 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6a ), + .Q(\blk00000003/sig00000516 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d69 ), + .Q(\blk00000003/sig00000517 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d68 ), + .Q(\blk00000003/sig00000518 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d67 ), + .Q(\blk00000003/sig00000519 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d66 ), + .Q(\blk00000003/sig0000051a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d65 ), + .Q(\blk00000003/sig0000051b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d64 ), + .Q(\blk00000003/sig0000051c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d63 ), + .Q(\blk00000003/sig0000051d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d62 ), + .Q(\blk00000003/sig0000051e ) + ); + GND \blk00000003/blk00000386/blk00000387 ( + .G(\blk00000003/blk00000386/sig00000d61 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ad/blk000003bf ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003ad/sig00000d93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003be ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000003ad/sig00000d92 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000003ad/sig00000d91 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bc ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000003ad/sig00000d90 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bb ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000003ad/sig00000d8f ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003ba ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000003ad/sig00000d8e ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b9 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000003ad/sig00000d8d ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b8 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000003ad/sig00000d8c ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b7 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000003ad/sig00000d8b ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d92 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d91 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d90 ), + .Q(\blk00000003/sig00000507 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8f ), + .Q(\blk00000003/sig00000508 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8e ), + .Q(\blk00000003/sig00000509 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8d ), + .Q(\blk00000003/sig0000050a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8c ), + .Q(\blk00000003/sig0000050b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8b ), + .Q(\blk00000003/sig0000050c ) + ); + GND \blk00000003/blk000003ad/blk000003ae ( + .G(\blk00000003/blk000003ad/sig00000d8a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003c0/blk000003d2 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003c0/sig00000db2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/blk000003c0/sig00000db1 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/blk000003c0/sig00000db0 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cf ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/blk000003c0/sig00000daf ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ce ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/blk000003c0/sig00000dae ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cd ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/blk000003c0/sig00000dad ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cc ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/blk000003c0/sig00000dac ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cb ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/blk000003c0/sig00000dab ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ca ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/blk000003c0/sig00000daa ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db1 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db0 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daf ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dae ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dad ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dac ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dab ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daa ), + .Q(\blk00000003/sig000004d4 ) + ); + GND \blk00000003/blk000003c0/blk000003c1 ( + .G(\blk00000003/blk000003c0/sig00000da9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d3/blk000003e5 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003d3/sig00000dd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e4 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk000003d3/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e3 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk000003d3/sig00000dcf ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e2 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk000003d3/sig00000dce ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e1 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk000003d3/sig00000dcd ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e0 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk000003d3/sig00000dcc ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003df ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk000003d3/sig00000dcb ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003de ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk000003d3/sig00000dca ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003dd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk000003d3/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dd0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcf ), + .Q(\blk00000003/sig00000558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dce ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcd ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcc ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcb ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dca ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dc9 ), + .Q(\blk00000003/sig0000055e ) + ); + GND \blk00000003/blk000003d3/blk000003d4 ( + .G(\blk00000003/blk000003d3/sig00000dc8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003e6/blk000003f8 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003e6/sig00000df0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/blk000003e6/sig00000def ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/blk000003e6/sig00000dee ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/blk000003e6/sig00000ded ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/blk000003e6/sig00000dec ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/blk000003e6/sig00000deb ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/blk000003e6/sig00000dea ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/blk000003e6/sig00000de9 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/blk000003e6/sig00000de8 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000def ), + .Q(\blk00000003/sig0000051f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dee ), + .Q(\blk00000003/sig00000520 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000ded ), + .Q(\blk00000003/sig00000521 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dec ), + .Q(\blk00000003/sig00000522 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000deb ), + .Q(\blk00000003/sig00000523 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dea ), + .Q(\blk00000003/sig00000524 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de9 ), + .Q(\blk00000003/sig00000525 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de8 ), + .Q(\blk00000003/sig00000526 ) + ); + GND \blk00000003/blk000003e6/blk000003e7 ( + .G(\blk00000003/blk000003e6/sig00000de7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000040b ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00000e0f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a3 ), + .Q(\blk00000003/blk000003f9/sig00000e0e ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000409 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a4 ), + .Q(\blk00000003/blk000003f9/sig00000e0d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000408 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a5 ), + .Q(\blk00000003/blk000003f9/sig00000e0c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000407 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a6 ), + .Q(\blk00000003/blk000003f9/sig00000e0b ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000406 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a7 ), + .Q(\blk00000003/blk000003f9/sig00000e0a ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000405 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a8 ), + .Q(\blk00000003/blk000003f9/sig00000e09 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000404 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a9 ), + .Q(\blk00000003/blk000003f9/sig00000e08 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000403 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003aa ), + .Q(\blk00000003/blk000003f9/sig00000e07 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0e ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0d ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0c ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0b ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0a ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e09 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e08 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e07 ), + .Q(\blk00000003/sig0000056e ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00000e06 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000040c/blk0000041e ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk0000040c/sig00000e2e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/blk0000040c/sig00000e2d ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/blk0000040c/sig00000e2c ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/blk0000040c/sig00000e2b ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/blk0000040c/sig00000e2a ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000419 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/blk0000040c/sig00000e29 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000418 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/blk0000040c/sig00000e28 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000417 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/blk0000040c/sig00000e27 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000416 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/blk0000040c/sig00000e26 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000415 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2d ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000414 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2c ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000413 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2b ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000412 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2a ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000411 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e29 ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000410 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e28 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e27 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e26 ), + .Q(\blk00000003/sig00000566 ) + ); + GND \blk00000003/blk0000040c/blk0000040d ( + .G(\blk00000003/blk0000040c/sig00000e25 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f/blk00000431 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk0000041f/sig00000e4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000430 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f5 ), + .Q(\blk00000003/blk0000041f/sig00000e4c ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f6 ), + .Q(\blk00000003/blk0000041f/sig00000e4b ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f7 ), + .Q(\blk00000003/blk0000041f/sig00000e4a ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f8 ), + .Q(\blk00000003/blk0000041f/sig00000e49 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f9 ), + .Q(\blk00000003/blk0000041f/sig00000e48 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fa ), + .Q(\blk00000003/blk0000041f/sig00000e47 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fb ), + .Q(\blk00000003/blk0000041f/sig00000e46 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000429 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fc ), + .Q(\blk00000003/blk0000041f/sig00000e45 ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4c ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4b ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4a ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e49 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e48 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e47 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e46 ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e45 ), + .Q(\blk00000003/sig00000590 ) + ); + GND \blk00000003/blk0000041f/blk00000420 ( + .G(\blk00000003/blk0000041f/sig00000e44 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000432/blk00000444 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000432/sig00000e6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000443 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/blk00000432/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000442 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/blk00000432/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000441 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/blk00000432/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000440 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/blk00000432/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/blk00000432/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000432/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000432/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000432/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6b ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6a ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000439 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e69 ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000438 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e68 ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000437 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e67 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e66 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e65 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e64 ), + .Q(\blk00000003/sig00000588 ) + ); + GND \blk00000003/blk00000432/blk00000433 ( + .G(\blk00000003/blk00000432/sig00000e63 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000445/blk00000457 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000445/sig00000e8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000456 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000445/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000455 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000445/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000454 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000445/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000453 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000445/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000452 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000445/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000451 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000445/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000450 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000445/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk0000044f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000445/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e8a ), + .Q(\blk00000003/sig000003a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e89 ), + .Q(\blk00000003/sig000003a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e88 ), + .Q(\blk00000003/sig000003a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e87 ), + .Q(\blk00000003/sig000003a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e86 ), + .Q(\blk00000003/sig000003a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e85 ), + .Q(\blk00000003/sig000003a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e84 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e83 ), + .Q(\blk00000003/sig000003aa ) + ); + GND \blk00000003/blk00000445/blk00000446 ( + .G(\blk00000003/blk00000445/sig00000e82 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000458/blk0000046a ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk00000458/sig00000eaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000469 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000458/sig00000ea9 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000468 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000458/sig00000ea8 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000467 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000458/sig00000ea7 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000466 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000458/sig00000ea6 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000465 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000458/sig00000ea5 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000464 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000458/sig00000ea4 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000463 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000458/sig00000ea3 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000462 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000458/sig00000ea2 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea9 ), + .Q(\blk00000003/sig0000039b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea8 ), + .Q(\blk00000003/sig0000039c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea7 ), + .Q(\blk00000003/sig0000039d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea6 ), + .Q(\blk00000003/sig0000039e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea5 ), + .Q(\blk00000003/sig0000039f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea4 ), + .Q(\blk00000003/sig000003a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea3 ), + .Q(\blk00000003/sig000003a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea2 ), + .Q(\blk00000003/sig000003a2 ) + ); + GND \blk00000003/blk00000458/blk00000459 ( + .G(\blk00000003/blk00000458/sig00000ea1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000046b/blk0000047d ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000046b/sig00000ec9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk0000046b/sig00000ec8 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk0000046b/sig00000ec7 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk0000046b/sig00000ec6 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000479 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk0000046b/sig00000ec5 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000478 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk0000046b/sig00000ec4 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000477 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk0000046b/sig00000ec3 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000476 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk0000046b/sig00000ec2 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000475 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk0000046b/sig00000ec1 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000474 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec8 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec7 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec6 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec5 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec4 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec3 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec2 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec1 ), + .Q(\blk00000003/sig000003fc ) + ); + GND \blk00000003/blk0000046b/blk0000046c ( + .G(\blk00000003/blk0000046b/sig00000ec0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000047e/blk00000490 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000047e/sig00000ee8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk0000047e/sig00000ee7 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk0000047e/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk0000047e/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk0000047e/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk0000047e/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk0000047e/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000489 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk0000047e/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000488 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk0000047e/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee7 ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee6 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee5 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000484 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee4 ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000483 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee3 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000482 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee2 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000481 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee1 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000480 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee0 ), + .Q(\blk00000003/sig000003f4 ) + ); + GND \blk00000003/blk0000047e/blk0000047f ( + .G(\blk00000003/blk0000047e/sig00000edf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e1/blk00000507 ( + .I0(\blk00000003/sig00000305 ), + .I1(ce), + .O(\blk00000003/blk000004e1/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000506 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000505 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000504 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000503 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000502 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000501 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000500 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004ff ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fe ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fd ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fc ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fb ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fa ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f9 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f8 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f7 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f6 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f5 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f24 ), + .Q(\blk00000003/sig000001a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f23 ), + .Q(\blk00000003/sig000001a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f22 ), + .Q(\blk00000003/sig000001aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f21 ), + .Q(\blk00000003/sig000001ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f20 ), + .Q(\blk00000003/sig000001ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1f ), + .Q(\blk00000003/sig000001ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1e ), + .Q(\blk00000003/sig000001ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1d ), + .Q(\blk00000003/sig000001af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1c ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1b ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1a ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f19 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f18 ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f17 ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f16 ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f15 ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f14 ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f13 ), + .Q(\blk00000003/sig000001b9 ) + ); + GND \blk00000003/blk000004e1/blk000004e2 ( + .G(\blk00000003/blk000004e1/sig00000f12 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo new file mode 100644 index 000000000..ce561daa2 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec2 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec2.v when simulating +// the core, hbdec2. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco new file mode 100644 index 000000000..1a4ba91f8 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Fri Jan 9 20:45:11 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx150t +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=4 +CSET component_name=hbdec2 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=32 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 80021ddf diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif new file mode 100644 index 000000000..079623297 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_0.mif @@ -0,0 +1,9 @@ +111111111111000010 +000000000011000010 +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif new file mode 100644 index 000000000..d4a0b357e --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_1.mif @@ -0,0 +1,9 @@ +111111101000011111 +000000100110101110 +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif new file mode 100644 index 000000000..6d9d6044f --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto0_2.mif @@ -0,0 +1,9 @@ +111101110000011101 +000011100100101000 +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt new file mode 100644 index 000000000..d0a6a5443 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_flist.txt @@ -0,0 +1,19 @@ +# Output products list for +hbdec2.asy +hbdec2.gise +hbdec2.mif +hbdec2.ngc +hbdec2.v +hbdec2.veo +hbdec2.xco +hbdec2.xise +hbdec2COEFF_auto0_0.mif +hbdec2COEFF_auto0_1.mif +hbdec2COEFF_auto0_2.mif +hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +hbdec2_flist.txt +hbdec2_readme.txt +hbdec2_reload_addrfilt_decode_rom.mif +hbdec2_reload_order.txt +hbdec2_xmdf.tcl +hbdec2filt_decode_rom.mif diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt new file mode 100644 index 000000000..bcda9c01c --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_readme.txt @@ -0,0 +1,75 @@ +The following files were generated for 'hbdec2' in directory +/disk2/ianb/ettus/fpgadev2/fpgadev/usrp3/top/b200/coregen_dsp/ + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec2_flist.txt + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec2.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec2.ngc + * hbdec2.v + * hbdec2.veo + * hbdec2COEFF_auto0_0.mif + * hbdec2COEFF_auto0_1.mif + * hbdec2COEFF_auto0_2.mif + * hbdec2COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec2_reload_addrfilt_decode_rom.mif + * hbdec2filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec2.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec2.asy + * hbdec2.mif + * hbdec2_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec2_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec2.gise + * hbdec2.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec2_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec2_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt new file mode 100644 index 000000000..071b84e5b --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 16 +Reload index 1 = Index 18 +Reload index 2 = Index 20 +Reload index 3 = Index 22 +Reload index 4 = Index 8 +Reload index 5 = Index 10 +Reload index 6 = Index 12 +Reload index 7 = Index 14 +Reload index 8 = Index 0 +Reload index 9 = Index 2 +Reload index 10 = Index 4 +Reload index 11 = Index 6 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl new file mode 100644 index 000000000..efebbe070 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2_xmdf.tcl @@ -0,0 +1,99 @@ +# The package naming convention is _xmdf +package provide hbdec2_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec2_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec2_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2 +} +# ::hbdec2_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec2_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif b/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b200/coregen_dsp/hbdec2filt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b200/gpio.ucf b/fpga/usrp3/top/b200/gpio.ucf new file mode 100644 index 000000000..1bccafe0d --- /dev/null +++ b/fpga/usrp3/top/b200/gpio.ucf @@ -0,0 +1,12 @@ + + +## GPIO bus - These pins are N/C on the LX75 +NET "fp_gpio<0>" LOC = "F8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<1>" LOC = "E8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<2>" LOC = "F9" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<3>" LOC = "G8" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<4>" LOC = "H10" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<5>" LOC = "G9" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<6>" LOC = "F10" | IOSTANDARD = LVCMOS33 | PULLUP ; +NET "fp_gpio<7>" LOC = "E10" | IOSTANDARD = LVCMOS33 | PULLUP ; + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif new file mode 100644 index 000000000..897eebbf3 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/cache/b200_ngc_d1c0f267.edif @@ -0,0 +1,59025 @@ +(edif b200 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2013 1 29 17 25 52) + (program "Xilinx ngc2edif" (version "P.49d")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure b200.ngc b200.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell FDP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port PRE + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUFG + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell ODDR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port C0 + (direction INPUT) + ) + (port C1 + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell BUFG + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port O + (direction OUTPUT) + ) + (port I + (direction INPUT) + ) + ) + ) + ) + (cell DCM_SP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK2X180 + (direction OUTPUT) + ) + (port PSCLK + (direction INPUT) + ) + (port CLK2X + (direction OUTPUT) + ) + (port CLKFX + (direction OUTPUT) + ) + (port CLK180 + (direction OUTPUT) + ) + (port CLK270 + (direction OUTPUT) + ) + (port RST + (direction INPUT) + ) + (port PSINCDEC + (direction INPUT) + ) + (port CLKIN + (direction INPUT) + ) + (port CLKFB + (direction INPUT) + ) + (port PSEN + (direction INPUT) + ) + (port CLK0 + (direction OUTPUT) + ) + (port CLKFX180 + (direction OUTPUT) + ) + (port CLKDV + (direction OUTPUT) + ) + (port PSDONE + (direction OUTPUT) + ) + (port CLK90 + (direction OUTPUT) + ) + (port LOCKED + (direction OUTPUT) + ) + (port DSSEN + (direction INPUT) + ) + (port (rename STATUS_7_ "STATUS<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename STATUS_6_ "STATUS<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename STATUS_5_ "STATUS<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename STATUS_4_ "STATUS<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename STATUS_3_ "STATUS<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename STATUS_2_ "STATUS<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename STATUS_1_ "STATUS<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename STATUS_0_ "STATUS<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "STATUS<7:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + ) + ) + ) + (cell IBUFGDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port IB + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDRE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FD + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDSE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell SRLC32E + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + (port Q31 + (direction OUTPUT) + ) + (port (array (rename A "A<4:0>") 5) + (direction INPUT)) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXF7 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IOBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port T + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + (port IO + (direction OUTPUT) + ) + ) + ) + ) + (cell RAMB8BWER + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port RSTBRST + (direction INPUT) + ) + (port ENBRDEN + (direction INPUT) + ) + (port REGCEA + (direction INPUT) + ) + (port ENAWREN + (direction INPUT) + ) + (port CLKAWRCLK + (direction INPUT) + ) + (port CLKBRDCLK + (direction INPUT) + ) + (port REGCEBREGCE + (direction INPUT) + ) + (port RSTA + (direction INPUT) + ) + (port (array (rename WEAWEL "WEAWEL<1:0>") 2) + (direction INPUT)) + (port (array (rename DOADO "DOADO<15:0>") 16) + (direction OUTPUT)) + (port (array (rename DOPADOP "DOPADOP<1:0>") 2) + (direction OUTPUT)) + (port (array (rename DOPBDOP "DOPBDOP<1:0>") 2) + (direction OUTPUT)) + (port (array (rename WEBWEU "WEBWEU<1:0>") 2) + (direction INPUT)) + (port (array (rename ADDRAWRADDR "ADDRAWRADDR<12:0>") 13) + (direction INPUT)) + (port (array (rename DIPBDIP "DIPBDIP<1:0>") 2) + (direction INPUT)) + (port (array (rename DIBDI "DIBDI<15:0>") 16) + (direction INPUT)) + (port (array (rename DIADI "DIADI<15:0>") 16) + (direction INPUT)) + (port (array (rename ADDRBRDADDR "ADDRBRDADDR<12:0>") 13) + (direction INPUT)) + (port (array (rename DOBDO "DOBDO<15:0>") 16) + (direction OUTPUT)) + (port (array (rename DIPADIP "DIPADIP<1:0>") 2) + (direction INPUT)) + ) + ) + ) + (cell RAMB16BWER + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port REGCEA + (direction INPUT) + ) + (port CLKA + (direction INPUT) + ) + (port ENB + (direction INPUT) + ) + (port RSTB + (direction INPUT) + ) + (port CLKB + (direction INPUT) + ) + (port REGCEB + (direction INPUT) + ) + (port RSTA + (direction INPUT) + ) + (port ENA + (direction INPUT) + ) + (port (array (rename DIPA "DIPA<3:0>") 4) + (direction INPUT)) + (port (array (rename WEA "WEA<3:0>") 4) + (direction INPUT)) + (port (array (rename DOA "DOA<31:0>") 32) + (direction OUTPUT)) + (port (array (rename ADDRA "ADDRA<13:0>") 14) + (direction INPUT)) + (port (array (rename ADDRB "ADDRB<13:0>") 14) + (direction INPUT)) + (port (array (rename DIB "DIB<31:0>") 32) + (direction INPUT)) + (port (array (rename DOPA "DOPA<3:0>") 4) + (direction OUTPUT)) + (port (array (rename DIPB "DIPB<3:0>") 4) + (direction INPUT)) + (port (array (rename DOPB "DOPB<3:0>") 4) + (direction OUTPUT)) + (port (array (rename DOB "DOB<31:0>") 32) + (direction OUTPUT)) + (port (array (rename WEB "WEB<3:0>") 4) + (direction INPUT)) + (port (array (rename DIA "DIA<31:0>") 32) + (direction INPUT)) + ) + ) + ) + ) + + (library b200_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell fifo_4k_2clk + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port rst + (direction INPUT) + ) + (port wr_clk + (direction INPUT) + ) + (port rd_clk + (direction INPUT) + ) + (port wr_en + (direction INPUT) + ) + (port rd_en + (direction INPUT) + ) + (port full + (direction OUTPUT) + ) + (port empty + (direction OUTPUT) + ) + (port (array (rename din "din<71:0>") 72) + (direction INPUT)) + (port (array (rename dout "dout<71:0>") 72) + (direction OUTPUT)) + (port (array (rename rd_data_count "rd_data_count<9:0>") 10) + (direction OUTPUT)) + (port (array (rename wr_data_count "wr_data_count<9:0>") 10) + (direction OUTPUT)) + ) + ) + ) + (cell b200 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port cat_miso + (direction INPUT) + ) + (port fx3_ce + (direction INPUT) + ) + (port fx3_mosi + (direction INPUT) + ) + (port fx3_sclk + (direction INPUT) + ) + (port FPGA_RXD0 + (direction INPUT) + ) + (port FPGA_TXD0 + (direction INPUT) + ) + (port SCL_FPGA + (direction INPUT) + ) + (port SDA_FPGA + (direction INPUT) + ) + (port codec_data_clk_p + (direction INPUT) + ) + (port rx_frame_p + (direction INPUT) + ) + (port cat_clkout_fpga + (direction INPUT) + ) + (port codec_main_clk_p + (direction INPUT) + ) + (port codec_main_clk_n + (direction INPUT) + ) + (port GPIF_CTL4 + (direction INPUT) + ) + (port GPIF_CTL5 + (direction INPUT) + ) + (port GPIF_CTL6 + (direction INPUT) + ) + (port GPIF_CTL8 + (direction INPUT) + ) + (port GPIF_CTL9 + (direction INPUT) + ) + (port gps_lock + (direction INPUT) + ) + (port gps_rxd + (direction INPUT) + ) + (port gps_txd + (direction INPUT) + ) + (port gps_txd_nmea + (direction INPUT) + ) + (port pll_lock + (direction INPUT) + ) + (port FPGA_CFG_CS + (direction INPUT) + ) + (port AUX_PWR_ON + (direction INPUT) + ) + (port PPS_IN_EXT + (direction INPUT) + ) + (port PPS_IN_INT + (direction INPUT) + ) + (port pps_out + (direction INPUT) + ) + (port cat_ce + (direction OUTPUT) + ) + (port cat_mosi + (direction OUTPUT) + ) + (port cat_sclk + (direction OUTPUT) + ) + (port fx3_miso + (direction OUTPUT) + ) + (port pll_ce + (direction OUTPUT) + ) + (port pll_mosi + (direction OUTPUT) + ) + (port pll_sclk + (direction OUTPUT) + ) + (port codec_enable + (direction OUTPUT) + ) + (port codec_en_agc + (direction OUTPUT) + ) + (port codec_reset + (direction OUTPUT) + ) + (port codec_sync + (direction OUTPUT) + ) + (port codec_txrx + (direction OUTPUT) + ) + (port codec_fb_clk_p + (direction OUTPUT) + ) + (port tx_frame_p + (direction OUTPUT) + ) + (port IFCLK + (direction OUTPUT) + ) + (port FX3_EXTINT + (direction OUTPUT) + ) + (port GPIF_CTL0 + (direction OUTPUT) + ) + (port GPIF_CTL1 + (direction OUTPUT) + ) + (port GPIF_CTL2 + (direction OUTPUT) + ) + (port GPIF_CTL3 + (direction OUTPUT) + ) + (port GPIF_CTL7 + (direction OUTPUT) + ) + (port GPIF_CTL11 + (direction OUTPUT) + ) + (port GPIF_CTL12 + (direction OUTPUT) + ) + (port gps_out_enable + (direction OUTPUT) + ) + (port gps_ref_enable + (direction OUTPUT) + ) + (port LED_RX1 + (direction OUTPUT) + ) + (port LED_RX2 + (direction OUTPUT) + ) + (port LED_TXRX1_RX + (direction OUTPUT) + ) + (port LED_TXRX1_TX + (direction OUTPUT) + ) + (port LED_TXRX2_RX + (direction OUTPUT) + ) + (port LED_TXRX2_TX + (direction OUTPUT) + ) + (port ext_ref_enable + (direction OUTPUT) + ) + (port pps_fpga_out_enable + (direction OUTPUT) + ) + (port SFDX1_RX + (direction OUTPUT) + ) + (port SFDX1_TX + (direction OUTPUT) + ) + (port SFDX2_RX + (direction OUTPUT) + ) + (port SFDX2_TX + (direction OUTPUT) + ) + (port SRX1_RX + (direction OUTPUT) + ) + (port SRX1_TX + (direction OUTPUT) + ) + (port SRX2_RX + (direction OUTPUT) + ) + (port SRX2_TX + (direction OUTPUT) + ) + (port tx_bandsel_a + (direction OUTPUT) + ) + (port tx_bandsel_b + (direction OUTPUT) + ) + (port tx_enable1 + (direction OUTPUT) + ) + (port tx_enable2 + (direction OUTPUT) + ) + (port rx_bandsel_a + (direction OUTPUT) + ) + (port rx_bandsel_b + (direction OUTPUT) + ) + (port rx_bandsel_c + (direction OUTPUT) + ) + (port (array (rename codec_ctrl_out "codec_ctrl_out<7:0>") 8) + (direction INPUT)) + (port (array (rename rx_codec_d "rx_codec_d<11:0>") 12) + (direction INPUT)) + (port (array (rename codec_ctrl_in "codec_ctrl_in<3:0>") 4) + (direction OUTPUT)) + (port (array (rename tx_codec_d "tx_codec_d<11:0>") 12) + (direction OUTPUT)) + (port (array (rename debug "debug<31:0>") 32) + (direction OUTPUT)) + (port (array (rename debug_clk "debug_clk<1:0>") 2) + (direction OUTPUT)) + (port (array (rename GPIF_D "GPIF_D<31:0>") 32) + (direction INOUT)) + (designator "xc6slx75-3-fgg484") + (property TYPE (string "b200") (owner "Xilinx")) + (property BUS_INFO (string "8:INPUT:codec_ctrl_out<7:0>") (owner "Xilinx")) + (property BUS_INFO (string "12:INPUT:rx_codec_d<11:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:codec_ctrl_in<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "12:OUTPUT:tx_codec_d<11:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:OUTPUT:debug<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:debug_clk<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4") (owner "Xilinx")) + (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "b200_b200") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename bus_sync_reset_out_renamed_0 "bus_sync/reset_out") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename bus_sync_reset_int_renamed_1 "bus_sync/reset_int") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gpif_sync_reset_out_renamed_2 "gpif_sync/reset_out") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gpif_sync_reset_int_renamed_3 "gpif_sync/reset_int") + (viewRef view_1 (cellRef FDP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_data_clk_bufg + (viewRef view_1 (cellRef IBUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx")) + (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx")) + (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx")) + (property IOSTANDARD (string "DEFAULT") (owner "Xilinx")) + ) + (instance ODDR2_ifclk + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance ODDR2_ifclk_dbg + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "NONE") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf") + (viewRef view_1 (cellRef BUFG (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst") + (viewRef view_1 (cellRef DCM_SP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>") (owner "Xilinx")) + (property CLKIN_DIVIDE_BY_2 (string "FALSE") (owner "Xilinx")) + (property CLKOUT_PHASE_SHIFT (string "NONE") (owner "Xilinx")) + (property CLK_FEEDBACK (string "1X") (owner "Xilinx")) + (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS") (owner "Xilinx")) + (property DFS_FREQUENCY_MODE (string "LOW") (owner "Xilinx")) + (property DLL_FREQUENCY_MODE (string "LOW") (owner "Xilinx")) + (property DSS_MODE (string "NONE") (owner "Xilinx")) + (property DUTY_CYCLE_CORRECTION (string "TRUE") (owner "Xilinx")) + (property FACTORY_JF (string "16'B1100000010000000") (owner "Xilinx")) + (property STARTUP_WAIT (string "FALSE") (owner "Xilinx")) + (property CLKFX_DIVIDE (integer 2) (owner "Xilinx")) + (property CLKFX_MULTIPLY (integer 5) (owner "Xilinx")) + (property PHASE_SHIFT (integer 0) (owner "Xilinx")) + (property CLKDV_DIVIDE (number (e 2 0)) (owner "Xilinx")) + (property CLKIN_PERIOD (string "25.000000") (owner "Xilinx")) + (property VERY_HIGH_FREQUENCY (string "FALSE") (owner "Xilinx")) + ) + (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf") + (viewRef view_1 (cellRef IBUFGDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property CAPACITANCE (string "DONT_CARE") (owner "Xilinx")) + (property DIFF_TERM (string "FALSE") (owner "Xilinx")) + (property IBUF_DELAY_VALUE (string "0") (owner "Xilinx")) + (property IBUF_LOW_PWR (string "TRUE") (owner "Xilinx")) + (property IOSTANDARD (string "DEFAULT") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_renamed_4 "slave_fifo32/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_renamed_5 "slave_fifo32/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_pktend_renamed_6 "slave_fifo32/pktend") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slwr_renamed_7 "slave_fifo32/slwr") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd3_renamed_8 "slave_fifo32/slrd3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd2_renamed_9 "slave_fifo32/slrd2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd1_renamed_10 "slave_fifo32/slrd1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK1_renamed_11 "slave_fifo32/EP_WMARK1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY1_renamed_12 "slave_fifo32/EP_READY1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY_renamed_13 "slave_fifo32/EP_READY") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_write_ready_go_renamed_14 "slave_fifo32/write_ready_go") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_read_ready_go_renamed_15 "slave_fifo32/read_ready_go") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK_renamed_16 "slave_fifo32/EP_WMARK") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename catgen_oddr2_clk "catgen/oddr2_clk") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_oddr2_frame "catgen/oddr2_frame") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2") + (viewRef view_1 (cellRef ODDR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property DDR_ALIGNMENT (string "C0") (owner "Xilinx")) + (property SRTYPE (string "ASYNC") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_18 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_renamed_19 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_renamed_20 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_renamed_21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready_renamed_22 "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_renamed_23 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_renamed_24 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e") + (viewRef view_1 (cellRef SRLC32E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:A<4:0>") (owner "Xilinx")) + (property INIT (string "00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready_renamed_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_4__ "f1/Mcompar_becoming_full_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_4__ "f1/Mcompar_becoming_full_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_3__ "f1/Mcompar_becoming_full_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_3__ "f1/Mcompar_becoming_full_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_2__ "f1/Mcompar_becoming_full_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_2__ "f1/Mcompar_becoming_full_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_1__ "f1/Mcompar_becoming_full_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_1__ "f1/Mcompar_becoming_full_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_0__ "f1/Mcompar_becoming_full_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_0__ "f1/Mcompar_becoming_full_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_12__ "f1/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_11__ "f1/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11__ "f1/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_10__ "f1/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_10__ "f1/Mcount_rd_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_9__ "f1/Mcount_rd_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_9__ "f1/Mcount_rd_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_8__ "f1/Mcount_rd_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_8__ "f1/Mcount_rd_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_7__ "f1/Mcount_rd_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7__ "f1/Mcount_rd_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_6__ "f1/Mcount_rd_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6__ "f1/Mcount_rd_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_5__ "f1/Mcount_rd_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_5__ "f1/Mcount_rd_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_4__ "f1/Mcount_rd_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_4__ "f1/Mcount_rd_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_3__ "f1/Mcount_rd_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3__ "f1/Mcount_rd_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_2__ "f1/Mcount_rd_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2__ "f1/Mcount_rd_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_1__ "f1/Mcount_rd_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_1__ "f1/Mcount_rd_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_xor_0__ "f1/Mcount_rd_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_cy_0__ "f1/Mcount_rd_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_12__ "f1/Mcount_wr_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_11__ "f1/Mcount_wr_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11__ "f1/Mcount_wr_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_10__ "f1/Mcount_wr_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10__ "f1/Mcount_wr_addr_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_9__ "f1/Mcount_wr_addr_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_9__ "f1/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_8__ "f1/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_8__ "f1/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_7__ "f1/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7__ "f1/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_6__ "f1/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6__ "f1/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_5__ "f1/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5__ "f1/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_4__ "f1/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_4__ "f1/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_3__ "f1/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_3__ "f1/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_2__ "f1/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2__ "f1/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_1__ "f1/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1__ "f1/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_xor_0__ "f1/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_cy_0__ "f1/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_12__ "f1/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_11__ "f1/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_11__ "f1/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_10__ "f1/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_10__ "f1/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_9__ "f1/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_9__ "f1/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_8__ "f1/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_8__ "f1/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_7__ 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f1_Msub_dont_write_past_me_cy_5__ "f1/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_4__ "f1/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_4__ "f1/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_3__ "f1/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_3__ "f1/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) 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(viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_12__ "f0/Mcount_rd_addr_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_11__ "f0/Mcount_rd_addr_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11__ "f0/Mcount_rd_addr_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_xor_10__ "f0/Mcount_rd_addr_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10__ 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(true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_9__ "f0/Mcount_wr_addr_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_8__ "f0/Mcount_wr_addr_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_8__ "f0/Mcount_wr_addr_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_7__ "f0/Mcount_wr_addr_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_7__ "f0/Mcount_wr_addr_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_6__ "f0/Mcount_wr_addr_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6__ "f0/Mcount_wr_addr_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_5__ "f0/Mcount_wr_addr_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5__ "f0/Mcount_wr_addr_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_4__ "f0/Mcount_wr_addr_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4__ "f0/Mcount_wr_addr_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_3__ "f0/Mcount_wr_addr_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3__ "f0/Mcount_wr_addr_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_2__ "f0/Mcount_wr_addr_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_2__ "f0/Mcount_wr_addr_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_1__ "f0/Mcount_wr_addr_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_1__ "f0/Mcount_wr_addr_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_xor_0__ "f0/Mcount_wr_addr_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_cy_0__ "f0/Mcount_wr_addr_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_12__ "f0/Msub_dont_write_past_me_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_11__ "f0/Msub_dont_write_past_me_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_11__ "f0/Msub_dont_write_past_me_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_10__ "f0/Msub_dont_write_past_me_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_10__ "f0/Msub_dont_write_past_me_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_9__ "f0/Msub_dont_write_past_me_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_9__ "f0/Msub_dont_write_past_me_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_8__ "f0/Msub_dont_write_past_me_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_8__ "f0/Msub_dont_write_past_me_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_7__ "f0/Msub_dont_write_past_me_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_7__ "f0/Msub_dont_write_past_me_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_6__ "f0/Msub_dont_write_past_me_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_6__ "f0/Msub_dont_write_past_me_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_5__ "f0/Msub_dont_write_past_me_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_5__ "f0/Msub_dont_write_past_me_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_4__ "f0/Msub_dont_write_past_me_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_4__ "f0/Msub_dont_write_past_me_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_3__ "f0/Msub_dont_write_past_me_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_3__ "f0/Msub_dont_write_past_me_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_2__ "f0/Msub_dont_write_past_me_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_2__ "f0/Msub_dont_write_past_me_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_1__ "f0/Msub_dont_write_past_me_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1__ "f0/Msub_dont_write_past_me_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_0__ "f0/Msub_dont_write_past_me_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0__ "f0/Msub_dont_write_past_me_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_0 "f0/wr_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_0 "f0/rd_addr_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd1_renamed_31 "f0/read_state_FSM_FFd1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd2_renamed_32 "f0/read_state_FSM_FFd2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_12 "f0/wr_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_11 "f0/wr_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_10 "f0/wr_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_9 "f0/wr_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_8 "f0/wr_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_7 "f0/wr_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_6 "f0/wr_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_5 "f0/wr_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_4 "f0/wr_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_3 "f0/wr_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_2 "f0/wr_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_wr_addr_1 "f0/wr_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_12 "f0/rd_addr_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_11 "f0/rd_addr_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_10 "f0/rd_addr_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_9 "f0/rd_addr_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_8 "f0/rd_addr_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_7 "f0/rd_addr_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_6 "f0/rd_addr_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_5 "f0/rd_addr_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_4 "f0/rd_addr_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_3 "f0/rd_addr_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_2 "f0/rd_addr_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_rd_addr_1 "f0/rd_addr_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance fx3_miso1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance cat_mosi1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance cat_sclk1 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance reset_global_locked_OR_1_o1 + (viewRef view_1 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view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx")) + (property INIT (string "82") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5410") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11") (owner "Xilinx")) + (property INIT (string "14") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11") (owner "Xilinx")) + (property INIT (string "A8880888") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1") (owner "Xilinx")) + (property INIT (string "20002222") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00010000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99AA99A6AAAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "0111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "FEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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INIT (string "C9C9C9C900FFFF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (owner "Xilinx")) + (property INIT (string "54") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx")) + (property INIT (string "0455") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "69") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (owner "Xilinx")) + (property INIT (string "6AA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "0111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (owner "Xilinx")) + (property INIT (string "FEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance 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"___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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"___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx")) + (property INIT (string "0455") (owner "Xilinx")) + ) + (instance (rename f1_write11 "f1/write11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename f0_write11 "f0/write11") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_renamed_33 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_renamed_34 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx")) + (property INIT (string "D0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "777FF7FFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (owner "Xilinx")) + (property INIT (string "80008080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2A7F7F7FFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32__n0279_inv_renamed_35 "slave_fifo32/_n0279_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0020202008282828") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In2_renamed_36 "slave_fifo32/state_FSM_FFd1-In2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2700050022000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In1_renamed_37 "slave_fifo32/state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In2_renamed_38 "slave_fifo32/state_FSM_FFd2-In2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1054101010101010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4") (owner "Xilinx")) + (property INIT (string "FFF4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000C0000000800") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1555555555555555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9CCC9CC6CCCCCCC6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C000000080000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1555555555555555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "FF57") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04040000FF04FF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212_renamed_40 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0010001000000010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214_renamed_41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216_renamed_42 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FAF8AA0000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113_renamed_43 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114_renamed_44 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB33A820A820A820") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_renamed_45 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_renamed_46 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000001FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCC0F5AF05A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF05A0F5A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_47 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000010005") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14_renamed_48 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "010F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4_renamed_49 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (owner "Xilinx")) + (property INIT (string "A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31_renamed_50 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32_renamed_51 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFF9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12_renamed_52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFAAB9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (owner "Xilinx")) + (property INIT (string "FF57") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04040000FF04FF00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0010001000000010") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "99900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216_renamed_56 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FAF8AA0000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113_renamed_57 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB33A820A820A820") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A8A8A8A8B9A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219_renamed_59 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA08880800008008") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx")) + (property INIT (string "BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0111111111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000001FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF0550FAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0307") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFFFFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F700") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5_renamed_64 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (owner "Xilinx")) + (property INIT (string "DFDDFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFBEEEA55514440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAA2A080808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx")) + (property INIT (string "FFF9") (owner "Xilinx")) + ) + (instance (rename cat_miso_IBUF_renamed_69 "cat_miso_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_ce_IBUF_renamed_70 "fx3_ce_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_mosi_IBUF_renamed_71 "fx3_mosi_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_sclk_IBUF_renamed_72 "fx3_sclk_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL4_IBUF_renamed_73 "GPIF_CTL4_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL5_IBUF_renamed_74 "GPIF_CTL5_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename GPIF_CTL9_IBUF_renamed_75 "GPIF_CTL9_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_ctrl_in_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_11_OBUF_renamed_76 "tx_codec_d_11_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_10_OBUF_renamed_77 "tx_codec_d_10_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_9_OBUF_renamed_78 "tx_codec_d_9_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_8_OBUF_renamed_79 "tx_codec_d_8_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_7_OBUF_renamed_80 "tx_codec_d_7_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_6_OBUF_renamed_81 "tx_codec_d_6_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_5_OBUF_renamed_82 "tx_codec_d_5_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_4_OBUF_renamed_83 "tx_codec_d_4_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_3_OBUF_renamed_84 "tx_codec_d_3_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_2_OBUF_renamed_85 "tx_codec_d_2_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_1_OBUF_renamed_86 "tx_codec_d_1_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_codec_d_0_OBUF_renamed_87 "tx_codec_d_0_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_31_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_30_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_29_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_28_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_27_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_26_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_25_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_24_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_23_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_22_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_21_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_20_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_19_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_18_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_17_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_16_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_15_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_14_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_13_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_12_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_11_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_10_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_9_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_8_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_7_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_6_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_5_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_4_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename debug_clk_1_OBUF_renamed_88 "debug_clk_1_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance debug_clk_0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance cat_ce_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename cat_mosi_OBUF_renamed_89 "cat_mosi_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename cat_sclk_OBUF_renamed_90 "cat_sclk_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename fx3_miso_OBUF_renamed_91 "fx3_miso_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_ce_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_mosi_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pll_sclk_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_en_agc_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_reset_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_sync_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance codec_txrx_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename codec_fb_clk_p_OBUF_renamed_92 "codec_fb_clk_p_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename tx_frame_p_OBUF_renamed_93 "tx_frame_p_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename IFCLK_OBUF_renamed_94 "IFCLK_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance FX3_EXTINT_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL0_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL3_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL7_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL11_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_CTL12_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gps_out_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gps_ref_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_RX1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_RX2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance LED_TXRX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance ext_ref_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance pps_fpga_out_enable_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SFDX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX1_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX1_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX2_RX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance SRX2_TX_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_bandsel_a_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_bandsel_b_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_enable1_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance tx_enable2_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance rx_bandsel_a_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance rx_bandsel_b_OBUF + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename rx_bandsel_c_OBUF_renamed_95 "rx_bandsel_c_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_renamed_96 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_renamed_97 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_renamed_98 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_renamed_99 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_renamed_100 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_renamed_101 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_renamed_102 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_renamed_103 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_renamed_104 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_renamed_105 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_renamed_106 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_renamed_107 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_renamed_108 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_renamed_109 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_renamed_110 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_renamed_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_renamed_112 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_renamed_113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_renamed_114 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_renamed_115 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_full_reg_renamed_116 "f1/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_full_reg_renamed_117 "f0/full_reg") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_118 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_119 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt_renamed_120 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt_renamed_121 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt_renamed_122 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_123 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_124 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_125 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_126 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_127 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_128 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_129 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_130 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_131 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt_renamed_132 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt_renamed_133 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt_renamed_134 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_135 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_136 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_137 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_138 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_139 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_140 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_141 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_142 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_143 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt_renamed_144 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt_renamed_145 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt_renamed_146 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt_renamed_147 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt_renamed_148 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt_renamed_149 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt_renamed_150 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt_renamed_151 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt_renamed_152 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt_renamed_153 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt_renamed_154 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt_renamed_155 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt_renamed_156 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt_renamed_157 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt_renamed_158 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt_renamed_159 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt_renamed_160 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt_renamed_161 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_162 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_163 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_164 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_165 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_166 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_167 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_168 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_169 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_170 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_171 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_172 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_173 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_174 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_175 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_176 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_177 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt_renamed_178 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt_renamed_179 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt_renamed_186 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt_renamed_187 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt_renamed_188 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt_renamed_189 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB_renamed_264 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB_renamed_265 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB_renamed_266 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB_renamed_267 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB_renamed_268 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB_renamed_269 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB_renamed_270 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB_renamed_271 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB_renamed_272 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_273 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB_renamed_274 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB_renamed_275 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB_renamed_276 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB_renamed_277 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB_renamed_278 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB_renamed_279 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB_renamed_280 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB_renamed_281 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB_renamed_282 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB_renamed_283 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB_renamed_284 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB_renamed_285 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB_renamed_286 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_287 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_288 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB_renamed_289 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB_renamed_290 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB_renamed_291 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB_renamed_292 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB_renamed_293 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB_renamed_294 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB_renamed_295 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB_renamed_296 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB_renamed_309 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB_renamed_310 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB_renamed_311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename 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+ (instance (rename f0_Result_5_2_FRB_renamed_381 "f0/Result<5>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_6_2_FRB_renamed_382 "f0/Result<6>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_7_2_FRB_renamed_383 "f0/Result<7>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_8_2_FRB_renamed_384 "f0/Result<8>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_9_2_FRB_renamed_385 "f0/Result<9>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_10_2_FRB_renamed_386 "f0/Result<10>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_11_2_FRB_renamed_387 "f0/Result<11>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_12_2_FRB_renamed_388 "f0/Result<12>2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_0_1_FRB_renamed_389 "f0/Result<0>1_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_1_1_FRB_renamed_390 "f0/Result<1>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_2_1_FRB_renamed_391 "f0/Result<2>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_3_1_FRB_renamed_392 "f0/Result<3>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_4_1_FRB_renamed_393 "f0/Result<4>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_5_1_FRB_renamed_394 "f0/Result<5>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_6_1_FRB_renamed_395 "f0/Result<6>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_7_1_FRB_renamed_396 "f0/Result<7>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_8_1_FRB_renamed_397 "f0/Result<8>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_9_1_FRB_renamed_398 "f0/Result<9>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_10_1_FRB_renamed_399 "f0/Result<10>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_11_1_FRB_renamed_400 "f0/Result<11>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Result_12_1_FRB_renamed_401 "f0/Result<12>1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_0__FRB_renamed_402 "f0/dont_write_past_me<0>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_1__FRB_renamed_403 "f0/dont_write_past_me<1>_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_2__FRB_renamed_404 "f0/dont_write_past_me<2>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_3__FRB_renamed_405 "f0/dont_write_past_me<3>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_4__FRB_renamed_406 "f0/dont_write_past_me<4>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_5__FRB_renamed_407 "f0/dont_write_past_me<5>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_6__FRB_renamed_408 "f0/dont_write_past_me<6>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_7__FRB_renamed_409 "f0/dont_write_past_me<7>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_8__FRB_renamed_410 "f0/dont_write_past_me<8>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_9__FRB_renamed_411 "f0/dont_write_past_me<9>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_10__FRB_renamed_412 "f0/dont_write_past_me<10>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_11__FRB_renamed_413 "f0/dont_write_past_me<11>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_dont_write_past_me_12__FRB_renamed_414 "f0/dont_write_past_me<12>_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "55555504FFFFFF5D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (owner "Xilinx")) + (property INIT (string "F110") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0303CFCF0203DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "56555656") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx")) + (property INIT (string "6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "CCCCCCCCF50A05FA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEFEFEEEEEEEEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "54A855AA55AA55AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FFFF0000FEFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5555555555545555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0001FFFE0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F0E4D8CC00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (owner "Xilinx")) + (property INIT (string "A8EA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000023003300") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100010001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100010001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0EE00FF00FF00FF0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0021FFFF00FFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00F7000000F7F7F7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FFFB0004FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9AAA9A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8282414141418228") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8020401008020401") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8282414141418228") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF05FF04FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001FFFF00007FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF55FF01FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF55FF00FF55FF54") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_renamed_418 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FBFBFBFFFB00FB00") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AABAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4000FBFF4400FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFB0400FFFA0500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF00FFE8FF17FFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5599665556955695") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0000FFFF1000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set_renamed_420 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8FDA8A8A8A8A8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111000111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111000111111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "3333333333323333") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0C0C0C0C0C0D0C0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0404040404040504") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0C0C0C0C0C0C0D0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A521") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00008400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF008C008C008C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E1E1E1E10FF0F00F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A9A9A9A9AA5555AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00400000AAEAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEEEFEEE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFBF8FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "F0F0F0F08877EE11") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFDBFDDBFDFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FCBFFBEFFC7FF7DF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_renamed_423 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "350035F0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA3B8819AA2A8808") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAB9AAAAAAA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "FFAEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "FFAEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFEFEFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111_renamed_424 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2002000000002002") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111_renamed_425 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2002000000002002") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx")) + (property INIT (string "9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAA9AAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01FE00FF00FF807F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA8AAAAAAABAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "999A999999959999") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140514055555140") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140514055555140") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_426 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4C4CFF4C4C4C4C4C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "C8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "C8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217_renamed_427 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0080000000000080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0080000000000080") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "4500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "4500") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213_renamed_429 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9090900000900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9090900000900000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFF0FFFFFF80FF80") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9996") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_renamed_431 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4141414141411441") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set_renamed_432 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00400000AAEAAAAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (owner "Xilinx")) + (property INIT (string "04") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF0D2F087F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot_renamed_433 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "6AAA595566AA5555") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set_renamed_434 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "FFA2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set_renamed_435 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "FFA2") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "01") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut_renamed_436 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1111111011111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB_renamed_437 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB_renamed_438 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB_renamed_439 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB_renamed_440 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB_renamed_441 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB_renamed_442 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB_renamed_443 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB_renamed_444 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB_renamed_445 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB_renamed_446 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB_renamed_447 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB_renamed_448 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB_renamed_449 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB_renamed_450 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB_renamed_451 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB_renamed_452 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB_renamed_453 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB_renamed_454 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB_renamed_455 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB_renamed_456 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB_renamed_457 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB_renamed_458 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_459 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB_renamed_460 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB_renamed_461 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB_renamed_462 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB_renamed_463 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0_renamed_464 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1_renamed_465 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1_renamed_466 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1_renamed_467 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1_renamed_468 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0_renamed_469 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1_renamed_472 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1_renamed_473 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_474 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_475 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0_renamed_476 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_479 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_482 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_483 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_484 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1_renamed_485 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5_renamed_489 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1_renamed_490 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1_renamed_491 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1_renamed_492 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1_renamed_493 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1_renamed_494 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1_renamed_495 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_17_BRB0_renamed_496 "slave_fifo32/debug1_17_BRB0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_debug1_16_BRB0_renamed_497 "slave_fifo32/debug1_16_BRB0") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_rd_one_BRB0_renamed_498 "slave_fifo32/rd_one_BRB0") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_rd_one_BRB1_renamed_499 "slave_fifo32/rd_one_BRB1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112_renamed_500 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8822228C80202084") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8822228C80202084") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1_renamed_502 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3_renamed_503 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4_renamed_504 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (owner "Xilinx")) + (property INIT (string "EEEF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF0C080C0C0C0C") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "5400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "5400") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1_renamed_505 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF1110FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "11101110FFFF1110") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut_renamed_506 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000FAFB00000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "2E22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "2E22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFB8FF88") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C60ACC000A0A0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "C60ACC000A0A0000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_lut_renamed_507 "f1/_n0161_inv1_lut") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_lut1_renamed_508 "f1/_n0161_inv1_lut1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_lut_renamed_509 "f0/_n0161_inv1_lut") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_lut1_renamed_510 "f0/_n0161_inv1_lut1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "D") (owner "Xilinx")) + ) + (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFD") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFEFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEFFFEFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EEFFEFFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFEFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFAAAAFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FB") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx")) + (property INIT (string "FFFF7222") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_wr_one_rstpot_renamed_512 "slave_fifo32/wr_one_rstpot") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1") (owner "Xilinx")) + (property INIT (string "EEAAA2AA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set_renamed_513 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "A2A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set_renamed_514 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "A2A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_rstpot_renamed_515 "slave_fifo32/slrd_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA2AAAFAAA2AFAFA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_renamed_516 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00000000DD09C000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E178E1E1E1E1E1E1") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215_renamed_517 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0220000000000220") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215_renamed_518 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0220000000000220") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2272") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2272") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF4040BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF7FFFFFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (owner "Xilinx")) + (property INIT (string "BF4040BF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218_renamed_519 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "0440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218_renamed_520 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (owner "Xilinx")) + (property INIT (string "0440") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000000000001") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFFFFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0155115501111111") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (owner "Xilinx")) + (property INIT (string "CCC9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAAAAAAAAAAAAA9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (owner "Xilinx")) + (property INIT (string "CCC9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000000100000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1B") (owner "Xilinx")) + ) + (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "72") (owner "Xilinx")) + ) + (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "72") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (owner "Xilinx")) + (property INIT (string "4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_521 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "7F2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51_renamed_522 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA9AAAA6A696A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (owner "Xilinx")) + (property INIT (string "7F2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set_renamed_523 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (owner "Xilinx")) + (property INIT (string "5540FFC0") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A8A8A88820202000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF0040BFBF4000FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFF6FFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217_renamed_524 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "999F999699999990") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A6AAA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A6AAA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "FDA8") (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1") (owner "Xilinx")) + (property INIT (string "FDA8") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (owner "Xilinx")) + (property INIT (string "FFFF8D88") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "59555959") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "8A8ADF8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "8A8ADF8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0004FFFF00040004") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_renamed_526 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0004FFFF00040004") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (owner "Xilinx")) + (property INIT (string "9F") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_renamed_527 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0020000002200200") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8421000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8421000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000000000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set_renamed_528 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set_renamed_529 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (owner "Xilinx")) + (property INIT (string "A9") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "00440F44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (owner "Xilinx")) + (property INIT (string "00440F44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFF5455FFFF5657") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (owner "Xilinx")) + (property INIT (string "EA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FF66FF69FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFF7FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (owner "Xilinx")) + (property INIT (string "FFFF7FFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_renamed_531 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AA8AAA8AFFCFAA8A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF55555554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFF55555554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFCF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_532 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "9AAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41_renamed_533 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (owner "Xilinx")) + (property INIT (string "9AAAAAA6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_1_rstpot_renamed_534 "slave_fifo32/sloe_1_rstpot") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA2AAAAAAAFFAA") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_renamed_536 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FC55FC54FF55FF55") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "7FFF7F7F2AFF2A2A") (owner "Xilinx")) + ) + (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx")) + ) + (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FDFDFDFFA8A8A8FF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "00FBFB0005FBFB05") (owner "Xilinx")) + ) + (instance (rename f1_full_reg_glue_set_renamed_537 "f1/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___123___f1/write11") (owner "Xilinx")) + (property INIT (string "F0FF4044") (owner "Xilinx")) + ) + (instance (rename f0_full_reg_glue_set_renamed_538 "f0/full_reg_glue_set") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___122___f0/write11") (owner "Xilinx")) + (property INIT (string "F0FF4044") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "FFFF4B44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (owner "Xilinx")) + (property INIT (string "FFFF4B44") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "BB4BBBBBBB4BBB4B") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1_renamed_539 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_renamed_540 "slave_fifo32/sloe") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_rstpot_renamed_541 "slave_fifo32/sloe_rstpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_rstpot_renamed_542 "slave_fifo32/gpif_data_out_31_rstpot") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E4") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance gpif_clk_INV_4_o1_INV_0 + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename catcap_data_clk_INV_6_o1_INV_0 "catcap/data_clk_INV_6_o1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_renamed_543 "slave_fifo32/state_FSM_FFd1-In3") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F") + (viewRef view_1 (cellRef LUT5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "80808000") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04155555FFFFFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "AAAA2A22FFAA7F22") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "A2AAA6A6F7FFA6A6") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FFFFFFFFFFFF5554") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G") + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "FE") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2") + (viewRef view_1 (cellRef MUXF7 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "EFEEEFEEEFEEFFFF") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "54555454FCFFFCFC") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd2_1_renamed_544 "slave_fifo32/slrd2_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_WMARK1_1_renamed_545 "slave_fifo32/EP_WMARK1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_EP_READY1_1_renamed_546 "slave_fifo32/EP_READY1_1") + (viewRef view_1 (cellRef FD (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_1_renamed_547 "slave_fifo32/gpif_data_out_31_1") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slwr_1_renamed_548 "slave_fifo32/slwr_1") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_34_renamed_549 "slave_fifo32/sloe_34") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_slrd_1_renamed_550 "slave_fifo32/slrd_1") + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_pktend_1_renamed_551 "slave_fifo32/pktend_1") + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_1_1_renamed_552 "slave_fifo32/fifoadr_1_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifoadr_0_1_renamed_553 "slave_fifo32/fifoadr_0_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance GPIF_D_31_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_33_renamed_554 "slave_fifo32/sloe_33") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_30_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_32_renamed_555 "slave_fifo32/sloe_32") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_29_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_31_renamed_556 "slave_fifo32/sloe_31") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_28_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_30_renamed_557 "slave_fifo32/sloe_30") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_27_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_29_renamed_558 "slave_fifo32/sloe_29") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_26_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_28_renamed_559 "slave_fifo32/sloe_28") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_25_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_27_renamed_560 "slave_fifo32/sloe_27") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_24_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_26_renamed_561 "slave_fifo32/sloe_26") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_23_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_25_renamed_562 "slave_fifo32/sloe_25") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_22_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_24_renamed_563 "slave_fifo32/sloe_24") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_21_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_23_renamed_564 "slave_fifo32/sloe_23") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_20_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_22_renamed_565 "slave_fifo32/sloe_22") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_19_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_21_renamed_566 "slave_fifo32/sloe_21") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_18_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_20_renamed_567 "slave_fifo32/sloe_20") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_17_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_19_renamed_568 "slave_fifo32/sloe_19") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_16_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_18_renamed_569 "slave_fifo32/sloe_18") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_15_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_17_renamed_570 "slave_fifo32/sloe_17") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_14_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_16_renamed_571 "slave_fifo32/sloe_16") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_13_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_15_renamed_572 "slave_fifo32/sloe_15") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_12_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_14_renamed_573 "slave_fifo32/sloe_14") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_11_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_13_renamed_574 "slave_fifo32/sloe_13") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_10_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_12_renamed_575 "slave_fifo32/sloe_12") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_9_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_11_renamed_576 "slave_fifo32/sloe_11") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_8_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_10_renamed_577 "slave_fifo32/sloe_10") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_7_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_9_renamed_578 "slave_fifo32/sloe_9") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_6_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_8_renamed_579 "slave_fifo32/sloe_8") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_5_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_7_renamed_580 "slave_fifo32/sloe_7") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_4_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_6_renamed_581 "slave_fifo32/sloe_6") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_3_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_5_renamed_582 "slave_fifo32/sloe_5") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_2_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_4_renamed_583 "slave_fifo32/sloe_4") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_1_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_3_renamed_584 "slave_fifo32/sloe_3") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance GPIF_D_0_IOBUF + (viewRef view_1 (cellRef IOBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename slave_fifo32_sloe_2_renamed_585 "slave_fifo32/sloe_2") + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0") + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property IOB (string "true") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17") + (viewRef view_1 (cellRef RAMB8BWER (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "13:INPUT:ADDRAWRADDR<12:0>") (owner "Xilinx")) + (property BUS_INFO (string "13:INPUT:ADDRBRDADDR<12:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:DOPADOP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:OUTPUT:DOPBDOP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:DIPBDIP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:DIPADIP<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:WEAWEL<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:WEBWEU<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:OUTPUT:DOADO<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:INPUT:DIBDI<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:INPUT:DIADI<15:0>") (owner "Xilinx")) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>") (owner "Xilinx")) + (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_08 (string 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(property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_19 (string 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"Xilinx")) + (property DOA_REG (integer 0) (owner "Xilinx")) + (property DOB_REG (integer 0) (owner "Xilinx")) + (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx")) + (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx")) + (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_A (string "00000") (owner "Xilinx")) + (property INIT_B (string "00000") (owner "Xilinx")) + (property RAM_MODE (string "TDP") (owner "Xilinx")) + (property RST_PRIORITY_A (string "CE") (owner "Xilinx")) + (property RST_PRIORITY_B (string "CE") (owner "Xilinx")) + (property RSTTYPE (string "SYNC") (owner "Xilinx")) + (property SRVAL_A (string "00000") (owner "Xilinx")) + (property SRVAL_B (string "00000") (owner "Xilinx")) + (property INIT_FILE (string "NONE") (owner "Xilinx")) + (property SIM_COLLISION_CHECK (string "ALL") (owner "Xilinx")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16") + (viewRef view_1 (cellRef RAMB16BWER (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "14:INPUT:ADDRA<13:0>") (owner "Xilinx")) + (property BUS_INFO (string "14:INPUT:ADDRB<13:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:DIPA<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:DOPA<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:DIPB<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:DOPB<3:0>") (owner "Xilinx")) + (property BUS_INFO (string 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(property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INIT_38 (string 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(owner "Xilinx")) + (property DATA_WIDTH_A (integer 2) (owner "Xilinx")) + (property DATA_WIDTH_B (integer 2) (owner "Xilinx")) + (property DOA_REG (integer 0) (owner "Xilinx")) + (property DOB_REG (integer 0) (owner "Xilinx")) + (property EN_RSTRAM_A (string "TRUE") (owner "Xilinx")) + (property EN_RSTRAM_B (string "TRUE") (owner "Xilinx")) + (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000") (owner "Xilinx")) + (property INITP_05 (string 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) + ) + (net tx_frame_p_OBUF + (joined + (portRef Q (instanceRef catgen_oddr2_frame)) + (portRef I (instanceRef tx_frame_p_OBUF_renamed_93)) + ) + ) + (net (rename gpif_sync_reset_out "gpif_sync/reset_out") + (joined + (portRef Q (instanceRef gpif_sync_reset_out_renamed_2)) + (portRef S (instanceRef slave_fifo32_slwr_renamed_7)) + (portRef S (instanceRef slave_fifo32_pktend_renamed_6)) + (portRef R (instanceRef slave_fifo32_state_FSM_FFd2_renamed_5)) + (portRef R (instanceRef slave_fifo32_state_FSM_FFd1_renamed_4)) + (portRef R (instanceRef slave_fifo32_fifoadr_0)) + (portRef R (instanceRef slave_fifo32_fifoadr_1)) + (portRef R (instanceRef slave_fifo32_idle_cycles_0)) + (portRef R (instanceRef slave_fifo32_idle_cycles_1)) + (portRef R (instanceRef slave_fifo32_idle_cycles_2)) + (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0)) + (portRef R (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1)) + (portRef R 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(instanceRef f1_ram_Mram_ram18)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram20)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram20)) + (portRef RSTA (instanceRef f1_ram_Mram_ram20)) + (portRef RSTB (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram20)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram16)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram16)) + (portRef RSTA (instanceRef f1_ram_Mram_ram16)) + (portRef RSTB (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram16)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram15)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram15)) + (portRef RSTA (instanceRef f1_ram_Mram_ram15)) + (portRef RSTB (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram15)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram17)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram17)) + (portRef RSTA (instanceRef f1_ram_Mram_ram17)) + (portRef RSTB (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram17)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram14)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram14)) + (portRef RSTA (instanceRef f1_ram_Mram_ram14)) + (portRef RSTB (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram14)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram13)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram13)) + (portRef RSTA (instanceRef f1_ram_Mram_ram13)) + (portRef RSTB (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram13)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram12)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram12)) + (portRef RSTA (instanceRef f1_ram_Mram_ram12)) + (portRef RSTB (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram12)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram11)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram11)) + (portRef RSTA (instanceRef f1_ram_Mram_ram11)) + (portRef RSTB (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram11)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram9)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram9)) + (portRef RSTA (instanceRef f1_ram_Mram_ram9)) + (portRef RSTB (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram9)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram8)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram8)) + (portRef RSTA (instanceRef f1_ram_Mram_ram8)) + (portRef RSTB (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram8)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram10)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram10)) + (portRef RSTA (instanceRef f1_ram_Mram_ram10)) + (portRef RSTB (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram10)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram6)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram6)) + (portRef RSTA (instanceRef f1_ram_Mram_ram6)) + (portRef RSTB (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram6)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram5)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram5)) + (portRef RSTA (instanceRef f1_ram_Mram_ram5)) + (portRef RSTB (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram5)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram7)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram7)) + (portRef RSTA (instanceRef f1_ram_Mram_ram7)) + (portRef RSTB (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram7)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram3)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram3)) + (portRef RSTA (instanceRef f1_ram_Mram_ram3)) + (portRef RSTB (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram3)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram2)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram2)) + (portRef RSTA (instanceRef f1_ram_Mram_ram2)) + (portRef RSTB (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram2)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram4)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram4)) + (portRef RSTA (instanceRef f1_ram_Mram_ram4)) + (portRef RSTB (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram4)) + (portRef REGCEA (instanceRef f1_ram_Mram_ram1)) + (portRef REGCEB (instanceRef f1_ram_Mram_ram1)) + (portRef RSTA (instanceRef f1_ram_Mram_ram1)) + (portRef RSTB (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 3) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 2) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 1) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEB 0) (instanceRef f1_ram_Mram_ram1)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram33)) + (portRef REGCEBREGCE (instanceRef f0_ram_Mram_ram33)) + (portRef RSTA (instanceRef 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f0_ram_Mram_ram27)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram27)) + (portRef RSTA (instanceRef f0_ram_Mram_ram27)) + (portRef RSTB (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram27)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram29)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram29)) + (portRef RSTA (instanceRef f0_ram_Mram_ram29)) + (portRef RSTB (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram29)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram25)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram25)) + (portRef RSTA (instanceRef f0_ram_Mram_ram25)) + (portRef RSTB (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram25)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram24)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram24)) + (portRef RSTA (instanceRef f0_ram_Mram_ram24)) + (portRef RSTB (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram24)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram26)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram26)) + (portRef RSTA (instanceRef f0_ram_Mram_ram26)) + (portRef RSTB (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram26)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram22)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram22)) + (portRef RSTA (instanceRef f0_ram_Mram_ram22)) + (portRef RSTB (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram22)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram21)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram21)) + (portRef RSTA (instanceRef f0_ram_Mram_ram21)) + (portRef RSTB (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram21)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram23)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram23)) + (portRef RSTA (instanceRef f0_ram_Mram_ram23)) + (portRef RSTB (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram23)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram19)) + (portRef REGCEB (instanceRef f0_ram_Mram_ram19)) + (portRef RSTA (instanceRef f0_ram_Mram_ram19)) + (portRef RSTB (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEB 0) (instanceRef f0_ram_Mram_ram19)) + (portRef REGCEA (instanceRef f0_ram_Mram_ram18)) + (portRef REGCEB (instanceRef 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f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_37_ "tx_tdata<37>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_36_ "tx_tdata<36>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_35_ "tx_tdata<35>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_34_ "tx_tdata<34>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_33_ "tx_tdata<33>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram15)) + ) + ) + (net (rename tx_tdata_28_ "tx_tdata<28>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram15)) + ) + ) + (net (rename tx_tdata_27_ "tx_tdata<27>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram14)) + ) + ) + (net (rename tx_tdata_26_ "tx_tdata<26>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram14)) + ) + ) + (net (rename tx_tdata_25_ "tx_tdata<25>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram13)) + ) + ) + (net (rename tx_tdata_24_ "tx_tdata<24>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram11)) + ) + ) + (net (rename tx_tdata_19_ "tx_tdata<19>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram10)) + ) + ) + (net (rename tx_tdata_18_ "tx_tdata<18>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram10)) + ) + ) + (net (rename tx_tdata_17_ "tx_tdata<17>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_16_ "tx_tdata<16>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_15_ "tx_tdata<15>") + (joined + (portRef Q (instanceRef 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f1_ram_Mram_ram6)) + ) + ) + (net (rename tx_tdata_10_ "tx_tdata<10>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram6)) + ) + ) + (net (rename tx_tdata_9_ "tx_tdata<9>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram5)) + ) + ) + (net (rename tx_tdata_8_ "tx_tdata<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram5)) + ) + ) + (net (rename tx_tdata_7_ "tx_tdata<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram4)) + ) + ) + (net (rename tx_tdata_6_ "tx_tdata<6>") + (joined + (portRef Q (instanceRef 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) + ) + (net (rename tx_tdata_1_ "tx_tdata<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portRef (member DIA 30) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename tx_tdata_0_ "tx_tdata<0>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portRef (member DIA 31) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename ctrl_tdata_63_ "ctrl_tdata<63>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_62_ "ctrl_tdata<62>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_61_ "ctrl_tdata<61>") + (joined + (portRef Q (instanceRef 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(member DIA 30) (instanceRef f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_56_ "ctrl_tdata<56>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_55_ "ctrl_tdata<55>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_54_ "ctrl_tdata<54>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portRef (member DIA 31) (instanceRef f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_53_ "ctrl_tdata<53>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portRef (member DIA 30) (instanceRef f0_ram_Mram_ram27)) + ) + ) + (net (rename ctrl_tdata_52_ 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(portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") + (joined + (portRef O (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef CI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef CI (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_renamed_53)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full92") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121211") + (joined + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214_renamed_55)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114_renamed_58)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217_renamed_428)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212_renamed_54)) + (portRef I3 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") + (joined + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14__)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12__)) + (portRef CI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5__)) + (portRef LI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1__)) + (portRef LI (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") + (joined + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv") + (joined + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0__)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_renamed_25)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portRef (member ADDRB 0) (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB_renamed_336)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt_renamed_250)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portRef I1 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr<6>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213_renamed_430)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112_renamed_501)) + (portRef (member ADDRB 2) (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<13>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13__)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1_renamed_471)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<12>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12__)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1_renamed_470)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<11>") + (joined + (portRef O (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<4>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4__)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<3>") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3__)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT<2>") + (joined + (portRef O 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<5>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_renamed_60)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_renamed_61)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I3 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I3 (instanceRef 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(instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portRef I2 (instanceRef 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I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I2 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I1 (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<2>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12_renamed_63)) + (portRef I0 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portRef I2 (instanceRef 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I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") + (joined + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2__)) + (portRef I0 (instanceRef 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(net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int") + (joined + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set_renamed_422)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4_renamed_488)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portRef I5 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") + (joined + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set_renamed_421)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot_renamed_511)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2_renamed_415)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<7>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<6>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<5>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<4>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<3>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<2>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<1>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT<0>") + (joined + (portRef D (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") + (joined + (portRef O (instanceRef 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+ (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") + (joined + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portRef I5 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>") + (joined + (portRef O + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3__ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>") + (joined + (portRef O + (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<0>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<1>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<2>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<3>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<4>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<5>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<6>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<7>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<8>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<9>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<10>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<11>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<12>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<13>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<14>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32<15>") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_renamed_28)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14__)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15__)) + (portRef I (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_renamed_27)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11_renamed_62)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_3__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_2__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_1__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_0__)) + (portRef CI (instanceRef f1_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef S (instanceRef f1_Mcompar_becoming_full_cy_0__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_11__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_11__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_10__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_9__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_0__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_rd_addr_xor_1__)) + ) + ) + (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut<0>") + (joined + (portRef S (instanceRef f1_Mcount_rd_addr_cy_0__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_0__)) + (portRef O (instanceRef f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_11__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_11__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_10__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_9__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>") + (joined + (portRef O (instanceRef f1_Mcount_wr_addr_cy_0__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f1_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut<0>") + (joined + (portRef S (instanceRef f1_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef f1_Mcount_wr_addr_xor_0__)) + (portRef O (instanceRef f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + (portRef CI (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef S (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut<12>") + (joined + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_12__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut<11>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_11__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_11__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_11__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_11__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut<10>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_10__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_10__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_9_ "f1/Msub_dont_write_past_me_lut<9>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_9__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_9__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_8_ "f1/Msub_dont_write_past_me_lut<8>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_8__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_8__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_7_ "f1/Msub_dont_write_past_me_lut<7>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_7__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_7__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_6_ "f1/Msub_dont_write_past_me_lut<6>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_6__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_6__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_5_ "f1/Msub_dont_write_past_me_lut<5>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_5__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_5__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_4_ "f1/Msub_dont_write_past_me_lut<4>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_4__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_4__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_3_ "f1/Msub_dont_write_past_me_lut<3>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_3__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_3__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_2_ "f1/Msub_dont_write_past_me_lut<2>") + (joined + (portRef S (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef LI (instanceRef f1_Msub_dont_write_past_me_xor_2__)) + (portRef O (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_2__)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>") + (joined + (portRef O (instanceRef f1_Msub_dont_write_past_me_cy_0__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f1_Msub_dont_write_past_me_xor_1__)) + ) + ) + (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") + (joined + (portRef Q (instanceRef f1_read_state_FSM_FFd2_renamed_30)) + (portRef I0 (instanceRef f1__n0161_inv1_lut1_renamed_508)) + (portRef I2 (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef I3 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I5 (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In") + (joined + (portRef D (instanceRef f1_read_state_FSM_FFd2_renamed_30)) + (portRef O (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_read_state_FSM_FFd1_In1 "f1/read_state_FSM_FFd1-In1") + (joined + (portRef D (instanceRef f1_read_state_FSM_FFd1_renamed_29)) + (portRef O (instanceRef f1_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_12)) + (portRef Q (instanceRef f1_Result_12_2_FRB_renamed_349)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_xor_12__rt_renamed_253)) + ) + ) + (net (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_11)) + (portRef Q (instanceRef f1_Result_11_2_FRB_renamed_348)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_11__rt_renamed_207)) + ) + ) + (net (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_10)) + (portRef Q (instanceRef f1_Result_10_2_FRB_renamed_347)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_10__rt_renamed_208)) + ) + ) + (net (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_9)) + (portRef Q (instanceRef f1_Result_9_2_FRB_renamed_346)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_9__rt_renamed_209)) + ) + ) + (net (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_8)) + (portRef Q (instanceRef f1_Result_8_2_FRB_renamed_345)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_8__rt_renamed_210)) + ) + ) + (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_7)) + (portRef Q (instanceRef f1_Result_7_2_FRB_renamed_344)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_7__rt_renamed_211)) + ) + ) + (net (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_6)) + (portRef Q (instanceRef f1_Result_6_2_FRB_renamed_343)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_6__rt_renamed_212)) + ) + ) + (net (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_5)) + (portRef Q (instanceRef f1_Result_5_2_FRB_renamed_342)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_5__rt_renamed_213)) + ) + ) + (net (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_4)) + (portRef Q (instanceRef f1_Result_4_2_FRB_renamed_341)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_4__rt_renamed_214)) + ) + ) + (net (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_3)) + (portRef Q (instanceRef f1_Result_3_2_FRB_renamed_340)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_3__rt_renamed_215)) + ) + ) + (net (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_2)) + (portRef Q (instanceRef f1_Result_2_2_FRB_renamed_339)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_2__rt_renamed_216)) + ) + ) + (net (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_1)) + (portRef Q (instanceRef f1_Result_1_2_FRB_renamed_338)) + (portRef I0 (instanceRef f1_Mcount_wr_addr_cy_1__rt_renamed_217)) + ) + ) + (net (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") + (joined + (portRef D (instanceRef f1_wr_addr_0)) + (portRef Q (instanceRef f1_Result_0_2_FRB_renamed_337)) + (portRef I (instanceRef f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_12)) + (portRef Q (instanceRef f1_Result_12_1_FRB_renamed_362)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_xor_12__rt_renamed_252)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_11)) + (portRef Q (instanceRef f1_Result_11_1_FRB_renamed_361)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_11__rt_renamed_196)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_10)) + (portRef Q (instanceRef f1_Result_10_1_FRB_renamed_360)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_10__rt_renamed_197)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_9)) + (portRef Q (instanceRef f1_Result_9_1_FRB_renamed_359)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_9__rt_renamed_198)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_8)) + (portRef Q (instanceRef f1_Result_8_1_FRB_renamed_358)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_8__rt_renamed_199)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_7)) + (portRef Q (instanceRef f1_Result_7_1_FRB_renamed_357)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_7__rt_renamed_200)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_6)) + (portRef Q (instanceRef f1_Result_6_1_FRB_renamed_356)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_5)) + (portRef Q (instanceRef f1_Result_5_1_FRB_renamed_355)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_4)) + (portRef Q (instanceRef f1_Result_4_1_FRB_renamed_354)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_4__rt_renamed_203)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_3)) + (portRef Q (instanceRef f1_Result_3_1_FRB_renamed_353)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_3__rt_renamed_204)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_2)) + (portRef Q (instanceRef f1_Result_2_1_FRB_renamed_352)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_2__rt_renamed_205)) + (portRef I (instanceRef f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_1)) + (portRef Q (instanceRef f1_Result_1_1_FRB_renamed_351)) + (portRef I0 (instanceRef f1_Mcount_rd_addr_cy_1__rt_renamed_206)) + (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_1__rt_renamed_218)) + ) + ) + (net (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") + (joined + (portRef D (instanceRef f1_rd_addr_0)) + (portRef Q (instanceRef f1_Result_0_1_FRB_renamed_350)) + (portRef I0 (instanceRef f1_Msub_dont_write_past_me_cy_0__rt_renamed_219)) + (portRef I (instanceRef f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f1__n0161_inv "f1/_n0161_inv") + (joined + (portRef CE (instanceRef f1_rd_addr_1)) + (portRef CE (instanceRef f1_rd_addr_2)) + (portRef CE (instanceRef f1_rd_addr_3)) + (portRef CE (instanceRef f1_rd_addr_4)) + (portRef CE (instanceRef f1_rd_addr_5)) + (portRef CE (instanceRef f1_rd_addr_6)) + (portRef CE (instanceRef f1_rd_addr_7)) + (portRef CE (instanceRef f1_rd_addr_8)) + (portRef CE (instanceRef f1_rd_addr_9)) + (portRef CE (instanceRef f1_rd_addr_10)) + (portRef CE (instanceRef f1_rd_addr_11)) + (portRef CE (instanceRef f1_rd_addr_12)) + (portRef CE (instanceRef f1_rd_addr_0)) + (portRef CE (instanceRef f1_Result_0_1_FRB_renamed_350)) + (portRef CE (instanceRef f1_Result_1_1_FRB_renamed_351)) + (portRef CE (instanceRef f1_Result_2_1_FRB_renamed_352)) + (portRef CE (instanceRef f1_Result_3_1_FRB_renamed_353)) + (portRef CE (instanceRef f1_Result_4_1_FRB_renamed_354)) + (portRef CE (instanceRef f1_Result_5_1_FRB_renamed_355)) + (portRef CE (instanceRef f1_Result_6_1_FRB_renamed_356)) + (portRef CE (instanceRef f1_Result_7_1_FRB_renamed_357)) + (portRef CE (instanceRef f1_Result_8_1_FRB_renamed_358)) + (portRef CE (instanceRef f1_Result_9_1_FRB_renamed_359)) + (portRef CE (instanceRef f1_Result_10_1_FRB_renamed_360)) + (portRef CE (instanceRef f1_Result_11_1_FRB_renamed_361)) + (portRef CE (instanceRef f1_Result_12_1_FRB_renamed_362)) + (portRef CE (instanceRef f1_dont_write_past_me_0__FRB_renamed_363)) + (portRef CE (instanceRef f1_dont_write_past_me_1__FRB_renamed_364)) + (portRef CE (instanceRef f1_dont_write_past_me_2__FRB_renamed_365)) + (portRef CE (instanceRef f1_dont_write_past_me_3__FRB_renamed_366)) + (portRef CE (instanceRef f1_dont_write_past_me_4__FRB_renamed_367)) + (portRef CE (instanceRef f1_dont_write_past_me_5__FRB_renamed_368)) + (portRef CE (instanceRef f1_dont_write_past_me_6__FRB_renamed_369)) + (portRef CE (instanceRef f1_dont_write_past_me_7__FRB_renamed_370)) + (portRef CE (instanceRef f1_dont_write_past_me_8__FRB_renamed_371)) + (portRef CE (instanceRef f1_dont_write_past_me_9__FRB_renamed_372)) + (portRef CE (instanceRef f1_dont_write_past_me_10__FRB_renamed_373)) + (portRef CE (instanceRef f1_dont_write_past_me_11__FRB_renamed_374)) + (portRef CE (instanceRef f1_dont_write_past_me_12__FRB_renamed_375)) + (portRef O (instanceRef f1__n0161_inv1_cy1)) + ) + ) + (net (rename f1_becoming_full "f1/becoming_full") + (joined + (portRef O (instanceRef f1_Mcompar_becoming_full_cy_4__)) + (portRef I1 (instanceRef f1_full_reg_glue_set_renamed_537)) + ) + ) + (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o") + (joined + (portRef O (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + (portRef CI (instanceRef f1__n0161_inv1_cy)) + (portRef I2 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_0__FRB_renamed_363)) + ) + ) + (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_1__FRB_renamed_364)) + ) + ) + (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f1_dont_write_past_me_2__FRB_renamed_365)) + ) + ) + (net (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_3__FRB_renamed_366)) + ) + ) + (net (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_4__FRB_renamed_367)) + ) + ) + (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f1_dont_write_past_me_5__FRB_renamed_368)) + ) + ) + (net (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_6__FRB_renamed_369)) + ) + ) + (net (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_7__FRB_renamed_370)) + ) + ) + (net (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f1_dont_write_past_me_8__FRB_renamed_371)) + ) + ) + (net (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_9__FRB_renamed_372)) + ) + ) + (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") + (joined + (portRef I3 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_10__FRB_renamed_373)) + ) + ) + (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") + (joined + (portRef I5 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f1_dont_write_past_me_11__FRB_renamed_374)) + ) + ) + (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") + (joined + (portRef I1 (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef Q (instanceRef f1_dont_write_past_me_12__FRB_renamed_375)) + ) + ) + (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o") + (joined + (portRef O (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef ENBRDEN (instanceRef f1_ram_Mram_ram33)) + (portRef ENB (instanceRef f1_ram_Mram_ram31)) + (portRef ENB (instanceRef f1_ram_Mram_ram30)) + (portRef ENB (instanceRef f1_ram_Mram_ram32)) + (portRef ENB (instanceRef f1_ram_Mram_ram28)) + (portRef ENB (instanceRef f1_ram_Mram_ram27)) + (portRef ENB (instanceRef f1_ram_Mram_ram29)) + (portRef ENB (instanceRef f1_ram_Mram_ram25)) + (portRef ENB (instanceRef f1_ram_Mram_ram24)) + (portRef ENB (instanceRef f1_ram_Mram_ram26)) + (portRef ENB (instanceRef f1_ram_Mram_ram22)) + (portRef ENB (instanceRef f1_ram_Mram_ram21)) + (portRef ENB (instanceRef f1_ram_Mram_ram23)) + (portRef ENB (instanceRef f1_ram_Mram_ram19)) + (portRef ENB (instanceRef f1_ram_Mram_ram18)) + (portRef ENB (instanceRef f1_ram_Mram_ram20)) + (portRef ENB (instanceRef f1_ram_Mram_ram16)) + (portRef ENB (instanceRef f1_ram_Mram_ram15)) + (portRef ENB (instanceRef f1_ram_Mram_ram17)) + (portRef ENB (instanceRef f1_ram_Mram_ram14)) + (portRef ENB (instanceRef f1_ram_Mram_ram13)) + (portRef ENB (instanceRef f1_ram_Mram_ram12)) + (portRef ENB (instanceRef f1_ram_Mram_ram11)) + (portRef ENB (instanceRef f1_ram_Mram_ram9)) + (portRef ENB (instanceRef f1_ram_Mram_ram8)) + (portRef ENB (instanceRef f1_ram_Mram_ram10)) + (portRef ENB (instanceRef f1_ram_Mram_ram6)) + (portRef ENB (instanceRef f1_ram_Mram_ram5)) + (portRef ENB (instanceRef f1_ram_Mram_ram7)) + (portRef ENB (instanceRef f1_ram_Mram_ram3)) + (portRef ENB (instanceRef f1_ram_Mram_ram2)) + (portRef ENB (instanceRef f1_ram_Mram_ram4)) + (portRef ENB (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_write "f1/write") + (joined + (portRef CE (instanceRef f1_wr_addr_1)) + (portRef CE (instanceRef f1_wr_addr_2)) + (portRef CE (instanceRef f1_wr_addr_3)) + (portRef CE (instanceRef f1_wr_addr_4)) + (portRef CE (instanceRef f1_wr_addr_5)) + (portRef CE (instanceRef f1_wr_addr_6)) + (portRef CE (instanceRef f1_wr_addr_7)) + (portRef CE (instanceRef f1_wr_addr_8)) + (portRef CE (instanceRef f1_wr_addr_9)) + (portRef CE (instanceRef f1_wr_addr_10)) + (portRef CE (instanceRef f1_wr_addr_11)) + (portRef CE (instanceRef f1_wr_addr_12)) + (portRef CE (instanceRef f1_wr_addr_0)) + (portRef O (instanceRef f1_write11)) + (portRef CE (instanceRef f1_Result_0_2_FRB_renamed_337)) + (portRef CE (instanceRef f1_Result_1_2_FRB_renamed_338)) + (portRef CE (instanceRef f1_Result_2_2_FRB_renamed_339)) + (portRef CE (instanceRef f1_Result_3_2_FRB_renamed_340)) + (portRef CE (instanceRef f1_Result_4_2_FRB_renamed_341)) + (portRef CE (instanceRef f1_Result_5_2_FRB_renamed_342)) + (portRef CE (instanceRef f1_Result_6_2_FRB_renamed_343)) + (portRef CE (instanceRef f1_Result_7_2_FRB_renamed_344)) + (portRef CE (instanceRef f1_Result_8_2_FRB_renamed_345)) + (portRef CE (instanceRef f1_Result_9_2_FRB_renamed_346)) + (portRef CE (instanceRef f1_Result_10_2_FRB_renamed_347)) + (portRef CE (instanceRef f1_Result_11_2_FRB_renamed_348)) + (portRef CE (instanceRef f1_Result_12_2_FRB_renamed_349)) + (portRef (member WEAWEL 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member WEAWEL 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member WEA 2) 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(instanceRef f1_ram_Mram_ram3)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member WEA 3) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 2) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 1) (instanceRef f1_ram_Mram_ram1)) + (portRef (member WEA 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_0_ "f1/wr_addr<0>") + (joined + (portRef Q (instanceRef f1_wr_addr_0)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I0 (instanceRef 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f1_ram_Mram_ram4)) + (portRef (member ADDRA 12) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_1_ "f1/wr_addr<1>") + (joined + (portRef Q (instanceRef f1_wr_addr_1)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 11) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 11) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 11) (instanceRef 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(portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 9) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_4_ "f1/wr_addr<4>") + (joined + (portRef Q (instanceRef f1_wr_addr_4)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 8) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 8) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_5_ "f1/wr_addr<5>") + (joined + (portRef Q (instanceRef f1_wr_addr_5)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 7) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 7) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_6_ "f1/wr_addr<6>") + (joined + (portRef Q (instanceRef f1_wr_addr_6)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 6) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 6) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_7_ "f1/wr_addr<7>") + (joined + (portRef Q (instanceRef f1_wr_addr_7)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 5) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 5) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_8_ "f1/wr_addr<8>") + (joined + (portRef Q (instanceRef f1_wr_addr_8)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 4) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 4) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_9_ "f1/wr_addr<9>") + (joined + (portRef Q (instanceRef f1_wr_addr_9)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 3) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 3) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_10_ "f1/wr_addr<10>") + (joined + (portRef Q (instanceRef f1_wr_addr_10)) + (portRef I3 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I2 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 2) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 2) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_11_ "f1/wr_addr<11>") + (joined + (portRef Q (instanceRef f1_wr_addr_11)) + (portRef I5 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I4 (instanceRef f1_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 1) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_12_ "f1/wr_addr<12>") + (joined + (portRef Q (instanceRef f1_wr_addr_12)) + (portRef I1 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef I0 (instanceRef f1_Mcompar_becoming_full_lut_4__)) + (portRef (member ADDRAWRADDR 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRA 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_0_ "f1/rd_addr<0>") + (joined + (portRef Q (instanceRef f1_rd_addr_0)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 12) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 12) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_1_ "f1/rd_addr<1>") + (joined + (portRef Q (instanceRef f1_rd_addr_1)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 11) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 11) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_2_ "f1/rd_addr<2>") + (joined + (portRef Q (instanceRef f1_rd_addr_2)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 10) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 10) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_3_ "f1/rd_addr<3>") + (joined + (portRef Q (instanceRef f1_rd_addr_3)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 9) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 9) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_4_ "f1/rd_addr<4>") + (joined + (portRef Q (instanceRef f1_rd_addr_4)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 8) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 8) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_5_ "f1/rd_addr<5>") + (joined + (portRef Q (instanceRef f1_rd_addr_5)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 7) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 7) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_6_ "f1/rd_addr<6>") + (joined + (portRef Q (instanceRef f1_rd_addr_6)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 6) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 6) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_7_ "f1/rd_addr<7>") + (joined + (portRef Q (instanceRef f1_rd_addr_7)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 5) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 5) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_8_ "f1/rd_addr<8>") + (joined + (portRef Q (instanceRef f1_rd_addr_8)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 4) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 4) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_9_ "f1/rd_addr<9>") + (joined + (portRef Q (instanceRef f1_rd_addr_9)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 3) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 3) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_10_ "f1/rd_addr<10>") + (joined + (portRef Q (instanceRef f1_rd_addr_10)) + (portRef I2 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 2) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 2) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_11_ "f1/rd_addr<11>") + (joined + (portRef Q (instanceRef f1_rd_addr_11)) + (portRef I4 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 1) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 1) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_rd_addr_12_ "f1/rd_addr<12>") + (joined + (portRef Q (instanceRef f1_rd_addr_12)) + (portRef I0 (instanceRef f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef (member ADDRBRDADDR 0) (instanceRef f1_ram_Mram_ram33)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram31)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram30)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram32)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram28)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram27)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram29)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram25)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram24)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram26)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram22)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram21)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram23)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram19)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram18)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram20)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram16)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram15)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram17)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram14)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram13)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram12)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram11)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram9)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram8)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram10)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram6)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram5)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram7)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram3)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram2)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram4)) + (portRef (member ADDRB 0) (instanceRef f1_ram_Mram_ram1)) + ) + ) + (net (rename f1_full_reg "f1/full_reg") + (joined + (portRef I1 (instanceRef f1_write11)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portRef Q (instanceRef f1_full_reg_renamed_116)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_renamed_417)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set_renamed_419)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portRef I4 (instanceRef f1_read_state_FSM_FFd2_In1)) + (portRef I4 (instanceRef f1_full_reg_glue_set_renamed_537)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_renamed_39)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") + (joined + (portRef Q (instanceRef f1_read_state_FSM_FFd1_renamed_29)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portRef I1 (instanceRef f1__n0161_inv1_lut_renamed_507)) + (portRef I1 (instanceRef f1__n0161_inv1_lut1_renamed_508)) + (portRef I0 (instanceRef f1_GND_14_o_read_OR_37_o1)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portRef I0 (instanceRef f1_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_renamed_525)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_renamed_530)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_renamed_535)) + (portRef I0 (instanceRef f1_read_state_FSM_FFd2_In1)) + (portRef I3 (instanceRef f1_full_reg_glue_set_renamed_537)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_3__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_4__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_2__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_3__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_1__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_2__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_0__)) + (portRef CI (instanceRef f0_Mcompar_becoming_full_cy_1__)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef S (instanceRef f0_Mcompar_becoming_full_cy_0__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_11__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_11__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_10__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_9__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>") + (joined + (portRef O (instanceRef f0_Mcount_rd_addr_cy_0__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_rd_addr_xor_1__)) + ) + ) + (net (rename f0_Mcount_rd_addr_lut_0_ "f0/Mcount_rd_addr_lut<0>") + (joined + (portRef S (instanceRef f0_Mcount_rd_addr_cy_0__)) + (portRef LI (instanceRef f0_Mcount_rd_addr_xor_0__)) + (portRef O (instanceRef f0_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_10_ "f0/Mcount_wr_addr_cy<10>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_11__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_11__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_10__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_10__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_9__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_9__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_8__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_8__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_7__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_7__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_6__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_6__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_5__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_4__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_3__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_2__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>") + (joined + (portRef O (instanceRef f0_Mcount_wr_addr_cy_0__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_cy_1__)) + (portRef CI (instanceRef f0_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut<0>") + (joined + (portRef S (instanceRef f0_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef f0_Mcount_wr_addr_xor_0__)) + (portRef O (instanceRef f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + (portRef CI (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1__)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef S (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut<12>") + (joined + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_12__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut<11>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_11__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_11__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_11__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_11__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut<10>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_10__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_10__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_10__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut<9>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_9__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_9__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_9__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut<8>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_8__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_8__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_8__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut<7>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_7__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_7__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_7__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut<6>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_6__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_6__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_6__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut<5>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_5__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_5__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_5__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut<4>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_4__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_4__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_4__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut<3>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_3__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_3__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_3__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut<2>") + (joined + (portRef S (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef LI (instanceRef f0_Msub_dont_write_past_me_xor_2__)) + (portRef O (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_2__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_2__)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>") + (joined + (portRef O (instanceRef f0_Msub_dont_write_past_me_cy_0__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_cy_1__)) + (portRef CI (instanceRef f0_Msub_dont_write_past_me_xor_1__)) + ) + ) + (net (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2") + (joined + (portRef Q (instanceRef f0_read_state_FSM_FFd2_renamed_32)) + (portRef I0 (instanceRef f0__n0161_inv1_lut1_renamed_510)) + (portRef I2 (instanceRef f0_GND_14_o_read_OR_37_o1)) + (portRef I3 (instanceRef f0_read_state_FSM_FFd1_In111)) + (portRef I5 (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_read_state_FSM_FFd2_In "f0/read_state_FSM_FFd2-In") + (joined + (portRef D (instanceRef f0_read_state_FSM_FFd2_renamed_32)) + (portRef O (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_read_state_FSM_FFd1_In1 "f0/read_state_FSM_FFd1-In1") + (joined + (portRef D (instanceRef f0_read_state_FSM_FFd1_renamed_31)) + (portRef O (instanceRef f0_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_12)) + (portRef Q (instanceRef f0_Result_12_2_FRB_renamed_388)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_xor_12__rt_renamed_255)) + ) + ) + (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_11)) + (portRef Q (instanceRef f0_Result_11_2_FRB_renamed_387)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_11__rt_renamed_231)) + ) + ) + (net (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_10)) + (portRef Q (instanceRef f0_Result_10_2_FRB_renamed_386)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_10__rt_renamed_232)) + ) + ) + (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_9)) + (portRef Q (instanceRef f0_Result_9_2_FRB_renamed_385)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_9__rt_renamed_233)) + ) + ) + (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_8)) + (portRef Q (instanceRef f0_Result_8_2_FRB_renamed_384)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_8__rt_renamed_234)) + ) + ) + (net (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_7)) + (portRef Q (instanceRef f0_Result_7_2_FRB_renamed_383)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_7__rt_renamed_235)) + ) + ) + (net (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_6)) + (portRef Q (instanceRef f0_Result_6_2_FRB_renamed_382)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_6__rt_renamed_236)) + ) + ) + (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_5)) + (portRef Q (instanceRef f0_Result_5_2_FRB_renamed_381)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_5__rt_renamed_237)) + ) + ) + (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_4)) + (portRef Q (instanceRef f0_Result_4_2_FRB_renamed_380)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_4__rt_renamed_238)) + ) + ) + (net (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_3)) + (portRef Q (instanceRef f0_Result_3_2_FRB_renamed_379)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_3__rt_renamed_239)) + ) + ) + (net (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_2)) + (portRef Q (instanceRef f0_Result_2_2_FRB_renamed_378)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_2__rt_renamed_240)) + ) + ) + (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_1)) + (portRef Q (instanceRef f0_Result_1_2_FRB_renamed_377)) + (portRef I0 (instanceRef f0_Mcount_wr_addr_cy_1__rt_renamed_241)) + ) + ) + (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") + (joined + (portRef D (instanceRef f0_wr_addr_0)) + (portRef Q (instanceRef f0_Result_0_2_FRB_renamed_376)) + (portRef I (instanceRef f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_12)) + (portRef Q (instanceRef f0_Result_12_1_FRB_renamed_401)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_xor_12__rt_renamed_254)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_11)) + (portRef Q (instanceRef f0_Result_11_1_FRB_renamed_400)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_11__rt_renamed_220)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_10)) + (portRef Q (instanceRef f0_Result_10_1_FRB_renamed_399)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_10__rt_renamed_221)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_9)) + (portRef Q (instanceRef f0_Result_9_1_FRB_renamed_398)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_9__rt_renamed_222)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_8)) + (portRef Q (instanceRef f0_Result_8_1_FRB_renamed_397)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_8__rt_renamed_223)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_7)) + (portRef Q (instanceRef f0_Result_7_1_FRB_renamed_396)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_7__rt_renamed_224)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_6)) + (portRef Q (instanceRef f0_Result_6_1_FRB_renamed_395)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_6__rt_renamed_225)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_5)) + (portRef Q (instanceRef f0_Result_5_1_FRB_renamed_394)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_5__rt_renamed_226)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_4)) + (portRef Q (instanceRef f0_Result_4_1_FRB_renamed_393)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_4__rt_renamed_227)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_3)) + (portRef Q (instanceRef f0_Result_3_1_FRB_renamed_392)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_3__rt_renamed_228)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_2)) + (portRef Q (instanceRef f0_Result_2_1_FRB_renamed_391)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_2__rt_renamed_229)) + (portRef I (instanceRef f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_1)) + (portRef Q (instanceRef f0_Result_1_1_FRB_renamed_390)) + (portRef I0 (instanceRef f0_Mcount_rd_addr_cy_1__rt_renamed_230)) + (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_1__rt_renamed_242)) + ) + ) + (net (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") + (joined + (portRef D (instanceRef f0_rd_addr_0)) + (portRef Q (instanceRef f0_Result_0_1_FRB_renamed_389)) + (portRef I0 (instanceRef f0_Msub_dont_write_past_me_cy_0__rt_renamed_243)) + (portRef I (instanceRef f0_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename f0__n0161_inv "f0/_n0161_inv") + (joined + (portRef CE (instanceRef f0_rd_addr_1)) + (portRef CE (instanceRef f0_rd_addr_2)) + (portRef CE (instanceRef f0_rd_addr_3)) + (portRef CE (instanceRef f0_rd_addr_4)) + (portRef CE (instanceRef f0_rd_addr_5)) + (portRef CE (instanceRef f0_rd_addr_6)) + (portRef CE (instanceRef f0_rd_addr_7)) + (portRef CE (instanceRef f0_rd_addr_8)) + (portRef CE (instanceRef f0_rd_addr_9)) + (portRef CE (instanceRef f0_rd_addr_10)) + (portRef CE (instanceRef f0_rd_addr_11)) + (portRef CE (instanceRef f0_rd_addr_12)) + (portRef CE (instanceRef f0_rd_addr_0)) + (portRef CE (instanceRef f0_Result_0_1_FRB_renamed_389)) + (portRef CE (instanceRef f0_Result_1_1_FRB_renamed_390)) + (portRef CE (instanceRef f0_Result_2_1_FRB_renamed_391)) + (portRef CE (instanceRef f0_Result_3_1_FRB_renamed_392)) + (portRef CE (instanceRef f0_Result_4_1_FRB_renamed_393)) + (portRef CE (instanceRef f0_Result_5_1_FRB_renamed_394)) + (portRef CE (instanceRef f0_Result_6_1_FRB_renamed_395)) + (portRef CE (instanceRef f0_Result_7_1_FRB_renamed_396)) + (portRef CE (instanceRef f0_Result_8_1_FRB_renamed_397)) + (portRef CE (instanceRef f0_Result_9_1_FRB_renamed_398)) + (portRef CE (instanceRef f0_Result_10_1_FRB_renamed_399)) + (portRef CE (instanceRef f0_Result_11_1_FRB_renamed_400)) + (portRef CE (instanceRef f0_Result_12_1_FRB_renamed_401)) + (portRef CE (instanceRef f0_dont_write_past_me_0__FRB_renamed_402)) + (portRef CE (instanceRef f0_dont_write_past_me_1__FRB_renamed_403)) + (portRef CE (instanceRef f0_dont_write_past_me_2__FRB_renamed_404)) + (portRef CE (instanceRef f0_dont_write_past_me_3__FRB_renamed_405)) + (portRef CE (instanceRef f0_dont_write_past_me_4__FRB_renamed_406)) + (portRef CE (instanceRef f0_dont_write_past_me_5__FRB_renamed_407)) + (portRef CE (instanceRef f0_dont_write_past_me_6__FRB_renamed_408)) + (portRef CE (instanceRef f0_dont_write_past_me_7__FRB_renamed_409)) + (portRef CE (instanceRef f0_dont_write_past_me_8__FRB_renamed_410)) + (portRef CE (instanceRef f0_dont_write_past_me_9__FRB_renamed_411)) + (portRef CE (instanceRef f0_dont_write_past_me_10__FRB_renamed_412)) + (portRef CE (instanceRef f0_dont_write_past_me_11__FRB_renamed_413)) + (portRef CE (instanceRef f0_dont_write_past_me_12__FRB_renamed_414)) + (portRef O (instanceRef f0__n0161_inv1_cy1)) + ) + ) + (net (rename f0_becoming_full "f0/becoming_full") + (joined + (portRef O (instanceRef f0_Mcompar_becoming_full_cy_4__)) + (portRef I1 (instanceRef f0_full_reg_glue_set_renamed_538)) + ) + ) + (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o "f0/rd_addr[12]_wr_addr[12]_equal_11_o") + (joined + (portRef O (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__)) + (portRef CI (instanceRef f0__n0161_inv1_cy)) + (portRef I2 (instanceRef f0_read_state_FSM_FFd1_In111)) + (portRef I1 (instanceRef f0_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_0__FRB_renamed_402)) + ) + ) + (net (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_1__FRB_renamed_403)) + ) + ) + (net (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef Q (instanceRef f0_dont_write_past_me_2__FRB_renamed_404)) + ) + ) + (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_3__FRB_renamed_405)) + ) + ) + (net (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_4__FRB_renamed_406)) + ) + ) + (net (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef Q (instanceRef f0_dont_write_past_me_5__FRB_renamed_407)) + ) + ) + (net (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_6__FRB_renamed_408)) + ) + ) + (net (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_7__FRB_renamed_409)) + ) + ) + (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef Q (instanceRef f0_dont_write_past_me_8__FRB_renamed_410)) + ) + ) + (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_9__FRB_renamed_411)) + ) + ) + (net (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") + (joined + (portRef I3 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_10__FRB_renamed_412)) + ) + ) + (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") + (joined + (portRef I5 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef Q (instanceRef f0_dont_write_past_me_11__FRB_renamed_413)) + ) + ) + (net (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") + (joined + (portRef I1 (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef Q (instanceRef f0_dont_write_past_me_12__FRB_renamed_414)) + ) + ) + (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o") + (joined + (portRef O (instanceRef f0_GND_14_o_read_OR_37_o1)) + (portRef ENBRDEN (instanceRef f0_ram_Mram_ram33)) + (portRef ENB (instanceRef f0_ram_Mram_ram31)) + (portRef ENB (instanceRef f0_ram_Mram_ram30)) + (portRef ENB (instanceRef f0_ram_Mram_ram32)) + (portRef ENB (instanceRef f0_ram_Mram_ram28)) + (portRef ENB (instanceRef f0_ram_Mram_ram27)) + (portRef ENB (instanceRef f0_ram_Mram_ram29)) + (portRef ENB (instanceRef f0_ram_Mram_ram25)) + (portRef ENB (instanceRef f0_ram_Mram_ram24)) + (portRef ENB (instanceRef f0_ram_Mram_ram26)) + (portRef ENB (instanceRef f0_ram_Mram_ram22)) + (portRef ENB (instanceRef f0_ram_Mram_ram21)) + (portRef ENB (instanceRef f0_ram_Mram_ram23)) + (portRef ENB (instanceRef f0_ram_Mram_ram19)) + (portRef ENB (instanceRef f0_ram_Mram_ram18)) + (portRef ENB (instanceRef f0_ram_Mram_ram20)) + (portRef ENB (instanceRef f0_ram_Mram_ram16)) + (portRef ENB (instanceRef f0_ram_Mram_ram15)) + (portRef ENB (instanceRef f0_ram_Mram_ram17)) + (portRef ENB (instanceRef f0_ram_Mram_ram14)) + (portRef ENB (instanceRef f0_ram_Mram_ram13)) + (portRef ENB (instanceRef f0_ram_Mram_ram12)) + (portRef ENB (instanceRef f0_ram_Mram_ram11)) + (portRef ENB (instanceRef f0_ram_Mram_ram9)) + (portRef ENB (instanceRef f0_ram_Mram_ram8)) + (portRef ENB (instanceRef f0_ram_Mram_ram10)) + (portRef ENB (instanceRef f0_ram_Mram_ram6)) + (portRef ENB (instanceRef f0_ram_Mram_ram5)) + (portRef ENB (instanceRef f0_ram_Mram_ram7)) + (portRef ENB (instanceRef f0_ram_Mram_ram3)) + (portRef ENB (instanceRef f0_ram_Mram_ram2)) + (portRef ENB (instanceRef f0_ram_Mram_ram4)) + (portRef ENB (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_write "f0/write") + (joined + (portRef CE (instanceRef f0_wr_addr_1)) + (portRef CE (instanceRef f0_wr_addr_2)) + (portRef CE (instanceRef f0_wr_addr_3)) + (portRef CE (instanceRef f0_wr_addr_4)) + (portRef CE (instanceRef f0_wr_addr_5)) + (portRef CE (instanceRef f0_wr_addr_6)) + (portRef CE (instanceRef f0_wr_addr_7)) + (portRef CE (instanceRef f0_wr_addr_8)) + (portRef CE (instanceRef f0_wr_addr_9)) + (portRef CE (instanceRef f0_wr_addr_10)) + (portRef CE (instanceRef f0_wr_addr_11)) + (portRef CE (instanceRef f0_wr_addr_12)) + (portRef CE (instanceRef f0_wr_addr_0)) + (portRef O (instanceRef f0_write11)) + (portRef CE (instanceRef f0_Result_0_2_FRB_renamed_376)) + (portRef CE (instanceRef f0_Result_1_2_FRB_renamed_377)) + (portRef CE (instanceRef f0_Result_2_2_FRB_renamed_378)) + (portRef CE (instanceRef f0_Result_3_2_FRB_renamed_379)) + (portRef CE (instanceRef f0_Result_4_2_FRB_renamed_380)) + (portRef CE (instanceRef f0_Result_5_2_FRB_renamed_381)) + (portRef CE (instanceRef f0_Result_6_2_FRB_renamed_382)) + (portRef CE (instanceRef f0_Result_7_2_FRB_renamed_383)) + (portRef CE (instanceRef f0_Result_8_2_FRB_renamed_384)) + (portRef CE (instanceRef f0_Result_9_2_FRB_renamed_385)) + (portRef CE (instanceRef f0_Result_10_2_FRB_renamed_386)) + (portRef CE (instanceRef f0_Result_11_2_FRB_renamed_387)) + (portRef CE (instanceRef f0_Result_12_2_FRB_renamed_388)) + (portRef (member WEAWEL 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member WEAWEL 0) (instanceRef f0_ram_Mram_ram33)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram31)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram30)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram32)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram28)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram27)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram29)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram25)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram24)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram26)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram22)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram21)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram23)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram19)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram18)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram20)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram16)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram15)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram17)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram14)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram13)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram12)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram11)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram9)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram8)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram10)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram6)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram5)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram7)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram3)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram2)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram4)) + (portRef (member WEA 3) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 2) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 1) (instanceRef f0_ram_Mram_ram1)) + (portRef (member WEA 0) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_0_ "f0/wr_addr<0>") + (joined + (portRef Q (instanceRef f0_wr_addr_0)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 12) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 12) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_1_ "f0/wr_addr<1>") + (joined + (portRef Q (instanceRef f0_wr_addr_1)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 11) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 11) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_2_ "f0/wr_addr<2>") + (joined + (portRef Q (instanceRef f0_wr_addr_2)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_0__)) + (portRef (member ADDRAWRADDR 10) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 10) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_3_ "f0/wr_addr<3>") + (joined + (portRef Q (instanceRef f0_wr_addr_3)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 9) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 9) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_4_ "f0/wr_addr<4>") + (joined + (portRef Q (instanceRef f0_wr_addr_4)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 8) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 8) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_5_ "f0/wr_addr<5>") + (joined + (portRef Q (instanceRef f0_wr_addr_5)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_1__)) + (portRef (member ADDRAWRADDR 7) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 7) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_6_ "f0/wr_addr<6>") + (joined + (portRef Q (instanceRef f0_wr_addr_6)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 6) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 6) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_7_ "f0/wr_addr<7>") + (joined + (portRef Q (instanceRef f0_wr_addr_7)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 5) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 5) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_8_ "f0/wr_addr<8>") + (joined + (portRef Q (instanceRef f0_wr_addr_8)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_2__)) + (portRef (member ADDRAWRADDR 4) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 4) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_9_ "f0/wr_addr<9>") + (joined + (portRef Q (instanceRef f0_wr_addr_9)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 3) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 3) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_10_ "f0/wr_addr<10>") + (joined + (portRef Q (instanceRef f0_wr_addr_10)) + (portRef I3 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I2 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 2) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 2) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_11_ "f0/wr_addr<11>") + (joined + (portRef Q (instanceRef f0_wr_addr_11)) + (portRef I5 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef I4 (instanceRef f0_Mcompar_becoming_full_lut_3__)) + (portRef (member ADDRAWRADDR 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 1) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_12_ "f0/wr_addr<12>") + (joined + (portRef Q (instanceRef f0_wr_addr_12)) + (portRef I1 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4__)) + (portRef I0 (instanceRef f0_Mcompar_becoming_full_lut_4__)) + (portRef (member ADDRAWRADDR 0) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRA 0) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_0_ "f0/rd_addr<0>") + (joined + (portRef Q (instanceRef f0_rd_addr_0)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 12) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 12) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_1_ "f0/rd_addr<1>") + (joined + (portRef Q (instanceRef f0_rd_addr_1)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 11) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 11) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_2_ "f0/rd_addr<2>") + (joined + (portRef Q (instanceRef f0_rd_addr_2)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0__)) + (portRef (member ADDRBRDADDR 10) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 10) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_3_ "f0/rd_addr<3>") + (joined + (portRef Q (instanceRef f0_rd_addr_3)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 9) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 9) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_4_ "f0/rd_addr<4>") + (joined + (portRef Q (instanceRef f0_rd_addr_4)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 8) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 8) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_5_ "f0/rd_addr<5>") + (joined + (portRef Q (instanceRef f0_rd_addr_5)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1__)) + (portRef (member ADDRBRDADDR 7) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 7) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_6_ "f0/rd_addr<6>") + (joined + (portRef Q (instanceRef f0_rd_addr_6)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 6) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 6) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_7_ "f0/rd_addr<7>") + (joined + (portRef Q (instanceRef f0_rd_addr_7)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 5) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 5) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_8_ "f0/rd_addr<8>") + (joined + (portRef Q (instanceRef f0_rd_addr_8)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2__)) + (portRef (member ADDRBRDADDR 4) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 4) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_9_ "f0/rd_addr<9>") + (joined + (portRef Q (instanceRef f0_rd_addr_9)) + (portRef I0 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 3) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 3) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_10_ "f0/rd_addr<10>") + (joined + (portRef Q (instanceRef f0_rd_addr_10)) + (portRef I2 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 2) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram25)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram24)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram26)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram22)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram21)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram23)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram19)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram18)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram20)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram16)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram15)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram17)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram14)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram13)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram12)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram11)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram9)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram8)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram10)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram6)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram5)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram7)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram3)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram2)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram4)) + (portRef (member ADDRB 2) (instanceRef f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_11_ "f0/rd_addr<11>") + (joined + (portRef Q (instanceRef f0_rd_addr_11)) + (portRef I4 (instanceRef f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3__)) + (portRef (member ADDRBRDADDR 1) (instanceRef f0_ram_Mram_ram33)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram31)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram30)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram32)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram28)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram27)) + (portRef (member ADDRB 1) (instanceRef f0_ram_Mram_ram29)) + (portRef (member ADDRB 1) (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") + (joined + (portRef O + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211_renamed_416)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N88 + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portRef I2 + (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In3") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31_renamed_65)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32_renamed_66)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net N90 + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portRef I1 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In1") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11_renamed_67)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12_renamed_68)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") + (joined + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portRef rd_en (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In1") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net cat_miso + (joined + (portRef cat_miso) + (portRef I (instanceRef cat_miso_IBUF_renamed_69)) + ) + ) + (net fx3_ce + (joined + (portRef fx3_ce) + (portRef I (instanceRef fx3_ce_IBUF_renamed_70)) + ) + ) + (net fx3_mosi + (joined + (portRef fx3_mosi) + (portRef I (instanceRef fx3_mosi_IBUF_renamed_71)) + ) + ) + (net fx3_sclk + (joined + (portRef fx3_sclk) + (portRef I (instanceRef fx3_sclk_IBUF_renamed_72)) + ) + ) + (net GPIF_CTL4 + (joined + (portRef GPIF_CTL4) + (portRef I (instanceRef GPIF_CTL4_IBUF_renamed_73)) + ) + ) + (net GPIF_CTL5 + (joined + (portRef GPIF_CTL5) + (portRef I (instanceRef GPIF_CTL5_IBUF_renamed_74)) + ) + ) + (net GPIF_CTL9 + (joined + (portRef GPIF_CTL9) + (portRef I (instanceRef GPIF_CTL9_IBUF_renamed_75)) + ) + ) + (net N96 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_31)) + (portRef O (instanceRef GPIF_D_31_IOBUF)) + ) + ) + (net N97 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_30)) + (portRef O (instanceRef GPIF_D_30_IOBUF)) + ) + ) + (net N98 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_29)) + (portRef O (instanceRef GPIF_D_29_IOBUF)) + ) + ) + (net N99 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_28)) + (portRef O (instanceRef GPIF_D_28_IOBUF)) + ) + ) + (net N100 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_27)) + (portRef O (instanceRef GPIF_D_27_IOBUF)) + ) + ) + (net N101 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_26)) + (portRef O (instanceRef GPIF_D_26_IOBUF)) + ) + ) + (net N102 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_25)) + (portRef O (instanceRef GPIF_D_25_IOBUF)) + ) + ) + (net N103 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_24)) + (portRef O (instanceRef GPIF_D_24_IOBUF)) + ) + ) + (net N104 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_23)) + (portRef O (instanceRef GPIF_D_23_IOBUF)) + ) + ) + (net N105 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_22)) + (portRef O (instanceRef GPIF_D_22_IOBUF)) + ) + ) + (net N106 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_21)) + (portRef O (instanceRef GPIF_D_21_IOBUF)) + ) + ) + (net N107 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_20)) + (portRef O (instanceRef GPIF_D_20_IOBUF)) + ) + ) + (net N108 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_19)) + (portRef O (instanceRef GPIF_D_19_IOBUF)) + ) + ) + (net N109 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_18)) + (portRef O (instanceRef GPIF_D_18_IOBUF)) + ) + ) + (net N110 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_17)) + (portRef O (instanceRef GPIF_D_17_IOBUF)) + ) + ) + (net N111 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_16)) + (portRef O (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net N112 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_15)) + (portRef O (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net N113 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_14)) + (portRef O (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net N114 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_13)) + (portRef O (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net N115 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_12)) + (portRef O (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net N116 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_11)) + (portRef O (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net N117 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_10)) + (portRef O (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net N118 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_9)) + (portRef O (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net N119 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_8)) + (portRef O (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net N120 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_7)) + (portRef O (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net N121 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_6)) + (portRef O (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net N122 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_5)) + (portRef O (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net N123 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_4)) + (portRef O (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net N124 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_3)) + (portRef O (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net N125 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_2)) + (portRef O (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net N126 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_1)) + (portRef O (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net N127 + (joined + (portRef D (instanceRef slave_fifo32_gpif_data_in_0)) + (portRef O (instanceRef GPIF_D_0_IOBUF)) + ) + ) + (net (rename codec_ctrl_in_3_ "codec_ctrl_in<3>") + (joined + (portRef (member codec_ctrl_in 0)) + (portRef O (instanceRef codec_ctrl_in_3_OBUF)) + ) + ) + (net (rename codec_ctrl_in_2_ "codec_ctrl_in<2>") + (joined + (portRef (member codec_ctrl_in 1)) + (portRef O (instanceRef codec_ctrl_in_2_OBUF)) + ) + ) + (net (rename codec_ctrl_in_1_ "codec_ctrl_in<1>") + (joined + (portRef (member codec_ctrl_in 2)) + (portRef O (instanceRef codec_ctrl_in_1_OBUF)) + ) + ) + (net (rename codec_ctrl_in_0_ "codec_ctrl_in<0>") + (joined + (portRef (member codec_ctrl_in 3)) + (portRef O (instanceRef codec_ctrl_in_0_OBUF)) + ) + ) + (net (rename tx_codec_d_11_ "tx_codec_d<11>") + (joined + (portRef (member tx_codec_d 0)) + (portRef O (instanceRef tx_codec_d_11_OBUF_renamed_76)) + ) + ) + (net (rename tx_codec_d_10_ "tx_codec_d<10>") + (joined + (portRef (member tx_codec_d 1)) + (portRef O (instanceRef tx_codec_d_10_OBUF_renamed_77)) + ) + ) + (net (rename tx_codec_d_9_ "tx_codec_d<9>") + (joined + (portRef (member tx_codec_d 2)) + (portRef O (instanceRef tx_codec_d_9_OBUF_renamed_78)) + ) + ) + (net (rename tx_codec_d_8_ "tx_codec_d<8>") + (joined + (portRef (member tx_codec_d 3)) + (portRef O (instanceRef tx_codec_d_8_OBUF_renamed_79)) + ) + ) + (net (rename tx_codec_d_7_ "tx_codec_d<7>") + (joined + (portRef (member tx_codec_d 4)) + (portRef O (instanceRef tx_codec_d_7_OBUF_renamed_80)) + ) + ) + (net (rename tx_codec_d_6_ "tx_codec_d<6>") + (joined + (portRef (member tx_codec_d 5)) + (portRef O (instanceRef tx_codec_d_6_OBUF_renamed_81)) + ) + ) + (net (rename tx_codec_d_5_ "tx_codec_d<5>") + (joined + (portRef (member tx_codec_d 6)) + (portRef O (instanceRef tx_codec_d_5_OBUF_renamed_82)) + ) + ) + (net (rename tx_codec_d_4_ "tx_codec_d<4>") + (joined + (portRef (member tx_codec_d 7)) + (portRef O (instanceRef tx_codec_d_4_OBUF_renamed_83)) + ) + ) + (net (rename tx_codec_d_3_ "tx_codec_d<3>") + (joined + (portRef (member tx_codec_d 8)) + (portRef O (instanceRef tx_codec_d_3_OBUF_renamed_84)) + ) + ) + (net (rename tx_codec_d_2_ "tx_codec_d<2>") + (joined + (portRef (member tx_codec_d 9)) + (portRef O (instanceRef tx_codec_d_2_OBUF_renamed_85)) + ) + ) + (net (rename tx_codec_d_1_ "tx_codec_d<1>") + (joined + (portRef (member tx_codec_d 10)) + (portRef O (instanceRef tx_codec_d_1_OBUF_renamed_86)) + ) + ) + (net (rename tx_codec_d_0_ "tx_codec_d<0>") + (joined + (portRef (member tx_codec_d 11)) + (portRef O (instanceRef tx_codec_d_0_OBUF_renamed_87)) + ) + ) + (net (rename debug_31_ "debug<31>") + (joined + (portRef (member debug 0)) + (portRef O (instanceRef debug_31_OBUF)) + ) + ) + (net (rename debug_30_ "debug<30>") + (joined + (portRef (member debug 1)) + (portRef O (instanceRef debug_30_OBUF)) + ) + ) + (net (rename debug_29_ "debug<29>") + (joined + (portRef (member debug 2)) + (portRef O (instanceRef debug_29_OBUF)) + ) + ) + (net (rename debug_28_ "debug<28>") + (joined + (portRef (member debug 3)) + (portRef O (instanceRef debug_28_OBUF)) + ) + ) + (net (rename debug_27_ "debug<27>") + (joined + (portRef (member debug 4)) + (portRef O (instanceRef debug_27_OBUF)) + ) + ) + (net (rename debug_26_ "debug<26>") + (joined + (portRef (member debug 5)) + (portRef O (instanceRef debug_26_OBUF)) + ) + ) + (net (rename debug_25_ "debug<25>") + (joined + (portRef (member debug 6)) + (portRef O (instanceRef debug_25_OBUF)) + ) + ) + (net (rename debug_24_ "debug<24>") + (joined + (portRef (member debug 7)) + (portRef O (instanceRef debug_24_OBUF)) + ) + ) + (net (rename debug_23_ "debug<23>") + (joined + (portRef (member debug 8)) + (portRef O (instanceRef debug_23_OBUF)) + ) + ) + (net (rename debug_22_ "debug<22>") + (joined + (portRef (member debug 9)) + (portRef O (instanceRef debug_22_OBUF)) + ) + ) + (net (rename debug_21_ "debug<21>") + (joined + (portRef (member debug 10)) + (portRef O (instanceRef debug_21_OBUF)) + ) + ) + (net (rename debug_20_ "debug<20>") + (joined + (portRef (member debug 11)) + (portRef O (instanceRef debug_20_OBUF)) + ) + ) + (net (rename debug_19_ "debug<19>") + (joined + (portRef (member debug 12)) + (portRef O (instanceRef debug_19_OBUF)) + ) + ) + (net (rename debug_18_ "debug<18>") + (joined + (portRef (member debug 13)) + (portRef O (instanceRef debug_18_OBUF)) + ) + ) + (net (rename debug_17_ "debug<17>") + (joined + (portRef (member debug 14)) + (portRef O (instanceRef debug_17_OBUF)) + ) + ) + (net (rename debug_16_ "debug<16>") + (joined + (portRef (member debug 15)) + (portRef O (instanceRef debug_16_OBUF)) + ) + ) + (net (rename debug_15_ "debug<15>") + (joined + (portRef (member debug 16)) + (portRef O (instanceRef debug_15_OBUF)) + ) + ) + (net (rename debug_14_ "debug<14>") + (joined + (portRef (member debug 17)) + (portRef O (instanceRef debug_14_OBUF)) + ) + ) + (net (rename debug_13_ "debug<13>") + (joined + (portRef (member debug 18)) + (portRef O (instanceRef debug_13_OBUF)) + ) + ) + (net (rename debug_12_ "debug<12>") + (joined + (portRef (member debug 19)) + (portRef O (instanceRef debug_12_OBUF)) + ) + ) + (net (rename debug_11_ "debug<11>") + (joined + (portRef (member debug 20)) + (portRef O (instanceRef debug_11_OBUF)) + ) + ) + (net (rename debug_10_ "debug<10>") + (joined + (portRef (member debug 21)) + (portRef O (instanceRef debug_10_OBUF)) + ) + ) + (net (rename debug_9_ "debug<9>") + (joined + (portRef (member debug 22)) + (portRef O (instanceRef debug_9_OBUF)) + ) + ) + (net (rename debug_8_ "debug<8>") + (joined + (portRef (member debug 23)) + (portRef O (instanceRef debug_8_OBUF)) + ) + ) + (net (rename debug_7_ "debug<7>") + (joined + (portRef (member debug 24)) + (portRef O (instanceRef debug_7_OBUF)) + ) + ) + (net (rename debug_6_ "debug<6>") + (joined + (portRef (member debug 25)) + (portRef O (instanceRef debug_6_OBUF)) + ) + ) + (net (rename debug_5_ "debug<5>") + (joined + (portRef (member debug 26)) + (portRef O (instanceRef debug_5_OBUF)) + ) + ) + (net (rename debug_4_ "debug<4>") + (joined + (portRef (member debug 27)) + (portRef O (instanceRef debug_4_OBUF)) + ) + ) + (net (rename debug_3_ "debug<3>") + (joined + (portRef (member debug 28)) + (portRef O (instanceRef debug_3_OBUF)) + ) + ) + (net (rename debug_2_ "debug<2>") + (joined + (portRef (member debug 29)) + (portRef O (instanceRef debug_2_OBUF)) + ) + ) + (net (rename debug_1_ "debug<1>") + (joined + (portRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt_renamed_180)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt_renamed_181)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt_renamed_182)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt_renamed_183)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt_renamed_184)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt_renamed_185)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2__)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt_renamed_190)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt_renamed_191)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt_renamed_192)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt_renamed_193)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt_renamed_194)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1__)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") + (joined + (portRef O (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt_renamed_195)) + (portRef S (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__)) + (portRef LI (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0__)) + ) + ) + (net (rename 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(portRef LI (instanceRef f1_Mcount_rd_addr_xor_8__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_7__rt_renamed_200)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_7__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_7__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6__rt "f1/Mcount_rd_addr_cy<6>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_6__rt_renamed_201)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_6__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_6__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") + (joined + (portRef O (instanceRef f1_Mcount_rd_addr_cy_5__rt_renamed_202)) + (portRef S (instanceRef f1_Mcount_rd_addr_cy_5__)) + (portRef LI (instanceRef f1_Mcount_rd_addr_xor_5__)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") + (joined + (portRef O (instanceRef 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1_renamed_477)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portRef I0 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0_renamed_478)) + (portRef I0 (instanceRef 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_480)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portRef I5 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portRef I4 (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_481)) + (portRef I3 (instanceRef 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2_renamed_486)) + (portRef I2 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") + (joined + (portRef Q (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3_renamed_487)) + (portRef I3 (instanceRef slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") + 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"slave_fifo32/gpif_data_out<17>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_17)) + (portRef I (instanceRef GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_18_renamed_569)) + (portRef T (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out<16>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_16)) + (portRef I (instanceRef GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_17_renamed_570)) + (portRef T (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out<15>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_15)) + (portRef I (instanceRef GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_16_renamed_571)) + (portRef T (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out<14>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_14)) + (portRef I (instanceRef GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_15_renamed_572)) + (portRef T (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out<13>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_13)) + (portRef I (instanceRef GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_14_renamed_573)) + (portRef T (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out<12>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_12)) + (portRef I (instanceRef GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_13_renamed_574)) + (portRef T (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out<11>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_11)) + (portRef I (instanceRef GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_12_renamed_575)) + (portRef T (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out<10>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_10)) + (portRef I (instanceRef GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_11_renamed_576)) + (portRef T (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out<9>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_9)) + (portRef I (instanceRef GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_10_renamed_577)) + (portRef T (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out<8>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_8)) + (portRef I (instanceRef GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_9_renamed_578)) + (portRef T (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out<7>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_7)) + (portRef I (instanceRef GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_8_renamed_579)) + (portRef T (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out<6>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_6)) + (portRef I (instanceRef GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_7_renamed_580)) + (portRef T (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out<5>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_5)) + (portRef I (instanceRef GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_6_renamed_581)) + (portRef T (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out<4>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_4)) + (portRef I (instanceRef GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_5_renamed_582)) + (portRef T (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out<3>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_3)) + (portRef I (instanceRef GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_4_renamed_583)) + (portRef T (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out<2>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_2)) + (portRef I (instanceRef GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_3_renamed_584)) + (portRef T (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out<1>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_1)) + (portRef I (instanceRef GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") + (joined + (portRef Q (instanceRef slave_fifo32_sloe_2_renamed_585)) + (portRef T (instanceRef GPIF_D_0_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_0_ "slave_fifo32/gpif_data_out<0>") + (joined + (portRef Q (instanceRef slave_fifo32_gpif_data_out_0)) + (portRef I (instanceRef GPIF_D_0_IOBUF)) + ) + ) + ) + ) + ) + ) + + (design b200 + (cellRef b200 + (libraryRef b200_lib) + ) + (property PART (string "xc6slx75-3-fgg484") (owner "Xilinx")) + ) +) + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml new file mode 100644 index 000000000..6234dfdc5 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/constrs_1/fileset.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg new file mode 100644 index 000000000..147f3a950 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1.psg @@ -0,0 +1,20 @@ + + + + ISE Defaults, including packing registers in IOs off + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml new file mode 100644 index 000000000..d7d32c943 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml new file mode 100644 index 000000000..4d152cf5b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg new file mode 100644 index 000000000..147f3a950 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg @@ -0,0 +1,20 @@ + + + + ISE Defaults, including packing registers in IOs off + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml new file mode 100644 index 000000000..1ebdc052b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/impl_1/sources.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml new file mode 100644 index 000000000..b8f171cc0 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/runs/runs.xml @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml new file mode 100644 index 000000000..65babe32f --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/sim_1/fileset.xml @@ -0,0 +1,10 @@ + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml new file mode 100644 index 000000000..b0421e4c2 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/sources_1/fileset.xml @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf new file mode 100644 index 000000000..d32729c6c --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/java_command_handlers.wdf @@ -0,0 +1,12 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697466696e64:32:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c657a6f6f6d617265616d6f6465:32:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d666974:31:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:3133:00:00 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d6f7574:3137:00:00 +eof:1108508211 diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc new file mode 100644 index 000000000..9b3420931 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/project.wpc @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml new file mode 100644 index 000000000..4c889614e --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.data/wt/webtalk_pa.xml @@ -0,0 +1,38 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/fpga/usrp3/top/b200/planahead/planahead.ppr b/fpga/usrp3/top/b200/planahead/planahead.ppr new file mode 100644 index 000000000..706cfae4b --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.ppr @@ -0,0 +1,28 @@ + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat new file mode 100644 index 000000000..f95ac9bd2 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.bat @@ -0,0 +1,21 @@ +@echo off + +rem PlanAhead(TM) +rem launch.bat: a PlanAhead-generated ExploreAhead Script +rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. + + +setlocal + +set HD_LDIR=%~dp0 + +rem *** Create Queue Clues +set HD_RUNDIR=%HD_LDIR%\../impl_1 +if exist "%HD_RUNDIR%" echo. > "%HD_RUNDIR%/.ISE.queue.rst" + + +rem *** Launch Runs (one at a time) +set HD_RUNBAT=%HD_LDIR%\../impl_1\runme.bat +if exist "%HD_RUNBAT%" call "%HD_RUNBAT%" %* + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh new file mode 100755 index 000000000..48861c686 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/.jobs/job1.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# launch.sh: a PlanAhead-generated ExploreAhead Script for UNIX +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +HD_LDIR=`dirname "$0"` + +# *** Create Queue Clues +HD_RUNDIR="$HD_LDIR/../impl_1" +if [ -d "$HD_RUNDIR" ] +then +/bin/touch "$HD_RUNDIR/.ISE.queue.rst" +fi + + +# *** Launch Runs (one at a time) +HD_RUNSH="$HD_LDIR/../impl_1/runme.sh" +if [ -f "$HD_RUNSH" ] +then +"$HD_RUNSH" +fi + + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf new file mode 100644 index 000000000..665f5d76c --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/b200.ucf @@ -0,0 +1,317 @@ +## SPI Nets + +NET "cat_ce" LOC = Y1; +NET "cat_ce" IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = V1; +NET "cat_miso" IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = T4; +NET "cat_mosi" IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = P7; +NET "cat_sclk" IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = H20; +NET "fx3_miso" LOC = G20; +NET "fx3_mosi" LOC = AA20; +NET "fx3_sclk" LOC = Y21; + +NET "pll_ce" LOC = W11; +NET "pll_mosi" LOC = AB11; +NET "pll_sclk" LOC = Y12; + +NET "FPGA_RXD0" LOC = AB8; +NET "FPGA_TXD0" LOC = AB7; + +NET "SCL_FPGA" LOC = P21; +NET "SDA_FPGA" LOC = W22; + +## Catalina Controls + +NET "codec_enable" LOC = J6; +NET "codec_enable" IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = P6; +NET "codec_en_agc" IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = Y2; +NET "codec_reset" IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = M3; +NET "codec_sync" IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = M7; +NET "codec_txrx" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in[0]" LOC = E3; +NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[1]" LOC = F2; +NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[2]" LOC = F1; +NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[3]" LOC = E1; +NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out[0]" LOC = D1; +NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[1]" LOC = C1; +NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[2]" LOC = H3; +NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[3]" LOC = F3; +NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[4]" LOC = P1; +NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[5]" LOC = J1; +NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[6]" LOC = B1; +NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[7]" LOC = H2; +NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d[0]" LOC = T2; +NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[0]" DRIVE = 4; +NET "rx_codec_d[1]" LOC = R1; +NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[1]" DRIVE = 4; +NET "rx_codec_d[2]" LOC = V2; +NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[2]" DRIVE = 4; +NET "rx_codec_d[3]" LOC = N1; +NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[3]" DRIVE = 4; +NET "rx_codec_d[4]" LOC = V3; +NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[4]" DRIVE = 4; +NET "rx_codec_d[5]" LOC = T1; +NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[5]" DRIVE = 4; +NET "rx_codec_d[6]" LOC = W1; +NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[6]" DRIVE = 4; +NET "rx_codec_d[7]" LOC = U1; +NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[7]" DRIVE = 4; +NET "rx_codec_d[8]" LOC = W3; +NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[8]" DRIVE = 4; +NET "rx_codec_d[9]" LOC = U3; +NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[9]" DRIVE = 4; +NET "rx_codec_d[10]" LOC = P2; +NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[10]" DRIVE = 4; +NET "rx_codec_d[11]" LOC = R3; +NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[11]" DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d[0]" LOC = M1; +NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[0]" DRIVE = 4; +NET "tx_codec_d[1]" LOC = K1; +NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[1]" DRIVE = 4; +NET "tx_codec_d[2]" LOC = L3; +NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[2]" DRIVE = 4; +NET "tx_codec_d[3]" LOC = K2; +NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[3]" DRIVE = 4; +NET "tx_codec_d[4]" LOC = M4; +NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[4]" DRIVE = 4; +NET "tx_codec_d[5]" LOC = J4; +NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[5]" DRIVE = 4; +NET "tx_codec_d[6]" LOC = L4; +NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[6]" DRIVE = 4; +NET "tx_codec_d[7]" LOC = H1; +NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[7]" DRIVE = 4; +NET "tx_codec_d[8]" LOC = M2; +NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[8]" DRIVE = 4; +NET "tx_codec_d[9]" LOC = G1; +NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[9]" DRIVE = 4; +NET "tx_codec_d[10]" LOC = N3; +NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[10]" DRIVE = 4; +NET "tx_codec_d[11]" LOC = G3; +NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[11]" DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = J3; +NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = K3; +NET "codec_data_clk_p" IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = P3; +NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = K5; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = K4; + +NET "rx_frame_p" LOC = U4; +NET "rx_frame_p" IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = T3; +NET "tx_frame_p" IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug[0]" LOC = C14; +NET "debug[1]" LOC = F15; +NET "debug[2]" LOC = A18; +NET "debug[3]" LOC = A17; +NET "debug[4]" LOC = E14; +NET "debug[5]" LOC = G13; +NET "debug[6]" LOC = D13; +NET "debug[7]" LOC = F13; +NET "debug[8]" LOC = D8; +NET "debug[9]" LOC = A6; +NET "debug[10]" LOC = D7; +NET "debug[11]" LOC = A5; +NET "debug[12]" LOC = B6; +NET "debug[13]" LOC = A3; +NET "debug[14]" LOC = A7; +NET "debug[15]" LOC = A8; +NET "debug[16]" LOC = B18; +NET "debug[17]" LOC = C17; +NET "debug[18]" LOC = H13; +NET "debug[19]" LOC = D12; +NET "debug[20]" LOC = H14; +NET "debug[21]" LOC = C10; +NET "debug[22]" LOC = D10; +NET "debug[23]" LOC = C8; +NET "debug[24]" LOC = D9; +NET "debug[25]" LOC = C5; +NET "debug[26]" LOC = A9; +NET "debug[27]" LOC = B8; +NET "debug[28]" LOC = A4; +NET "debug[29]" LOC = C7; +NET "debug[30]" LOC = C6; +NET "debug[31]" LOC = D6; + +NET "debug_clk[0]" LOC = A12; +NET "debug_clk[1]" LOC = C12; + +## GPIF + +NET "IFCLK" LOC = H21; +NET "FX3_EXTINT" LOC = U20; + +NET "GPIF_CTL0" LOC = V20; +NET "GPIF_CTL1" LOC = T22; +NET "GPIF_CTL2" LOC = R22; +NET "GPIF_CTL3" LOC = U22; +NET "GPIF_CTL4" LOC = P19; +NET "GPIF_CTL5" LOC = N22; +NET "GPIF_CTL6" LOC = T21; +NET "GPIF_CTL7" LOC = V21; +NET "GPIF_CTL8" LOC = K18; +NET "GPIF_CTL9" LOC = R20; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = P22; +NET "GPIF_CTL12" LOC = M20; + +NET "GPIF_D[0]" LOC = T17; +NET "GPIF_D[1]" LOC = U14; +NET "GPIF_D[2]" LOC = U13; +NET "GPIF_D[3]" LOC = AA6; +NET "GPIF_D[4]" LOC = AB6; +NET "GPIF_D[5]" LOC = Y3; +NET "GPIF_D[6]" LOC = AB3; +NET "GPIF_D[7]" LOC = AA4; +NET "GPIF_D[8]" LOC = AA2; +NET "GPIF_D[9]" LOC = AB2; +NET "GPIF_D[10]" LOC = AB19; +NET "GPIF_D[11]" LOC = AA18; +NET "GPIF_D[12]" LOC = AB18; +NET "GPIF_D[13]" LOC = Y13; +NET "GPIF_D[14]" LOC = AA12; +NET "GPIF_D[15]" LOC = AB12; +NET "GPIF_D[16]" LOC = N20; +NET "GPIF_D[17]" LOC = L20; +NET "GPIF_D[18]" LOC = N19; +NET "GPIF_D[19]" LOC = M22; +NET "GPIF_D[20]" LOC = L19; +NET "GPIF_D[21]" LOC = M21; +NET "GPIF_D[22]" LOC = M19; +NET "GPIF_D[23]" LOC = K22; +NET "GPIF_D[24]" LOC = J20; +NET "GPIF_D[25]" LOC = L22; +NET "GPIF_D[26]" LOC = K19; +NET "GPIF_D[27]" LOC = H22; +NET "GPIF_D[28]" LOC = J22; +NET "GPIF_D[29]" LOC = K20; +NET "GPIF_D[30]" LOC = G22; +NET "GPIF_D[31]" LOC = F22; + +## GPS + +NET "gps_lock" LOC = Y17; +NET "gps_out_enable" LOC = V22; +NET "gps_ref_enable" LOC = AB13; +NET "gps_rxd" LOC = AB14; +NET "gps_txd" LOC = W12; +NET "gps_txd_nmea" LOC = AA14; + +## LEDS + +NET "LED_RX1" LOC = C22; +NET "LED_RX2" LOC = L15; +NET "LED_TXRX1_TX" LOC = C20; +NET "LED_TXRX2_RX" LOC = D21; +NET "LED_TXRX1_RX" LOC = K16; +NET "LED_TXRX2_TX" LOC = D22; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = Y15; +NET "pll_lock" LOC = AB10; +NET "AUX_PWR_ON" LOC = AA21; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = AB15; +NET "PPS_IN_EXT" LOC = AB16; +NET "PPS_IN_INT" LOC = AB21; +NET "pps_out" LOC = AB17; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = W4; +NET "SFDX1_TX" LOC = T18; +NET "SFDX2_RX" LOC = F18; +NET "SFDX2_TX" LOC = H17; +NET "SRX1_RX" LOC = Y7; +NET "SRX1_TX" LOC = AA8; +NET "SRX2_RX" LOC = J17; +NET "SRX2_TX" LOC = F19; +NET "tx_bandsel_a" LOC = N16; +NET "tx_bandsel_b" LOC = M16; +NET "tx_enable1" LOC = Y4; +NET "tx_enable2" LOC = R19; +NET "rx_bandsel_a" LOC = T20; +NET "rx_bandsel_b" LOC = U19; +NET "rx_bandsel_c" LOC = P20; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf new file mode 100644 index 000000000..907b97539 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.constrs/timing.ucf @@ -0,0 +1,85 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_D_9_IOBUF" IOB =TRUE; +INST "GPIF_D_8_IOBUF" IOB =TRUE; +INST "GPIF_D_7_IOBUF" IOB =TRUE; +INST "GPIF_D_6_IOBUF" IOB =TRUE; +INST "GPIF_D_5_IOBUF" IOB =TRUE; +INST "GPIF_D_4_IOBUF" IOB =TRUE; +INST "GPIF_D_3_IOBUF" IOB =TRUE; +INST "GPIF_D_31_IOBUF" IOB =TRUE; +INST "GPIF_D_30_IOBUF" IOB =TRUE; +INST "GPIF_D_2_IOBUF" IOB =TRUE; +INST "GPIF_D_29_IOBUF" IOB =TRUE; +INST "GPIF_D_28_IOBUF" IOB =TRUE; +INST "GPIF_D_27_IOBUF" IOB =TRUE; +INST "GPIF_D_26_IOBUF" IOB =TRUE; +INST "GPIF_D_25_IOBUF" IOB =TRUE; +INST "GPIF_D_24_IOBUF" IOB =TRUE; +INST "GPIF_D_23_IOBUF" IOB =TRUE; +INST "GPIF_D_22_IOBUF" IOB =TRUE; +INST "GPIF_D_21_IOBUF" IOB =TRUE; +INST "GPIF_D_20_IOBUF" IOB =TRUE; +INST "GPIF_D_1_IOBUF" IOB =TRUE; +INST "GPIF_CTL0_OBUF" IOB =TRUE; +INST "GPIF_CTL11_OBUF" IOB =TRUE; +INST "GPIF_CTL12_OBUF" IOB =TRUE; +INST "GPIF_CTL1_OBUF" IOB =TRUE; +INST "GPIF_CTL2_OBUF" IOB =TRUE; +INST "GPIF_CTL3_OBUF" IOB =TRUE; +INST "GPIF_CTL4_IBUF" IOB =TRUE; +INST "GPIF_CTL5_IBUF" IOB =TRUE; +INST "GPIF_CTL7_OBUF" IOB =TRUE; +INST "GPIF_CTL9_IBUF" IOB =TRUE; +INST "GPIF_D_0_IOBUF" IOB =TRUE; +INST "GPIF_D_10_IOBUF" IOB =TRUE; +INST "GPIF_D_11_IOBUF" IOB =TRUE; +INST "GPIF_D_12_IOBUF" IOB =TRUE; +INST "GPIF_D_13_IOBUF" IOB =TRUE; +INST "GPIF_D_14_IOBUF" IOB =TRUE; +INST "GPIF_D_15_IOBUF" IOB =TRUE; +INST "GPIF_D_16_IOBUF" IOB =TRUE; +INST "GPIF_D_17_IOBUF" IOB =TRUE; +INST "GPIF_D_18_IOBUF" IOB =TRUE; +INST "GPIF_D_19_IOBUF" IOB =TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D[*]" TNM = "gpif_net_out"; +INST "GPIF_D[*]" TNM = "gpif_net_in"; +INST "GPIF_CTL0" TNM = "gpif_net_out"; +INST "GPIF_CTL1" TNM = "gpif_net_out"; +INST "GPIF_CTL2" TNM = "gpif_net_out"; +INST "GPIF_CTL3" TNM = "gpif_net_out"; +INST "GPIF_CTL4" TNM = "gpif_net_in"; +INST "GPIF_CTL5" TNM = "gpif_net_in"; +INST "GPIF_CTL6" TNM = gpif_net_in; +INST "GPIF_CTL7" TNM = "gpif_net_out"; +INST "GPIF_CTL8" TNM = gpif_net_in; +INST "GPIF_CTL11" TNM = "gpif_net_out"; +INST "GPIF_CTL12" TNM = "gpif_net_out"; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.map.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.ngdbuild.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.par.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.trce.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.begin.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/.xdl.end.rst new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js new file mode 100644 index 000000000..72d04e50d --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.js @@ -0,0 +1,196 @@ +// +// PlanAhead(TM) +// ISEWrap.js: ExploreAhead Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.close(); +} + +function ISEOpenFile( ISEFilename ) { + + var ISEFullPath = ISERunDir + "/" + ISEFilename; + return ISEFileSys.OpenTextFile( ISEFullPath, 8, true ); +} diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh new file mode 100755 index 000000000..4ebc95977 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ISEWrap.sh @@ -0,0 +1,62 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# ISEWrap.sh: ExploreAhead Script for UNIX +# Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf new file mode 100644 index 000000000..6fe23b7b5 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.edf @@ -0,0 +1,51815 @@ +(edif b200 + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2013 01 29 17 25 56) + (program "PlanAhead" (version "14.4")) + (comment "Built on 'Tue Dec 18 05:17:28 MST 2012'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell FDRE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell MUXCY (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port CI (direction INPUT)) + (port DI (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell SRLC32E (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port Q31 (direction OUTPUT)) + (port CE (direction INPUT)) + (port CLK (direction INPUT)) + (port D (direction INPUT)) + (port (array (rename A "A[4:0]") 5) (direction INPUT)) + ) + ) + ) + (cell XORCY (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port CI (direction INPUT)) + (port LI (direction INPUT)) + ) + ) + ) + (cell OBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell FD (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell ODDR2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C0 (direction INPUT)) + (port C1 (direction INPUT)) + (port CE (direction INPUT)) + (port D0 (direction INPUT)) + (port D1 (direction INPUT)) + (port R (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell IOBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port IO (direction INOUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell RAMB16BWER (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLKA (direction INPUT)) + (port CLKB (direction INPUT)) + (port ENA (direction INPUT)) + (port ENB (direction INPUT)) + (port REGCEA (direction INPUT)) + (port REGCEB (direction INPUT)) + (port RSTA (direction INPUT)) + (port RSTB (direction INPUT)) + (port (array (rename DOA "DOA[31:0]") 32) (direction OUTPUT)) + (port (array (rename DOB "DOB[31:0]") 32) (direction OUTPUT)) + (port (array (rename DOPA "DOPA[3:0]") 4) (direction OUTPUT)) + (port (array (rename DOPB "DOPB[3:0]") 4) (direction OUTPUT)) + (port (array (rename ADDRA "ADDRA[13:0]") 14) (direction INPUT)) + (port (array (rename ADDRB "ADDRB[13:0]") 14) (direction INPUT)) + (port (array (rename DIA "DIA[31:0]") 32) (direction INPUT)) + (port (array (rename DIB "DIB[31:0]") 32) (direction INPUT)) + (port (array (rename DIPA "DIPA[3:0]") 4) (direction INPUT)) + (port (array (rename DIPB "DIPB[3:0]") 4) (direction INPUT)) + (port (array (rename WEA "WEA[3:0]") 4) (direction INPUT)) + (port (array (rename WEB "WEB[3:0]") 4) (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell FDSE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell FDR (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell FDE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell IBUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell MUXF7 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell RAMB8BWER (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLKAWRCLK (direction INPUT)) + (port CLKBRDCLK (direction INPUT)) + (port ENAWREN (direction INPUT)) + (port ENBRDEN (direction INPUT)) + (port REGCEA (direction INPUT)) + (port REGCEBREGCE (direction INPUT)) + (port RSTA (direction INPUT)) + (port RSTBRST (direction INPUT)) + (port (array (rename DOADO "DOADO[15:0]") 16) (direction OUTPUT)) + (port (array (rename DOBDO "DOBDO[15:0]") 16) (direction OUTPUT)) + (port (array (rename DOPADOP "DOPADOP[1:0]") 2) (direction OUTPUT)) + (port (array (rename DOPBDOP "DOPBDOP[1:0]") 2) (direction OUTPUT)) + (port (array (rename ADDRAWRADDR "ADDRAWRADDR[12:0]") 13) (direction INPUT)) + (port (array (rename ADDRBRDADDR "ADDRBRDADDR[12:0]") 13) (direction INPUT)) + (port (array (rename DIADI "DIADI[15:0]") 16) (direction INPUT)) + (port (array (rename DIBDI "DIBDI[15:0]") 16) (direction INPUT)) + (port (array (rename DIPADIP "DIPADIP[1:0]") 2) (direction INPUT)) + (port (array (rename DIPBDIP "DIPBDIP[1:0]") 2) (direction INPUT)) + (port (array (rename WEAWEL "WEAWEL[1:0]") 2) (direction INPUT)) + (port (array (rename WEBWEU "WEBWEU[1:0]") 2) (direction INPUT)) + ) + ) + ) + (cell BUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell IBUFGDS (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + (port IB (direction INPUT)) + ) + ) + ) + (cell FDS (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell FDP (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell IBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell DCM_SP (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port CLK0 (direction OUTPUT)) + (port CLK180 (direction OUTPUT)) + (port CLK270 (direction OUTPUT)) + (port CLK2X (direction OUTPUT)) + (port CLK2X180 (direction OUTPUT)) + (port CLK90 (direction OUTPUT)) + (port CLKDV (direction OUTPUT)) + (port CLKFX (direction OUTPUT)) + (port CLKFX180 (direction OUTPUT)) + (port LOCKED (direction OUTPUT)) + (port PSDONE (direction OUTPUT)) + (port CLKFB (direction INPUT)) + (port CLKIN (direction INPUT)) + (port DSSEN (direction INPUT)) + (port PSCLK (direction INPUT)) + (port PSEN (direction INPUT)) + (port PSINCDEC (direction INPUT)) + (port RST (direction INPUT)) + (port (array (rename STATUS "STATUS[7:0]") 8) (direction OUTPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library b200_lib + (edifLevel 0) + (technology (numberDefinition )) + (cell fifo_4k_2clk (celltype GENERIC) + (view view_1 (viewtype NETLIST) + (interface + (port rst (direction INPUT)) + (port wr_clk (direction INPUT)) + (port rd_clk (direction INPUT)) + (port wr_en (direction INPUT)) + (port rd_en (direction INPUT)) + (port full (direction OUTPUT)) + (port empty (direction OUTPUT)) + (port (array (rename din "din[71:0]") 72) (direction INPUT)) + (port (array (rename dout "dout[71:0]") 72) (direction OUTPUT)) + (port (array (rename rd_data_count "rd_data_count[9:0]") 10) (direction OUTPUT)) + (port (array (rename wr_data_count "wr_data_count[9:0]") 10) (direction OUTPUT)) + ) + ) + ) + (cell b200 (celltype GENERIC) + (view view_1 (viewtype NETLIST) + (interface + (port cat_miso (direction INPUT)) + (port fx3_ce (direction INPUT)) + (port fx3_mosi (direction INPUT)) + (port fx3_sclk (direction INPUT)) + (port FPGA_RXD0 (direction INPUT)) + (port FPGA_TXD0 (direction INPUT)) + (port SCL_FPGA (direction INPUT)) + (port SDA_FPGA (direction INPUT)) + (port codec_data_clk_p (direction INPUT)) + (port rx_frame_p (direction INPUT)) + (port cat_clkout_fpga (direction INPUT)) + (port codec_main_clk_p (direction INPUT)) + (port codec_main_clk_n (direction INPUT)) + (port GPIF_CTL4 (direction INPUT)) + (port GPIF_CTL5 (direction INPUT)) + (port GPIF_CTL6 (direction INPUT)) + (port GPIF_CTL8 (direction INPUT)) + (port GPIF_CTL9 (direction INPUT)) + (port gps_lock (direction INPUT)) + (port gps_rxd (direction INPUT)) + (port gps_txd (direction INPUT)) + (port gps_txd_nmea (direction INPUT)) + (port pll_lock (direction INPUT)) + (port FPGA_CFG_CS (direction INPUT)) + (port AUX_PWR_ON (direction INPUT)) + (port PPS_IN_EXT (direction INPUT)) + (port PPS_IN_INT (direction INPUT)) + (port pps_out (direction INPUT)) + (port cat_ce (direction OUTPUT)) + (port cat_mosi (direction OUTPUT)) + (port cat_sclk (direction OUTPUT)) + (port fx3_miso (direction OUTPUT)) + (port pll_ce (direction OUTPUT)) + (port pll_mosi (direction OUTPUT)) + (port pll_sclk (direction OUTPUT)) + (port codec_enable (direction OUTPUT)) + (port codec_en_agc (direction OUTPUT)) + (port codec_reset (direction OUTPUT)) + (port codec_sync (direction OUTPUT)) + (port codec_txrx (direction OUTPUT)) + (port codec_fb_clk_p (direction OUTPUT)) + (port tx_frame_p (direction OUTPUT)) + (port IFCLK (direction OUTPUT)) + (port FX3_EXTINT (direction OUTPUT)) + (port GPIF_CTL0 (direction OUTPUT)) + (port GPIF_CTL1 (direction OUTPUT)) + (port GPIF_CTL2 (direction OUTPUT)) + (port GPIF_CTL3 (direction OUTPUT)) + (port GPIF_CTL7 (direction OUTPUT)) + (port GPIF_CTL11 (direction OUTPUT)) + (port GPIF_CTL12 (direction OUTPUT)) + (port gps_out_enable (direction OUTPUT)) + (port gps_ref_enable (direction OUTPUT)) + (port LED_RX1 (direction OUTPUT)) + (port LED_RX2 (direction OUTPUT)) + (port LED_TXRX1_RX (direction OUTPUT)) + (port LED_TXRX1_TX (direction OUTPUT)) + (port LED_TXRX2_RX (direction OUTPUT)) + (port LED_TXRX2_TX (direction OUTPUT)) + (port ext_ref_enable (direction OUTPUT)) + (port pps_fpga_out_enable (direction OUTPUT)) + (port SFDX1_RX (direction OUTPUT)) + (port SFDX1_TX (direction OUTPUT)) + (port SFDX2_RX (direction OUTPUT)) + (port SFDX2_TX (direction OUTPUT)) + (port SRX1_RX (direction OUTPUT)) + (port SRX1_TX (direction OUTPUT)) + (port SRX2_RX (direction OUTPUT)) + (port SRX2_TX (direction OUTPUT)) + (port tx_bandsel_a (direction OUTPUT)) + (port tx_bandsel_b (direction OUTPUT)) + (port tx_enable1 (direction OUTPUT)) + (port tx_enable2 (direction OUTPUT)) + (port rx_bandsel_a (direction OUTPUT)) + (port rx_bandsel_b (direction OUTPUT)) + (port rx_bandsel_c (direction OUTPUT)) + (port (array (rename codec_ctrl_out "codec_ctrl_out[7:0]") 8) (direction INPUT)) + (port (array (rename rx_codec_d "rx_codec_d[11:0]") 12) (direction INPUT)) + (port (array (rename codec_ctrl_in "codec_ctrl_in[3:0]") 4) (direction OUTPUT)) + (port (array (rename tx_codec_d "tx_codec_d[11:0]") 12) (direction OUTPUT)) + (port (array (rename debug "debug[31:0]") 32) (direction OUTPUT)) + (port (array (rename debug_clk "debug_clk[1:0]") 2) (direction OUTPUT)) + (port (array (rename GPIF_D "GPIF_D[31:0]") 32) (direction INOUT)) + ) + (contents + (instance (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_11_2_FRB "f1/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_2_ "f1/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___111___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_3_ "f1/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___85___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_23_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_18_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "4'h8")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_4_ "f1/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_GND_14_o_read_OR_37_o1 "f1/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1")) + (property INIT (string "8'h72")) + ) + (instance (rename slave_fifo32_debug1_0 "slave_fifo32/debug1_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_10_ "f0/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_1 "slave_fifo32/debug1_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug1_2 "slave_fifo32/debug1_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_3 "slave_fifo32/debug1_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_4 "slave_fifo32/debug1_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_5 "slave_fifo32/debug1_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_11_ "f0/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_6 "slave_fifo32/debug1_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug1_7 "slave_fifo32/debug1_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_8 "slave_fifo32/debug1_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_9 "slave_fifo32/debug1_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_wr_addr_xor_12_ "f0/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___109___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_4__oddr2 "catgen/gen_pins[4].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___108___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hC8")) + ) + (instance (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_1_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_debug2_0 "slave_fifo32/debug2_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___134___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_debug2_1 "slave_fifo32/debug2_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_2 "slave_fifo32/debug2_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_3 "slave_fifo32/debug2_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_4 "slave_fifo32/debug2_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_5 "slave_fifo32/debug2_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_6 "slave_fifo32/debug2_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_7 "slave_fifo32/debug2_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_1_11 "slave_fifo32/Mcount_fifoadr_xor<1>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_debug2_8 "slave_fifo32/debug2_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_9 "slave_fifo32/debug2_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___133___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_sloe_1_rstpot "slave_fifo32/sloe_1_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA2AAAAAAAFFAA")) + ) + (instance debug_19_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_24_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___132___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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(property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + 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(property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string 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(property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_5__INV_0 "f1/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string 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slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string 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(property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string 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(property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___84___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFBFBFBFFFB00FB00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance debug_30_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_25_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_3__FRB "f1/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_EP_READY "slave_fifo32/EP_READY") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_0__rt "f1/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9CCC9CC6CCCCCCC6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")) + (property INIT (string "16'hFFA2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance debug_26_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_31_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h999A999999959999")) + ) + (instance (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_dont_write_past_me_4__FRB "f1/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1")) + (property INIT (string "16'h5400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<6>1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0001FFFF00007FFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1")) + (property INIT (string "16'h0455")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance debug_27_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_20_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_15_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0")) + (property INIT (string "16'hEEEF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_rd_addr_0 "f1/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_1 "f1/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_2 "f1/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_3 "f1/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_4 "f1/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_8__INV_0 "f0/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_rd_addr_5 "f1/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_6 "f1/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_7 "f1/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1")) + (property INIT (string "16'h0455")) + ) + (instance (rename f1_rd_addr_8 "f1/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_9 "f1/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_10__rt "f0/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance SRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_1__rt "f1/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h01FE00FF00FF807F")) + ) + (instance (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_8_2_FRB "f1/Result<8>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance cat_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename f1_Result_12_2_FRB "f1/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_28_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF7FFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance ODDR2_ifclk_dbg (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "NONE")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_0_11 "slave_fifo32/Mcount_idle_cycles_xor<0>11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_10_ "f1/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_6__FRB "f1/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance SRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6__rt "f1/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_2_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___130___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT101")) + (property INIT (string "4'hE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_11_ "f1/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_10_ "f1/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram6") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram8") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___129___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT121")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_0_ "f0/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11__rt "f1/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance debug_29_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_1_ "f0/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___128___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT141")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32__n0223_inv1 "slave_fifo32/_n0223_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1")) + (property INIT (string "8'h82")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_cy_2_ "f0/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___146___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hAC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9CCC9CC6CCCCCCC6")) + ) + (instance (rename slave_fifo32__n0279_inv_SW0 "slave_fifo32/_n0279_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00400000AAEAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___145___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hAC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcount_rd_addr_cy_5_ "f0/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___11___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Mcount_rd_addr_cy_6_ "f0/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_7__FRB "f1/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___144___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd1 "slave_fifo32/slrd1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_slrd2 "slave_fifo32/slrd2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_slrd3 "slave_fifo32/slrd3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_7_ "f0/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___151___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___141___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___170___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/i_tready1")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_rd_addr_cy_8_ "f0/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___143___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_0 "slave_fifo32/gpif_data_out_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_1 "slave_fifo32/gpif_data_out_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_out_2 "slave_fifo32/gpif_data_out_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_9_ "f0/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_3 "slave_fifo32/gpif_data_out_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_4 "slave_fifo32/gpif_data_out_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___140___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_5 "slave_fifo32/gpif_data_out_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0__n0161_inv1_cy1 "f0/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_gpif_data_out_6 "slave_fifo32/gpif_data_out_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_7 "slave_fifo32/gpif_data_out_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT33") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_gpif_data_out_8 "slave_fifo32/gpif_data_out_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0020202008282828")) + ) + (instance (rename slave_fifo32_gpif_data_out_9 "slave_fifo32/gpif_data_out_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___142___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___139___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT51 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT51") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___32___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111_SW0")) + (property INIT (string "16'hF110")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT61") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___136___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___138___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT71 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT71") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT81 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT81") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___137___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_dont_write_past_me_8__FRB "f1/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT91 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT91") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___42___slave_fifo32/Mcount_fifoadr_xor<1>11")) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32__n0230_inv1 "slave_fifo32/_n0230_inv1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hEFFF")) + ) + (instance (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_GND_14_o_read_OR_37_o1 "f0/GND_14_o_read_OR_37_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1")) + (property INIT (string "8'h72")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_1_11 "slave_fifo32/Mcount_idle_cycles_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11")) + (property INIT (string "8'h14")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_full_reg "f1/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___169___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hE4")) + ) + (instance (rename catgen_gen_pins_7__oddr2 "catgen/gen_pins[7].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0004FFFF00040004")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_12__INV_0 "f0/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/clear_dump_OR_154_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_21_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_16_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_8__INV_0 "f1/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA2A22FFAA7F22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA2AAA6A6F7FFA6A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f1_Result_9_2_FRB "f1/Result<9>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3__rt "f0/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h2F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_wr_addr_cy_3__rt "f1/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename f1_rd_addr_10 "f1/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_rd_addr_11 "f1/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_rd_addr_12 "f1/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance LED_TXRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance gps_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_3_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f1_Mcount_wr_addr_cy_0_ "f1/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0C0C0C0C0C0D0C0C")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1_ "f1/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mcount_idle_cycles_xor_2_11 "slave_fifo32/Mcount_idle_cycles_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___23___slave_fifo32/Mcount_idle_cycles_xor<2>11")) + (property INIT (string "16'h1444")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2_ "f1/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_3_ "f1/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_cy_4_ "f1/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0010001000000010")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9090900000900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h99900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0220000000000220")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5_ "f1/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0080000000000080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921")) + (property INIT (string "16'h0440")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFAF8AA0000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFFFF")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6_ "f1/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance FX3_EXTINT_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_0_ "f1/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance codec_data_clk_bufg (viewref netlist (cellref IBUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IBUF_LOW_PWR (boolean (true))) + (property IOSTANDARD (string "DEFAULT")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_1_ "f1/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_2_ "f1/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "8'hE0")) + ) + (instance (rename f0_read_state_FSM_FFd2_In1 "f0/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFDFDFDFFA8A8A8FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_3_ "f1/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0021FFFF00FFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_read_state_FSM_FFd2_In1 "f1/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFDFDFDFFA8A8A8FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename f0__n0161_inv1_lut "f0/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h01")) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h7F2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_9_ "f1/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1 "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h5410")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2A7F7F7FFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFF6FFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___20___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2002000000002002")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8822228C80202084")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_ram_Mram_ram10 "f0/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "32'hFFAEFFFF")) + ) + (instance (rename f0_Mcount_wr_addr_xor_0_ "f0/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_3__INV_0 "f0/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_ram_Mram_ram11 "f0/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000023003300")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram13 "f0/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + 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(viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram16 "f0/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string 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(property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string 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(property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram18 "f0/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string 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(property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string 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(property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string 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(property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string 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(property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string 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(property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram24 "f0/ram/Mram_ram24") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string 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(property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string 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(property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string 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(property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram30 "f0/ram/Mram_ram30") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram25 "f0/ram/Mram_ram25") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram26 "f0/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram31 "f0/ram/Mram_ram31") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_2_ "f0/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram27 "f0/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram32 "f0/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_ram_Mram_ram28 "f0/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram33 "f0/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_ram_Mram_ram29 "f0/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_3_ "f0/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_4_ "f0/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_5_ "f0/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_6_ "f0/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance rx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___47___slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/read1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_wr_addr_xor_7_ "f0/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_xor_8_ "f0/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111")) + (property INIT (string "4'hE")) + ) + (instance (rename f0_Mcount_wr_addr_xor_9_ "f0/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_22_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_17_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance SRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000001FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_ram_Mram_ram10 "f1/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance rx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_ram_Mram_ram11 "f1/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram12 "f1/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_i_tready "slave_fifo32/fifo64_to_gpmc32_tx/i_tready") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_ram_Mram_ram13 "f1/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram14 "f1/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5140514055555140")) + ) + (instance (rename f1_ram_Mram_ram15 "f1/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram20 "f1/ram/Mram_ram20") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string 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(property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram16 "f1/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string 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BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram22 "f1/ram/Mram_ram22") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string 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"f1/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram23 "f1/ram/Mram_ram23") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 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INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram18 "f1/ram/Mram_ram18") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram26 "f1/ram/Mram_ram26") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string 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(property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string 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(property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string 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(property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram27 "f1/ram/Mram_ram27") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string 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(property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string 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(property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string 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(property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram32 "f1/ram/Mram_ram32") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram28 "f1/ram/Mram_ram28") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string 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(property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string 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(property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string 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(property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string 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"256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_ram_Mram_ram33 "f1/ram/Mram_ram33") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename f1_ram_Mram_ram29 "f1/ram/Mram_ram29") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32__n0237_inv1 "slave_fifo32/_n0237_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1__n0161_inv1_cy1 "f1/_n0161_inv1_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_pktend "slave_fifo32/pktend") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance fx3_miso1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f1_Mcount_rd_addr_xor_0_ "f1/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "32'hBF4040BF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_4_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31")) + (property INIT (string "32'hFFFF4B44")) + ) + (instance (rename f1_Mcount_rd_addr_xor_1_ "f1/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE178E1E1E1E1E1E1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance rx_bandsel_c_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_rd_one_rstpot "slave_fifo32/rd_one_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_xor_2_ "f1/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "32'h9AAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_3_ "f1/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA9AAAA6A696A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FFFF0000FEFF")) + ) + (instance (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA2AAAFAAA2AFAFA")) + ) + (instance (rename f1_Mcount_rd_addr_xor_4_ "f1/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h99AA99A6AAAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_rd_addr_xor_5_ "f1/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_xor_6_ "f1/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF0040BFBF4000FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_rd_addr_xor_7_ "f1/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___4___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/_n0227_inv1")) + (property INIT (string "32'hDFDDFFFF")) + ) + (instance LED_RX1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFBEEEA55514440")) + ) + (instance (rename f1_Mcount_rd_addr_xor_8_ "f1/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_0_1_FRB "f0/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In14") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAA2A080808")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFC55FC54FF55FF55")) + ) + (instance (rename f1_Mcount_rd_addr_xor_9_ "f1/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0")) + (property INIT (string "16'hCCC9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFDFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFB")) + ) + (instance (rename catgen_gen_pins_10__oddr2 "catgen/gen_pins[10].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___124___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW0")) + (property INIT (string "4'h6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "4'h8")) + ) + (instance pll_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421")) + (property INIT (string "16'hFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___19___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421")) + (property INIT (string "16'h0111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11")) + (property INIT (string "16'hFFF9")) + ) + (instance LED_RX2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename catgen_gen_pins_2__oddr2 "catgen/gen_pins[2].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA3B8819AA2A8808")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h777FF7FFFFFFFFFF")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1 "slave_fifo32/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2 "slave_fifo32/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8020401008020401")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0 "slave_fifo32/Mcount_fifoadr_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename gen_clks_clkout1_buf "gen_clks/clkout1_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_1__rt "f0/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "4'h8")) + ) + (instance (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_0_1_FRB "f1/Result<0>1_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11_ "f0/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___81___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_3__INV_0 "f1/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___80___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___51___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata341") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___79___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata291")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance tx_enable1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr10_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr10_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata401 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata401") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata411 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___75___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_6__rt "f0/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata421 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata421") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___74___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata371") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___78___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_wr_one "slave_fifo32/wr_one") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata431") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___73___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata381") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___50___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gen_clks_clkin1_buf "gen_clks/clkin1_buf") (viewref netlist (cellref IBUFGDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IOSTANDARD (string "DEFAULT")) + (property IBUF_DELAY_VALUE (string "0")) + (property IBUF_LOW_PWR (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata441 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata441") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___72___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata391") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___77___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata410")) + (property INIT (string "8'hE4")) + ) + (instance LED_TXRX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1")) + (property INIT (string "4'h4")) + ) + (instance GPIF_D_23_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_18_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata501 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata501") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___66___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata451") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___71___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_write11 "f1/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___123___f1/write11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___76___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata510")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata461 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata461") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___70___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata511 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___65___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h9996")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata471 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata471") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___69___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata521 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata521") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___64___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<3>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA9A9A9A9FF0000FF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata481 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata481") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___68___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata531") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___63___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_10_ "f0/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_enable2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata491") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___67___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata541") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___62___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_11_ "f0/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0001000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC9C9C9C900FFFF00")) + ) + (instance (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata601") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___56___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata551") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___61___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_12_ "f0/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata561") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___60___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata611") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___55___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0EE00FF00FF00FF0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata571") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___59___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata621") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___54___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF0000FFFF1000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hF0F0F0F08877EE11")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata581") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___58___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata631") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___53___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata351")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___116___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full921")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata641") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___52___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata361")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata591") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___57___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcount_wr_addr_cy_0_ "f0/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF1110FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance LED_TXRX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_wr_addr_cy_1_ "f0/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_2_ "f0/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename f1__n0161_inv1_lut "f1/_n0161_inv1_lut") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_3_ "f0/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h11101110FFFF1110")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0")) + (property INIT (string "8'hD0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4_ "f0/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_5_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___8___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h00440F44")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5_ "f0/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_12__INV_0 "f1/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6_ "f0/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_7_ "f0/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_8_ "f0/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_9_ "f0/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_6__INV_0 "f0/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h56555656")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11")) + (property INIT (string "8'h54")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Result_1_1_FRB "f0/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "8'hA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8282414141418228")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAB9AAAAAAA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___135___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h7")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1 "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A88820202000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF008C008C008C")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0")) + (property INIT (string "8'hBF")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFF7FFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11_SW1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_0_ "f1/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF55555554")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_1_ "f1/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_wr_addr_cy_4__rt "f1/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_2_ "f1/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_in_0 "slave_fifo32/gpif_data_in_0") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_1 "slave_fifo32/gpif_data_in_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_2 "slave_fifo32/gpif_data_in_2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FFFB0004FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_in_3 "slave_fifo32/gpif_data_in_3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_3_ "f1/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_4 "slave_fifo32/gpif_data_in_4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance ODDR2_ifclk (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "NONE")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_in_5 "slave_fifo32/gpif_data_in_5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___123___f1/write11")) + (property INIT (string "32'hF0FF4044")) + ) + (instance (rename slave_fifo32_gpif_data_in_6 "slave_fifo32/gpif_data_in_6") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_7 "slave_fifo32/gpif_data_in_7") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h350035F0")) + ) + (instance (rename slave_fifo32_gpif_data_in_8 "slave_fifo32/gpif_data_in_8") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA8AAA8AFFCFAA8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h999F999699999990")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_4_ "f1/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_slrd_rstpot_SW0 "slave_fifo32/slrd_rstpot_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4141414141411441")) + ) + (instance (rename slave_fifo32_gpif_data_in_9 "slave_fifo32/gpif_data_in_9") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA08880800008008")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_5_ "f1/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_24_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_19_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_6_ "f1/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_7_ "f1/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1__n0161_inv1_lut1 "f1/_n0161_inv1_lut1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance IFCLK_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_wr_addr_cy_9__rt "f0/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_8_ "f1/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_oddr2_frame "catgen/oddr2_frame") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_9_ "f1/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_o_tlast1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_9__rt "f1/Mcount_wr_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111000111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_0 "f0/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "4'h7")) + ) + (instance (rename f0_rd_addr_1 "f0/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/i_tready1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___172___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/o_tlast1")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_rd_addr_2 "f0/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_3 "f0/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_4 "f0/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_5 "f0/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_6 "f0/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_7 "f0/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_8 "f0/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_rd_addr_9 "f0/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF66FF69FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___16___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/write1")) + (property INIT (string "16'hA2A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_5__oddr2 "catgen/gen_pins[5].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_10__INV_0 "f0/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0004FFFF00040004")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_6_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_10_ "f1/Msub_dont_write_past_me_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_11_ "f1/Msub_dont_write_past_me_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full421_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Msub_dont_write_past_me_xor_12_ "f1/Msub_dont_write_past_me_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h7F2A")) + ) + (instance (rename f1_Mcount_rd_addr_xor_10_ "f1/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___5___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_11_ "f1/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_xor_12_ "f1/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_pktend_1 "slave_fifo32/pktend_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_6__INV_0 "f1/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename gpif_sync_reset_int "gpif_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01217_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hA521")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_2_1_FRB "f0/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance ext_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_reset_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___14___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv31")) + (property INIT (string "16'h4500")) + ) + (instance (rename slave_fifo32_slrd_1 "slave_fifo32/slrd_1") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<6>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0")) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___1___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance cat_sclk1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename f1_Mcount_wr_addr_lut_0__INV_0 "f1/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_cy1") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Mcount_rd_addr_lut_0__INV_0 "f1/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_write11 "f0/write11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___122___f0/write11")) + (property INIT (string "4'h1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___22___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_read_state_FSM_FFd1 "f0/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_read_state_FSM_FFd2 "f0/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31")) + (property INIT (string "16'h4500")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021")) + (property INIT (string "4'h9")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___3___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_11_ "f1/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___117___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "16'hFF57")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "8'h80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF0550FAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_dont_write_past_me_10__FRB "f0/dont_write_past_me<10>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA8AAAAAAABAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00400000AAEAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance LED_TXRX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_30_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_25_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_11__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_9__INV_0 "f0/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance XST_GND (viewref netlist (cellref GND (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2700050022000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In4 "slave_fifo32/state_FSM_FFd1-In4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4")) + (property INIT (string "4'hE")) + ) + (instance cat_miso_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_full_reg_glue_set "f0/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___122___f0/write11")) + (property INIT (string "32'hF0FF4044")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___48___slave_fifo32/_n0230_inv1")) + (property INIT (string "32'hEEAAA2AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0__n0161_inv1_cy "f0/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gpif_sync_reset_out "gpif_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "8'hE0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___150___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8FDA8A8A8A8A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance GPIF_D_7_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___149___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF0001FFFE0000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___148___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_rd_one_BRB0 "slave_fifo32/rd_one_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_rd_one_BRB1 "slave_fifo32/rd_one_BRB1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___147___slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance SFDX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename gen_clks_clkout2_buf "gen_clks/clkout2_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_2__rt "f0/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___13___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h2E22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_ctrl_tx_tvalid1 "slave_fifo32/ctrl_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h01000000")) + ) + (instance (rename f1_Result_0_2_FRB "f1/Result<0>2_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFF0FFFFFF80FF80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In12_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___46___slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1__n0161_inv1_cy "f1/_n0161_inv1_cy") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A8A8A8A8B9A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h55555504FFFFFF5D")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF55555554")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_cy_7__rt "f0/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8421000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000FAFB00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_3_1_FRB "f1/Result<3>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcount_rd_addr_cy_11__rt "f0/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_8__oddr2 "catgen/gen_pins[8].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance fx3_ce_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror1_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___118___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2-In11")) + (property INIT (string "8'h04")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFAAAAFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___120___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set")) + (property INIT (string "16'hFFA2")) + ) + (instance (rename f0_Mcount_rd_addr_xor_10_ "f0/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_11_ "f0/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_31_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_26_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_12_ "f0/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_idle_cycles_0 "slave_fifo32/idle_cycles_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_idle_cycles_1 "slave_fifo32/idle_cycles_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___171___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tvalid11")) + (property INIT (string "8'hC8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename catgen_gen_pins_0__oddr2 "catgen/gen_pins[0].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tready_int11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h3333333333323333")) + ) + (instance (rename slave_fifo32_idle_cycles_2 "slave_fifo32/idle_cycles_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_9__INV_0 "f1/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1555555555555555")) + ) + (instance gps_ref_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata65 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___107___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata65")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___106___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata71")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___105___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata81")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets_0_rstpot") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAA595566AA5555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___104___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata91")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01218_SW0_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFC55FC54FF55FF55")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<9>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_8_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT101") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_0__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT110") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")) + (property INIT (string "32'hFFFF8D88")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_0_ "f0/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT121") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_1_ "f0/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT131") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_xor_2_ "f0/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT141") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcount_rd_addr_xor_3_ "f0/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT201") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT151") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_4_ "f0/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT210") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0C0C0C0C0C0C0D0C")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT161") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT211 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT211") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_12_1_FRB "f0/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_5_ "f0/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/a_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT171 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT171") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename f0_Result_4_1_FRB "f0/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT221") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_xor_6_ "f0/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT231") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance XST_VCC (viewref netlist (cellref VCC (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT181") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_10 "f0/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifoadr_1_1 "slave_fifo32/fifoadr_1_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_7_ "f0/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_wr_addr_11 "f0/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_12 "f0/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT241") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT191") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h1")) + ) + (instance (rename f1_Result_1_2_FRB "f1/Result<1>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_1__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_read_state_FSM_FFd1_In111 "f0/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___30___f0/GND_14_o_read_OR_37_o1")) + (property INIT (string "16'hFDA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_8_ "f0/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT251") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT301") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance cat_ce_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_xor_9_ "f0/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT261") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT311") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename f0_Mcount_wr_addr_cy_5__rt "f0/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1 "slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT271") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32__n0258_inv_SW0 "slave_fifo32/_n0258_inv_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___121___slave_fifo32/_n0258_inv_SW0")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT321") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_i_tvalid_int1_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC000000080000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT281") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Mcount_wr_addr_cy_5__rt "f1/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291 "slave_fifo32/Mmux_state[1]_wr_fifo_data[31]_wide_mux_20_OUT291") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA8880888")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___12___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv31")) + (property INIT (string "32'hFFFF4B44")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEFEFEEEEEEEEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_0_ "f0/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEFEFEEEEEEEEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_1_ "f0/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_2_ "f0/Mcompar_becoming_full_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance tx_codec_d_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_3_ "f0/Mcompar_becoming_full_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_10__INV_0 "f1/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_becoming_full_cy_4_ "f0/Mcompar_becoming_full_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_data_tx_tvalid1 "slave_fifo32/data_tx_tvalid1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h00010000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFAAB9")) + ) + (instance (rename slave_fifo32__n0290_inv1 "slave_fifo32/_n0290_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___21___slave_fifo32/_n0223_inv1")) + (property INIT (string "32'h20002222")) + ) + (instance (rename f1_Result_4_1_FRB "f1/Result<4>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___174___slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0121111")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In14") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_4__INV_0 "f0/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___115___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<1>11")) + (property INIT (string "16'hFF57")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0102_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "8'h80")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In33") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFDFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In34") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100010001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAA9AAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04040000FF04FF00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE1E1E1E10FF0F00F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_3__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___37___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0154_inv1")) + (property INIT (string "8'hDC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT52") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA9A9A9A9AA5555AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8000000000000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT71") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h54A855AA55AA55AA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFF9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF00FFE8FF17FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In13") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA3B8819AA2A8808")) + ) + (instance GPIF_D_27_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF50A05FA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0404040404040504")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF7FFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_10_ "f0/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_11_ "f0/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0_lut") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111111011111111")) + ) + (instance tx_codec_d_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0010001000000010")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9090900000900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h99900000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0220000000000220")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0080000000000080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921")) + (property INIT (string "16'h0440")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01219") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFAF8AA0000000000")) + ) + (instance SFDX1_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Result_10_2_FRB "f0/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_2_2_FRB "f0/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000001FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_0_ "f0/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___7___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFF7FFF")) + ) + (instance debug_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance codec_fb_clk_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_2_ "f0/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance GPIF_D_9_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_5_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___127___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_5__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_write1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/write1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCCF05A0F5A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_F "slave_fifo32/state_FSM_FFd1-In3_F") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80808000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_state_FSM_FFd1_In3_G "slave_fifo32/state_FSM_FFd1-In3_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04155555FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hCCCCCCCC0F5AF05A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance SFDX2_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8421000000000000")) + ) + (instance (rename slave_fifo32_gpif_data_in_10 "slave_fifo32/gpif_data_in_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_11 "slave_fifo32/gpif_data_in_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_in_12 "slave_fifo32/gpif_data_in_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_13 "slave_fifo32/gpif_data_in_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_14 "slave_fifo32/gpif_data_in_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_15 "slave_fifo32/gpif_data_in_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_20 "slave_fifo32/gpif_data_in_20") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_16 "slave_fifo32/gpif_data_in_16") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h0001")) + ) + (instance (rename slave_fifo32_gpif_data_in_21 "slave_fifo32/gpif_data_in_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror21_SW1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h01")) + ) + (instance (rename slave_fifo32_gpif_data_in_17 "slave_fifo32/gpif_data_in_17") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_22 "slave_fifo32/gpif_data_in_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_18 "slave_fifo32/gpif_data_in_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_23 "slave_fifo32/gpif_data_in_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_19 "slave_fifo32/gpif_data_in_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_24 "slave_fifo32/gpif_data_in_24") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_25 "slave_fifo32/gpif_data_in_25") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_30 "slave_fifo32/gpif_data_in_30") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_26 "slave_fifo32/gpif_data_in_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_31 "slave_fifo32/gpif_data_in_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_gpif_data_in_27 "slave_fifo32/gpif_data_in_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_28 "slave_fifo32/gpif_data_in_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_in_29 "slave_fifo32/gpif_data_in_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_5_1_FRB "f0/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAA8AAA8AFFCFAA8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_codec_d_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Result_2_2_FRB "f1/Result<2>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212_SW1_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021")) + (property INIT (string "8'hEA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename catgen_gen_pins_11__oddr2 "catgen/gen_pins[11].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_12__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<12>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_i_tready1_INV_0 "f0/i_tready1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_wr_addr_0 "f1/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_1 "f1/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_2 "f1/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_3 "f1/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_4 "f1/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL4_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_wr_addr_5 "f1/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_6 "f1/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_7 "f1/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_8 "f1/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h00440F44")) + ) + (instance (rename f1_wr_addr_9 "f1/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance debug_clk_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename catgen_gen_pins_3__oddr2 "catgen/gen_pins[3].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___9___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<3>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_o_tvalid11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5555555555545555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00FBFB0005FBFB05")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01213_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFF5455FFFF5657")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___173___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0121111")) + (property INIT (string "4'h9")) + ) + (instance tx_codec_d_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_7__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o71") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Result_5_1_FRB "f1/Result<5>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL5_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_4__INV_0 "f1/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance debug_clk_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In1 "slave_fifo32/state_FSM_FFd2-In1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___177___slave_fifo32/Mcount_idle_cycles_xor<0>11")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In2 "slave_fifo32/state_FSM_FFd2-In2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1054101010101010")) + ) + (instance (rename slave_fifo32_state_FSM_FFd2_In3 "slave_fifo32/state_FSM_FFd2-In3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___176___slave_fifo32/state_FSM_FFd1-In4")) + (property INIT (string "16'hFFF4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA6AAA6A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1111000111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance tx_bandsel_a_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance reset_global_locked_OR_1_o1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___179___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/write1")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance GPIF_D_28_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + 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INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC60ACC000A0A0000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram15") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___28___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "32'hFFAEFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hDFCF")) + ) + (instance debug_4_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT4_SW0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___35___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511_SW0")) + (property INIT (string "16'hCCC9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<4>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFBF8FFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hAABAAAAA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6_SW2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___119___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg_glue_set")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_9__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance tx_bandsel_b_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename gen_clks_clkout3_buf "gen_clks/clkout3_buf") (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_3__rt "f0/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[17].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Result_3_2_FRB "f0/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[22].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename f1_ram_Mram_ram1 "f1/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFEFFFFFFFFFFF")) + ) + (instance (rename f1_ram_Mram_ram2 "f1/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_ram_Mram_ram3 "f1/ram/Mram_ram3") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/GND_50_o_read_OR_57_o1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h2272")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEEFFFEFFFFFFFFFF")) + ) + (instance (rename f1_ram_Mram_ram4 "f1/ram/Mram_ram4") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string 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(property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string 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(property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string 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(property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string 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(property INIT (string "2'h2")) + ) + (instance (rename f1_ram_Mram_ram7 "f1/ram/Mram_ram7") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string 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(property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string 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(property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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(property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr12_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr12_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEEFFEFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFEFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[25].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[30].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_10_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_7__INV_0 "f0/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_xor_0_ "f1/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance debug_6_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f1_Mcount_wr_addr_xor_1_ "f1/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_xor_2_ "f1/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_0__FRB "f0/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance pll_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___33___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_o_tready_int11")) + (property INIT (string "8'hA8")) + ) + (instance fx3_mosi_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_Mcount_wr_addr_xor_3_ "f1/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4000FBFF4400FFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[28].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_3_2_FRB "f1/Result<3>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[33].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_4_ "f1/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_5_ "f1/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_xor_6_ "f1/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_xor_7_ "f1/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___27___slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_xor_8_ "f1/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_CTL9_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename f1_Mcount_wr_addr_xor_9_ "f1/Mcount_wr_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[0].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT73_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5599665556955695")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_1__FRB "f0/dont_write_past_me<1>_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[41].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[36].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_2") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_3") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_4") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_5") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding_9") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_6") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_7") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_8") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_10 "f0/rd_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF55FF01FF55FF55")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_11 "f0/rd_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int14_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF55FF00FF55FF54")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_rd_addr_12 "f0/rd_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[43].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[38].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance codec_en_agc_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h5140514055555140")) + ) + (instance tx_codec_d_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[3].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_6_1_FRB "f1/Result<6>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h04040000FF04FF00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o10_SW1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[39].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[44].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance debug_8_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_dont_write_past_me_2__FRB "f0/dont_write_past_me<2>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_slwr_1 "slave_fifo32/slwr_1") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Msub_dont_write_past_me_xor<8>1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8A8A8A8A8B9A8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___39___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy<6>11")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 18)) + (property DATA_WIDTH_B (integer 18)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[46].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[51].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hF2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000010005")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h010F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int15") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFFFFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[6].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00F7000000F7F7F7")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance tx_codec_d_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_29_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[47].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[52].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance cat_mosi1 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___178___cat_mosi1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tready1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0111111111111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_9_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF0D2F087F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1")) + (property INIT (string "16'h5400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_wr_addr_cy_1__rt "f0/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[49].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[54].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___38___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1")) + (property INIT (string "16'hA8EA")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_i_tvalid_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h1555555555555555")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___41___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy<6>11")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[9].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_1__rt "f1/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_10 "slave_fifo32/gpif_data_out_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_11 "slave_fifo32/gpif_data_out_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_12 "slave_fifo32/gpif_data_out_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_13 "slave_fifo32/gpif_data_out_13") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_14 "slave_fifo32/gpif_data_out_14") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_15 "slave_fifo32/gpif_data_out_15") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_20 "slave_fifo32/gpif_data_out_20") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance SFDX1_TX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_CTL11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_gpif_data_out_21 "slave_fifo32/gpif_data_out_21") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_16 "slave_fifo32/gpif_data_out_16") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_12_2_FRB "f0/Result<12>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_gpif_data_out_17 "slave_fifo32/gpif_data_out_17") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_22 "slave_fifo32/gpif_data_out_22") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[55].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_out_18 "slave_fifo32/gpif_data_out_18") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_23 "slave_fifo32/gpif_data_out_23") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[60].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_gpif_data_out_24 "slave_fifo32/gpif_data_out_24") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_19 "slave_fifo32/gpif_data_out_19") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_gpif_data_out_25 "slave_fifo32/gpif_data_out_25") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_30 "slave_fifo32/gpif_data_out_30") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_out_31 "slave_fifo32/gpif_data_out_31") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_26 "slave_fifo32/gpif_data_out_26") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_27 "slave_fifo32/gpif_data_out_27") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_28 "slave_fifo32/gpif_data_out_28") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_gpif_data_out_29 "slave_fifo32/gpif_data_out_29") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_oddr2_clk "catgen/oddr2_clk") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012110_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h00008400")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_57__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[57].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___44___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2-In1_SW0")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_62__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[62].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename catgen_gen_pins_6__oddr2 "catgen/gen_pins[6].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_6__rt "f0/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_dont_write_past_me_4__FRB "f0/dont_write_past_me<4>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_11__INV_0 "f0/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcount_wr_addr_cy_6__rt "f1/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[58].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[63].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance GPIF_CTL12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance GPIF_D_11_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full411") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421")) + (property INIT (string "16'hFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___17___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full421")) + (property INIT (string "16'h0111")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_7__INV_0 "f1/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/GND_63_o_space[15]_LessThan_2_o1_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFB8FF88")) + ) + (instance (rename f0_Result_7_1_FRB "f0/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_dont_write_past_me_5__FRB "f0/dont_write_past_me<5>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_gpif_data_out_31_rstpot "slave_fifo32/gpif_data_out_31_rstpot") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hE4")) + ) + (instance (rename f1_Result_4_2_FRB "f1/Result<4>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW0") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT72_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance pps_fpga_out_enable_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hA8A8FDA8A8A8A8A8")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut<0>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut<1>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000000000001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<7>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___29___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>111")) + (property INIT (string "8'hA9")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut<2>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_dont_write_past_me_6__FRB "f0/dont_write_past_me<6>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/state") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut<3>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000009009")) + ) + (instance (rename f0_full_reg "f0/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut<4>") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___0___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg_rstpot")) + (property INIT (string "32'hFFFF7222")) + ) + (instance fx3_miso_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int16_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hEEEEFEEE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_7_1_FRB "f1/Result<7>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance tx_frame_p_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<0>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata111") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___162___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata101")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<1>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full611") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100010001")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<2>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full621") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata131") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___161___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<3>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFF5554")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___10___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0146_inv1")) + (property INIT (string "16'h2E22")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13_SW1_G") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<4>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata151") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___160___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata141")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<5>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[20].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[15].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata210") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___167___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata211") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___157___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata201")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<6>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___114___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/becoming_full921")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata171") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___159___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata161")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<7>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata231") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___156___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata221")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifoadr_0 "slave_fifo32/fifoadr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<8>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifoadr_1 "slave_fifo32/fifoadr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata191") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___158___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata181")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut<9>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h4C4CFF4C4C4C4C4C")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT21") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata251") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___155___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata241")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_xor<9>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAAAAB9AAAAAAA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT17") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___175___slave_fifo32/fifo64_to_gpmc32_resp/fifo_rst_gpif_rst_OR_155_o1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hDC")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT31") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance GPIF_CTL0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<13>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT41") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___152___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___154___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata261")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<14>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT51") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[23].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[18].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_xor<15>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT61") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata291") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___153___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata281")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_2__INV_0 "f0/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT91") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___131___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mmux_space[15]_GND_50_o_mux_35_OUT81")) + (property INIT (string "4'hE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_EP_WMARK1 "slave_fifo32/EP_WMARK1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_2 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_4 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_5 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_6 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000000DD09C000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_8 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/rd_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0020000002200200")) + ) + (instance (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance codec_sync_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___126___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/clear_dump_OR_131_o_SW0")) + (property INIT (string "4'hD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[31].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[26].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/full_reg") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_D_12_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance cat_mosi_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[34].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[29].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0303CFCF0203DFCF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/fifo_4k_2clk") (viewref view_1 (cellref fifo_4k_2clk (libraryref b200_lib))) + (property BUS_INFO (string "10:OUTPUT:wr_data_count<9:0>")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFBFBFBFFFB00FB00")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_5_2_FRB "f1/Result<5>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_read_state_FSM_FFd1_In111 "f1/read_state_FSM_FFd1-In111") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___31___f1/GND_14_o_read_OR_37_o1")) + (property INIT (string "16'hFDA8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_10 "slave_fifo32/debug1_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_11 "slave_fifo32/debug1_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_12 "slave_fifo32/debug1_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_13 "slave_fifo32/debug1_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_14 "slave_fifo32/debug1_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_15 "slave_fifo32/debug1_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_21 "slave_fifo32/debug1_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_22 "slave_fifo32/debug1_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/o_tvalid1_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<1>11") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h69")) + ) + (instance (rename slave_fifo32_debug1_18 "slave_fifo32/debug1_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_23 "slave_fifo32/debug1_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_19 "slave_fifo32/debug1_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_debug1_26 "slave_fifo32/debug1_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_31 "slave_fifo32/debug1_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_27 "slave_fifo32/debug1_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_28 "slave_fifo32/debug1_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug1_29 "slave_fifo32/debug1_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_0_ "f0/Msub_dont_write_past_me_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[42].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[37].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_1_ "f0/Msub_dont_write_past_me_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_2_ "f0/Msub_dont_write_past_me_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg_glue_set") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___45___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/write1")) + (property INIT (string "32'h5540FFC0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hEFEEEFEEEFEEFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81_SW2_G") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h54555454FCFFFCFC")) + ) + (instance GPIF_CTL3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_3_ "f0/Msub_dont_write_past_me_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 36)) + (property DATA_WIDTH_B (integer 36)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_4_ "f0/Msub_dont_write_past_me_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h2002000000002002")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___180___slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/write1")) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8822228C80202084")) + ) + (instance (rename bus_sync_reset_int "bus_sync/reset_int") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012113") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_5_ "f0/Msub_dont_write_past_me_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB33A820A820A820")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_6_ "f0/Msub_dont_write_past_me_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_7_ "f0/Msub_dont_write_past_me_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___36___slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "4'h7")) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_8_ "f0/Msub_dont_write_past_me_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[45].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[50].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Result_8_1_FRB "f1/Result<8>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_xor_9_ "f0/Msub_dont_write_past_me_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1 "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/read1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename catgen_gen_pins_9__oddr2 "catgen/gen_pins[9].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/ram/Mram_ram") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 36)) + (property DATA_WIDTH_B (integer 36)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<10>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[53].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[48].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_10_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy<5>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy<6>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___26___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv_SW0")) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy<7>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy<8>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename catgen_gen_pins_1__oddr2 "catgen/gen_pins[1].oddr2") (viewref netlist (cellref ODDR2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property DDR_ALIGNMENT (string "C0")) + (property SRTYPE (string "ASYNC")) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy<9>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe "slave_fifo32/sloe") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_10 "slave_fifo32/debug2_10") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFF7F7F2AFF2A2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_debug2_11 "slave_fifo32/debug2_11") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_12 "slave_fifo32/debug2_12") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename f0_Mcount_rd_addr_cy_9__rt "f0/Mcount_rd_addr_cy<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_13 "slave_fifo32/debug2_13") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_14 "slave_fifo32/debug2_14") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_15 "slave_fifo32/debug2_15") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[61].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[56].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_debug2_16 "slave_fifo32/debug2_16") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_21 "slave_fifo32/debug2_21") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_17 "slave_fifo32/debug2_17") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "16'h6AA9")) + ) + (instance (rename slave_fifo32_debug2_22 "slave_fifo32/debug2_22") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_18 "slave_fifo32/debug2_18") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_slrd "slave_fifo32/slrd") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_23 "slave_fifo32/debug2_23") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_19 "slave_fifo32/debug2_19") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_debug2_26 "slave_fifo32/debug2_26") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_31 "slave_fifo32/debug2_31") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_27 "slave_fifo32/debug2_27") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_28 "slave_fifo32/debug2_28") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_debug2_29 "slave_fifo32/debug2_29") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance debug_11_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_write_AND_42_o_inv2 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/read_write_AND_42_o_inv2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hDFCF")) + ) + (instance (rename f0_Result_6_2_FRB "f0/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_2__INV_0 "f1/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___168___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1021")) + (property INIT (string "4'h9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_10") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_11") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_12") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_13") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT21") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "32'hBF4040BF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_14") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_F") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFD")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_20") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror7_SW2_G") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_15") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_21") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n0121211") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h8282414141418228")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_16") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_17") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_22") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_18") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT31") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hE178E1E1E1E1E1E1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_23") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_19") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_24") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_25") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_30") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_31") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_26") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_27") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_28") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___34___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT3111")) + (property INIT (string "32'h9AAAAAA6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[59].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[64].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding_29") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_0_11_INV_0 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_a_xor<0>11_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_slwr "slave_fifo32/slwr") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hAAAA9AAAA6A696A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___40___slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write1")) + (property INIT (string "16'hEFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT61") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h99AA99A6AAAAAAA6")) + ) + (instance (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance codec_ctrl_in_0_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<2>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01211_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFF05FF04FF")) + ) + (instance (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFB0400FFFA0500")) + ) + (instance (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance debug_12_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT81") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFF0040BFBF4000FF")) + ) + (instance (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<0>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA6AAA6A6")) + ) + (instance (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + (property IOB (string "TRUE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_13_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<1>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (viewref netlist (cellref FDR (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<2>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[2].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<12>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<3>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<3>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___15___slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/write1")) + (property INIT (string "16'hA2A6")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut<2>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata33 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<10>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<13>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<4>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata41") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___166___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata33")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Result_9_1_FRB "f0/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance GPIF_CTL7_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<11>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy<14>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<5>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<12>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<6>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata61") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___165___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata51")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_Result_6_2_FRB "f1/Result<6>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<13>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename bus_sync_reset_out "bus_sync/reset_out") (viewref netlist (cellref FDP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h9009000000000000")) + ) + (instance codec_ctrl_in_1_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<7>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename f1_Result_10_2_FRB "f1/Result<10>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'h0307")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int12") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFFFFFFFFFFFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<14>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW0") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFDBFDDBFDFFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int13") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "16'hF700")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___43___slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full1021")) + (property INIT (string "16'hEFFF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<4>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<8>") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h59555959")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n01216_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFCBFFBEFFC7FF7DF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata81") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___164___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata71")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[10].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int16") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hF0E4D8CC00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut<15>") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'h1B")) + ) + (instance debug_13_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance pll_sclk_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<9>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91 "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___163___slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/Mmux_o_tdata91")) + (property INIT (string "8'hE4")) + ) + (instance fx3_sclk_IBUF (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + (property IBUF_DELAY_VALUE (string "0")) + (property IFD_DELAY_VALUE (string "AUTO")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[5].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr5_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram10") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram11") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram12") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram13") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string 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(property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string 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(property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string 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(property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram14") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string 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(property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string 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(property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string 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(property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string 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(property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string 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(property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string 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(property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram16") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string 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(property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string 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(property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string 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(property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/ram/Mram_ram17") (viewref netlist (cellref RAMB8BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "16:OUTPUT:DOBDO<15:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string 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(property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 1)) + (property DATA_WIDTH_B (integer 1)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "18'h00000")) + (property INIT_B (string "18'h00000")) + (property RAM_MODE (string "TDP")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "18'h00000")) + (property SRVAL_B (string "18'h00000")) + (property INIT_FILE (string "NONE")) + (property SIM_COLLISION_CHECK (string "ALL")) + ) + (instance (rename f0_Mcount_wr_addr_cy_11_ "f0/Mcount_wr_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut<5>1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'hA9AAA9A9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<3>11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___18___slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<2>11")) + (property INIT (string "32'h6AAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance SRX2_RX_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance GPIF_D_0_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance codec_txrx_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[13].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Msub_dont_write_past_me_lut_11__INV_0 "f1/Msub_dont_write_past_me_lut<11>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance codec_ctrl_in_2_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[1].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[8].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_14_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_wr_addr_0 "f0/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_1 "f0/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_wr_addr_2 "f0/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_3 "f0/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f0_wr_addr_4 "f0/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_2__rt "f0/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_wr_addr_5 "f0/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Msub_dont_write_past_me_lut_5__INV_0 "f0/Msub_dont_write_past_me_lut<5>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename f0_wr_addr_6 "f0/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_7 "f0/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_wr_addr_8 "f0/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hC60ACC000A0A0000")) + ) + (instance (rename f0_wr_addr_9 "f0/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_wr_addr_cy_2__rt "f1/Mcount_wr_addr_cy<2>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty") (viewref netlist (cellref FDS (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[16].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[21].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[4].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance codec_ctrl_in_3_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename f0_ram_Mram_ram1 "f0/ram/Mram_ram1") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram2 "f0/ram/Mram_ram2") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string 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(true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string 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(property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance (rename f0_ram_Mram_ram9 "f0/ram/Mram_ram9") (viewref netlist (cellref RAMB16BWER (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "32:INPUT:DIA<31:0>")) + (property INIT_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_08 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_09 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_0F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_10 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_11 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_12 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_13 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_14 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_15 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_16 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_17 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_18 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_19 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_1F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_20 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_21 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_22 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_23 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_24 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_25 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_26 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_27 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_28 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_29 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_2F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_30 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_31 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_32 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_33 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_34 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_35 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_36 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_37 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_38 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_39 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3A (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3B (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3C (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3D (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3E (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_3F (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property WRITE_MODE_A (string "READ_FIRST")) + (property WRITE_MODE_B (string "WRITE_FIRST")) + (property DATA_WIDTH_A (integer 2)) + (property DATA_WIDTH_B (integer 2)) + (property DOA_REG (integer 0)) + (property DOB_REG (integer 0)) + (property EN_RSTRAM_A (boolean (true))) + (property EN_RSTRAM_B (boolean (true))) + (property INITP_00 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_01 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_02 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_03 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_04 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_05 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_06 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INITP_07 (string "256'h0000000000000000000000000000000000000000000000000000000000000000")) + (property INIT_A (string "36'h000000000")) + (property INIT_B (string "36'h000000000")) + (property RST_PRIORITY_A (string "CE")) + (property RST_PRIORITY_B (string "CE")) + (property RSTTYPE (string "SYNC")) + (property SRVAL_A (string "36'h000000000")) + (property SRVAL_B (string "36'h000000000")) + (property SIM_COLLISION_CHECK (string "ALL")) + (property SIM_DEVICE (string "SPARTAN6")) + (property INIT_FILE (string "NONE")) + ) + (instance debug_20_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_15_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0155115501111111")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT411") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<10>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr3_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_cy_7__rt "f0/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<11>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename gen_clks_dcm_sp_inst "gen_clks/dcm_sp_inst") (viewref netlist (cellref DCM_SP (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "8:OUTPUT:STATUS<7:0>")) + (property CLKIN_DIVIDE_BY_2 (boolean (false))) + (property CLKOUT_PHASE_SHIFT (string "NONE")) + (property CLK_FEEDBACK (string "1X")) + (property DESKEW_ADJUST (string "SYSTEM_SYNCHRONOUS")) + (property DFS_FREQUENCY_MODE (string "LOW")) + (property DLL_FREQUENCY_MODE (string "LOW")) + (property DSS_MODE (string "NONE")) + (property DUTY_CYCLE_CORRECTION (boolean (true))) + (property FACTORY_JF (string "16'hC080")) + (property STARTUP_WAIT (boolean (false))) + (property CLKFX_DIVIDE (integer 2)) + (property CLKFX_MULTIPLY (integer 5)) + (property PHASE_SHIFT (integer 0)) + (property CLKDV_DIVIDE (string "2.000000")) + (property CLKIN_PERIOD (string "25.000000")) + (property VERY_HIGH_FREQUENCY (string "FALSE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<12>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[24].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[19].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f1_Mcount_wr_addr_cy_7__rt "f1/Mcount_wr_addr_cy<7>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___6___slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In11")) + (property INIT (string "32'h8A8ADF8A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut<8>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_7__srlc32e "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/gen_srlc32e[7].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___25___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT511")) + (property INIT (string "8'hBF")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_12__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<5>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_0") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_1") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_2") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_3 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_3") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_4") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_10_ "f1/Mcount_rd_addr_cy<10>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_5") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_6") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT531") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___2___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7_SW0")) + (property INIT (string "16'h8000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_7") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_8 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_8") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_9 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr_9") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_Mcount_rd_addr_cy_11_ "f1/Mcount_rd_addr_cy<11>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance debug_21_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_16_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read_SW0 "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "32'h80000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<8>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr8_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Result_7_2_FRB "f0/Result<7>2_FRB") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a_xor<4>11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h6AAAAAAAAAAAAAA9")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[32].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[27].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<0>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (viewref netlist (cellref FD (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata101 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___102___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata101")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_14_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_14_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<1>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0 "slave_fifo32/Mmux_state[1]_wr_fifo_eof_Mux_22_o1_SW0") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___24___slave_fifo32/Mmux_state[1]_wr_fifo_xfer_Mux_21_o1_SW0")) + (property INIT (string "32'h80008080")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata111 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___101___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata111")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<2>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata121 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1 "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___125___slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/Mmux_o_tvalid11")) + (property INIT (string "4'h4")) + ) + (instance (rename f0_Mcount_wr_addr_lut_0__INV_0 "f0/Mcount_wr_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<3>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcount_rd_addr_lut_0__INV_0 "f0/Mcount_rd_addr_lut<0>_INV_0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h1")) + (property XILINX_LEGACY_PRIM (string "INV")) + (property XILINX_REPORT_XFORM (string "INV")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata131 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___100___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata131")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<10>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[11].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<4>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata141 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___99___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata141")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<11>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_o_tready_int1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h00000C0000000800")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<5>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___98___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata151")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<12>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata201 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___93___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata201")) + (property INIT (string "4'h8")) + ) + (instance (rename f1_wr_addr_10 "f1/wr_addr_10") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f1_wr_addr_11 "f1/wr_addr_11") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "8'hFB")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<6>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_wr_addr_12 "f1/wr_addr_12") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW1") (viewref netlist (cellref MUXF7 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___110___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata210")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata161 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___97___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata161")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<13>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_terror51_SW2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h0000000100000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata211 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___91___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata211")) + (property INIT (string "4'h8")) + ) + (instance debug_22_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance debug_17_OBUF (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property CAPACITANCE (string "DONT_CARE")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<7>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/gen_srlc32e[12].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<14>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2-In1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'h7FFF7F7F2AFF2A2A")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___90___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata221")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata171 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___96___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata171")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[40].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/gen_srlc32e[35].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<8>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance GPIF_D_14_IOBUF (viewref netlist (cellref IOBUF (libraryref hdi_primitives))) + (property XILINX_REPORT_XFORM (string "IOBUF")) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Msub_dont_write_past_me_cy_0__rt "f0/Msub_dont_write_past_me_cy<0>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut<15>") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "64'hBB4BBBBBBB4BBB4B")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata231 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata181 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___95___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata181")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215_SW0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___49___slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full1011")) + (property INIT (string "8'h9F")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_xor<9>") (viewref netlist (cellref XORCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<2>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata241 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___89___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata241")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata191 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___94___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata191")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_15_BRB1") (viewref netlist (cellref FDE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b0")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<3>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata301 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___103___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata301")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata251 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___88___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata251")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___82___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata310")) + (property INIT (string "4'h8")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/gen_srlc32e[14].srlc32e") (viewref netlist (cellref SRLC32E (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property BUS_INFO (string "5:INPUT:A<4:0>")) + (property INIT (string "32'h00000000")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata311 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___92___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata311")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata261") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___113___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata110")) + (property INIT (string "8'hE4")) + ) + (instance (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename f1_dont_write_past_me_0__FRB "f1/dont_write_past_me<0>_FRB") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "1'b1")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy<0>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata321 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___87___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata321")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata271") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___112___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata121")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property INIT (string "2'h2")) + ) + (instance (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy<1>") (viewref netlist (cellref MUXCY (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata331 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___86___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata331")) + (property INIT (string "8'hE4")) + ) + (instance (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata281 "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata281") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property XSTLIB (boolean (true))) + (property PK_HLUTNM (string "___XLNM___83___slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/Mmux_o_tdata231")) + (property INIT (string "8'hE4")) + ) + (net codec_main_clk_n (joined + (portref IB (instanceref gen_clks_clkin1_buf)) + (portref codec_main_clk_n) + ) + + (property DIFF_TERM (boolean (false))) + ) + (net codec_main_clk_p (joined + (portref I (instanceref gen_clks_clkin1_buf)) + (portref codec_main_clk_p) + ) + + (property DIFF_TERM (boolean (false))) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + (portref rst (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9__rt "f1/Mcount_rd_addr_cy<9>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_9__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_xor<9>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename f0_rd_addr_12__wr_addr_12__equal_11_o_l1 "f0/rd_addr[12]_wr_addr[12]_equal_11_o_l1") (joined + (portref O (instanceref f0__n0161_inv1_cy)) + (portref CI (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_Mcount_idle_cycles1 "slave_fifo32/Mcount_idle_cycles1") (joined + (portref D (instanceref slave_fifo32_idle_cycles_1)) + (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_1_11)) + ) + ) + (net (rename slave_fifo32_Mcount_idle_cycles2 "slave_fifo32/Mcount_idle_cycles2") (joined + (portref D (instanceref slave_fifo32_idle_cycles_2)) + (portref O (instanceref slave_fifo32_Mcount_idle_cycles_xor_2_11)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_5__rt "f0/Mcount_rd_addr_cy<5>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_5__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename f0_wr_addr_0_ "f0/wr_addr[0]") (joined + (portref Q (instanceref f0_wr_addr_0)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 12) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_1_ "f0/wr_addr[1]") (joined + (portref Q (instanceref f0_wr_addr_1)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 11) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10__rt "f0/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f0_wr_addr_2_ "f0/wr_addr[2]") (joined + (portref Q (instanceref f0_wr_addr_2)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 10) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_3_ "f0/wr_addr[3]") (joined + (portref Q (instanceref f0_wr_addr_3)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 9) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_4_ "f0/wr_addr[4]") (joined + (portref Q (instanceref f0_wr_addr_4)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 8) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_5_ "f0/wr_addr[5]") (joined + (portref Q (instanceref f0_wr_addr_5)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 7) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_6_ "f0/wr_addr[6]") (joined + (portref Q (instanceref f0_wr_addr_6)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 6) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Result_5_2_FRB "f0/Result<5>2_FRB") (joined + (portref D (instanceref f0_wr_addr_5)) + (portref Q (instanceref f0_Result_5_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename f0_wr_addr_7_ "f0/wr_addr[7]") (joined + (portref Q (instanceref f0_wr_addr_7)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 5) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 5) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_8_ "f0/wr_addr[8]") (joined + (portref Q (instanceref f0_wr_addr_8)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 4) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 4) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_wr_addr_9_ "f0/wr_addr[9]") (joined + (portref Q (instanceref f0_wr_addr_9)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 3) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 3) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename f0_rd_addr_10_ "f0/rd_addr[10]") (joined + (portref Q (instanceref f0_rd_addr_10)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Result_11_1_FRB "f1/Result<11>1_FRB") (joined + (portref D (instanceref f1_rd_addr_11)) + (portref Q (instanceref f1_Result_11_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_11__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename f0_rd_addr_11_ "f0/rd_addr[11]") (joined + (portref Q (instanceref f0_rd_addr_11)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_rd_addr_12_ "f0/rd_addr[12]") (joined + (portref Q (instanceref f0_rd_addr_12)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 0) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 0) (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[13]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata51)) + (portref (member din 58) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[14]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata61)) + (portref (member din 57) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1__n0161_inv "f1/_n0161_inv") (joined + (portref CE (instanceref f1_rd_addr_1)) + (portref CE (instanceref f1_rd_addr_2)) + (portref CE (instanceref f1_rd_addr_3)) + (portref CE (instanceref f1_rd_addr_4)) + (portref CE (instanceref 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(portref (member din 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[15]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata71)) + (portref (member din 56) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[21]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata141)) + (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[16]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata81)) + (portref (member din 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"slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[17]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata91)) + (portref (member din 54) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_23_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[23]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata161)) + (portref (member din 48) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_18_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[18]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata101)) + (portref (member din 53) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_dont_write_past_me_12__FRB "f0/dont_write_past_me<12>_FRB") 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(member din 44) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[28]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata211)) + (portref (member din 43) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[29]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata221)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/o_tready_int") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + (portref I1 (instanceref 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(portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref I0 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + ) + ) + (net (rename tx_tdata_9_ "tx_tdata[9]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/read") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[30]") (joined + (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 41) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[25]") (joined + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 46) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61)) + (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[31]") (joined + (portref (member DIA 18) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 40) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[26]") (joined + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 45) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71)) + (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[27]") (joined + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 44) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[32]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portref (member dout 39) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tlast "slave_fifo32/fifo64_to_gpmc32_resp/i32_tlast") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1)) + (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[28]") (joined + (portref (member DIA 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 43) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/wr_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[29]") (joined + (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_data_rx_tvalid "slave_fifo32/data_rx_tvalid") (joined + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_10_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[10]") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_11_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[11]") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_)) + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0008_12_ "slave_fifo32/fifo64_to_gpmc32_tx/n0008[12]") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref 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(rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0003_12_ "slave_fifo32/fifo64_to_gpmc32_rx/n0003[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_10_ 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][4]") (joined + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n0129_inv3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/full") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_write1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0129_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I3 (instanceref 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full (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][5]") (joined + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][6]") (joined + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][7]") (joined + (portref (member DOB 24) (instanceref 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f1_Result_11_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_11__rt)) + ) + ) + (net fx3_miso (joined + (portref O (instanceref fx3_miso_OBUF)) + (portref fx3_miso) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/fifo64_to_fifo32/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set)) + ) + ) + (net tx_tlast (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref (member DIADI 15) (instanceref f1_ram_Mram_ram33)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_tx/cross_clock_fifo/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In12_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref I4 (instanceref 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename gen_clks_clk0 "gen_clks/clk0") (joined + (portref I (instanceref gen_clks_clkout1_buf)) + (portref CLK0 (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_11__rt "f0/Mcount_wr_addr_cy<11>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_11__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_11_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata110)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_11_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1__rt "f0/Msub_dont_write_past_me_cy<1>_rt") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_1__rt)) + (portref S (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net fx3_mosi (joined + (portref I (instanceref fx3_mosi_IBUF)) + (portref fx3_mosi) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10_ "f1/Mcount_wr_addr_cy[10]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy<4>_inv") (joined + (portref D (instanceref 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f1__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0076_inv") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/read") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename bus_sync_reset_int "bus_sync/reset_int") (joined + (portref Q (instanceref bus_sync_reset_int)) + (portref D (instanceref bus_sync_reset_out)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full92 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full92") (joined + (portref O (instanceref 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(rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1__rt)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_)) + ) + ) + (net (rename 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_4_)) + (portref LI (instanceref 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_7_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[8]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_8_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/dont_write_past_me[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1-In1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full621_FRB") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621_FRB)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid_bdd8 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_tvalid_bdd8") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2__rt)) + ) + ) + (net tx_codec_d_5_OBUF (joined + (portref Q (instanceref catgen_gen_pins_5__oddr2)) + (portref I (instanceref tx_codec_d_5_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[0]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[1]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_6__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename f0_Result_9_2_FRB "f0/Result<9>2_FRB") (joined + (portref D (instanceref f0_wr_addr_9)) + (portref Q (instanceref f0_Result_9_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_9__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_becoming_full_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net tx_frame_p_OBUF (joined + (portref Q (instanceref catgen_oddr2_frame)) + (portref I (instanceref tx_frame_p_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_inv") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + ) + ) + (net IFCLK (joined + (portref O (instanceref IFCLK_OBUF)) + (portref IFCLK) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRAWRADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/wr_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRA 5) 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref R (instanceref f1_wr_addr_9)) + (portref R (instanceref f1_wr_addr_8)) + (portref R (instanceref f1_wr_addr_7)) + (portref R (instanceref f1_wr_addr_6)) + (portref R (instanceref f1_wr_addr_5)) + (portref R (instanceref f1_wr_addr_4)) + (portref R (instanceref f1_wr_addr_3)) + (portref R (instanceref f1_wr_addr_2)) + (portref R (instanceref f1_wr_addr_12)) + (portref R (instanceref f1_wr_addr_11)) + (portref R (instanceref f1_wr_addr_10)) + (portref R (instanceref f1_wr_addr_1)) + (portref R (instanceref f1_wr_addr_0)) + (portref R (instanceref f1_rd_addr_9)) + (portref R (instanceref f1_rd_addr_8)) + (portref R (instanceref f1_rd_addr_7)) + (portref R (instanceref f1_rd_addr_6)) + (portref R (instanceref f1_rd_addr_5)) + (portref R (instanceref f1_rd_addr_4)) + (portref R (instanceref f1_rd_addr_3)) + (portref R (instanceref f1_rd_addr_2)) + (portref R (instanceref f1_rd_addr_12)) + (portref R (instanceref f1_rd_addr_11)) + (portref R (instanceref f1_rd_addr_10)) + (portref R (instanceref f1_rd_addr_1)) + (portref R (instanceref f1_rd_addr_0)) + (portref R (instanceref f1_read_state_FSM_FFd1)) + (portref R (instanceref f0_wr_addr_9)) + (portref R (instanceref f0_wr_addr_8)) + (portref R (instanceref f0_wr_addr_7)) + (portref R (instanceref f0_wr_addr_6)) + (portref R (instanceref f0_wr_addr_5)) + (portref R (instanceref f0_wr_addr_4)) + (portref R (instanceref f0_wr_addr_3)) + (portref R (instanceref f0_wr_addr_2)) + (portref R (instanceref f0_wr_addr_12)) + (portref R (instanceref f0_wr_addr_11)) + (portref R (instanceref f0_wr_addr_10)) + (portref R (instanceref f0_wr_addr_1)) + (portref R (instanceref f0_wr_addr_0)) + (portref R (instanceref f0_rd_addr_9)) + (portref R (instanceref f0_rd_addr_8)) + (portref R (instanceref f0_rd_addr_7)) + (portref R (instanceref f0_rd_addr_6)) + (portref R (instanceref f0_rd_addr_5)) + (portref R (instanceref f0_rd_addr_4)) + (portref R (instanceref f0_rd_addr_3)) + (portref R (instanceref f0_rd_addr_2)) + (portref R (instanceref f0_rd_addr_12)) + (portref R (instanceref f0_rd_addr_11)) + (portref R (instanceref f0_rd_addr_10)) + (portref R (instanceref f0_rd_addr_1)) + (portref R (instanceref f0_rd_addr_0)) + (portref R (instanceref f0_read_state_FSM_FFd1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo_rst_gpif_rst_OR_155_o1)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref R (instanceref f1_full_reg)) + (portref R (instanceref f0_full_reg)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref S (instanceref f1_Result_0_2_FRB)) + (portref R (instanceref f1_Result_1_2_FRB)) + (portref R (instanceref f1_Result_2_2_FRB)) + (portref R (instanceref f1_Result_3_2_FRB)) + (portref R (instanceref f1_Result_4_2_FRB)) + (portref R (instanceref f1_Result_5_2_FRB)) + (portref R (instanceref f1_Result_6_2_FRB)) + (portref R (instanceref f1_Result_7_2_FRB)) + (portref R (instanceref f1_Result_8_2_FRB)) + (portref R (instanceref f1_Result_9_2_FRB)) + (portref R (instanceref f1_Result_10_2_FRB)) + (portref R (instanceref f1_Result_11_2_FRB)) + (portref R (instanceref f1_Result_12_2_FRB)) + (portref S (instanceref f1_Result_0_1_FRB)) + (portref R (instanceref f1_Result_1_1_FRB)) + (portref R (instanceref f1_Result_2_1_FRB)) + (portref R (instanceref f1_Result_3_1_FRB)) + (portref R (instanceref f1_Result_4_1_FRB)) + (portref R (instanceref f1_Result_5_1_FRB)) + (portref R (instanceref f1_Result_6_1_FRB)) + (portref R (instanceref f1_Result_7_1_FRB)) + (portref R (instanceref f1_Result_8_1_FRB)) + (portref R (instanceref f1_Result_9_1_FRB)) + (portref R (instanceref f1_Result_10_1_FRB)) + (portref R (instanceref f1_Result_11_1_FRB)) + (portref R (instanceref f1_Result_12_1_FRB)) + (portref S (instanceref f1_dont_write_past_me_0__FRB)) + (portref R (instanceref f1_dont_write_past_me_1__FRB)) + (portref S (instanceref f1_dont_write_past_me_2__FRB)) + (portref S (instanceref f1_dont_write_past_me_3__FRB)) + (portref S (instanceref f1_dont_write_past_me_4__FRB)) + (portref S (instanceref f1_dont_write_past_me_5__FRB)) + (portref S (instanceref f1_dont_write_past_me_6__FRB)) + (portref S (instanceref f1_dont_write_past_me_7__FRB)) + (portref S (instanceref f1_dont_write_past_me_8__FRB)) + (portref S (instanceref f1_dont_write_past_me_9__FRB)) + (portref S (instanceref f1_dont_write_past_me_10__FRB)) + (portref S (instanceref f1_dont_write_past_me_11__FRB)) + (portref S (instanceref f1_dont_write_past_me_12__FRB)) + (portref S (instanceref f0_Result_0_2_FRB)) + (portref R (instanceref f0_Result_1_2_FRB)) + (portref R (instanceref f0_Result_2_2_FRB)) + (portref R (instanceref f0_Result_3_2_FRB)) + (portref R (instanceref f0_Result_4_2_FRB)) + (portref R (instanceref f0_Result_5_2_FRB)) + (portref R (instanceref f0_Result_6_2_FRB)) + (portref R (instanceref f0_Result_7_2_FRB)) + (portref R (instanceref f0_Result_8_2_FRB)) + (portref R (instanceref f0_Result_9_2_FRB)) + (portref R (instanceref f0_Result_10_2_FRB)) + (portref R (instanceref f0_Result_11_2_FRB)) + (portref R (instanceref f0_Result_12_2_FRB)) + (portref S (instanceref f0_Result_0_1_FRB)) + (portref R (instanceref f0_Result_1_1_FRB)) + (portref R (instanceref f0_Result_2_1_FRB)) + (portref R (instanceref f0_Result_3_1_FRB)) + (portref R (instanceref f0_Result_4_1_FRB)) + (portref R (instanceref f0_Result_5_1_FRB)) + (portref R (instanceref f0_Result_6_1_FRB)) + (portref R (instanceref f0_Result_7_1_FRB)) + (portref R (instanceref f0_Result_8_1_FRB)) + (portref R (instanceref f0_Result_9_1_FRB)) + (portref R (instanceref f0_Result_10_1_FRB)) + (portref R (instanceref f0_Result_11_1_FRB)) + (portref R (instanceref f0_Result_12_1_FRB)) + (portref S (instanceref f0_dont_write_past_me_0__FRB)) + (portref R (instanceref f0_dont_write_past_me_1__FRB)) + (portref S (instanceref f0_dont_write_past_me_2__FRB)) + (portref S (instanceref f0_dont_write_past_me_3__FRB)) + (portref S (instanceref f0_dont_write_past_me_4__FRB)) + (portref S (instanceref f0_dont_write_past_me_5__FRB)) + (portref S (instanceref f0_dont_write_past_me_6__FRB)) + (portref S (instanceref f0_dont_write_past_me_7__FRB)) + (portref S (instanceref f0_dont_write_past_me_8__FRB)) + (portref S (instanceref f0_dont_write_past_me_9__FRB)) + (portref S (instanceref f0_dont_write_past_me_10__FRB)) + (portref S (instanceref f0_dont_write_past_me_11__FRB)) + (portref S (instanceref f0_dont_write_past_me_12__FRB)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + (portref R (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + ) + ) + (net (rename f0_Result_11_1_FRB "f0/Result<11>1_FRB") (joined + (portref D (instanceref f0_rd_addr_11)) + (portref Q (instanceref f0_Result_11_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_11__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[10]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[11]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[12]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[13]") (joined + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_13_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_14_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename 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slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename ctrl_tdata_8_ "ctrl_tdata[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net GPIF_CTL5_IBUF (joined + (portref D (instanceref slave_fifo32_EP_WMARK)) + (portref O (instanceref GPIF_CTL5_IBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/GND_56_o_read_OR_123_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref ENB (instanceref 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0154_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0154_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr1_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr2_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr6_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr8_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_write1)) + (portref (member WEA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a3") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11)) + ) + ) + (net (rename f1_GND_14_o_read_OR_37_o "f1/GND_14_o_read_OR_37_o") (joined + (portref O (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref ENBRDEN (instanceref f1_ram_Mram_ram33)) + (portref ENB (instanceref f1_ram_Mram_ram31)) + (portref ENB (instanceref f1_ram_Mram_ram30)) + (portref ENB (instanceref f1_ram_Mram_ram32)) + (portref ENB (instanceref f1_ram_Mram_ram28)) + (portref ENB (instanceref f1_ram_Mram_ram27)) + (portref ENB (instanceref f1_ram_Mram_ram29)) + (portref ENB (instanceref f1_ram_Mram_ram25)) + (portref ENB (instanceref f1_ram_Mram_ram24)) + (portref ENB (instanceref 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(instanceref f1_ram_Mram_ram2)) + (portref ENB (instanceref f1_ram_Mram_ram4)) + (portref ENB (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/_n0131_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker__n0131_inv1)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_3_ "slave_fifo32/ctrl_rx_tdata[3]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a4") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_a5") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_4_ "slave_fifo32/ctrl_rx_tdata[4]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_slrd_rstpot "slave_fifo32/slrd_rstpot") (joined + (portref D (instanceref slave_fifo32_slrd)) + (portref O (instanceref slave_fifo32_slrd_rstpot)) + (portref D (instanceref slave_fifo32_slrd_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_5_ "slave_fifo32/ctrl_rx_tdata[5]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281)) + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_3_)) + ) + ) + (net tx_codec_d_11_OBUF (joined + (portref Q (instanceref catgen_gen_pins_11__oddr2)) + (portref I (instanceref tx_codec_d_11_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_6_ "slave_fifo32/ctrl_rx_tdata[6]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291)) + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_7_ "slave_fifo32/ctrl_rx_tdata[7]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301)) + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net tx_codec_d_9_OBUF (joined + (portref Q (instanceref catgen_gen_pins_9__oddr2)) + (portref I (instanceref tx_codec_d_9_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/empty") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_8_ "slave_fifo32/ctrl_rx_tdata[8]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311)) + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[13]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In_bdd1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + ) + ) + (net (rename slave_fifo32_read_ready_go "slave_fifo32/read_ready_go") (joined + (portref Q (instanceref slave_fifo32_read_ready_go)) + (portref I2 (instanceref slave_fifo32__n0290_inv1)) + (portref I0 (instanceref slave_fifo32__n0258_inv_SW0)) + (portref I1 (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In2)) + (portref I1 (instanceref slave_fifo32_slrd_rstpot_SW0)) + (portref I2 (instanceref slave_fifo32_sloe_1_rstpot)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_14_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines3215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In2 "slave_fifo32/state_FSM_FFd1-In2") (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In2)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In4)) + (portref I3 (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In3 "slave_fifo32/state_FSM_FFd1-In3") (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In4)) + ) + ) + (net (rename codec_ctrl_in_0_ "codec_ctrl_in[0]") (joined + (portref O (instanceref codec_ctrl_in_0_OBUF)) + (portref (member codec_ctrl_in 3)) + ) + ) + (net (rename codec_ctrl_in_1_ "codec_ctrl_in[1]") (joined + (portref O (instanceref codec_ctrl_in_1_OBUF)) + (portref (member codec_ctrl_in 2)) + ) + ) + (net (rename codec_ctrl_in_2_ "codec_ctrl_in[2]") (joined + (portref O (instanceref codec_ctrl_in_2_OBUF)) + (portref (member codec_ctrl_in 1)) + ) + ) + (net (rename codec_ctrl_in_3_ "codec_ctrl_in[3]") (joined + (portref O (instanceref codec_ctrl_in_3_OBUF)) + (portref (member codec_ctrl_in 0)) + ) + ) + (net codec_sync (joined + (portref O (instanceref codec_sync_OBUF)) + (portref codec_sync) + ) + ) + (net (rename tx_tdata_10_ "tx_tdata[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + ) + ) + (net (rename tx_tdata_11_ "tx_tdata[11]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename tx_tdata_12_ "tx_tdata[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net ctrl_tlast (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref (member DIADI 15) (instanceref f0_ram_Mram_ram33)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<2>_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_2__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename tx_tdata_13_ "tx_tdata[13]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_4_)) + ) + ) + (net (rename tx_tdata_14_ "tx_tdata[14]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_5_)) + ) + ) + (net (rename tx_tdata_20_ "tx_tdata[20]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram11)) + ) + ) + (net (rename tx_tdata_15_ "tx_tdata[15]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_6_)) + ) + ) + (net (rename slave_fifo32_debug1_0_ "slave_fifo32/debug1[0]") (joined + (portref Q (instanceref slave_fifo32_debug1_0)) + (portref D (instanceref slave_fifo32_debug2_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8__rt "f1/Mcount_wr_addr_cy<8>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_8__rt)) + (portref S (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename tx_tdata_16_ "tx_tdata[16]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram9)) + ) + ) + (net (rename tx_tdata_21_ "tx_tdata[21]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_7_)) + ) + ) + (net (rename slave_fifo32_debug1_1_ "slave_fifo32/debug1[1]") (joined + (portref Q (instanceref slave_fifo32_debug1_1)) + (portref D (instanceref slave_fifo32_debug2_1)) + ) + ) + (net (rename tx_tdata_22_ "tx_tdata[22]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram12)) + ) + ) + (net (rename tx_tdata_17_ "tx_tdata[17]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram9)) + ) + ) + (net (rename f1_rd_addr_10_ "f1/rd_addr[10]") (joined + (portref Q (instanceref f1_rd_addr_10)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_8_)) + ) + ) + (net (rename slave_fifo32_debug1_2_ "slave_fifo32/debug1[2]") (joined + (portref Q (instanceref slave_fifo32_debug1_2)) + (portref D (instanceref slave_fifo32_debug2_2)) + ) + ) + (net (rename tx_tdata_23_ "tx_tdata[23]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram12)) + ) + ) + (net (rename tx_tdata_18_ "tx_tdata[18]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram10)) + ) + ) + (net (rename f1_rd_addr_11_ "f1/rd_addr[11]") (joined + (portref Q (instanceref f1_rd_addr_11)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_)) + ) + ) + (net (rename slave_fifo32_debug1_3_ "slave_fifo32/debug1[3]") (joined + (portref Q (instanceref slave_fifo32_debug1_3)) + (portref D (instanceref slave_fifo32_debug2_3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename tx_tdata_24_ "tx_tdata[24]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram13)) + ) + ) + (net (rename tx_tdata_19_ "tx_tdata[19]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram10)) + ) + ) + (net (rename f1_rd_addr_12_ "f1/rd_addr[12]") (joined + (portref Q (instanceref f1_rd_addr_12)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_debug1_4_ "slave_fifo32/debug1[4]") (joined + (portref Q (instanceref slave_fifo32_debug1_4)) + (portref D (instanceref slave_fifo32_debug2_4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename tx_tdata_30_ "tx_tdata[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename tx_tdata_25_ "tx_tdata[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_debug1_5_ "slave_fifo32/debug1[5]") (joined + (portref Q (instanceref slave_fifo32_debug1_5)) + (portref D (instanceref slave_fifo32_debug2_5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net (rename tx_tdata_31_ "tx_tdata[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename tx_tdata_26_ "tx_tdata[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_debug1_6_ "slave_fifo32/debug1[6]") (joined + (portref Q (instanceref slave_fifo32_debug1_6)) + (portref D (instanceref slave_fifo32_debug2_6)) + ) + ) + (net (rename tx_tdata_32_ "tx_tdata[32]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram17)) + ) + ) + (net (rename tx_tdata_27_ "tx_tdata[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net GPIF_CTL9_IBUF (joined + (portref RST (instanceref gen_clks_dcm_sp_inst)) + (portref I1 (instanceref reset_global_locked_OR_1_o1)) + (portref O (instanceref GPIF_CTL9_IBUF)) + ) + ) + (net (rename slave_fifo32_debug1_7_ "slave_fifo32/debug1[7]") (joined + (portref Q (instanceref slave_fifo32_debug1_7)) + (portref D (instanceref slave_fifo32_debug2_7)) + ) + ) + (net (rename tx_tdata_33_ "tx_tdata[33]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram17)) + ) + ) + (net (rename tx_tdata_28_ "tx_tdata[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_debug1_8_ "slave_fifo32/debug1[8]") (joined + (portref Q (instanceref slave_fifo32_debug1_8)) + (portref D (instanceref slave_fifo32_debug2_8)) + ) + ) + (net (rename tx_tdata_34_ "tx_tdata[34]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename tx_tdata_29_ "tx_tdata[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_debug1_9_ "slave_fifo32/debug1[9]") (joined + (portref Q (instanceref slave_fifo32_debug1_9)) + (portref D (instanceref slave_fifo32_debug2_9)) + ) + ) + (net (rename tx_tdata_40_ "tx_tdata[40]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename tx_tdata_35_ "tx_tdata[35]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename tx_tdata_41_ "tx_tdata[41]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename tx_tdata_36_ "tx_tdata[36]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename tx_tdata_42_ "tx_tdata[42]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename tx_tdata_37_ "tx_tdata[37]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/full_reg_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_full_reg_glue_set)) + ) + ) + (net (rename tx_tdata_43_ "tx_tdata[43]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename tx_tdata_38_ "tx_tdata[38]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_39_ "tx_tdata[39]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename tx_tdata_44_ "tx_tdata[44]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename tx_tdata_50_ "tx_tdata[50]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename tx_tdata_45_ "tx_tdata[45]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_10_)) + ) + ) + (net fx3_sclk_IBUF (joined + (portref I1 (instanceref cat_sclk1)) + (portref O (instanceref fx3_sclk_IBUF)) + ) + ) + (net (rename tx_tdata_51_ "tx_tdata[51]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename tx_tdata_46_ "tx_tdata[46]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[11]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<4>_FRB") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_4__FRB)) + ) + ) + (net (rename tx_tdata_52_ "tx_tdata[52]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename tx_tdata_47_ "tx_tdata[47]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[12]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<10>_FRB") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_10__FRB)) + ) + ) + (net (rename tx_tdata_53_ "tx_tdata[53]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename tx_tdata_48_ "tx_tdata[48]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[13]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename tx_tdata_54_ "tx_tdata[54]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram28)) + ) + ) + (net (rename tx_tdata_49_ "tx_tdata[49]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[14]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename tx_tdata_60_ "tx_tdata[60]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram31)) + ) + ) + (net (rename tx_tdata_55_ "tx_tdata[55]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/lines32[15]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_9_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_9_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + ) + ) + (net (rename slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o "slave_fifo32/ctrl_tx_tready_data_tx_tready_OR_55_o") (joined + (portref D (instanceref slave_fifo32_read_ready_go)) + (portref O (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + ) + ) + (net (rename tx_tdata_61_ "tx_tdata[61]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram31)) + ) + ) + (net (rename tx_tdata_56_ "tx_tdata[56]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram29)) + ) + ) + (net codec_txrx (joined + (portref O (instanceref codec_txrx_OBUF)) + (portref codec_txrx) + ) + ) + (net (rename tx_tdata_62_ "tx_tdata[62]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram32)) + ) + ) + (net (rename tx_tdata_57_ "tx_tdata[57]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram29)) + ) + ) + (net (rename tx_tdata_63_ "tx_tdata[63]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram32)) + ) + ) + (net (rename tx_tdata_58_ "tx_tdata[58]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref (member DIA 31) (instanceref f1_ram_Mram_ram30)) + ) + ) + (net (rename tx_tdata_59_ "tx_tdata[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref (member DIA 30) (instanceref f1_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_debug2_0_ "slave_fifo32/debug2[0]") (joined + (portref Q (instanceref slave_fifo32_debug2_0)) + (portref I (instanceref debug_0_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_1_ "slave_fifo32/debug2[1]") (joined + (portref Q (instanceref slave_fifo32_debug2_1)) + (portref I (instanceref debug_1_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_2_ "slave_fifo32/debug2[2]") (joined + (portref Q (instanceref slave_fifo32_debug2_2)) + (portref I (instanceref debug_2_OBUF)) + ) + ) + (net (rename f0_full_reg "f0/full_reg") (joined + (portref I1 (instanceref f0_write11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref f0_full_reg)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref D (instanceref slave_fifo32_debug1_16_BRB0)) + (portref I4 (instanceref f0_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref f0_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_debug2_3_ "slave_fifo32/debug2[3]") (joined + (portref Q (instanceref slave_fifo32_debug2_3)) + (portref I (instanceref debug_3_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_4_ "slave_fifo32/debug2[4]") (joined + (portref Q (instanceref slave_fifo32_debug2_4)) + (portref I (instanceref debug_4_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_5_ "slave_fifo32/debug2[5]") (joined + (portref Q (instanceref slave_fifo32_debug2_5)) + (portref I (instanceref debug_5_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename f1_wr_addr_0_ "f1/wr_addr[0]") (joined + (portref Q (instanceref f1_wr_addr_0)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 12) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 12) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_6_ "slave_fifo32/debug2[6]") (joined + (portref Q (instanceref slave_fifo32_debug2_6)) + (portref I (instanceref debug_6_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/write") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref wr_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_wr_addr_1_ "f1/wr_addr[1]") (joined + (portref Q (instanceref f1_wr_addr_1)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 11) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 11) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_7_ "slave_fifo32/debug2[7]") (joined + (portref Q (instanceref slave_fifo32_debug2_7)) + (portref I (instanceref debug_7_OBUF)) + ) + ) + (net (rename f1_wr_addr_2_ "f1/wr_addr[2]") (joined + (portref Q (instanceref f1_wr_addr_2)) + (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I4 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref (member ADDRAWRADDR 10) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 10) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_8_ "slave_fifo32/debug2[8]") (joined + (portref Q (instanceref slave_fifo32_debug2_8)) + (portref I (instanceref debug_8_OBUF)) + ) + ) + (net (rename f1_wr_addr_3_ "f1/wr_addr[3]") (joined + (portref Q (instanceref f1_wr_addr_3)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 9) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 9) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_9_ "slave_fifo32/debug2[9]") (joined + (portref Q (instanceref slave_fifo32_debug2_9)) + (portref I (instanceref debug_9_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename f1_wr_addr_4_ "f1/wr_addr[4]") (joined + (portref Q (instanceref f1_wr_addr_4)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 8) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 8) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210)) + (portref (member din 61) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_wr_addr_5_ "f1/wr_addr[5]") (joined + (portref Q (instanceref f1_wr_addr_5)) + (portref I5 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref I4 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref (member ADDRAWRADDR 7) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 7) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<6>_FRB") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_6__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata33)) + (portref (member din 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371)) + (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_6_ "f1/wr_addr[6]") (joined + (portref Q (instanceref f1_wr_addr_6)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 6) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 6) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<12>_FRB") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_12__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata41)) + (portref (member din 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_7_ "f1/wr_addr[7]") (joined + (portref Q (instanceref f1_wr_addr_7)) + (portref I3 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref I2 (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref (member ADDRAWRADDR 5) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 5) (instanceref f1_ram_Mram_ram1)) + ) + ) + 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) + ) + (net (rename slave_fifo32_data_rx_tdata_11_ "slave_fifo32/data_rx_tdata[11]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[31]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata251)) + (portref (member din 40) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[26]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata191)) + (portref (member din 45) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_i32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_resp/i32_tdata[29]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata221)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[28]") 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slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tlast "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tlast") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_write1)) + ) + ) + (net (rename f1_Result_9_1_FRB "f1/Result<9>1_FRB") (joined + (portref D (instanceref f1_rd_addr_9)) + (portref Q (instanceref f1_Result_9_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_9__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_16_ "slave_fifo32/data_rx_tdata[16]") (joined + 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(portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_18_ "slave_fifo32/data_rx_tdata[18]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_23_ "slave_fifo32/data_rx_tdata[23]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[10]") (joined + (portref S (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_25_ "slave_fifo32/data_rx_tdata[25]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT181)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_30_ "slave_fifo32/data_rx_tdata[30]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT241)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_26_ "slave_fifo32/data_rx_tdata[26]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_31_ "slave_fifo32/data_rx_tdata[31]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/dont_write_past_me<8>_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_dont_write_past_me_8__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT8211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_27_ "slave_fifo32/data_rx_tdata[27]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT201)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_3__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined + (portref S (instanceref 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+ (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_29_ "slave_fifo32/data_rx_tdata[29]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n012121") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0121211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_0_ "f1/Mcount_rd_addr_cy[0]") (joined + (portref O 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_1_ "f1/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg_glue_set_lut1") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_cy1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + ) + ) + (net (rename slave_fifo32_fifoadr_0_ "slave_fifo32/fifoadr[0]") (joined + (portref Q (instanceref slave_fifo32_fifoadr_0)) + (portref I (instanceref GPIF_CTL12_OBUF)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2_ "f1/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_7__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/GND_50_o_read_OR_57_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifoadr_1_ "slave_fifo32/fifoadr[1]") (joined + (portref Q (instanceref slave_fifo32_fifoadr_1)) + (portref I (instanceref GPIF_CTL11_OBUF)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3_ "f1/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata210)) + ) + ) + (net (rename f0_rd_addr_0_ "f0/rd_addr[0]") (joined + (portref Q (instanceref f0_rd_addr_0)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 12) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4_ "f1/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata310)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f0_rd_addr_1_ "f0/rd_addr[1]") (joined + (portref Q (instanceref f0_rd_addr_1)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 11) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/read_state_FSM_FFd2_BRB5") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5_ "f1/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata410)) + ) + ) + (net (rename f0_rd_addr_2_ "f0/rd_addr[2]") (joined + (portref Q (instanceref f0_rd_addr_2)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_6_ "f1/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata510)) + ) + ) + (net (rename f0_rd_addr_3_ "f0/rd_addr[3]") (joined + (portref Q (instanceref f0_rd_addr_3)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7_ "f1/Mcount_rd_addr_cy[7]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net codec_enable (joined + (portref O (instanceref codec_enable_OBUF)) + (portref codec_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata65)) + ) + ) + (net (rename f0_rd_addr_4_ "f0/rd_addr[4]") (joined + (portref Q (instanceref f0_rd_addr_4)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tlast "slave_fifo32/fifo64_to_gpmc32_tx/o32_tlast") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state_glue_set)) + (portref (member DOBDO 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_write1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8_ "f1/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_20_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[20]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[15]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata71)) + ) + ) + (net (rename f1_dont_write_past_me_1__FRB "f1/dont_write_past_me<1>_FRB") (joined + (portref I3 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f1_dont_write_past_me_1__FRB)) + ) + ) + (net (rename f0_rd_addr_5_ "f0/rd_addr[5]") (joined + (portref Q (instanceref f0_rd_addr_5)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_9_ "f1/Mcount_rd_addr_cy[9]") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[21]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_16_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[16]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata81)) + ) + ) + (net (rename f0_rd_addr_6_ "f0/rd_addr[6]") (joined + (portref Q (instanceref f0_rd_addr_6)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/_n0123_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_22_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata91)) + ) + ) + (net (rename f0_Result_11_2_FRB "f0/Result<11>2_FRB") (joined + (portref D (instanceref f0_wr_addr_11)) + (portref Q (instanceref f0_Result_11_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_11__rt)) + ) + ) + (net (rename f0_rd_addr_7_ "f0/rd_addr[7]") (joined + (portref Q (instanceref f0_rd_addr_7)) + (portref I2 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref f1__n0161_inv1_lut)) + (portref I1 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portref I1 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref f1_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_23_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[23]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata161)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[18]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata101)) + ) + ) + (net (rename f0_rd_addr_8_ "f0/rd_addr[8]") (joined + (portref Q (instanceref f0_rd_addr_8)) + (portref I4 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_24_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[24]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata171)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_19_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[19]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata111)) + ) + ) + (net (rename f0_rd_addr_9_ "f0/rd_addr[9]") (joined + (portref Q (instanceref f0_rd_addr_9)) + (portref I0 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[30]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata241)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[25]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata181)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata251)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata191)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[27]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata201)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_32_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[32]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata261)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt)) + ) + ) + (net (rename f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "f0/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename f1_Result_7_2_FRB "f1/Result<7>2_FRB") (joined + (portref D (instanceref f1_wr_addr_7)) + (portref Q (instanceref f1_Result_7_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_33_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[33]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata271)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[28]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/i_tvalid_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_write1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata221)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_34_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata281)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_40_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_35_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata291)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_2__rt "f1/Mcount_rd_addr_cy<2>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_2__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_1__rt "f1/Msub_dont_write_past_me_cy<1>_rt") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_1__rt)) + (portref S (instanceref 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(portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_37_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_42_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata371)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[4]") (joined + (portref Q (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata381)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_10_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[10]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref (member dout 61) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_full_reg_glue_set "f0/full_reg_glue_set") (joined + (portref D (instanceref f0_full_reg)) + (portref O (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_11_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_11_BRB1") (joined + (portref Q (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_44_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata391)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_11_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[11]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[53]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_20_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[20]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + (portref (member dout 51) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_15_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[15]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8)) + (portref (member dout 56) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename 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slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_5)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata311)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_29_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[29]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + (portref (member dout 42) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_becoming_full "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/becoming_full") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[9]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename f1_write "f1/write") (joined + (portref CE (instanceref f1_wr_addr_1)) + (portref CE (instanceref f1_wr_addr_2)) + (portref CE (instanceref f1_wr_addr_3)) + (portref CE (instanceref f1_wr_addr_4)) + (portref CE (instanceref f1_wr_addr_5)) + (portref CE (instanceref f1_wr_addr_6)) + (portref CE (instanceref f1_wr_addr_7)) + (portref CE (instanceref f1_wr_addr_8)) + (portref CE (instanceref f1_wr_addr_9)) + (portref CE (instanceref f1_wr_addr_10)) + (portref CE (instanceref f1_wr_addr_11)) + (portref CE (instanceref f1_wr_addr_12)) + (portref CE (instanceref f1_wr_addr_0)) + (portref O (instanceref f1_write11)) + (portref CE (instanceref f1_Result_0_2_FRB)) + (portref CE (instanceref f1_Result_1_2_FRB)) + (portref CE (instanceref f1_Result_2_2_FRB)) + (portref CE (instanceref f1_Result_3_2_FRB)) + (portref CE (instanceref f1_Result_4_2_FRB)) + (portref CE (instanceref f1_Result_5_2_FRB)) + (portref CE (instanceref f1_Result_6_2_FRB)) + (portref CE (instanceref f1_Result_7_2_FRB)) + (portref CE (instanceref f1_Result_8_2_FRB)) + (portref CE (instanceref f1_Result_9_2_FRB)) + (portref CE (instanceref f1_Result_10_2_FRB)) + (portref CE (instanceref f1_Result_11_2_FRB)) + (portref CE (instanceref f1_Result_12_2_FRB)) + (portref (member WEAWEL 1) (instanceref f1_ram_Mram_ram33)) + (portref (member WEAWEL 0) (instanceref f1_ram_Mram_ram33)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram31)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram30)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram32)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram28)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram27)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram29)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram25)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram24)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram26)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram22)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram21)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram23)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram19)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram18)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram20)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram16)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram15)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram17)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram14)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram13)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram12)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram11)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram9)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram8)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram10)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram6)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram5)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram7)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram3)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram2)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram4)) + (portref (member WEA 3) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref f1_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_13_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_13_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_8__rt "f0/Mcount_rd_addr_cy<8>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_8__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename f0_Result_0_2_FRB "f0/Result<0>2_FRB") (joined + (portref D (instanceref f0_wr_addr_0)) + (portref Q (instanceref f0_Result_0_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename f0_dont_write_past_me_3__FRB "f0/dont_write_past_me<3>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref f0_dont_write_past_me_3__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_5__FRB "f1/dont_write_past_me<5>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref Q (instanceref f1_dont_write_past_me_5__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename f0_GND_14_o_read_OR_37_o "f0/GND_14_o_read_OR_37_o") (joined + (portref O (instanceref f0_GND_14_o_read_OR_37_o1)) + (portref ENBRDEN (instanceref f0_ram_Mram_ram33)) + (portref ENB (instanceref f0_ram_Mram_ram31)) + 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+ ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr2") (joined + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + ) + ) + (net (rename f1_Mcount_wr_addr_lut_0_ "f1/Mcount_wr_addr_lut[0]") (joined + (portref S (instanceref f1_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_0_)) + (portref O (instanceref f1_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I5 (instanceref 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(joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0076_inv") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In_bdd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In_bdd1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01212211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net rx_bandsel_c_OBUF (joined + (portref G (instanceref XST_GND)) + (portref D (instanceref bus_sync_reset_int)) + (portref D (instanceref gpif_sync_reset_int)) + (portref D1 (instanceref ODDR2_ifclk)) + (portref R (instanceref ODDR2_ifclk)) + (portref S (instanceref ODDR2_ifclk)) + (portref D1 (instanceref ODDR2_ifclk_dbg)) + (portref R (instanceref ODDR2_ifclk_dbg)) + (portref S (instanceref ODDR2_ifclk_dbg)) + (portref DSSEN (instanceref gen_clks_dcm_sp_inst)) + (portref PSCLK (instanceref gen_clks_dcm_sp_inst)) + (portref PSEN (instanceref gen_clks_dcm_sp_inst)) + (portref PSINCDEC (instanceref gen_clks_dcm_sp_inst)) + (portref D0 (instanceref catgen_gen_pins_0__oddr2)) + (portref D1 (instanceref catgen_gen_pins_0__oddr2)) + (portref R (instanceref catgen_gen_pins_0__oddr2)) + (portref S (instanceref catgen_gen_pins_0__oddr2)) + (portref D0 (instanceref catgen_gen_pins_1__oddr2)) + (portref D1 (instanceref catgen_gen_pins_1__oddr2)) + (portref R (instanceref catgen_gen_pins_1__oddr2)) + (portref S (instanceref catgen_gen_pins_1__oddr2)) + (portref D0 (instanceref catgen_gen_pins_2__oddr2)) + (portref D1 (instanceref catgen_gen_pins_2__oddr2)) + (portref R (instanceref catgen_gen_pins_2__oddr2)) + (portref S (instanceref catgen_gen_pins_2__oddr2)) + (portref D0 (instanceref catgen_gen_pins_3__oddr2)) + (portref D1 (instanceref catgen_gen_pins_3__oddr2)) + (portref R (instanceref catgen_gen_pins_3__oddr2)) + (portref S (instanceref catgen_gen_pins_3__oddr2)) + (portref D0 (instanceref catgen_gen_pins_4__oddr2)) + (portref D1 (instanceref catgen_gen_pins_4__oddr2)) + (portref R (instanceref catgen_gen_pins_4__oddr2)) + (portref S (instanceref catgen_gen_pins_4__oddr2)) + (portref D0 (instanceref catgen_gen_pins_5__oddr2)) + (portref D1 (instanceref catgen_gen_pins_5__oddr2)) + (portref R (instanceref catgen_gen_pins_5__oddr2)) + (portref S (instanceref catgen_gen_pins_5__oddr2)) + (portref D0 (instanceref catgen_gen_pins_6__oddr2)) + (portref D1 (instanceref catgen_gen_pins_6__oddr2)) + (portref R (instanceref catgen_gen_pins_6__oddr2)) + (portref S (instanceref catgen_gen_pins_6__oddr2)) + (portref D0 (instanceref catgen_gen_pins_7__oddr2)) + (portref D1 (instanceref catgen_gen_pins_7__oddr2)) + (portref R (instanceref catgen_gen_pins_7__oddr2)) + (portref S (instanceref catgen_gen_pins_7__oddr2)) + (portref D0 (instanceref catgen_gen_pins_8__oddr2)) + (portref D1 (instanceref catgen_gen_pins_8__oddr2)) + (portref R (instanceref catgen_gen_pins_8__oddr2)) + (portref S (instanceref catgen_gen_pins_8__oddr2)) + (portref D0 (instanceref catgen_gen_pins_9__oddr2)) + (portref D1 (instanceref catgen_gen_pins_9__oddr2)) + (portref R (instanceref catgen_gen_pins_9__oddr2)) + (portref S (instanceref catgen_gen_pins_9__oddr2)) + (portref D0 (instanceref catgen_gen_pins_10__oddr2)) + (portref D1 (instanceref catgen_gen_pins_10__oddr2)) + (portref R (instanceref catgen_gen_pins_10__oddr2)) + (portref S (instanceref catgen_gen_pins_10__oddr2)) + (portref D0 (instanceref catgen_gen_pins_11__oddr2)) + (portref D1 (instanceref catgen_gen_pins_11__oddr2)) + (portref R (instanceref catgen_gen_pins_11__oddr2)) + (portref S (instanceref catgen_gen_pins_11__oddr2)) + (portref D0 (instanceref catgen_oddr2_frame)) + (portref D1 (instanceref catgen_oddr2_frame)) + (portref R (instanceref catgen_oddr2_frame)) + (portref S (instanceref catgen_oddr2_frame)) + (portref D1 (instanceref catgen_oddr2_clk)) + (portref R (instanceref catgen_oddr2_clk)) + (portref S (instanceref catgen_oddr2_clk)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_11_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref DI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + (portref DI (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref REGCEBREGCE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref RSTBRST (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member WEBWEU 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member WEBWEU 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member DIPB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member DIA 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIB 16) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPA 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member DIPB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref RSTA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref RSTB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member WEB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref REGCEA (instanceref f1_ram_Mram_ram33)) + (portref REGCEBREGCE (instanceref f1_ram_Mram_ram33)) + (portref RSTA (instanceref f1_ram_Mram_ram33)) + (portref RSTBRST (instanceref f1_ram_Mram_ram33)) + (portref (member WEBWEU 1) (instanceref f1_ram_Mram_ram33)) + (portref (member WEBWEU 0) (instanceref f1_ram_Mram_ram33)) + (portref REGCEA (instanceref f1_ram_Mram_ram31)) + (portref REGCEB (instanceref f1_ram_Mram_ram31)) + (portref RSTA (instanceref f1_ram_Mram_ram31)) + (portref RSTB (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram31)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram31)) + (portref REGCEA (instanceref f1_ram_Mram_ram30)) + (portref REGCEB (instanceref f1_ram_Mram_ram30)) + (portref RSTA (instanceref f1_ram_Mram_ram30)) + (portref RSTB (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram30)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram30)) + (portref REGCEA (instanceref f1_ram_Mram_ram32)) + (portref REGCEB (instanceref f1_ram_Mram_ram32)) + (portref RSTA (instanceref f1_ram_Mram_ram32)) + (portref RSTB (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram32)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram32)) + (portref REGCEA (instanceref f1_ram_Mram_ram28)) + (portref REGCEB (instanceref f1_ram_Mram_ram28)) + (portref RSTA (instanceref f1_ram_Mram_ram28)) + (portref RSTB (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram28)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram28)) + (portref REGCEA (instanceref f1_ram_Mram_ram27)) + (portref REGCEB (instanceref f1_ram_Mram_ram27)) + (portref RSTA (instanceref f1_ram_Mram_ram27)) + (portref RSTB (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram27)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram27)) + (portref REGCEA (instanceref f1_ram_Mram_ram29)) + (portref REGCEB (instanceref f1_ram_Mram_ram29)) + (portref RSTA (instanceref f1_ram_Mram_ram29)) + (portref RSTB (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram29)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram29)) + (portref REGCEA (instanceref f1_ram_Mram_ram25)) + (portref REGCEB (instanceref f1_ram_Mram_ram25)) + (portref RSTA (instanceref f1_ram_Mram_ram25)) + (portref RSTB (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram25)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram25)) + (portref REGCEA (instanceref f1_ram_Mram_ram24)) + (portref REGCEB (instanceref f1_ram_Mram_ram24)) + (portref RSTA (instanceref f1_ram_Mram_ram24)) + (portref RSTB (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram24)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram24)) + (portref REGCEA (instanceref f1_ram_Mram_ram26)) + (portref REGCEB (instanceref f1_ram_Mram_ram26)) + (portref RSTA (instanceref f1_ram_Mram_ram26)) + (portref RSTB (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram26)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram26)) + (portref REGCEA (instanceref f1_ram_Mram_ram22)) + (portref REGCEB (instanceref f1_ram_Mram_ram22)) + (portref RSTA (instanceref f1_ram_Mram_ram22)) + (portref RSTB (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram22)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram22)) + (portref REGCEA (instanceref f1_ram_Mram_ram21)) + (portref REGCEB (instanceref f1_ram_Mram_ram21)) + (portref RSTA (instanceref f1_ram_Mram_ram21)) + (portref RSTB (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram21)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram21)) + (portref REGCEA (instanceref f1_ram_Mram_ram23)) + (portref REGCEB (instanceref f1_ram_Mram_ram23)) + (portref RSTA (instanceref f1_ram_Mram_ram23)) + (portref RSTB (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram23)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram23)) + (portref REGCEA (instanceref f1_ram_Mram_ram19)) + (portref REGCEB (instanceref f1_ram_Mram_ram19)) + (portref RSTA (instanceref f1_ram_Mram_ram19)) + (portref RSTB (instanceref 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f1_ram_Mram_ram20)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram20)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram20)) + (portref REGCEA (instanceref f1_ram_Mram_ram16)) + (portref REGCEB (instanceref f1_ram_Mram_ram16)) + (portref RSTA (instanceref f1_ram_Mram_ram16)) + (portref RSTB (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram16)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram16)) + (portref REGCEA (instanceref f1_ram_Mram_ram15)) + (portref REGCEB (instanceref f1_ram_Mram_ram15)) + (portref RSTA (instanceref f1_ram_Mram_ram15)) + (portref RSTB (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram15)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram15)) + (portref REGCEA (instanceref f1_ram_Mram_ram17)) + (portref REGCEB (instanceref f1_ram_Mram_ram17)) + (portref RSTA (instanceref f1_ram_Mram_ram17)) + (portref RSTB (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram17)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram17)) + (portref REGCEA (instanceref f1_ram_Mram_ram14)) + (portref REGCEB (instanceref f1_ram_Mram_ram14)) + (portref RSTA (instanceref f1_ram_Mram_ram14)) + (portref RSTB (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram14)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram14)) + (portref REGCEA (instanceref f1_ram_Mram_ram13)) + (portref REGCEB (instanceref f1_ram_Mram_ram13)) + (portref RSTA (instanceref f1_ram_Mram_ram13)) + (portref RSTB (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram13)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram13)) + (portref REGCEA (instanceref f1_ram_Mram_ram12)) + (portref REGCEB (instanceref f1_ram_Mram_ram12)) + (portref RSTA (instanceref f1_ram_Mram_ram12)) + (portref RSTB (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram12)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram12)) + (portref REGCEA (instanceref f1_ram_Mram_ram11)) + (portref REGCEB (instanceref f1_ram_Mram_ram11)) + (portref RSTA (instanceref f1_ram_Mram_ram11)) + (portref RSTB (instanceref f1_ram_Mram_ram11)) + (portref (member WEB 3) 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(portref REGCEB (instanceref f1_ram_Mram_ram5)) + (portref RSTA (instanceref f1_ram_Mram_ram5)) + (portref RSTB (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram5)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram5)) + (portref REGCEA (instanceref f1_ram_Mram_ram7)) + (portref REGCEB (instanceref f1_ram_Mram_ram7)) + (portref RSTA (instanceref f1_ram_Mram_ram7)) + (portref RSTB (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram7)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram7)) + (portref REGCEA (instanceref f1_ram_Mram_ram3)) + (portref REGCEB (instanceref f1_ram_Mram_ram3)) + (portref RSTA (instanceref f1_ram_Mram_ram3)) + (portref RSTB (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram3)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram3)) + (portref REGCEA (instanceref f1_ram_Mram_ram2)) + (portref REGCEB (instanceref f1_ram_Mram_ram2)) + (portref RSTA (instanceref f1_ram_Mram_ram2)) + (portref RSTB (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 1) (instanceref f1_ram_Mram_ram2)) + (portref (member WEB 0) (instanceref f1_ram_Mram_ram2)) + (portref REGCEA (instanceref f1_ram_Mram_ram4)) + (portref REGCEB (instanceref f1_ram_Mram_ram4)) + (portref RSTA (instanceref f1_ram_Mram_ram4)) + (portref RSTB (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 3) (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 2) (instanceref f1_ram_Mram_ram4)) + (portref (member WEB 1) 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slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 36) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 37) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref (member din 38) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full61") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full611)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full62") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01219)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full621)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o81)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01217)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net fx3_miso_OBUF (joined + (portref O (instanceref fx3_miso1)) + (portref I (instanceref fx3_miso_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename f0_dont_write_past_me_7__FRB "f0/dont_write_past_me<7>_FRB") (joined + (portref I3 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref f0_dont_write_past_me_7__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_9__FRB "f1/dont_write_past_me<9>_FRB") (joined + (portref I1 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_9__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n0146_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3210 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3210") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3211 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3212 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_12_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3213 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3214 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_14)) + ) + ) + (net (rename slave_fifo32_wr_one "slave_fifo32/wr_one") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref Q (instanceref slave_fifo32_wr_one)) + (portref I0 (instanceref slave_fifo32_wr_one_rstpot)) + (portref I0 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines3215 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines3215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_15)) + ) + ) + (net (rename slave_fifo32_sloe_1 "slave_fifo32/sloe_1") (joined + (portref I (instanceref GPIF_CTL2_OBUF)) + (portref Q (instanceref slave_fifo32_sloe_1)) + ) + ) + (net (rename slave_fifo32_sloe_2 "slave_fifo32/sloe_2") (joined + (portref Q (instanceref slave_fifo32_sloe_2)) + (portref T (instanceref GPIF_D_0_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_3 "slave_fifo32/sloe_3") (joined + (portref Q (instanceref slave_fifo32_sloe_3)) + (portref T (instanceref GPIF_D_1_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_4 "slave_fifo32/sloe_4") (joined + (portref Q (instanceref slave_fifo32_sloe_4)) + (portref T (instanceref GPIF_D_2_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_5 "slave_fifo32/sloe_5") (joined + (portref Q (instanceref slave_fifo32_sloe_5)) + (portref T (instanceref GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_6 "slave_fifo32/sloe_6") (joined + (portref Q (instanceref slave_fifo32_sloe_6)) + (portref T (instanceref GPIF_D_4_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_7 "slave_fifo32/sloe_7") (joined + (portref Q (instanceref slave_fifo32_sloe_7)) + (portref T (instanceref GPIF_D_5_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_8 "slave_fifo32/sloe_8") (joined + (portref Q (instanceref slave_fifo32_sloe_8)) + (portref T (instanceref GPIF_D_6_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_9 "slave_fifo32/sloe_9") (joined + (portref Q (instanceref slave_fifo32_sloe_9)) + (portref T (instanceref GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_empty "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/empty") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref empty (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename GPIF_D_10_ "GPIF_D[10]") (joined + (portref IO (instanceref GPIF_D_10_IOBUF)) + (portref (member GPIF_D 21)) + ) + ) + (net (rename GPIF_D_11_ "GPIF_D[11]") (joined + (portref IO (instanceref GPIF_D_11_IOBUF)) + (portref (member GPIF_D 20)) + ) + ) + (net pll_ce (joined + (portref O (instanceref pll_ce_OBUF)) + (portref pll_ce) + ) + ) + (net (rename GPIF_D_12_ "GPIF_D[12]") (joined + (portref IO (instanceref GPIF_D_12_IOBUF)) + (portref (member GPIF_D 19)) + ) + ) + (net (rename GPIF_D_13_ "GPIF_D[13]") (joined + (portref IO (instanceref GPIF_D_13_IOBUF)) + (portref (member GPIF_D 18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/becoming_full102") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_becoming_full1021)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net (rename GPIF_D_14_ "GPIF_D[14]") (joined + (portref IO (instanceref GPIF_D_14_IOBUF)) + (portref (member GPIF_D 17)) + ) + ) + (net N10 (joined + (portref O (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I3 (instanceref slave_fifo32__n0279_inv)) + ) + ) + (net (rename GPIF_D_20_ "GPIF_D[20]") (joined + (portref IO (instanceref GPIF_D_20_IOBUF)) + (portref (member GPIF_D 11)) + ) + ) + (net (rename GPIF_D_15_ "GPIF_D[15]") (joined + (portref IO (instanceref GPIF_D_15_IOBUF)) + (portref (member GPIF_D 16)) + ) + ) + (net N14 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + ) + ) + (net cat_miso (joined + (portref I (instanceref cat_miso_IBUF)) + (portref cat_miso) + ) + ) + (net N22 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + ) + ) + (net N18 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename GPIF_D_21_ "GPIF_D[21]") (joined + (portref IO (instanceref GPIF_D_21_IOBUF)) + (portref (member GPIF_D 10)) + ) + ) + (net (rename GPIF_D_16_ "GPIF_D[16]") (joined + (portref IO (instanceref GPIF_D_16_IOBUF)) + (portref (member GPIF_D 15)) + ) + ) + (net N24 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1)) + ) + ) + (net LED_RX1 (joined + (portref O (instanceref LED_RX1_OBUF)) + (portref LED_RX1) + ) + ) + (net N30 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + ) + ) + (net LED_RX2 (joined + (portref O (instanceref LED_RX2_OBUF)) + (portref LED_RX2) + ) + ) + (net N26 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_i_tvalid_int1)) + ) + ) + (net (rename GPIF_D_22_ "GPIF_D[22]") (joined + (portref IO (instanceref GPIF_D_22_IOBUF)) + (portref (member GPIF_D 9)) + ) + ) + (net (rename GPIF_D_17_ "GPIF_D[17]") (joined + (portref IO (instanceref GPIF_D_17_IOBUF)) + (portref (member GPIF_D 14)) + ) + ) + (net N34 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net N40 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + ) + ) + (net N42 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + ) + ) + (net N38 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0)) + ) + ) + (net (rename GPIF_D_23_ "GPIF_D[23]") (joined + (portref IO (instanceref GPIF_D_23_IOBUF)) + (portref (member GPIF_D 8)) + ) + ) + (net (rename GPIF_D_18_ "GPIF_D[18]") (joined + (portref IO (instanceref GPIF_D_18_IOBUF)) + (portref (member GPIF_D 13)) + ) + ) + (net N50 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + ) + ) + (net N52 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + ) + ) + (net (rename GPIF_D_24_ "GPIF_D[24]") (joined + (portref IO (instanceref GPIF_D_24_IOBUF)) + (portref (member GPIF_D 7)) + ) + ) + (net (rename GPIF_D_19_ "GPIF_D[19]") (joined + (portref IO (instanceref GPIF_D_19_IOBUF)) + (portref (member GPIF_D 12)) + ) + ) + (net N54 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + ) + ) + (net N60 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + ) + ) + (net N56 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + ) + ) + (net N62 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + ) + ) + (net N58 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_4__rt "f0/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename GPIF_D_30_ "GPIF_D[30]") (joined + (portref IO (instanceref GPIF_D_30_IOBUF)) + (portref (member GPIF_D 1)) + ) + ) + (net (rename GPIF_D_25_ "GPIF_D[25]") (joined + (portref IO (instanceref GPIF_D_25_IOBUF)) + (portref (member GPIF_D 6)) + ) + ) + (net N64 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net N66 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename f0_dont_write_past_me_9__FRB "f0/dont_write_past_me<9>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f0_dont_write_past_me_9__FRB)) + ) + ) + (net (rename GPIF_D_31_ "GPIF_D[31]") (joined + (portref IO (instanceref GPIF_D_31_IOBUF)) + (portref (member GPIF_D 0)) + ) + ) + (net (rename GPIF_D_26_ "GPIF_D[26]") (joined + (portref IO (instanceref GPIF_D_26_IOBUF)) + (portref (member GPIF_D 5)) + ) + ) + (net (rename f1_read_state_FSM_FFd1 "f1/read_state_FSM_FFd1") (joined + (portref Q (instanceref f1_read_state_FSM_FFd1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I1 (instanceref f1__n0161_inv1_lut)) + (portref I1 (instanceref f1__n0161_inv1_lut1)) + (portref I0 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_write1)) + (portref I0 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + (portref I0 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I3 (instanceref f1_full_reg_glue_set)) + ) + ) + (net N80 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + ) + ) + (net (rename f1_read_state_FSM_FFd2 "f1/read_state_FSM_FFd2") (joined + (portref Q (instanceref f1_read_state_FSM_FFd2)) + (portref I0 (instanceref f1__n0161_inv1_lut1)) + (portref I2 (instanceref f1_GND_14_o_read_OR_37_o1)) + (portref I3 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net N76 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + ) + ) + (net N82 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + ) + ) + (net N78 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + ) + ) + (net (rename GPIF_D_27_ "GPIF_D[27]") (joined + (portref IO (instanceref GPIF_D_27_IOBUF)) + (portref (member GPIF_D 4)) + ) + ) + (net N84 (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + ) + ) + (net N90 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N86 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + ) + ) + (net debug_clk_1_OBUF (joined + (portref Q (instanceref ODDR2_ifclk_dbg)) + (portref I (instanceref debug_clk_1_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net N88 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tlast1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + ) + ) + (net (rename GPIF_D_28_ "GPIF_D[28]") (joined + (portref IO (instanceref GPIF_D_28_IOBUF)) + (portref (member GPIF_D 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012111") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0121111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + ) + ) + (net N96 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_31)) + (portref O (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012112") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111)) + ) + ) + (net N97 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_30)) + (portref O (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net locked (joined + (portref LOCKED (instanceref gen_clks_dcm_sp_inst)) + (portref D (instanceref slave_fifo32_debug1_21)) + (portref I0 (instanceref reset_global_locked_OR_1_o1)) + (portref I1 (instanceref slave_fifo32__n0230_inv1)) + (portref I0 (instanceref slave_fifo32__n0223_inv1)) + (portref I5 (instanceref slave_fifo32__n0237_inv1)) + (portref I0 (instanceref slave_fifo32__n0290_inv1)) + (portref I0 (instanceref slave_fifo32__n0279_inv)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd2_In1)) + (portref I1 (instanceref slave_fifo32_wr_one_rstpot)) + (portref I2 (instanceref slave_fifo32_slrd_rstpot)) + (portref I3 (instanceref slave_fifo32_sloe_1_rstpot)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) 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"GPIF_D[29]") (joined + (portref IO (instanceref GPIF_D_29_IOBUF)) + (portref (member GPIF_D 2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/_n012114") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012114)) + ) + ) + (net N99 (joined + (portref D (instanceref slave_fifo32_gpif_data_in_28)) + (portref O (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref 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f0_Mcount_rd_addr_cy_4__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr10 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr10") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_10)) + ) + ) + (net (rename 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"slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state<0>_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv4") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_EP_WMARK1_1 "slave_fifo32/EP_WMARK1_1") (joined + (portref Q (instanceref slave_fifo32_EP_WMARK1_1)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1_SW0)) + (portref I5 (instanceref slave_fifo32_slrd_rstpot)) + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net cat_mosi (joined + (portref O (instanceref cat_mosi_OBUF)) + (portref cat_mosi) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net fx3_mosi_IBUF (joined + (portref I1 (instanceref cat_mosi1)) + (portref O (instanceref fx3_mosi_IBUF)) + ) + ) + (net (rename slave_fifo32_rd_one "slave_fifo32/rd_one") (joined + (portref D (instanceref slave_fifo32_rd_one_BRB1)) + (portref O (instanceref slave_fifo32_rd_one_rstpot)) + ) + ) + (net (rename slave_fifo32_sloe_rstpot "slave_fifo32/sloe_rstpot") (joined + (portref O (instanceref slave_fifo32_sloe_rstpot)) + (portref D (instanceref slave_fifo32_sloe)) + (portref D (instanceref slave_fifo32_sloe_33)) + (portref D (instanceref slave_fifo32_sloe_32)) + (portref D (instanceref slave_fifo32_sloe_31)) + (portref D (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_xor<8>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8__rt)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_3__rt "f1/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_16)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_17)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_18)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_19)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_20)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_22)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_23)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_24)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + ) + ) + (net (rename slave_fifo32_debug1_17_BRB0 "slave_fifo32/debug1_17_BRB0") (joined + (portref Q (instanceref slave_fifo32_debug1_17_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_chk_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/chk_tready") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker__n0227_inv1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined + (portref S (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB3") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg_BRB4") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_3_ "f0/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[6]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_10_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[10]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata210)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4_ "f0/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref O (instanceref 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(portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0)) + ) + ) + (net (rename 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(rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_64_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[64]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_o_tlast1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0003_59_ "slave_fifo32/fifo64_to_gpmc32_resp/n0003[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_Mmux_o_tdata201)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/full_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_write1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[14]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_14_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_14_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[7]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[8]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net tx_bandsel_a (joined + (portref O (instanceref tx_bandsel_a_OBUF)) + (portref tx_bandsel_a) + ) + ) + (net tx_bandsel_b (joined + (portref O (instanceref tx_bandsel_b_OBUF)) + (portref tx_bandsel_b) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_10__rt "f1/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net GPIF_CTL0 (joined + (portref O (instanceref GPIF_CTL0_OBUF)) + (portref GPIF_CTL0) + ) + ) + (net GPIF_CTL1 (joined + (portref O (instanceref GPIF_CTL1_OBUF)) + (portref GPIF_CTL1) + ) + ) + (net GPIF_CTL2 (joined + (portref O (instanceref GPIF_CTL2_OBUF)) + (portref GPIF_CTL2) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net GPIF_CTL3 (joined + (portref O (instanceref GPIF_CTL3_OBUF)) + (portref GPIF_CTL3) + ) + ) + (net GPIF_CTL4 (joined + (portref I (instanceref GPIF_CTL4_IBUF)) + (portref GPIF_CTL4) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/clear_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + ) + ) + (net GPIF_CTL5 (joined + (portref I (instanceref GPIF_CTL5_IBUF)) + (portref GPIF_CTL5) + ) + ) + (net GPIF_CTL7 (joined + (portref O (instanceref GPIF_CTL7_OBUF)) + (portref GPIF_CTL7) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_0_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[0]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref D (instanceref slave_fifo32_gpif_data_out_0)) + ) + ) + (net GPIF_CTL9 (joined + (portref I (instanceref GPIF_CTL9_IBUF)) + (portref GPIF_CTL9) + ) + ) + (net (rename f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "f1/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_1_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[1]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref D (instanceref slave_fifo32_gpif_data_out_1)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_2_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[2]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231)) + (portref D (instanceref slave_fifo32_gpif_data_out_2)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_3_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[3]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref D (instanceref slave_fifo32_gpif_data_out_3)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_4_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[4]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref D (instanceref slave_fifo32_gpif_data_out_4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/GND_66_o_read_OR_144_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_5_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[5]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT281)) + (portref D (instanceref slave_fifo32_gpif_data_out_5)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_6_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[6]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT291)) + (portref D (instanceref slave_fifo32_gpif_data_out_6)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_7_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[7]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT301)) + (portref D (instanceref slave_fifo32_gpif_data_out_7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename n0035_10_ "n0035[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/_n0074_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[0]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRBRDADDR 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_8_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[8]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT311)) + (portref D (instanceref slave_fifo32_gpif_data_out_8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_11_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename n0035_11_ "n0035[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram6)) + ) + ) + (net pll_sclk (joined + (portref O (instanceref pll_sclk_OBUF)) + (portref pll_sclk) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[1]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1__rt)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref (member ADDRBRDADDR 11) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_9_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[9]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT321)) + (portref D (instanceref slave_fifo32_gpif_data_out_9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_12_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_4_)) + ) + ) + (net (rename n0035_12_ "n0035[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[2]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename n0035_13_ "n0035[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename n0035_14_ "n0035[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[4]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename n0035_20_ "n0035[20]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram11)) + ) + ) + (net (rename n0035_15_ "n0035[15]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[5]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename n0035_21_ "n0035[21]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram11)) + ) + ) + (net (rename n0035_16_ "n0035[16]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[6]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename n0035_22_ "n0035[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram12)) + ) + ) + (net (rename n0035_17_ "n0035[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename n0035_23_ "n0035[23]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram12)) + ) + ) + (net (rename n0035_18_ "n0035[18]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[8]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename n0035_19_ "n0035[19]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram10)) + ) + ) + (net (rename n0035_24_ "n0035[24]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net cat_sclk (joined + (portref O (instanceref cat_sclk_OBUF)) + (portref cat_sclk) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[9]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename n0035_25_ "n0035[25]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net (rename n0035_30_ "n0035[30]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename n0035_26_ "n0035[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename n0035_31_ "n0035[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0146_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_10__rt "f1/Mcount_wr_addr_cy<10>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_10__rt)) + (portref S (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename n0035_27_ "n0035[27]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename n0035_32_ "n0035[32]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Msub_dont_write_past_me_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net (rename n0035_28_ "n0035[28]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename n0035_33_ "n0035[33]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename n0035_29_ "n0035[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename n0035_34_ "n0035[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename f0_Result_6_1_FRB "f0/Result<6>1_FRB") (joined + (portref D (instanceref f0_rd_addr_6)) + (portref Q (instanceref f0_Result_6_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_6__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename n0035_35_ "n0035[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename n0035_40_ "n0035[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename f0_Mcount_wr_addr_lut_0_ "f0/Mcount_wr_addr_lut[0]") (joined + (portref S (instanceref f0_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_0_)) + (portref O (instanceref f0_Mcount_wr_addr_lut_0__INV_0)) + ) + ) + (net (rename n0035_36_ "n0035[36]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename n0035_41_ "n0035[41]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename n0035_37_ "n0035[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename n0035_42_ "n0035[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_tlast") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref (member DIADI 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net ext_ref_enable (joined + (portref O (instanceref ext_ref_enable_OBUF)) + (portref ext_ref_enable) + ) + ) + (net (rename f1_Mcount_rd_addr_lut_0_ "f1/Mcount_rd_addr_lut[0]") (joined + (portref S (instanceref f1_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_0_)) + (portref O (instanceref f1_Mcount_rd_addr_lut_0__INV_0)) + ) + ) + (net (rename n0035_38_ "n0035[38]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename n0035_43_ "n0035[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename n0035_44_ "n0035[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename n0035_39_ "n0035[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename n0035_50_ "n0035[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename n0035_45_ "n0035[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename f1_dont_write_past_me_10__FRB "f1/dont_write_past_me<10>_FRB") (joined + (portref I3 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_10__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd0 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd0") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net (rename n0035_51_ "n0035[51]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename n0035_46_ "n0035[46]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror_bdd6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror_bdd6") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net (rename n0035_52_ "n0035[52]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename n0035_47_ "n0035[47]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename n0035_53_ "n0035[53]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename n0035_48_ "n0035[48]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata261)) + ) + ) + (net (rename n0035_54_ "n0035[54]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename n0035_49_ "n0035[49]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1_ "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/holding[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata271)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines321 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines321") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines322 "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines322") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_2_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_lines32_2)) + ) + ) + (net (rename n0035_60_ "n0035[60]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename n0035_55_ "n0035[55]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines323 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slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + (portref I (instanceref gpif_clk_inverter)) + ) + ) + (net gpif_clk_inv (joined + (portref O (instanceref gpif_clk_inverter)) + (portref C1 (instanceref ODDR2_ifclk_dbg)) + (portref C1 (instanceref ODDR2_ifclk)) + ) + ) + (net (rename GPIF_D_6_ "GPIF_D[6]") (joined + (portref IO (instanceref GPIF_D_6_IOBUF)) + (portref (member GPIF_D 25)) + ) + ) + (net (rename ctrl_tdata_30_ "ctrl_tdata[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename ctrl_tdata_25_ "ctrl_tdata[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o "slave_fifo32/fifo64_to_gpmc32_tx/fifo32_to_fifo64/i_tvalid_o_tready_AND_73_o") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_7)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_8)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_9)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_15)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_16)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_18)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_19)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_20)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_21)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_23)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_24)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_25)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_26)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_27)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_28)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_30)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_31)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + ) + ) + (net (rename GPIF_D_7_ "GPIF_D[7]") (joined + (portref IO (instanceref GPIF_D_7_IOBUF)) + (portref (member GPIF_D 24)) + ) + ) + (net (rename ctrl_tdata_31_ "ctrl_tdata[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram16)) + ) + ) + (net (rename ctrl_tdata_26_ "ctrl_tdata[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename f1_dont_write_past_me_12__FRB "f1/dont_write_past_me<12>_FRB") (joined + (portref I1 (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref Q (instanceref f1_dont_write_past_me_12__FRB)) + ) + ) + (net (rename GPIF_D_8_ "GPIF_D[8]") (joined + (portref IO (instanceref GPIF_D_8_IOBUF)) + (portref (member GPIF_D 23)) + ) + ) + (net (rename f0_Result_4_2_FRB "f0/Result<4>2_FRB") (joined + (portref D (instanceref f0_wr_addr_4)) + (portref Q (instanceref f0_Result_4_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net reset_global_locked_OR_1_o (joined + (portref PRE (instanceref bus_sync_reset_int)) + (portref PRE (instanceref bus_sync_reset_out)) + (portref PRE (instanceref gpif_sync_reset_int)) + (portref PRE (instanceref gpif_sync_reset_out)) + (portref O (instanceref reset_global_locked_OR_1_o1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Msub_num_packets[7]_GND_55_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I3 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename ctrl_tdata_32_ "ctrl_tdata[32]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename ctrl_tdata_27_ "ctrl_tdata[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram14)) + ) + ) + (net (rename GPIF_D_9_ "GPIF_D[9]") (joined + (portref IO (instanceref GPIF_D_9_IOBUF)) + (portref (member GPIF_D 22)) + ) + ) + (net (rename ctrl_tdata_28_ "ctrl_tdata[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename ctrl_tdata_33_ "ctrl_tdata[33]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram17)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename ctrl_tdata_29_ "ctrl_tdata[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram15)) + ) + ) + (net (rename ctrl_tdata_34_ "ctrl_tdata[34]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename ctrl_tdata_35_ "ctrl_tdata[35]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram18)) + ) + ) + (net (rename ctrl_tdata_40_ "ctrl_tdata[40]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename ctrl_tdata_36_ "ctrl_tdata[36]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename ctrl_tdata_41_ "ctrl_tdata[41]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram21)) + ) + ) + (net (rename f1_Result_10_1_FRB "f1/Result<10>1_FRB") (joined + (portref D (instanceref f1_rd_addr_10)) + (portref Q (instanceref f1_Result_10_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_10__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename ctrl_tdata_37_ "ctrl_tdata[37]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram19)) + ) + ) + (net (rename ctrl_tdata_42_ "ctrl_tdata[42]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename ctrl_tdata_38_ "ctrl_tdata[38]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename ctrl_tdata_43_ "ctrl_tdata[43]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Msub_num_packets[7]_GND_65_o_sub_15_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename ctrl_tdata_39_ "ctrl_tdata[39]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram20)) + ) + ) + (net (rename ctrl_tdata_44_ "ctrl_tdata[44]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename ctrl_tdata_45_ "ctrl_tdata[45]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram23)) + ) + ) + (net (rename ctrl_tdata_50_ "ctrl_tdata[50]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/empty_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename ctrl_tdata_46_ "ctrl_tdata[46]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename ctrl_tdata_51_ "ctrl_tdata[51]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename ctrl_tdata_47_ "ctrl_tdata[47]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram24)) + ) + ) + (net (rename ctrl_tdata_52_ "ctrl_tdata[52]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_10_ "slave_fifo32/gpif_data_out[10]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_10)) + (portref I (instanceref GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename ctrl_tdata_53_ "ctrl_tdata[53]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram27)) + ) + ) + (net (rename ctrl_tdata_48_ "ctrl_tdata[48]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_11_ "slave_fifo32/gpif_data_out[11]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_11)) + (portref I (instanceref GPIF_D_11_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename ctrl_tdata_54_ "ctrl_tdata[54]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename ctrl_tdata_49_ "ctrl_tdata[49]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/state<0>_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_0__inv1_INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_12_ "slave_fifo32/gpif_data_out[12]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_12)) + (portref I (instanceref GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o "slave_fifo32/fifo64_to_gpmc32_tx/GND_49_o_space[15]_LessThan_2_o") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_i_tready)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + ) + ) + (net (rename ctrl_tdata_60_ "ctrl_tdata[60]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename ctrl_tdata_55_ "ctrl_tdata[55]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram28)) + ) + ) + (net (rename f1_Result_2_1_FRB "f1/Result<2>1_FRB") (joined + (portref D (instanceref f1_rd_addr_2)) + (portref Q (instanceref f1_Result_2_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_2__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_13_ "slave_fifo32/gpif_data_out[13]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_13)) + (portref I (instanceref GPIF_D_13_IOBUF)) + ) + ) + (net (rename ctrl_tdata_56_ "ctrl_tdata[56]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram29)) + ) + ) + (net (rename ctrl_tdata_61_ "ctrl_tdata[61]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram31)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_14_ "slave_fifo32/gpif_data_out[14]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_14)) + (portref I (instanceref GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename ctrl_tdata_62_ "ctrl_tdata[62]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_57_ "ctrl_tdata[57]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram29)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_20_ "slave_fifo32/gpif_data_out[20]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_20)) + (portref I (instanceref GPIF_D_20_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_15_ "slave_fifo32/gpif_data_out[15]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_15)) + (portref I (instanceref GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net (rename ctrl_tdata_63_ "ctrl_tdata[63]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram32)) + ) + ) + (net (rename ctrl_tdata_58_ "ctrl_tdata[58]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref (member DIA 31) (instanceref f0_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/rd_addr[9]_wr_addr[9]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_16_ "slave_fifo32/gpif_data_out[16]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_16)) + (portref I (instanceref GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_21_ "slave_fifo32/gpif_data_out[21]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_21)) + (portref I (instanceref GPIF_D_21_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename ctrl_tdata_59_ "ctrl_tdata[59]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref (member DIA 30) (instanceref f0_ram_Mram_ram30)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_22_ "slave_fifo32/gpif_data_out[22]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_22)) + (portref I (instanceref GPIF_D_22_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_17_ "slave_fifo32/gpif_data_out[17]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_17)) + (portref I (instanceref GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_23_ "slave_fifo32/gpif_data_out[23]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_23)) + (portref I (instanceref GPIF_D_23_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_18_ "slave_fifo32/gpif_data_out[18]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_18)) + (portref I (instanceref GPIF_D_18_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_24_ "slave_fifo32/gpif_data_out[24]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_24)) + (portref I (instanceref GPIF_D_24_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_19_ "slave_fifo32/gpif_data_out[19]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_19)) + (portref I (instanceref GPIF_D_19_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_8__rt)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_30_ "slave_fifo32/gpif_data_out[30]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_30)) + (portref I (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_25_ "slave_fifo32/gpif_data_out[25]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_25)) + (portref I (instanceref GPIF_D_25_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready "slave_fifo32/fifo64_to_gpmc32_ctrl/i_tready") (joined + (portref D (instanceref slave_fifo32_debug1_18)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_i_tready)) + (portref I3 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_31_ "slave_fifo32/gpif_data_out[31]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_31)) + (portref I (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_26_ "slave_fifo32/gpif_data_out[26]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_26)) + (portref I (instanceref GPIF_D_26_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/Mcount_space_xor<3>11") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_4_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_27_ "slave_fifo32/gpif_data_out[27]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_27)) + (portref I (instanceref GPIF_D_27_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_4__rt "f1/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_28_ "slave_fifo32/gpif_data_out[28]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_28)) + (portref I (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_29_ "slave_fifo32/gpif_data_out[29]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_29)) + (portref I (instanceref GPIF_D_29_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr8_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr8_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_8__rt)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_0_ "f1/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_1_ "f1/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_2_ "f1/Mcompar_becoming_full_lut[2]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_2_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_0_ "slave_fifo32/data_rx_tdata[0]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_3_ "f1/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_1_ "slave_fifo32/data_rx_tdata[1]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_Mcompar_becoming_full_lut_4_ "f1/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref f1_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_2_ "slave_fifo32/data_rx_tdata[2]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT231)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_EP_WMARK "slave_fifo32/EP_WMARK") (joined + (portref Q (instanceref slave_fifo32_EP_WMARK)) + (portref D (instanceref slave_fifo32_EP_WMARK1)) + (portref D (instanceref slave_fifo32_EP_WMARK1_1)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_3_ "slave_fifo32/data_rx_tdata[3]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT261)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_4_ "slave_fifo32/data_rx_tdata[4]") (joined + (portref I1 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT271)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_10_ "f0/Mcount_rd_addr_cy[10]") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_10_)) + (portref CI (instanceref f0_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_data_rx_tdata_5_ "slave_fifo32/data_rx_tdata[5]") (joined + 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(rename slave_fifo32_fifoadr_0_1 "slave_fifo32/fifoadr_0_1") (joined + (portref Q (instanceref slave_fifo32_fifoadr_0_1)) + (portref D (instanceref slave_fifo32_debug1_26)) + (portref I1 (instanceref slave_fifo32_Mcount_fifoadr_xor_1_11)) + (portref I0 (instanceref slave_fifo32_ctrl_tx_tready_data_tx_tready_OR_55_o1)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT110)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT111)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT121)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT131)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT141)) + (portref I3 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151)) + (portref I3 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata431)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[21]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_21)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata491)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2_1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + ) + ) + (net (rename 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f1_ram_Mram_ram13)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 12) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[30]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_30)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata591)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[25]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_25)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata531)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_1_ "slave_fifo32/gpif_data_out[1]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_1)) + (portref I (instanceref GPIF_D_1_IOBUF)) + ) + ) + (net (rename f1_rd_addr_1_ "f1/rd_addr[1]") (joined + (portref Q (instanceref f1_rd_addr_1)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 11) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 11) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[31]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata601)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[26]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_26)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata541)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_2_ "slave_fifo32/gpif_data_out[2]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_2)) + (portref I (instanceref GPIF_D_2_IOBUF)) + ) + ) + (net (rename f1_rd_addr_2_ "f1/rd_addr[2]") (joined + (portref Q (instanceref f1_rd_addr_2)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref (member ADDRBRDADDR 10) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 10) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[27]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_27)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata551)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_3_ "slave_fifo32/gpif_data_out[3]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_3)) + (portref I (instanceref GPIF_D_3_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0__rt)) + ) + ) + (net (rename f1_rd_addr_3_ "f1/rd_addr[3]") (joined + (portref Q (instanceref f1_rd_addr_3)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 9) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 9) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[28]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_28)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tvalid "slave_fifo32/ctrl_rx_tvalid") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref I2 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_eof_Mux_22_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o1)) + (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In2)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_4_ "slave_fifo32/gpif_data_out[4]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_4)) + (portref I (instanceref GPIF_D_4_IOBUF)) + ) + ) + (net (rename f1_rd_addr_4_ "f1/rd_addr[4]") (joined + (portref Q (instanceref f1_rd_addr_4)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 8) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 8) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/fifo32_to_fifo64/holding[29]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_29)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata581)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_5_ "slave_fifo32/gpif_data_out[5]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_5)) + (portref I (instanceref GPIF_D_5_IOBUF)) + ) + ) + (net (rename f1_rd_addr_5_ "f1/rd_addr[5]") (joined + (portref Q (instanceref f1_rd_addr_5)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref (member ADDRBRDADDR 7) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 7) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_6_ "slave_fifo32/gpif_data_out[6]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_6)) + (portref I (instanceref GPIF_D_6_IOBUF)) + ) + ) + (net (rename f1_rd_addr_6_ "f1/rd_addr[6]") (joined + (portref Q (instanceref f1_rd_addr_6)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 6) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 6) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_7_ "slave_fifo32/gpif_data_out[7]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_7)) + (portref I (instanceref GPIF_D_7_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/full_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename f1_rd_addr_7_ "f1/rd_addr[7]") (joined + (portref Q (instanceref f1_rd_addr_7)) + (portref I2 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 5) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 5) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_8_ "slave_fifo32/gpif_data_out[8]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_8)) + (portref I (instanceref GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_9_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + ) + ) + (net (rename f1_rd_addr_8_ "f1/rd_addr[8]") (joined + (portref Q (instanceref f1_rd_addr_8)) + (portref I4 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref (member ADDRBRDADDR 4) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 4) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_9_ "slave_fifo32/gpif_data_out[9]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_out_9)) + (portref I (instanceref GPIF_D_9_IOBUF)) + ) + ) + (net (rename f1_rd_addr_9_ "f1/rd_addr[9]") (joined + (portref Q (instanceref f1_rd_addr_9)) + (portref I0 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 3) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRB 3) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename f1_rd_addr_12__wr_addr_12__equal_11_o "f1/rd_addr[12]_wr_addr[12]_equal_11_o") (joined + (portref O (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref CI (instanceref f1__n0161_inv1_cy)) + (portref I2 (instanceref f1_read_state_FSM_FFd1_In111)) + (portref I1 (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename f0_dont_write_past_me_11__FRB "f0/dont_write_past_me<11>_FRB") (joined + (portref I5 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f0_dont_write_past_me_11__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[0]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + ) + ) + (net (rename f0_Result_8_1_FRB "f0/Result<8>1_FRB") (joined + (portref D (instanceref f0_rd_addr_8)) + (portref Q (instanceref f0_Result_8_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_8__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + ) + ) + (net (rename tx_codec_d_0_ "tx_codec_d[0]") (joined + (portref O (instanceref tx_codec_d_0_OBUF)) + (portref (member tx_codec_d 11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_ctrl_tx_tvalid "slave_fifo32/ctrl_tx_tvalid") (joined + (portref D (instanceref slave_fifo32_debug1_19)) + (portref O (instanceref slave_fifo32_ctrl_tx_tvalid1)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd2_BRB0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_5_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_6_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_7_)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_write_AND_42_o_inv2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_read)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tvalid11)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_11__rt "f1/Mcount_rd_addr_cy<11>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_11__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_11_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + ) + ) + (net (rename tx_codec_d_1_ "tx_codec_d[1]") (joined + (portref O (instanceref tx_codec_d_1_OBUF)) + (portref (member tx_codec_d 10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + ) + ) + (net (rename tx_codec_d_2_ "tx_codec_d[2]") (joined + (portref O (instanceref tx_codec_d_2_OBUF)) + (portref (member tx_codec_d 9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + ) + ) + (net (rename tx_codec_d_3_ "tx_codec_d[3]") (joined + (portref O (instanceref tx_codec_d_3_OBUF)) + (portref (member tx_codec_d 8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01211 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01211") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_lut)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01213") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01214") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + ) + ) + (net (rename tx_codec_d_4_ "tx_codec_d[4]") (joined + (portref O (instanceref tx_codec_d_4_OBUF)) + (portref (member tx_codec_d 7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01216") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/num_packets[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Msub_num_packets_7__GND_55_o_sub_15_OUT_cy_6_11_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg_glue_set_lut)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01217") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_sloe_10 "slave_fifo32/sloe_10") (joined + (portref Q (instanceref slave_fifo32_sloe_10)) + (portref T (instanceref GPIF_D_8_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n01218") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01219)) + ) + ) + (net (rename slave_fifo32_sloe_11 "slave_fifo32/sloe_11") (joined + (portref Q (instanceref slave_fifo32_sloe_11)) + (portref T (instanceref GPIF_D_9_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_12 "slave_fifo32/sloe_12") (joined + (portref Q (instanceref slave_fifo32_sloe_12)) + (portref T (instanceref GPIF_D_10_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + ) + ) + (net (rename slave_fifo32_sloe_13 "slave_fifo32/sloe_13") (joined + (portref Q (instanceref slave_fifo32_sloe_13)) + (portref T (instanceref GPIF_D_11_IOBUF)) + ) + ) + (net (rename tx_codec_d_5_ "tx_codec_d[5]") (joined + (portref O (instanceref tx_codec_d_5_OBUF)) + (portref (member tx_codec_d 6)) + ) + ) + (net (rename slave_fifo32_sloe_14 "slave_fifo32/sloe_14") (joined + (portref Q (instanceref slave_fifo32_sloe_14)) + (portref T (instanceref GPIF_D_12_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_20 "slave_fifo32/sloe_20") (joined + (portref Q (instanceref slave_fifo32_sloe_20)) + (portref T (instanceref GPIF_D_18_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_15 "slave_fifo32/sloe_15") (joined + (portref Q (instanceref slave_fifo32_sloe_15)) + (portref T (instanceref GPIF_D_13_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_21 "slave_fifo32/sloe_21") (joined + (portref Q (instanceref slave_fifo32_sloe_21)) + (portref T (instanceref GPIF_D_19_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_16 "slave_fifo32/sloe_16") (joined + (portref Q (instanceref slave_fifo32_sloe_16)) + (portref T (instanceref GPIF_D_14_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_22 "slave_fifo32/sloe_22") (joined + (portref Q (instanceref slave_fifo32_sloe_22)) + (portref T (instanceref GPIF_D_20_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_17 "slave_fifo32/sloe_17") (joined + (portref Q (instanceref slave_fifo32_sloe_17)) + (portref T (instanceref GPIF_D_15_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + ) + ) + (net (rename slave_fifo32_sloe_18 "slave_fifo32/sloe_18") (joined + (portref Q (instanceref slave_fifo32_sloe_18)) + (portref T (instanceref GPIF_D_16_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_23 "slave_fifo32/sloe_23") (joined + (portref Q (instanceref slave_fifo32_sloe_23)) + (portref T (instanceref GPIF_D_21_IOBUF)) + ) + ) + (net (rename tx_codec_d_6_ "tx_codec_d[6]") (joined + (portref O (instanceref tx_codec_d_6_OBUF)) + (portref (member tx_codec_d 5)) + ) + ) + (net (rename slave_fifo32_sloe_19 "slave_fifo32/sloe_19") (joined + (portref Q (instanceref slave_fifo32_sloe_19)) + (portref T (instanceref GPIF_D_17_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_24 "slave_fifo32/sloe_24") (joined + (portref Q (instanceref slave_fifo32_sloe_24)) + (portref T (instanceref GPIF_D_22_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_30 "slave_fifo32/sloe_30") (joined + (portref Q (instanceref slave_fifo32_sloe_30)) + (portref T (instanceref GPIF_D_28_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_25 "slave_fifo32/sloe_25") (joined + (portref Q (instanceref slave_fifo32_sloe_25)) + (portref T (instanceref GPIF_D_23_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_31 "slave_fifo32/sloe_31") (joined + (portref Q (instanceref slave_fifo32_sloe_31)) + (portref T (instanceref GPIF_D_29_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_26 "slave_fifo32/sloe_26") (joined + (portref Q (instanceref slave_fifo32_sloe_26)) + (portref T (instanceref GPIF_D_24_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_32 "slave_fifo32/sloe_32") (joined + (portref Q (instanceref slave_fifo32_sloe_32)) + (portref T (instanceref GPIF_D_30_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_27 "slave_fifo32/sloe_27") (joined + (portref Q (instanceref slave_fifo32_sloe_27)) + (portref T (instanceref GPIF_D_25_IOBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + ) + ) + (net (rename slave_fifo32_sloe_28 "slave_fifo32/sloe_28") (joined + (portref Q (instanceref slave_fifo32_sloe_28)) + (portref T (instanceref GPIF_D_26_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_33 "slave_fifo32/sloe_33") (joined + (portref Q (instanceref slave_fifo32_sloe_33)) + (portref T (instanceref GPIF_D_31_IOBUF)) + ) + ) + (net (rename tx_codec_d_7_ "tx_codec_d[7]") (joined + (portref O (instanceref tx_codec_d_7_OBUF)) + (portref (member tx_codec_d 4)) + ) + ) + (net (rename slave_fifo32_sloe_29 "slave_fifo32/sloe_29") (joined + (portref Q (instanceref slave_fifo32_sloe_29)) + (portref T (instanceref GPIF_D_27_IOBUF)) + ) + ) + (net (rename slave_fifo32_sloe_34 "slave_fifo32/sloe_34") (joined + (portref Q (instanceref slave_fifo32_sloe_34)) + (portref D (instanceref slave_fifo32_debug1_31)) + (portref I0 (instanceref slave_fifo32_sloe_1_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + ) + ) + (net (rename tx_codec_d_8_ "tx_codec_d[8]") (joined + (portref O (instanceref tx_codec_d_8_OBUF)) + (portref (member tx_codec_d 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + ) + ) + (net (rename tx_codec_d_9_ "tx_codec_d[9]") (joined + (portref O (instanceref tx_codec_d_9_OBUF)) + (portref (member tx_codec_d 2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + ) + ) + (net bus_clk (joined + (portref C (instanceref bus_sync_reset_int)) + (portref C (instanceref bus_sync_reset_out)) + (portref O (instanceref gen_clks_clkout3_buf)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_a_4)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_14__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_15__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_16__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_17__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_18__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_19__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_20__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_21__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_22__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_23__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_24__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_25__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_27__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_28__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_30__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_32__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_33__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_48__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_53__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref CLK (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_59__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref CLK (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_64__srlc32e)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_9)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_10)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_11)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_12)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_13)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_14)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_lines32_15)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_6)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_7)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_8)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_9)) + (portref C (instanceref f1_rd_addr_1)) + (portref C (instanceref f1_rd_addr_2)) + (portref C (instanceref f1_rd_addr_3)) + (portref C (instanceref f1_rd_addr_4)) + (portref C (instanceref f1_rd_addr_5)) + (portref C (instanceref f1_rd_addr_6)) + (portref C (instanceref f1_rd_addr_7)) + (portref C (instanceref f1_rd_addr_8)) + (portref C (instanceref f1_rd_addr_9)) + (portref C (instanceref f1_rd_addr_10)) + (portref C (instanceref f1_rd_addr_11)) + (portref C (instanceref f1_rd_addr_12)) + (portref C (instanceref f1_wr_addr_1)) + (portref C (instanceref f1_wr_addr_2)) + (portref C (instanceref f1_wr_addr_3)) + (portref C (instanceref f1_wr_addr_4)) + (portref C (instanceref f1_wr_addr_5)) + (portref C (instanceref f1_wr_addr_6)) + (portref C (instanceref f1_wr_addr_7)) + (portref C (instanceref f1_wr_addr_8)) + (portref C (instanceref f1_wr_addr_9)) + (portref C (instanceref f1_wr_addr_10)) + (portref C (instanceref f1_wr_addr_11)) + (portref C (instanceref f1_wr_addr_12)) + (portref C (instanceref f1_read_state_FSM_FFd2)) + (portref C (instanceref f1_read_state_FSM_FFd1)) + (portref C (instanceref f1_rd_addr_0)) + (portref C (instanceref f1_wr_addr_0)) + (portref C (instanceref f0_rd_addr_1)) + (portref C (instanceref f0_rd_addr_2)) + (portref C (instanceref f0_rd_addr_3)) + (portref C (instanceref f0_rd_addr_4)) + (portref C (instanceref f0_rd_addr_5)) + (portref C (instanceref f0_rd_addr_6)) + (portref C (instanceref f0_rd_addr_7)) + (portref C (instanceref f0_rd_addr_8)) + (portref C (instanceref f0_rd_addr_9)) + (portref C (instanceref f0_rd_addr_10)) + (portref C (instanceref f0_rd_addr_11)) + (portref C (instanceref f0_rd_addr_12)) + (portref C (instanceref f0_wr_addr_1)) + (portref C (instanceref f0_wr_addr_2)) + (portref C (instanceref f0_wr_addr_3)) + (portref C (instanceref f0_wr_addr_4)) + (portref C (instanceref f0_wr_addr_5)) + (portref C (instanceref f0_wr_addr_6)) + (portref C (instanceref f0_wr_addr_7)) + (portref C (instanceref f0_wr_addr_8)) + (portref C (instanceref f0_wr_addr_9)) + (portref C (instanceref f0_wr_addr_10)) + (portref C (instanceref f0_wr_addr_11)) + (portref C (instanceref f0_wr_addr_12)) + (portref C (instanceref f0_read_state_FSM_FFd2)) + (portref C (instanceref f0_read_state_FSM_FFd1)) + (portref C (instanceref f0_rd_addr_0)) + (portref C (instanceref f0_wr_addr_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref C (instanceref f1_full_reg)) + (portref C (instanceref f0_full_reg)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref C (instanceref f1_Result_0_2_FRB)) + (portref C (instanceref f1_Result_1_2_FRB)) + (portref C (instanceref f1_Result_2_2_FRB)) + (portref C (instanceref f1_Result_3_2_FRB)) + (portref C (instanceref f1_Result_4_2_FRB)) + (portref C (instanceref f1_Result_5_2_FRB)) + (portref C (instanceref f1_Result_6_2_FRB)) + (portref C (instanceref f1_Result_7_2_FRB)) + (portref C (instanceref f1_Result_8_2_FRB)) + (portref C (instanceref f1_Result_9_2_FRB)) + (portref C (instanceref f1_Result_10_2_FRB)) + (portref C (instanceref f1_Result_11_2_FRB)) + (portref C (instanceref f1_Result_12_2_FRB)) + (portref C (instanceref f1_Result_0_1_FRB)) + (portref C (instanceref f1_Result_1_1_FRB)) + (portref C (instanceref f1_Result_2_1_FRB)) + (portref C (instanceref f1_Result_3_1_FRB)) + (portref C (instanceref f1_Result_4_1_FRB)) + (portref C (instanceref f1_Result_5_1_FRB)) + (portref C (instanceref f1_Result_6_1_FRB)) + (portref C (instanceref f1_Result_7_1_FRB)) + (portref C (instanceref f1_Result_8_1_FRB)) + (portref C (instanceref f1_Result_9_1_FRB)) + (portref C (instanceref f1_Result_10_1_FRB)) + (portref C (instanceref f1_Result_11_1_FRB)) + (portref C (instanceref f1_Result_12_1_FRB)) + (portref C (instanceref f1_dont_write_past_me_0__FRB)) + (portref C (instanceref f1_dont_write_past_me_1__FRB)) + (portref C (instanceref f1_dont_write_past_me_2__FRB)) + (portref C (instanceref f1_dont_write_past_me_3__FRB)) + (portref C (instanceref f1_dont_write_past_me_4__FRB)) + (portref C (instanceref f1_dont_write_past_me_5__FRB)) + (portref C (instanceref f1_dont_write_past_me_6__FRB)) + (portref C (instanceref f1_dont_write_past_me_7__FRB)) + (portref C (instanceref f1_dont_write_past_me_8__FRB)) + (portref C (instanceref f1_dont_write_past_me_9__FRB)) + (portref C (instanceref f1_dont_write_past_me_10__FRB)) + (portref C (instanceref f1_dont_write_past_me_11__FRB)) + (portref C (instanceref f1_dont_write_past_me_12__FRB)) + (portref C (instanceref f0_Result_0_2_FRB)) + (portref C (instanceref f0_Result_1_2_FRB)) + (portref C (instanceref f0_Result_2_2_FRB)) + (portref C (instanceref f0_Result_3_2_FRB)) + (portref C (instanceref f0_Result_4_2_FRB)) + (portref C (instanceref f0_Result_5_2_FRB)) + (portref C (instanceref f0_Result_6_2_FRB)) + (portref C (instanceref f0_Result_7_2_FRB)) + (portref C (instanceref f0_Result_8_2_FRB)) + (portref C (instanceref f0_Result_9_2_FRB)) + (portref C (instanceref f0_Result_10_2_FRB)) + (portref C (instanceref f0_Result_11_2_FRB)) + (portref C (instanceref f0_Result_12_2_FRB)) + (portref C (instanceref f0_Result_0_1_FRB)) + (portref C (instanceref f0_Result_1_1_FRB)) + (portref C (instanceref f0_Result_2_1_FRB)) + (portref C (instanceref f0_Result_3_1_FRB)) + (portref C (instanceref f0_Result_4_1_FRB)) + (portref C (instanceref f0_Result_5_1_FRB)) + (portref C (instanceref f0_Result_6_1_FRB)) + (portref C (instanceref f0_Result_7_1_FRB)) + (portref C (instanceref f0_Result_8_1_FRB)) + (portref C (instanceref f0_Result_9_1_FRB)) + (portref C (instanceref f0_Result_10_1_FRB)) + (portref C (instanceref f0_Result_11_1_FRB)) + (portref C (instanceref f0_Result_12_1_FRB)) + (portref C (instanceref f0_dont_write_past_me_0__FRB)) + (portref C (instanceref f0_dont_write_past_me_1__FRB)) + (portref C (instanceref f0_dont_write_past_me_2__FRB)) + (portref C (instanceref f0_dont_write_past_me_3__FRB)) + (portref C (instanceref f0_dont_write_past_me_4__FRB)) + (portref C (instanceref f0_dont_write_past_me_5__FRB)) + (portref C (instanceref f0_dont_write_past_me_6__FRB)) + (portref C (instanceref f0_dont_write_past_me_7__FRB)) + (portref C (instanceref f0_dont_write_past_me_8__FRB)) + (portref C (instanceref f0_dont_write_past_me_9__FRB)) + (portref C (instanceref f0_dont_write_past_me_10__FRB)) + (portref C (instanceref f0_dont_write_past_me_11__FRB)) + (portref C (instanceref f0_dont_write_past_me_12__FRB)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB0)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB2)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB5)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB1)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB3)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_empty_reg_BRB4)) + (portref C (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref CLKAWRCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref CLKBRDCLK (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref CLKA (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref CLKAWRCLK (instanceref f1_ram_Mram_ram33)) + (portref CLKBRDCLK (instanceref f1_ram_Mram_ram33)) + (portref CLKA (instanceref f1_ram_Mram_ram31)) + (portref CLKB (instanceref f1_ram_Mram_ram31)) + (portref CLKA (instanceref f1_ram_Mram_ram30)) + (portref CLKB (instanceref f1_ram_Mram_ram30)) + (portref CLKA (instanceref f1_ram_Mram_ram32)) + (portref CLKB (instanceref f1_ram_Mram_ram32)) + (portref CLKA (instanceref f1_ram_Mram_ram28)) + (portref CLKB (instanceref f1_ram_Mram_ram28)) + (portref CLKA (instanceref f1_ram_Mram_ram27)) + (portref CLKB (instanceref f1_ram_Mram_ram27)) + (portref CLKA (instanceref f1_ram_Mram_ram29)) + (portref CLKB (instanceref f1_ram_Mram_ram29)) + (portref CLKA (instanceref f1_ram_Mram_ram25)) + (portref CLKB (instanceref f1_ram_Mram_ram25)) + (portref CLKA (instanceref f1_ram_Mram_ram24)) + (portref CLKB (instanceref f1_ram_Mram_ram24)) + (portref CLKA (instanceref f1_ram_Mram_ram26)) + (portref CLKB (instanceref f1_ram_Mram_ram26)) + (portref CLKA (instanceref f1_ram_Mram_ram22)) + (portref CLKB (instanceref f1_ram_Mram_ram22)) + (portref CLKA (instanceref f1_ram_Mram_ram21)) + (portref CLKB (instanceref f1_ram_Mram_ram21)) + (portref CLKA (instanceref f1_ram_Mram_ram23)) + (portref CLKB (instanceref f1_ram_Mram_ram23)) + (portref CLKA (instanceref f1_ram_Mram_ram19)) + (portref CLKB (instanceref f1_ram_Mram_ram19)) + (portref CLKA (instanceref f1_ram_Mram_ram18)) + (portref CLKB (instanceref f1_ram_Mram_ram18)) + (portref CLKA (instanceref f1_ram_Mram_ram20)) + (portref CLKB (instanceref f1_ram_Mram_ram20)) + (portref CLKA (instanceref f1_ram_Mram_ram16)) + (portref CLKB (instanceref f1_ram_Mram_ram16)) + (portref CLKA (instanceref f1_ram_Mram_ram15)) + (portref CLKB (instanceref f1_ram_Mram_ram15)) + (portref CLKA (instanceref f1_ram_Mram_ram17)) + (portref CLKB (instanceref f1_ram_Mram_ram17)) + (portref CLKA (instanceref f1_ram_Mram_ram14)) + (portref CLKB (instanceref f1_ram_Mram_ram14)) + (portref CLKA (instanceref f1_ram_Mram_ram13)) + (portref CLKB (instanceref f1_ram_Mram_ram13)) + (portref CLKA (instanceref f1_ram_Mram_ram12)) + (portref CLKB (instanceref f1_ram_Mram_ram12)) + (portref CLKA (instanceref f1_ram_Mram_ram11)) + (portref CLKB (instanceref f1_ram_Mram_ram11)) + (portref CLKA (instanceref f1_ram_Mram_ram9)) + (portref CLKB (instanceref f1_ram_Mram_ram9)) + (portref CLKA (instanceref f1_ram_Mram_ram8)) + (portref CLKB (instanceref f1_ram_Mram_ram8)) + (portref CLKA (instanceref f1_ram_Mram_ram10)) + (portref CLKB (instanceref f1_ram_Mram_ram10)) + (portref CLKA (instanceref f1_ram_Mram_ram6)) + (portref CLKB (instanceref f1_ram_Mram_ram6)) + (portref CLKA (instanceref f1_ram_Mram_ram5)) + (portref CLKB (instanceref f1_ram_Mram_ram5)) + (portref CLKA (instanceref f1_ram_Mram_ram7)) + (portref CLKB (instanceref f1_ram_Mram_ram7)) + (portref CLKA (instanceref f1_ram_Mram_ram3)) + (portref CLKB (instanceref f1_ram_Mram_ram3)) + (portref CLKA (instanceref f1_ram_Mram_ram2)) + (portref CLKB (instanceref f1_ram_Mram_ram2)) + (portref CLKA (instanceref f1_ram_Mram_ram4)) + (portref CLKB (instanceref f1_ram_Mram_ram4)) + (portref CLKA (instanceref f1_ram_Mram_ram1)) + (portref CLKB (instanceref f1_ram_Mram_ram1)) + (portref CLKAWRCLK (instanceref f0_ram_Mram_ram33)) + (portref CLKBRDCLK (instanceref f0_ram_Mram_ram33)) + (portref CLKA (instanceref f0_ram_Mram_ram31)) + (portref CLKB (instanceref f0_ram_Mram_ram31)) + (portref CLKA (instanceref f0_ram_Mram_ram30)) + (portref CLKB (instanceref f0_ram_Mram_ram30)) + (portref CLKA (instanceref f0_ram_Mram_ram32)) + (portref CLKB (instanceref f0_ram_Mram_ram32)) + (portref CLKA (instanceref f0_ram_Mram_ram28)) + (portref CLKB (instanceref f0_ram_Mram_ram28)) + (portref CLKA (instanceref f0_ram_Mram_ram27)) + (portref CLKB (instanceref f0_ram_Mram_ram27)) + (portref CLKA (instanceref f0_ram_Mram_ram29)) + (portref CLKB (instanceref f0_ram_Mram_ram29)) + (portref CLKA (instanceref f0_ram_Mram_ram25)) + (portref CLKB (instanceref f0_ram_Mram_ram25)) + (portref CLKA (instanceref f0_ram_Mram_ram24)) + (portref CLKB (instanceref f0_ram_Mram_ram24)) + (portref CLKA (instanceref f0_ram_Mram_ram26)) + (portref CLKB (instanceref f0_ram_Mram_ram26)) + (portref CLKA (instanceref f0_ram_Mram_ram22)) + (portref CLKB (instanceref f0_ram_Mram_ram22)) + (portref CLKA (instanceref f0_ram_Mram_ram21)) + (portref CLKB (instanceref f0_ram_Mram_ram21)) + (portref CLKA (instanceref f0_ram_Mram_ram23)) + (portref CLKB (instanceref f0_ram_Mram_ram23)) + (portref CLKA (instanceref f0_ram_Mram_ram19)) + (portref CLKB (instanceref f0_ram_Mram_ram19)) + (portref CLKA (instanceref f0_ram_Mram_ram18)) + (portref CLKB (instanceref f0_ram_Mram_ram18)) + (portref CLKA (instanceref f0_ram_Mram_ram20)) + (portref CLKB (instanceref f0_ram_Mram_ram20)) + (portref CLKA (instanceref f0_ram_Mram_ram16)) + (portref CLKB (instanceref f0_ram_Mram_ram16)) + (portref CLKA (instanceref f0_ram_Mram_ram15)) + (portref CLKB (instanceref f0_ram_Mram_ram15)) + (portref CLKA (instanceref f0_ram_Mram_ram17)) + (portref CLKB (instanceref f0_ram_Mram_ram17)) + (portref CLKA (instanceref f0_ram_Mram_ram14)) + (portref CLKB (instanceref f0_ram_Mram_ram14)) + (portref CLKA (instanceref f0_ram_Mram_ram13)) + (portref CLKB (instanceref f0_ram_Mram_ram13)) + (portref CLKA (instanceref f0_ram_Mram_ram12)) + (portref CLKB (instanceref f0_ram_Mram_ram12)) + (portref CLKA (instanceref f0_ram_Mram_ram11)) + (portref CLKB (instanceref f0_ram_Mram_ram11)) + (portref CLKA (instanceref f0_ram_Mram_ram9)) + (portref CLKB (instanceref f0_ram_Mram_ram9)) + (portref CLKA (instanceref f0_ram_Mram_ram8)) + (portref CLKB (instanceref f0_ram_Mram_ram8)) + (portref CLKA (instanceref f0_ram_Mram_ram10)) + (portref CLKB (instanceref f0_ram_Mram_ram10)) + (portref CLKA (instanceref f0_ram_Mram_ram6)) + (portref CLKB (instanceref f0_ram_Mram_ram6)) + (portref CLKA (instanceref f0_ram_Mram_ram5)) + (portref CLKB (instanceref f0_ram_Mram_ram5)) + (portref CLKA (instanceref f0_ram_Mram_ram7)) + (portref CLKB (instanceref f0_ram_Mram_ram7)) + (portref CLKA (instanceref f0_ram_Mram_ram3)) + (portref CLKB (instanceref f0_ram_Mram_ram3)) + (portref CLKA (instanceref f0_ram_Mram_ram2)) + (portref CLKB (instanceref f0_ram_Mram_ram2)) + (portref CLKA (instanceref f0_ram_Mram_ram4)) + (portref CLKB (instanceref f0_ram_Mram_ram4)) + (portref CLKA (instanceref f0_ram_Mram_ram1)) + (portref CLKB (instanceref f0_ram_Mram_ram1)) + (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + (portref rd_clk (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + (portref wr_clk (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename gen_clks_CLK_OUT1_40_int "gen_clks/CLK_OUT1_40_int") (joined + (portref O (instanceref gen_clks_clkout1_buf)) + (portref CLKFB (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_10_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_10)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata210)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata371)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012121 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/_n012121") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0121211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01216)) + ) + ) + (net (rename n0036_10_ "n0036[10]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_10__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_11_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata310)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata381)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + ) + ) + (net (rename n0036_11_ "n0036[11]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_11__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_12_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_12)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata410)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata391)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + ) + ) + (net (rename n0036_12_ "n0036[12]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_12__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_13_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_13)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata510)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + ) + ) + (net (rename n0036_13_ "n0036[13]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_13__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_14_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[14]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_14)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata65)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata411)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT41 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT41") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename n0036_14_ "n0036[14]") (joined + (portref D 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"slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[22]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_22)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata151)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501)) + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_17_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[17]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_17)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata91)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + ) + ) + (net (rename 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(rename n0036_26_ "n0036[26]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_26__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram14)) + ) + ) + (net (rename n0036_31_ "n0036[31]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_31__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram16)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_27_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[27]") (joined + (portref D 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(portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o32_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_tx/o32_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_holding_29)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581)) + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_4)) + (portref I1 (instanceref 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(rename n0036_35_ "n0036[35]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_35__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram18)) + ) + ) + (net (rename n0036_40_ "n0036[40]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_40__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata110)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata321)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611)) + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename n0036_36_ "n0036[36]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_36__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename n0036_41_ "n0036[41]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_41__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full101 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full101") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1011)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_7)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata331)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata621)) + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full102 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full102") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename n0036_37_ "n0036[37]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_37__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram19)) + ) + ) + (net (rename n0036_42_ "n0036[42]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_42__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata231)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_8)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata351)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata631)) + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename n0036_38_ "n0036[38]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_38__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename n0036_43_ "n0036[43]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_43__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram22)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata341)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tdata[9]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_holding_9)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata361)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata641)) + (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename n0036_39_ "n0036[39]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_39__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram20)) + ) + ) + (net (rename n0036_44_ "n0036[44]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_44__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata451)) + ) + ) + (net LED_TXRX1_RX (joined + (portref O (instanceref LED_TXRX1_RX_OBUF)) + (portref LED_TXRX1_RX) + ) + ) + (net (rename f1_Result_12_1_FRB "f1/Result<12>1_FRB") (joined + (portref D (instanceref f1_rd_addr_12)) + (portref Q (instanceref f1_Result_12_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_xor_12__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + ) + ) + (net (rename n0036_45_ "n0036[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram23)) + ) + ) + (net (rename n0036_50_ "n0036[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata561)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + ) + ) + (net (rename n0036_46_ "n0036[46]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_46__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename n0036_51_ "n0036[51]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_51__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tdata611)) + ) + ) + (net LED_TXRX1_TX (joined + (portref O (instanceref LED_TXRX1_TX_OBUF)) + (portref LED_TXRX1_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + ) + ) + (net (rename n0036_47_ "n0036[47]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_47__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram24)) + ) + ) + (net (rename n0036_52_ "n0036[52]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_52__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram27)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tdata[7]") (joined + (portref D (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_34_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[34]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_34__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata281)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_29_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[29]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_29__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata221)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__18_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][18]") (joined + (portref (member DOB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 53) (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/becoming_full411_FRB") (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411_FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Mmux_i_tvalid_int11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + ) + ) + (net (rename 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(instanceref slave_fifo32_sloe)) + ) + ) + (net LED_TXRX2_TX (joined + (portref O (instanceref LED_TXRX2_TX_OBUF)) + (portref LED_TXRX2_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_50_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[50]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_50__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata461)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_45_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[45]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_45__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata401)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0006_32_0__29_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0006[32:0][29]") (joined + (portref (member DOB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref (member din 42) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_5)) + (portref O (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_slrd "slave_fifo32/slrd") (joined + (portref I (instanceref GPIF_CTL3_OBUF)) + (portref Q (instanceref slave_fifo32_slrd)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_54_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[54]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_54__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata501)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_49_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[49]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_49__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata441)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/read_state_FSM_FFd1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I1 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[60]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_60__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata571)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_55_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[55]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_55__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata511)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_61_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[61]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_61__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata581)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_56_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[56]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_56__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata521)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_62_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[62]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_62__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata591)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_57_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[57]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_57__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata531)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_ctrl/cross_clock_fifo/full") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_GND_50_o_read_OR_57_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_write1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_4_)) + (portref I2 (instanceref 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f1_Result_2_2_FRB "f1/Result<2>2_FRB") (joined + (portref D (instanceref f1_wr_addr_2)) + (portref Q (instanceref f1_Result_2_2_FRB)) + (portref I0 (instanceref f1_Mcount_wr_addr_cy_2__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_63_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[63]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_63__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata601)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_58_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[58]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_gen_srlc32e_58__srlc32e)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tdata541)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tdata_59_ "slave_fifo32/fifo64_to_gpmc32_tx/o64_tdata[59]") (joined + (portref D (instanceref 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"slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012112") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012113") (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n012114") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_5__rt "f1/Mcount_rd_addr_cy<5>_rt") (joined + (portref O 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"slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/_n0074_inv5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT51") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I1 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(instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_11_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[11]") (joined + (portref (member DIA 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 60) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_12_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[12]") (joined + (portref (member DIA 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 59) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_13_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[13]") (joined + (portref (member DIA 18) (instanceref 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"f0/Mcompar_becoming_full_lut[0]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_2_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata231)) + (portref (member din 69) (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_1_ "f0/Mcompar_becoming_full_lut[1]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_1_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_3_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[3]") (joined + (portref O (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata271)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net tx_codec_d_0_OBUF (joined + (portref Q (instanceref catgen_gen_pins_0__oddr2)) + (portref I (instanceref tx_codec_d_0_OBUF)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_3_ "f0/Mcompar_becoming_full_lut[3]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_5_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata281)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcompar_becoming_full_lut_4_ "f0/Mcompar_becoming_full_lut[4]") (joined + (portref O (instanceref f0_Mcompar_becoming_full_lut_4_)) + (portref S (instanceref f0_Mcompar_becoming_full_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_6_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata291)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_full_reg_glue_set "f1/full_reg_glue_set") (joined + (portref D (instanceref f1_full_reg)) + (portref O (instanceref f1_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_7_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata301)) + (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Result_8_2_FRB "f0/Result<8>2_FRB") (joined + (portref D (instanceref f0_wr_addr_8)) + (portref Q (instanceref f0_Result_8_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_8__rt)) + ) + ) + (net tx_frame_p (joined + (portref O (instanceref tx_frame_p_OBUF)) + (portref tx_frame_p) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_8_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata311)) + (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In12") (joined + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In14)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_read1)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_i32_tdata_9_ "slave_fifo32/fifo64_to_gpmc32_rx/i32_tdata[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_Mmux_o_tdata321)) + (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In31") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/state_FSM_FFd1-In32") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In33)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space_12_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_12_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename f0_Result_10_1_FRB "f0/Result<10>1_FRB") (joined + (portref D (instanceref f0_rd_addr_10)) + (portref Q (instanceref f0_Result_10_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_10__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<10>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename slave_fifo32_EP_READY1 "slave_fifo32/EP_READY1") (joined + (portref Q (instanceref slave_fifo32_EP_READY1)) + (portref I (instanceref debug_24_OBUF)) + ) + ) + (net (rename f1_read_state_FSM_FFd2_In "f1/read_state_FSM_FFd2-In") (joined + (portref D (instanceref f1_read_state_FSM_FFd2)) + (portref O (instanceref f1_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_6_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_a_xor_2_11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0102_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I4 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_4_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__0_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][0]") (joined + (portref (member DOB 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 71) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Maddsub_num_packets[7]_num_packets[7]_mux_13_OUT_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__1_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][1]") (joined + (portref (member DOB 30) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 70) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/dump") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_clear_dump_OR_131_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename f0_wr_addr_10_ "f0/wr_addr[10]") (joined + (portref Q (instanceref f0_wr_addr_10)) + (portref I3 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I2 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 2) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 2) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__2_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][2]") (joined + (portref (member DOB 29) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 69) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_wr_addr_11_ "f0/wr_addr[11]") (joined + (portref Q (instanceref f0_wr_addr_11)) + (portref I5 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref I4 (instanceref f0_Mcompar_becoming_full_lut_3_)) + (portref (member ADDRAWRADDR 1) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 1) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_slrd2_1 "slave_fifo32/slrd2_1") (joined + (portref Q (instanceref slave_fifo32_slrd2_1)) + (portref D (instanceref slave_fifo32_slrd3)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIPA 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__3_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][3]") (joined + (portref (member DOB 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 68) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_wr_addr_12_ "f0/wr_addr[12]") (joined + (portref Q (instanceref f0_wr_addr_12)) + (portref I1 (instanceref f0_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref I0 (instanceref f0_Mcompar_becoming_full_lut_4_)) + (portref (member ADDRAWRADDR 0) (instanceref f0_ram_Mram_ram33)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram31)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram30)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram32)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram28)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram27)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram29)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram25)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram24)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram26)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram22)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram21)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram23)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram19)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram18)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram20)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram16)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram15)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram17)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram14)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram13)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram12)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram11)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram9)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram8)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram10)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram6)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram5)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram7)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram3)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram2)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram4)) + (portref (member ADDRA 0) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__4_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][4]") (joined + (portref (member DOB 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 67) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__5_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][5]") (joined + (portref (member DOB 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 66) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_wr_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__6_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][6]") (joined + (portref (member DOB 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 65) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__7_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][7]") (joined + (portref (member DOB 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 64) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__8_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][8]") (joined + (portref (member DOB 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 63) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net tx_codec_d_6_OBUF (joined + (portref Q (instanceref catgen_gen_pins_6__oddr2)) + (portref I (instanceref tx_codec_d_6_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__9_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][9]") (joined + (portref (member DOB 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 62) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_10_ "f1/Msub_dont_write_past_me_lut[10]") (joined + (portref S (instanceref f1_Msub_dont_write_past_me_cy_10_)) + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_10_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int13") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int14 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_i_tvalid_int14") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int15)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16_SW0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_11_ "f1/Msub_dont_write_past_me_lut[11]") (joined + (portref S (instanceref f1_Msub_dont_write_past_me_cy_11_)) + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_11_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_lut_12_ "f1/Msub_dont_write_past_me_lut[12]") (joined + (portref LI (instanceref f1_Msub_dont_write_past_me_xor_12_)) + (portref O (instanceref f1_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<2>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename tx_codec_d_10_ "tx_codec_d[10]") (joined + (portref O (instanceref tx_codec_d_10_OBUF)) + (portref (member tx_codec_d 1)) + ) + ) + (net (rename f0_Mcount_rd_addr_xor_12__rt "f0/Mcount_rd_addr_xor<12>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_xor_12__rt)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename n0035_0_ "n0035[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_0__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/o_tready_int") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_o_tready_int1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n0146_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + ) + ) + (net (rename tx_codec_d_11_ "tx_codec_d[11]") (joined + (portref O (instanceref tx_codec_d_11_OBUF)) + (portref (member tx_codec_d 0)) + ) + ) + (net (rename n0035_1_ "n0035[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_1__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty_glue_rst") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename n0035_2_ "n0035[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_2__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[0]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_0_)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW0)) + (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_3_ "n0035[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_3__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[1]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd1_In12)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_1_)) + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_4_ "n0035[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[2]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_2_)) + (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_5_ "n0035[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[3]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_3_)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_6_ "n0035[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[4]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_4_)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename n0035_7_ "n0035[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[5]") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_5_)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F)) + (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net GPIF_CTL4_IBUF (joined + (portref D (instanceref slave_fifo32_EP_READY)) + (portref O (instanceref GPIF_CTL4_IBUF)) + ) + ) + (net (rename n0035_8_ "n0035[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DOB 31) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[6]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_6_)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0035_9_ "n0035[9]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_gen_srlc32e_9__srlc32e)) + (portref (member DOB 30) (instanceref f0_ram_Mram_ram5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[7]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_7_)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_becoming_full "f0/becoming_full") (joined + (portref O (instanceref f0_Mcompar_becoming_full_cy_4_)) + (portref I1 (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0144_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref 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O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[8]") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW2)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_lut_8_)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_n0008_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/n0008[9]") (joined + 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"f1/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[2]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_4_ "n0036[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_4__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram3)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_7_ "f1/Mcount_wr_addr_cy[7]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_4_ "f1/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename gen_clks_clkfx "gen_clks/clkfx") (joined + (portref I (instanceref gen_clks_clkout3_buf)) + (portref I (instanceref gen_clks_clkout2_buf)) + (portref CLKFX (instanceref gen_clks_dcm_sp_inst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[3]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member dout 68) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv3 "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/_n0129_inv3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01214)) + ) + ) + (net (rename n0036_5_ "n0036[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_5__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram3)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_8_ "f1/Mcount_wr_addr_cy[8]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_8_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_5_ "f1/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_4_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[4]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref (member dout 67) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_6_ "n0036[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_6__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram4)) + ) + ) + (net (rename f1_Mcount_wr_addr_cy_9_ "f1/Mcount_wr_addr_cy[9]") (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_9_)) + (portref CI (instanceref f1_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_6_ "f1/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[10]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_10_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_10)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_5_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[5]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref (member dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_7_ "n0036[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_7__srlc32e)) + (portref (member DOB 30) (instanceref f1_ram_Mram_ram4)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_7_ "f1/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[11]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_11_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref (member ADDRBRDADDR 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram7)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram8)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram9)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram12)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram10)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram11)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram13)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram14)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram15)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_rx/n0005[6]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename n0036_8_ "n0036[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_gen_srlc32e_8__srlc32e)) + (portref (member DOB 31) (instanceref f1_ram_Mram_ram5)) + ) + ) + (net (rename f1_Msub_dont_write_past_me_cy_8_ "f1/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_Result_0_ "slave_fifo32/Result[0]") (joined + (portref D (instanceref slave_fifo32_fifoadr_0)) + (portref D (instanceref slave_fifo32_fifoadr_0_1)) + (portref O (instanceref slave_fifo32_Mcount_fifoadr_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_12_)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref (member ADDRBRDADDR 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram17)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram5)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram3)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram4)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_ram_Mram_ram6)) + (portref (member ADDRB 0) (instanceref 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) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[11]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_11_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_ctrl/dead_lock_fix/full") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full)) + (portref I0 (instanceref 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slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT41)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[12]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_12_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_12_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_4)) + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[13]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_13_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_13_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/full") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref f0__n0161_inv1_lut)) + (portref I1 (instanceref f0_GND_14_o_read_OR_37_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_write1)) + (portref I1 (instanceref f0_read_state_FSM_FFd1_In111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref f0_read_state_FSM_FFd2_In1)) + (portref I2 (instanceref f0_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full921)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218)) + (portref (member ADDRA 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[14]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_14_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_14_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_10_ "slave_fifo32/ctrl_rx_tdata[10]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT210)) + (portref (member DOB 21) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT7)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_2)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01217)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01215)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01218)) + (portref (member ADDRA 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[15]") (joined + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[0]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_0_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_11_ "slave_fifo32/ctrl_rx_tdata[11]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT33)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_3)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012113)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212111)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012111)) + (portref (member ADDRA 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[1]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_1_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_12_ "slave_fifo32/ctrl_rx_tdata[12]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT41)) + (portref (member DOB 19) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/wr_addr[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref (member ADDRA 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[2]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0154_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/_n0154_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_0)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + (portref CE (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_lut[3]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_3_)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_14_ "slave_fifo32/ctrl_rx_tdata[14]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT61)) + (portref (member DOB 17) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename 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slave_fifo32_debug2_15)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tdata_29_ "slave_fifo32/ctrl_rx_tdata[29]") (joined + (portref I4 (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT221)) + (portref (member DOB 20) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_debug1_21_ "slave_fifo32/debug1[21]") (joined + (portref Q (instanceref slave_fifo32_debug1_21)) + (portref D (instanceref slave_fifo32_debug2_21)) + ) + ) + (net (rename slave_fifo32_debug1_16_ "slave_fifo32/debug1[16]") (joined + (portref D (instanceref slave_fifo32_debug2_16)) + (portref O (instanceref f0_i_tready1_INV_0)) + ) + ) + (net (rename slave_fifo32_debug1_22_ "slave_fifo32/debug1[22]") (joined + (portref Q (instanceref slave_fifo32_debug1_22)) + (portref D (instanceref slave_fifo32_debug2_22)) + ) + ) + (net (rename slave_fifo32_debug1_17_ "slave_fifo32/debug1[17]") (joined + (portref D (instanceref slave_fifo32_debug2_17)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_o_tvalid1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/full_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_write1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_read)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt__n0074_inv1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + ) + ) + (net (rename slave_fifo32_debug1_23_ "slave_fifo32/debug1[23]") (joined + (portref Q (instanceref slave_fifo32_debug1_23)) + (portref D (instanceref slave_fifo32_debug2_23)) + (portref I2 (instanceref slave_fifo32_rd_one_rstpot)) + (portref I2 (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + ) + ) + (net (rename slave_fifo32_debug1_18_ "slave_fifo32/debug1[18]") (joined + (portref Q (instanceref slave_fifo32_debug1_18)) + (portref D (instanceref slave_fifo32_debug2_18)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename f0_write "f0/write") (joined + (portref CE (instanceref f0_wr_addr_1)) + (portref CE (instanceref f0_wr_addr_2)) + (portref CE (instanceref f0_wr_addr_3)) + (portref CE (instanceref f0_wr_addr_4)) + (portref CE (instanceref f0_wr_addr_5)) + (portref CE (instanceref f0_wr_addr_6)) + (portref CE (instanceref f0_wr_addr_7)) + (portref CE (instanceref f0_wr_addr_8)) + (portref CE (instanceref f0_wr_addr_9)) + (portref CE (instanceref f0_wr_addr_10)) + (portref CE (instanceref f0_wr_addr_11)) + (portref CE (instanceref f0_wr_addr_12)) + (portref CE (instanceref f0_wr_addr_0)) + (portref O (instanceref f0_write11)) + (portref CE (instanceref f0_Result_0_2_FRB)) + (portref CE (instanceref f0_Result_1_2_FRB)) + (portref CE (instanceref f0_Result_2_2_FRB)) + (portref CE (instanceref f0_Result_3_2_FRB)) + (portref CE (instanceref f0_Result_4_2_FRB)) + (portref CE (instanceref f0_Result_5_2_FRB)) + (portref CE (instanceref f0_Result_6_2_FRB)) + (portref CE (instanceref f0_Result_7_2_FRB)) + (portref CE (instanceref f0_Result_8_2_FRB)) + (portref CE (instanceref f0_Result_9_2_FRB)) + (portref CE (instanceref f0_Result_10_2_FRB)) + (portref CE (instanceref f0_Result_11_2_FRB)) + (portref CE (instanceref f0_Result_12_2_FRB)) + (portref (member WEAWEL 1) (instanceref f0_ram_Mram_ram33)) + (portref (member WEAWEL 0) (instanceref f0_ram_Mram_ram33)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram31)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram30)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram32)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram28)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram27)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram29)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram25)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram24)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram26)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram22)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram21)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram23)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram19)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram18)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram20)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram16)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram15)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram17)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram14)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram13)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram12)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram11)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram9)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram8)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram10)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram6)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram5)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram7)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram3)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram2)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram4)) + (portref (member WEA 3) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 2) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 1) (instanceref f0_ram_Mram_ram1)) + (portref (member WEA 0) (instanceref f0_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug1_19_ "slave_fifo32/debug1[19]") (joined + (portref Q (instanceref slave_fifo32_debug1_19)) + (portref D (instanceref slave_fifo32_debug2_19)) + ) + ) + (net (rename f0_Mcount_wr_addr_cy_8__rt "f0/Mcount_wr_addr_cy<8>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_8__rt)) + (portref S (instanceref f0_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_2__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full421)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full411)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_debug1_31_ "slave_fifo32/debug1[31]") (joined + (portref Q (instanceref slave_fifo32_debug1_31)) + (portref D (instanceref slave_fifo32_debug2_31)) + ) + ) + (net (rename slave_fifo32_debug1_26_ "slave_fifo32/debug1[26]") (joined + (portref Q (instanceref slave_fifo32_debug1_26)) + (portref D (instanceref slave_fifo32_debug2_26)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_debug1_27_ "slave_fifo32/debug1[27]") (joined + (portref Q (instanceref slave_fifo32_debug1_27)) + (portref D (instanceref slave_fifo32_debug2_27)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_0_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[0]") (joined + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 71) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr7_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_7)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr7_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_7__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename slave_fifo32_debug1_28_ "slave_fifo32/debug1[28]") (joined + (portref Q (instanceref slave_fifo32_debug1_28)) + (portref D (instanceref slave_fifo32_debug2_28)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_1_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[1]") (joined + (portref (member DIA 30) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 70) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_debug1_29_ "slave_fifo32/debug1[29]") (joined + (portref Q (instanceref slave_fifo32_debug1_29)) + (portref D (instanceref slave_fifo32_debug2_29)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_2_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[2]") (joined + (portref (member DIA 29) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 69) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_3_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[3]") (joined + (portref (member DIA 28) (instanceref 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dout 66) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_6_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[6]") (joined + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 65) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcount_wr_addr_xor_12__rt "f0/Mcount_wr_addr_xor<12>_rt") (joined + (portref O (instanceref f0_Mcount_wr_addr_xor_12__rt)) + (portref LI (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_7_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[7]") (joined + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 64) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_8_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[8]") (joined + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 63) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_n0005_9_ "slave_fifo32/fifo64_to_gpmc32_resp/n0005[9]") (joined + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + (portref (member dout 62) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename f1_full_reg "f1/full_reg") (joined + (portref I1 (instanceref f1_write11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref f1_full_reg)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref I4 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref f1_full_reg_glue_set)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_gpif_data_out_31_1 "slave_fifo32/gpif_data_out_31_1") (joined + (portref Q (instanceref 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"f0/Msub_dont_write_past_me_cy[10]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_10_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_10_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_10_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_10_BRB1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_11_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[11]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_11_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_11_BRB1)) + ) + ) + (net (rename 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"f0/dont_write_past_me<0>_FRB") (joined + (portref I1 (instanceref f0_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f0_dont_write_past_me_0__FRB)) + ) + ) + (net (rename f1_dont_write_past_me_2__FRB "f1/dont_write_past_me<2>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_0_)) + (portref Q (instanceref f1_dont_write_past_me_2__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__space_15__mux_33_OUT_15_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_space[15]_mux_33_OUT[15]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_15_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15_BRB1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_11_)) + ) + ) + (net (rename f0__n0161_inv "f0/_n0161_inv") (joined + (portref CE (instanceref f0_rd_addr_1)) + (portref CE (instanceref f0_rd_addr_2)) + (portref CE (instanceref f0_rd_addr_3)) + (portref CE (instanceref f0_rd_addr_4)) + (portref CE (instanceref f0_rd_addr_5)) + (portref CE (instanceref f0_rd_addr_6)) + (portref CE (instanceref f0_rd_addr_7)) + (portref CE (instanceref f0_rd_addr_8)) + (portref CE (instanceref f0_rd_addr_9)) + (portref CE (instanceref f0_rd_addr_10)) + (portref CE (instanceref f0_rd_addr_11)) + (portref CE (instanceref f0_rd_addr_12)) + (portref CE (instanceref f0_rd_addr_0)) + (portref CE (instanceref f0_Result_0_1_FRB)) + (portref CE (instanceref f0_Result_1_1_FRB)) + (portref CE (instanceref f0_Result_2_1_FRB)) + (portref CE (instanceref f0_Result_3_1_FRB)) + (portref CE (instanceref f0_Result_4_1_FRB)) + (portref CE (instanceref f0_Result_5_1_FRB)) + (portref CE (instanceref f0_Result_6_1_FRB)) + (portref CE (instanceref f0_Result_7_1_FRB)) + (portref CE (instanceref f0_Result_8_1_FRB)) + (portref CE (instanceref f0_Result_9_1_FRB)) + (portref CE (instanceref f0_Result_10_1_FRB)) + (portref CE (instanceref f0_Result_11_1_FRB)) + (portref CE (instanceref f0_Result_12_1_FRB)) + (portref CE (instanceref f0_dont_write_past_me_0__FRB)) + (portref CE (instanceref f0_dont_write_past_me_1__FRB)) + (portref CE (instanceref f0_dont_write_past_me_2__FRB)) + (portref CE (instanceref f0_dont_write_past_me_3__FRB)) + (portref CE (instanceref f0_dont_write_past_me_4__FRB)) + (portref CE (instanceref f0_dont_write_past_me_5__FRB)) + (portref CE (instanceref f0_dont_write_past_me_6__FRB)) + (portref CE (instanceref f0_dont_write_past_me_7__FRB)) + (portref CE (instanceref f0_dont_write_past_me_8__FRB)) + (portref CE (instanceref f0_dont_write_past_me_9__FRB)) + (portref CE (instanceref f0_dont_write_past_me_10__FRB)) + (portref CE (instanceref f0_dont_write_past_me_11__FRB)) + (portref CE (instanceref f0_dont_write_past_me_12__FRB)) + (portref O (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net cat_ce (joined + (portref O (instanceref cat_ce_OBUF)) + (portref cat_ce) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a1 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a1") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_0_11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a2 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a2") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_1_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a3 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a3") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_2_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In11 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In11") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename f1_Mcount_rd_addr_xor_12__rt "f1/Mcount_rd_addr_xor<12>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_xor_12__rt)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a4 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a4") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_3_11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In12 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In12") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_read1)) + (portref rd_en (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a5 "slave_fifo32/fifo64_to_gpmc32_resp/dead_lock_fix/Mcount_a5") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_a_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_a_xor_4_11)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_7__rt "f1/Mcount_rd_addr_cy<7>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_7__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_7_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In31 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In31") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In32 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd1-In32") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In33)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In34)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB0") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT51)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT61)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT21)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT161)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_15_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_9_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_10_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_11_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_13_)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_14_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space_12_BRB1") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_12_BRB1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT41)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_lut_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT311 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT311") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT51)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_i_tvalid_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/i_tvalid_int") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT511)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_write1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_i_tvalid_int1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt__n0074_inv1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref S (instanceref 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"slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[22]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT151)) + (portref D (instanceref slave_fifo32_gpif_data_out_22)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_18_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[18]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT101)) + (portref D (instanceref slave_fifo32_gpif_data_out_18)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_23_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[23]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT161)) + (portref D (instanceref slave_fifo32_gpif_data_out_23)) + ) + ) + (net (rename slave_fifo32_ctrl_rx_tvalid_data_rx_tvalid_OR_56_o "slave_fifo32/ctrl_rx_tvalid_data_rx_tvalid_OR_56_o") (joined + (portref D (instanceref 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"slave_fifo32/pktend") (joined + (portref Q (instanceref slave_fifo32_pktend)) + (portref I (instanceref GPIF_CTL7_OBUF)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_26_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[26]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT191)) + (portref D (instanceref slave_fifo32_gpif_data_out_26)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_data_31__wide_mux_20_OUT_31_ "slave_fifo32/state[1]_wr_fifo_data[31]_wide_mux_20_OUT[31]") (joined + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_data_31__wide_mux_20_OUT251)) + (portref I2 (instanceref slave_fifo32_gpif_data_out_31_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr11_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr11_FRB") (joined + (portref D (instanceref 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(instanceref f0_Result_2_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_2_)) + ) + ) + (net N252 (joined + (portref D (instanceref f1_Result_8_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_8_)) + ) + ) + (net N247 (joined + (portref D (instanceref f1_Result_3_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net N198 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr10_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_10_)) + ) + ) + (net N303 (joined + (portref D (instanceref f0_Result_3_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_3_)) + ) + ) + (net N253 (joined + (portref D (instanceref f1_Result_9_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_9_)) + ) + ) + (net N248 (joined + (portref D (instanceref f1_Result_4_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_4_)) + ) + ) + (net N199 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr11_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_11_)) + ) + ) + (net N304 (joined + (portref D (instanceref f0_Result_4_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net N254 (joined + (portref D (instanceref f1_Result_10_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_10_)) + ) + ) + (net N249 (joined + (portref D (instanceref f1_Result_5_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_5_)) + ) + ) + (net N255 (joined + (portref D (instanceref f1_Result_11_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_11_)) + ) + ) + (net N310 (joined + (portref D (instanceref f0_Result_10_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_10_)) + ) + ) + (net N305 (joined + (portref D (instanceref f0_Result_5_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_5_)) + ) + ) + (net N260 (joined + (portref D (instanceref f1_Result_2_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_2_)) + ) + ) + (net N256 (joined + (portref O (instanceref f1_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net N311 (joined + (portref D (instanceref f0_Result_11_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_11_)) + ) + ) + (net N306 (joined + (portref D (instanceref f0_Result_6_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_6_)) + ) + ) + (net N261 (joined + (portref D (instanceref f1_Result_3_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net N312 (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net N307 (joined + (portref D (instanceref f0_Result_7_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_7_)) + ) + ) + (net N262 (joined + (portref D (instanceref f1_Result_4_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_4_)) + ) + ) + (net N257 (joined + (portref D (instanceref f1_Result_12_2_FRB)) + (portref O (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename f0_Result_3_1_FRB "f0/Result<3>1_FRB") (joined + (portref D (instanceref f0_rd_addr_3)) + (portref Q (instanceref f0_Result_3_1_FRB)) + (portref I0 (instanceref f0_Mcount_rd_addr_cy_3__rt)) + (portref I0 (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_wr_addr_cy<7>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net N313 (joined + (portref D (instanceref f0_Result_12_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_12_)) + ) + ) + (net N308 (joined + (portref D (instanceref f0_Result_8_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_8_)) + ) + ) + (net N263 (joined + (portref D (instanceref f1_Result_5_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_5_)) + ) + ) + (net N258 (joined + (portref D (instanceref f1_Result_0_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_0_)) + ) + ) + (net N259 (joined + (portref D (instanceref f1_Result_1_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_1_)) + ) + ) + (net N314 (joined + (portref D (instanceref f0_dont_write_past_me_0__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net N309 (joined + (portref D (instanceref f0_Result_9_1_FRB)) + (portref O (instanceref f0_Mcount_rd_addr_xor_9_)) + ) + ) + (net N264 (joined + (portref D (instanceref f1_Result_6_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_6_)) + ) + ) + (net N265 (joined + (portref D (instanceref f1_Result_7_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_7_)) + ) + ) + (net N320 (joined + (portref D (instanceref f0_dont_write_past_me_6__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net N315 (joined + (portref D (instanceref f0_dont_write_past_me_1__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net N270 (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_11_)) + (portref CI (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net N266 (joined + (portref D (instanceref f1_Result_8_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net N321 (joined + (portref D (instanceref f0_dont_write_past_me_7__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net N316 (joined + (portref D (instanceref f0_dont_write_past_me_2__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net N271 (joined + (portref D (instanceref f1_Result_12_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net N322 (joined + (portref D (instanceref f0_dont_write_past_me_8__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net N317 (joined + (portref D (instanceref f0_dont_write_past_me_3__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net N272 (joined + (portref D (instanceref f1_dont_write_past_me_0__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_0_)) + ) + ) + (net N267 (joined + (portref D (instanceref f1_Result_9_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_9_)) + ) + ) + (net N268 (joined + (portref D (instanceref f1_Result_10_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_10_)) + ) + ) + (net N323 (joined + (portref D (instanceref f0_dont_write_past_me_9__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net N318 (joined + (portref D (instanceref f0_dont_write_past_me_4__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net N273 (joined + (portref D (instanceref f1_dont_write_past_me_1__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net N269 (joined + (portref D (instanceref f1_Result_11_1_FRB)) + (portref O (instanceref f1_Mcount_rd_addr_xor_11_)) + ) + ) + (net N324 (joined + (portref D (instanceref f0_dont_write_past_me_10__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net N319 (joined + (portref D (instanceref f0_dont_write_past_me_5__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net N274 (joined + (portref D (instanceref f1_dont_write_past_me_2__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net N275 (joined + (portref D (instanceref f1_dont_write_past_me_3__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net N325 (joined + (portref D (instanceref f0_dont_write_past_me_11__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net N280 (joined + (portref D (instanceref f1_dont_write_past_me_8__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net N276 (joined + (portref D (instanceref f1_dont_write_past_me_4__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net N331 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N326 (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N281 (joined + (portref D (instanceref f1_dont_write_past_me_9__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net N332 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N327 (joined + (portref D (instanceref f0_dont_write_past_me_12__FRB)) + (portref O (instanceref f0_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N282 (joined + (portref D (instanceref f1_dont_write_past_me_10__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net N277 (joined + (portref D (instanceref f1_dont_write_past_me_5__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net N278 (joined + (portref D (instanceref f1_dont_write_past_me_6__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net N328 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N283 (joined + (portref D (instanceref f1_dont_write_past_me_11__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_11_)) + ) + ) + (net N279 (joined + (portref D (instanceref f1_dont_write_past_me_7__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net N334 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net N329 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111)) + ) + ) + (net N284 (joined + (portref O (instanceref f1_Msub_dont_write_past_me_cy_11_)) + (portref CI (instanceref f1_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N285 (joined + (portref D (instanceref f1_dont_write_past_me_12__FRB)) + (portref O (instanceref f1_Msub_dont_write_past_me_xor_12_)) + ) + ) + (net N335 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + ) + ) + (net N290 (joined + (portref D (instanceref f0_Result_4_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr_cy<6>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net N291 (joined + (portref D (instanceref f0_Result_5_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_5_)) + ) + ) + (net N286 (joined + (portref D (instanceref f0_Result_0_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net N337 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror5_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_tlast1)) + ) + ) + (net N292 (joined + (portref D (instanceref f0_Result_6_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_6_)) + ) + ) + (net N287 (joined + (portref D (instanceref f0_Result_1_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_1_)) + ) + ) + (net N288 (joined + (portref D (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net N347 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + ) + ) + (net N297 (joined + (portref D (instanceref f0_Result_11_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_11_)) + ) + ) + (net N298 (joined + (portref O (instanceref f0_Mcount_wr_addr_cy_11_)) + (portref CI (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net N353 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_tvalid61)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net N299 (joined + (portref D (instanceref f0_Result_12_2_FRB)) + (portref O (instanceref f0_Mcount_wr_addr_xor_12_)) + ) + ) + (net N354 (joined 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slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net N407 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net N357 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int14_SW1)) + (portref I2 (instanceref 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(portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + ) + ) + (net N415 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_Mcount_space_xor_3_111_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N370 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int16)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + ) + ) + (net N421 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror21_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/Mmux_num_packets[7]_num_packets[7]_mux_17_OUT7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net N417 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + ) + ) + (net N372 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net N367 (joined + (portref O (instanceref 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(instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + ) + ) + (net N441 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10)) + ) + ) + (net N391 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net N386 (joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N437 (joined + (portref O (instanceref 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(joined + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + ) + ) + (net N439 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In12_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_state_FSM_FFd2_In13)) + ) + ) + (net N445 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[2]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net N397 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + ) + ) + (net N447 (joined + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror1_SW1)) + ) + ) + (net N453 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_0_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/clear_inv") (joined + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined + 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+ ) + (net N458 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_1_)) + ) + ) + (net N463 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr6_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_6_)) + ) + ) + (net N459 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr2_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_2_)) + ) + ) + (net N464 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr7_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net N470 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr3_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_3_)) + ) + ) + (net N465 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[4]") (joined + (portref O (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + ) + ) + (net N481 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Msub_dont_write_past_me_xor_8_1_SW0)) + ) + ) + (net N476 (joined + (portref D (instanceref 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"slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net N485 (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0_FRB)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01218_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + ) + ) + (net N543 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net N550 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0)) + ) + ) + (net N545 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + ) + ) + (net N551 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1)) + ) + ) + (net N546 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror7_SW2)) + ) + ) + (net N547 (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + ) + ) + (net N552 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1)) + ) + ) + (net N548 (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + ) + ) + (net N553 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + ) + ) + (net N549 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0)) + ) + ) + (net N554 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_terror51_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_8_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + ) + ) + (net N561 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_empty_glue_rst)) + ) + ) + (net N563 (joined + (portref O (instanceref slave_fifo32_slrd_rstpot_SW0)) + (portref I1 (instanceref slave_fifo32_slrd_rstpot)) + ) + ) + (net N559 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net N565 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Maddsub_space[15]_space[15]_mux_33_OUT_cy[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_9_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_cy_10_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_10_)) + ) + ) + (net N571 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net N567 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + ) + ) + (net N573 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212_SW1)) + ) + ) + (net N569 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17)) + ) + ) + (net N575 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net N581 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_GND_63_o_space_15__LessThan_2_o1)) + ) + ) + (net N577 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + ) + ) + (net N583 (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + (portref I0 (instanceref slave_fifo32_state_FSM_FFd1_In3)) + ) + ) + (net N579 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_GND_49_o_space_15__LessThan_2_o1)) + ) + ) + (net N584 (joined + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In3_G)) + (portref I1 (instanceref slave_fifo32_state_FSM_FFd1_In3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_1_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net N590 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + ) + ) + (net N585 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__GND_50_o_mux_35_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_GND_50_o_mux_35_OUT[8]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_8)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01212") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_full_reg_glue_set)) + ) + ) + (net N586 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd1_In14)) + ) + ) + (net N587 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + ) + ) + (net N588 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_i_tvalid_int13_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/_n01215") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01217_SW0)) + ) + ) + (net N589 (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2_F)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81_SW2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_2_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_12__wr_addr_12__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/rd_addr[12]_wr_addr[12]_equal_11_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0_cy)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4__inv_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_4_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_5_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_7_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT141)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_8_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_8_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT151)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr5_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_5)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr5_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_15__space_15__mux_33_OUT_9_ "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/space[15]_space[15]_mux_33_OUT[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Maddsub_space_15__space_15__mux_33_OUT_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_space_9_BRB1)) + ) + ) + (net (rename f0_Result_1_2_FRB "f0/Result<1>2_FRB") (joined + (portref D (instanceref f0_wr_addr_1)) + (portref Q (instanceref f0_Result_1_2_FRB)) + (portref I0 (instanceref f0_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net (rename f0_dont_write_past_me_8__FRB "f0/dont_write_past_me<8>_FRB") (joined + (portref I5 (instanceref f0_Mcompar_becoming_full_lut_2_)) + (portref Q (instanceref f0_dont_write_past_me_8__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_0_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_wr_addr_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<3>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename f0__n0161_inv1_lut1 "f0/_n0161_inv1_lut1") (joined + (portref O (instanceref f0__n0161_inv1_lut1)) + (portref S (instanceref f0__n0161_inv1_cy1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net pps_fpga_out_enable (joined + (portref O (instanceref pps_fpga_out_enable_OBUF)) + (portref pps_fpga_out_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_5_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_6_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_debug2_10_ "slave_fifo32/debug2[10]") (joined + (portref Q (instanceref slave_fifo32_debug2_10)) + (portref I (instanceref debug_10_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_7_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_debug2_11_ "slave_fifo32/debug2[11]") (joined + (portref Q (instanceref slave_fifo32_debug2_11)) + (portref I (instanceref debug_11_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_8_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_debug2_12_ "slave_fifo32/debug2[12]") (joined + (portref Q (instanceref slave_fifo32_debug2_12)) + (portref I (instanceref debug_12_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_wr_addr_lut[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_lut_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_debug2_13_ "slave_fifo32/debug2[13]") (joined + (portref Q (instanceref slave_fifo32_debug2_13)) + (portref I (instanceref debug_13_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_0__rt)) + ) + ) + (net (rename slave_fifo32_debug2_14_ "slave_fifo32/debug2[14]") (joined + (portref Q (instanceref slave_fifo32_debug2_14)) + (portref I (instanceref debug_14_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_15_ "slave_fifo32/debug2[15]") (joined + (portref Q (instanceref slave_fifo32_debug2_15)) + (portref I (instanceref debug_15_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_9__wr_addr_9__equal_11_o10_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 9) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_16_ "slave_fifo32/debug2[16]") (joined + (portref Q (instanceref slave_fifo32_debug2_16)) + (portref I (instanceref debug_16_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_21_ "slave_fifo32/debug2[21]") (joined + (portref Q (instanceref slave_fifo32_debug2_21)) + (portref I (instanceref debug_21_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1_ "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/wr_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full1021)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01216_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01215)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref (member ADDRA 8) (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_debug2_17_ "slave_fifo32/debug2[17]") (joined + (portref Q (instanceref slave_fifo32_debug2_17)) + (portref I (instanceref debug_17_OBUF)) + ) + ) + (net (rename slave_fifo32_debug2_22_ "slave_fifo32/debug2[22]") (joined + (portref Q (instanceref slave_fifo32_debug2_22)) + (portref I (instanceref debug_22_OBUF)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_wr_addr_2_ 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr9") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_rd_addr_9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__16_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][16]") (joined + (portref (member DOB 15) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 55) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__21_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][21]") (joined + (portref (member DOB 10) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 50) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__17_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][17]") (joined + (portref (member DOB 14) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 54) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__22_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][22]") (joined + (portref (member DOB 9) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 49) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__18_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][18]") (joined + (portref (member DOB 13) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 53) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__23_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][23]") (joined + (portref (member DOB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 48) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/state_FSM_FFd2-In1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_state_FSM_FFd2_In13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__19_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][19]") (joined + (portref (member DOB 12) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 52) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__24_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][24]") (joined + (portref (member DOB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 47) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__30_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][30]") (joined + (portref (member DOB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 41) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__25_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][25]") (joined + (portref (member DOB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 46) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__26_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][26]") (joined + (portref (member DOB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 45) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__31_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][31]") (joined + (portref (member DOB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 40) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr2_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_2)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr2_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_2__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__32_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][32]") (joined + (portref (member DOPB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 39) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__27_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][27]") (joined + (portref (member DOB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 44) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net codec_en_agc (joined + (portref O (instanceref codec_en_agc_OBUF)) + (portref codec_en_agc) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_n0006_32_0__28_ "slave_fifo32/fifo64_to_gpmc32_tx/n0006[32:0][28]") (joined + (portref (member DOB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member din 43) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/full_reg") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0129_inv31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_full_reg_glue_set)) + (portref D (instanceref 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(member ADDRA 1) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 1) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_0_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_wr_one_rstpot "slave_fifo32/wr_one_rstpot") (joined + (portref D (instanceref slave_fifo32_wr_one)) + (portref O (instanceref slave_fifo32_wr_one_rstpot)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/GND_56_o_read_OR_123_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref ENBRDEN (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram17)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram16)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram15)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram14)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram13)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram11)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram10)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram12)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram9)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram8)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram7)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram6)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram4)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram3)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram5)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram2)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_ram_Mram_ram1)) + ) + ) + (net (rename f1_wr_addr_12_ "f1/wr_addr[12]") (joined + (portref Q (instanceref f1_wr_addr_12)) + (portref I1 (instanceref f1_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref I0 (instanceref f1_Mcompar_becoming_full_lut_4_)) + (portref (member ADDRAWRADDR 0) (instanceref f1_ram_Mram_ram33)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram31)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram30)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram32)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram28)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram27)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram29)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram25)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram24)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram26)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram22)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram21)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram23)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram19)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram18)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram20)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram16)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram15)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram17)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram14)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram13)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram12)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram11)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram9)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram8)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram10)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram6)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram5)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram7)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram3)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram2)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram4)) + (portref (member ADDRA 0) (instanceref f1_ram_Mram_ram1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_1_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/empty_reg") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_In1_SW0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_read_state_FSM_FFd2_BRB1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_empty_reg_rstpot)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n0146_inv1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n01211_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_full_reg_glue_set)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd1_In "slave_fifo32/state_FSM_FFd1-In") (joined + (portref D (instanceref slave_fifo32_state_FSM_FFd1)) + (portref O (instanceref slave_fifo32_state_FSM_FFd1_In4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_2_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename f1_Mcount_wr_addr_xor_12__rt "f1/Mcount_wr_addr_xor<12>_rt") (joined + (portref O (instanceref f1_Mcount_wr_addr_xor_12__rt)) + (portref LI (instanceref f1_Mcount_wr_addr_xor_12_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_3_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01216)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref (member ADDRB 8) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_4_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full921)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref (member ADDRB 7) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_debug1_16_BRB0 "slave_fifo32/debug1_16_BRB0") (joined + (portref Q (instanceref slave_fifo32_debug1_16_BRB0)) + (portref I0 (instanceref f0_i_tready1_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_5_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_5_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012114)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01217)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01215)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01218)) + (portref (member ADDRB 6) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o64_tvalid") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_full_glue_set)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_6_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_6_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012113)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref (member ADDRB 5) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_7_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_7_)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_read_state_FSM_FFd1_In11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_4)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 4) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_8_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_8_)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_5)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 3) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_becoming_full_lut_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_6)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0121111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01213)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012112)) + (portref (member ADDRB 2) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[7]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_7)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n01212111)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n012111)) + (portref (member ADDRB 1) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Msub_dont_write_past_me_xor_8_1)) + (portref (member ADDRB 0) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + ) + ) + (net SRX1_RX (joined + (portref O (instanceref SRX1_RX_OBUF)) + (portref SRX1_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy<1>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net SRX1_TX (joined + (portref O (instanceref SRX1_TX_OBUF)) + (portref SRX1_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr_cy<0>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename f1_Mcount_rd_addr_cy_8__rt "f1/Mcount_rd_addr_cy<8>_rt") (joined + (portref O (instanceref f1_Mcount_rd_addr_cy_8__rt)) + (portref S (instanceref f1_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref f1_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr_cy[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_6_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_7_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_10_ "f0/Msub_dont_write_past_me_lut[10]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_10_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_10__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT17)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_11_ "f0/Msub_dont_write_past_me_lut[11]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_11_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_11_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_11__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/dump") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0074_inv1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_dump_glue_set)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + (portref I2 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT81)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_12_ "f0/Msub_dont_write_past_me_lut[12]") (joined + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_12_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_12__INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_rx/cross_clock_fifo/full") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_write1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_fifo64_to_fifo32_state_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_full_glue_set)) + (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_rx_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Mcount_rd_addr_cy_4__rt "f0/Mcount_rd_addr_cy<4>_rt") (joined + (portref O (instanceref f0_Mcount_rd_addr_cy_4__rt)) + (portref S (instanceref f0_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref f0_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT91)) + ) + ) + (net (rename slave_fifo32_state_FSM_FFd2_In "slave_fifo32/state_FSM_FFd2-In") (joined + (portref D (instanceref slave_fifo32_state_FSM_FFd2)) + (portref O (instanceref slave_fifo32_state_FSM_FFd2_In3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT101)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT121)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set "slave_fifo32/fifo64_to_gpmc32_resp/fifo64_to_fifo32/state_glue_set") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_0_ "f1/Mcompar_becoming_full_cy[0]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_cy_0_)) + (portref CI (instanceref f1_Mcompar_becoming_full_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_15__GND_50_o_mux_35_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/space[15]_GND_50_o_mux_35_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_space_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mmux_space_15__GND_50_o_mux_35_OUT131)) + ) + ) + (net (rename f1_Mcompar_becoming_full_cy_1_ "f1/Mcompar_becoming_full_cy[1]") (joined + (portref O (instanceref f1_Mcompar_becoming_full_cy_1_)) + (portref CI (instanceref f1_Mcompar_becoming_full_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy[10]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_10_)) + (portref CI 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slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + ) + ) + (net SRX2_RX (joined + (portref O (instanceref SRX2_RX_OBUF)) + (portref SRX2_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[2]") (joined + (portref O (instanceref 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"debug[18]") (joined + (portref O (instanceref debug_18_OBUF)) + (portref (member debug 13)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr_cy<9>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/Mcount_lines32_lut[9]") (joined + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_cy_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_xor_9_)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_Mcount_lines32_lut_9_)) + ) + ) + (net (rename debug_24_ "debug[24]") (joined + (portref O (instanceref debug_24_OBUF)) + (portref (member debug 7)) + ) + ) + (net (rename debug_19_ "debug[19]") (joined + (portref O (instanceref debug_19_OBUF)) + (portref (member debug 12)) + ) + ) + (net (rename debug_30_ "debug[30]") (joined + (portref O (instanceref debug_30_OBUF)) + (portref (member debug 1)) + ) + ) + (net (rename debug_25_ "debug[25]") (joined + (portref O (instanceref debug_25_OBUF)) + (portref (member debug 6)) + ) + ) + (net (rename slave_fifo32_state_1__wr_fifo_xfer_Mux_21_o "slave_fifo32/state[1]_wr_fifo_xfer_Mux_21_o") (joined + (portref D (instanceref slave_fifo32_slwr)) + (portref O (instanceref slave_fifo32_Mmux_state_1__wr_fifo_xfer_Mux_21_o1)) + (portref D (instanceref slave_fifo32_slwr_1)) + ) + ) + (net (rename debug_31_ "debug[31]") (joined + (portref O (instanceref debug_31_OBUF)) + (portref (member debug 0)) + ) + ) + (net (rename debug_26_ "debug[26]") (joined + (portref O (instanceref debug_26_OBUF)) + (portref (member debug 5)) + ) + ) + (net (rename debug_27_ "debug[27]") (joined + (portref O (instanceref debug_27_OBUF)) + (portref (member debug 4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr1 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr1") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_1_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr2 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr2") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_2_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr3 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr3") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_3_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr4 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr4") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_4_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_4)) + ) + ) + (net (rename debug_28_ "debug[28]") (joined + (portref O (instanceref debug_28_OBUF)) + (portref (member debug 3)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr5 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_5_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_5)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr6 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr6") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_6_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/_n0074_inv") (joined + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_1)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_2)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_3)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_4)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_5)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_6)) + (portref CE (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr7 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_7_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_7)) + ) + ) + (net (rename f1_Result_1_1_FRB "f1/Result<1>1_FRB") (joined + (portref D (instanceref f1_rd_addr_1)) + (portref Q (instanceref f1_Result_1_1_FRB)) + (portref I0 (instanceref f1_Mcount_rd_addr_cy_1__rt)) + (portref I0 (instanceref f1_Msub_dont_write_past_me_cy_1__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr8 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_8_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_8)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr9 "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcount_wr_addr9") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcount_wr_addr_xor_9_)) + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_wr_addr_9)) + ) + ) + (net (rename debug_29_ "debug[29]") (joined + (portref O (instanceref debug_29_OBUF)) + (portref (member debug 2)) + ) + ) + (net (rename debug_clk_0_ "debug_clk[0]") (joined + (portref O (instanceref debug_clk_0_OBUF)) + (portref (member debug_clk 1)) + ) + ) + (net (rename debug_clk_1_ "debug_clk[1]") (joined + (portref O (instanceref debug_clk_1_OBUF)) + (portref (member debug_clk 0)) + ) + ) + (net rx_bandsel_a (joined + (portref O (instanceref rx_bandsel_a_OBUF)) + (portref rx_bandsel_a) + ) + ) + (net rx_bandsel_b (joined + (portref O (instanceref rx_bandsel_b_OBUF)) + (portref rx_bandsel_b) + ) + ) + (net rx_bandsel_c (joined + (portref O (instanceref rx_bandsel_c_OBUF)) + (portref rx_bandsel_c) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_terror") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_terror11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_dump_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer__n0074_inv6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_dont_write_past_me_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/dont_write_past_me[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo__n012110_SW0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_wr_addr1_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_wr_addr_1)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr1_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_wr_addr_cy_1__rt)) + ) + ) + (net gps_out_enable (joined + (portref O (instanceref gps_out_enable_OBUF)) + (portref gps_out_enable) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr6_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_wr_addr_6)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr6_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_6__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[0]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_11 "slave_fifo32/fifo64_to_gpmc32_rx/dead_lock_fix/Mcount_space_xor<3>11") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_2_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_1_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_3_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_a_xor_4_11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_dead_lock_fix__n0123_inv)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o") (joined + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_read_state_FSM_FFd1_In11)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff__n0144_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[1]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT3111_SW1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT511_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int13)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_0_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[2]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_2_1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT411)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_1_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[3]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_3_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT531)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4_SW0)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_2_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[4]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_3_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net SFDX1_RX (joined + (portref O (instanceref SFDX1_RX_OBUF)) + (portref SFDX1_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full61 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full61") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full611)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[5]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_clear_dump_OR_154_o)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_5_1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8212_SW1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW0)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Msub_num_packets_7__GND_65_o_sub_15_OUT_cy_6_11)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1_SW0)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tvalid_int12)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT8211)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tready_int11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6_SW1)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW0_G)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_F)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT72_SW1_G)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_ "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full62 "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/becoming_full62") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_becoming_full621)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_xor_9_11)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_G)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo__n01213_SW0_F)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<4>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[6]") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Maddsub_num_packets_7__num_packets_7__mux_13_OUT_lut_6_1)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_i_tready1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer__n0076_inv)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT71)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_clear_inv1)) + (portref I5 (instanceref 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"slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/read_state_FSM_FFd2") (joined + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_GND_56_o_read_OR_123_o1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd1_In111)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo__n0146_inv1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_o64_tvalid "slave_fifo32/fifo64_to_gpmc32_tx/o64_tvalid") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_fifo32_to_fifo64_Mmux_o_tvalid11)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I3 (instanceref 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(portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_12_)) + ) + ) + (net (rename f1_dont_write_past_me_11__FRB "f1/dont_write_past_me<11>_FRB") (joined + (portref I5 (instanceref f1_Mcompar_becoming_full_lut_3_)) + (portref Q (instanceref f1_dont_write_past_me_11__FRB)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[12]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_12_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_)) + (portref CI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_xor_13_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_Mcount_lines32_cy_13_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/Mcount_lines32_cy[13]") (joined + (portref O (instanceref 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+ ) + ) + (net (rename slave_fifo32_gpif_data_in_0_ "slave_fifo32/gpif_data_in[0]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_0)) + (portref D (instanceref slave_fifo32_debug1_0)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 31) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_o32_tvalid "slave_fifo32/fifo64_to_gpmc32_ctrl/o32_tvalid") (joined + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_i_tvalid_o_tready_AND_73_o1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_o_tvalid11)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_dead_lock_fix_empty_glue_rst_SW0)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_fifo32_to_fifo64_state_glue_set)) + (portref I2 (instanceref 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slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32__n0279_inv "slave_fifo32/_n0279_inv") (joined + (portref O (instanceref slave_fifo32__n0279_inv)) + (portref D (instanceref slave_fifo32_rd_one_BRB0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_3_ "slave_fifo32/gpif_data_in[3]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_3)) + (portref D (instanceref slave_fifo32_debug1_3)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 28) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/GND_66_o_read_OR_144_o") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_GND_66_o_read_OR_144_o1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram1)) + (portref ENB (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_ram_Mram_ram2)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/Mcount_rd_addr4_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_4)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr4_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_Mcount_rd_addr_cy_4__rt)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_becoming_full621)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_4_ "slave_fifo32/gpif_data_in[4]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_4)) + (portref D (instanceref slave_fifo32_debug1_4)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 27) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty "slave_fifo32/fifo64_to_gpmc32_tx/dead_lock_fix/empty") (joined + (portref I0 (instanceref f1_write11)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0102_SW0)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_full_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_empty_glue_rst_SW0)) + (portref I3 (instanceref f1_read_state_FSM_FFd2_In1)) + (portref I0 (instanceref f1_full_reg_glue_set)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix__n0123_inv)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_dead_lock_fix_Mcount_space_xor_3_111)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_0_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_0_)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_5_ "slave_fifo32/gpif_data_in[5]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_5)) + (portref D (instanceref slave_fifo32_debug1_5)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 26) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_1_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_rd_addr9_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_rd_addr_9)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr9_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_9__rt)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_6_ "slave_fifo32/gpif_data_in[6]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_6)) + (portref D (instanceref slave_fifo32_debug1_6)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 25) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_2_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_0_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[0]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_0)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT11_INV_0)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_7_ "slave_fifo32/gpif_data_in[7]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_7)) + (portref D (instanceref slave_fifo32_debug1_7)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 24) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_3_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_1_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[1]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_1)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT21)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_8_ "slave_fifo32/gpif_data_in[8]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_8)) + (portref D (instanceref slave_fifo32_debug1_8)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 23) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_4_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_2_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[2]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_2)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT31)) + ) + ) + (net (rename slave_fifo32_gpif_data_in_9_ "slave_fifo32/gpif_data_in[9]") (joined + (portref Q (instanceref slave_fifo32_gpif_data_in_9)) + (portref D (instanceref slave_fifo32_debug1_9)) + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_ram_Mram_ram)) + (portref (member DIA 22) (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_ram_Mram_ram)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[5]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_5_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_5_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_3_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[3]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_3)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT4)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[6]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_6_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_6_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_6_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[0]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_0_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_0_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_4_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[4]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_4)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT52)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[7]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_7_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_7_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_7_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[1]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_1_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_5_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[5]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_5)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT6)) + ) + ) + (net SFDX2_RX (joined + (portref O (instanceref SFDX2_RX_OBUF)) + (portref SFDX2_RX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[8]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_8_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_cy_8_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_8_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[2]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_2_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_2_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_6_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[6]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_6)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT73)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_2_ "f0/Msub_dont_write_past_me_lut[2]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_2_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_2__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_0_ "f0/Msub_dont_write_past_me_cy[0]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_0_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_1_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/axi_fifo/Mcount_rd_addr_lut[9]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_lut_9_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_axi_fifo_Mcount_rd_addr_xor_9_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[3]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_3_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_3_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7__num_packets_7__mux_17_OUT_7_ "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/num_packets[7]_num_packets[7]_mux_17_OUT[7]") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_num_packets_7)) + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_checker_gate_xfer_Mmux_num_packets_7__num_packets_7__mux_17_OUT81)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_3_ "f0/Msub_dont_write_past_me_lut[3]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_3_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_3__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_1_ "f0/Msub_dont_write_past_me_cy[1]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_1_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_2_)) + ) + ) + (net SFDX2_TX (joined + (portref O (instanceref SFDX2_TX_OBUF)) + (portref SFDX2_TX) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_ "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/axi_fifo/Mcompar_rd_addr[12]_wr_addr[12]_equal_11_o_lut[4]") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_lut_4_)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_tx_checker_gate_xfer_axi_fifo_Mcompar_rd_addr_12__wr_addr_12__equal_11_o_cy_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_full "slave_fifo32/fifo64_to_gpmc32_resp/cross_clock_fifo/full") (joined + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_i_tready1)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_write1)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_Mcount_space_xor_3_111)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_fifo64_to_fifo32_state_glue_set)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_dead_lock_fix_full_glue_set)) + (portref full (instanceref slave_fifo32_fifo64_to_gpmc32_resp_cross_clock_fifo_fifo_4k_2clk)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_4_ "f0/Msub_dont_write_past_me_lut[4]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_4_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_4__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_2_ "f0/Msub_dont_write_past_me_cy[2]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_2_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_3_)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_5_ "f0/Msub_dont_write_past_me_lut[5]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_5_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_5__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_3_ "f0/Msub_dont_write_past_me_cy[3]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_3_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_4_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o5 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o5") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o41)) + (portref I4 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01213)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o7 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o7") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o61)) + (portref I3 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n01212)) + (portref I5 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o9_SW1)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/axi_fifo/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_resp_buffer_whole_pkt_axi_fifo_Mcount_rd_addr_cy_3__rt)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o8 "slave_fifo32/fifo64_to_gpmc32_tx/min_read_buff/rd_addr[8]_wr_addr[8]_equal_11_o8") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff_rd_addr_8__wr_addr_8__equal_11_o71)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_tx_min_read_buff__n012112)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_6_ "f0/Msub_dont_write_past_me_lut[6]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_6_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_6__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_4_ "f0/Msub_dont_write_past_me_cy[4]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_4_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_5_)) + ) + ) + (net (rename slave_fifo32_write_ready_go "slave_fifo32/write_ready_go") (joined + (portref Q (instanceref slave_fifo32_write_ready_go)) + (portref I1 (instanceref slave_fifo32__n0258_inv_SW0)) + (portref I0 (instanceref slave_fifo32__n0279_inv_SW0)) + (portref I5 (instanceref slave_fifo32_state_FSM_FFd2_In2)) + (portref I4 (instanceref slave_fifo32_state_FSM_FFd1_In3_F)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_7_ "f0/Msub_dont_write_past_me_lut[7]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_7_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_7__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_5_ "f0/Msub_dont_write_past_me_cy[5]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_5_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_6_)) + ) + ) + (net (rename debug_0_ "debug[0]") (joined + (portref O (instanceref debug_0_OBUF)) + (portref (member debug 31)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_8_ "f0/Msub_dont_write_past_me_lut[8]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_8_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_8__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_6_ "f0/Msub_dont_write_past_me_cy[6]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_6_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_7_)) + ) + ) + (net (rename debug_1_ "debug[1]") (joined + (portref O (instanceref debug_1_OBUF)) + (portref (member debug 30)) + ) + ) + (net fx3_ce (joined + (portref I (instanceref fx3_ce_IBUF)) + (portref fx3_ce) + ) + ) + (net (rename f0_Msub_dont_write_past_me_lut_9_ "f0/Msub_dont_write_past_me_lut[9]") (joined + (portref S (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref LI (instanceref f0_Msub_dont_write_past_me_xor_9_)) + (portref O (instanceref f0_Msub_dont_write_past_me_lut_9__INV_0)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_7_ "f0/Msub_dont_write_past_me_cy[7]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_7_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_8_)) + ) + ) + (net (rename debug_2_ "debug[2]") (joined + (portref O (instanceref debug_2_OBUF)) + (portref (member debug 29)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_8_ "f0/Msub_dont_write_past_me_cy[8]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_8_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_9_)) + ) + ) + (net (rename debug_3_ "debug[3]") (joined + (portref O (instanceref debug_3_OBUF)) + (portref (member debug 28)) + ) + ) + (net (rename f0_Msub_dont_write_past_me_cy_9_ "f0/Msub_dont_write_past_me_cy[9]") (joined + (portref O (instanceref f0_Msub_dont_write_past_me_cy_9_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_cy_10_)) + (portref CI (instanceref f0_Msub_dont_write_past_me_xor_10_)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB "slave_fifo32/fifo64_to_gpmc32_ctrl/min_read_buff/Mcount_rd_addr3_FRB") (joined + (portref D (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_rd_addr_3)) + (portref Q (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr3_FRB)) + (portref I0 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_Mcount_rd_addr_cy_3__rt)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full421)) + (portref I1 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full411)) + (portref I2 (instanceref slave_fifo32_fifo64_to_gpmc32_ctrl_min_read_buff_becoming_full621)) + ) + ) + (net (rename debug_4_ "debug[4]") (joined + (portref O (instanceref debug_4_OBUF)) + (portref (member debug 27)) + ) + ) + (net (rename debug_5_ "debug[5]") (joined + (portref O (instanceref debug_5_OBUF)) + (portref (member debug 26)) + ) + ) + (net (rename debug_6_ "debug[6]") (joined + (portref O (instanceref debug_6_OBUF)) + (portref (member debug 25)) + ) + ) + (net (rename slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/axi_fifo/Mcount_wr_addr_cy<5>_rt") (joined + (portref O (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5__rt)) + (portref S (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_cy_5_)) + (portref LI (instanceref slave_fifo32_fifo64_to_gpmc32_rx_buffer_whole_pkt_axi_fifo_Mcount_wr_addr_xor_5_)) + ) + ) + (net (rename debug_7_ "debug[7]") (joined + (portref O (instanceref debug_7_OBUF)) + (portref (member debug 24)) + ) + ) + (net (rename debug_8_ "debug[8]") (joined + (portref O (instanceref debug_8_OBUF)) + (portref (member debug 23)) + ) + ) + (net (rename debug_9_ "debug[9]") (joined + (portref O (instanceref debug_9_OBUF)) + (portref (member debug 22)) + ) + ) + ) + + (property TYPE (string "b200")) + (property BUS_INFO (string "32:INOUT:GPIF_D<31:0>")) + (property SHREG_MIN_SIZE (string "2")) + (property X_CORE_INFO (string "fifo_generator_v9_3, Xilinx CORE Generator 14.4")) + (property CORE_GENERATION_INFO (string "b200_clk_gen,clk_wiz_v3_6,{component_name=b200_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}")) + (property SHREG_EXTRACT_NGC (string "YES")) + (property NLW_UNIQUE_ID (integer 0)) + (property NLW_MACRO_TAG (integer 0)) + (property NLW_MACRO_ALIAS (string "b200_b200")) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design b200 + (cellref b200 (libraryref b200_lib)) + (property PART (string "xc6slx75fgg484-3")) + ) +) diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd new file mode 100644 index 000000000..2ef54e4b7 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4184:XlxV32DM 3ffc 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f88eNrNm8uy3CgShl/GD8D9Ugrv5xl64QiQUERvuhe9dPjdh2tCUuK4qk6dnnGEpbR+AQkpwacsvP0ppb6R27fd2ZsLbtviBdMv2HzBxgvp7NL5790c6fzLU01ZtGT8S35+2+15C5xtf+1O34RW27dg1Y1KyrdYGblxpmi8dtCb3FmsbT9KrQcp59Pk2gNh+d/BytpKoMlDOrZit//sHurdea3X6+TdXstJLmbvfPHOWnPnHTek1WI2PCoeRqUNRhXMdjUqkqlohbHdfftj9/JmflIpaWyVp4NkyUoHIeKByWSlQyz/K/t5lj9hdDa76EIawDM3LAPPnilC6pnWM6tnXh009WzruTnuy4CTUM9nOVNSz7SFm8h5QI8WbvnGcKsp3EI9Fu7ZO2FauN0z4dZ34b589omam7NtMMSbBuOfM8dS/vweXzV6i5e37/mlq1aMR7NUtn6kw69/qAqpQvazKoRtP5TOShmlpKTHLMY2lk7XYseivO9mUOOTE9UUjzjKqfDuQpNjkTg22w95HqVBjRSTlFxGc4YUnRQflXD6oW9xKGrfqhX71iyVrR/yqD0gg4/xLYhKPGQnFPRall7LGM1URvKxrf1obRUrtVUtla0f6ZDKUT20Fd+Uds9piqyQ7FplVWa8+ZPaihfbjbbIDGSK5Fp6rDy+5ak3qoyAgCEVOXItmiTHsPmcJs4UuRZNVmJ4DIVLDHdbhk8iJcVwNyWGFCkphnseWE3Y0MUy5I5nJwXEPVqDk+TMTipw0iAnaXbyEEPh4qQ9SoMUKclJWx80gpTkpPWlDBkGujhpq5O9NoqcDNlJCU465CQpTvKhcHFSlpE8T6QkJ2UZSWaRkpyUaSSN9FmI/0xPUVFdFvYq2LC1vhXhqMKeS+TIFCFU4Qxbe+2iECctFc44s6bH4sbYz792z+JM6ESaXuOKmGYx7lmdqE6J5sXAKIaDwMSG1sPA+LAexhEuc5v1/YbMF3bvF4584egXMnDYUKpwtYr8RKdzb5znWXrvjXOVL7h6Z51gyxoZJ1pZ18pa09l9ELmms/sgcjfO0C+wbfs7zp/j3JzWKTmtU0w+tk7NCwfTbZ3an1mnzAxrfpv4xG3XK5eeHTBt5eJvXMbFPDznY8Mze8dpG57w3uHRi+ExS6hlbxwe/iLUmhXUOvLQ8Lz20EiRbtkvoFZHqBWpVaYTwKYDM8lKhzjd5aKP8+yKY9/Cr3bJr/RtkZU8tSKuONTdgyEXCkVoiMy+jkz/OkMPrlsSKfkCIo3TSKNPA5YFy2EiPWENTgoi0r4kWiBSW4mU7h4wKF5MC1le1yaytBONnkgBGh2YM3rf+NKAZcFymDk7i0UfMXMG6JddMWdqq/KlAcuC5Sbm9ENbjTldZ06HZNcqa7IFf0yDynxjYU7aPww0kktpDvzPTeOhHJVClh54iDceimojSy+GwpgsD6Rck6VBZKnCPnQEkSXv3xp6dLKSpQMnBXKykKVnQ+GRLFXwSLkky6x0slTBDcOJyJL3x1YhJwtZWnBSIicLWXoyFEZkGSxSLskyKwNZnogss5o5URFElrlvRaCYLE0DSOYMvbFbfMaOG5MAkJl7bAFIYegKIMUMkPQxgNQDSL7OjxUTsxMjSHIAyQt+BG5UEz92qBW5FxkoJ45kwJGX+EhfwUdWvgcu8VEfZZZnJq7NT2S1EDD9jgTiI3Au8DEuZncOvM5H5BV8ZEbxFT7q86HheYkambNkQY2c8/eNSmabp6kxjsoyFWroMw/NHVTrjxLE8WGVy1RodCp+hRoRZxKjeTzIdNAiWekQX5hc/godi7MNHSEFKoP7d1KhMdx6gZKcszeGO7ySCo0ju0yFRgx4KdzTS2AXL4FZECjn9E2j0gk0z0SZNvPb1ywNlhkJNN5dV/6idAKtw5WU9LxlAs3XWk5UDGrNicbAlJwoJ8o3WaGcaF4rRwUolLldIuU+J5r7llk0961ZGiwz8mm8m0Df9Eih8TXaxxoTcZYaq6XBMiOFxvdSDb3OFFruyZgZZYlk1yqrMg/gDymYWW+0RT6anJwa5FJajpUPmc86j5WBq5nPGrPCpy0hl17cTFU1ZqxEig+FBz5lTp9IAT6NkRJIAT6NZcYuDnxal6BSho9OVj5lgH4EOUmzk9IMhQc+jQ0eSAE+jU4ypACfRtdONJLp48lW98kQgoFcWUs4fs/W6H4hVwruU+Q+ye6LYyg8kCtz6kQKkCtz3iKlk6tiA7lWtQAqH8i19roIYiDXGrMiyCEnWl+7hrQ25UQnpFUlJzpyLfs91044S36XD93nfKgHnv0NxqoZY+VHGHuXBv0AZ8k25UfZOj96xbXkeI1r1TItGiefl7j2QXCzS5wlb1zJ9xdxdpkNNU/R/nO/7MdRcSucZecbR8W/iLPLJKg5v3BUTFZWOKtTqzIdtE5WOmiTrHTQ9pbL/x5n//1f9mO4/QpnWXhjuN2LOGuXv+w/9fWi1+H++JPX7iuuZccXcK21wLAOLA/WPnGtAxDZJ67tC6sFrrXzb/1ZbVzrgGsBEFIRzLUWKddcaxdcay0wrAPLg7Ujrh1JEOVdoxMGeu1XxGst0K0Dy4O1T8TrhrYa8e6deC2SXausyd0fB0hrgXiFBtkiuRLvWDkm3s6DBmjM3v/WH6fSRmO2E28YCiPiNRop18RrMPEaNXQRE2+vTY9Ozr/1kx05WYhXHUNhRLxGIuWaeDUmXiOGgUZcq+CLRink5PRbfwSY0cnCtWofCiOuNRwpl1yrcEa2etK4VvWMrMZc2zOyBnOtAcFirrWdazW/4Fp9z7X89R/82f/yB3++fZJ0+Uy6ZHsqg5t/TnyFdN1yAwD/VDLuLle5StMcK+Rl+xtXe/Mi8vrlBgD53uFZfRGEJfv6Nw6Peo195bHc1aq/MMFtxPkR+7pEt+mgfbLSQaXMrgjJSodY/v+UfemSfd0bwy1fY18ZluxrP/Wpox+dLNiSfe1XsO8BnBvAomAxzL66r/YMs68E9IkPXmVfGe7ZN6qNfSWwr+i5qoDZV3OkXLJvVi7Z9wDODWBRsNjEvnbwEbGv7plsumTfAzg3gEXBYhP7kqGtxr6sp3NPJLtWWWPfHfwJDW7zjZV9PcgHkmvpsXLEvrInE49GbDmaM/uqRmw5moV9RRgK42wvRcol+2ZlZN8wdBGzb8//+9HJO/Y1yMnCvloOhTH7Hki5Zl8/se8+DDRmX/i2UQ45ObOvRU4W9tVsKIzZ1yPlmn0dZl+H2dcByXrMvh6EHbFvjkwRDsS++bVr7Osv9rmaYZ+rMGKFveTz+1z37dP7FD6Z4P1wn+u0vZVebm8l4sX9CeeSbv2nkjX+0WQNX9KteeN6zl+kW7Kk288ldB+mW7GkW/3G4WEvZnbpkm6/NLOb57jr7a3RqTMxLUl0mw6SJisdJLvloo+D7ddtb42RlUuQVe+KLCs/yl1vb734en1ke+u0q9Vs+HlVS/6UX8GfHFhTgCXBUhN/9hVXTblXWDTj89Fyr6zyJyeyZ43YuKsV5VDZxJ4eKfe7WrP3jSYFWBIshQmzk5dmE2H2nLJcEiYHmhRgSbDURJhiaKsRpuoIyZHsWmVN7sQrGkLmGythUpA5kktp1Tdi0EY/OSrTrlbCGv1EtXGkZENhzJEWKdc5VDrtGjBDRzBH9nw7GZ2cd7USjpysuwboUBjvGtBIueZIgjlSq2E48d6A/mF0IienXa1EICcLR0oyFEYc2TE4K9d7A07MkQHvDTiBCk/MkaQJmuAcKm24eB5H2tR63NRIi3ZMkhKFaFF2kMucJlWdxj7a7UrWGDmmU2G7q53TqG7eJ/ABcXKyJs6RSV0DSjlnWlW/kJsf4ZTPcCrm5KyE5Gzn2ZaN/VOG2upp5220bs7G+hlgL3cmTESb/FP5Kd5idNMDoS+AVLK6YJ2HbuvHwdF6Jef16i7QFxtp9XP/ceMMZHKwIaFk9AkHDTiIkOcjKPovx0YGeg==###4400:XlxV32DM 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1214eNrNm0uS3DgOhi/TBxBJkRIzo/dzhlk4gi9F9Ka98NLhuw9A8AEolVXpiqqe9iKL1i+SAJ+fKEj//FOnsN2KUndIxeWW9nz/9SMd7rbcdFPdYkAN2YGaQNUphy5DFmv9/Zs9MJ+O8H+u7Ki0PEUoGyqR8iihOFQCWlEOZoUt4f5nOuAOZWqBwQjVQLbiSMlDKdWj7uVSS+1qyFv1qHupyU7DMpNvyVc7QxEK+pZ2yrMJBX1LG+U5hIK+pWZkHEriRi5HNTINI3dhpKqZU2KZyUhPHRCkgkb61gGLUNBITx3A2is1I30gI/1QgjCyVCPjMNILI5ea+TAsMxlpW0sGoaCRlloybUJBI21rySgUNNJiS+5BVwH+G+5dDVUwTfDl3n0jYW1CohxlCLYJR7n34QjCrwhpd1M3ezO37effKeqbMfG4/yfF/f5H8sfNLuv9j5LhlsPe/wJvoCD8i+33BzZj0eqOF9Dz+3frNd2QcHzcI7QgCjgRlp+1wKItFm+g+LDcjE66lR+3+3doa8xW7cKCVp5vu/+NvZA15C3e3cBB3Uox3vVS9ksrQ9mZldDhvZqwn6ox6f7fFO1N/azir1pn8pbXWWsKZbj53Zal1ggjpP6FcVQrkLN5v8H9OFGOqkTHlbLg6KSpyhYOPUbn3kdnVmN0hjE69zE6y8Iyi9EZtVDG6NyDEyOtqnV4KL+Azzdlb+GmSh8gacEe9DRAVq3FAHFzYOja5Nu8YO69c9qF5f58LP0Fc3UKGQUf5wVfL6R5IdYLeV4I9UJp43HaZTYU0rTLVLvStMvYemHaZVy90MZ4cVTmMe1baxHHtG9d64Vp31pdO6Z9a22eo9oX1bbqj8wT6CAs0V3Mk7S2eQL32D5Ptk3MEzfnh5edFUqQnRXKdn9lSoEn6uzJ8Zonx8kTo5onS77wZH/mSTx7sp098a96spw8Mf4lT5Q6exK7J+mLPQmXnvgFr4SLZW79CeKG9uz442/1Xlr1DvpXuMl96YNZYGgWlCCWPtjJ21/d/hq+JMLfg/6qtlTWxgIj03EeN+boDaOhPmV6t5jjdOPqXusWc+qWde/dEn+nW8K5W+K5W/Zzt/iLbvkBFrUVuTZ6hdVq5QlWq1phtfpOsKq8iV2GLAxW1T6LrcqAVchThDJgFfIYoTzCarWiwapqsFr3B64OWIVillGgok2seSlgtU6yuok1LzXZ6VhmBqtg5yKUAauQxwtlwCrkUUIZsApVjvZYDm6khNW6pnEjVc2sD5aZwaraRbEMVsFII5QBq5BHljZgFf6fhpKFkQJW6xbCjVxqZmtYZoYDUGESysABcCwIZcAq5MlCYbC6MYRoKqHnzmC1+UaCZ7DaeoaEwGC1DcdGI8qfYTUpBqtrRUMJq4JF/Bk9rqkVmtJ8bDdW9gm1pqU8LjEX1PpsXd+erOvxKb5WkRbyuC9Xa/j7+Crmd+T4WvuCKRNfQVnHdLNjvMYzvtZG7uM1jvG6LiyzGK+iWIGvUYy9qtKAUUYjvmZY9bUeQ0YzfDX6EEPGnoeMO+PrdqZVNsrc81HWLlQs9FsDXHZnup+I15+I1yzPibeDLiffOr+wj+0jAbszAYczAW9nAl4HAU9GnihcWmWHPwNvOAMvY+TlzMjrmZHNZOS/3OZodiqDI2G7mGVrWdtAV7o/G+psxCyz51n21s6+n3f29HxiThhgM1QZe7K1U+1a9O/YGs62bmdb03M4PJm4n0x0ZxNjN3F5ycT3WvHBsvgcwKftwkT9nF8V7MNwx4I/6lbvveRXpfXX8ut25tfSW0ohv+rhzHZq786hay6/MyT2+3vPcNu7DX/1vPAjmL0ttdiYSJ7fYPLhIky2d4WIFa8RsSpt1ZC3ugrXXRwV7YUyaVXbRSiTVrXehTJpVdsolEGrSg/AIsWi4itNc58ax8IdCvesoLNwWCPGenJYi2wTcNVgVEzRNkeNspCJgcnUFKmZqIUy4VZbL5QJt9oooUy41XYXyoRbbRahYFMkW73VwlsFQmje2qFY7lPlYahrYzL55Fv3HkKZLKytE8pkYa2LUCYLa2uFMllYs46yzSePpruYhE8VRzbyaR3KKnwiyy2XySfb6kpCmSiirRHKRGeto1AmOuv1EMpAZ8izCQV9gp/KL7B5A78stwIQM/hl5fxSz0Yez2c72LZFjmNDnudi321oNzzu/e0QLjW+yJYffsHfxjB8+2YnWt/dRjtD8ZZ2bUDod5jaXDK1cpjHXOz2QeWH5dKE/fIk+EzOKmCplpfaFuG9ny/zRdh12wAeWZssrQ1qLd9L2zKay1CL2eyHzsJUjCefTX3OaY7Pja35/PQ5Il4+NqjoT84b3Z2/ACinPuj8+qHjM5XOHQ488onO10W2XLDEDizhYLopWBIghY0ACx6k8AcKhhT+QP7P5wswcG9/ffvbDY+v8Qf06nHu1dx71X5Wr+ZFvUY5ZjMfOqVT9bHESDr6SO/7696vj0O8kVbfG8l9UiP9OGojWVzRYZmBy7jlwJzrqaOnwBhMfcMf3KrS2CtRQQyBZZSUsUfA8GvclTp35fGUjiqdFGL7t5NC8pmKFYSVF83yVSbC/iUmKvVJrTsBPjcneuroKSgdU99gi6DaBnago8RStAU6z0tMuZfYUkdPYYmQ+oY/v37ELTArYT70W469ql6ooRfV1EFHWBFc6/f5qo5WRYOYWjdzZb1oHsZ+aeBY6oeb1DFLbdbeArgE0hEHdUw9H6F52jNzylMxMGup6YIhZXAFpFiFdFB5HKNCKypUlNmzzBzBVNCsAahCTxW60YtOeEiHOEdHN9zVeYULFatYZnFUk/hRDal06Jf5MSHZSULhx4TUYiQc/JiQRnY79cn5hg+Ct8ypydJBIUen8s+gE52yvYZQ61sIZbaPvSRU1ZITQv3Wmnq9lManCLV9IkV87HWiqvEuX4dQWT1FqP0Tnf/YG0iV/dciVH4LoTxCUkBcwh94VIcU/tiEKfyB/O8jFDueNv8UQtWAp2uE8p/Xq+5jLzBVPj4HjZ4N6fwUjcIXoBEsHw2D8oAkaP+eyhKN8jgsQIWjUR7bKQyrhkb5GGgUmNrQyI2XqOQzFXtwNGL0A3Y20smDg8DOnsqSfhgzZPHCROWBIujlNRdhXcRAeRAS1tVSWXJRYVU1LsJbGvlkoYZeVFPH2Uae5JMHFw3aQIOY2riIFy24KA/va+RcvvdeIS7yA1OWQQ15cFHeWGbBRVkzawUX5XESkw2vsHJRXvZRoRIVEheNV1GYWXBRSqwBBBel4XvKosJSK9xGhVpUSFyUIsvMuaiFl3YuSuP1aQsF61yUzRC04KLaYiQYwUX5mFwE9PXIRe6Ri45/Hxe9ebRkXPkYFxX7FVxUt6trLoqfuImkj3FR+dqjpfL8aCl9ovPxY1xUoxG+kIvcW1yUkXwKMhD+WHxr5QymLKbwzAny/zu5qEaIXnNR/sReDR/jovqM+HVHRvWh9ZqLyhdwEfRqY6Ayjoyg/XsqSS4KYz9ChXNRmHjgOhe17wYkF7nBRWFwURgb4Pgm4MxFYGdjoDJOhcDOnkonLsqsPsFFYR7CuGdchHURA5VxXoR1tVQSXLRrVlXjIryFyGdXQg29qKaOY48yz4vc4KKBmmgQUymv4S5yLAoD/cI+oME9YpGLAxrcwKLgWGaBRSUwYwUWjaAwTLEKz1jkkqiQsKh4lllgUVmZ/wKLyjhiLFZUeMIiV0SFhEXFsMwCi1aBRcUOyLECi8o4LopOYFFtMRI2gUX924h6bq5h0XGwgOwDijYWVWbU8iyqzN0ZEF1jzaQURd48o401jXdYKT1boZIMi6gQeE0ax6cty8qdKYkFmaH4a9r/xm7VdqEZXEZLHh1Lar6o0RrTBbaKsBnmrFhEaKkYWfhisHKBpqyz41EmGm4DH9FxZhyvjZ3tr41V1EyeYxbaK6qML20LBp2ZMaLaYNK7fjnebHn3+4n1/sq3OCPcLJzDzV6LLhMBaUVQP9B+q2SEm731oYU7h5mt5zCzcBlmlg/55cUINwvnYLL4+OiwnYPK1HiWmFFm351dZJRZUsd5ulo2XU1dHghL1oklMkJnvXNOifpZ3JqP/bVrVGMV2MLLcWvbux9vxNc+eYg1fuHqIwwf3aOJurwcI5/ur4e4XkbSxRqOcfVVhY/775gW322sh/D99HZ4Gs74p9wfzYqGwWoZTcQU/piEKfwx+VbzX3J/9ef/+Eo56vzkkwkfw++0+Ryg78VTPkQChjv/ZCKN2HRsNB6aFkdoECrEu3ithaatrhMtXuShaXEcIJIyQ9PCeD9KygxNS8oKZYampRHoRsoMTUsjnI1Mn0FmaeUKEus3WI5I2YSCVueDFCcUtDpUYEzmEMo+IrNpnHaFE2rUs3XaV7utGasZ67YwmQezxcFupMxgtjBeSpMyuTWpXSgzmC2NUChSZjBb0k403oxZiyPkClPMdIpZW11hMo9Zi0UJZcashWUVyiTgpKQyY9aStkKZMWtJJdHqYYSm0YZAeVZheqGMvSMxRdhM3lOnuJ3l5vFpcZxqkzLj08KihDLj05KSyoxPS6o+XjczMDSt39Mj1YCudw7qpBJdR63w0BFwm4fg+05D5tnHow/B9uvrH4/+D8C6TSU=###4064:XlxV32DM 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fc8eNrNm82y5CYShV/GDyCBEKIU3s8zzMIRCFCEN/bCyw6/+2Tym0mJq6quOw73QtLlFMUhQfAV0I9fnDWPIMS+/6mMeEyP/XdldL5buKcPyGnHhKMmCB8TXP6kb4KJQmgJB363zd8NKfHu1vbdGnM43RJkTNjyJ00TlijYLJx4/1P5fA9rSg+5iLPZX2IRZ7O/xCJO1xJiBU+fszb7ywz2VzVFYdWxjGM+BH4C/5h+/OLMCdXU+x/O6oc53P5LMOtjPmaxw3dMDylFgDQ/P9SxwberWncbLBardEs4YsLWEqJ1ZVrCFhNsS4CI/+m2aP1vtHZ21uRcrIV3rLmxtc6RvnEkp97RkR256R1HR+9Ijxy1GPHQzPAUqBG3/9cd6rH9AJcBbeBFnviEl2WCi8DLMj9i/r+j8TP9Y/GMnm0gPTPI1Gum3HumOd9FvstscMt3k+/F+BE/F6aQ72e6z1O+zzXCcxfhZSsRFh+1uR13x67NN9Lmf81OYh3Fj19j0KCm+2/w8qCSvBYF6rD/GtMgL8rL6osMiVDC/hu8jjFjmJhiUIl5bAxkUzZUXLQxr0zRqBzJ4MyUFRWblIlZF6BAj0YHsycKNDMocME8iyMKNBxUV01JOZiC9fE5j2UK1seKpBimYH1MVFIPrg6CRG85rC06UwxmCfCUwnoQOYXV2RTWhSlow5kUVs0UtOG2FFbDFAyr01GJo09TMKxuTUpgYZ2xuimsLQ88EevTmaxTOVk3uUcIpqB1k3uEYkqMYO4Rmilo3aQeITxT0LpJPUI4Zn1CRSfrrVKBWQ/J+kbkZF2lqHvPFLSuctRnpqB1laPOFbSuctQPpqB1uPwNQ4NT8jE/hHxsD2F//OEOAQMAtHwcJsS25JHgVGwkCGLhI0EQ6/VYG9mBjgRBzJcwYXqYsAwROF2YShcMNwhmuB4zbMQM2WGGesaNtccNW3GDAckld+QEFRM8BZHflVcUROCuOyBp37jEoFFCkT2hzD2h6EooDFkIqiyIKlp1qBJH4ktUgVf2k9nXjWZfs38xN6AjbCV9RSjnhaPpYI5Ub2DtC74EBFYJ009wQ68ujpsL9SqyV/k8s4p1yl5h2m0dxE+5A6R5PqT5PwKJ6iNRyOg0L0XiDifdbQDucDKOlyNmWgRSEV4WiU94kQpNo3MZ7et/JzM5Nfct60vLTt/QsmvXspXIzuOdPm72uybe+iZ2+x2fH7yPK9lFYjHZqwgfRgLnpjprQVegJOhUIQ90EBC0YPRK0+pK8mRGhLRnRoTEASNGpTFiqmRTGiMSeowKYcRGj1EhjKg0UxQqJlV3YtVt9Chil12wujCoQMD2X2MnLE8yPgEdqo704HsYaypRwzansMFUE/PEWa2W4HwpIT/J+PQbXiJl0hKQWfNnzkQby8RkW76syIV8YlmQWD6YwrB4lpsgbAMwrBhFWNGgTRWYiu3fIyzIA4SNSkPY9JI3pSEsgduoEIRtcBsVgrCKO8BWdyr9ZlCs1RvcutWROKXWsjIRe/vVIml1n7AX5AH2RqVhryOULxn2EiCOCsHe1h5RIdireB6srkmVkgurLgHi9rsPnmileiAGeQDEUbkE4qhcAnFUCBCT2IoOiFeBQCwehgLxUYBYMSBWjGpvCHniA3FBZoLKskfltO4mX0HljpDdLSEfPSGbISEzql37hTjds/NrqPwVIX9ExtMtGc9fkDHOzbqbmysRw1zxxty87a8vUI3mZvs1fjnlurlZFI6YzTdQyjYk8fPnSPxu/eiJP59+LOguAGEE4LP9hgCYAYDDqPMRpun97UgMFi0lprgLANe4aKnR4IawjReYuuAJL7N9xKyvs/eIub+DtddpxNrz8Q2NaIesrb6Xte/f5+2GtVcxYu3Zfc7aq6ywITqirouN0CkKUdsrorZDoracqFfBlGuitkOitkOith1RL8T6M1GrSMKucnQoT9DpypPgbE2Qx3K2XucawOmCrWtZmahDecKy8pPoKFuRsjJl42cKRi9MtuXLilwbFMtKlB0/mCm7/RRwTN5SozeSNQXGYvM/AbUZArXhQL1OTLkGajMEajMEasOBWkjW6ASo1UlCwoBatNXWjVb3eR15G64jbxyoVWDKJVBH5RKoo0KBemUKAWohWHUbUDvlSROn6ppc3VaOZtV9WnvWw7VnzVA70UZTGmrTVWnNUXvmSkFt9vshKlhduACEi3D4B2B4eKwPISuEuwzhpxxB+NJDuOghXPYQPvUQPpNp9nrPm6N2ZnDXk/VXe95+uOddgPqOo22/5LzuL+51L5WX38ZkebHXLU4XG5giqNr/447MzAJqn2crV3YTQOMz6xonQZcmQRHcMgLwQ6ZJEHpInbC1HU3Yx+0CsH1jO53M02DxGO6iq2eLF6vmdwux5r1VOnDkRrvoh37L0R2Hut6I5UYOP1wRFsEvaEPBxR/4hBfv8AkvMPLE/FdUmtwXKq0rwSrYf2ZFGCLsR7voh3kpwk8/A9+mRRrqv+DVy+NxDBpZO81eixJ5LqYVnjO6yJBIeE6c28yUynPCG8eUynPiPBRTKs+BwYMpledAscx6pTZxBqqQvXJQDFPqXjkoG1PqXjkoM1PqQmPup0UhC435VUquXZo5cxgTFxkqEy6C4K1MqVwkvJ2YUrkIgrcxpXIRhMgwpXIRKBsLXqWfPC6lPAe1nhnHWCITxgHrC1Mq40C7B6ZUxgHrPE9lHDComVIZB/IEFnVbSCaP+inPwqwng640JD7BZLGX2udGobkJtIhTn0yp0AI1O5hSoQVczkyp0AKFY0PKbAN5pXym4Mtf25HaLfJUUW3iGsgzI9fAACgq1/jCNcPd9vUNjHlpt/2LzXXCMx3G2I8xRlaMeaaXnz2x11HMcrsNfkkxwY1P7B3vDO7fdEQKHY0P6vl3HJmXN+a3G8Tww4N6x/kJYgwj0pGFm78ii4Cl4wX6DzzhJcB7GBxeYBqI+e/J4p/faxZY9Oh83vxzne8O4vQNWfg2nM6cLPxMlEwWvp3PM3Vq8nNHFoIplCw8UyhZrEwhZOElUwhZeMGsN7IgM75j5/OAEgJROHN4plDmcEyhzHEwhTCHo8FjzOErIPipzH6unc8zK5E5c2imUOaYmUKZwzCFMIfneQhzNINu7pijTbAntV6Y4yAyZw7FFMocJ1Moc2imUObgeQhzuMCsT4Q5mhKY9dBDBTufx6CCnc9jUMHO5zGoCBw3Gq07fj5PnKe6OJ8XCjGol8/nTaPzeevn5/NcRYhuJcTsryHEF5uOy+2m4/35PLVf4sYH5/PmfhdS9LuQev85MOnO58F7OD6ft/7cr8670/Fu/xpM/Ph83oWjN87n2f0WEF4iFTlNbngs73lCfXNDCV7S8bG87Z0AbLe7gu79/dF+NUZ/wUxBIBXhBVgHnvDicXHmwCr4WA/972Sm85SjPUNxfkMTj8/n2Y+a2LzfxPrrJsYpYnQ+z38YCZybKmgd7HwelFuYBB2Q3cQcvZKnrD6tF4zo1hEjOnY+L1eyKY0RCT26lTNio0e3ckY8LVPqbiJUV7DqXpzPi6NL3DmMnbA8KbqHSEnv0Jw1z6WGTdI9RHGulpaA+4WphPyk6M4hUCZtmLhzmD5zJtoIgsm2fFmWz4xzqSzcGswfzItwJ8tNl800rRhbNmtNpOoCjr5AWKdGCOvY+bz8kjelISyBW6c4wja4dYoj7OmYUrcTAW41a/UKtxAdT+JEthPzNJhQWdLqPmGvlyPs9ex8Xp62mtKwlwCxlxx7W3t4ybH33JhStxOhuiurLgHi9uPJC1apHoi9GAGxFyMg9mIExF5wIPaKKQ2IIUby4nzeWYB4ffl83nQNG/RYXgfGcnga7/UltdFpvCcwdndgvO79YtuIh+UtD+v9J0/jLZWD++W4Iey2k3bwGo5P2rlvAqnhFsvNnOqH5+qWb6CL8bm68FK9P4eK7Q4qzuG5OvUNARifq5veaXi7v7qfqm/BuV/sHJ+rA1GjwQ0hGS8w5cATXg77iFlfZ+b/37k6GCuH/4dlXl9oxP8Bm+SDPA==###4352:XlxV32DM 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1250eNq9W0mS5SgSvUwdgEFI4sty32foRZoBArPaVC1ymRZ3b8edwdEQ/0dkRKdZfin0BLgz+XsIfkg5qUcUaXv7tYv1IR7q9w+pZ/MIa9h+IDoLCaiUIRZY7uJhzLr9NDYQYisSVshMZUQT4hriIMu9ZBlFxAKXVuA8FCgo8coSU4Hw8/ZrDR4B+NNtFXUIhALYuFU7CdgLEDDFPjcgFiBRikDAm5fS2Yd8SPnYH3L//U/w6qH1vm7/CR5/7PZXsOmh5bT9FXf5MMlsf4OBkF++Zse3f6Ee6G+bLfsrQJ5R7Vt+EOkFV15AZ+kFveQXsOrydS/XRNfdUMI4l+tCz1MvYVI5g0QlzAsm+DtavHqobAk3+b/4jS5EZbJDGhxy4qFVUMUjv2z/QrPkZLlCooI7zdMtOd2y/RPc8kj0L5ZctJtrLuu5XqArtFwhv4fhua6U4apXyMHO0AZKVdtmWXIFI3vd7KLUAZbyL3RB7vJb9lkcfU6v+bwefNbyYz5ji7jot2vn54PzWlXn7dc5b9LBecj8FeedOTrvv9J5nYdx5NmH7b/Bm8f6W0qjwPVJw4/JP9OUf1b40S7f2QemfztY0msMLXGxDRwYKDTSYHYpV1muqlx1MXAtV1uu1XBP9SpiudKAjFKUq2z1po+tutdWdV/YqvHQqtP8Wqv6Q6tO66da1V63qrMH5ydbnfdf5PyvhG1ncmiA6QMe57kbxlK5g/qvdxbvfuafHFJci0cZyZEKpkdCfEWgW0FbYmqPMStHKsdQ6CmA5vrPMQsTtwAISShSpYzE5Jmd4Faxs9yBnfXO4t1PmN0xw0mx8qAHAxISFTW1onSJtXFBJAZeVthrWXSXyyp3Fu9+5p+3X95KVhR08vpKWhEVA+pqVoSuqaK5IHhW37OINsKQDWIo5ay5i1FnR2Zy0TQXTSUN2CgCm6LWdZ7WCmnARlGUWLPE1BRhpfpZmLFUc45YSmxEA+5YgSdaJIYCiRbhFF4TD7QoSub/QItia1644wUeaZEcCiRaFAVLPNCiNNAiRJHk7GKgRWgnAXKgRVhjBKiBFmGvrrQowaQzwwSyNlJkiRQVPmROfKjwnnljhOia1nSWIj3adsc2JmfrDBXC3QwVtnFmSrdMI3zZtCwndwyaJarJ3wi+dfvfiVYlCtVoU6c86tiJT2o0x1SAzSJshEGxwyQSA0/CJ4OJAzRkJ1eGLLSJ4DbwHu2bdV42ou9Kjy5VX+HeZ998glEJkX6HHqVU61COE2zlhw5lCpGch44FD5b+YNoOXU/iA9sfqBa8ygONpLxwaWvLlb2AJMb6/iBsI6/XAh/s/Q3XiD5n/q5kHoonoXuiMUXonmh0jWsDdC10T7RpYqGrh6oO/jaxFJZ6igkrI/UUE+qN1F2b0BMUFPlaun6Ko8CYFywDmjDnvYwjFTu5MYk6edqXOqx2PYzWU2viqOWtWekjG9fr2JqcipQHjo/8FN3BQCDxxcD9Ewbao4FuO088o4Hr0UA/GuiPBvpqoP+KGnQfr8GDgTkzdzGpTb9TnB4pGvgPVsJ7V5Qcra9zXGPiJrpXGPlzxh2wMw8CJ9Y6klCeVNWNcKjnaa31bF+p56H23qvwZeOa1zLt2+u7Ve8vpwvFyPWX2SWw0kyFUp2n83PkpPkJUVIpxVRBWrTAYA2A2HcO2AyUFJoDjaVCisCBJQOeUkQOzBlwmKKSKQJMBjLnC4l5Au27/chtAw2QvVQ79xKZq0UvF56mEUEaFficeHipBmJBYu8geR+KZTMHsvfBUorAgU4MRTQcyN4HYtTCcyB7H2ZKMXEgex8Meqi4hzIzTPLQ1eeOeSIoGAsGkieW2jFqDmRPbGlHy4HOOEVUHMie2NKOKweyJ7bUluRA9sRmi2cfuCeZU9gFPWlFW+4JRXmxdJA8MaUUwYHsiSltMnOgUVlo3cSB7IkpbaI4kD0x1Ca750D2BH4yYxVOwtwQYNzLzjA8p6wq3FFWdeQNYuOLe+pucW8/0oR4XuUzx0iuh2W/smqBFQF8eMd+/d6qnb6S+ylmU6bL4Lwcpzxtn4h9e5zhjupfI3P6+DqbQFk7XYRoa8TJTCfeX2myx8h3NHNP05MVMX1jpjma6auZ6mym+sPaFChm7UXY1RB21we8oB741tOgy5bBRLmqd4PvTdBl0zUWzGVFHmgMiXmG3wlpCpsQnE8UpTENqWI/v0PTfEhllscWIymc0SL2RXIsMZ/sRUsoDssAoi2g5DtWIM7GIVVllHsyL1BStgtLzOZkJcM8IG1SpgGI89I+FBexuKrd8vDmxZUgZ3paPm+KPXKgLwHsmi0BEEh6fuIrAGQiAYavAIi6AvDm1QoWnZVZYMrMCHNSZoPe+pBEe2eqvZVogzRzRyXmj0qsCBpbBA1XZvaZMjNHZTY1ZXaYxt2HBZk6CjJxFGR6O3zhwdLTftRwcVR5VaJBY643Gk3LMnHBO+IrqO9Jrb0z2V2pNbDD3sg1+tb2sq32qa3rM5q+HCxzNzpNy/kly54pybNBg+l3+gwH651AA1Bnu6b8Yx747lW8INO/UaXhGtoQdFOtIJVVmm7O+BuZpuX6Rx1geSqMTwTiVPErV26zLRM41iqTbsWJiqB4w2ek3pS1c4M9l2/KVV1XkKbfII0ZkCbgII0akKbglHViQJqEU06uA9I1XPlYTpaTiINH0D7osBgcbiqudMGerOm4MmwIKfqnVIogtxKDmZYDE+cBafEd0sQBafEd0kwD0uQcpNkHpOk5SKMGpAm6eTWDt03RlUmKEMt9QhoBZQUGM1UHZYkB6RTCsr5kOYWA5o0D0oQdpHED0pQdpBkt6NJunQafmrYrQYKQdfApUlmWwUzfQVluQBpRgTTrgDSmAmlGpEk8SDMNSNN4kEYMSBd50M/3vFvDAFuRrrGVnak8I+Y7lSeO1EN2On69GLw3gnHkFael3yOvGOjDe0u/+kQwDryCKMlxW8gy8Iy+6wPXmD686wNqOtwISC3daTJ+R0Eu92uiPJJZ/JJwFf3tdBH9Y3wWY32b829C650d6ibW20mc7Uj+/7RYmC3Lo2C9VIVg0vKAwZAe+NrzMM904ef0IA29gygu2x2WsJxravyu9tqX/jzkczHss1dboUJHWSBq38MwBfsexiJUTsKUK/yteSn9qzr8HXka0LQlX/wAXnoJweVLLr5YQpvTHOahbd3nAWGhze0DwkKbCQPCQlvd11CQHtr2KAeEhbZpqL8e2qzvSST3iUKb05bBQ2hT+4D00FY/NFekhzbrRqSHNmfcgPTQttfFwYK00FYmKwoQYTCdPqw3ca9XUtvF+cJDFpaYRzEn5gFhentmerugJJ9Vpton+RyZfFbO3cnn+Sif9VE+y4/L5+nZF85wCmo3a5pFX8dDuLsKc8sxzM3HMOeOXzj10y+c0zNBrY+CWt1/4bwT1LLvoew6WmF4vdLRUpRvnUrt6bk0Cceo4O6l4Ms6etSE6qT5aySVYn/J1lsT/0g0ZcvsTWyVwn+kFv3TWgzbMxpin9lq7pW1gqAJPzr/TA989zLkojPfqazja8panRYwqrKWwn6k4t32bCVjeaqsr3gXE9S5MrmgVk1FZoQEtSp6EmDtQoPdIKh1UgPSBbV2fkC6oNZJDkgX1NrPA9IFtU6jBReCOlteBHU8CWpyuAtqVb9LlmRdUKsmPlUTn1Qpgkw0DOasQyc/IJ11aD8NSGcdOrkB6axDN9akmvgk1qGTHZALQU3edtahmvhUTXyiT8Q6tFcM5qxDp3VAOuvQXg5IZx26ruMXpLMO7cWAdNah0zwgF4KafOqCWsVezDL4RJbXXVEIc0GtkxmQTkV046OEdEGt0zQgXVBr5wakC2qdxIAwQa3x+ANoisfS2Eticlo5f3nu4dm30lC+Z2onPqVHFa6rTZcReDlNYVd69JVPb1DMfBQ1bRsfgm+lzPlqij9+bWtTfNvON4zueRAj2lmO9I9lxXdCfOtPdYEmVJKNdUv0VpUlHsx2Z4mHPpX0gDB6u3B6q2LfBioW3LeX9+/30zFgKtu359Pdesu0fcsJmT8+GbPH6VPf2JM/H4zB7uGUPX8VXj92TEIYfbdt9fwFX836c4cJcF7+xHf7OXzn+Rgxu7vzMWY9+/7JgxTr9KnjMWLR33g8JuGgvD4dk6BHpwgjT8C0koCqwI2Emzwgwb2c9Mt34X3BuRixyLtzMRfb7z7XmrswL20FhFbXnzo+Ixb7ncdn8rx6c3zGuK+pI3Z6Js8tdFImj7RyB61U75bh9IxY2i6OjLDTM1QpeT9C0uXwTH5UD8/MHSxnZ6Dyy9kZcpgytZyD722nV9JEmnPb0lbCfq4me0BnaLIH5Q48qHfLcK5GLKoVJofTM7R3peWIJ2UwR7rLOZa7ZdgwX6l2NpIOz+AbdDymcmoCXc2ogHV3PhaTt9rTa3h0xjc7jeZgTplquKaK6QdnaEIi73TZnZd0OzdT9+7n+Q7ZAbUH7aRZJEs67JeZPbOTH5uhuZ+QwIorG2lSK87w4mgfzexY0mELo5mY5+yIQaoyJEdbVhhto4ltG83gm6AsdU85sJuVb5ZJvu2JscNmmTk0wA2bZbCmCPD8uAx15MKT1nQ+RRzl6RRxEP9nsvSR48TTu8eJV/Wp48RiSX94nPh96rDst7TJfx11kJ+jTav5Vtq06lvaFLjv/wPO9HBk###4172:XlxV32DM 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10c8eNrVm8uO4zoOhl/mPIAuli0l6P08wywa0M3AbE4valnodx9RlGTSsasSV/XBTAMdu/KHJilR0hfZ+f2mtLM3cVPvP8qZu0Wb7uVs8bcs1vvvtyQzqjKLpaixqbOQRVVaUmNj3P2ncakqwXSlnGWhQNFVcfOwWZjDXB2m7lAq5lCgQ0OM0WF5+f1mV4yk/OnvXfVVcE1w+d7jRME3IVYLa4YQmrBWC9su9Tso7dNN3uabvtn3v2NQN61zuP8rBnv/K7r1puZ8/ysneTOruf+nWJUL/RW9u2Ul7/dfpQXKG0WIqR1XPCZTj9nVY/Fja9Dlv3ivF85quf8d/XLzYi4eShMqldbi1IsSQ+xeSxzUq8+2eC1NDFdt4YuboZe1eNklrw+XVbNul42KxJwEHmuD33+VrqWxgxcHn9TEi473f8dSBvK9ir+rSyk9dVkd+TwapYRt8cIi1wu/SWVj7/ySSHF4/wkvVbFEKSGWskigBB1GvRQhrkWIa62kEgIxiQmUVE2ol5LmHY1LPGiXaBC0sLcg7BhJLrXCVmqNRIaK+tnLSghdOruUtr/JPAorQmE5LCwZF1ZY81ZY0x3eWLY3RH0DG68MDlaCrTrK0ZHaDCC4sL3h6htxe8PXN1oFuNyqd4tCa/hA3KLQc33Dbm+Y+sYWjq6BxxrOL5PnVlVbWFP9QB2McNyimWoia9reqCmvNawgc4SPSlrlBppS97ou5dyGywJlFlvdCgG+54NBtxrZSlWU/m6DbrFs0M3boAu8R3xejnukDs/eI9swLQmEfQLrcwnEXQJa9gTEKwm48wRY4K5l9JiA3yWg3XMJ5H0CoSUwra8ksOwT8PsE3P2Zrije4CL+YC6b3os4QTwGXmpkS5vaVvyXach9fiul3haBjCOxrGztKNtRtaOm81854mKRpWhHiUHG5Pat3efToIo/qUe37D84zU91S/VIu2WyvVvytYFxWk6sA3lvvBUna5tCoa1LA5QZFoKDufb3W0yJqKX57j9qygARZY1YY0cHMEF0WCuriNkzxYLSbGamLKAEtIlMmUHxNYqZRFE6+f4DOqj0AmagmaqLWZ5R2aLPbfXALEW96tSxqIwtxCLMUmGcmhhjbtFhnAtTILdo0WZiCuRWVplq45gCucUWZBhKpEFWWIxJjyADC1KiQ0mMKSyKeWIKBOlaByimQJCudcDMFAjSeQxyC9+zIHMNUo0gIwtSVIdhJcYEMItDwRQI0rSW5AoEaVpLaqZAkGaujBkprqKK8JkormJuKGSKq9gzKKwUV7EcG1eoqQx3U1hsGVSRCK7KaBlV2D0rEHjQZEQapyi/wsySri25Ei40HS656nFmcTObWT6aQPzJdG53/giagojzd47T0dQ90NRkwabugahsfFvGm9AXRMmAqE5VRY5xUb/yYL3aUa9y1Gsa9WpHvcaFGPN6TUwZ9eqEYLVXVSwYY/0BiGYColOYH0D0U/48wc50jp2dNhmgHmCn+RQ7p4Gdn9CmGrTJ8PMj7NQEO9VkzKUxYJw8wU4oTixDY90Hq+untHk0FCYzXYJM/A57BJkAa8+E+zIlu/txAvoSZJr6RfUIMrP2ryTgPoXMDym5OMnnbGlsgDAivKRb/ewhW9ZI/yRb+qfYsvSGusSWxi0nbAnd+ZXeCPcra8RbiaiDBTQ6QqZpO1UUMkGtkFlzR8hUZspdHvtTCJkmr0wZkFlsuLJBplklUw4gE6JokOk7ZMIsTtUNMo2bxgVNW2owSwaZdWzhUoNZKowzEmMKmSZzZUBmsUlM2SDT5MyUDTKRLlDRNEgOmXUGo0FKdOiJMYVMkx1TBmQWm8CUDTJN5soGmcaJoUgWJIPMuirQIAU6tMSYLtomG6aMRbvYOKZskGkyv9qATCckXehR9VVQFDIxNxQ0hUzsGRQmCpnGbXuiUR4wwyoYM4SzzStx/I3wY/7kFOH2FJH2m1fhvsMJ/4ATO4pY9hSh95tX5nTz6mTPSgx4IMzgU77EDFGdMUNSS5s1o3SvbJRcA2qf0iWKiOqMIpKaryVwNu0/udPjU7yEE1Gd4UQqfflMJp8lsNyf4qEoP8CJKAOEEeEl3epnD3GiRvoncSI8hxP+4YPP4URUZziR1PRSb5x2whEzRNXXY2hZZAYIZc8MoCIzQIKNGULqKyGYUGaIVjJlY4aQVqZszBCtZsoBM0AUjRlCZwaYxam6MUMcX1yh1HGlwyw5M8AAwpUOs1QYZyTGlBnikpmyMUPYmktxZohWMGVjhqjUUDQNcscMMF/RICU69MSYMkNcAlM2ZgiJKxszxCUxZWOGqLbwJQuSMwOsCjRIgQ4tMabMEJeFKRszhOSYsjFDXDxTCDMYygyoIgHMlBkwNxQWygzYMyhYygxYjo0ZdNhvTK2SbExNIZ5tTIlXNqZKU64XF1h3sjGVlH2cR843ppbn1tEo1/ONKRBxto7OH03UT2xM0fG9so2pOG6RVoVsTEW1lZwb9bruN6ZqI/d6XUe9ZkGMWb3aiSlkY8rx2nO9YKQts8UjZCoKmerKHdIz2lRP3yqNL98qXcaeVYfMHVvq+6tbVeJ8q4rcGF2m5cpgkNaaE9qMsu3Slg5KX9ryOcPOQ9YpmcxXsLNkspxgZ5TylUy+uPdTEjBXaLMk4E5oM0pxrStONt2Ww4a3Vp1CZnG8Fu9ljS4v8lY/ewSZGOCfhMz43P3QZZquQGZJLJxAZhTrl6ropfvsbyWQNqnXtq7YWYPbYWdV8X4opNzuh9pJDDlQ7JQ2T0zZ7ofaSTJlYGexmZnyiJ01ioadsWFnndepOrCz/G2H0hafliW/HwojqS4+Lct6P9TqTIwJdpY4JVO2+6FWr0wZ2FlsNFMGdpa/t+QWGuTufijMVzRIiQ4jMSbYKW3KTNnuh1qdmDKwswQpmDKws/y9dadhQfL7obA80CAFOvTEmCzjJUiubPdDbSeKpgzsLDaJKQQ7PVn6m4oQGQh2ttxQiAQ7W8+gkAh2tnJEihA+AUWIW77JNChiohQh+B3R46entgf56K6S23aVfhmvybo+lnPyFJ2hy3s5tqmYr9m/5oU/GSi1my6t4aLendJ8DS92/XbrmKFxzvILm7M+fWRJ1Kfpjp4stHP73r2m5WsPFpbc9aVVH++Ear7qX8l9Ock97HLXquduHnOXl3JP9VbAR8Cgj3PXyz73BgxePwSnvXtI/TDj+u0oH1CAfZeizHWyPnkgJg9nC5wFOLNwFm/V/ogMaiRXwaA/MFqOrh173OE5cCg9Gfc9mXpPzt9UxUlNz9FJWsUndHLW427X451OvJ4u9/jDk8OT6y2zfE/LvK21X01ZHGA2gSd7f9Sx1c/iOOMP/4r+RC4q8ERumTarojtDQMUhH0HzIB+lvmlXVeQjaPTGR6Jvq1QTwkdJGWJXiQY6FYkm169lPQl4EhmT6GdxnLHnlFvpYRKxPVacF1Ros8Azyu2K7SyOM/4Yc38krEZZxkD/yGqrqpjq+6WaKkcwAR+Bbp9zVRVDXZhaV3+cHLbm2ZBO6NHgutMSdoyozdoDhrkOQQQ7RmF3SGJMkQ7n3x4tNp2vdDke0qtLAHGIv23oe4Z1YaEOJRp7YkzxTPiFNAB5BLytslUxhjmsv21QcjicmEOBxpoYE9RyIlM4QhVRZ6VwhHFWQQoKR9hiKEgKR1jZDY5C+c52K3qicGRwV44SkvtnCIn/NuJ1Ukr5s62/s/kzPJJSmz/1M/PnJ6CUT0HJfhcopZw/AaWz1A9AqaWuXkj9jJPWU05y35d6ushJ6yknyeuclD7ipAQkBIg0ZTgDRJpWOANEMuJW7T/lJLL5q/8pTgrilJP89/VkvMY/dY/imH/E5Z4M8pR/wh/gnzxYZ+1npc37meT8E8bKCArln7HFA5XU+GeSg3+o2vgnx8E/tu+HgAnhH4o4eeDM2s9KnP1McsQhYMB+i9XqCTMQp/CTB+is/Qx8tTPJ4Wchrhr8wEca3sxM9f1STR1rODhqeJMG/ExDzUxt8JNojgx+8uCXdaBB6vAje2PDBNbRIA34sY4Yc/hZSbQMfsb2EkzrxOHuh52wWFCHCD9WE2MOP5k0AIOfsVUESyh1yH/YCQszdYjwsyRiTOFHKgY/OgyU0Qx+9AY/E4efdQiGwc8kyc6QO4Cf+RF+/P8L/IRr8DPpM/hR69fhJ6hT+Inft264a/AzmTP4Ufnr8BP0Kfyk70vdXoQfeQY/Kl2Hn/kD+DES8Aa4x8COrALumWCnqHy5LmewU1Ts/yfhx9tT+Mnf15PLxc0ffQY/6mGE6f8CJSM8Hg==###4004:XlxV32DM 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f8ceNrNmsmS5DYOQH/GHyBuIqkM3+cbfOgIboqYi33wsaL/fQguEKgUa8lWedwRXYkqiARAcHmE0tnHbymyTXnz+K9Sdls2+HTw+VcwET5/erY40Kj8f3n7Ldh9S9I+/gxOb2bdcw923faoH78Ft2yCr6J1GnjuLMTaaVzq525K52nh5fdkVTHy974wsPH2O1s83/KfHyCJLjmDki3SD/jx8+/mG39rmoU/fqy6agTvGr5uiTFoLcSW48rqyBeiXReRtTHprA2lsUpdnZvkoXn8UDu0S7snfuawmp9Nyn52yRbph4rVGx6JPRX2rMk/SgQGIzA1ApV01dAxyUPZbVUJbDXJFukH/Pj5tw+emArG90d2U7Ru0LreVdPicIKh/Lf+nC1adBUcItraNtAQk4BA1poKHGzBSgJ6UhZIBdubNiZTEtCTwmsqDGlcUxFs0WQXD2fryDlRNFJ2jVTU4LIXgwkN2sEgK42tJ42rQRurQU7irwZtM4gaKQaDqRiMaNAPBpdqUJHG1aCCCC1biyL/WtJUtK4odFPY9Oh+VoVpilBalBGrCtsUe3r0WZ0VZXm7jW3rJjbz9mfIgQmx68d/Qt4UymqXi28reld9e8hrPa82zh6Pv/II1KXdl3rY25JXdIlnO6KESbYRrus24rg/byMipGFvQqMumce4ObnT5sRN25z0cs/mlI1IGD1BjIjw+CN4tbG3ovxZLKqVWix2XMIRyU6b2u+S6KZXl76j21rdZbqC7CNkjUl72kZoX8N2EKmiLlpp26Jt44c+0DktcBEJXETStjnNlpWqYTL96DOK5YHkG1u2tLGIc8rAnLJ1TvFohjllhzmFZxDOLRuPBwI8YFN9wPXJd/QgVnigbHM0x6o2SGv71C3nR8+ymN5rz/kUGaev0JA9RieagohEn1t5SrUZqyHXoc0d5pbT3OFldbW5v9d/qc97p5/O5GPeXxzObOez+S9inY2Mcf6LC0BofQ5+/1Tw3pwXDnspeDcJfj0FL3gPPl0Ez14KPvt8Cl7YMXhxHbzh5+B93/DMk3fC2S8Gr2EBpotNybwxZlnufN3zjxxHfpaDBAa1AElvpf3PUxoOn/rulVdKW2Kprqh8aLVP1j55+xR0l8uftn12xz3d/fJnPScyBLRPhlnV56zGntX9rikduTonde/jz3PUTGD2l9ODcv1c9uUp+9L07OuvZH+27s0MyuVy0yARKodtphI4rLkuaZTMQOXVOf7WNITKmenMBtOvUjmMVKfylWgrlcP4NypnoVMWNCFUXpPZ2+WZ+vgd/pSTOCA7BFHxHILokkbJDMhep2ENQg9gzlKgPRYILz02SaNkhpPYGuJlBfPySEVvqwet6101LY4MGCqneH2ugDkSZHGIaMsZX3eKY3gOMmeG4YjydsbXxBQy5z1ZqXB7ePTEFDJnPpDGlMzrvty9pWTOPEbpDTVYyZz3BMOBQw2y2liRxpTM6ynYB4BSTD1+i8Ytg8FC5pyhQTMYLGTObCKNBzJ3lMyrtnK2p2Re/ayKQMm8jlhVRErmdWZ3jgobbONbpBxlK5tTmLLfAFMXDDWS/fssxd9jqUwPH7DUbE9dn1mq7anrHXuqnbGUZLexVOLpA5aaBX/BUi14dQNO7G7GUpLfGHx8kaXclKXkp4K/RijzHkIZgCSgJ2tBAhPWgQT0ZP1W2n+MUHgB7Cj1TyCUnyGUFDcmM7yIRmGKRuIrM9lOZnKYopH8DjSyiEEOJY9SOKERHpqgGdDI4yltEI3CU8EStA2NeEA0ig7P4nBdsAQ/O+k4lDxKYaQfwgxmqDQwLE6UKCdcZJGBHEoepTByUSCmOhcFJB8/aF3vqmkx7t0h+RjkIotaO2gbFxka48BF2DCvvU4N5qliCdtZpwaDXBQlaTxyEfV24CKDXGQMNXiqWMLhQQ1WLgqJNB65iA7AwEUGWcqsg8GxYglHNTVYuQgLwdB44KI0cFHRVsrZBy4yyEVtXiMXOVSwkYsC4SJ5wUXumYvcjIv4lIteqS3dyEX+RS5KUy7id2yoccpF6sbTxL7GRXaZchF7HQ1Kjq5xaL0xZvMaDukwxaHljtISe4+LApAPIFFeMVkCJLJQX9ILSFBfyu3/pVwkplykb8yqfo2LdJpxEdvvWMZyykXmO7goIgMllARK8sRFeGiChnKRjnhKs85FOl1wEUMuwhe5DN8PQ5MJF0VkoISSQEmeuMgQeyMXYWlrF1MuishACSWBkhy4yNHQOhdJJJ990LreVdMiEoChRj4MuQiHFBwi2tIWXyWVECkW6YPFAkIDu8Cio5jCEIucII1HLKLOjliEQdqFGnzCIjsYrFiUVtJ4xCIa/4hFqDFpMHjGIj8YrFiUFtKYYlGrayEWJYQcMWCRxToSlwMW6YAKNWCRTgSL1NOLXE9e5PJ4z4tcZpbZi1z2/Nbl029ywf0ZZdjb9mZm5fxVLijruSWTevfIeuddLsRx+S4XFPRd7rHMrBx3khRoE7ojcKqo69Yedd5dUR/otNa4jgyuI9uroHlpUjV9l8vdEuBdrsqszRlOq0AwW7rxXa45Y/aH9ciGyeUa2B6Mj1Oh0l0WKg9bQj9OqK6+9Bo4nBGdMLt4971wtK+8F+ZWQgfyYhVx1w57btKCh70cVpE5H/YfFTe5Y7MvSvDEn+y9+q5UlDrEl18U59Gwp9HoEM89/8po+M+Ohp/gPU/ixtHwH+D9bDTceTR8Hw31S6NxSYbcijTlfW4V3/ITNv9QK0gBJA1SBMlspf0V71cn/3+vknOa9wnv8yRvTPNHddBZmv0pzZ33uTe/tAW460lfWPnqAsCTumk0jgtA2XEK7JfV1qW9S9kZckzmg6axVdUcF4A2TKCBeVYuAOVv9QIQkiPaegGAhNQLAHeCdXVuQi4A5WSjGgOaQK8GJYJyDSgRdGnvUvaTnOe5w+5nifK4AHBbShTYI8B+7bFJe5egx+O4zxFxElu5AdRnCuPnP7JB7XpnTc1xRFmtl/YHbVUHVLtB3TpPpHNyC2i7Ux24VhxtmVlKPvqNC3a/wsgtM7zmYyGNyS0gD58bNJCPYKrGkkDI/aAdG7WNpa6U+0FIBl1xgyusdMt30pjcD7JBM2jAFRtqJvkwKkBKVtc2jAwnga920tfe1OBkKk5qdNIOTi7VyUgakztFNrgMGnBSmXJFoF8bbdp6d6BfG22xVQX92mgb/6qgXxttC6WBIStF2BMYxnMRVjr7RIefKsa+B4P+yzAoX6rbEiiUjy99WTDGF6EwzKDQ+0+dCJ86712prV+z4HrjsZheZME4ZcH0DfTjOJ+yoL5xNPYXWTDNWDCwbyBjW77KPmVBwECxA/e5/EMuIHmQGEiAhrn9xyz4z9d+c5rFlAXNfWlOy4ssuM9YMMjvuABxOWVB+w0smHeczn0cJYGSHFmQKWRBeWLB48zmyII7sqAi2saCabliwX1kQSYHzRUL5gg693GUBEpDmZjSk+S0uJNNCYxNzCgRbDUi5CgJlOSJEldiq1OiPChRDWrXO+tqif7wjoHlwUqJ4nCXDeraWnIa50CJxwikTj0lZ5USJVLP3qmn5OyJEtNIiYwPGkKJjJFARko8GCpSVxolCnQlDa48UWIcKZEtg+agRLfsZNBGFjwuHWFwpbIgfv8xxsGVJxYMJxZMg4awoBtZ8Kgj+5EFIyrCyIJHrTqOLLgfLLhcsWB6ZkE3qxTKc6VQfBkKw5ehcP1VKORfg8LEXoNCtcygMOhfOhpmZQI1pUN340HJX6NDxWZ0GNy3jMY6pUN/42iIF+lwndJh/IbRsMK/R4dQEJQCSDCBJEGCXwXAooJfc/t/Jx2yMKXDcGOa5Yt0qGd0GJdveVkQp3QYv4MOFZLgipXCgFI8VQqRDlk80aHG6oxHOtTPdJi1nQ7lFR3qU6VQDppLOlRIgitWCgNKcaTDg5qEH+lwQdxiYUqHCklwxRpiQCmOdHjwi/CdDuGZ/X/7fi/J###4568:XlxV32DM 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f94eNrVm8Gy3KgOhl9mHsCAMeCu7O8zzCJVGNtVdzNZzDJ13v0iCWSpT/vkxOnOzM3CTfxbCAEWH3Sf1cw+b7dvfnPzMN/+67eMn9MwtE/TPm37pOe2YWufO32aoX3i829LWeEG/Gf4/kdJ+7y5/fbHtlZ/i63+jKPnjLFrLQXx4Bhvf5Uc5jHbapGmuT5TSyUPs7Or67XE2lrvq11V0py3dIMb03Ej441w3Ah4Ix43FryRjhsRb2AXfCtxxSb+PaWlFuz3L7Udca49cPs6hakKre1dqbHfvuC9aoryPrK8zrXe21e/b6BYb5SSQGk2TikRlEI2g1ICKAvZbEqZQMlksyjFg5KqUopseR312xcYsTosGPCgArbVaksUcFRmDpTWFYWVgh3QO2WgJq5Cpq4orYlZKdAVhZztRSnQFSWSTVIKdEUJZLMoBbqiTGQTlQJdUTxEG72K1lQht2iPyhYZ07CTryxkiim14Q1KgZhSG96kFIgpteGdlAIxpTa8USkQU2p955UCMaWEMY0qpgEE6iB7NDqrmDbyFYRMMfnma1QKxOTbOE1KgZh8GyenFIjJt3GySoGYPI3TuCsFYqqXN0gVu6kZxc9uDt//Koud3Wj87T+lpgLMHHbrKWb36k3f7MBv+vGC+0Q5zRfMYYtxvtzlLIvVu558iu3JJ0B+KJzC4P0bpV3oKWx4l8JcmlQKi/cJSreypyFwk+7cuHL7syx+Nt9RfCOfaZc+0VNN8T3MmuoHleJbKr97u9Ncn4dXpE11I5UN55MlmyP3bDyfUptPZe120Le1x5oKMxKr9cJYzinrrVJ4TqWJasRp2dWM02NNcbZzXYi22aw8QSYYwdQmSMjvJoicD20NTOWYOCsMSdrogdweKMfMcjhmJTdhpc/Vt66e2meg+/tR82jBcKeap+BpLJJvU3Gxl6bimmGQnZ6K1a7Nx53+bX0q5vdT8dHMWzOUvKy1rdGhrlo02Vbfa7VTX6NrI0WfDK0P0Mu3rRFFC/kNYjb3Me+fijmNdzE783MxKxx4FzymCRm8sz347UHw5mLw73gpfS74cB/88szgF6h6e5Bz4vcqphp6bXi9ZLgYuCxwsXApM9q/3bXk6LGem34WP2sDY/tM7bM3fPkcntZ+8/ejuvZR3Z81qivy4Scg2OFrKx8cp8+Nfr4b/QrPV0Y/nUz9eNdJY6Ka4zA8qZNqrsdwfM31kGfq/ZrX4aXrJc+liKWvcKl2a+oshQpgas2jpHTIgflHXA73iMtXZ4QKPP8FBwCWJzSOXG2WBL4yDoIdMjMMMDFzjSKKKGrULYpe8lyKWPpaFwlyN7E7T1HU5QKULTpZY1l7ja3kuRSx9BUub38vvE+AZtY3oj+yw/q5MF6RmntVTd24MRbv9ecSqh3isUFCRdqjXHH0z7E5oCRF1YYGCTQyA/ZrH0dIggQJNDKWjL0wltuANTnRWuq67EgZWRmlQyT3lTkHlhzp0JCxFcaS0de8iQ4gh4kcZu5WnEmHww0dBnZolcOBjFdhrGDHStghNaPgmlA3HL2dJIxNKDSygQXfhH279anduCmPNfXUzLhKbgoE1hKelt8DT8Spz4AoHK4LEJXWV0AUHiM8gqg4mOdxRF6vQVQeXgtR2wlExcE+MfhyDaJwbr4QosJHEAWv3TLCBTYusJ1blx0u0CcF6Sp8AqLEBs/9LojK5gSi4uCeOKrLNTjK00vhKI+ncDS+Ao5q/uggtPVSHYBeGjUcZV41QZFwlBk46rxqcFTvNTgaslA7HC0MR5kX1mqijicP/qkN7ayz9VJtaC+Nmn8ENQR16LBmXochzMdkBL4aBW29BL5aadRkNApXjYzgEWIf75Sae1VNPaBgY/YJnYz4PBcbJNRGRkHGKMkos9PsmBtCJ6OBySgX5obAZJSNMNZktIvWKjLKTId5kA6JjAYmo7wqh42MNmGsyCgV0QGKjBLDTVqVQySjgckob8ohkREfvYOxIqNJkVFamXOCIiNsJwlRkRH2GAlJkRHO605GdVs7p3maN+aiKA8cQ7mARAKFHhKPBJh88RQoveQUKJwCjH9atl9xDbdnIGLgdJOaXcoHy7Bqdz5lj+l57S5wZ3qwyLu6yBc8GokzPvb5tbyv4fdr9f3azAuFw3cz8KKQ1aJAObo/0/NxvsvHnKuKVfmYsi5btwybdYbltQUEyoPFcpY81qSgVEpaeRHGOmlxdsn9yyUwbF/E0AB3WW/YovCoN2x8eFBLskpMS85yWso9LVWVN2xBGKu0lPWGLfVcYt0wPTidTnKD5fTpdDqyhr39S4+psRd/OkFZZ7afSlBBvenpB2hm3bs3/jivbudW1q77r55X4+T66a1WnQn2hVsta/f99LzaPAj+KpSHK1utGrx/4VbLOjuebrWsS7m+ZAbeNIsXWy9ugJKDkpnR/lF6ph77586ra7+50/Nq+6xRXd302fPq6cqWrEYRX7glwxz7eEsWdvekThJbMswzuNLiS0clGKhemuTqW//fVg1Sji1Z6xZU6vzDLRne6+fVUu1bsqltyVrQVG1U59UuCDs6r64DfH9ejVEgC2AUVIIoemmSfFD/P7I7J3dlllIC1wh8QDViCWtspUkxw2hEM3FXRo+0E+lBqblXRaprGxJyBETRnkPecGu37TTS1IjttaPqH96VtSRFMXqCgzYyuCtznuEgEBy0kbFk7ISx2JXV/w+itQJwqsJ9MFjpkHZlbmSHUTmEXVlL+N1Y4E9bB3sHCPypWZC7xmzKIeGPY4dJORzIeBHG4mv7NC0Cf5pKe6widmWtnSSsYlfWeoyETezK2tRuJGXsg/Pq/O682i1nvwYZb//2g2t/DauG5Rf3fR8vrngc8RirxieSxXgRq7ZXYpUbyilW+ScG765hFYLCC7EqfoBVDjjKekAo4Cg7QWmEUoASCNX+x1j1+0+w66jup1g1PXFU7TVcMuNLccnYU1wKr8Clmj86GhUuMTgZq3HJ8DpqrMYlcyzcseOSGe9PsFHtuGQZl4zlasfHJ9jY0E4/hUvMRsZqIrKyOeLEpD7J8DLsZ6wEvhoXFS4xNRmrWckLV42VjGVWGpWae1VNPbikMA1F/m6fuwUaJNTGSlHGKFnJMLoYwyQRH5xgOyaJeLDSLow1K62itZqVNlY26fDdCfaoHBoyLsJYsdIxbWCaSlYaGHeGRTm8P8H2yiGxUu8ANFZHRbtipWHp5BMGzUoMUcEoVsIeI8EqVjIjs5Ld0wNWWt6zUvn/ZSVz8QgqvJSVjD9lpfi8hSXt11jJ5JeykomnrJSeGPx2iZXsHl/LSuYjVgI4sgm4CODIwomULXDBc6h1Rvt/JSvZfTplpfzEUV0vsZLdl1eykt3TKSstr2Al45mLIh8yTVxKipVs/1MUUgQr2Z0XrzqviJXg3ntWMp2V0tpZyfa/VkGTE1Yynrko8jnSxKV0x0pROJSsZPtfnlCYj1nJeOaiyCdME5eSZqUkXBEr4SONhqJSc6+qqXx0ZiLTkGFW4hM345VKtrLHJSrZ/oc8WOogYd6jUtoYJExHJdv/ygaNFSqZJBqrUMnw8JosHd6jUtqVQ0IlE4WxQiUj49fHSke/BeXwHpWMctiOlbwwlqgUnD5W4h81hlGhkskseIlK1GMkTBKVaFp3VCo17Uw1hUQGpSK/7HfrGSNNN8FGP/hSv/rZ7r7gVuBhpvjjL7jLTeemcsoa5VmJuY7Uu/MV/vMjFN+O9n+wXrV1SPzZESU9mtnlwffVXRF5RL5jm95y5SBNZDqQXvpLu/UNju1/oEiNEHPa7scZ87Hf2Nqcbp3f5WPW1qVsGfODr3xXyd2j/83c/RneHj/k7XG49JuUxW8v5O1a/dk7EE2DE7MY+6tf+bpLvG1oxXjZr2tp4//wFy5meRD8RTJzl3jb0EL8sl/XLvgj+ZNf1y5TzUiL3+tlinAZ4JLgYuCSZ7R/+Isc7LF/8E+UCEIe/rrWlOeM6v8AEgRnMQ==###3960:XlxV32DM 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f60eNrVm02S3LYOgC/jA4ikSIrqyv6dIQtXiX9V3iSLLF1z90cSJARopPFE7rYrqYoa0xAI/gn8hIbffJRpnVZR/p++fwkur0nlx5cUxaq9fPythSqqx5sXSsXDjbN5/C949fgStmlVMshhZx9/hyV0Oz9XSVG7pdrZx19hs2uG/1JvRW1mtLI8vmm9FLuiceuW/KN+sdVmS/MRm6/faNq8g5YXEUtTzqzCCzk6aURvvvT2mw6tlW86TvCZl9Z6mmT7OzndvPwjZBuO/v6H8Dqs5ftHkeYZJYvS1qSv9VLs/OyLnfzeNZN8fDW2a8LQGLkmIZp1WMvIijoqQbRmUkVbF6BMKxhv2GxYyyw9vupcNVF6YqfT9vijLnBZRRjFQkZRRt1HMSSL0takrzr2vi7ozsIodLJNEzxtMcTRYpcsSluTvtbL2z/eZNLNsPhxS16aNjHtNprq2oidmdt34z7XtDittUNEu7T+GsnmR9WRGBijw2ZdW4WxMlOb16FVKrVVGCsjwdgSY1iPAA5nTXoLU7cp0BjUGOpwys3hgg4zcyjAeCbG4NDB1tCRTAA4dOBQ47TqxBym5nAMQc0TcziBcSDG4FDXEToLduXPtk5NuzXF0hUuPUY/QeG6IsDKOlRsXZHTY2ztoqhPuS6P8SrEGlcRv/8VvFzVLFKNIy2YuEd79uU8okfWLHokOZPoUSYEnncX9htivcEluGHrN4S9BWXrDWHrih45Qu4RRINhMv3T9oiye5hlbSCDhxIFaIip4TUcwqvUnwuv+RBepX1qeI2H8CqXEV7Tk8JrHbw/Dj5/avBaHgavxDMHr6fD4JUcg89PHPx2PIHd5wavj4P3zxy8qVs50ebD48/g9bp8L0pfhm5UvYR6mesl1ouul7Q2+7dDT/YZaz3ZEj5B5YmBR67Em/4p+qfsn6p3cOmfrn+OjnuY1yn1T3gyS/zunwLnTR1XNfZVldMTV9Xdw6W2Mk/AJXexpc0VLknxClwq8aOjUXmYhqRQMhyXNJ6jVUNxSSOClH3Vcal813Fp2oh24JJDXNJ41BYTgkuUiEpHO/2Ujg5JoWQ4ERGOKJqQ64GfwReezHWY56xUfQEXVV9dUigZxkp2Jq46K9VbgIasYtptNNW1iJHVUachM1jJTggRkWnBVtMhUlTSqCnSAAkzUGnaUWlDkDCISloRY4ZKmnaWoZLG2daSOgRUmnZU8swhoJKeiDFDpTmR8TNUmpFP58wcNlSaEJVUYA4BleZIjBkqeYZKTQvgExgqtX6CIjJUajMGisRQqW3rgUquhB1TQsiCoJQBlDoj2StGmh6Ejc4JZwcWr9torsBDhTBiVJXOY1RBKhab3BVrSPm0wAzvHurkXBPfm/Jt7/8H51U/h8Z5g0EPNppjYQ2izNCQOEKfsczDSPDUhIYDQxX9oc34gqM32gmG/3uLHvd07nu6T/5Q77v2zcuUQllnUWFgh++yWQh3lyB93FMvwe2fx+yg7mC2zJP8Scw+OY1lyvmSrvtpLJPfd7y6hyJB3qHrsu72hXRdmp8v6VqeDP4mhwVxh65L7/wL6brsp2u6Lkq/louql1Avc73EetH1ktZmf0bXMGMjWiFV67T9Grou87Zc0bVQz1rVKPMnk5ZhukPhZRT5hRTeIupV0nJ+0iQRCm9xphF3e+iGtKAU6HFV/u5cBJqdwvu0VE3df43C23eHpGXTdgoPU6fwPmhoNp8mLZtdT1rmd0nLNoqG420UQ1pQCvRoLX9v6G6hIC5zyy9iixW6ocUuLSgFnrTUpJsNxOGWnpacmXYbTXWtws70pGW/D5KWcmhrh4h2af2dDJsfJPEepKDZfqb3lTkkLUsQbJzaV0aC8UKMCYmXvzXpLSHxfiSAxlKHx6RlkMyhAOOZGBMSLzdNZAIItfRzF8YumcND0rKc69Th1BzmTIwZiWdC4l3buHqZCIn3foJCEBLvMwYKSUi8b+0NuCm790lLKd4lLa35NfD0vFylz7cgKuXXQNR0CVH6eRzh0z2IyvqlEJXVJUSZJw4+3oOovLwWoraPICpXTLLlUiClSEuVRJVcleTa7H8MUb8+RVnmzVxClH3iqoZ7cJT9S+Eou0s4Wl4CR9MAoaxQMig5DkcZsSI7Dkd5x5htwFH2xxRl03Y48gHhKDts1p+nKFtHO+tkhZJBiaUWGDVsNLdQ7sRDPJtLMpoGBWWFkkGJ5ySMI646GWWH7LMw7Taa6tq9MwrZZ0MyMqidmBZs6ZwyMMrINnlBbNjepyh9RGzYEIyyIcYMjPJMOsvAKCMyZU0dHlOUPjGHAEZZEWMKRikLMn4KRnCWgkYyh4cUpc/MYQejiRhTMFoUBSPQAubMDIwyZiIXzcAoL6gwDIyyJ2AUjilKKWmK0l6mKM2/SFEWP+mjFKUsQfWHKcrw4LEpXLKGe1ZgLoeTukxRNuXb3v8PzqsPUpRtIKcpyqahKcr9GROKhZFsEjWh4cBTBTy0Qo3XmZQj7QTb03uLaexpofqe7pM/1DRFKWKJIu9TlIpRdvqvpCi9v1UJENtvAk+m69Lq5Y6fOoqIqNPPpij9dqsAIBr1ygKAaMQVXU/LyeDvcpi7VQAQ2+H4sgKA2N5sLwoAYokXZW/kcimUWy5TvWz1IurFr83+tACgzdjvS1GWeZuv6Hpyz1rVqKZPpij9cqtQIDboelmhQGxcdkrh0/akSaKFAjXOQFFAfeiGNKNk2XEVB1OChhQKxMGibf9BoUD97lhXWbWDwpdRKBAHjDaT07rKagcpyrLA7+oq6yigYqCOYkgzSpZVEcSRUYSRklqBGGfaYqsLaC12aUbJspMXf/2r3YRagXYLoLZ2TLuNprp2n1LRf1iE+xqIY2VG6xDRtp8d4yLZ/OzFAnEQfJPgZ0dYmUOK0rv+UzqsjATjmRjTYoGIBRhtu5BigThSrU0iDo8pSr8xhwKMBTGmxQLRRjIB9IfVaBNqEnN4SFF6zxxOYByIMSNxVlcJWuBqVlcJ/QQFq6uEGQMFq6uErQ3FAtGqkxTl/D5Fmf9zKUp7D6JMeAVEme0SovwTOcLchKj8WoiKlxAVnjh4fQ+irHwtRJmPICpUTFL1Uh/A8o5dLvUVprxUl0ujK/MJiPoNVZTRTpcQFZ+4qvM9OLL6pXBk1SUcpVfAkdkQhEY9ZV2AISkOR1gx2DQUjrDeqO6rDkdWv6uirNoBRzPCEZYaVpPzKsra0cE6o56ydnRIivMPoQZeRRmxcLEN85yMzIYUNOopm68uKU5GmbjqZGSxThL/0QRot9FU1+IZbSKyD/54i3VVrUNE28nI0DFSMrI4eiuRG07KKL1GbsAyyoi1m9WYk1EiveVkhHNgMnX4LkdpmMNORpEYMzIydAIYGZl94gJzeMxRWuYQyMhsxJiRESujBC1wTuBkhPWVCyujhBkDBSujhH09yKj+eOvW0lvkIk1zlMt0A4kICv2gvFJ5dTMLtLwkC2QuASY/LdpHeywpZSAiMLH6Qb7WP3i/3eXPo9Pz+u3qOpmTQ16VQ9611Ejpfr3t82f5OMOPZ/XxbMaDQrVgYPBQOKtBHfeMeOwO8RhjlRM8Hreoi9Y9wh5+BNpD9ihMrc2MH3L2eGWYFoKW3YgxC1oWo4sdZavVEIJWX+Ch5i9slnjkL2z4pmsX1mQLS0piWFIjLBUtvrAZYszCUuYvbHtJtinzKlehy1uWFBhNDHnBUpg3ffeLR3vNaW/u/Qtx+i/ZLIk39bPv3R+/ge0tK/Nz+ey4f6E+fDfT90IbPBAzD23teZpVL/QQOigMbfPHUOf2L5ZTyjNuvgh6sw7v/N1GXD3femsDtJ95sOyzsXxqNsYknI9dXwTOWccnjv3eSxu8zsz8pa2P3f+bneCPO2E73Qk6XxealM5sxVsuAd5MvkpLlUKVXJXi2uxPI3/r5O9Lhf8fw1GUpg==###3984:XlxV32DM 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f78eNq1msmy3TYOhl8mu96I4nxOed/P0AtXcazyJllk6fK7NyfwiAMUK3HiypWuKEr4ABL8QV0itHgdL57+P77/5nR8BerfvzsjX4yH928hNRPu6Ps3Z44XPQVJ1zx5cXe+v3HnU7909Ec9RpWPf4TjLL8HnZ/7/mEJ5fkt5PIWJt7/dbY/Nz2uPtfK9x9OudZPHDSdsWs/1ayjq3XUMHiKStbwbE1q0S8T9Dtf0J8LplwwxV6nPLxPy8kbTIM34i/yxp/xyI7g37+k17FXuvzOZ7yfiX4my9nX/OPHn0SobNz5vbUc5/urkLWluCm38GhegZDcO11LYKnZBXNpTddTaw5IcnPpbKA5d0lOen/l0dcXiqFF5ZbcJ0R7IUjAjQDORD+T5ewr942AdwJRCXiQpeVU1yc6D09sZ6KfyXL2Nf9I/Xg8LmxOWbgnqtIc4tBs4GHQHLo9vFyEG3Vt9r2ZDc21d7z6lQeaaUSNx9kdd5YoQGSOEg/dWinnJQoQmbPGQ18613g4Xd1Hh5YcD6dqy3kBqY41tJpCeh9yNeWIxRTVTWGDKaSaoi6dqym6DY1jaMmm6DqcKBu8YnJLjbGMF3dWI3Uz8vO0YzAyFCNlN5IORh7VSHHpXI3k1V/SDy3ZSJ79pXV9X/q1jIjSakoDaQ06vIGtNpytwdUeZ2+grSGGN0yU1JCTiQop5RH+8q+TfP/d2fNF2Slz3lP5h36XFEMFZK3Ih6wVTjZmrXCSS9bi5c3pd+3aseUfHWq7ae3u80Qq8wPc54lUlAum3dme4GLLZLw+KYh2lC2zuf4AVmyM/nOBlgvVhpSfrrkvLwRyWghO/nMLAZsWguTImpgZebIQ2HkhUMhCoKaF4ISFRxy/cFlUszfiz3mDT96gBLzBfsob4IQ9u54lwQns5Bey64md6p9jFzO7BXb5j0bCXhLUoRyu73Pv/znLX+p7MiZNcZ5Ww3QW85lLZ+TIZz6f5emf+v8o9sX636Bbimkm9DmX5lidtTUl5iNpx7MdaTNQtaNuRzDcVkcfoR3rXE5LTzuSHmaDKT9x/sIwm7+p/CSm/Jj5F8IstMWUn6D/hvJTXeXpfmb6mZ2U32fltJPyk321DV35ya78+KUVlJ/ZKT85Kb8wtGyVn+oqT/cz08/soPyuWikkr8UsXWJ91UdkGVQTqq7/dD8z/cxOmpBd3gWa0HbRF+nQbOBh0PyRUrqLvtA1Yex6Kht1aW69w5Vz0IQfmSK6xgldE7KucXTXOGGnCcWkCd3QctWE9gIyasIuww9+NaVpQtpNUYMpiybkkyY0Q8tFEyp9cdqo/FjvwwZTqvI7uylyMGVRfmxUfkoNLRflx0blx7qO46Py471BjMpP9AY5Kj/5UX5JLZKXfaWccXThp6rwa5qPY5rvfKb5wudG/76Kvq2Uuwox+zeFmEKFmP9HFTkmxBwqxNgvW6XEkQ2hO0HFV7lHnd0KKjOsOgOERxUV/3UQJAOIjVKhSamQM2uR+Cq3/bwgASEyC45ZYMDiRsskd30h89eFrK4ecAusFH5aKfrSkwwdVoqyHvTeLff7Kff3lJBbSnrOz+nZ+7MB4YbmmjI1vfQeU+YnAeuWp3LHmjKHpKhLGih5pDzyHFouSVGTiy1jUvw8TQ0vq0lR9KRoW1LMrZukqMakqI+h5ZIU1ZgUFWSyUHNc/tfzWCtbg4cMRt7fXNmaev/HFU35Tv3KEz9D0bimpqRt8ylEDeOdw6OseH8zjtVxBuO62kCuzzL1WeQgCnrG/vI0zEqPNFCyGS4PxHwlNb+/5h8//hS2LZr5hvTCdF3JyqsXXtN4xS2vQXnJY16N8+o9rwZeA7wa4TUTr114beXV6pbXobznY16L85o9rwVeB7wW4XUTr194XeM9b3kDyksf83qc1+55PfAG4PUIbxh4Y53yA6+vvC7c8EZLMF4ZHvJWG3a8sc+pAbd2SLjZioKbr1xwCfMtQeY7Rl6y8IbKSyi5BT5RYP8YmKDAfA9MAPgEYDIBawA+J+BzAY4AbG6BKQrsHgOfKDDbA58ATAH4nIANANMJeMlY9ADg8xYYTVmSPQbGUlb0bg9sAdgB8JixFANeN/HShZdUXuVvcRmKax/jUjS+dI9LAZcBLp3ia4GXTbxu4T3bCqxveT3KSx/zOjS8ds/rgNcDrxt5oajOd4y8bOGlLb73GZqjvOYxL0Pje+55GfBy4GVTfB3w8ol3WYEpq7w+3vKiK7A8H/N6NL5mz+uBNwCvn+Lb5++0Alc5PvByyFe3A9pJDFg8DrARKPA+wKVDBnayAacrF2BKYO8w3zEGmC/AokkscRtggQZYPw4wRwc02QeYQ4AFBJhPA9pDgMXEGxZeWXkNveWNKC95zBvQ+Oo9bwDeCLxhGtAceOM0oNXCq2BAs9sBjdaE4nGAjUKB9wE2Cga0ggGtJmBYkZyaArzOYA3A8jbC6AyW6nGE0Rkcjn2EYQZbmMFaTCM6QITnGRwX4FYE6/uMdaC8x2PeiAZY7XkjBPgA3jjywlZzvmPkXTY5qIUA89sAoyNaysfAEgWOe2AJAYYRPW5ypABHCPA0os1SFdJWBZPjuI0wWhaK+HgKo2Whl/spDGWhg7LQTGUh7JvlO8YIrzmrlcGE3KsOjUZYPI4wnrPCPsKQs6yGCM8564AI6ynCSx1MWx1sb1OWQ8tg8bjuN2gZ7Pd1v4Ey2EEZbKYyGLY+8x1jgJd9O9rKYHdf9qP7dpI/jq9Gef0+vhriayC+euIlEF8zxXcp+1mrgtXteHZo1S8eb3MYtOr3+20OA1W/g6rfTFU//KVXvmPkXapg1qpgd5uhHVoFi8e7HAatgv1+l8NAFeygCjZTFRx6wpqqYLNUheyEJcndAqNloXhc9hu0LPT7st9AWeigLDRTWQh/+pjvuAJTEtcRTSFF3+no1BMV0mIjs8IdcjNjz7zVWa1Hgi6GFOpybSiWYluJy9nEvahLxoD7rl6i54HnavmcG9WXLiLcTWAWQ4B7LBJP+DvYcjZxL6KLQV1M2D03nsPEc25UdrmAcMvOTTu3nLhp56Yz9yJFmABufs+N5zL+nBsVI84j3Kpzs86tJm7WudnMvazQTILm/AtuPKWx59zoIu0cwq07N+/ceuLmnXvJa2bhhnKZhHtudENE0OfcBuW2CLfp3KJzm4lbdG4xcy/79AyqZmLuufGNr/M5N7pT7wzCbTu37Nx24padW87cy/41a8UzOek9N74/Qp5zo1vYTiPcrnOrzu0mbtW51cy97OsyKKLJec+N1ljieM6Nbu06hXD7zq07t5+4defWM/ey/ceglj7/Iq+htQePz7nRHUAnEe7QuU3nDhO36dxjAWLsskfEWkVt7nYQDL5HpJ9uAlYb9h/Sj+0uYO2RmA1sEhk7bBI18+oNgyD3y642awV1/yS01eMeTeLm8S6+5/gfDuy38T1sa3vY1vZ8/9nRj/nbta+lNPUGXiioL/XHH6Z8dvvwerpM5j78WGKqt3+Y3PrZTgHT+pmDfjQ47w/5BrjN6L2DxDbr1R7JQc7WGf/F2SHlNfu+f8lgyfp3uzP/qZoX4tOWL33NNxTnmdl5vFXn3t86zzx0nsWdpx47z+DOk3vnGXCeBeeZ0XkWHGTAeXZ1nhmcF9lS+nICQvH2gwpDdaLe1EPudqoxtPSN+91YBqUvg9KXDaVvs67eMGaWZTOWQ6l/3H5P8WgdpJ6nFnQzNiKZBTZjPezl+GEzNlL4AOynrRy/FPocCv3jdq/Oo/WPevz9yKNlftx/P/Kwd+VhL8cPNX6zrt5w5SVn+350zQbwxdvcZYN1PN9mg/QiiaYDHh6mg2b2Ph/wbYnYuuQ/0D3bp4gv5dp1B6gZmeZ9ngc5J7Sbx6TQZhEkhXSPWpzYtgt8uHMiP546UeM59XjuRIU7MSJOVN2JujtRTU5sejTjgRP14kR+jE6kdXv14sT/A3kfpO8=###3396:XlxV32DM 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11e4eNq9W0mO3DoPvkwOoMGaqpD9O0UAWQOQzetFlo3c/ddIkS67u/p14V8kpTZtSiJp8hNJK2du7Hb/rULsv1HV310YUwe+/GPvP4LLt6TY/d/gzc2y+4/k9E0Yzu8/gmc3KYwo1yK/qd0XHkp1XkqP3zGHsuPXjV+P5/ytGa+/b8H2taSY6+/fPynvZSDef7ZVldvvv+p/f/8IYx2ilAcKJcRC4ZIlRCmsC8WZ+oxt00xKmaxQxNa4yQ3Po3yhlP8ahRGKqxTXKCIQiq0U2ymGUEylmE4RhKIrRReK87oRyp/qPqllo393Kco8vOij/Hv/N+ziJvec700zvAi9Sz/r+1vZy5DuF7VwZQmJsQtL4CkMU4he/b9NoS4Lm0ISGlGQKUi2G0RBptCEuijYFGJkeB5kCjGQFSBTiEETyjKFGCi3ZQpxp9yQKRhsCp3aTYEV7fNbkfpND1MIap+mEKYpmGIKYZhCmKodUg9D6qFJ/U116RZVyyruDanabl3VWvmh6iTsVLUDVZtL1RYVhqa6yt0euevJXT1wl4u7vTSYaSBNy/OlqvN0XYbtoP+yv7KeajO5UWx1EnJQqhr7012roWk1eXqPhXuqfkPTb7IczdD1G0zToh1aDB6e81WLPBel8BvXt/JjQY9h6jEuPY63qIjF3ZLe7/N1GhfCfQp/XPD3o7w6wfD7FNy4M92L8p3sRuDGEy6uJ0x9wqV1wdYnvBzms5ZlRb0zrGWZdJ+GN+5oszcLHBfUfZriuMDu0yYHj3wHl/CmUrOvN22GizDdpSTX/RTPsRqaQeZVXFEzr1wYNfPiKYJ5qUDMC7bik6US9slRCftkziXsU6AS9qloC2y06twf3gAj+xJTjg9LFJqNJQZR5cD6fLnN+5aYwPuv3FPlLDH3MASgt0cBGEYEgHbhP9tFPu4izl3Y7+8i+oMap5fIxn1FjftRjeaoxvWiEPW5o+Y9sQ0iif3o0cyURHiBJNiBu+OTu/km9z+Cm2op6v1ns8py/f6zaXaO9jkqnOroV/2vAKu8+e7rGqXwv/8qr2KjBIMoZcZKac8Ia9FcZW1jrjna56hyLKMR0wtFTI51PZVjcQONEneYyzdvP/hk2xfpELmH7+A7RRMKOPpCkYQC7p1nmQkF3HuhBEKp4Tt0YUhLKBWohLEpWEEVd9uUl42SVA817VWem8pdyMU/91UC33JP35lLnaIIpe7MxT4jhxn9mNH1GWOEVQaY0YMYk0RkhILK9hKhAAoqy+CEAiioPGMIBVBQoXhCARRUKIpQqhg7DOLZuRpA3a38BAigcQbQ/SqAhvsRjw5CpO5gBtKvB9B9PdFinAvrwnY/hFgNIbZGVjF+n4iwI35+EGF7/PwwwqYvRdjdXkbY8BXX7M5VcOKRzf2LEbbJ+izCZqa/75H90SOXkDS4i0fuRk8BsKe47w/c/Yzf8pG7Dw/oe4hEHqUojlLc7giYl20dYf8CDo/bkk49APMrba34SZTk+QWAyOVw9m0l7foSQOhvAYjwKYCwnwIIczDXeAEgMlMvMFdxASAyY98FEDwbCAG7pY7ebISCHL0xhIIcvRGEMh19BSp1BbpSyss9QIlnMOJzVGQ5rwkKWSzMWigEsjiHKAiy9DzDnHSgE89gxOeoTDqvCYpdHAihLgxjl30JQc+gW/mMoGs1IhPsYiWhIOxiGaEg7GICoSDsYhyhIOxiFKEg7OIAfVS5Y+wyj8nNm4xNVTFh7OIBR/kOHX82p1eP5I25QeTBXPTtATDae86lT0NAjhXkHgv3tAX0GQwsYJ95GLf3uUG01cgwRNodMsyprQDa8oHYLYJIZicUgEjOu5EUKMBtLrIlBSSPsqV2OErtpIFoAsepHcjyPQNkDueaiWwokNn5JuoVfRLfNfiLrQa64TkT8ZzPhHN39I/mo3D+p8mjy7CuDSXo+KYZoiC5S5Y4oYDcC0URyvJYm6PcwGOVFWhCmR7r7y7EvlcAKm/hxg2oayZlgyAAlAq/gMWB9Jyk2dcWEE6QoHcodUfQHEnXzlzeBHO/VRoP5oU5bVHDm1bsQ7QneMt5K2QNOo/jp595X84ZgB2DwQ6s6pMYJXgzD4Ftjt3/CbtBU/UJgiF4xxF4g9KMvCV11VmSZWeP69YcR73n1y35cRY3l7y/UDr+KB1PpLN/IB0qlHhc7szZ+Pw6oXB5mMVO0Xv/OqH0Mg3NUmOh+M9NZjuYTDquG5ilF0pnO84COnAvlI4+SicR6bjPpSMP0smHdUMeyscXSafCvHrFvf9sjqcBufYqj5HkcC3OUbG2eS3BtQ2uZQwCy6s0qzOVgkBg8+OLgkDglOV759sAS7vWAYsQLiFyf1Cx/qCaFDmRWo59GUApi+7oKLmVJJsCaKCyCWCMJIdrcY6KAOa1BNc2uJYxIC3b9GhmBEgFb7EUZg5xztxHdeZxLc5RnXlcS3Btg2u5jUYBbr6w7+O5IcZtiTEicl9Yq8+UmySIcSNVGa6ApYhDjN71bTpEQRB1OtP3saW+DOVhGXtEZAQ/y03AUnkMOsvfsEARJtY1nZtFFAQoZ8Sb0h7LsGsZAZHHg2MZBpaBAWV5RdnWoMhWi0kARep5rkMReYoccWl2wUAKJfcDlBwpMHfElv6APnHKy5IM18xsfalUJA6JrJHZ8mcV6wcIBIiGNXM6zV/ZWYBkYgIOuT9mBg4Jgf2YELBfryh4nBAoSxRXNRxlHpeo96tUzH6WeRFMXcKA+CiBQ0bg6RDEVL6CAVE+zkLTZM/P0tLJ6qRYnZV7nMXSaKeP2TGkRXXUor5/GCBZCxPqLOOk7KPSrCZK++i8tB8nthdqvcQvcXuRWmuErp5jK/6nmlGPslXVc5RI0qWHs3l3D0n17jlKJDixbXq9xgcHp2ZMwKcFmMZnjBIJNQyiPJMjt9Lvaaf1MjQwTR6+t9rR8L1sS4iMIxFrBSX53m/vnQJMkiRMc8L4Hgv3rE4B1kLhusfAPZCYKXwi7MHgxEyheFgfjW0MYEX1IHPfEfYtBSKjqlFhaQkFkiXl78VSkuYYNitljYKbY9jGCGU1xzBpCWU1xzAZCGU1xzBNuUG2sMyjCQWyhc573HDRRet7jNS1gyre9C1BhOQzQmocIemZ/OQMfog3p0ftJ07YrEHe05NqSK/zxkZe+fwQXzjLduWCQnjhLPrqCBX86yLLlj88QgX/5KmbNc2fnpzC/mK/rOvLYMT0xkbCaIORhpEiZ6PuudrrVFsO0dmovjSLgs9GQ0jvne9wpeXadKU6IjI+GyH3Vm7HZyPki8x2cjaaWxwhxEgYbTDSMFI0wGiPeD8GGODdw4qRMNpgpGGkaNBZ3shIchhh2iEKcdjLhxpBTg5MG0RZJ4da0NlUcWGhuLAILkxMF+b+Q77x0bed+7QPasLtILadZAkzHybOM8/3f5QrSMTnchaK8b8WSFvO7TJXWCc8nebJzGHZC7sqHvP82V6+WptTlzVQnl4+l7iqMvL48rnkVc2Rh5fONVuYWpFObbP2p6AyqKAyqASMJK0MCigIKUkrg6ubRknSzJQF1D2VOPdSbT2jLKigaKigaKgEjCQtGq7mGSVo0VBAp47i2MfgVhx1qMkJqE0phn0MbrhRjJa75FrBNmt05dqs0a32I7Xh7ES5CUqQNbuCshM8M9F619UN+nRqQ0N3W564LdxDTFIQp8WrB7925c9wl6i59Ffbt1s4UnObknqo0Ulx0rLn9WUD9dlBs7A/dlBDAkPrrzRq2Os6HGlPiPbSIcoX9De6SxcoXtDfOM6fTeWzl9HCyGFH0Mv98+bZjGhh5AiW4AxK+5WC30UmEIW8i2y1xVnyxqU8X6mq3lFgrnP3AnPKq2vOjBeymtl8IRlDZJIuZBLxxWcxzmapvDLqpfJ+zzqVcVhvvwdOZc7v88MED8/1lvaUc89CloOWhzd9m2/6/vCmP12v3q9f+U8a1jfSsG6OKcWPmuU4zjFelVfzQOk5Hcqr5sHxiEvH417geMSV43FnvWPxqnfsIfe1HTwQv/JA1nzFA7mnMltFavzSA/lve6DU+lvPO+bdtzrmD21eUV56uld0zB8huAUZmRdY1vGrAkiz6v2pkEaSqB/ENnXxdVDW/luxzV9YlroExfoFlqUPUnMABOxTlvXxhwetK+UcZavvh06IKXUb6ITew6RpwQYgbARYGyWMAP5GBSNNoG7Kq4NcEaibsoLpFQREtQLiir4bBMRZTSzkiMgkh5sz4ksytzlBQNwgICqauQW+/Z7VSJfy+giAHPILZYVgCTuRkJWFByuZZGXnZ46DstrcUl6t8vyAI1bE5jAZX2Jb0ESA2MQS247IGEew6BBfktNtDctdbALExml2F9bb71nZ3Q7QpjFNWAZntihhBGe7qGCkyTku5fWFhiantZQ1suUpFT1VgGHObLbMqcGcQGEO7zCnECLKMA8zGZ/06VaFVbd44w7wj5r4JxD8Q+HOdYIGvip4qKg++xEBpK2PBdVPW8bWlDY80TLGsw1XGEfOxu6s1GuSQXr7MBlUJjxPBtEAdYl0Cr64Qh5yxqPMwmuSJjZefVcg2cvlZpbc/gfcizTp###4660:XlxV32DM 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121ceNq1W0uSJCkOvUwdAHDnF269nzPMoswAB7PedC16mVZ3H75CwsMjqypjFt1JIT5COOjpiQg2PaJ2x3+C18c/welH2tjxH2n345tL4RHP8/gWHHtsIqjjWzz5Q+aWf0tpHuyRJfbhojqOH8GEXHH89IKzlEtb/o99fAt1/NCHtmUIqx6Cad2H3Zwdw5oyrJ3D2qNUuDJsHv5sw/PEfS7tePhzaG7b8Dyx8HwNivXJgshjn6yM+bdMps4Rmaj/jlaOuUxc5jJbn0ukMZeUz+fSYC/2S3OpslKB59rxtuQJv7It2W5hXQvsuHm73dI619gjEd9ut3O1WyR2i1+127msxfJhN/1Wu/0ruC4S+/FXtmAex8ojl7gbpXwGRp2Hugh10MMkqGs9vpf//fw3/7usQ3w0Sdbj+K6yuYtEBSTJmhVJ69Ps+9HGLX3+qnXZQlVsBBK3jpK1jn5IcvNs4eO7TK0P32Cy0NSQ+bT//Dcmj9af7dXX30t5/aPOQ12EOuhR9Ox1rcd3efa1WDRxVVZG3SQOlhFhlQ5WqSMSt45nah0NrNL1VQbTVgmWKerWVTrb+igkaaO5rX4ArM9Tb9F86WWJbaMpDRqcoKCeCnok7kOKMiTzDA2ZL9gy5NmGlKC67qrbvkEcFHRdddvttCFJm8duTQLflgmg4D4V1EjcO4rWEeyUmzc1ZFmzdc0YuWE8hvru+FkPpXzwfCjzfx//BC8eW1D5PJfjycPZz1zSx4+sXDtzVre/p8RnLo/kLu5kXPFsuJN4mj8+0GAu58lRFMYgCfpIBZsHznlqfC7xaGD8egvGi0H0MEicBhkG+JFPd9U1n//FIDze3nfq/3Lfta8pLjeVRBJ6U0XcZ95U7fKALmDRYh2ZzfDI5zE8uAL7mGGfhO0zPUFU4ShfUNX6+iXZAA21KQ1db+h6Q2fb3zBHNOKYW5BvkPY39hFj75DmyKaokC/UT/asfkx4z1Qaeybf7W+rgbC/1YzAR/m7/nZf/K26O5BbfDtOsetcdsy1v91ufrUbhd37V3GKvsXF59vt5u5w8ba93W7xJS7OE37RbuYWF4e3283f4eJNvB0X85e4OE/4RbvZWz/h3+snsk3AJebdIrhNTmDmBurIdYA6BBIT3CYB8ObmBLex6WA0xW3SIQnCbeNw13ksqOGnGgyJETrLjQCR5uYEg7G5ZkVhgNRIQjCYBH+aPcJQw4AaKiExwWASEGlujjAYCUkMhBUKQg0LdRrqIGDh0MNAwMLt4ujBNNwujh5LaEgC8NR4gJp8WntHYhKSSDBAbk5CEpbQF3YTkhgIKxSEGhbqNNRBwMKhh4GAhdsFm2R8kbHJ+bAPwQCb2I5NPMFuUk7IwSs7oiZYOWuFnhXuuMIZzLBE5YFh6RXxAKCT/5oOdGYPrUsPO3vkrSoVflbI44qNcsU5K/ZaETtYWkBTkP2v6n/1Ap4wmqpzhameYbViqmc4xlsNZ/3o9wzFWak0TFNLU62X4qwoxpqIy5emGntb0W+/7NbXsGGTgZBccl6qgW6ji45uo4v6WO5heyxEmaHb6KI/CGNm3W2IY74Y4pTR4x2GYvt19N/1Yr6MrChq6naW19HtSZwXsrNc7byvdt6Oq7+jdhbUAXq+qjZ4Tn1d+GboJ6DW/dTrfhqyn1QT/ZwatekOArLt6xvt3fLJGzXWG5988uflkx/rXpbr1+WG45YJnoeErNvfQTim37DudXTLxrrP67qVI+v+42UN1yuL67HgUi3wfRZYPkuphXiCM/e+k0ipQRuzI0khU7IkNokmksISpcYS6ZNIwGc2zzjU697NAh1ngYSznpJwFjCZ9RTMecBk3lXFe++mfTwlEjftg2vacyIp2ocG2bQiEgTztCMSXSRNDU1HU0XSIMmkc6pEFklfFMxjE4WGvvTZah8Oi0oD0TVdPKzMAvvoJ3dmsZjARyNh8L0uvE1DaL7K0M42BtogsFn5zdlGQ5tiFusnxTjbKGhTDGTbRkxCp7YpBrJtIywY1S7EoQe87U8wkBu7nrxA4rbr0i1wtkrKkqVdEKA/MZzFNGSVlOVJvWD0KimLkmoJIqqkLErKSlAmRFB2Y1SCUrCw59iL+4efqG5zYTBO4wZKkkI0wRaIJji66ScVhZHZAGQDhw34RVHXxgB19ZHP4zVXtekFTG3VIYazt0yYUJ0kVpod9upS0wSHe1UCwa59X2DXzgF2XXkvQF8xFLU5upKFLLHtBkGsmDgApSbZhbcQw1HsFlKTblzlVt1d5foegiHHJFgll7HL3EaMbCAV6vYxnw+fusyhxzJ9eIkABUulrcR6dLQa41WPxUGODf/MUeYR3JL43XxfrUzX1Sp/Z13/0t3nXWTLLm7h+G/Idyj/qMKfbWne4S2tU7kIX27+YtuCFGt/Y4376wTVgRJzdRwVE3+fuU6zzLLLsSlXcy3A+Tc2Ja2zDNSmnqzFaAKg1QqgNUHDn+DljbwLYDWdQzQxQxN2/TwMPXyvAiL/i6fx1KsCdmwre9O2FtRmGyyqp64itPpBjZKBksaoLXuM7uSbZNIdWZKGxMXmIGub5iBzkUHHTvrUXW/gIfc2SIzYkCzpwKA2r+ChzoDQX/VjuI2BNoAD878DaaOhTfGuybdxNKwhde+aHEaR1VwVMVZzjZKBkqZZspHwrCc+n+kCxVKbaoMFK4wvBa+8EcwVzjFXLxko6Vr6Xv5XRrQBzxXZ4M3yXBGW5WBrFGyNc0iMEGvuyIkEcGmWqCFJFtOPgsWEJDhtzNwJo3mcNhbMByRpGtjYJJZIADCijHGTAEzMEkkkAA7zouloAAlzn0QkAAmzMaGPAeNlA+eLOIvPNKBk8fblY27SfF03Y0TUmYA/a4lk5pP7uip+HFJXBbwLUoRvt+K4jedzz3OQn/8Dbs51FHfuONEMpJIjyTuCf4w9PqOd/Eo7Zd/n+S5WGmTEoDKNLPWeP4gRe8c7rsF/yjVcolS3emOLo9RqobZPRUkcbe5AlxcJijY3FjmRwH2TJZJIJkO7Gzoa3C0bh3i3ScbdUrcvXrbPj+2T5J2AQVC6E5X+U25TAbdJwXXhScuuyRuGqOj3G7sWPt21yQm+ohSqPYapJHlfskMGo0jQRUE2S+KLgmyWJPHkbuhocFGQzZLoosj+WXhdmPCtZOk1bNeImU5FmHD7q1n68znPDAEPIrcjjm8+TdKfT2OUNTcveH3JIJ/k5qPr7GtuwwDm6T+CeXx7mZWvU/XQiCI8e5OHzzrxRe/BGke/X/WuYPL3QTDnK9Qe7HF0+o3Wca9y73WqW+tQo4hV3REZ+O2NRlmB6kivR6feaJTwKrFep/rskxHLJ3Oueo/BvHijdda4aSTRo5NvtE58lT6vU/3aJyNWdUeePHr+JqOUqEO0NGW9b1qEUU7wKCkoCShpKJ1QGtFJ0RpHJ1yK8YpQGJymrbf2lOC4pZvwo43bApNS1wMT4QQS48CEbwPOluY4HOH7HPLEadr+nm4YoMUMxQCjpKAkoKShdEJpxBt1mSjeEF6gmWlUwfDMNYKoM/eSgpKAkobSCaURfdSZUfTRz+lH79fNGKYZORKjJw65kQczBsyKZzNu0EeQGEM4jSTkaermQKJADTfVYEiMH6DyzYIajgQafJs25fiJgxA2IAlii4ejG9buahhQwyYkRk8cciNY2WZQwFCIgb0gxLwBLsMMAB7nAB6aAA+9ZtwNSZ/fJdifQRS7Jsndmmj3a9b8KfYk6PRVXp1kyZ8k2Pnx7LkiTrDLhRN+jpk6VgIMxKS5w0AnkHQifJXqEuf6w5ORqDPndRbPyL2tV6rrnsgSK5EFuX8TLvO8ILLcnxJZ0t5Bs9NeF/qn/GSd9yk0O80bN23lJyHBb/x1FqvuEvzq+DXC8n5bN7Y+6Rj5fGOfbKu8e9Lh3/qkg268v4Ofp37fxm/8LtFvrqd12/mdIexxk/H//MO/JDQ0TQHU13tPkeap3mSIAqoq61KYJAm0rQRSVzooeSiFJ6/8xwidyZTAc0oHJQ+lQHnOHYhTGSjuqI/ZYOzGXErgNcvYveShFCivKfcx9sYHAScDsJe7RGLCXu6CSCayKK4USxCvuSUigXx7/rcjEsi3C6boPJBvz/OA6pL+hIZJoH/zgR6L8rAoALLVQo0tF5Mt3zkSk9/R7Gyw3ALY8jwDYU53PDdhTrdIemvojTjUCpRmGwVtEJtaKezZRkIbxKsCfK4fKwJPTMLqBGQSpJ22AeJXQiZBnGAbwJP1OCBsxSooa1qdwzYiYlo2twlobvzElClGemvoDdl529H3oG5FBOp2w78RaqboKXhVUF3e+EcATBcHpjM3P/kozyrnC8gLWfQc53RO6AUHVH/wtT1DDHa+YoOfxIbzxROicQsO91BXGm/xgHifW1Dp1vnw981Sn2E8v9nZG2fhd0F5SG/zHwxilWI7kspRG5KQ60vBEVWRHl4B4Vz+nPrhVREOr2JITJ9w7yPtpeJwVCqNUjb4KHGakdzhOtCcxPxMKSQhucp5yvO41wB9aNGdnUqjVFr3El9+DrejEa8OEEZsLq6M2EplxF7iyO2VF32h/HpQsPI4Z/5cLo27wV6eXC8vrRc6frzFNmvcZ9dQ8Usvrc2xvvAhkeGfBILif8+RNEw=###4308:XlxV32DM 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10bceNqtW8uS5KgO/Zn+AB4GQ2b0/n5FR4CBiNnMLGbZMf9+eQoJp7O6qrzoThfCIA5CHAn8fP6lDv1gjx+Hs49o2LMU7FCwp1pgZg1VC+ysEWuBmzV4KQgqFzz/UbG0lf9OqIIvFZLvgmMKTBWELoi1Ba1Y+91ri39FW389T5Hnh9I8+/3jsCmrIp5/H25/pN0/f0SrHzwG88xts4eU6shlgT+UN7lx1RpTCsbuoi29q30WHLXAzIKqn7KzwNUCNwvy0P45TB3Bf1nFCtyGVZRNxZjSSUWhWVfxEAVB1nEwdfyRCTz+2vqxtm5H62cAxK4HAOyPWo9lgjRu3Q14zbl1G0br+4C3Q1INBuOsAecFXrHCKyuaB2hkVo2OodF+nnBDJ1yTSXqtwL4qYGB+6bSGFfgwgHffn9YQF7s2ug8zL62zXYeTXZNhvjNwsxr4sQKwrwbuFgO3CxJmH0jEG5BIa+txIMHOrTtJTFCvJvja4oiBlSoK9WdZ70+rM/KWEeTf2tNrM4rL8Cwf4Nlvgvdvbr3UEL9/1knK8uev7IyrJIIkm1rW59nq5LaKOPqExFnt/OLh6ovbRiS2SGyVSEskpkhMkwQi2YukqSFpa7pIdJNoIlFFotqg4J28Btug8rTXQRV4ZZFkNzEGFeqgfinbdIkHvH1Uyc/q5rIFtMYlEvfGRRu4gcZ9HXjrpkGQXV+to0gdA3WqAq2HjZM6O9QpsFjfBh9JHQ11CkC2TYT0Q9NapwBk20TMyct7TxuD7QAJeIcDQGbMeooWidusq9KZ4HuBRY8mrXp2gPpTgCcLT7E+/Sr/VWAVKBWbUnk3b73CTOe1N5SKYIrThrMrKNP0K9OBhqRAL7Z5SH0e/MAvvzPmYe/zkPo87KTODnXKPKQ2Dxvuu6GfKvrCGARIXokdkPEU4MnCU6xPvzItavMnCNhFe9UX0k4kRWfVF5IjkqKp6gtJEknRVPWFpIik2IkqGljf1lE2jgj25apAdUGKAEoWFHcl0oM/XHZY7vffhxcPeezZJRXHxYPrvintmfNZ2XyT3RsHdP1v1z3hyg2r6U2Gp3e9MD22X9CoJICKZJf5P2W35w+XGWUM4at7DjMXe3sS++19Xe2eSejb+3IXm00S6ta+stkxPswu91o9cJ7TKhEJSYgnYLDcmO1eO9q53FSV7GNBMVh4DBZZ6QsvMhFRi3gDzOQbJKb35dryEwFJ8P4S02xtH7tKW37iQBLkcrvnHJp338jAhzLwlwUL8Jd1qdm81Lh4HA+uYbHxsdj8XGyYb0SdQ7G8+kRbXXQV5t8ZaGUCX5aleL08cbQncCxX6dhp3dIQLjPIU8h2XtDbGrnoNIxRdmNMPL02xs/GMaL6Wryg2fN/h99nhy+7OTRhk4bEL5g0MnnpnI67F/EWLiK+PMrbcVMrbo7gJr6L23bpaP3tuK1M28Ac8dtxMwtuZiO48e/ipi43DXc7bqcADOaI3Y6bX3GLBDf2Xdz05QZo794ABbC4PFsk9mrWUSRbHCGIMBCCTMK2daacvW57EZiyMCTCigmCgbyk6G62IQmJlsTsJ4AaaqohkZhEQgIkuTqObWICfpo9It0gOZKQmEQAD94gIMtloAYW9xe7GsAWcnVEk/uea8c7fX+V42mDaKUg0ssilCkoS1CmSSwT02QIeuE2DkkItxEwQ7ndMcwZd07OX7qtL/YoR0BQJjyJYGI6kIWd6dIAYFAjOZ42iE6KsfSyCGUKyhKUaUSrykKSLJOTrfwDaiIGNTkwNXnN8zGv95eubLt3SXa7aIB5Gp0ygSRnKEFCAjiGW4MFXuDhBRruHjxXEICQHAgFQt5OSaNK4nAOLuqAkpBnducJq+s0r/yGKagZVxs73VtoH872R8j2jyT/yO2/oYHJrxl8ygd7Sr8X1JT5h7l9J68IIuffTm3HUEYmKSXsiWT5Iq9Id5gXeT6608SwhlrzYIK9SCMqkkY0awL35XEDySO67YqBcvb9JKxTV5yTpRumwq9TAacM4o+mghwqmA7NnIrTEQkcGfA/moplBuzFDOgrLstuSIO7/Yq9snDDDIRlBjJf7Unv9JkZEBczcKLe4zRDx0/NwGvgzdUOwo4bgLdX9Jf5G4BPK/DjdEOHrwH/2h3VdP/28lTj+JY7uloMl5km9t3TMcLvHLA6B1zOAYNzGp4g9+Ig9+Ig9+LcwgYgN+QUpr6C6UHTildBqf8s0T2dXNxZSzm3OkCPcx0Fb3ua8GeQWXIboccxOnjHjey42yA7PlP2TnZaWba2QStZQGLEnrMuG2oXpZ+zRMJILIzEEYbNNIO3LU1Ec4g3HM3uxQTvZGscI3FzJBN0CyNJMBIukRgR5KxLQO2iY4AsOWAk4xig1QESnet4GEkiyX9Eoh1QZweE2QFNdhqeIDfpIDfpIDfpltwkB87pDM1Nxgg6weGcMxOpOak7IBUmUhyJUfyYx+pQu+jsLkssIBVgzskpXq5j4O1AT/E4MGGnacYUTtvKWhgj0XMkHi20MZIRFFmv+zmEcmCD7YBixycXbZk1gemCw8EImsDiI41mBO1IY6s0c89OeAeivg2iHvGRxteOMHIPQa/8pm8hcvj4jYnP+MKitj/tHH3Xk+brjdazNvnCbcv9i43+KxlYc2keR8sN+iFBviK/M0y8jPMcj21FEsa6q3XaU+kBrbHNCdQOWmOSs+HJazsoY7J5gyTTmqut1LPbHNtJsBU1bCV9bCtl2uKVLdivIoxi1NI8Gn/G8cASPErHkYSMMhl1Cu71GCW7PuQbo0QhnGWXefFh+kmpm4J7CNRzr2g7R7kxS60js08swekqo3BjsB//5wWLvMT26hEe3AI++8CHY3xq7u17oT2N4N8c2Nj1Al94H7HDwU14GYav5zWC15yzehGOx9gPDwVz22siDMp8QIgzuuzdSU3tqud8d8KFLbnpM6lv1nuNbSASt9vQu85fpb7OvKe+C9MVLPEFFrjeF+MZFi2wUf8xLLwmrtWra35xuxF8+e64p3b1EfgbAZ8lseo9bsnF8AId9kV01jtbBuZA3oiOeneoU7v6LDpy1RsaO25Ex6y9wByIG9HZ3x3d1K4u0aGgbOsFvHEjLvqbQMlktt9x+VknARGMtltk1l8dXmUVdY23J94T4T+rZY+yHcoklBko2/CeI1hIqGPESATXHPd8hNFzfao99zIBZTuUSSgzULbVp1/lv9JzHEPm/fbCz1rWyHauHpGYhA1xGypHRcMGz2AwAtOLPMyAJCgkGE7mdx9SV0NONQ4kJrF35KCGpLF3cNAZp7cvWI8A6zZQ44+GaVVVbK1dBj0qUIhNhRwSkxA6RFCIkRCa7xZNZU0yNNXqE+/HSR2bXrZDmYQyA2UbZjQZdwsD3jClzpoIJEGUeizQ391E+jD3OcyExCS+HvfzanUSXwcL7wScH7DeocitS12nT77Qp3KJjE96aQZ9EuRkhLKkN9davsKS+J+zpHesyF6yIn6jc3XvWRH/LCtiSV3SFnfj1uMuaQu7EZ3wnrawz2/M+pK22BvR8Ve0JaT70EnsLW0pXX3WdvZL2mJuQ4clc8kD9tt4QPPUprowC95WgQd2UKahzEPZ9NmG+ucDdsxkFv98IAnxzwdsb2k/M5Kh4mAVCpiGgzINZR7KJjcxlIdEi7o78xDor3MJBfzCQZmGMg9lk5EYyj7S3GX92H4S7LKcSSSm7AN22cQW9jGplKbsY25ZSS/sI0A/DnbBMNUQSEzZh4ddMFD24eeUKpxFwMQpKcJLWJykwoIabqrBkZhwjmhADZy2LwvGl7vZ3JadNcLOasfOKt9cGEX5B/nyoujVVYJesD3xXQK1ZiL0uum+vG2Ab5vibwvTE90/+Gi/Tna9duDOFxT8ekEhXV9QmHcaTjcUsvtRl6mFc2Qltf9kaiFcphaSvi21wM7n1uN43J4ZjNzkF44G56dQZHiXuYGk7ttGgrzaZNONmRN32hLHAbp9QXSsvvpQcntefrb2Rx9I5l7M5ZeD53yUNOrqy0G7auJWTfbnRxZgLux6u+IPSd438ZXz76+OvE16Ydf8408ol/G7D7+c/HAFqCuKk8SNqY7+oVO10vqhU7USdIKX60hSR0Md+CIva+tJHQV14Nu83A5svGEJ+w+I0bPD6ZF4EP0kML8okLh9embjEtxXCd54FZGgg3YPXCrQhAA7gPY4BWpwUCNgMf4CDqU6nFpum9r2KVjrrBHCIOBJwtMGT2qhi9B2UAsphDSKs6CumqhhcVM3NdS8JxIUtE/WVCXm/wTbVcM=###3776:XlxV32DM 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ea8eNrNW8mS5CgS/Zn+AEAsIsL6Pl+RZojFrC5dhzmW9b8PzupOCBubmYrIOVRKWU8ChD+eL5DPL5X88+9/CnadD/YQv/4UzNmHUuaZkasikiAaEFeQ4AmiALEZienKgAYg8IcK7Al3Ytwd406OO1XuvlRQtdPYm87PRCYyEg0gXHPctg+97XZ3jDs57lS5+4If0Lafwz4f/hxPp7PC1+j6KP8JD5r8YJsoh+A6spAqYjNy/KqPK2WftQe4y33b+gzuW6kTEOjWXrXX/Ksb7+VZ/vsSJxcP/nDw79df/hKPw6n4/MPb9OAxPP+IMA9JP38qAZZ6/siWaFfdrqZdz3a17erq1Tbch3oN5f1LmBNu4CH2q/QXFXv+5fPXOZ/7tfohDOd5KC5/tzCijeVy/8UYap8/NAPzPn9ms5TfY0hw7ZyCmYNRAU06V8xpEZJf6JbmB48IyU1nxBYWwZxOBDjwlWevtHZI3E+2wVcxBCCMIGBVVaxqhCcIWFWdFTEEgWWlTEUEQWBZ5R/ABN+YkBdUR1VhgkkrE8w1mJAmE1ZL/swsrr+nNuupzXqZVLj6dm3vpVitYXRjgtYLE/RZmXCGTzOBi5T61OVhFbPmgZZJTQIh1ax1VSOzZqSaNcXFrAUBs6awmLUgYNaqlsisBZlqicxakKGWiL8A3PM3I4i/9gqNCQm0pDbYmcAWJnh5NCYkhjXBN03wzQq+WcH3Nd+s4JsVvLvTgh8q2s4EuWpCakxI38CEMKZOtgUe7TLbcjvbEs92mdOJVPL4VROgtUIev2pCQabSY/JIrPSEPLKRx6+aUBAgj6+aELt3KJpQ0MKEQxxuYcLJU2cCx0ywbZZtm2Xb1b9pgG0aYJvlbdUA5ey9d4gsrkwwlQk887VSITj1afcAw8IGj0IjBBn8YGVNdKSyx4HxyqROpFLBFuOFwHA/hQq26EjwZASFCjZURBMEqGB9RWhrQAVbdCRctDWggnWFCqlRwYIoVLRRgZ8LFS5pOxXEO91DiH7jHnhwn6bCwdzR5g7GhfxDmaGJYP8w7QoI9g/TrhWZ/mHatSLTP0y7VmT6h2nXitz4hwLcEhgQ7B9aL80/1Aabf4hrpHAx16lwvFMVjNIbVbDfGTOqrc9VxOdyERNCkCiUOZ0IFgXkH5QmooD8g9JEFJB/UJqIAvIPShNRQP5BaSIKnmNRqGj3DxAp5HA3E0L0qDHqzgX5+/KHN3gYcWzyDx74h2UF/J3c+jv2Pf4Okk2YJGD1n2WAr8LRnwGS12eID0R+Ri4+kCGE+kCBEOoDA0GwDzwJgn0gbQ37QE+QQfeDhb584ctQYncIGRGCEzvkuWHGUGKHPHdBZmKHPHdBZmKHPHdBZmKHPHdBZmLXPrQldhVVBTioS0fRHberjpuh4+qduX+IYbv2ru+L7mBYO+cYKLOdRAjhCLcIuedI6eeWIxW540hF7jhSkTuOVARxRGKOVLS7dL6Wga6rU0G/tQykdmUgG77TpW/LQEotLj0iBJeBYE4nsikDqW0ZSG3LQGpbBlLbMpCiZaCWnPQykFJIFNaUzzPemWDeG+fHbZzvvyHOV2MVxSXOdwjZxflxG+fHbZwft3F+3Mb5cRfnx62URRrnaxrnj5RPcOMzDc7H8bCdCtM/nJ0Kps92tovNNovPddob4J9j/nM0J9r1IPaItskCPwE4EBlMk4UEtahCBq5NJ4OznQx0OC4Ho2M42cq+hVtcw/9I3LzozfOX5g/bs5rrvP04Fy36uEamNoNLN0ftJp4adfMPZXOs7BJkYKF/k+4E9wImiLVVUz8lMoEnDPYuzk4XmDssA+LoVIbx5DeeX/ADxOs8EYL3SPjJ8TtlJyLPAiCmh2EwiXWHo7xd1wA/BRoG7GvkF0V9MaIXsbbVaTrG0GFXpD4zVM560xXLDdQ1mspG03PQdPguO2k6ydZTCnfQFKErWTS4LIlIadTWnPGVlP+RAaF1vbYeeuvhN7RultZP01v3/2Pr3eqy0EUViv1ZvqffGUw7bQdTMwC8aYXVxsfeTN29g2b6naEcNRK1g/bx9DkJr1sHrjHtQEh9xR3lldmWaq9UN86NQMhcCdlXcndl5h3wbzDPd+a5PfNG9FNaWGSuMcrJVvHmMnfZrcL+vVXwsi7toynLv1uMzM9sI+kI/kwBza0hQc/xI3tnSMBLA3chgR/yCcr5mf2AkX/CsPDOEJLRdJKIgF8YwREBHzvfFZkRAb8YQWZEMGzUkBkRcKcJchMRFABFBIJ5hJCI4MQRQW1QNSbIl3rP6brYRv6+vaHfwaW02Vu60oe5BIORO2LbbyC2HUyQC7ElQiixL4RQYmuCYGILgmBiB4JgYhuCDGJzEebY0uv23NGAWr0qL7+Qvz9Tq1fwDN6yE2dCHeAtO7yqE9myw6s6kS07vKoT2bLDqzqRLTu8qhPZsmsWa1t2Fa3VHkfXrkRrd03szGn6yhXvVXG3I7v8BrJPq7qF7A4hOxV3WxV3WxV3WxV3WxV3OxV3WxV3VMUvygTXmZBkWms9om/vx+ONROBO7g56HLolddyx60NM8H1Sy7gQE2CCJoCIwN3BEYKIwJ0IBBlEyIglyCBCRiRBBhG444kgr0SowCQCd6dBCCGCR0RoDVYiqNfdG3cMby7fV/b7DVTSuwryAar2USoBsc2W2PLjxHZCDSoYyivBCLLw6gBA1xp4e+SFYf2Z4jPLM7gaGnrFsTyDqqHJaASgYiheU5qUxfGa0qQsjteUJmVxvKY0KYvjNaVJWTwLgUezgoVA4emiQiDJRGIhiATBQuAIMoTA+oCqsW141ZtHunTN9OZm3bsxcXjzt+7d8Og2Ky+IT3tz5Bfj1i9GRwv2V0IILtjDnE4EF+xRABAdKdijACA6WtSaAUB0pGCPAoDoSKUOBQDR0YJ9wgX7ijYmaLlm50cvQkT91rguqI3qFQZ+OK5zI3oLisZ1WiJkE9cFtYvrgtrFdUHt4rqgdnFdUJu4LqgdfwPZcLKBnMupDVZ3bsIqCaMOGs1b4zqzy2aPXrn8oPsLU2cNSWeTCQjYxHVG7uI6I3dxnZG7uM7IXVxn5CauM3IX1xlJicCJczAo1dPxtUyTTdK4cP4/H8sRzGzcy3V+vkwT0uZUztiR/LCvg5IFTFEra4S0KWvAM62sEdLi/6a0JXIGDWgzEXwoB1V7QiKHclC1JyRyKAdVe0Iih3JQtSckcigHVXtCwodyuBh/DgRfRry2NQi599plxm69dkXuvHZF7rx2Re68dkWm1w7kUE5FS2AXyKGc+rFNxNXLX2GwvnDtG+O6/BF+m1HpT4s40kPtd3qo/ZJ7cISQ3EMhYJd7+G3u4be5h9/mHn6be3jKEElDf49E/Ho5nTXiOvfOU7Y8+J3qpW+M8IPfRkh+UTiOEKpwuDWqcCfuhyicJAhWOEYQrHBk1EThNEHmKdugqCQgJtj173EsTHplwvXOXE8wtnPG8fuYAKO6ZwIghAlBIYR6DYaQnddgW6/Btl6Dbb0G23oNRjVBU6/BkCYcLzuxgwn+rVl/kBsmRP2dmiC3miApE5xFCGGCPhCyyfqD3GX9Qe6y/iB3WX+Qu6w/SMoEQ7L+gEJ8ux7YtH4U8eM7s35RzHKX7F3h81l/mIuI06zfcoTcZ/2A3Gf9FbnL+ityl/VX5C7rr8hN1l+AjZJxmuyRPfnaYDu664EFHM72cDaOoYR+DCXiYyhEFch5Pb2e00Mn+q5xhK79h3suR/vC3dG+fwGTqT1O###4464:XlxV32DM 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12e4eNq1W0my3CgTvkwfQBJiqgrv/1M4AhBEeNNeeOnou//JlGQi6dXz6+qF/Sh9iCFnktRjeTx/xmV7wN8f0cr89x+/+mOFVv61/P4r2PSIenn+HZx+KLs+/4pWPVa/bs+/glseYnP5GbwivX7+kFLBe4DYh4v7Mz/Q44EoD8x4sJUHdjyQz+fPYAKuREBL0ZVsfSXLaSXCHn0lZlqJnVdi5pXoeSWuPHB5JbCiA1e0z7QRdUV2CWfaKNFWFDYYLZRRfshjqX+TeVxx4Ne6FQqI399gvu0Bz5/fysy59T3/V/oY0gfGbH1y67s8Sh8fPO0Tjt4HWt/zf7lP2dH2u82wbIBYAUgQFgHxABL0l5MpqEN0K8++FcEB5tVRNwK3UbeC7DuuCQgj7bNOkFvf83+5jwysj8E+JvcxdRzH+mjso3MfXfto1kdhH5X7KOjjVlEWCj8dou75D/B69/qxPkT+9/vv4LeHAIY/C9e33TTGJv38CfSqDLW6MbgwEkYoDXEhLSI2YdmXISwLFZZrIUHGZ9Lm4Qm7xbooiqRMLFsIkbcykMFk2KVNK+zQwCpt36Vb+i7t2GXfFazIdy2JpuhRCg04BlDUJ8WydiWX+ldLKuh5bjPRx8RKn7DsjUD2CGhpLLM0erYjpilrNx/2yAvayfB26cNvp+GFFcx8mLopahPspU3IFJymWes0IH9kmv9JC5tyQK14HMj07TXTh2XYNiEbI/Os1B7YpCiSWQz0rkjXxUyQqsi5T1VkaGp80RT9/Q4Mq4ggL1YFTUdF1qZY+Z2qoLVPlrkUah9Jxq1qmTwgsQhQXykRYLfuTRdTxAGLLm6r2U9SunYpdVRKgx5CuGZ+BTMeFDkJyNGoY3ngqNr+lEeqf6Nm4gqL8LO47pXRaW/iuq1KvxZXOXsfRd0ejGEngTKqz7Od5rmS2zasn52avhLgQtxpPl3ny40x31sFuMxKBBilogBEKuC3pa8U4xV1RXAwIFmR7Pp2kWxoOnzRV8kG3lZEkRerZAdbkeaeyjtFslufLNmhjWvIuFWygy4CLJsAB4fvNQEOYAUeKygCGAMU4a2JsGCG1hIBVZljtgmoHZZXF1baMB4UU2yHCdaF+zaOBxCP/ZROVOEOex0zyKEeRS6DGg+WJ9eopi9Do3SaNKrpnJt0rqtWalY12dlVuNmpEC8T0Mu0B8UQU3fjz+6G6G3ZgaZuOLSgLctxle8s2lWfhGL6JGf7r5pj0HOw+JHmBdS8oYpUBQvVqQrqoy5R+3Ra4qbWP1A6GN3tEwG6QbEhnAmwijsChOerwFrPlDD3gfWgFaOEmWL+HhMUVz1TolBnGFk5nz7UHCRoZnX5WsWHxxEgo5zI2OMJvcgzGY17LUeManqWn8+RcVDvV1rWbplAoIh19SJ1ADaRLeX3FsdLBALz/tBRdUsYTA3Uy8skDoDfnvUx2AfjgG31C+ujsQ9GBNBnZ30U9smBenK1j2F9JPaRuY/lPgS2z3yI23H/e9t/2AthKJCtdTHe+RWbGEJ8RLAMGZ5hk4Yh6BnWZSytIHlfQdXR+ArybkJddHCUm8XxOVERjYjuji9vufE0ErTuyca6Cs2QvCdbORkUQ8rZofKvyP9A8p6sr758ZUjek620CxzJe7K2eEhFQrzGv+IhxbLG7CETRHlrQg8pepAX6IFra85rKFVUkStVVI4rVVSTUkW9cqWKarLSUR3P0/EOfjcn9qGzVcPZ/pDO3jvdbXK6zcd+FMYucxibaBiLaQbJwlgZ7eSDL49rw8PieU1pxR1qKkTUF3kZK3rAGD3mZdbtzhD6l4bwlKgJz9tD2bCMw5+IZVM3GZtNmNNaJ8/6yYwNUMSt80m/hRhqC2eK6JVR5KM4wU670fNujr4b/b7dSH8TL+jVXPA3fZ2/p8jJzvw1V2cWIISZCNHPLFuJ395FCDuxFT3+eiHoQd+x9SSkZmKrnXbTUwhwXnrTbn6BhT2qVS7UoweppPO7siCqJgqLqPWWwZalyUOgT/ddWWSIW20i1BHqVytNBzL8akK/VZHhVxP61YqgX92SORgy/GqSkiHDr6ZtQTrolidztlIoEIR63IQBRFb1ulNr6juRIMTbbskqhgxvmwgnFM3UwWiOICQdC7twuB/TVrBVWmtPkLoCWWltV4ZgihUQwRBMrAIiGYLpVFgbnweTqLA/PlqmtZQjld0lq6SyK21by2DL0ngVeKSQDrZSCNxQXUUiCEl0wdwBV2FpkAvvaIJUCqXKI5MYMmLbtAmiLZVH0Y4MLGpLTr1XSWotgy1LgtBsTmCy9eHhnOcxwNl7gHPcZ5TnQOKlj7/33M7cekPxRm9ob73U9sZZ3K0LWN84i781zcu7TPNQk8KhohKFir3lsOWZmsSIIg8IURMq2PkdoiYxojGFcS8Fu6yiCHFZRW85bHl2uiJGOK+UOhYV6YjZidQRW8thyzPHEuMwt5aaaJgrEISa6JjGjg01qvCOIwi9/ii2E04d6yPfxaBSyq6Ukebl6OHiwECGnynaqaOpaQtbpN3aX3GO/9c56SZfJd1I/M9zbe0ccG0bhg0oxoFKtEr9DtOfJVpjULP8kd7o/e4WebuY5f4WWV5Tml4e0yRN0vruznhz55Dt/s7Y3c2rLzg88ldJm9sbYndhL8TXrJJ2NxG6sWerJKS8i9DdHKGHlxk9e9r/VUzbopIr82zXdxvOPas2iHUzkhpNqPYXl+a9dzNmGk2dnszaiKu0vzBrOE41YRoNnGbGLAi0jsC1mqwpXeotRUwLgWmkHKNiCImUMc9XkREpx3gwZETKMVqGjEg5JsEQEilrdBXa8OIADKi0xj0ZLA4Yr9WL6G/FHtTigGaAOkyKA5rZF79r95pzzBPQyLWa+dHHYJ8Rw1a3OPpo7IPRbHODo4/CPqQ4QJPigIbW4gB/5OIA99hIKKe610jMa8jZa6g5aaXnlJSZU1J2djCOpbWIZ2HGf1y1+0PdpGzMRVHPnxgMPxuM8PJIrz88DRfa3pjQ9aIA6V9Zjlqioi+sREfOBTWIsDIaTUejmhIRUFhGo/vtu98PApOzWyuUGchcHjOQuShmIHMpzEBQxmG0hSH97JYZ4Y4cHLl8aTnEXDcxlwsT85NDYNlTkjW9vN0cV5T8mlPiNeerhGuWoZFgbZd0H6ZR5V0YFa/CKHZ12W8sX11Uug8uKolyujBnD5ty6nIzPCmniqc000cp0MLGu5AkvUmf8iz+5pZVC3fexBq/fjs2ksKvsqeeE8Kn+W6x5zXFfibEoU+x4avsZbiLjfS0EHt3k9iP4ZRW/nwhe7Mg/9L2Xt4bgmHDYj+gEQlC4HdkCAYhbRMDwSAEDIlnyLgGCzoxBIMQeAeNmvM0wbb6GAlCr7M8VjZVBBNstKrReXqdRQ218/Q6q6nJQPA6C+ZxDMHrLPg91nZwsz+2E7rZhy7d7EtBYGb2pWLIMPvEYeW5iMPyHlfuWeKL1mF6lviCPR0MGcVdYVkYMkq6/CEZghe4MJpgCF7bAvcSQ/CylrrZTJhrN5sR6mY9lZ+RcAadyqK1Zk/1kOiqTHdV60flmncxUzB3RzkRxH8Qh+T5ruOQjHACHRShBOolURUhNaBD9co8tAY0y/dMOttJt7HqOu4U7/KMa1iXm6yZ8O6/IB3MxzSiXzIUhOTFiC6Xd0idJCF3fudSHguC5IZTbq5nmwsTXSeduLyz1nP4f3Jk9CIas0cz8YHIe5qKhnoiZ1/imchafT6RU/y5mIMS/AxAnUcPy121o5pd0M6qajZxKn1qwY88uqgc4sCEzf6VKl3GXSAb566mCMlCjmLFvEhy5bIGoeg7tfzdiV7+HvqdUIFp+Tsp7XeinXDz4MTQj8N9BUZ4HwRaP8cq3d1q6EG1vudafXfRazioDt32XUD3P7lzOLBqW9xUtXu5vKx3/kyRu2/Fw+LiBsHv7i1ztGKhWsMs2gcUeVoqGqQCOkmahmbVzZKmoVtt9NbHJRbYpp0gLA2dS0pnLoXOJfkFLrUS1ysuRbu9LOr9FJdaIewVl6Jxb5ljcKlsqObpVu4NaTUv+jxn50pdwyuoDFZdGXYDC781QTiXvKlFvOAuD+TT0dM+np2HeZ0RYdzFYXa/PMy6821By/Cr+VTbI5lP17rPp9up5p0V6PrnZ4+7aT7umrmuyD3P34Fsa0kBXJ1/HdbokMLKcNwVvIdxyuouoLAt3MRx6XhVW/vpjPxashb7VQXQcq7gFSq9cmP6RZ2sP27uWFN436ZKuM1y+J1y7jzJF2+K1qIJ6uKzCoUXBXSW24pf8fzs1dEpJNl4oW/R0as8geqBFSv0FX98h/TZLzPK4fvqDiX5N0puvElGqJ5uZeXx7nVq+FVWIrzMCNupKPzuOJHsm+iQa4S37mrs0YuQbeDFuh7dRulDinUdlsn6g7saLAPKNqIV6/oDv1IZdcaWpTdgSM0QUq3rPENIta5DjwdWj9YPrVjXk81tX0bAZThFYBJ11nBU9RHLvVrZYmslbMXeCuwwBsioY2ZHLpgKK6lBCHsd84Jr8prAtGxn9YIhpCTdG4aQQnSXGELKz51jCCk6d3yeqdS8U6XFJf7AVsJW7K2w8KjFY410phz9rKnUmuHYAQWmtRK2Ym+FhR1cVjsIF5DXcYjcEJJ2einy3O7n4PRM4Lqy9t1USXcNFbGoIqQ6ftT726N/E1D6kC+oSrQ6+mjsQ76lsuxbKhvwWyodU7l7g389CFt6ugKjyqTmOvHZOM1+Fw3wXWYIZlZZHByxQ3LpmfRmh3S2mc1TYd2z+8IaWjZKFfUbYU2skRr92CGvKgtVlyyNH8xlBF7A7NCWwkD+DxPuTQQ=###4388:XlxV32DM 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11e4eNq9W0ly3DgQ/Mw8gNiB7vBXFIGNEXMZHXx0+O+DHVUg2ZQszRxssZkklkItWQXw8fz9kxEnH9uD/vpBOPUPr8PzTVCeEMI5B4gQNiHpv/TOFglCTEZMRQRCdEZ0aU3h1lRGVBlBkAiRGZHP378d1VQ8yMM9+MP9+sc7+mA+qudf3uwP6vzzrxjIQ+zq+S4MS208/xZG5b/vwrbf1tS/PtS/QVQ8qvo7FvxdqnL/b6lk+RtN+e2oLA3lH9uv0m9U7PmPt+oRtEsDMPJBpRFpTHZ7MCpJG5SnsNOt/t116SxuFHbyO/fC115C78V+Yy9i6UWr3ov5xl7k0oshvRf9Tb38pDLuuZdfP8oKpfvPH0WK/UqMK1mu3vJ/+T3flK0gqf3nW1rzjGRdm0jqMSPtnYmI+k7Sm6zUVGswijTqNop+JcaVLFdvSf9qXxy0WPpKGln6CgG26ENvsV2JcSXL1Vv+r4xxtsjbGK2pfTGA1L4sq+9MhLV3jKrvUIDUdwwrJhk1TyZpk0naYZK6m2T470wy9+zTBT8xRSr2pliR6qFY28cVq8wrrK03E6wtfbF1o5fWu+lVA/hi60W0/MTkqKRfbD35dNO8fekHmkzWhYkAk2Gbjh1JMwcmE3fX9DsvZ7WOLPp2lR+uV82eusVETUCD0GKi9bDFYh2lxXqVW6xXzZ6axaQhdh0vTwOLiUoABFgM25QaiEcWE6UFCLQYEnwOYir/GxZjusVEaDFV9GkJsgWkxTJJTfwz37Dzhi433Lyxlxt+3jDlRpg3bLkR5w33fOZxZcNSUGu2qjXatHBAgohda0IfqtOpNSF6aza63LyQ84YqN9S8USYh9LxRJiHMvFHGLOy8kcb87otNZkcbugsuo64sZS+8InICkMpS9lgRipDMUvZQEYaQvIy7rwhHSGYpuyuIwq1llrLbimwIERkxZemjystO9kcS5T4W3/bF3+Hil5CAJBulx5KNMmLJRumwZKMiWLJJL7FkowzPE+dsmuqZ+Way5HxjvpmMPt+YqqdK72aqnuLlxlQ9VVTBTNVT+nkIBe/Ct7l7oPhbftMDxafPk6BxZjJ2NRm/moxZTUavJrOfmMxghUlNwmI6ilbTMZydmI68Mh2zmo5bTUevpuNX01GvTCeNtXjOMwZLOoOFY/0z1pck4leJ+NqL2vZDL4y7K4noVSLm1pmoVSJ2lYhbJEIv2DbpbPs7JFKCI4MhX9ZeJAlHiXiFJPLKNeLZhGI05278ZDaBfaMuHiTvX7vxyFuULBYEUsriKSEyUkoyonFDZko5Ym5DRkpJInMI6SllHoFBSHbWQtQQY4cbNzjEAAdvLkOMWUIMQQgIMXJHCAgxIPiYJcTgfnqI6RkIy/NJdl64U9FvwJ3SbwafyWyoPjPZUPo9JJb0ts7e84p4gNTZ+zoqxhGSZ+/LqIIdK5P7mdwqzUQDBHCrNPu5Zr0QYbL8XQwAqAMwTfw7QvIATJlOCAYhhahV8QuCkCx+U8UvGEKy+I2tqqERksVv2kSH2mbRTkKYJioBMgnhT7dDfYYFF1ok3dep5K9VSiN/zW4ljZIkPkEfchAK1wiF304JhUGxv9knjJ2v4p7PVDGK1Zf1eCfpdvRlilz5Mgv6Bw5Z0KX57sIkpZ9p3r9ylWiFU4/YxDlAsIkrhAATF2MhBUcLCVyW4NjNTfcjOHBzWQgsJ9Yk6Vea7Fha35eWzKVtbrt76+6ku2/GS94IoUUcsvM/wPtesTq9sjq+sjr1hCxOrKRtMlhdhuMng1WF0nrAYIsKnjPBG+LnPp8r+ZX4mdUALCJ+TFwQPx2ONIf6Y870oVW70WTXXO9ZLUR5ekdhbqlLCIeiZyNz2h0pI6M7muUrquY+SV5DKVGpExKli2zXkbAP56h2JTfqEzkqGmLwV/xLnzBfp6+GaD+fRh/EqVdxGuQA6YzljMO6aJpF7AwjeOwaB5fKCHKNLCIEsh+OEJhgU4RA9kMQAtjPTNeDP2E/fT6I87CZ4jPEZ0JwAEF8hguETD4z3XZF8ny8rq3tCMnz8QoHjork+XiJWXBF8nx8HrXfwpgogxQo/d4AgjgQowgZHMjt+BVAgQbXrgigQExC/ZikpTm+iogytCbzoiR+8wAFAc9FiwBA6yd5LMik9cFjBNB6ZxACaL3cENJpfXEhJa7mijWZJevQ4yq9rMEspZfwXF32VcXFnUfck0ir10gr10jr7iPtEmC3JcC2EDwHrMUaYMlSaskheImwS2DdR2C9qz26U0IZ2H4RR9U2/DqbTtNextGDO78rl+ibdJpvF7FPbeE4MsmvYp9bnbX5VLKcFdddxD4TTuqz0d3J6FBJcbe1pUMlRS9D5Bexz8izIYa7IfqrZdSfqvFAJ5KvQDzzQgAAhjMYGDgKZ9DJcxzOBEEICGeCIQSGMzyCEc68kANwFzl4RkDM8sIhAIQsxhEyQxYsTbglZDGEgJCl8DsjZLkptGQ4MGRFowCCQpbxCJlpezQMISBmmR0hIGbpETSTUwFpmAsaACgLG1l7RUBU0jtCQLHJUoSAqGQFQkBUcgEhICrlIaSoRFLWS+iISrFHJQazvQ95ebJ6ebp4+ZZX2Vebrx/cgnJrWqXXtGq/3YIyMK0KpQBw6urcdnC61NtPuzr7CeqMEi2nL85MEE2OI/vDWnEQl35U0ZNwGL8xzfG3W3H6KodIskE5xHStguMcYvoCsTjdmSkI7HSBlxCL052+QCxOdxqpWJyuFQg5zSGcxjmEhQjYc05tOPgOrKO6wbpbiak9UwURZlQYdaaafAShEQI8+fRWBRmenFInEAI8+QwYBQGefMaFgnRPXqhPUrPHnonyNlzS3l0Sv9usdOtm5QUn67uYV2VJQ89d1HBNr8o3N/t2bj1nJfduzeJozWrsyWyfsmaehSAhhezWnE+vHXoZ1qwWa2arNdMreiRXIxbFZv0YkVjLRb1+S/zRv1hcRnnlNc8LuqHkvvysoEvMCYnWH+7vZoMJOqelwMEHuUqDw86JAAQVOAxHCHROGiHTOUF3gksS0Glw5DSAE+QCV5ItnE8e8I8yk7S0dRgBTrfm63QSGfarPp6HXhtHZMcw9IwezwDaA1icRLQncI0QQHsAv5Nwj03Gmr8XHtb7spUPJSUpWboG1e99685HoOo3Tr7BYYaWqb48s6Buq9uHnFvAMwuwur2N6vZlUXtJtcWHTjUc2FhjbZBz+cG5LqnW812KDZ1nTTInFzs5ltmjZfpwZZl+2l13AIUuXR820N9Hlzi7OGxgpDv2sov/gC7615lxdOzyjIH8RkHoK95sj4JgTN3v/V/SxU9uUDhxyZv5N84/rL3EHmnZsReLI+3JdOXVdDmOpyXtl2d8/WR2TOPSzEm/7qrfsz2HHuZ48ftjp9ixcSVg6HNuxLc0bBj5Ap+OOpSY8pYcRnXhcYSG0MNHehvHQIue0eMZSNUFekaNZwBpL/F3PiPHM5O+16jaJ9yOOTg2rsRC3McevxMnxH20U49CODauBCbzduTvydA6mReDzANKoTGZBwFdYzIP6hgal2WMQQgg8yCeakTmYQzWsCyT3plkg+FzFnZWbNiYFGuTgjkFX3YaZk7B2VK2UQgBZZuZbfBlqwGUehg6bZFsCSHztEU0dEyK4O0JO4VHxqRIXylQ1uEE8hvZ9icK4+tqVxmJI4mPPEKKlXHwEdL5iDzUZ1CR5UWh5rDffSjUHDlCqe1ccoNX29v6thxvczleEHIVR2Kvcoh8jq/6MyL//PSeen6J4td1Wc7VtcjCiTqMdTnsfnWEPklgPRM4PHrcjhKQ4sNb3venE9EerZfdYvKQoLf20gEE5il+VKErMn20H/WGikzP7CVFyPTHM4PJooZ+tYq+I9CvCrKN1rr9lbfb0BkDMKxfSwxMR+nlhpDpKL2ICJmO0guPkOkoZ9W/IrPqQand12/MdtrtXP0f35gRSi9Ic/L87fMNQrYvfpdF6BUjTbHiG3vhF7wv9tOo39KLuPjGLPZPF77cy09KyqnL/GVJXqH6PVmWYr/i4wrxLUr6ScaCwA9msq5NBH5jRvqZgNLu+TdmeRT165g8in7FxxUiQamvCFqEX8yQYlqjxfJ1TGmxXfFxhehQGqMZLTL0xQztRKnKB3xjRjpDqX2BL2ZoL21U6cJvzFQM5RszMr4xc6KXAsIwSXm1YX91tGow6W7Cq8mmnmX2cBYoluhhoH9IpQgZlbt+eMDZPxhDaO5gI5Dd/x3LZuP4VCoLKI8qr2pfWqUNQNILg7HS3QIkNT3Erfop2oKAGhNVnaPVfuY+WUI2hIzSUZq5R8ggVAlRCBkFo4RQhIyCkYyul4WyOVW0Ome9+UUTlO5HN4KfmnDzYchaQlkrJ6NgMr82VHpbNEHqdg5A/t+aQBgZC56GVZa1f7W6eYAAugCXVW+QLsBl1RukC3BZ9QbpAlxWvUG6AJe1ICNpA/qbgXP9TQjQXxl9p+Pm2RusmsC3ogWJ+M0wzbomhI8e4jl8PxWW76ekvz7NA/Ym2oqNEM7cWvDuGwvK9+87adjPNxZuwx0rm5CnGwo2nLQeDhsKCysvZY5/AV38Xb8=###4216:XlxV32DM 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12a4eNq9G0uSJKfuMj5AAsmvKrx/p5gIfhkxG3sxy4m5+wMBQpCZU93ushddTSFAoL8E5ezDJf58/h1MeGyP5y/PnD1yS+a/7ecfIX9Jmj//Ck4/VGDPP5JVD+aMff4R3PYQQofcF9lDevP8LqXO8zKkLOuepcOMDg0ddnRY6HAFcd5AhA38YJGp3OI//4St5P7nN8n3CvEd4mSGhAyxvEBckmRORpIh+SNDQirHEW1O3s+zjzFljClj/JamMRrH6DJG5zEatsl/5q8Ooe75qxAsZoo83GN/uJ9/Bc8fIopMlEI6IX2jzqGff0sryhG/S6vhyNK1787W/yHW/1FWeNL1ewL430pD/3elC4GeGfOx58ZOWSUqq8SRTqziamubCZwi2+r/wwCStPEuCIdcV4999eMNq6tldaPr6vu2vWF1vaxuWV+dfXH1IlNbl7aMJ8Of3zJPQA6jIpA8o0AkzIkHQlSdk/maIekoQi0BsD8y0iJemfS9pbClofUti0dFJcmCgCoLTBXnQFcMsa/YWgpbGlrfygdsMeGKsm3R2YprJ5CKy4k6JyJkb3OsrnMEgdQ5VoDGxM1ljQmZPwE1JnaNCVRj+F5ZMOxKUn62K0ml2a4kFYhdyQai/q9czNz0ONDAwCOMDrBZRxwdYKKOVPVPbk3vvFs1Y2smMtqzdGUT1UykXkykWE2kWk3kvthmsSLuttmrs20eiM2Cx3/EFJeD2lVJUz+o+cxB1XrQfd2AWA7KV/3tFPbyMwe1Kx5z7XM2h/6DN59zgG+IHJUiEwN8TpaDagVU9xoZUtxNnV29zwEq5dk2jTE4pijKEaqiBIKh+pzD112hv8uMnzwhR2uSZZF6wgBOQzRI35WYfCLxdzDG4JjhE91QbBhDPKGfPaGonjADQgNk59OP6ZrCFxepHvyhUOFTV/j4SuFHINF5eVLvIqr7rU7unxFVfsZGBdOkWw1kHxLM8xmoGKL7yHhmhqOA5oPODOfIzL0zPM++Y/jeGQ5jKMMNwTAxPE4Mh3nAV649y3w1ma8G+Xo0vuZQhPAVre8w0waM0OFGB+gmtc/23j6fzTLX1txYK+ld5Q3XGWsTgcIlIgJyiIAEEVCrTOgba5UXjUvI3K2V9PaE+Dchs3nemq8LcQHyA8tgB8RqZQjvkEwUYrW47q4c5hBbxXWKEwQtFNeuiQ+sBvFxG4O2Kq8rCcZMvQJxADnMBJEFYkGwEjEYbcUqWIZvWbB8ZqbvgrVvXbDUvxdTf09WVmFSNq1pUIuto2nRbx4jMYJkH48gO5JfBcsp2YodS3ofFrctWHqsHU18Ixa2agHrWMKbsPzgCvK5HNwCh3L/80+gYmvlpXuLQetb+SjzQteVAiExO8jagJCYPc8ZkI3G7IwbQ3YBATrsorXK6NZiNGjnhh1kRRK0cwX+FlcsAXpdsbbKiq3FaNDOlccVy+gRtGdciUBI0J7nDEiiQXueEwlkCtr5XoJ2lrE/mEClZF0p9aSUzdrbYe01GFU7rL2GcoAd1l6D9bPD2muIGu2IxjVEjTY1TedUs2fXcrx0LX51LeE+9B/OB+1FtxOMHccaENgq9Tr0LJlx3qUe6eS3D+gU41sZoejqrq5uj+28OtiMS5cmVpcmn58O0ec6UZbE9eChRUIHP21NOPbhEF1f5iJ8L5j1hZO1KZ7xbXHCR0gRVlLo56vKlb/PIsYhpr26m/KDxPIDYdtsCl+ZwGNjLZgrsgfWDhASa5e/96wFIKQOwXePkAAxQx3T0h2+cQIu7hi8czYNEROCChlJTj3tgJDAYZcTZKQ2XOwTBMOF/F1NEAwXaqGkn7sWRWDnpCiSzVafrFyLiGw7WK/ZwOyjhMClr8RGABYE3IwlxNdVwQvaMrzG12XxSgEbK23sNMbgGDCtFcPeMdQxhRa2hk47nyCFFtZV3GyCFFrYGjodLXSyCXFB6CQ2XQ5qH+Jh0UrzbqUNtdLvCpXivt8EMcG0ZJ1Hrr8YXkSQpasgJpj9jVjUTRATjHgTliwvpvB1z2620K4GLOV8vaWm0CUq3ZxygZDQpfG6Q2joEpVCiDyXGzvqGqXAkNZSVJ/EphJZhsYrUR10HYhNYJ3WUlOUEpXEdXYapWQMkUBGlFIkOU9akwDRJdn+F0lAFPEmCQgqvU/mRLrTHxXfKNl3SUBQ4Y1Y7pKAoPyb9acEy4VDTWtEQv3ZsMUWTWIobGzWJCKgbNGkoWPbZeEeNtH0RyTUpA1bbNGpnSx41ilcsWqSSKhTG7bmHCBK1FKRFu3iBEJzgChR7wqukQPkOYxAaA4gNufXOt6+d410VCNDq+OFUcfTEJSHUbg3UFYJJGzfoKNV9uDCJCthkutdTrb3NdDULZjiiZu3V9t5EtuKWDXEezoh/mq1/QdQtxK+YK7BS9gBEjqDCzFq9S8eADGt3AsQiE5gdo1OAiSCCcs3dYzBMYXpAQpGOa8gGGp0EqD618Q/f3U4r0YazDuQBkakQXZp8JdVXbVWdZshptc5/lzz8mwXp0So1123fiGwbxj9yzTx4jLYX5hkfldqg7PWSGxH3tTK7L4bAqkRM9TDxZbYBMF6bIbICTKqsLueV8MqrGB4tVghJUrMH5UR4cQI1RkRLsuwbs2VL6uuS0bs1ow4p1KZNYwvrMHqZzKfYU143pZDb/VnaNjErH6jUvZGb3N2TFUKhKQ3lFlsusOhzGLzzc2u59UwvaHMAkhPb34VSS7M0uUPmaU7s+KrmnlYCxv+Zc38eL5iowE2QqxzlV+rTZ/Z6NVdfu3X/No9X5W5w/MVgzVlMNCw68JU+GbcJgKhDGZ4aV8hg8FUs6bCt2CaTRDCYDXjwfw1Q/wE6flr0dOgTnpqOuvTK4O5qEe/9x6WM3vD5SLcz2QEo1sUNt7YUnmIzyisXRnrXzLW/JaxQKGuN3E2s3InkBszy+KdmWVxNrNmXu3SzLK4mFkXM+tizqwjss929h2X0Y8cSgYFtzD4aYBboXkiEhbphGFRj4ZoADXnMMRK0Fsxouk9mcnbPxYF7+GMVRd2WqQPF9DcnU/VJ586xGCUy4Cw12+BnDw7d67EJ8plxTvCHfxV4VBdGDY1385dbN5OtoibZovgGCTbCF1iYQfESGWzchAIMVJ5H3KCkCKbMQQNzSeYS3QDI59oHBcAqS/p2myI9kPVq83i7KPtJbjJYDYIBpSNXwOCYeTQngbBMHIY5gYpehUUkElMgGIvg6xXDqakG3v5Q4VzTeHMdl8AwDsBrNKXla5fynX54sahfPHPlGPb2lCky62RL/1gQmwUQuuznZsAIdxUaJgAgGlZCRwyp8rtS44nkBq+U4MNagwTgaYhXb8ftHUXF5oRZNcMc7CuGWG2CGuBvkqSuEj9ndwutHh7TWWQT93tcV6fvrVDyYUWrXFb0+eUE9LwwOIzigKhmjc4AniQI/lgWsPN1/7IgRs+8dz7E0/DKel/559VWP1zvHqohrLcDLpN053ZqG6R3Lql0mZNpe2afbu5EFZz7FEQu3Ii5uray+yryVZHZbaP7a0F01LgtZf61LVXfXIiLh7zZKN6Xt3Fz7w7I3dY9cnS1WuesJsTHlEurz94h+Uu77DMHm7MkI/+fK6PqMhEtbRSrd3IBX7midDbK0fnnvPm0817YI+vHv/55s2+3qMaJI15g0AdC2l6DSnwcCFQ6p8KlLorGQXuvyRQ5lqg5HYTOfmovy5QUAm8ipwCt/9EoPQsUJLd3JL6qL64+WzqdXcP5RjnUEpnSLFi9SKxaGZvJWz1a8ZC5t6airnZN3QsZQx9ha373QwIRb1ohXWqJ9Kqv+AENHAfWaS03UdqrAMVcF0XKn75XIasS8KyDOlPP8tC9RayjsEALY/p6U0dMwI0rTVinErFeY2Ec1I/yZ76SayWBFx9qk0Vsk8QvDDNyCQiC1PMpFXAOQGRhUG2iBMjki0OsikCbuvCNa7tYSasSx9H1pigki12sskw5YtWj9lTvsgsvJrrwlRv4+FMrZWw1e/qQVBaa7qegECjC9N0CZEhjAhzFyY2WOAmWcewRrdafnu7WY8Fj3XbxUAt6zYxqQWqEPnp2q2/zjfiP7h2Y9bJm2s33yv+OX6zX7uqyljUzbWb19sbseibazevjjdiMTfXbr5fVH4ZS5F13X5YUjhUZbhQsbc0tswk1zZ0pS0QGsMXWRuQKYYPASH6+vcyZRPVKpdN9JbGlpksdYiMLEgttQX5xBXhtzGwYmtpbJnp9zI2eFxRTb+XCXEjEGpLbcAExMnp9zIhHAQyPb0LUDdkoiQgo2jcH9DD64eRgMzlv4u0QpP0YrzN6+/pLrT4RpvX3CFZmkP0Z9m/0fLT21dMIaQ9y+z8cu7jmlHfcM6pxP+C1wRVRRD0FPTd/jbFwpvFS+sk4xs1er2u7+8KvTRvpA5fqeMm6pjPUyfcWVUZ3kgdvlpV5IF+I3XkQp2sa5Q6+jfUmYkS75yA9G8kilixIOnVG4miV6KkiSjqw0RJdz5Lujf7LFvMan8lDhrcPdWGfQH7OPZF7BPYl2bf1t9SA2TybXiXYftbavRtWJ/K69YgtvS1IDYQvyLaxPqTMzuWDHrKaaxHF2vj2V328zfXaD06yQ37AvZx7IvYJ7AvzW41SIL47FYRc3WhBXNzphv2Bezj2BexT2BfWtwvYi7zGhXloKIj4CmDCjtSUc4ZFF4cw6aoRx9zbFg8+ghhNtwGH9swBEwfltqAAUngU3ZkPQqA9UuQIAiE5k02YMhhD9zGNrahCbgnRv8HcX4pJA==###4924:XlxV32DM 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1194eNq9W0uy3SgM3UwWYIz53VuZ9ypSBRiqetIZZJjqvTdfIWGT+9K5ySB5PI4tBOhIQvix56dg5IMpY59/CXM8P9noH+E8n5+83R58VzI9cbKHcNvzb3Fuj+2Rfkadf34N215+D0bkn/86pqxMrdy7ff/kTXwEHZ5/eaee/3irHi6w+2E8DKOSeJHFJ8Q8bJDP51evfZevWWodSL5hXbTtc1HH/SBya4P4/fVcvqW55J79++c06vZI+POLCKoivCPePJKE5+fSl/QssNsQXF88Y32RdSQ9nuaZEK8LomRHVCwivwhrCpJmOZAqzfIqbYyjQY0N1LABwe3FvYoEJD1e1TD1HSVgsNDUMHXOxiOkSjNVDXPCOKqrkfpADQy3F5sariPp8aqGKKthQt4U098x4tmGra08ndYXoc/0Vt6s1mehj5XWl/xfmaaGrWV1mjJZetFWIKRoK1V9x8IOJbl9teXY9B3B9UWx1RcPWG3ZphnbaitkYXW1Q970EB2afzLVNv/Wyrvd+iL0md7KolqfhT5WWskO01wSj7wPD/ZwiUnu+z8+qc7PNMvCKG5to0lUz69pjytNjCo0Ebb9nshZfvqz/jxFxYOqv4eCf5XFoJ5/y2LfQC/HjLapIRCTFW9MzpoUJhttgLsMcxcGfeWPjHbzKGcf5XjfKEZOo+ju8NKk3jZKcR7izvep/U2jZOrlDRTJ9PIOVfrkVWytNEhrWUop402z5YxgSmVbGwimlPHdj2a5F/vvSlQbzkq0Vn64tiy26zyUQQKxyzbFPkGiP7vE2soSaytLTK0v+b/8nuusL08jv+ydRwj2y8Y6QCxxop4gw4lmRtorI2VnpPsjjCwCbhkpzzdasV0xUvo38t6vGCndG0c5V4yU9ncw0hpg3+Cmh9ZJGQmBNyOEkZAZlHcwI+0war9gpDXAvsFND62TMhIp4VeMzBIb+wY3PbROykgfwZ1YysjzQAhhJHJBhjLy5AghjDSJMOyhH/yhgZGqM9L/DCPvmYiYF+yU1QLzjtjt6PRgR/tP5LFZupuld8Yd4Q3S/SQdmHacvyg9bVzMS3bk7Qlg8QGiUfDY4qXp+XAGLsbbpTRDDRBOgicma4JBYpDJSi0AoLGg5qsdQZYnNZhkoKGgsrojNBT4/RIKdDe884+EgiLwPhSwN6ZNehkKtjeOYlahQMQ3jmJXoUCE3xEKjIKUTEMLwoOxNBQ4C3mRnZKzHSEkFLiRS5lFKDAKUjINLQgPxk7JGUMCF6EgS2wpmYYWhAdjp+QMaGc0DQV+QwgJBQ54ZxQNBS4ihDLSuQsjTWdk+DOM3JeMfONxqah/z8h3HpeOZXL2xuNSad0nZ7/luJR2qLOPQ+uAlpgYCbEkIYSRziGEMhKCSZK7YOQO7OPQOqAlKCORWziWjNyBfRxaB7TExMhxouPTcckghDJyuKB9YqRGCGak33QipMr/gJC2EzJiQtadSztoek0xpE3PHXZ0xNLhRocuHb692owhhvGAfSZSCpF7FDaxrZqYdp2UgvFmYtxBkVPnIqcYRc4ynJCjw5cONTrUs9dF88/mTIQdD5hSJz2rWeblqQuXVUzdueSk6Qk0I0lCRgLN1CtiMnLSk25FRgHLn4wgKiOuIjtBZEYszbgrIjJi8qa6M63XIzzSVsOmurapbsOb6o/mTcXYEZZXyMvRsZUOWMOgyi57PTpC6eie2VaPfGcwbjYYDQbT7aQBZeOKwRBbC9WLC+kng9GyG4y8GszGVgZjZ4Mxs8Ho51RIrxaELWcYTNZsW5my8lfNhPywZgo0mxRyoBBRmWr2zZ09XmcVqSkHhBBThgJ8RbAp7wRBpgzOtSLIlKEEVBFsynScbsrf0u9As7TlVWt/lOlIBFSlvaWULUDW2WdZXp0EQHcGuyFIVtnXYj0TBMkqe0nPyBXJKvtSE/YsH3fPdNw9gX2+sS/ZO2Lf3th33dQg7Y2ViZK7LKgVZ2rZ2Rebiy8mJAyEfI7Jcl/CcQ7TLFkGsGTfLXl3htw8Kexh0cWT3C/Fsb1LVRepXEXCjxvr/zEd5ZqOPl4ncfIVHf1POIqJjuo5hRiHQ0xa506/vOL5FqTf60iXowJvSDblz2X9qlGLQhAJtykVGXc/klvytoK3s32LbN/ZVNvLk0+QwiME+wRpdoIMnyAPigyfIIF6cvIJ8ogEGT5Bak2Q4RPkrtGUq9Z79glK1Sj6JevbJ2vLwUMyewmJZyeluSXlCInS0c0PMtz74qAY9cWdx4OW8ny+JPAcEhepky4sZXEy8M4n7fXVwCP/cOrkVvHGP18ZuH0SDjK34qBxVxXD8ZqDs2aLXE5RorGepWeNiLUfBiHE2g9PEGTtYicIsnaoVVUEWbu2BMHWLgkC1u7ZACI29qSaRkhVWlRhhyAI8haDogVB3mJQlEXsI5JqG0Gy0kJWhBMkKy3qvaiUR+Ibz/+Ab6Hzzd7yzRCOUNLUgCT5HJAgdOib0EGTPjOnVqucv+jePQ+nS64DQsiSC02QvuRpKWwpf9vH8bCwFLEvxW+8kHLMbXJRDuexn9wtOrlvHz+5/5ulq0U5nEf+Bul6UQ7n8XiDdLP4/IVH8YvSU24YOy/yOLgmYaEknhFck/BxB0Tf1yTydtb6Q1763tLQMqQmYaGUnp/BNQm3eSyx1B+KxNbS0DKkJuEjA4mK1CQs1OAzgmsSPm6ASFKTsEEihFQJT+5KsOYjWKdDaGMMvTBqzt8M55EWOncM56FKeDIjEVYl1Jlx2Ew7kDtGRqyO0hEqzeCQ3CIPOgrrfX0UJsfplsCfsZ1fy/GJRG3fQqKGgke5JKsFj+X51cxR285pqZvPr3odvnHUdts5eVt9dG97QxFHPzyT1zRYkA/QrJ/r/P0EL81VPFf8cg5YzU89l+4ee/lsZNX+siroZNn4US3zbAl5/ezMF6rzhtSEPL+NTpnpGYnk4mOm2wJBxjHTHhsakRwzIxxNk8lULU2RJgxDSI1FJpSTsSdAVs3UlMUrgozP1SR8QFKRrJqpKYun0rJqpoY8TqXl6G9MScP3loZ7CwtU03CbfOcUCxNBGrPP3xsL7TIWyjfEE7eMheqXpdsQlrFQv0F6XMZC8+uxEMpOeRwSC/2JEBILobaTZ76IhRbiXr9/Lg+3VqSxEIw4P7OKhRbiXv+cqUhsrTjFQgGMdVMsdAihsfAAxE6x0CKExEKrc3HeJEc8GLN3xqAbs8EEOFt+rBa0qre6UW/9KsVGb9GqKyMW2exdeXe1mRzJfuLjZ7fFOTaEKt3Im9wPimoj9DTPf8zBkD+vX0X/MEqVIoS8Oboa3stHdnM9ShlDotRPlZXdh8JW3EYOFshFWDaUZuNJaXy6rcvZ36kf3Oa+9sGtYxsWiT64xeGu15+ycFIILuFuPKPhmXEgrtYynlHwzDga1xA4npHwDBySK/thHoPfSvEWcNKhvb/WAk4Syx6MJVtlOxCIdwJFTCBc8QlzxWfKq/oZ9UelH3dziu2B7T51FS9T12NOXSWkrihjtTsOjoO29mCrYpENV3PmcZV2uvXlBLHeH1WN9I9O4a4ZxF3AVt5edJ2unV+6GMvmr62U7StxXqUbR1yMmD2KJA6ErsROPQoLi8xfcXbdAqiVvK7X2fVVJ3FC96Vy5FnyyiPPMmiXAUQ7r/qRNU8K5aZ+G4BvCXT9gwnLInoF56Z2PwgyclNbbgx4k9a8BwskS7X7SZ6R8MzIVy1n5BkBz0Dmmma440VAf5xRqVMRVibb1iPWGWMUFYa8osAoxY2cvyKjFIdOJgUZpbgN7tYqMkpxlluC9FJc8o1H840mwISbb+S5Jp47HiyCbzyabzTbL1TFidPU1wKff+JbLewJJwfoZgcoXjvA4TunC+4X99paTIf5dro38823nU73zc3++NMIP6dg8cPXcbmc3g80w5ezc+HLFd+vHiz6/1H4X34zQRzKXDmwTK+KG+7Gxd1cgb/6iEO/9my3NxGWrz8buK4Zd/srzS5pnX9+/HJ+oeLyssTebWv4/9vqP3xhOUVmbhcHRuXNTWTmP/Olctz6wSoPQxJcfmIEnRftcJjcdd/MbfPNDqqxGcWXOxt8wliRkdVaHgkCuSyKkpze7ZzcE2Tc7djjIAjc7aDIysknni6ON8hXDy0l7wj67CGNwglyW5HiflWR4uTDB78dBBgFKcvpK/27h/QKbBzTpFJl4fOKjKBKVQvbA0HpAGcEGenABl+RVAQlASi50DT0o+RC04DPhgYnueuxTCIE3/Wg+MxOHNNxQkT/DhMF+4LchnR2rkJ6QdDtmj3jpYzW/+rQsN9ZRrMlUN1l5cf262U0G8OijHZsbyijxbgoox2bfkMJcFt4xWN7QxkNXRxttIx2RoSQMhrcAOWZ35bR8na2klmE4lmMUFrbaBntDEjgfRmtSKwlswjFsxihtLbRMhpcHJWncRntPBFCymhwcVTGwmU0qHxnBJfRduVj+RukffwNku5/Fej5xz+J7BnjlCj+B6tHS3w=###4864:XlxV32DM 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1220eNrVW0mO5DgS/Ew/QCTFLQP9lQK4CahL16GOjfn7cHd3SkpFZjcwmEMlosIkyrnI3MzJcPbDJf56/ZTSfmwffwRXvpCv169gQv7i9R/PjHL5k8z/tr//CPb4SEa9/gpOfwTmX38kqz7yNeaVb94+hNAyfxfZh/SmNKuhWVOfY+ALvT7Y1S/K40oAcQSgVf604wB0C8DbdAqAK94DCDy3FrfSyk95mNpq2nj9f7Kyty5NaV2j1u3WWjdu661LrUfrKZDuybV7au2Nbs/H/Q6z36O7MCCz379ZcGUK+N9/1hhzS68f8vAV8ZEgqiCuIFpYgsiC2IIYPZAynnk8MpIKkg6fAVGB/SMP2Ktfkj/9kFG2Zg26OQ9iuVkXxEY5kLxOcvAZCXt7oJv3mIyE0tpREQVPNDlI+2p3l0/57h7uRq4x85oSeDA1KubINXpeU4Yq6NbOjqJoQxVUQeREZH5Wi9yaNvARIXmGCpIakghS4rWxTclGkBKlDQ3hBCmx2T6NO0FKbNY1RBGkTKPt46Jnf/Y+jbb3VCKkzZEVGfFphmZk7yjf2xBwhLSOyraOuCVI6ai0bdAlQUoAsg+bJ0jpqNStO4EgpaNStYWlCVI6KuuSs8miZZnf174sy6cf5U/pGEOLvXXsMK1jgrwGpWNHag+kSOnYEVuXNUFKx44yg1q3Sc8Lx80Vlkcpk0cZDPbB/EcmifT3X2WqhcpXVSIRcTDRIQlXJM4oVyS+XXNF4opyZOLiRUgj5Zl8/coTXektL+DWhEV3VB6y6A5fv/DwRaxfBPjC1i/i/ELU+GyCKyqHBQhUyPoFPFbUQAM8VlS6r3SRA41HCzR1Gjzgzr0mpAPu3Pf6BQS813CO0G+FOPf6jAPi3MtId7Iv0xUWruc9k2g5uZ6Jkcpya+9yvX7m+lOO61/4F0527fXCyY6bFuKu0ilErtiXkl1jTDwAgvUB2I/zAGzy7QGwryXb+8dsH9aRcGQkpIzLSAjfYrXqYrKUJbGaNTS7RnI7BVKuq2TvU2DlxSBJdjdIdh0kvw6SnoP0NDZmCdEvY7O7ESJZJW1tiNwYa2shf9vkVVsTP9OWutxAzJgHgHAmMGNFgDODTwSZnMlC5ARB4iUygoB4CSESBMRLiBCbz7ktUfFSgPLiIMkS9mPeEWtuaPeWUamdZQhunQ098ymCgCQJIRAECxE7o3BESkCGLQiWEnKm64aAlJCKIlhKBIIgKTElS0OQlHCeICAlNDdo7JBgyP9XEwl98Or4Hr27BsFENjBHkCvZ0BCQDZpTBGQDiJCGTNlwbAxHjhXBgdZJKEDTnGHHCxUvB96i0+RJQ4ZUfxBKimcfIv/pKT7mhnuKH+/YoXNS4/v6Jie1vMlJFbLJErldGUAUmJr2gurAZImk08y1NMUauaRYs5W2D3NKqcYvKdUcS0o1ZqbU/kVNVCi3Grvk1qzoX4WKSqQCUZHmI6XEC5qOhC3typafUJ5dWHnYUKMvnpPXyQ0r+8nK3yZjSyOrny4dpN7PDvLgd5G5NV+E+3xxl9vMZ7ntd13NQ+RGKpmVRAiifx8OAkz2D5oCk/x9SAQA7sfmIVLu94EgwP1SASFb7DB9xADi8KAjARCFx50gQOE4w1jiIHEms8RB4kxme8yhJh8zHVeePey4kLXMCKZO5J4qMqizqLbMg5mCInYZ0apBQfslBUnCOMRtqEjXVdKMrqvBWojG3EpjlZSQzdB+sRl6X2yGlovN0GraDOoudCmESNc9zedcSTgSdelYDIrZFoNi2GTPky9BJPoeRS7M6LHrkHplrsGQJoYLfrDfqDARwvgH2lfztMYaeqzhgmX3Wy4L9w7prhxo78pibgnRLto38393SMc/dkgtIlJs3PsApPMAcD/yv9fLAKh1AB7KrJqXT+oiv+nqMJaR13SVfHOgP627SsOWwu/Ia3q/yGvhuCv86m/N9CBLUSlx1AnLMGFGR2KZB8roIJZ5oIzuPGlXzXYxt0OmMJjbs3WYkj6vxCabXZPNfKrf/Bp12ZyvGbKZewRjL4AkcEXACyAJXJHpBQJo8AogKxACQcAKIA1eEbACUptZb7Q4YSFBrS3OV4FFAkylj7Kytljoo6ysLdb5PiUCQHVQBU2QWR1EBqDMARiAvGih2MmIwEGWLyPY3ypUuGRLTVARBPwtLlwyrHGQIy1Tj4vo/EALEgmZwBJaa6hSrrvC6pXHtkZr5dFnuZIlgcxMxfQsPMYuCSYrHfJaEpwLkPsiCXrh0awlys8qkS0pw1OEW7K0UEuW7kVCsxQJcRlxX8uIhTY/LR+ytXyo78uHpMCI6ohirSPy6nVqkf+qfmgLDy6MKDh7O5P7x0yuHwuJiytx677WLJ/lJXSKVYq3M7l7dCX+0ZWsscrbipu9iNW9Pa7h67E+jut+W3ozONb3S28+Tf7JjZOqxdyFcXJULfIlvWqhvEAwZjSpPUGA0aQ6CAKMpoIjCLg2JSJBwLUp2A9zkro2HVCfUMUu7BCaIn0SrU8Mwbgwh3KUU4sG8AQBDaACvQc0gBKOIJD5UTZwCmd+DxbRb8TVKagM+o24OuUPgkBBTFpGECiIoaznN1IQU0EQBGdK+hxUwFLel1Th8vvF4nSPeqQK5B4J3xdPOPaVqNFTXzd6/g2jR1JHt29qtW+XVTHiCT8rjzXHF6njS3pxfCOlOOQAF+N3vGf8jL0pjbmdnWktxLsdjAAMNHR6mdhoF32uxTBC6qzPqRGao/B8PsLdOcJ4wc18e3s35NmohPccoYrrCRVwhPpfHAh/V4D06cLG79/fO3tOUg97Zyr69cyOHiNi/sUR4TeFT73L89Lwx2lE1krsd+a/m4E9c195I9pJgbIkxie/GASwAZwYBMS7GSEGAVi8IpBOESNXBKfTQBCUTtHpHU7TaaDPmem0mYrRxXZGp3RxfPLEaKi5K1c7j07r5KHH7YQ42umffP30o/wp7UDCy2u/pep6Ta8YW4VgkqpRldmTVF2SEUYgVUulCYJStZcEQanaG4KASVfezSFwxKQrKOcaNzvlRqeQLjDLhh2oDEM37JBmMXTDDjtLumHX1j8g06UHRgMAk668nn2yZL9OQSHa2NmnWXhQcM7IYEuebWQqm1up7G1t00WmIQ0kPr6CfZ1afZ1YfZ37//J1zt56pXjhP8zbOzj60dd93SuZW68ULmLl/1OvpG+9kv+uVwJfoalXAsBMX6HBK3EEU6/kCIK9UiIIJndLEOyVAkGwV4oEufZKmnoluMWSPp28kr31SvbWK9nFK2mCXHsle+uV8A5YmXtfK1Rl+ie3RGsGtyi8aUV2eBbdzya1PMj9bhnczT4OVvWwf003ePwX9sBfv5Tcus6v8kBe7BlYcbHBY8Npz2B5EyU5TYbeN0G2DKQ71r2KuSV+VnnCyjt/8QkHkdc5sMXPmDT03tnPcMdJP9W6N6LvtkJkzVdXulKlCzo27lZX3lXX3Bf20cn2uQdrvmPxGIBEAmsl3Lw8Vp+/L9pREwTRS11QorfWDja3axDRVOUJ16h5DdaTgTxhUo4HEZTXEC5F71Mq+IMc2m7aVHSkbcaUmwm5gKipCFJ3UKqqdwO5uH0jCCIXKLFXZKo73Wv8vSzenuUqwDqQqX10up3UVZkR2YfPq9dPMrKDjDQmo1ny0LdHarWeJZCl8rHfb3GTUggqgRhcAom9dKDqbx7Ehbe3fL7aATY5t+dNzjoI4tbLp1OrwvlnnfPlAyrh8w1oVTOXuPDylttvdhz9xEH1Hzb8WR9ETNP8fURBiGOoZ/ja3WKo63J3O3zfkudM4eUabBvULMU2BNmGmaQbgmzDZJOGgG1o6wIQ2NxT8zxhQ5BvmO+Rmr/8aD8ZUBoj4CjKPKg80MUX5I6P92Wca/cGvy8zw16Uw1xR16pu0YpLOnfnVafZ6YTYJyLzd420d0JJaujthhBi6KUjyCDl0vE8WuzDEaLwo+MWF0ujvJcW7lFahDekxa82qaikqOpRXHWRgm2Q59dD+yepsV+kYvoGq9enIkQJe5OsrWIXs6uekrV9TNZvypW27rE8suOwe9wvqER84aAI2oEuj8EFJjV/K1WR8lLlaWzIpBgxbXq+ZizXudlcZhlrCFX38kRHWu4tTRA1UXsL15h5DdIV9QczcI2e1yBdIRO5Rs1rkK4ARqzXyHnNUrEao4CIVhuOc3S7refo7DPqOTeJz7mF8fI5slNxVT4kx9vMclYNbV33826OnHe7+BHNOwnerAleva72OP4Vi3Pa0WieZ+xkXB38Da8vM9PxePDX4F0OJfzd8TYfz6/ZsstxO43vvPcPB3Obb90vRJQOF5F98aSYqqdp1JWY8uHcejSnA1tfLrfYh6o/U3c7FPaivwd7ouLbX7A+zwQ9vK34dpckPL+IzD0f3n47W4THAps+7yY04nKU2PlE+EaFBg8IIUJDbARBfD29UkMQS0tDEMTNlraGGBkEDd/ueNhhHvZpOLKybPAPd5WzCCFlJS8Igur6LBAEnB/4u4agstLc7WgIdn6GIHCweoNbJP6hjU8cAUR/z7N1DUH6WyiCIP3NN4Ig/W3pc5D+nock6rrB1XkBUzC3UcTYcQhbQig9O8AIAmcHoCDXEHR2wCmCoLMDibZWIv8vsAYmVw==###4684:XlxV32DM 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11d4eNq9W0mS5LYOvYwPIFLilIq+iiNIiIrwxr3wsqPv/jkToMRSZtnxF11VnY+iOAEPD0Tujhm7vZaXCP+WX3+AOV9erfvfYNXLCbH/4Y18MaPN/gfY5bVyycJnB3sJ4PtfAo7wXPh9LPn3qePvn37h6f/exH733/8w41X4i//6kd4XPt//jD9+/+NPh4DQ0f6nOER65BAYgSMg4UdEQGPk1AExKiIAgF+z8Iis++/fjmm7vtiLxaky/utvcPy1Htbvac7ruZZpnSpMQ4g8HSHD7zBx8/LS7/ED1T840ge6faBY+sD0Fi59YPsHsO8/w3jKmqWX/CxrFtauN9Q6PplWpnxg0gdQWpZVP33qQYoFr3acKgt/KLylPG8pbHVLtYKypSvXZe5O387dekfnbr2lc7ce6Nyt13Tu1ocZ/ASdRl52Y3ltd6duWy9D5JLjU/dw2kLv0g2966P0bo7au9S1dyXrAizv9X4MFqN9WV7mr707VXtXw7LycVnXtqx1NeOaQXtv/ESi95qlvvc6q9V4sq3ovWp8r76+t2xe37NowxFZg3HF3Yvm+yOtNLLmYLRbMcA42vBsMMBgnwHREhriktH+SCsZ5pfhE8HJcsO5johirr42NA/D23Pn8a/Q+ZGf9qSNbm2ibzjzG9RK2qjWRsU2LrVJzrC3ka2NjG1sc1h1FaLDKjNCrkvb6rrSSjU3FJGlISytT+mnLJI5ERy2IDwobJ6hI0ice/iRulwJEmcsdF45S5A4T6HyWiwEibMLP1JvnCAiInFSSufOwjL4tio2ulYHPnhW9eIv1fzqWf3q1v3qT8G3q1+F0a+6wa8Wz4v8qt378RSGZ6cn9DnyWLGOsPHFOoRS1Sr1NrPKbW6V5QM5Oju+YzsV2o++jdeR8MtIVsOJnerR7ZrRcAe7jMufdyy+OJsc3xJwNuBMdhZOIY+bLF095hHJJhUfxsdKOk3a6NYGHTBu0BvwAetEnJF2wJR25RiFw1N7TMeICREZWodzpOs5Cg65nCOBz1GjzH4odFoszKHQOLRSJyHXYyRXQqYuGI8evG318mqrXl6wtXl5S86T6Jsm9uGAyXbAhv3m436v9FyJbeL/5ckuI1qNm/l/NxuAmrM4JoK4UWVzw5Cwk1eshnlx+dKRq16cV/KISDly4WnsxdWqSBvd2nQvrtaNtFGtTffiignSRrY2zYujA5rbRD93mnRAAfu5/Fw+oNGfBqf9Wl/QDiirB1TeOjoxhoeyAGr0b5h9iWu0xPEFh1damhINmn6SVTpaJp9kYatnVH4SDqrVX/2RM5dwkAR5lxnUA3WZQQr6aBSoSBSoePxrxSOzxVMCXG0MGLGxm/dtxGDsokdHDMVgvCzdq1XWidvl4oin08Hm0Gk2vjCbg4nmAKzqlDjR7IAtH04xrzFNfDhbgxmtgdeYJrdJeqdYQw004iYj3w8KAziQkN0zq8Hjd75Q1M9nLuhI9/NytQTpgYS0jiAokDiKgRnfppQNTCqIGu0ITo4dzcR4NTH1YGJFkn0UXNj9GvIWiYZMrSsxlVyi6XSiUpf3Rlg+iIde2CL7bA7rBZTxQx+/TgQAxcCgD1slFwF92DqRCiD6S94FEP0t+4PGPOcac0aUthFlJ90Y76iJf9FaXyOv5ikv/sWOTGnmQuXCWFfLjOfJjf6lqEzDXR0ZNP8il2eVmeK7S8YEamQgr/50Xcl8b93mTEVf/Kfd6fxgnN9R5wffn58a0wda1v1UV6/s9Ww/3Ywv1OPE7dfpAyFnoZDW8hoKST4LheCDE/bOnvzjjuZEJY2NwHqEZJccQoyIuIUgPSKKHhAjPQ4CtxGkRz/gJEFulGu0i6xc4wnCylWo9rBiZfiQxMRxICCPHmwCPAHi4MEkCqJPxLFDXomWJMhIHDtk2XCsBIljB5kRTpBIJyAoBaXJpGygzYSmACFZhtskw4Vu79Ebpuzw/wUheZ7GZ4QRpDO17HuhN8LPiDh13SXj8thcG5sjKQLpWBNeqqQI0oalmSV2D0hbjdAG07uQgiCd3oWiSKN35xkBGrs7vxCgkzvYgyCV3FOQHLMBzIS4i5nG4Wvh8EO9HyYTUv+Kw+FCArfxshs5G5G4aCQ+cHeMKDtXy4Ff7zmaUrM6GzVPpKvZn9K/5zT925k5htPrLNDfruH0KtxzoE/c8Vdu0tzvwTXi51PudNchwjbjThgHoN8cAPOjrJd1AOYT5rjEJmomgu5EdFyJZdisSmFqszebNY2a9P6U3oVpeveGXKOeOZtsWQiFyVMhBFOY9AdBOoXJ0xCkU5j0J0E6hcmT9tZlu2zXRRlpsj38f2uC3mPmCu9RCEHUFRBBkMZdRXx1pJOXPFeCdPKS3hCkk5firI2aE7qRfkUIpht5ngRBwnBhBEF0c1Kk043ibabBSSChGEbgEIKpJJ/QjnQqyUbUEZxyPgjSlWKWvB1BSvEUBEFkEiVpEoTixXwjk62Sif5YEI63eIVubslkdouXnKExo+Czo0Z0RAFSvtlG0ShI5mYdNGLJ1X2mALOaPCa3jQYpwoFtYBSCdhSCrmdM+7WjMFMdeC5XXbTot3Wg25+8v3m8f6Q0ICyMY4WaozdXzer5bKxm//iu9K0sazj7KfoSN+Juk8d1iN+6mI9iVo+XmVXs+fO6aVJeCPljKeeGnTgmPKjNTXZy4dPL6id1beYjQ/R3Nu8aNwDfbYou4OxBeFFoQAjmxTzCjiBeBEUQxIvuJAjiRVgJgnjROYI0Xuz1FXE6ROo1bZKQXl8BvIf9mjCpaJeQEcFMigWJJkyKMoRaUya1tDfEpC0TmfYACTd5NEEVLLiIozj8shFGIpiot65YEtLo1HVhmYDOpkIBQRqbuq5SExC3wYzJ1YTEbTBZfZl2VWYUydS2aCsCRMp1wWaIlEO6zMyUnCFKDstCM5VyRo3sm9KxZwiXOWvsKyr7mkvJDKFQOSZZv5Bw19qZY2Rdv98lZs3IsfY7GdttzNgmRr/PzE7kX6HfLwga6UCiGAeCTsHqm0TtRqI+97k+xEQ9uxDSh7u6XAZvk5961Imf0oNM6aW78rRNuv+OBe0yCwcOexMOqOfQ5eNcr3pIeVo7y8ramyw7uOes7EzJfqO6Sw2bNtZiaFU3Df7DTeOzyEGz61sO927k8MX8vxTOQnbi5pjs3WEIgLh+9QRBXG9pZ4jrEcnwK9enBG+wmpLgDVuBWV+2apGIZGr1qscD7Wk46tOo8lIePWixlX5jmzPTj0MozhF7IECPDoRlBOnRQfbYHenRgZCKIF1nS9gI0pLEwHpny5DvxQiJGFDottB8LwrdliHfexIE5XtR6LbQmAGFbguJGSS02C3sCMkRHy3OMb7tgy/7AMwhlFz+Worgch9GkC7pUdBnppe/hlz+gqKPtLvfHFzXM5ZLCNM5JGG2Q8ebpJ/6bYjlKMz+7eILYwka6yVoTtY4xT5lCdzTtTHKEkxL0XqYEgn2nBCs6TdonWA5ezu3Z55zezM6ccRXoZsJQ0u30G2GOWmipp/7hLRtxft90uxSN4j0CK5DWAmCj6IjSD2K0eW7FJGG/UVF3LHANu+0+7wG5/1awx6Y3sef8jn+HMJOt3952aDH0PEh2ROXx05v4u8CO/d+pc/7pYm3N9XC+UmAZdabZMZ5Poec79YgwUMmyMFYK94uBG5sVZpZtab+KLKNfNuEl4NBZmuEEJktD4LcymwHlEi7pTtPk8/d5ztPuc9ZgnTuy8vVkcZ9sG0E6NQH7dYgI4j6uqt3nsrl7gOcJR4F0bKz1KN09essvfqUjiCd3OCUBEF3nxsBkBdcFUGwYA6KPbgnHdPVvYZVV/cE//7u047parc/FQ3eC+ev5LAa/ZLeJwVL7FEW80EWF9F7fz16k6Z+qD7qolZaOb38vMk+O/X9y0+1P5m+eRC1KbOz3dYlqZu6nfWjb7/kkvj7ssebjKrUM4/2sVZP1Yh3EtVs/DKtL640nwvB3HeT6lYNFVPt1nW9SXcD9fZvVwGhJHLYahTdgqpKMI6EBrcnQsjdavOSGWmyEuV2w1uIymuXbXFPELeA0gggd6EgCIKoBSxBUAYXDoKgDO6xEKRrtOyKOtILeYTpgedwS4oiwuGW1G0EwUU5miBIpLW8atocLKuSD0nyJPxVS28ELb0xbWtDG8Q/oBQBcGEtRVBhbQuCM4Ki8CbyM4Kj8JMghH9srr0Jp9g2/jGVf44p/1DaKTz0Ton65CuOODz++G7Uze9GSXr23xbjdLZJ6aq73OtNJjWVvEpxTjOoy9XTbe7pG5awvxvOPnyxUjg2y2TGe/NLmhD+/9/9zBEEibi3QhOgr+yn3dvf1OJ90dDXAKTaJlecar1Wya76nNUcfVjhE62Rck3Nghpuv1+dm8o77xhMu/WGwfSFwb4iLiZ6Cg1E+c7CcSa/I1rmUG2UIHyrWARRvqmQ2yCqaN9myG1Ua4NIQ3H0bpLY8w1xjObvDEMIogZYJAFu03eOUWbomVXHiIax20IQfOV3EgSl71qeMroLcuVnEEAkDLcEQRwiOUEQh8iNIIhDGO0NcYhMi/M/0QYmbw==###4624:XlxV32DM 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11f8eNrFW0mSHKkSvUwfAAjGTNP+n0JmBIOZNq2FlrK++wdncoigsqpVUi9UiorH4MDzkaifX6gU8SGEeH7NP/754Yh6kAf7+YWKUz6c9gmIOgFUnhEhQtiMBEDcMSEmIz4hIZ4VkMo+hCcJ8AK6pN8HEghLSFB5fsU7wGH+2hmEUDoA+lU4+yxNsiD//HNSydiDPlT+9/Nvd7LH4U/7/MuZmJ7C86/gaRpEPb8Llmd4fkvrTf//5ax5BOmf+YUcLwK8UP2FovBCjxYWXpjx4oQXdrxwz2eRizzyQOQnSBMUe/7trHrocCaxjHxQ4Y4kqSWP47CuinrqSUQb7CyiDecsog1uFtGmDZ1EtEHPItpgns/vaZPzhuRTAVlh89NTOXzGAeEOIeXw88ZnRE9IPvz0A0bjE6IzUqjE44SojChA9DyazIgE5LAT0hgLRy/SsVP34OlHP/yzHX58cfj1aGUFVP3/9qiXE060+S6MLoAZXFAi9zCjpYKdN+d4AWdj3Hgh4YUfLzi8yIRPk7gqtxtya5YbuEFaBaR1g7QaxHBjJZrAiyGohrU7JGjMS4p1SRG1jLllHC018C+OJWkDL8aSNOxbHEvSsAsxjBdVRfxORQy7qkjSjI2KuLcPEivEogcW6UESiPJVIFcF0u4qEDt2AumXOmtXnTWrzqqus5OIB11E1LKKmCzsRUQhdiKeq4jqpVm5iGhXs6Ln7WRikdWQIqs6bkwgt6/Pd5pYrRv+vu0cG4BN4NFNYNrhYgJdMYGCIqSYQFdNoJqQbAJdMYGcT0g2ga6aQD8h2QS6YgK5mZBsAl0xgeKYkGwCXXGnh2wI5VVqU+ZhDiFFalO8NuzsQLLUxhfETkiW2rgyD5mQLLU5Sx89IVlqU3ZHzBJkqU11EKGbdL+4G4aQ2d2ICUHuRsx9sLtxE4LcDXJefnY3yEV5HCBVNhdEzBHScSBkipAkm5AeISWET0iWOpa9FmpCstSx7DWLE5KljnZ14KJKHQ04SRuSd3zY5CNtd5GuushAsIs0R/VnqrgeW3+31W46X/73ouChGtoA+Hep4P03qcAQn/QkWXE4tqZHUX9ObFV/m5xHUX8mmzCO4clI9Ujgmb6niLEalxOeptF9G/38hNH5MrpWbXT3CaOLZXRD2+j+F0f/QV1o6pXnyRz9ms4kI5kLA4HoO51a6eM7wkufdK49lBcAUAjlv8DWtyfen8QU6NtwoAFRoJ9+d3hE59uI9Yn3JwFPX/MPEPHsI7IqojVlLoqQMpc9Sh/bEVr7GFX6EISUPuYAjfHUJ42RD/aQXWN80xh6G1SqNYGocRROEyzy58KwoiMW4roDs7i6SBn4lQmWNxepFgcox7TJq7lKNGtzE3ETYUmnL8Mfak5C1BotXFZ1H6X8gC0su5slwBbe93A+Lz1JmvedlRM5UR9s4V2ETap9sq1sbYatP0mY2qjeplt9pWNNIoXtaEkiPTHpyHMiMfKI0I6cvTpy/3yZN/QjRzH2ucbHrgJ+Da1LLiAFqaQ55Wr6Gmm8vJLGsB1pxBo1sSE4ZpEh63yNRedxZdGYT78Mw3G4aE+92tzQlqU+siy2I+vxnJe1+qcWnsqTv2tZ2yx70gXS4ro8IY4bPOtakpYOupDOuNitzviEZDUovXEEcVIytdG9zYglrD/RDDiW8ER3qcisoT1ytFAJGhrqwH0cFWlSkUlXkR5CG93bDF213qIZsIYaMmko9LMA0AqkuKotE1SXSW5zESCkEIfRrryxKC8n4f1FgE0FSNpVvd3LClCpD0zx1Jz0a5zjt0ALpfQ1YVdrjq/XKoCZMvia0t8Eaz7ioG3J9FuCv1ilc83r3ZrX26t5+hYMTJlO5pKqNrORdx30i0lme3rv3p3+XbJp9TL9u1TApsyfSRVWR1ljVe+vsn4oImsbkmeBNOq4qS8Ebq87Is+dIT3vagOsZFziJiT23n3eIsS6Vbpv1XURTMm2CPKxrRLrLLxt1c1atJqcAeIKf269wxQ67dxEkoSvksgmyXk9NC13MdSFpOfzHQ4kb7hfBVBtw89PO1Zl5cb7irNtuNJn33AzbbiohlWu0REEGWg3lV3PtTldcZ6Xad6ISO3L3TR37pjJKEv6ATqf1v/8AorTnsY7D09f84/UT501oYElIDeeEN4Rid04U16iPsh5MxXNhHSXnX6vDhRGg0C2tunOO42r0IyoEJDGtRPSCgEjj4NlQ84Gy25P453HeVxyrzWCKBsy8jgmfcAj5pytjFifxjuP8zjW60+gWXDTU9qU3ZRC9gkDvPwCxiDvK8gTEFzk8bEgum5cbg7RCcyA6nIQLOA2urfpFTpWKoGjjepteq2O9SpebdNrdaxX8QqpRi6afue9D+nrdn3drcQGT6hgx3qZsSK9LMd6gascwUhvmVQcISO9zfMcfTSKAz/Wi29sFDoh+kq/xwnp4R7rBUg2Cp2irueckB7ksXzziJFefGO9yMdGoROKb8owdP9Xj6MEhgcKDKuilMCQ6xMKX2LkdI7UsJCiNP5FLncJ9m7y+BbrXWtmJfwaMZGQayolY7XlMVbzxyW9d54vbThXZFNNCIJdR7fy3Ykhn4w4V3STEAZBL/McRuzimPddeqRd21USfQzXdc0e8OWuCbmrJProf3H07G+g1pc4nc+++Ja8nvbEsJcpVro1LhY5N25PbLbNutkaQEZFDLg/EGyFuLYdoZNh4LpW0eB4i32CuYt94pr0jqTa5cy3apc5koW0cVmRUqNxJ+OhVbW0eaBijUsbZEa07L3JnCtylCvWfkXzVTCg+bSXvFUr4HHaqzlyTQh3d4iXmsVI6eYsK80MoZpFVBJVAY1owQ0d2t0rCvZfyFBNi4Qqe9eWb6FkeugjDJAqU6bxRvWzykjq0GusLEqEpKG7Q1EB98FuQx0cz4PchuourSDj5FWrMVRknLdiakKG21DtjqMi3W0oIxoTskoVVFQm8IUJJ2+lAXr8XiboHRPsf8kEvWWCXphAETIzgSNkxwS9ZYLeMkFvmaC3TNAzE+TMBN2ZoIlemKBttwl8MOFaOXmzUrKWbXs5pF+DMaXcwgSp6y24+dNMoAdtEVYWC4613A3BBg1kym/GsSYEXW/iYwUE5TfjWAFB+c04VkBQVjOOFZCe1SD+ZuCevwlB/FVGtbgw5wFlwMIEmZhNHzqFSbrHhbQxQXzkQvT+IhQVwCLbhS396OGapwYW7ENhi4zHLmxR+hNG312AeqV+cfQcFMUa5+Q9qgl3Wk974jgokqZnRnG6m6QMQos2TE1g0zDtic/hUjdpMMFIZaXuaUfujOIoGQlCUBwldc+vIpszrxARgi8W0wtTmWc681hjntxlJNsLRbdPRK6JhyLb1ICF63la86GLxtRV7DIC5i7DH+Z4dZdi7kthYITvNYqiaf4nTJrLxmwT/L/maMvx895h/8OOwReDmVoJ2ZCZfAH3wQl5L9nkTax1gdy71gViRGKg65iEnKjjFFjDNh1ddChzBIHdqzIah88FreEzoReaHo2mCtO0kux9V5k3dwX9mxFEU73QtFUhA4sfoSnb0FRurvwC859HU3X58qV93+EV+2SaDjLmWaeKJZEYGV97pN97pSfISjlFeqqnSHfRRM8FTXKgjpPDhyUftU+jnJxdPxFoXOT6kYOvH5lUtVHG4PJOGRBYehBz+UrD8cZS/eEr+zfu9MbnGixAKe725l3Wm3AWmP4XN+/87UuIcOzsq+TkMvEbV/DmPXcOP2B3y4mEQ+Ag/yCuucS8GcgeHUS1AmxGSgE2HLNlCr26Xdro3mYE/mnv0QxTym+xzSr9ChsYj0t4b2MP783vTPQCDHiX6FHfdN1b8aczvSwWjpQDkwhBkfJB2m08ICjTg00dCM70vCd4HpTpeTdJgI7eOzkh48C9m0cbntaf82go0ztxplfQEt8nXc4fBJBkGyjppkE0MtgPm4bz+ZHA65O+nkzLOHZfhil/NTVWvG1qzK6WG7jYfSIm6dWywNzvu5DTz3c5y2DtJqZjUl0X+rFPLdPo5yZLYlL/+ujwd0l3WRKT5hNGj5swgkn7i6Nnc91y5zwP+kwUNGggKHCoJr4g4fYzUTjOkn/lra9POvSnOIXFyNbrMF0vBuvwiHCVCCOWJx36U8TXi8lzdRFza5TMhV4UzwhK5lIf1RE7ZXOhl8szgsL2g5yhe6nFQw6DmnR48pBQnzoqUj0kXzxkL2kUBPnF4Tuht+q9kYd0k4fk2EPaS1G8R/Xnb/WQNGw8JCPqP/SQNOw8ZEJmDykQMntIi5CNh8zz3HtIQG49JCC3HhKQWw8JCPKQfvKQgIpCBUHXWqjsVHC/sxYaGN3UQln7k4A/R4Wkjl3VklyoGAo7NBBcDMWRD52KoTjymb7UnCKf6fvMKfKhUzEURz70vhgKwCbEo3MxNOBiaBmwUoHzCxV6FuV/KxWo3lKB/XkquB7qUj1Tof0pFyAbKlC9owLVOypQvaMC1TsqUL2hAtVbW6ZnKsSJClQjKsBf07KUUVPW70h0I0P4PBex/FVr+/K1ffDavnNtn7duv2ptwfPJfNzdu9Jg/jCZMrXNKk1s1D7+PLURTU2h9v8B56QT/A==###4616:XlxV32DM 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11f0eNrNW0mOHLcSvYwPkCSTUxe09xm8EMAR+BtroaWgu38Gh2CQldmS3K22YbQrVY/JIeYIRslkH9+/puxfjhfx7ROPOb7IKB+feGK2Pn2G/33/yhNXZEyKuY+Bp88yxDJG8FOWMfxbQ4KJgJzwdoycIFI6QFxFQlwQC4htiFkQA4hpyDqbBkRXxIcFUYAo2Nvhz47A/tXBCmJ13TW3BGm75n3XB0HarmXftV8Q2LXsu1YLAruWfdfrbLBr2Xe9zga7lrBr7dor5Z/Ak4bKCrAOBGQWAN+9OFR4YS8S/r79HTx/EWVLjz+CzS8ny48/UixI1o8v0ooyx+N/hQzts3KifEZZP5Otn57HEwbCP45vdZ6kxePv4HQhVpk5WfXCI9dljbJdwRXriwROJz3aZwamPr6kg9NFgAiGDSKU9cr3j8/wvyGdAygToUxGlSkS4pDEgpwUyQa5DeQhyxwcEFEpx0+gnIO/TjnDYqccPwblVKEcP9thpOyfqn92SkrTP23/dK9R2hflAuo4QmF5NArzww4KOzkorHnfjHf/YBOdvUUFKieKwDdOxNw4MekN23q2AQOhmn9ETZBFu85AkGvtqutcaldDrrSrIVfa1ZAr7WoI0S5OtauhVYmYzbaIgXkRLxaVSA9RYFOJkJqyEq3wp1hEYx7wRehAnICrQKp0V/Jon3pVN+YOAAQRBpO6uh2yCQOzMQxhcHYIgx7Mr6u5xB8oBYXLdTtwtAjrn2R6e4zpxdP0wooxvdllqi9jHyhcQ5g6BbdlWFvGn4Ys86e05+MPV6iVYkQTwqkJ+aHp4KL7nboqMR3l34kioO2F3g1xAykEAblsY8BWVLiblsqOQr3yYtHJinjyYhPOHBtim4us74BcjjEgpjm0MZHM28Q0e0C4MWSrxMxpJ7qY5oQzuiqm2uQipqyYrDKAo6SaIamKSuoUjaQ8ikb/okrm5GpSkXBVWt4/h8eYwq41DLRhfqHqF1Pq9Vm/aFIvXZ/K9anC3JVhMDDMXelUv+j2Kyz264ts9uqLTPpZAy1q4KJ5cdfRH6iiYbuuqNyFOPIuxFoKtMuD3v74sdgW7slzU3Q9NFGcz7M7dafoYuVm1Xyi8bp6CHqK4kD6OuxpHWHlk8b3afVjU313qfqG5X09Maj2vB5Xxy8oe5m9+spldjtmP96BJ2rniRu0Er/CE7nz5Nx4ovdThLEO/xWe2J0n+ponnO3rxU61kN+BJ3yb3QyOh/QOPDG7QzwHrY438WTXk91llfC2rcPzP9OTa1aIfRk9iBXfgRXnPjsyOrwDK9xdbMLTm0zWrh7+Lkjh8beoh7yLVoJ/I0+K00+A2OLawaFAaPKpGsn+BLF0f2L4xPFJ4NOJT3KJcrQZsUydq+Y0jgNiUk+qqsFpwYqNDTl6sAImrwUrbUzNlWqwYmLGt1UPVqxvK9qxIpwDs6iCKInvyB5XwZgeV+mRmFVSwJefqh+ECKvOawjc520niYnMS3KCgkQ8yYknkTQ7KGMcvn3S7KCGUIN2cokQtfL4jh8nKWPwJJPoJ57EzZMkArd5WwBpkibz0gDSJIUncXgSvwSQJk36OhpAtrRtCBnEj53w7ammckcXsvHE8Ung04lPkkah5UARDzQS59RIqCxuySKhxCQU8hQW7IQyk1CBwG3eklnWo55kXlIaKohAQhkk1FIkKmM4vm1okais6HFFNtSlC68m6jJOwuZJFNGzcRLVT6LdOdJJhyLoKiA7YBNqWQPUqOI4PEEDNA35mwy0kB9khEO8r1/YiPhFFiPiNyPil2uAz9kW4HP+aoCv1yjd2bVwEfIai48YPNklkFZarQG1PmFLjNhZLh9/Bo+WNfDpMYg/MFX4qH3m3WcGNsIyoyP6A3XnD8zjp7JXk8JW8iqUbf7AjFDAOH3tD36y5AWrxG0Vwccq6f1WMXu8IcLjr+DlC/tWwe99SUkJWRdyCXldeHz0ulH7TEfCY6T9GCPkMPEdiZW3Vc4R95vwTqtQmwOnolbORkBkRUItNn6qDBxPCZ8yLUUyY9HBFFoXKk6XFhiuFXuR0hH7NhBqoYxHtwK7mIVN4uoBoS7ZTAtr4rBqBmx4KnDMAwXlBFPW0MLn+vLJycuL30U/1pDpbW01A4NUPWaBg/QnjIFSXuIYE9C+phYxFF+spmccCPXSJgjCsEYQcqmB/Go+Dejcn9BHprz4OaMT5VeoRc5cjbKh9r0duhvlwsnyn4HiccQyjB1G2d+VYeJehkl7Gca9aqXtXnVxe12GFGrkXqgxv1aokbN4ctS6jNoLNa+UcgzHUk7/om4nkA3nx1NlHB3LrMjUiyR5VZGx/tkKrOnNz9saZ+4qM+eFYfbH6xmnvcs4TfWr8qoycz5bTmFWt6b3Qgzxc/4n8554d7XjrXs/091M51XJxtp3ZJrbVxmlm/PCQdg1N5VLKtpvUxYuPmWvr7AV1E5fFXdOd8HWNXuVe3Cidj7rPZ75J4yXO7GGz7bm/RjvwkYIrKicz9oqTvbThNCPX9aAgISYtFsoojaKYFmmONj3ii+aa1TgXSKm+BFT/IgpfpT4pJ5vQ8cE3YVFTN8ipm9R4pNaHVxAjw5TP4U4OHcLZ6LApxOfJD6pNdgJ6DwL63uoAWNaAmXGJV2FSRtAiWvigpBcb0ZJFSEZnncLMjM84+WCYBtA2UxYELjcDI0sHuO0KNeYK8y9YSEgynkonDKOQgDYop7fGk/hpTjje9tFHQ5nbissZZoZ7zm/Fme8Xd7W+PYs05ja9DDHKBwDFLGN8nHdhcQxQBvbeOAxhY9ijS0D5tIOc/8oJm2QRZEjbcykjSLwUu7xAndlkDZ2DUC9Jms/l3vm2xrfxsKPdnaJ5tzMvR3N1hsp+nUbEyXM4/CHQZ4bQV5YWiv6PWkNpma4BVPU/OLCNTgxEkvJsLBZq+fTIrrFvKHx+lp31oN4dvZbdttqFtwSpKlcOVg5TtDQJKLgD0/j22lENvQ02O6g9sCUthosV4tL8dszqUG51EWgo8UIdKRGRyDzcuxLu3+b2D+7u69BD3sAGyFNCEwFTRDShMAU2oOGTLlTmHI0ZMqdGq0GHZllRjXajzoymhCKVEFMvjfshMEHe8mHV8nexY2t7q4mG7BYvIk4jbHPjBDHU8T5o4LKk5t1i6S2DKQSwi7dVkwaiqys8AtCWDGZZNcctIUPExms+O6zslubj89u0NvNNp/nZCR3rc5dzLIjN897ywdeL48qmGdO7W0+qleVhB7hkDv8x7T5sMgGhWBftWenZdsZ67kANBY1c+4EI0hjUU4V4XFBZlHbcbsgs5Tt+LkgsxfCsbwgoC3Z0d6kBszeJOaMJgjpTdLOj1oqOJE2Ye3y4by8s0qCg+aeJgn+N0oCZ1nfSELuN/+cQV/MhwgCHwFM3RYRhEqgiRBJ4GxEBBUhklCQc0FQEgpyLAhKAmfOLwhKQkHUgjxLQgNIlxo/6HEWSQhEEvqEXRI0320C10MSwu9s/WO11HfV+hftR0sCoWkSdzQtCKEp41MQkqCdf5WmE6Gdf2x5h3b+EeGpyOz8I8JTkdn5R4SnIrPzjwhPRUjnX6Sdfw3tkiBrSxWHMG9EeU6gLMTfJwtvtyq8pptXspTFB8tSEex45+yS+2jBLpIwusxhW6uB0QuyGRhoeAeytqb4OuRJLcaY1hQPYxYFwdZYGLMoiOUEuVaQuvalgjTkSkEacqUgDblSkIaggjDuJCHL4hNkJsjqE/xCSuoT1IJQn8AXBH2CdomqaNtfa4fMixWPs2vXJVmt+IlWPIY4NDfdt77f33P+3P0mrBxuWt5EGgVjBwH2rxeP6rniTfOWSPnts9dvrvqRRD7ePLs/xE1njcjsjbN/ZSGNQBHWoTdGDvskAKE3RiGNPANOfnlj5PDGyOGNUR1cn+pSpKDmsNMAxtCCmq/2AWesJTOHd4Z1xvpUZyRltIB3eW67GXRRE4RWqULEcH67GXRYo3HLzSCkQucW9tiohsJk6urCSW6BxuXPuPMZVz0Xzbrbb0q6AhWhqw1ei6vq9zhC/hup0KhLwr6ajSYiMYCbfKMgxOBn7HByvW2o/wiKZk+9oWNUP0n2hC1BrfpJsidsBGrVT5I9Sb9UP0n2JD2tfmp/kF8NdVQ2Qdh/+qJ9z4TO43f+9KV4oLv4V+j00YJA00txm16uAXBkhiDEv2cVCEArHTSNXuLfJY1e4t8ljV7i3yWNXuLfJY1e41/PiHPtaBMEaZ/CX+vHTfbB/sPhL3P154eXoiTtB4sSWLjbYo90H27hHEfvILdaCz8W5DkAroStAXAb8qQWY0wNgOsYqiABf2kDY6iCnIkANwpyyjsFOeWdgpzyTkEqcqkgFZnxbzwovWhxTFoCrMWxcyEkLY6lBaHFMbcgM/z1fNHQur0a/nqxlLMkLWcdT7ob4Fah6S7/L6eurAZyV7o7fkDwkalrvlPd0aD/76Su+TZ1zTepK6vNTTV1zXepK4zpqWveUtcwqzF5q+1kgtzVdvJtbSff1nbybW0n39Z28pq6BknIspYzD4LcpK75NnXNt6lr3nT3XKtLGXVXrgVIorv2fArAwtBc8bsi8f8DK90znQ==###4648:XlxV32DM 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1210eNrNW0mS3LYSvYwPgHkohvY+w184AmOENtZCS4Xu/jElmECRPajbshdSsflAAMzhZSIBPg7PGBEP8nDlH/nxR7D5kWQ+/g5OP7w//khWPRi14vgjOPLgTLNyL9KH9O74KqUsj9VfNX71+DXj145f139jb68Irb/fgont7xRz/f35nbJYn2A/vrRplXbHXzLZgqTsEVA6KkD57+f38ndASOmqICE2xAqElMEqIipCvcG9SVcR1xGxILYitiNkQUxFTEPcMjepK6I7ohZEVUQVRPsOlD/lAWh5nZ+eRhoe9FGk/lA//g6ePXgM6WiaEUQM6Wd9fJNMIKkX/dhHUu4A8Y8b/gA9jBvhmAr5Ji2rv566UPviyAg06UagEu9WQJ2xYAUO5uH1Mr5LbB3flaernkPTbxmnCUTicdgYp0hsH4frAOOYbRy9j2PW93TFas73HIZWDKxKt2mkTaXbBBMN4RaQUK0lFMSyirjk0DPdJmS1CRpyE9t4ptoEtKnWIat1FLNJSxs921Q7kbpZgx7WUCwRUFetIStdjIGyYg2UDXPwWoA5SDAHhc3hnU5p9bCFgduBW8D9+A3jN47f1H/daB8idvKia5l3Yhk2xbUDXRP/W5ilzibts9EwG/ubZzPYrNlEEVIlsi9tgojXihto1KbyWm+DGK5YMwfLLEinS1cts9rNCXQzt80cHRcI6dRnU0NYWpBq5jZ2xC1INW4bOiIXpJq09R0hC1Kpz7o+6XMGeUza6jZpgwDsm45ThPRJS9eHiQty+qZjdkFOj3RMLMj0Q+poXpA6adn52oCHdl3lztcFsAOwFpQIRE5icVtf2C4Oz+XOgedq8Fy58jVjG18z+szXxddy/zsPA2z21B8Qoj6Qh7PmeAKt69y89puSpHtpsf5yQZFfMHn8GTwHTwjs5PqTyXOqlifwY8OdJB1pQ44aeNyqhcfNztJ25/GVtn2OaRuNh+N/wcsH/VGxn2Nkh0Zu47mEhJXI8Mr+mxoxN27wYeteqBGVon+OfpbdRT917KQwALFGQSv38cwYrwjoKQqe45mb7m9iHZm+UQbs/pRNj3XTn8qrt1hXDKJFtGSBdQpSXak/3T0rxy2itTZmtqk+ljsxxIxG6D6WKzHkOCZV9VZUU7ks1ycI5EoNSATCb7e0er9c1JdoDYryChYzvGE14/oeDSwa7j2680lMDZRIDExm0N6hONxB1+77cT+n+a49PpvwHJ+rA3QvD58Xn/f4inx/tM8OccFOAdPzvyqtRnw28i4+K/b747PZlyHKwGzo747POK4Zgc0XxzUDKX12a0wvgh0x3Yi7mF7ajJhuxBrT+Qy2pQ0OjyYi4CY8GnkXHo28C49G3oXHhlyGx4bM8IiTZzPWbcXO2qQDAjAHoUTEwBos74mIEQvzoETECMw32oclPrfp9fgcwXUtKKTH56yKzxaDK/+G42o911nxdNx/wPGaOV6aupa/3dQjOdM+u6hOMQSsqqMIWVUXFwSrzi4IChUoHbOrr6F0zD772gSePAwQ5Ffap8UQWofdEIpN7BxuAwVTyP9pDtfujsMt//0crv2dYdcK0r/H4WVeNxzekCsOL4IdHF6bXHN4aTM4vLRZOfwcwK0czhFww+F16GsOb8glhzfkksMbcsnhDcEcTpFUFg4XCLjh8CbISw5vyCWHNwRxeF44vE2vcXggi+u2x7rryvicfjEyXJeS/7TrSn6bfuV/oTxym35p8m+6rrxNv+Rd+lUECyWV2/SrtIGSypZ+kbMIwRfXlQEBd9UJflud4LfVCX5bneC31Qm+ui6xSCrYdWVEwI3rytv0S96mX3JNvwJdyyN8ui5bo+5Mv5jStPpuS8HErHTn4bs8nJXutX4dj1kHKb98dVJ7ljvK+5cGbjR0fCtWnj3qfFy4d4Siwei5rYuPb0pL7MZfk+3VTqZM2irbamyjxBDGPopibjrQrIgQPDgZXNEc51siDA/ShNbMf63T/xm8RkONso1eihSoWCBxLaL06PaKPB+dRfk8bwWcGti75m3yPoqFKftPlA7fpeMW6fjXpSM26fh93hGkIz5POpZsoxjQQXCfKB25SceIRTrudenwTTphnzd0FvnnSUfHbRRLYRT2SaN8ZypXhzY/vjRPLvePL803xpXJ856Hq6I1uBfmVWxXf9X/aq9iMGZDKvUOYi5/M4SU+VRkPKMnEvozeA8UplheaUxxXJk873m4KlOEe2FexXYF+6dKZTRcm0ghvYa0quscr8THMV6/quONex6u6njjXphXsV3Bruwwwx+jdXm9L+1erd5V2BgE9+nE3B8Uc6Jy2ZpVYnZZp9Ik5jqiAkJ6b4733jgg9UXGNPg5DY3g8SDrD9LZJcfbJGUap0rdmIbtklQOIb03O6ZB5jhpToOc01AIHg/2aag0uyQotSgOI7wtkbUuamdcjZAT84h3kPfwORKzGdRE20EXF8EhkZGjMmHY8aes6ztXUt4U47UjvsEBQRJ1VORElE2TqAi2XWE8RpDEhbe4tynxyifF07cN9girfZ7uxfOcROziUlnfiCvqmQOkeZZCsXcIqPZu9t4hFmn/wd6/M01GbtzeYrBZaY0UMVPs1mSwSWmCNKLM9MQKYE/MCiHIE5WZbl17xV6TJUI2HdaFnyw6lFOHDHSY36/D2qPfT0BM3Tkk3V829THrbYypQfEpY4CzdCXNMJA3yp+HaRqyaCkiZOHLbCfiNzUFhCxq0qGykClqMlNNfKhJkMuzLHI/uqLOG+nYTrvE/bSLe8tpF6bbEQdxcdqlxqiuB21mslh34lA6JJd0CM8QNgD1XbKtmxVeHX+Rc5FwDvzC8Re3H3/Rbzr+0hTSdVWnghaxBZETsfj4C9NJo2fQIpYZ4hZkLmKZdmOLsPXWDr2MNnM5W/o1aES0nC39hgWpK/ixnORog2706LqpEfnECHBORtBfYQRN+C0jxE9iBN12Iq8ZQX4OI5ysXV+oE0IdFhNCf9Um8IogQtBEIgQTgiZ0InwhBE0EQjAhcGLTU+yVoCWGtXRxssHYebJh3GjejY44GHdxxIElsQdOk8Z2uwLaTcy8vr3Pd69Tx4urxyTINrCFU3WCPg18tc8/uvVv8u4m3S74OjKq9nAS6EQM3vDnRI8N/4a0Df/2NKr7sDS9ubcxs82sALE0M+3eZpbsgHL65vl4rvtsYjUTs8X+3bQGBdbAL8OD2rle7/HC7PHi5WjwnMX1txUXlZzCkc/mojVejb+axSX3VAkZNmEVf+7dmMUY1X7S8iPWyerD6iIY2ZYG15lEJ6d12sU61R579H6G5932myejVBU8JZ4AYOKqFjQQtsazLuf5TFtY1XtjYZXmad421rmwKk7kwNhdBodgS+ArbezSxsw2ZwhETuPyCIG9zRkCY6synm3UbHOePBtxeYS8jrpOpoo3U6Io5GlwH4Hrp3txcy1qnqYfW1H4qqATjAGTYHoGIPpLpZZoQM91PFwuiTIj5Kn0MYHTAoYQZmeofBHV0tksQTTJ+SfJGZCcfEFyt+XfyPNNkSoY/Y9ILq+SQ2LIuNA03nU+cxaasEzz4lVYcnmTnKdPAdyC5BSm7DAoO8D+2UnMpnEXLsE3pg4Ol94LQcmdiI0Y4VObN8Xt1wiRrYTI9+W7gWOAUnwoXOvrcO0n33GNv0/gJELWldrx3QBFME7a03wgg524XsphiHnGcV1oc36zkAxBI6BvFnSYXya4+VzjG2ovFt1woFXoX0ixS493i24v4fiCjeEjKXab9XWK7YX/lDHQoru9Ucux27jIqca7sh8DOXPsMUNAUI5d/rYTWRbd5e+AEJxjU5uec2w4kSjMB+pbped8U9/ykiFR/lJ9q7wIualveUk/2HsVWAYVpVHLbyM+FxqhDaiRXBa4OoC1mBJCrgpcvVesxBQRsiyUaKHLqkSKlBhAifa11Di8OzXW5zHzs7biqWjb7Vc5Yj253nUiCANKlOkuR7TvzxHDOqNW9EDsSQNs1NdJ4v14IRVC0H48J4kuCMroklyQcz9emLW3mb1xGlcEcrZiyzo9l+AjqM+9owRPL2pV4HMZvpjSJcX4hBI8ssc66mUJviGY1rQlGEHWrZPFvWGKqg/t4oGzl42UZ/71St5FTVsAiIu8y8PWKdWS/7JA4LXrOFggBopiDUH5FhJIe+Yi3+qPTBkWeRhRz6JS9dAPelZK4SyEWM9CyN3PX1gTD7d++mQAGMEtjADWiL4FW89TjI++xg1xoJgR5H6g4pyWIQckguOGPN6eEY4W7U3WBcwLZtFkoC94KwjyZBZcroVWufPWS4vdcPfNh9n5yyP+qjqXd47t0wcttwog71lPGAJg8lkAmiwCuFypnwJY3sLdBW1vP+Et5KZGyMgDd+9Rozlei0fheHsSfxGPqiR2JoK1s/fx45IQ/o7n5idDH+U5WampWGVPjqpm4UrNK7+w4Nw0aAhmQQN74f2ZnQVhqJ5j1aHgSs0rv8QZw+PsUOF1fjESCMPVXNoXQr2fftBtbnk0GH3rTeHUGiBzBUXhsDggc91E4RMhQOa6icJHvIDMb70LwhekbmeE/lJizkC4JfM3ioxU1IxvIYeYeoAdb3b2m5dPOeHELCDnp5yGhzmi/D/aczSc###4500:XlxV32DM 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117ceNq9W8mSJCcM/Rl/ALmwVYZ/xRFsGeGL+9DHifl3swqJTLqqPTU+eDpdIhEIvSchyEdg6/EX19vx83NRXD3YY/3xZ3ySD6f8EZ92/uCnKuKAxJyb+GL8J0qk1USik0QXiSMSlSSqSFYikUkii4QTiUgSUSSMSHiS8OPnT7uoIB/Lg6f/fvzjYt+bD+z4w+nzse/++CP4KDnl8RHnGvs4/uZalr/Ol7+e579B57+xxzMpS//DfuR+gtyOf5yRD6ts7FCLx6KMjDoMe2yrYFWJW3GnrPw9k2WPj2htrCROSQcwXdQXfz/+Sv/8/AynRYLYUZyr5/kVv2OJ81ES/0kr5BSWnMnaOts0mQepgUXPlmPRajbO1IHllma50C33N8/uEaeroymWA0z5wU01qdF3Jv3goZo6z/X4ELKYWkhBTa59mvOGTb4Wk7voAMXkkq/V5Jtr62oVGZ0JLo4u+m/Ryk22dZqpmq1otMV7VjRp0aMW37Ssb9RiBi1KNi3LG7XYQUvsvGphb8OAsltzzmi74rYm04fyHkmK25rCVR7gEVeVsJgRVZLcqbJYbNNYzBskxoxUoMhblxGFVW19MvBkMVDj8PtQbBl+9OyCOoYkeZDR98s7gMfYb5ly0AD7NogE+2qV+mTgyRJSUD6gDos9gux0AT0633qsTwaeLCKTtPguru5j2R+RWSVQw9qo4cSkuu4VaxwoQkQQxh8E4Yz4g+wtzNFwm/5qBNfawKYG2vUuVP4hUNpxXYfKOlzXIc/8Q2cuteYfdG8R8g/mnrr8SSisRweTBiHvqGoXF2Rs1hGq4p2qNLVS5i5sJRNX8UsrmaA626VlM34kUVdHtqjryISdkWg2fiFP3L2XU3oT7yMeP5KoAqrer1qkaJNg39KScxCiZW+mMlctkWGrFjmsGR/XbDsGY4qjLV79Yc2L5mAkyzgS0Uair4umBFk0SXzhbhX16E7XZVXTeMLfnO3siYuiG1U69UCxXl0zoNa40p4HKvSKEqADRvXqhgChn0J2HgjQK5pDeeDsuCY1fHgUPhZQU2LVn9mN4lKWUWgkLqPwZ5GkUWw/SvOUHhcNJVt2JdxlJuttFLRJ8cGVAZiTtJHQJmXQTg55YG6TMmhXIpKD3DotAA6o7mySSCBt3hLmbTwSl+Rfh/LiRiQ56SzG6Ol6ZMvU5V8xUBRJQBK8lUDBNEv6VgJlCVnSAzcKplnStxI92BdJ30ootxBJ20p8yupH0WIGTGtyQBRxpjEg2kfEgoeAuNWAuPpnATEMAVEMVN8ipBoCYEdvEP4YQmSOoRqFs8w0ureQe/7B9h84RNX0t2L3ElT5Nbjyp8GVDcG1xmMzht/bDcJHJY5IIL6/kHWcof+QZgxxuNjzLg4rLStv8WVrxMnkLA7bMQ7rkdPdSK1qpFZzDJFZksjMNRvHWiOz3Nv+g0vg2LQLezFnkMc0DIw5Ax6Q8G4Sy3ehrwMSy3+K5cX35E1sU/a8aNm2/TLtZxnSJejppytjD2oIP4l+uzDvM4QcM7O4icpaRLgxhGTEEHo0gCHzhdl8nmypESKtbwmtaYJ4z8Jlq8ukQRVqLkTPhUaSQs1nJnrhHJEkaj49BOqmsITnpBCHZ+HariwPBYXnOD38dg7K+W0UlIVvYSs5UwlOuU0dszZIXMbsTJE4IumxVkDYKpIeYbmQRNLjKtcLkfS4KhwjkhROXJ34ChN3JOIKqOMkYmiTcjApzpEYR1yuBZGkSeliJ3sSSY/FXDkiSZPSNkqcpII0J21KZ5ZI0py0LhYCe0dcosBuw4kEKK7bEIgAwrr1ggggqjvpiQCCupNUR4/prhs0S3p50MZkbHmEiL0AcXtvcTvcxm0xxu1awyKkSvaxhV25Xuvf2vDL2CzH2LyPO94SrEmQTpTKR+KuTKKVuvKV3mcbF/H11MZtSpnUfhdt/VXvpsVlb/nSZqQkIXeBUil2VWPly4HSzDfXl6B+Hdmn9UCOcYjF8bUqMF+QBKMVEU2WILTClqVIOlqFFUQCaI0STSQYro5IAK5xLws4VhitGPo872DiG2vpq21WkqRsVtLLOB8XwNuljYI2PTPHFMJJZo6ZimMUy7p3ycTReqz5t7Ep/96iAy474Jg3HJ+kVv1FIaom0beFKJKI31eket0bIO5HAAdSsvrgbkdZNcmmb2tXNKuuafZtyQpn1eMJhjBulhu7Gxht/o0wcsdLxaq0pAOh1DqPdOFZ4vU84cpg2W555JrWbSLMEi75dfrIHZtkuHJfr3rWdWZoNzf0s73Hl0P8rIbOaUj0CoLRzRBJxygX9J0eaYVdiAR2zyX3LAJ7f5yVBDgz5JAgJTMWenJ7GfOJJDitQ8zp2JDWOSLpaZ1wtLfbtM4xnNY5aYgAsjobINOILkbiwOaQhMQBqKAUCc7aGDYaOssoCG52rimisZAiOkaWoZdRevJYJI22o7P6JZ33icf6EMChonLoxm5zITkWJG5yIHfNgexiMhHuN3mKAAYySkOespI85baeOrj9TvITk5Otu/wkRqKLvk2vz/ITfZOffGYTFusmhbiw5RcOkkBCqguuhsskKSE1vY1DqmWBtFHQpsM1pmRIA4KrrKXHGjjLezVwxpUsS97PcWRb8gWHzeEwvBRiWv2ln9z2ELNuky2tCsCwDsovzlwY9rYukT3v7thRL+ul11Vs/6UYjagqqsOb46IeJP3Yzm0nCLYGx9gE4CiRGG+ded/9rtt169xUkQ3zKrAEH8z5RV0QrNpyrhjBUE/rOwyVgXr2HYbKoQRX3MyBVpyzCmU7Fi9UqNDy7gpls8+gLMZUgW4xjBnPZKBI4rYrhKWbnYTYUY88XgR3K56noeDSiN8AetYXcEfzFFBK9A5a38WdrRiT3qmQNmuF9OkG2Oc2EtokcJ82g9tUcEeHatICbs/4xRt084btmTfY0Rvca96QU979zhugpvcSsfOnB2UDw6tRMbiHZS8x/OxcbOINDAhd0UKZX3YgYuoNLsCaa9+oXpGSGaF68AvliV8YL5EG4g2WeIPy4A3uNBdvMM0b9mfeoMEbXnMCN3WC8Duiu7KztTf8fdE9mbAtuR2WfIMFcXTJc8DcqqQtuZ0uuYMlt3TJnUUayJI7uuS2E8CyXJbctiXn04RuOGkK85MmnNDljPM2ofOv4f4Z3PmQ0JlpQud+Ce5mQv4L2N/QzG4DIsjbFJzZ+baudTNS3p5kdnVb0trgzG5DGkhm52lmZxD5h8vau7b24tupgB7J396nAmGGe++/g/tLKrA98wY5JX/9HW9QL3oDC+ANckgFYK1sGMjfQDDveb6cMYHteb6kTAB3x0obxASBMIGWyBvcxRt88wb5bGs3FsGulHC/x7N2SgnmO96wfjcV0PuUG+RvSQUceMM+cENfKztwg4KVtuAN+4wbrAVv2Ck3wPW+0gZxw0m5YQdvYGHJF3v3hwVvCM0b1PxK9Pvu87LLJdVW3eOyusbpf/VUlV3uqLZDbN6uir1DyTk5IObt6vAblFxunLdtL283h39VSd31ptugDC60snqh9c88zfpEb6MvTLZclLWr5fWSKwsLkuBLrkyCJPZ7e8mVwYVWVi+01sblabj5zoAT80DRITIzeFrlEJnVC621x/I03JhncJLJ2t3devWY+RNJ8Lkt4xtIDLllz+BSMoNLuPWWPQv8AsazgVH/L2A8lxkY243xd7jwOgUje5+SbQZGdb5PyawGxVV4Pxjj4jTgrfC0wRMtUDEFvnnuAxg5khAwKg2SbQLGOIgGvBWeNnjaBzDuqMMJGFOPFXgrPG3wtFMwKgBWao3BGLCEgBGuCWRdGIxQKM3GJWD0fgTj2T4W2sz/A0Y+A6Py73NhMQOjcu+LjG4KRvs+JX4KRvMbwMgBeAIio4MnepWKwWdxSULACF+v5HcwGOFLu9TvBIwcgCcgMjp4otermHeowxkYOQBPQGR08ESvXDENsSy1JmCUSELAqDv78AGMAkkGMIbxy72zfX+22f/y5R7Ll43uwaXf6i3F4OH+oDMJyBoZ/ArNQnYsIRlFwGqQ3Vbp1mgzFTd7CuzWPs7hpNJHLh8Mdw7W4UpvvYTwxeWDesfX4O9j4mjynbT95lMK7ioNrDIRQv2UQpNd4M0lT3FcK8V98xf18ckHE9yZi74vjgnM01u9t7vBbP68Mnko6Ng6SjaQiLobzN8ArLJF5/wOOrZeFVNEAsfWqzR1d5h7y4cDtQ0cYMd+BdKIDrBjv5pI4ARb1s8cyjX32mPeN27MXKoIZ7vkzvnvqSmtgatZTUnWvc8aVvX2mtIatmVWU9rPi+Jfrill65YVSZpRTWlj7YJCNgaqKW1M1SpCluQqQn4b1ZTWAH5S2ihoAzWlNUiLNOCaUv2qpdSU6nvZG+I7iZ5NtJABb2hXJ7n4fblS1Hw5Y2o0vkp5dYnvfJKU5nW9muBb7+oNvZ+jO8vWu/713s1YhW/p0NrqKq/1/i/U40SY###4564:XlxV32DM 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10f4eNrFW0mSHCsSvcw/QADBlGm9/6eQGaNZb74WWsr67o0zhTsZSFXdVaWFKkP5IoCA93yCPB7Pf8soH0f5VAeDz+/BxPr/FDN8/sdzffpy5cq/4+dfweZHkvn5T3D64dTzr2TVg2vGnn8FdzwE17x8F9lDelcal61xKVX/1P3T9E/bP137/M1gfjDBAeE//8W1MY9y3/ObtLog3DCJkPJkQfgJiBYnQkpfBSl/KnIQxAJiK8IDQQwgpiGaIBoQ3RBOEAWIglHzNEdQJrONOkE/KcPcnuORKJ/lSvlxdbarb/AHOjAW3V0mpd/dr8529U2GWO+OGnXaJiT0CZEIaRMS+oQIgsCEhD4hmSAwIaFPiCcITEjoE6IIAhMS6oSIY06IGhPiWj9ZI6SN2rZ+BEbaqG1qCCcIjNq2OeCJIDBqGxpiCQKjtr4hgiAwaguzo6OpQFnVujp1kWUFbAesHQvYAdeBMNcTgKIqmfyDPcr/H+HnP8Hzh0hHkQ7o61S+ayjroZWiLvtImj2f36UVVRzSiSYa10UUIhbRd5m62FLFvyvdxaWbGJOt//dcJWhIIIEXEVeBJ3N0hZ/q6AoXhV1d4YaMzqXwvCTbJQ1vmqFpiZsXrfnoY29eej4MCHRUmw8cv9PRPnM1HN/LXOF3qL2cay9x9BI+sBe59GL06MV/YC9q6cWy0Yv7oF5+lBaGNmDuyn1TgzIZhAAvCyIaoiYiOmIb4odhBjqBbts90G59UCIY21OV4UE5mrTy2bvtV3JeqXr1Df5Ai+EaimrDL8xufXmE1EEW7rdn+ERkf+Vqhxk3Bo2iTF4fxbiS80rVq2GSm7hGi21CUjV+KgbcYoijxX4l55WqV81sg78t+mXF35Z/3TI4roZlCMMyqBvB5+5VczcIuXvV6mTgM/TP/lxO2CCAp7eLp1eme3rz5Z6ep2nUy7Cqi+jrq6NESHMR2SyeviDNReS0ePqKgIvIcfH0FQFO5LB4+oqAi8h+8fQVAReR3fTnE3jx3QNBflpH331Ers6jNth8hDlSYQErDCh/Ohd0SoML8eLC9xLq9PmV01ucxR73BelfpOdYmf6Ff1IHc8bny1oVh8PvHcz/zTcLwIn4dvbIUkY2CGf8tHPnIJwlL+pSoi/q8kFf1KVYXVMYIa0Ni4GVx+j4uOk4EKZfzWZO58/l82b+OrehX8M3AtPn14fSbHK1DAsLzBwZIRuBFWQjsIrcCqwitwKryK3AKnInMADuBVYQEgiH4c5g3UlmEOYzhYqFH+DOeEWmD4FncGYAosQIygwcIKK3Bq8z7kE5QgqoR5QjlPzlIAi8WQ8iwwg73WyxxaORWI46U81y6BpdYh/iDz/sRsJ2I3S7ETq9QqdX6PQKnV5hBJnuzhaMILP0LPMmW7RfT3Ge58qXYb3kXQPY0KgghEYJP0PzqRO3RvKpgyA4nwoEwfmUJgjOpzhBZj6lYyJ5RkUrE0q+/BJNeD2YkLce5B2rYPUdIzyPaY0mhpFlUXcqRCe/hgrXgsOw8IKnmaQCghZcHO5ACKo11Em9EGxRYsTP4FpDDGQEyKLEoAhyWZQYaGuXHSnpBkGmHdEx4yS1oT2cKBaGUsFw06mgj08NLI3Y+T3xB/ze5Y8E9XuXCTZi6/fE1u+Jrd8TW78ntn5P7Pye2Po9QQLLdFD3IKZRAGazR5n1h5rFBzGYwK7iA1p5P2NEU8PKuuT9C/cca9+/sM9Jgu9KHo0E6XRLtGdSI4FSo5CYKiErC+xkgV5iObUEXekKuvoXgkR7qVIHd2y7IVKneOlYXB2v9Q279mOer1EethvQM6KROMIoLcFk1HijTE9FtO+xAyBAo/Y0JlSa8UW7x8x7LmollVAPiFo6scGGNJ9z1S5EnapdkA8/2XAONnBcirLXGhfFQAmK35ei3luCitouS6RtW6IgR10lajUthBpLdLylnhJNXRDcunv+HbxGXbSGgyaks4RjiFJRr1we1aagLBrv3xKiHlfEkmKc6QTH9Zrfj16HVTdj4Ip9eF9plQobk5Q+tK8fnNcqNBRIYPVbkQfmdVyFeZVI4afNR3V9BcGFn6gzQnDhp61XQ8Km8AOjaEUeuHtchXmVSOEn6ohaRIUfZc4JOFJWi9ojBJfVOkHHIDIoG74DC1EftAjuD/KGDLnD7VfluyxloXdRdXgIVGCWQ9UC2/ib0oFaSwfKLaUDlZbSgfLUOiYVny81hFG8vqLG7q6nJQgWpkJhZXVjHdnwEsHkwTnPiGDl6hSumkDiz9/5EbHad0lEH/yL6PkYmpxDS9OP6J0fMWs/7nlXLYAVXPoTQ4zudSreKb9LRtAPEliXxEAw6YM/MVK53XbfgsfP4MJw1MdEHImVgx9RNCw6zr5j9SeiI80bwtM4am6zc91j5j1X/By8QD3g+Dl4RZArD7/E1pArD+8FyZ6Ht76qBw0HZNu2eBg7pTYqtvq8lZpedWNW7d0K6RIjytzR/lB+jlS9R2LyOXL2/kVRQckEDFs3SzqTjR+pmRFh7vgIwmS9MvlXIZKjY3fFRmKOm1oRI85NjZHYm5HIN2sqrB171PEPWLK2ymaWuGoyLw6VEYKS+RKjMYLMZL4ggiAzmQ+HmwDD5C/dJISgRLE0dhBkUr4gnCCT6AWRBBlEr7F+qn7gRH5gFAC0fDs5F06GO+N+ly3YNVsIa7bgb7MF6VfjN4J2Ld+TLYj7N1gjulQzvDvjriR/U5KwNG9vbXqS2yRoloDf+VrEm22dV6o7+7dJkGTvSYL8W5zXj0q7nogIQZOgyGZ6tCRBxo0ER84kSNCsOvmD3GPmPSgJmrFZu2cmQWVUeY7qpHqMfD7jsTMqo5qpmfRzVCdxRig1k36O6iTOKM1Yrd0znZFOAjuW9lwt8PZjIyNnE2J4HMHPtcBbWhmqVp9Z1kssb8p6/DB/rqwHw7ov6wFCynoRI6Ssd+LW7st6tZ/bsl5D7sp6Dbkr6zXkrqzXkKus1/fPe1mvoa2sx619qfDOkyT8M6nAj12FNw+TwiBP/FomwKgwE/gREIKYwHhMCMGHyWBOLwQzgc1At/aDmMBmcNyQiwnMHwS5mMAcGTViAnOKIIgJCjOhoZ0JZVLWAu8wCkp8ZoGXVeCuwBu+nAllWYcph2HhAi83ESG4wHstKyC4wHsta0MuV3Qta0MuB3Qta0OuAu+1rA25KfBW4Ja/gJACr8YF3tZgZULWbjUJLA8inJ9oEpirMfKdSRCyH/Zi7vBfbBPqsNCcMmc0QrBNiMNvVATZhDxKSBVAJoE5wXA3l0lgjkeCTJNQEEuQaRIKchJkmgTmWCYIMgn4YGJHGxGMbCdI+HWCxIlRBlLy46jw4TvJRSl8RyX91VQCYofNvrYYldGvIzaL48RrHdfLxrYAQLXzEe2WV/KPe+rh4XoPkgHw5mofpceF7CdCUHpciJsIMtPjgjiCzPS4IJIgc6+7IAdBrrPDkU3tKk4UqjwCNgpVfKdQxXcKVXynUMV3ClWcKtQShSo+TggnfEK4v2uTrjxfpFsc7ZCu+kjp2o7bjtuBd/dvu/u3Xao2/erkcRFL3eq7la7SXy/d1x8w6DEa82d8UhUfbNA1gdJz/lig5Z4uUHq6n8Vj6uMkJ+iBNxeADtBj6Z7kAD2W7kkO0GPpnuQAPZbuSQ7QY+me5AA9C3nqo7wYlq4UCNhI93Q76Z5uJ93T7aQ7t0dfpFsRJF1PpFvRJt2ATv33d+1ed83IDLNDuPoT4/DCnGMThwtr/oCXmrFUGRcKxLOxCEBxOF7uuqE143C83HOrK8dluc2B43C83ObAcThebnPcxuENuI8ZC0LicHwOrzfYiWDWKk2ccbj5VCLovCWC/gNEuNx8pkQwCNgQQecdEXTeEUHnHRF03hFB5w0RdN4mD5kSIREi6HwlZOLFmQcxc3P7eSnZB1BJ7ao8woivd+bK7Yhtzi8nNnKCylFeXU5QuVdetejbjgBAuW2EbkcAoBwNANj02crSRJUjYBcG220YbLdhsN2GwXYbBpPaVRl0RrOCDYEWCKCG4CQTiQ1BIgg2BI4g0xDolGkcboczzweRrnKzqqYUHKRg8hEf7NrfnQcn9e0WmlkPSrz5XMRbj1jhXd76c4dV942k6xmsl623seX2i98H1m0ZvFuseuob568lFHf3h7Pe/KM3pdR6SOtAh7RqV787pEW3vFSd29vfNeo8fkaX596yM7/e8lq38to83f6uMdrXaaHHM94+LXX3Sd6cjIshf+Dk21+dkKtdve+EnNJ693vMaG5m5/gfZ2f9IY8ZaxDSB86OX2anuBo8O+n9s2N2vyOdZ+M/Ynbi2stYA/gR738B0xE5sw==###4668:XlxV32DM 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1224eNq1W8mu3LgO/Zl8gC1bUxV6318RQIMF9KZ7kWWQf3+iBoqU7Vv3JvXQSOLWsTVQEs+RyDqseggl3PNbcMtjE1o9vx1xfUi/PP+RIT6WR/43LvXfZODf/45FlP8/rIR/f3mhFLwJpcvPb8Gmx2GO59/B6+e/welHDLE3EHRvQOcKpc2fZMQ+3CGfz/+CCb1GDZAkNdq1VRahj1O/1dKqDeLz/f4h1Oah3z//yu2ZR37v+V0eNiNHAsACYNwjV/SEV1R/Mh7LNJYFLDNYFrHMlqfvMsrSsJKk4dwxaFgXJB605Wy51nJ9gpZbmcaygGUGyyKW2fL0Hf4qLeOQ4bs85L9KWTZ9gc1G4NqxmOqHriP59Tx1UKWtVlQ4GN2s6CqiNoLU2txWEYvteOyGHd1YCdw+FPVDjd2wrRu2jWzBxlT7xtbGLNS2AWJFbgJtWroq9vo1DgLs3jqksEM6EbhV3jq0Y4dU65Cso0+KTGVeda3Z9gQDa2UaywKWGSyLWGbL03f4q9gd+wSTDIPJ1dc+GYKU3irdFl7EcUQcZhx23wlcP5RL/TDgMGMbZqp2l9iNbF0pwab5r18/dKqTmP/XPTvqnr/y9pYhPNbHah7uscaf/wYvHtux2GfZ6rs2bTen4iR0dxKH8k8oMKPgeDI3cihXClzZ8HmG2r9bdQR2vJjbgAI3CnQp8KNgLwVhFKhSEEeBLAVHbcS1xlxrLMjxYoIXg8ICs5SCMTKzloIxMiNKweiwKY0F0uEydvR1srZ+aOrjsqVjnBypSt0ry+ZIpRd/SADSw6A30opeaitHmcypFb8wFtCDBbbnRAuC0YL0+zQaLXo7+tTOZnA0ZmrH8IXkDj83rMlCyi6jd6C4Z9aBrZtzPw/0t3gJWklzK7a3sr1x0uTciuvGVOdWrGKTJoepyr6QinE5N7eYrbtN0wofa9qT0HuyX0yrZNMq51kkPXFzT/Q88Xbumrme+GOZjRX7lIj3TbzXkyHyEm6GOO/WbV/vDGFmQ9jZEO7lDghoiGE7ZpF1sohBvbe+ySJAotCKyuwCnqwSIWzC/pT6U56f/rRSmlyFMaSGqseghv6U+lOuoT+tTK3V3gLDlbqZWgu07qK4St3tKfUnqLs9rUyPydiFEMx91SblnWRq057AQJ/5Q1cRw5Chx4BcKQKEHFptkiEaEF2RhSEKkKIlKqMMRALSzOLQLAtTdzKOvikc1IKDilglWKiIEHBGTYRUXuwwFX+VQref9XUYc22BysDKmb3tOnrb6t3Z1xq/BjtYX97xib2j8B2wiK2WP3gvJL4DtrFtDjYcw8HEqIwK+7d328CS6bbBKYoRbbMN26wEpjpU+gN7taFtdqZI894jbROplsck2dcavwbbSF3knKByrqKuAFsD7IGmqDovZj21Pnb4gyrPdZVnh8ojEk1TPTN0TPAwrfsF8QZpm7cJJqG3EdTbvPQy0fZtBu3Q6Yo6UOTkVzpC/UXwO0XKKcPqKnxzn/J/e/bxq0aT+G6SQE0i9trr4dcPFbhf7wKYSOQ4S2T/gUTm+tYwOdtlrJoVZ5uh4n+6Ru3S9EKRFi1zpUzLjOpLLbecuc6HO66zM9f5l1xnPqn2vJllbdcl+5n0t2xq2sUTt541hbjVFMv7NMUxa2bTJas/3igm53OG2bupLoSx4fdAapaKbY3JtsbKVHHFGObmulDat08dBE61X07QdidxfHqzxNkLjwoUMTs+bRdup7/dBcuOTxuXLhE9PtRzki5YTxMnOz5tk0wZOiQgo2+DtVByQBWNtfBaQcadwPRWSYbBtxFZK3A9E1f2jsF3iLLxjr2j8R2icSJycnmHaJyI6gdmgCkZ1DjZF/RxCxy3NwSu8iyTYBnYwRAiQ/wwpS1V9jsoKl1sq026IXwGQijdHwwhlE7I3lIib2Q/EDCEVLN0tE3QSFk4fm8cHxyatt3lZF2Q1zz8QUILndDiRxzPmYIwQ7l9vTxke/nmbVfGmvwNswPC7m3HOk9+2iAbRZDzfxT7kHZQW2TT+d2d5FHspju+Io+8WO/kUXLNZD7rjL+lzd7YpfA4Yrw24GuxZPqAoFViuHpr3gFqN78aihDrgAlIZcQ62yK3IhDEYyilo1sn0SvCm0sweVTaULpaCy5fmdWiOG78eyhSDKwWhUY7rb9FwFGkm1hG0P5NrcCsdC8Jo6rcAS3TG+O496taQMiNcbN1R+iNcdwPRI5zjKQ3WOmnVDvmPVcryMeUfqJK9OtCOuVr3FNlBSwn15LaCjDL77iWKMKNawn6ePNc1GGH6x0CAN0h1R6IEM8S90CRsXeKeUgz1LPIBOcMnz2C75Zbl245eW+5ofudvZbzn91bufZbJ27fJ24LcimhvXljK/ZWB+o3tuLuYp5evZn2ZKGjHneCt/uTxSfHfEdVYZXGHIs2yUQR6juICEqW+o5Gsb0XTbsmg08WnxzXs0ciNZ71LNZYVWwy+GTxyXHiHpInGRa9lMdBEKYKh1BLmpP9EQjCyV6tM9mva9+SitJZ22q3W8uXIN5+RSip37z6Tb6b7FVkC4Iwt4psQcBIyTdjQRCBoCKZV7BOVgjrI0/NI6B1RLeOZmRP7x9ugmXtpsJ9dBPxgX3TMtm3n5jD0cUUXCpcnphfbnNXnMl2cVKOWzzX7tQpVjZdLigWS3HFi+wXJ+O4hVP1m5Uf31m8vCPxaVaeqKEOex7Ol5Yf1C7ulvph/rB2WNy6nYFhyqvfg/H0J8HV04qrNwm+4Ie8TYIueHJahxaqT4MW+pOYZLLCenigwS99s8H81nNoqaeeQ/1i8cOlnb9hnbXzt193AtPzd1xpvfTUHVfbBBpUVE/d9Z1x6o447voOnrV1kvS4WL+rx0UvD7gBFY/wWBVu9a1vdR76t+xe8yKg37YDDcpDlOoUjEc1M/uIm1vKJm/y2onVVxSp9ZHPWGef3OPsIR2vDmBf9CB+Xad0K72QdCto8LKZzyZfeXV7157kW/kFxnLMbdneVny73bbZbo7ZLf6p3WbX28VoSPvb7ZbuOCqFt9tNzul9O7Nb+KrdxGQ3f0chaXu33cSJ23GO/Nvtpj9Ki4QGP2s3bq5wK//E/0X+QQ4bOLjGi6qfEWDz9jKHZQnLeoYbGL2XhUlEInOqwDlVHgShp4pm1p+13kp2UNbJbrcEpjlshF5XzXLY/I6I8teJoDD+xtqqn05g/L3MYVnCsp4mWvrZyvix30tHGmaMv0rsbMJRyjFKTWBK6YTsV8ko3e+IKMeOOl5qgtCjTvOZP9tgWze20Q1JYBqr9yseHNaNRej9Po4Ull8G4i1UWWMkDNsor89D68Y6urERmIbF/bogspKbc1DKeeusD7i8FqhD9q5DWHA6tUBROsaRIzwz6zu3TDvctrw3h2LbwFMV2+FgYtsxsY2a+kfpWdNV+bsaIqhCz3lLkBoiyHRfhuPgMnmFO591XPrIPiB3GVomwd31+eVky8gzhEp4Ooszc862VHO25T5nW/o521JitmWPSlOBF/ZTlmXLkFQN0PPx0Mzpl3ZOv+TJlWTeyZsl2pzGm6YEl9MYiSnJnmmMxJRoc4rnNeTrGoLK1EUcXAt3XkOY2VDXkJrztb6U5OjmFC/LUryM2W7y8rSw565J9ekQvZ77Gu5D9FMX3dTF/SZjTgvzlS6OzIqpZ/5lxqD7OFHOOT91sTsJLfxXuvg6qe9kRf0ZK/5oa7C6Fc8dDv4gAJDhcDKiLUMGmzojGQIOPoX6jWcIHBiTr9/w2iAmmVxFNEMgJpmAtYLurh0WQe102MvFOMYsACFZcxlJDEFyJJfpFcFT7rbgrxgqgqfcjHiGYEQ5I4EhI2vOmPHN1nptoZ2gEgFILDlXFhmCVJqRgyEYZd4WYpyNprhlRDAEE9syIhky0tmcG7PjWMza6Y0gNGbt9MqQEbN2eOVakRGzdjoxZMSsnZYM6TFriBLthcflw+S/kPhUJz7/gviUe0V8jRrtnIblGDWeQylXROhnIjRf/9mBfk6MKJ+nq45rhlzm3yHI6XcI7ZcKZr5JpTlejDI/jg4NBnWM9ThhhpkwHRImo9SDsfD9XYyx6oZRjel3CgZzBTcR7xhVv2TUMHOBfX6g7LyI+11ULBjxtoizMcsNbxvtf48U71Lr9NfZ0UwWuYvgBbO+zyIlTeZKJhinT0tCHJ9XMq9Vl/6ckonC3SUjmOV9hii/hVMXYsTgLww+tTdOv6x4rZPCi5Ug/G2eRHpbbN5hKhWYgkkQPB5XZEiQiKEumKTT9QAEHWFjtxyI3WA2hMMnz/MiSFKFu8iLwBprXsRuMEPC4RPPPzIeNUJe6kQM5dk0BCFiyCfHANRCPlkGjAt/hz8gqMhIrnOY81wRKoU0Q4YUivgj0DLCcR+RlYgiCL2PMKgGwckR+eQxxxAAIp+orlq4eiJ6Z5nUk2AIVU8LQ4h6IlpsYeop4s8xy5zSDA69E4ReeBiLfbOKKS5jFEGY4nIrQ1Bx5b7xb4jiwguFihDFhXknFRlZgjW9pa/Rlmq0G0w6cvjkp/Sjkf3iefoRSUzy7LLP2IVsSnoyMcax7UpOJpiVWRE8mWQ7WIb0k0n2PrsXF3Ep3VSkFSwuxdPrP4hL8ez6D+JSczD7ZVyKy6XXAaq91MgDVP8DiCVJ9w==###4060:XlxV32DM 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fc4eNrNW8lu3DgQ/Zl8ACWKWwtzn2+YQwCuQC7jQ45G/n24lqropjGG250cEqn5RLJYrOWJKp//eqtukcXzWzTyth9Wn38Lc5zfbPK3GML5zVt247uS+Ymw3YRj5w8R2I3d8jXpcn2JbK+/oxHl+svlcVy+K63s9Zs36RYVO//2Tp0w4d1pPEyj8vCiDJ8Rc7ORn+eL136MX+8OPD7vQ29qrEXv9yeRrE/i9/+1liDnucxYRni43uKsN0v0Fj6qNznpLcxrCUNv8uF6U9NceuwR84/Wm9smvemD6M1/Vm9xXssYehMP15ue5xp7xNzD9XbMeotEb+6jejsmvaVpLWYbejseqrefeS3lif31r7pbGT+/i6gasg0k22Qe4fyrtmU5GxwR3DqGVBGbBpIfz+vMiNcV0QdMFuqQ34U1rU9ASBvN8oZc88ghRm4DMTyCe8e9dQQkP97EMK2P5jCZ72KYtmZrEdJGM10MB/MIEMNdYmC4d+xiGBDDdTFE1YZMRfVm9DHi7NO2u7Kc3hagTUFbhDYNbanefS//1WVKWExqy5TZ0qu0HCFVWqlaHwc7lMcdm37AMj1DcOsoWOu4w6YffZmpa1sgC2vajmXTt11rpIBsq10B/a5sd28L0KagLUKbhrZU77Ih5sVUR9W3bLA3eQuv//osIY+bPqtLHXlbm5+k6oxmOGOUNjtj3rzqMHn3mwMZ1X7b/rvuanEw0dqjar9jbX/J6qy/s8Kxw5U4NecSmUbYkA+PU/Z9PiEXcUqROGWuOLXTOGXYkk/wR8d3sy1z8P7wufZl3toePhdfxnr24FjfAo6s/gYhJe/huNvgboc7PoUUiI8ZoSFFI4SEFA0BMI/71v+HPN2HszzjboO7He448vAyq0Jjk+ylL3k2mmqcRAhJNfoajdG84ARCSF5woJEQIGBaCJhhQzDJCw7Ukh/PXlbygqlhS29H9toth7rbZnrgcsyMwCVG4JKDRdAAdoSzNNgewEYg6w+aHriM7VfXr75fQ79GHOhehD/aby/6VfZrD3y+j+/7+L6P7/t4PuGAOQJldgBRBNiQAxypBCkORm5GNDI4+IiaqrHj5ETUHOcYTpoXCaOkMYq9qzWbDqQ1Xxl/mUYd5c7iaXossIOKqRIUeoDeySx9qaKrSnRVkdlhUlCNZBsW4kcMaQhTDZQI05OHtU8XRtg5+udw9I/PnrK9VvBXlSy4A+9GFchGMIicOVmfqF3zW24LVxvfB9ko686CjMARUzEZXoCjxI0Sqcoj5W5EhmbXpXMRJU9WSGilp6rGo9E7r6f3Lnf5mVB7A+msvSMDty2+eQmVtVL6HHVcrhCS9VgQ25CdIMXVfY1Fao8Euaiy2g1BVEFUQzhBZEFkjadxRLaysqawFvNUMAhpUps2Dz8Q0qQ2sSGMIEVqE5oEniAXs1a7IkiR2riG7AQpUhvbdG1A17bK1rRejjt+/QwJ6L9obLuh2VxqZ8FQ5yuKZiRwggDvVqlp6XtZ7EBtBVQHjDmHnKICugMeTE00hqkySd2yR+Z/PVBbHkegllegfhF7j58f9UOjaBwNnUiqw86xoMc/q54cC7pDts21xA2VNghBLpaNlSOkGWtLtipIhDRj3Y/ZWG03VmFnY6V2gI2V2AExVtuNVajZWG03ViGrJZhhO9USKlotge9cTJbgEliC+kpLiMwsLGFLI/YGK55tCkUsbApxlwhBpsAZvFUWBJlCVeqFYFMIAffBphA8kQCZQvCSIJcpBE9Hu0whODoaMgWLTaGhPSjEN6ag2TAF/aVBQaxMwZjfGBSEWQUFYWhQSDtCSFCIAiGLoCDMKigIswoKwqyCgjCroCAmS3AkKAhsCX62hN0OSzCYx9OdfOkvcfllrms9da2nTtdTp+up90sRnzfkmSWbLEHqbgn82ZaQtxU2XLK2rf21sSjoQtq2ppmYZKRta5qJSUXKtqaZmFTkOoRC21qRsq1pJiYVKduaLLXfAty334wg+1XJd0tIlUHUAXt62PIb3S3/ly/7oArZgLst2K+LCp+3pcjsMsGIJycYt4fKcu9Z9haenu5y5hjmU+TChhXgZLohk2HxmlJsf32pj7xJluOZ9pJSnqFpc4PUZKe0KRGySpt2mTbtMm3aZdq0y7RJGBRnJiC1oFhQXeRCcCwIgSr5igXBB4JcsSB4TRCIBSoFmrgt0PyIvbd1a3Fc5+w+e69RfHiv+5O9Vwm/4gTy+ScYKiycV+lnpyX8jq3ClBQ4Qe74blFrP3pQ4U56GM/0AwYVJqJz0Rk/ER2NkBXR8Uui45dExy+Jjl8SHY99d+ObRGrBeVwzrEqaxxVRJc7jO0FwHo8EQb6bKNXy3Xc1YyTzqoBezHjxXXvLl+sl3Q/f9Y/z3c8esn5F5tbLzM1/Q+ZWi7PULTyfR0SmVjwi7c/nEYgtKHw+xplLkEr1lOYPhKzSvF6meb1M83qZ5vUyzWua5qE8oOiZpHnOEULT/IYQmuYTQXCaNwS5KH/wgiCYmdHRpuh+jOV0Zqb6XX34DUcbTw+OpvpdeZqwNRPRBqPD2cx7OELw4SzmPYoczmLeo8jhLOY9ihzOYqqq8OGsZhtlRBqi6o5PRFu3BnAcbpsaxyuvfEuVPLzoBBxu/7RwqVRcBCilnk+VhF29wevf8AYPhEjY6Q1eImSR+YVdZX5hV5lf2OkN3hDkLlkTdkHWVBxkTdgVWcvPdLIm6FE13y4KE8l3Fc0sQhbfVcrc97+rVOTudxUVV99VKnL3u0pFIG9odpCvGRVtvisIVRIW+a6ajqv8sQ/PjV97cOlWLym/82tGlmp1cOkmPn8ghPJ5hZAVn3dLPu+WfN4t+bxb8nmHk7RmkrJpB5bgeGpR3N82CbVTUIKQSO2Uvmqn/Lp2qofz9mB+2yvFVPv9oip/jaj3EwX4kO5VW/XA3jsUEWT9LPhOGZaTYlGG5dM4KXdcPKQMy3H9XhlWmfBT5aJuM4syrMAGkXWrmtQPlis5uSrr9kk/XG/uvbLuMuGnypPdZhclZYFtD9fbqqzbJ/VwvcX3yrrLhJ/Um1uUxwXGHq63VVm3T/LReju298q6y4Sf1JtflPr5lB6qt59ZJ+P9oOwWLozr1lEQOcq6S1svWHMHhnFZt+Mj9ZTHca2KY9dkltTaOW4RgmvtunPXeSSI4S4xPIJxWbfjBsRwhCQ5Bn1yRMTlew6YaEFw+V6PzXUeAWLoSwyHYFy+5+CIvTxO3pb13quaa59aR1mnbXdSQpuFNgVtDto0tHlSg+lYgsV4UoPpDoYQXIPZTfu1jduXeUAtv4MqmjotKusuPKAjx0b4uGMRWRgq62z0aay/1W3WDWl3UkKbhTYFbQ7aNLR5UtXNd8Hmj6rbOM6z7Cs/qsZdLD89Pfs47SdnAQ5fslzkiAX2syD0iAUj9IjFEQQfsUiC4CMWOho+YqGj3fmqWoH79SEZQeRaM0UOG+qAnabGYgqbvOUd0EBTxxd2uxGaKghN7RvRG1rJrLr46XZOzNae058JOKgX7Q3xBM6LjjbCNaY64Qzj4rz+EkvXSUlhbe8Zz4kVi3Mute0AO9/8UcI7LLh+hVCYAe09k4txIGvjqKHlYpyVO030abPfE32WPkSfNvpzyo3qnP62QFN92uhOXIjrIl+wXA++d8n6YZ5RXZ7j0X3XBLdvNaEY0YSZFz5XEbuoF1TT+/gA4fm0jVp24Y/0kW205xyfyGbpeTtxxLosgaz7WFBFH/bPrzuaFaHy4ZOjjzwuSh6LfOTiCFk5r2zcGZqf5TiOKgjJz5EhBOXnFhTHVD3tRUiAeapxZ8ifPzjIAFUczPLgPKIYRyuqreO0NODkjmBcq+xEIshVq+yEJwjif0IT5KpVdkIQBGqVM7IRpOQB3xcFEkRNOWPNx7z2CbAoPaheX9k1Lq1ndiIS5Dp3cwFYauSUHiZgeUnAjBzUmDyC8QmOE4og1wmOE5YgF3FELCwJcoLjBCcInOBgup5EV+P47rm/rThyahzh2P3P/e7p9pDE6rtl3J//3TKRiqP/ABfHMYs=###4004:XlxV32DM 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f8ceNrNW9uS3KoO/Zn9Ab4ghLsrv5IqDLhqv+x5yGMq/364yhI2SebMZCYPaTO9MBchLS1ocjwC4PM/Z/Exh/X5T9j0Y/EWnv84Oz3WBZf4nZ8fsNvnvwDwmB7pqesT69PU51aftjx9qa+nOT1fnPH57+CP9PzxLRx7LKzfvyz+gEes/kwlnUtf08ePb0tYNKsTX611UukrOB/rrJNNDS/fCxK7i4jdErIsC0PiACKymdSu9xyJQ05IyIjzAtkS4gtiBGIS4goiW8OE7BnZnUB0QmwZ9YlAHfWGZdQzQ8qoF1VGPTGkjBpsGcEukDRq2AqiBZJGDcUGTraWRg1YRi1bS6OOHz++mamYIP5ZViuhkIGtAtvWljEBP/Y4HfOYHzb9+/6f25fHuk/R19x2PJRdq4MdOjqM89xxXuCojnVUxzqqY2W/SU9Xn/W9IxSHw+ygexxFqpBemr7n/oI2zdvNR3v7Ou0rGdWVBY8jLQtuGFIW/DD9gru64EfoF9zVBT98v+CuLvjh+gV3dcGPvV9wVxf8sBSjBFwisyEsHs1kqyscxRUccwXduQLu2FxBna7wEv29WveVq7BVXLpScgXbuQJMzRXwc4ivmM4OjWolye0zQyRd8HdGdGGHdGGHdGGHdGGHdGElXeySLuzpCiqa/jEvjyV+VGfY3NKcAf6cM7ydV8I8cqZlUh/sTGk0+4Dllgk+2rVZKkzjkhzjBNJxzJoBW3VArnKrA1KdogNSHREifqYOuhBRmiH3IZL7vg2RgtyFSEHuQqQgdyFSEAqROGpuMJEWFDJEpgVpZJ4WvEB4WjACobRgJseDtIyv5HTPiby81ohcXaLXrbZFr/6bo9cfOEwFHx+9Pk/nXqN8ZvSmcd1Hb0FuojcZtql4M1TxSCredCo+UAfYJbiVIaMEh8MEh8MEh8MEh8MEhzJ67cHMIkWdYsh99BZT3kVvQe6ityAseoNMsUjRe0gZZlju3XoZhkeLXfyTijzMfpir9Mcrcq+IEn1HvRtD7hV5Qu4VeUHuFHlB7hR5Qe4UeUFuFHkGbsVjQrginydJ5L65wmHshcct7NUXjPuLeXy2Zh3w+Kqn4kuznfaP4fE4mmXg2SscHzyab7NdoLhCHhfzq4hMArnyeDZs5vFS5fSw+DeyOpnHcx3ma7NfDXWwch4/zM4ARuOzXWeGMBqPo/UCIRqPyCYQovGIKIEQjc92PgRCNB4HjcwqjAlSgJwAI4I4aCUMSUQQBxAEQkQQESuQk8XnmbF4HV5m8XlhoVtfK6GrIYWufazxo4aumZsEiwN9t9B9ga3iW8W3htdQ3WqobjVUtxKqYLc/FPq5cBv65vj40MeLoKyHquv2CUQEo0OvmOU/gYiIbhD5+efsF0eIFjyBBwMGPIF6xBOoRzyBesQTqEc8gVryxEwjAHGGl6LxBCRPLAwRPLFOAuE84QRCPBERIxBO7KtAOmJXbTaF2BFbCdwNxbfaleIRWwmcJHtmd+RH74fh685O3jlvIvKTd86biPzknfMmIj9554kOkZ+8m3kVjIqaGFWxk+r6WgFAUC24k2r7Y8t9bnrZhD94bBkH4UdEh+ajg5mUZx7W1WkaIhxkXhjCo1xrBgyiHPwoysGPohz8KMrBj6IcvDi1nLVwHWBy+XpoiTY0Vzi4K7jqCq6ugqur4NpS11VwLUfaOxf4F8L2Xjnz4kpHy1LwCTkzjLLUpj88S3nGSUHKP2TAQP5FZCD/MnIr/zLCaR0EcqvXM0K0HgdNhI8ttMImlTx6IvwwUvLoieYDj93DaNZ+mbu75OEWoe6Sh1uEuksebhHqLnm4Rai75OEWoa5EKNYIdWVynjjcCA7PJiuhi/MldHdsv0Nmnfb37nQ1DuXu/PGhq0cnlqtZPnOnq80ocrQZ7HQ1ySBtRvGhSfxo0+U2UmkapYKdGDDIbRpHuU3jKLdpHOU2jaPcprFTsJ5ZhVMdzgwYUJ02I6rTZkR1Wp5XzptIrvqUX1aErjan/JpvfmyAFrrz37vTTQJuGLq4fsLe0Ix2qqg+R07mEINzNzIMQzj3IF0YTqcqNGIPomcGDPYgYEZ7EDCjPQiY0R4EDN+DcAoCI3e/07nDk9yhJwaMdPGQO2DIHTDkDhhyB6DUxbvUxWfoOrGlAgrdRZl0+Sduudx5ShXmdsBs6YAZm0NF19tiRtmfzbPqF+HZXKx+4Z7kazFsl/pcWXiWipHcKE5fwK5MhdcKx7PJ8fJFzGJNl9cv5icT6C2rFz9+gYAse9cXtmdL4/WLOJ8XjSUiwlYvpQDknTnPpFWSB7pHoPRM4dh+Vt2nNIypdpvD7yVMC288mV7n+GKtY6WegOHaum0nhrtcCxtWuRY2RIvGcHbUj+1mEXmj9rNc+imbjdyP6Zrd5RLbsLElrvTxI1nt0t/arAbXeekm7dzye1ZzvdVcbR2ua7LiJGbzG4N3/eB9G/z65sFDPi7grRsyzfIODuU70xjVTKNvHEr/3w4V+lno1g+8yaHsYE0u/WGz2vwODnV0VttaGML6GocyNPhzNmIWRzeLqIzqLKY3zuLbok3NcXk+TOmVLI4RSGwWG3p+yRHaSo5KnkqBSkcutR8wVdtt5zrJZeOONv8ArzBQ92UfXtspP8oq9PSiz19+yd4afaq0qxlc2o0CIk9LsXbZfjUia72ykBpKSbPVoZ1rrLPQ22LnGnsE6tHVHu1ahuroHUczcW0m2swM5veSdTtRrch5L1mZlTqztbOtdmbpHUud2dNsO724k9n202yKwbXdJY8FDtYuv12hV01m28ls8paUxvPtXdyz0AcwZ4reV8fbSo5KnkqBSkcufU0fefSGRn+U0ccEXKZ9MF9uVjnOJdDC1Wm7Y+Z2Hyp+16ZlM9DuYDhLbmKz/gEVov6JMnCP0Uf6xzX944X+gVOTZMWRlbaQOz9TSLZXSF4SRtZQTSJ1Ox0hlc43MHNO3vvUL/DZNkH1C3h2cksJubV0sgt62XVO0eSmuDALvTCbnv2BKRdoTZiRIGMVsnGOcyIm2/M4J2LyVO81XJRuMJXnRcJl8YN34kdfc+IKTrA7nGTu5II3/YA9/7P0huP0diZAkSHmgXDy8dW3aw/oW99a6/rN2gMwtax567bZ+UY3bVLMMjur3s66tzP0dl57Oy9CrkA+ONF3ilHf6F8jXUD3cgX79TS9C2y9C1wFjR6ITB/erpAhn0binTzT7sbl/cjlTb8UrjcA9gbYnv1Bw0ALLQNF52MTbzeA6VsPzQD7jQ5ehS/q3hex90Uz9rQ0NLiVktONMJZSEntP+xmVmIFj4UBj+qDerDGBLt2l9ePyDzQh9UC11Gk6RhkGs98jFkUXKoFOVYu+U3TTFehUtag6Rbf1gE5Vq6rbZWv0e0REDoGkEywHZVKnNNVCCQI2hZkYpE1K50m1/6YGeOpIqAotUWFVaKAcg2vjWaGpfBe+NK7yxEs3Qje6IOoYqnP+zzaVs+xZB6nO+X/clENRR1MdOu+KdUhL5jrJQNtW5nDqtFmoV9AkT5l6nduqAy4M5pd/9ZFcTbcmqzwEKmkqLVRCIR6TbGuDQiEeQdNKx2hsg8LTFU9PNXmZvkbtUCywsxf59VCVr6Gu9Z22DpO4KKpy9Jx1kOqcV0aV433znwqXrIWbQdrmC6ikqbRQCeXWbN+FsU/Fr+gKK3Q6X7lVIKfOV3SZvCB0xBiRIJDkJ/WMsV1njtuh5l9ZfC90uTWQUar4jqptfsw6JqvZkPj2TXyH3xbf9jk67xZi/JdS2/dCOrxCHk+dPK7HlKbXy1uvqH+uk0nT1p8bubaFoba1b9K2+HN73px19Ep2HSpZ8w753Y+OANXxmhOb0XGTGaqzdzgC1OtQnanXLJr55Ybk1yrC/erISg1lGr7DhmQbipXl7QdiOcdAptSVsoihkqLSJo8l/HlYs5VcX35/zWx1IiznVPpufTWCNlRSVNoEaYM6z3dUJ6iSXf4HO64tLg==###4744:XlxV32DM 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QA/cKJhGPLedCEVDvfXoSUwc8H51FZca+cLZR/8/DmFSlg==###4724:XlxV32DM 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SD1fGYAZvvL6u/fvZ4/zXLbhe2Ru+NZdWEl5X7iVp5y98vvK+TtAhv29IM/dUMPURWmxN558NslnzzlvwvpY7CJoLH21/KqR7Zrk/Vzn0m+0fdvZMM6exnx2+D4+CXU23v4Se+Nyw0qHvXF5f7Z6vvlwPDRfj4eW8NDXHdPpoYm93cSbygllLbdGaTUPrZiHid6qnzu071gku4D6qmd7kNTr8fBug/sZi5TOXyav6kft7fJc+NOwkcrOSifmPJNIqbPScZ84vIM7vufD2onv+XCGKv0aqmBDta8qNx9/RTFYFPcOPOXyq4PBOljPXHy+2x60ve9lx5K/265Mk3Havr7brozgOG3X77Yrwd3Fj7ivtvc5wG779Lv8atv6fa5EN3//atv6vYvfFtuvtq3fp/gRsbbv9v0N9me3Xb/b7s+Z4WdqNp++217FjVvob4v63fYsXuN9ih/x323P8f4f96ubRg==###6472:XlxV32DM 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F+m1Ooz1U8KRrUjDqj+u/i3h0DqMheqP+6eEI3uRhrG6v1pa7iUcsjhS9P9HrIRDpprTASujmDdKOG5l1m4vALl+SjiEm2/xXoQBoOKFEg6vF0h88/+WcAh3qC93RAlHRAlHRQlHuVDCsbyMolxvEUb5KeGI1o0Sjo4ijALu7lDFcX5KOKJ3m+4af0o4JMSeNuee7aeEI3q3/c7hJUixHlvQsU4/S58A/ZkWDbEzwL0TSjiSJXWVLr9Tx/MDiXLvhPKRTT8lHBLeG6VV8fyEg3ETFke3z8XpsooqrfDUNEUoOTCF0iN9yDUxskYu+baRzdNpoQhtZ1pBuI/rGNcxrvu46gmSUB1thDYbNzFuYtzEuGn4j67XSfNOaxtvu2krpfLIKkHn8v9SuDBW8y2hJP8RStLTVv1m2/xmrpSIawO93Vyb/F8R79Bz2fQIcaTlslQxXbLbbEZDtpEEyxssz7CcYHl1yzPshQ9qUbP/Jcy2BtvITSpu0nCTSNCWsquACNHiwds2UrNkwZLilhTXL1mizuaGdc2p/drZMa8FFmOGZUGq7RW2L5tXnmohDia4uTfTvZH8sDU7q82Z4S70d4LRJkWPaservUD7dl2uVOfysnXyQLjtItGfqZF6Ngt6mcInMRbviV9kWYEQpLM1vLD31ipTFlevH3EZK2eZOEkwVVx3cR3iJsQNFRchLrh1NX14OVxUSIOQd74Qml0jt+YfcRlreLm4CikIoddHycUVafaWij/7Kcd2XjkzlHd5qL1BwhhP/95lw7YPG0bI/qrjt4y33ZcJzcW4GN9+u2FS/veZy+JRhmWv8v/+u9Px706R/wI86xVxkolxRb/x1ux/+1SbEqno5/B+1OYerCRX//HZrre5Nsn7VN5wSn4FUskZkrf9NWDaxvRn4EJevac6husY8G1CW4dHHRPU7W8FzZKFknFqVYEt759M021R661qXR77/ADVJzn5w7Ic1PCmbOXZofoPItxtKerBDyzt/v7Aoon19rayCc8VfqvjPw1diretunG/wz2wJ3/MKH6a2xtMN9Fm66qeh7AcqaHWm6xd9VBvLLl/zmaicoc5vXtK0Tl7MNfyH7moHnvtn/zPb+HbhA7k6eZevVRRCK5wTq9dpWr14sYiN4JJ/Uchgy//1Wr6MLdtYqpQPpaJHLk0kh+DYZ5m0SmUGCECJf6EOqrvxK9AuQVRtS1bKf1Xsto5pQLHK3BBoEwJ1ruySHzKOv/YQGCZMouSQPNHOjV7uBa5NepAUmOXDVTZDd43DFxqRPwZOGBExMCt0+3JnKIqv2KG6ak9lWX3M8X39jlRZ5b/uUr+WGrMOrW7fpmlmGbu+cM8wNzArNO4+w/QwTXLQhYxssx1xkDJa9CZ/gePCtRJLvbUaq4UF/gRUyBmQ8zrlEKw29cpKUIRazQihHmA+XVqqQ0bzP8HBeA47A==###6464:XlxV32DM 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J1tUeqE8a5dPiRSXEE3UHz7uk6kiPVHfErnGMN5y5cdevhQFIA/kLrJbt6IA5IGEL4Mvgy+DL4OvgK+Ar4CvgK+Cr4Kvgq+Cr4Gvga+Br4Gvg6+Dr4Ovg2+Ab4BvgG+AD+NHGD/C+BHGz14OFQUgDyR8C3wLfAt8C3wbfBt8G3wb9jnY52Cfg30OfB58HnwefB58AXwBfAF8AXwP+B7wPeB7wKcvX4ruFHyifhA696HH0DOAlqGdgTpQADLZiNX/ELnUJ2rm862bs9dQBipAFagBdaABBH329sHxMrTB54A8UAB6gPStIoSl5VAHWTkX+8nvAmdAqn71lkGqNlz8M4MwNnE+fJ3fcH7D+Q3nN5zfcH7D+Q3nN5zfcH7D+Q3nN5zfcH7D+Q3nN5wnOD/h/FKftGbmOvrjvIzNM7TUTRizOP98nM+2qhnKQAWoAjWgDjSAoM/uteJ8tplqfA7IAwWgB0jvoeHp+qUjPFMPk+wInF9wfhnjRfxBVxjZeTetHtdZKcrZVjx+lslWppydffDNXLnOzYTNhpr+RXVoQ5t9S1ZBXa3a7dCs+fRtRnLf/E2O+2ZvGEke5xyVka1gRraCGRkJI21LeLaHGdkeZmSkf64kZRTL+OzKlvEJmJFodPZ1WG0cZhmstaJau2OrjcMsg7XKSHt8bBxmGazVp6OGV71qlZBiGaxVjW7FXxsJo6cI5Yw5918buTkXr1nB1kpBGe31ayNh9BjNexSUD+8trV8b+abUsj0UsbWi0a38sRF5tqfZaBlHHxuL2dhho/7h5NzHRuQea2Qb52Ybs/vYWMzGDhtFo1v118bXsoRx1KSwb5TB38K1fC8Sa2/NcEZvMvPPKMfw9esW62a3EoKguc4lxFd35oeejDy6G2Ws1YotqpTW8UiE35F4/V8WLbkqHOhV97znaNY9vE1cRu+UkZ9oWg6/g8dXQB68hFDrjCr2abnxM9wdk1Ks4I3RO8tkTNwan/EeyFYbeUtwsoIpV8kY71LIi/pFsqg7LSXgENEnRG9glqE3B7uEqPhPiAZmhwXLpnq08GdvBbbZaioErQIRNidX/4nqu44iqlwZy4hLVU9U4yeqw6LKk5WjKrppalFnoP58GHlKTCvvZCRJJn8hvYnwhn8ZeueTzvScPokwMNMtJWzZepYlwi3OA6Pct9uj5giy3Emf3HkzZhmid+/Q3MHegSomRrxMcBbpwoMKL9f2hxGIC5o4i2SaOKx+kjsVGVMtY3hlOQHGvhQwla3sSHJHjLi1sRr+kD6MBbmTDanuahWLkjHVMub+Sqd5UiVPbGWd9hylK3SzoMvqT8tZngwrhpHmN0+yITFi+mS6OU8qsqNadtgaa/tp8/l3cZAd4TEjfItW8dLMWm0uyA7kieou9not2VGRE9VyQqx1e//O+TQRt2ZoY9eWUOeqK8v/AZAsvQY=###6536:XlxV32DM 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FcmDdBVkuw2QTgD+XvYK5HzTb4Rn/ReKX4KyTDCR5MEkhARiv5vYE9y0u1yo7zbizvE1w4y4qGYaVCKVlbzjMGQDzzuBB5Wn2tt72pHQsweHzRsZyjrp7CTTND2Mr6+y3QQhqhzOtRvBll6R9D8R6S5Bktmu3S12N9jd6/+bdTnkhIqzoAJwXkhvLDMqyavpfc6q+nTrF/4i8C9Sa9jtTM1UoFcVPeFeMe2KlCcR0FhYwLHQTOdwmBwOOpbWMXifhz3fT9cHPj8ipUQpUyqUKqVGqVOivfP2atKitNnuonRTcpQ8pTP3usVk06cULMZN2LAyaQZGZDt7iORVH30THmTl1dJfCVtfFabRGRit2OHRX9loo2Z6nufUIJiILsCrYCmpbpTHyDQ4l5utjU9hp8pid7fN1lOrPDZVSarif1QCVIb2gvmhKvpoH7GgVDCvXMsdjsXrxzHl+IRNFQfHMiaDNhTlAALlI64flQAV2fpUpZmK7d1FbhP5P83ieJ/iK57OZTjrM3nFM7l4EJuBJw/msps/kWAFqj1+s6ngRXCMdTRUgNc4LDoGQ1VAo8OD/gjfvGnokake13cwvMNscpV+mvVVjdIpql/DEYbP9iC1BvuwRUcNDxpeNFxguCkGk+SG+B0cinTAyquGGwxPGm40zIlR1XK8bcXUMUSXLbf3T24HLC9arrRcabnDebmuBWEKPc77W+gIskpmGw7PKmlPI/4uxqTwd7VLu78b9uhjRaksd75BnwoX/m8Jl87Xf6RsCb1RVZRQJJfxbsSUtYTAI5KjdFMSPtEhxilrwSVKFYwHobKotCAdttGR7nGuCk6ZQw7/y4hB2SlFelk55uEdvg1lBxTppc4ofX7j9zJzkRZXJlXHGrZvww2LMgalod57HrH90KkKwlKeU4xfYpVef/eNP/IkOxrWkSws/lGx3fVtqGEdqbFh00l5z68TcaF6kW0k530lRCmRxfmv7UEnLBMkw5/CT8MNJ5AJEroPwGhYGVZFWI7sU/4hp2Ta88E8k8w4nbFzlH6TybQVzmv2P0zbaFxa0GX3h2krp+9Tq+4p9eZl2h7Vp4gk3QSmbUOvT5HW7nT/MG0juLTa6zVJl51Gl5WvYFWYtuWHaRuNS2sOX+HLtHXGw7WR5fz+YdpGIcPulyvbyLTdZNqml2mbfpi2on1+4YX2Tabt0lxpNZi284dpK9pyfDSmbSHTdupfGm73ATLsoc1+mbYRVFpwZfeXaetAxEXcd/9h2qrn/eXpJjJt+yduMm0Dmbbhh3HalGnbfpi27q82BNs1TTJtmy3LrsSXaet/mLYO1WDaJjJtk52ynP2JItrjh2kr2qehrk2uXOC3nw/JMiOFSmt8VVD4jGnrrBqel0rPcU05ZdReP0xbZ9Vk2i4ybZedOpRxqllbP5CItjTUJSIvUu+H3SSlDFnbP8NBtVd+ubKI+0jadx6NHOH9MxRVe1/seyPuFLBQC5V2GNP2ZxqYdoV2uRyZts4Q8/v/9dNW2Q==###6664:XlxV32DM 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0JmGbGzzwjZgP8jerk296nzukko6j6yrJHhmaMFMPoy08xGAjfAWZIwCTZ83JFgndYoNGWXMkM8eRAijg96fpxPnFoLR3NLxjH3+OxEw1eoUUQMRVRBRBRE1EFEDEVUQUQNxNBFHCXHUEEcVcTQQRwNxNBBHBXE0EEenybVrwCdO7d+dYjt07vqCw9GTJXo0BqNqnx9wNEDf+Cg4kx5RMRAVA1ExEAsFsTAQCwV+KIiFgVgoiIWBWCiIBUCCdfIivZWhorSTN4eMLdibE96s8GaFNye8OeHNCm9OeHPAmxneTPBmgTcnvDnhzQlvVnhzwofwnNBBvy7Xfc+O51rirgp3Zbirwl0T7kIKlYXvdr1ud2TlTarAsaS6Wt5kxHEVjqtw3ITjKhw34bgKxwESrNNPWyy+7LM0UIcQnkY43z/9QMFLReFexKOb8HLFMZq7iXLfwpwUQowevPj4LF4FLTOq09q+C/6i7a70A/pt7+5ojcz1uRuOjO7oRbr2ZT1KwG4wfRavipZHPPP59O02etKp2DczPZ5wY8//CLEWmjmxCqOP6Ic/ljyJ8XxWmejV/XzmpdBUaCT8tvBbxm8PfisK0fiPfzOAKrAOv126BqzHb5cO+s3ziRe9w41LB53PkFCgq/3VGZp2SDvDK1kZms77G3Y+sd95d3l3hPXkE8TzBImPevgJ0uFBEU+L3HsY+oAxKOHrYRUQVUnmfo2Ys37UlrN8l2lzw3f3OccP2iuaX/i70da8e/7oa0MWk79uxhtNJRGjqRYNRfvf0J1wh1KUO+AoEpq4GU0DvaXHYUPylwD7uKqaL+3cBe0VzZqfB8v3SW14xJQ0EHHOI875vGkgAB0+aEkD67N4FzTSQP6c1IbpmMwclJt/pKP6rIue7zTAox+5z2nx8lm8C1pkO/+8VQsFT7a8b/3Im0cxz0XLvhP2nT5o3ncM78WdFTT2Xd+qhaJTRk1/ARvT11EeQkr6e4B+sO+K9Kef5/LiJDvjzzD7ZtSxvtVXIqkzC6NPerT5n97OHbdzwe2ccTsT1JqOh2fQOrm7N8TVVOaeUWpxrpJm+1TgSWso6T3kz3ZSi3dU4AkV+EK1PVFjV9TYFbtDPT3wG+UKuu/NT/4nCnKRN5suWAyWefTOrijV29T6IVtpxan2oORDEP/DhZcuWPqyLG7R9IzyRguUnayifK8kO4XP2Ia0lyGQfMji6Jucdf7gus9to+9qjqOkGCdXVLgCDRIvTQ6oMPu1Q8buO8y+YPaELzgKHHB3Qk9gVv8pKczXKxk7mboT/m+MpVHQZYH7BtZel5mn0emcr3I+xdldtHxpxJADZAGdAHNWv0hiyAGygJhugG6AboBuKJ3Deg7rOaznsJ5zoHOgc6BzoPOg86DzoPOgC6ALoAugC6CLoIugi6CLoIP9HOznYD8H+5kMO2fYOcPOGXQFdAV0BXQFdBV0FXQVdBX+gP0s7GdhPwv7mYb1GtZrWK9hPdjZws4Wdraws+lYr2O9jvU61oM/LPxh4Q8Lf9gJugm6CboJuYg/g/gziD+D+LPwr4V/Lfxr4V+7QLdAt0C3IBf6GehnoJ+BfhbxYhEvFvFi73l7QPeA7gHdA7nQz0A/A/0M9LOIP4v4s4g/gsz/34PAWw==###6680:XlxV32DM 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zesDrGADyPbY4t4d0rm8zUHnq1RJk70JWwIJPVGjewB+rEZZYkHOz+wJNj0TagNZV49yTUBsOtxhkaUUbRoWprZ7qE3HTy0mlbjUkTgKGznwQI/seuK3/UI5UBaUISoDl4HLwGXgCnAFuAJcAa4CV4GrwFXgGnANuAZcA64D14HrwHXgBnADuAHcAG7y/zmECkRFyEbIRshGyC7gFnALuAXcBm4Dt4HbihtGccMobhjFDQOcBc4CZ4GzwDngHHAOOAecB84D54HzwAXgAnABuAAcxm9g/AbGb+j40Toe/Chq+fe7plzwSCnhaRLOp3nDj2Ler4tywVOhhAdCRQOnlMD0HgFvfEiEH+wkDV8ND3aGXD3W90sbEuFnM0nDScP1IWftdd1d1+Vb1r35oms68mh0TafUUqopdeMBB457YSfcu6iJKvcok1+q9UfLEI90unMaYOYNVE1FOGuc5fp762TEyDBvDp8UeZMiqKTUKTa0DbiYQVmlTrjXtgGJh/KgOnBoi9B8/Ci7/WH0heJ8nnfNpGXBNZ8+j4Aar+gtypDJpa9zxcs3ueJAeYu2DcooZQeoAm4FJRPlIj1GoIesW9Pb0/GnsiULY56IYNm9rrHZQqeTeygZVwoyHI1c02nmdzGNcBESQakGLW1rgLLxc15Ny4HUyPtLv9/JP4U35yNqA7vebL7P81FT/hg1x05b/+VFsZypm9MLtYXil5S0Q7IPstu5EU8pqXom6nk1yc9Ysr6hleeVUTTK5M+u50Fz6APcObU6JIqr4knnalGBFIxZJCqQoiiLQJjOHvrGApxbEkqSpQHtUQ98g5P/OxxqSl3R9VLZrhblHmzVLSMycN5CmkmWbeH/xzmqeOmfICbJVDprQen0Ooc250B5UAFUBAV9JoMqoCr6gD7T0AbNpqMNfdBbXubCPot+7QIXOPt82wYXOAv73L0/7PLfSuXCZmtAPdY/NsPSgPXoaD3Sn5+Cx/8P5QyV/4kof6KiO/CgQApJDMQ/GvkPU6Hp/0BWltMKb+7EU1q/7ganWtWbooetNwdL0f4qcAJI1UPTZwd2Gt0zbaLmHVPfNN5/r5EeAU4A+fB7zs8LYoPnZ4i0z2MyibS5fd7xGjzQep46eTzB4npzlc9rWoMnTM9jIERafeTjP29aDR75PI9fnoc69GdLU4eO7f0v0j0+83dbyKeOLe5437+f8tO9reeMtulRoG1LqzVm8wvBGTGgRgaUgY+eyRMcMMHpNcE8/2eC7WeC3a8CJ4CJJzi9J5je+902ffK6zGeCnU4wHR8ykP6AaFqGPVn+Levs0PJnZbzJzPzXogtc4vaPuR3mNu5GgAlA+lui0WSDG++e8fdKTL5m6nXnHXs+q7lNOvYzv8ee5pXZPPbLfsbe6di3CuBkPRrDLsWlOd0HqZ76HrNsfhWYACQ901uMvfynYZeAEa0Ty0weiHj2h3QKsVJ/s6kwXXTOwCOaNTTdjFt2OF6gr+dAYugfOHdQE8ce+h/ppoei0kj7f8xn/6fPkHlITwD576RNj1l2kRtV2+952qWIS1tB/r3KU407eRLJd01QCmbpyH3hj17Mpv8L4r3UkQ5vdmqQFuUf6VTBFmn7YWeweXDxRo3ZCWyeOb8/7Ag2702/Puyg7MCm+flh/w9zoq4B###5352:XlxV32DM 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e76R+YYruc5n9Z1XD6OyzPd7N9zKld7z9cw3/2b3fDPzTVdyzTd93y9130jmG775liu950vdmH+ze77UjelKru83HeeRuALfhSuYNaj+ffn1Nxs5m+Vk/y5fx7Wfvmu/Xel9Tkau/fqb3ddC5Vp4/vwHTi5yuA==###5888:XlxV32DM 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wwXrW9m4A6gtrHiwNbqWHe7A6JoTrm9yiV/XkMBFo1z0m8+saxt25SnN0ErENtkEboofh6fd2xXsPODFw+EGrDvVDWcYiiuw7Xg3HGIY7oJ36sYphuEH2HTjpEKxREwwdO8On4apOzssXbNV84vT47BEbGMieVuXFQ+2hlsuhzuwdQ1HSoYfw+gazpRUo0RsW46ruAaU11zPqw6cnwcEWV9aXfmH0tYmehB14CRdj8L4nuseIBxxbdKpRVKlJg5qkVSpi4uEFpqnTqbKIMd/FDjQB02VInCgD5Yqw3GjyYlUKSW19Iq0lDvNcG5rE7X0xIG7Hr4xj5mlZ12bdGpRSyUxUotZyt9hpF5helVLz7EKHOiDWYpVlgiEpTWjyZSjls6SxbTC0puXrkK91iZq6Sw1NqnM02ap3Chkk04tFtMKS2U/KtMf7yhpvcLpQy3lUl/wQB8Q0wpLb/5ZG+QamzQpOywtOy1tOGO9eUW78uabTAYPU7NlT14flYeG44cjMRbZkv/sTY7mRs1bX4KT9aRkQn0B7w39SVgwWsWbKbOjJEsiaaIX6LawrU16RUVNS3L2cqCJXsnb5Mz6ZpMb6U1LrbOEAysVKKVof+y+fa0sscVUYqUDpT74jNragY3DdjAlXVhWamfUiXKMRPMGezPgEV2oTs12IVFvS2iTHT6OCRGICRG4eW90435IJwlaqn6PiX4/Pr+PtUmnlk4t5ndeXt3wH7VNJoXetvGSVomDnRjoBEzlbVn9Ii5N5ICmIi76S87AFyuJgZkaz7VJZSjFVCk1NlFT9UYQm3Rq6dSipnbc3Lj4i8+G4xsbTUMF1lXgYB8G+mCWdl6fTYMRavaxZD77PwWPz/c=###6224:XlxV32DM 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx new file mode 100644 index 000000000..7adb4c324 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.twx @@ -0,0 +1,341 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.1 Trace (lin64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved./opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3 +-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf + +b200.ncdb200.ncdb200.pcfb200.pcfxc6slx75C-3PRODUCTION 1.21 2012-04-231103INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;000000016.000Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;0000000Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;00000001.639Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;4890322009931212.189Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path +-2.189slave_fifo32/EP_READYslave_fifo32/EP_READY112.263-0.30910.0000.235slave_fifo32/EP_READYslave_fifo32/EP_READY10ILOGIC_X17Y55.CLK0gpif_clkILOGIC_X17Y55.Q4Tickq0.992slave_fifo32/EP_READYslave_fifo32/EP_READYOLOGIC_X4Y173.D1net210.468slave_fifo32/EP_READYOLOGIC_X4Y173.CLK0Todck0.803slave_fifo32/EP_READY1slave_fifo32/EP_READY11.79510.46812.263gpif_clk14.685.4Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path +-1.341slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK111.0290.07710.0000.235slave_fifo32/EP_WMARKslave_fifo32/EP_WMARK10ILOGIC_X17Y78.CLK0gpif_clkILOGIC_X17Y78.Q4Tickq0.992slave_fifo32/EP_WMARKslave_fifo32/EP_WMARKOLOGIC_X2Y175.D1net29.234slave_fifo32/EP_WMARKOLOGIC_X2Y175.CLK0Todck0.803slave_fifo32/EP_WMARK1slave_fifo32/EP_WMARK11.7959.23411.029gpif_clk16.383.7Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 + HIGH 50%;1codec_main_clk_ncodec_main_clk_n12.189codec_main_clk_p12.189codec_main_clk_pcodec_main_clk_n12.189codec_main_clk_p12.18923530353004890301238816.00062.500Tue Jan 29 17:12:06 2013 TraceTrace Settings + +Peak Memory Usage: 536 MB + diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf new file mode 100644 index 000000000..6c9af6954 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.ucf @@ -0,0 +1,415 @@ + +#################################################################################### +# Generated by PlanAhead 14.4 built on 'Tue Dec 18 05:17:28 MST 2012' by 'xbuild' +#################################################################################### + + +#################################################################################### +# Constraints from file : 'b200.ucf' +#################################################################################### + +## SPI Nets + +NET "cat_ce" LOC = Y1; +NET "cat_ce" IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = V1; +NET "cat_miso" IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = T4; +NET "cat_mosi" IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = P7; +NET "cat_sclk" IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = H20; +NET "fx3_miso" LOC = G20; +NET "fx3_mosi" LOC = AA20; +NET "fx3_sclk" LOC = Y21; + +NET "pll_ce" LOC = W11; +NET "pll_mosi" LOC = AB11; +NET "pll_sclk" LOC = Y12; + +NET "FPGA_RXD0" LOC = AB8; +NET "FPGA_TXD0" LOC = AB7; + +NET "SCL_FPGA" LOC = P21; +NET "SDA_FPGA" LOC = W22; + +## Catalina Controls + +NET "codec_enable" LOC = J6; +NET "codec_enable" IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = P6; +NET "codec_en_agc" IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = Y2; +NET "codec_reset" IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = M3; +NET "codec_sync" IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = M7; +NET "codec_txrx" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in[0]" LOC = E3; +NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[1]" LOC = F2; +NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[2]" LOC = F1; +NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in[3]" LOC = E1; +NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out[0]" LOC = D1; +NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[1]" LOC = C1; +NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[2]" LOC = H3; +NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[3]" LOC = F3; +NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[4]" LOC = P1; +NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[5]" LOC = J1; +NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[6]" LOC = B1; +NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out[7]" LOC = H2; +NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d[0]" LOC = T2; +NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[0]" DRIVE = 4; +NET "rx_codec_d[1]" LOC = R1; +NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[1]" DRIVE = 4; +NET "rx_codec_d[2]" LOC = V2; +NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[2]" DRIVE = 4; +NET "rx_codec_d[3]" LOC = N1; +NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[3]" DRIVE = 4; +NET "rx_codec_d[4]" LOC = V3; +NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[4]" DRIVE = 4; +NET "rx_codec_d[5]" LOC = T1; +NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[5]" DRIVE = 4; +NET "rx_codec_d[6]" LOC = W1; +NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[6]" DRIVE = 4; +NET "rx_codec_d[7]" LOC = U1; +NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[7]" DRIVE = 4; +NET "rx_codec_d[8]" LOC = W3; +NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[8]" DRIVE = 4; +NET "rx_codec_d[9]" LOC = U3; +NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[9]" DRIVE = 4; +NET "rx_codec_d[10]" LOC = P2; +NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[10]" DRIVE = 4; +NET "rx_codec_d[11]" LOC = R3; +NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "rx_codec_d[11]" DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d[0]" LOC = M1; +NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[0]" DRIVE = 4; +NET "tx_codec_d[1]" LOC = K1; +NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[1]" DRIVE = 4; +NET "tx_codec_d[2]" LOC = L3; +NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[2]" DRIVE = 4; +NET "tx_codec_d[3]" LOC = K2; +NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[3]" DRIVE = 4; +NET "tx_codec_d[4]" LOC = M4; +NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[4]" DRIVE = 4; +NET "tx_codec_d[5]" LOC = J4; +NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[5]" DRIVE = 4; +NET "tx_codec_d[6]" LOC = L4; +NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[6]" DRIVE = 4; +NET "tx_codec_d[7]" LOC = H1; +NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[7]" DRIVE = 4; +NET "tx_codec_d[8]" LOC = M2; +NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[8]" DRIVE = 4; +NET "tx_codec_d[9]" LOC = G1; +NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[9]" DRIVE = 4; +NET "tx_codec_d[10]" LOC = N3; +NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[10]" DRIVE = 4; +NET "tx_codec_d[11]" LOC = G3; +NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18; +NET "tx_codec_d[11]" DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = J3; +NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = K3; +NET "codec_data_clk_p" IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = P3; +NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = K5; +# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = K4; + +NET "rx_frame_p" LOC = U4; +NET "rx_frame_p" IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = T3; +NET "tx_frame_p" IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug[0]" LOC = C14; +NET "debug[1]" LOC = F15; +NET "debug[2]" LOC = A18; +NET "debug[3]" LOC = A17; +NET "debug[4]" LOC = E14; +NET "debug[5]" LOC = G13; +NET "debug[6]" LOC = D13; +NET "debug[7]" LOC = F13; +NET "debug[8]" LOC = D8; +NET "debug[9]" LOC = A6; +NET "debug[10]" LOC = D7; +NET "debug[11]" LOC = A5; +NET "debug[12]" LOC = B6; +NET "debug[13]" LOC = A3; +NET "debug[14]" LOC = A7; +NET "debug[15]" LOC = A8; +NET "debug[16]" LOC = B18; +NET "debug[17]" LOC = C17; +NET "debug[18]" LOC = H13; +NET "debug[19]" LOC = D12; +NET "debug[20]" LOC = H14; +NET "debug[21]" LOC = C10; +NET "debug[22]" LOC = D10; +NET "debug[23]" LOC = C8; +NET "debug[24]" LOC = D9; +NET "debug[25]" LOC = C5; +NET "debug[26]" LOC = A9; +NET "debug[27]" LOC = B8; +NET "debug[28]" LOC = A4; +NET "debug[29]" LOC = C7; +NET "debug[30]" LOC = C6; +NET "debug[31]" LOC = D6; + +NET "debug_clk[0]" LOC = A12; +NET "debug_clk[1]" LOC = C12; + +## GPIF + +NET "IFCLK" LOC = H21; +NET "FX3_EXTINT" LOC = U20; + +NET "GPIF_CTL0" LOC = V20; +NET "GPIF_CTL1" LOC = T22; +NET "GPIF_CTL2" LOC = R22; +NET "GPIF_CTL3" LOC = U22; +NET "GPIF_CTL4" LOC = P19; +NET "GPIF_CTL5" LOC = N22; +NET "GPIF_CTL6" LOC = T21; +NET "GPIF_CTL7" LOC = V21; +NET "GPIF_CTL8" LOC = K18; +NET "GPIF_CTL9" LOC = R20; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = P22; +NET "GPIF_CTL12" LOC = M20; + +NET "GPIF_D[0]" LOC = T17; +NET "GPIF_D[1]" LOC = U14; +NET "GPIF_D[2]" LOC = U13; +NET "GPIF_D[3]" LOC = AA6; +NET "GPIF_D[4]" LOC = AB6; +NET "GPIF_D[5]" LOC = Y3; +NET "GPIF_D[6]" LOC = AB3; +NET "GPIF_D[7]" LOC = AA4; +NET "GPIF_D[8]" LOC = AA2; +NET "GPIF_D[9]" LOC = AB2; +NET "GPIF_D[10]" LOC = AB19; +NET "GPIF_D[11]" LOC = AA18; +NET "GPIF_D[12]" LOC = AB18; +NET "GPIF_D[13]" LOC = Y13; +NET "GPIF_D[14]" LOC = AA12; +NET "GPIF_D[15]" LOC = AB12; +NET "GPIF_D[16]" LOC = N20; +NET "GPIF_D[17]" LOC = L20; +NET "GPIF_D[18]" LOC = N19; +NET "GPIF_D[19]" LOC = M22; +NET "GPIF_D[20]" LOC = L19; +NET "GPIF_D[21]" LOC = M21; +NET "GPIF_D[22]" LOC = M19; +NET "GPIF_D[23]" LOC = K22; +NET "GPIF_D[24]" LOC = J20; +NET "GPIF_D[25]" LOC = L22; +NET "GPIF_D[26]" LOC = K19; +NET "GPIF_D[27]" LOC = H22; +NET "GPIF_D[28]" LOC = J22; +NET "GPIF_D[29]" LOC = K20; +NET "GPIF_D[30]" LOC = G22; +NET "GPIF_D[31]" LOC = F22; + +## GPS + +NET "gps_lock" LOC = Y17; +NET "gps_out_enable" LOC = V22; +NET "gps_ref_enable" LOC = AB13; +NET "gps_rxd" LOC = AB14; +NET "gps_txd" LOC = W12; +NET "gps_txd_nmea" LOC = AA14; + +## LEDS + +NET "LED_RX1" LOC = C22; +NET "LED_RX2" LOC = L15; +NET "LED_TXRX1_TX" LOC = C20; +NET "LED_TXRX2_RX" LOC = D21; +NET "LED_TXRX1_RX" LOC = K16; +NET "LED_TXRX2_TX" LOC = D22; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = Y15; +NET "pll_lock" LOC = AB10; +NET "AUX_PWR_ON" LOC = AA21; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = AB15; +NET "PPS_IN_EXT" LOC = AB16; +NET "PPS_IN_INT" LOC = AB21; +NET "pps_out" LOC = AB17; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = W4; +NET "SFDX1_TX" LOC = T18; +NET "SFDX2_RX" LOC = F18; +NET "SFDX2_TX" LOC = H17; +NET "SRX1_RX" LOC = Y7; +NET "SRX1_TX" LOC = AA8; +NET "SRX2_RX" LOC = J17; +NET "SRX2_TX" LOC = F19; +NET "tx_bandsel_a" LOC = N16; +NET "tx_bandsel_b" LOC = M16; +NET "tx_enable1" LOC = Y4; +NET "tx_enable2" LOC = R19; +NET "rx_bandsel_a" LOC = T20; +NET "rx_bandsel_b" LOC = U19; +NET "rx_bandsel_c" LOC = P20; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; + +#################################################################################### +# Constraints from file : 'timing.ucf' +#################################################################################### + + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_D_9_IOBUF" IOB =TRUE; +INST "GPIF_D_8_IOBUF" IOB =TRUE; +INST "GPIF_D_7_IOBUF" IOB =TRUE; +INST "GPIF_D_6_IOBUF" IOB =TRUE; +INST "GPIF_D_5_IOBUF" IOB =TRUE; +INST "GPIF_D_4_IOBUF" IOB =TRUE; +INST "GPIF_D_3_IOBUF" IOB =TRUE; +INST "GPIF_D_31_IOBUF" IOB =TRUE; +INST "GPIF_D_30_IOBUF" IOB =TRUE; +INST "GPIF_D_2_IOBUF" IOB =TRUE; +INST "GPIF_D_29_IOBUF" IOB =TRUE; +INST "GPIF_D_28_IOBUF" IOB =TRUE; +INST "GPIF_D_27_IOBUF" IOB =TRUE; +INST "GPIF_D_26_IOBUF" IOB =TRUE; +INST "GPIF_D_25_IOBUF" IOB =TRUE; +INST "GPIF_D_24_IOBUF" IOB =TRUE; +INST "GPIF_D_23_IOBUF" IOB =TRUE; +INST "GPIF_D_22_IOBUF" IOB =TRUE; +INST "GPIF_D_21_IOBUF" IOB =TRUE; +INST "GPIF_D_20_IOBUF" IOB =TRUE; +INST "GPIF_D_1_IOBUF" IOB =TRUE; +INST "GPIF_CTL0_OBUF" IOB =TRUE; +INST "GPIF_CTL11_OBUF" IOB =TRUE; +INST "GPIF_CTL12_OBUF" IOB =TRUE; +INST "GPIF_CTL1_OBUF" IOB =TRUE; +INST "GPIF_CTL2_OBUF" IOB =TRUE; +INST "GPIF_CTL3_OBUF" IOB =TRUE; +INST "GPIF_CTL4_IBUF" IOB =TRUE; +INST "GPIF_CTL5_IBUF" IOB =TRUE; +INST "GPIF_CTL7_OBUF" IOB =TRUE; +INST "GPIF_CTL9_IBUF" IOB =TRUE; +INST "GPIF_D_0_IOBUF" IOB =TRUE; +INST "GPIF_D_10_IOBUF" IOB =TRUE; +INST "GPIF_D_11_IOBUF" IOB =TRUE; +INST "GPIF_D_12_IOBUF" IOB =TRUE; +INST "GPIF_D_13_IOBUF" IOB =TRUE; +INST "GPIF_D_14_IOBUF" IOB =TRUE; +INST "GPIF_D_15_IOBUF" IOB =TRUE; +INST "GPIF_D_16_IOBUF" IOB =TRUE; +INST "GPIF_D_17_IOBUF" IOB =TRUE; +INST "GPIF_D_18_IOBUF" IOB =TRUE; +INST "GPIF_D_19_IOBUF" IOB =TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D[*]" TNM = "gpif_net_out"; +INST "GPIF_D[*]" TNM = "gpif_net_in"; +INST "GPIF_CTL0" TNM = "gpif_net_out"; +INST "GPIF_CTL1" TNM = "gpif_net_out"; +INST "GPIF_CTL2" TNM = "gpif_net_out"; +INST "GPIF_CTL3" TNM = "gpif_net_out"; +INST "GPIF_CTL4" TNM = "gpif_net_in"; +INST "GPIF_CTL5" TNM = "gpif_net_in"; +INST "GPIF_CTL7" TNM = "gpif_net_out"; +INST "GPIF_CTL11" TNM = "gpif_net_out"; +INST "GPIF_CTL12" TNM = "gpif_net_out"; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl new file mode 100644 index 000000000..f35ea02e6 Binary files /dev/null and b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/b200.xdl differ diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt new file mode 100644 index 000000000..bf500d659 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/htr.txt @@ -0,0 +1,13 @@ +# +# PlanAhead(TM) +# htr.txt: a PlanAhead-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for PlanAhead to track run status. +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf" +map -intstyle pa -w "b200.ngd" +par -intstyle pa "b200.ncd" -w "b200_routed.ncd" +trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf" +xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl" diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js new file mode 100644 index 000000000..759e0d89d --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/rundef.js @@ -0,0 +1,48 @@ +// +// PlanAhead(TM) +// rundef.js: a PlanAhead-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;"; +} else { + PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "ngdbuild", + "-intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc \"b200.ucf\" \"b200.edf\"" ); +ISEStep( "map", + "-intstyle pa -w \"b200.ngd\"" ); +ISEStep( "par", + "-intstyle pa \"b200.ncd\" -w \"b200_routed.ncd\"" ); +ISEStep( "trce", + "-intstyle ise -o \"b200.twr\" -v 30 -l 30 \"b200_routed.ncd\" \"b200.pcf\"" ); +ISEStep( "xdl", + "-secure -ncd2xdl -nopips \"b200_routed.ncd\" \"b200_routed.xdl\"" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat new file mode 100644 index 000000000..4eed28871 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem PlanAhead (TM) +rem runme.bat: a PlanAhead-generated Script +rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log new file mode 100644 index 000000000..9fee0944e --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.log @@ -0,0 +1,4 @@ +*** PLEASE NOTE: this run was imported on Tue Jan 29 17:25:57 2013 + from ISE results generated outside of PlanAhead. + Original messages and reports have not been imported + but you can launch bitgen on this run if desired... diff --git a/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh new file mode 100755 index 000000000..f814cb32f --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# PlanAhead(TM) +# runme.sh: a PlanAhead-generated Runs Script for UNIX +# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin +else + PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD=`dirname "$0"` +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf" +EAStep map -intstyle pa -w "b200.ngd" +EAStep par -intstyle pa "b200.ncd" -w "b200_routed.ncd" +EAStep trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf" +EAStep xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl" diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf new file mode 100644 index 000000000..75ffef7f3 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/b200.ucf @@ -0,0 +1,241 @@ +## SPI Nets + +NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18; +NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18; +NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18; +NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18; + +NET "fx3_ce" LOC = "H20" ; +NET "fx3_miso" LOC = "G20" ; +NET "fx3_mosi" LOC = "AA20" ; +NET "fx3_sclk" LOC = "Y21" ; + +NET "pll_ce" LOC = "W11" ; +NET "pll_mosi" LOC = "AB11" ; +NET "pll_sclk" LOC = "Y12" ; + +NET "FPGA_RXD0" LOC = "AB8" ; +NET "FPGA_TXD0" LOC = "AB7" ; + +NET "SCL_FPGA" LOC = "P21" ; +NET "SDA_FPGA" LOC = "W22" ; + +## Catalina Controls + +NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18; +NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18; +NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18; +NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18; +NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18; + +NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18; +NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18; + +## Catalina Data RX + +NET "rx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "rx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Data TX + +NET "tx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<2>" LOC = "L3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<3>" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<4>" LOC = "M4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<6>" LOC = "L4" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<8>" LOC = "M2" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; +NET "tx_codec_d<11>" LOC = "G3" | IOSTANDARD = LVCMOS18 | DRIVE = 4; + +## Catalina Clocks + +NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18; +NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18; +NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_p" LOC = "K5" ;# | IOSTANDARD = LVCMOS18; +NET "codec_main_clk_n" LOC = "K4" ;# | IOSTANDARD = LVCMOS18; + +NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18; +NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18; + +## Debug Bus + +NET "debug<0>" LOC = "C14" ; +NET "debug<1>" LOC = "F15" ; +NET "debug<2>" LOC = "A18" ; +NET "debug<3>" LOC = "A17" ; +NET "debug<4>" LOC = "E14" ; +NET "debug<5>" LOC = "G13" ; +NET "debug<6>" LOC = "D13" ; +NET "debug<7>" LOC = "F13" ; +NET "debug<8>" LOC = "D8" ; +NET "debug<9>" LOC = "A6" ; +NET "debug<10>" LOC = "D7" ; +NET "debug<11>" LOC = "A5" ; +NET "debug<12>" LOC = "B6" ; +NET "debug<13>" LOC = "A3" ; +NET "debug<14>" LOC = "A7" ; +NET "debug<15>" LOC = "A8" ; +NET "debug<16>" LOC = "B18" ; +NET "debug<17>" LOC = "C17" ; +NET "debug<18>" LOC = "H13" ; +NET "debug<19>" LOC = "D12" ; +NET "debug<20>" LOC = "H14" ; +NET "debug<21>" LOC = "C10" ; +NET "debug<22>" LOC = "D10" ; +NET "debug<23>" LOC = "C8" ; +NET "debug<24>" LOC = "D9" ; +NET "debug<25>" LOC = "C5" ; +NET "debug<26>" LOC = "A9" ; +NET "debug<27>" LOC = "B8" ; +NET "debug<28>" LOC = "A4" ; +NET "debug<29>" LOC = "C7" ; +NET "debug<30>" LOC = "C6" ; +NET "debug<31>" LOC = "D6" ; + +NET "debug_clk<0>" LOC = "A12" ; +NET "debug_clk<1>" LOC = "C12" ; + +## GPIF + +NET "IFCLK" LOC = "H21" ; +NET "FX3_EXTINT" LOC = "U20" ; + +NET "GPIF_CTL0" LOC = "V20" ; +NET "GPIF_CTL1" LOC = "T22" ; +NET "GPIF_CTL2" LOC = "R22" ; +NET "GPIF_CTL3" LOC = "U22" ; +NET "GPIF_CTL4" LOC = "P19" ; +NET "GPIF_CTL5" LOC = "N22" ; +NET "GPIF_CTL6" LOC = "T21" ; +NET "GPIF_CTL7" LOC = "V21" ; +NET "GPIF_CTL8" LOC = "K18" ; +NET "GPIF_CTL9" LOC = "R20" ; +##GPIF_CTL10 is "FPGA_CFG_DONE", defined later. +NET "GPIF_CTL11" LOC = "P22" ; +NET "GPIF_CTL12" LOC = "M20" ; + +NET "GPIF_D<0>" LOC = "T17" ; +NET "GPIF_D<1>" LOC = "U14" ; +NET "GPIF_D<2>" LOC = "U13" ; +NET "GPIF_D<3>" LOC = "AA6" ; +NET "GPIF_D<4>" LOC = "AB6" ; +NET "GPIF_D<5>" LOC = "Y3" ; +NET "GPIF_D<6>" LOC = "AB3" ; +NET "GPIF_D<7>" LOC = "AA4" ; +NET "GPIF_D<8>" LOC = "AA2" ; +NET "GPIF_D<9>" LOC = "AB2" ; +NET "GPIF_D<10>" LOC = "AB19" ; +NET "GPIF_D<11>" LOC = "AA18" ; +NET "GPIF_D<12>" LOC = "AB18" ; +NET "GPIF_D<13>" LOC = "Y13" ; +NET "GPIF_D<14>" LOC = "AA12" ; +NET "GPIF_D<15>" LOC = "AB12" ; +NET "GPIF_D<16>" LOC = "N20" ; +NET "GPIF_D<17>" LOC = "L20" ; +NET "GPIF_D<18>" LOC = "N19" ; +NET "GPIF_D<19>" LOC = "M22" ; +NET "GPIF_D<20>" LOC = "L19" ; +NET "GPIF_D<21>" LOC = "M21" ; +NET "GPIF_D<22>" LOC = "M19" ; +NET "GPIF_D<23>" LOC = "K22" ; +NET "GPIF_D<24>" LOC = "J20" ; +NET "GPIF_D<25>" LOC = "L22" ; +NET "GPIF_D<26>" LOC = "K19" ; +NET "GPIF_D<27>" LOC = "H22" ; +NET "GPIF_D<28>" LOC = "J22" ; +NET "GPIF_D<29>" LOC = "K20" ; +NET "GPIF_D<30>" LOC = "G22" ; +NET "GPIF_D<31>" LOC = "F22" ; + +## GPS + +NET "gps_lock" LOC = "Y17" ; +NET "gps_out_enable" LOC = "V22" ; +NET "gps_ref_enable" LOC = "AB13" ; +NET "gps_rxd" LOC = "AB14" ; +NET "gps_txd" LOC = "W12" ; +NET "gps_txd_nmea" LOC = "AA14" ; + +## LEDS + +NET "LED_RX1" LOC = "C22" ; +NET "LED_RX2" LOC = "L15" ; +NET "LED_TXRX1_TX" LOC = "C20" ; +NET "LED_TXRX2_RX" LOC = "D21" ; +NET "LED_TXRX1_RX" LOC = "K16" ; +NET "LED_TXRX2_TX" LOC = "D22" ; + +## Misc Hardware Control + +NET "ext_ref_enable" LOC = "Y15" ; +NET "pll_lock" LOC = "AB10" ; +NET "AUX_PWR_ON" LOC = "AA21" ; +#NET "RFUSE" LOC = "P15" ; + +## PPS + +NET "pps_fpga_out_enable" LOC = "AB15" ; +NET "PPS_IN_EXT" LOC = "AB16" ; +NET "PPS_IN_INT" LOC = "AB21" ; +NET "pps_out" LOC = "AB17" ; + +## RF Hardware Control + +NET "SFDX1_RX" LOC = "W4" ; +NET "SFDX1_TX" LOC = "T18" ; +NET "SFDX2_RX" LOC = "F18" ; +NET "SFDX2_TX" LOC = "H17" ; +NET "SRX1_RX" LOC = "Y7" ; +NET "SRX1_TX" LOC = "AA8" ; +NET "SRX2_RX" LOC = "J17" ; +NET "SRX2_TX" LOC = "F19" ; +NET "tx_bandsel_a" LOC = "N16" ; +NET "tx_bandsel_b" LOC = "M16" ; +NET "tx_enable1" LOC = "Y4" ; +NET "tx_enable2" LOC = "R19" ; +NET "rx_bandsel_a" LOC = "T20" ; +NET "rx_bandsel_b" LOC = "U19" ; +NET "rx_bandsel_c" LOC = "P20" ; + +## FPGA Config Pins + +#NET "FPGA_CFG_INIT_B" LOC = "T6" ; +#NET "FPGA_CFG_DONE" LOC = "Y22" ; +#NET "FPGA_CFG_M0" LOC = "AA22" ; +#NET "FPGA_CFG_M1" LOC = "U15" ; +#NET "FPGA_CFG_PROG_B" LOC = "AA1" ; + +## Special Pins + +#NET "VFS" LOC = "P16" ; +#NET "TMS" LOC = "C18" ; +#NET "TDO" LOC = "A19" ; +#NET "TDI" LOC = "E18" ; +#NET "TCK" LOC = "G15" ; +#NET "GND" LOC = "N15" ; diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf new file mode 100644 index 000000000..82d68aceb --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/constrs_1/imports/b200/timing.ucf @@ -0,0 +1,44 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_*" IOB = TRUE; + +# TODO not working... constraints ignored + +#constrain FX3 IO +INST "GPIF_D<*>" TNM = gpif_net_out; +INST "GPIF_D<*>" TNM = gpif_net_in; +INST "GPIF_CTL0" TNM = gpif_net_out; +INST "GPIF_CTL1" TNM = gpif_net_out; +INST "GPIF_CTL2" TNM = gpif_net_out; +INST "GPIF_CTL3" TNM = gpif_net_out; +INST "GPIF_CTL4" TNM = gpif_net_in; +INST "GPIF_CTL5" TNM = gpif_net_in; +INST "GPIF_CTL6" TNM = gpif_net_in; +INST "GPIF_CTL7" TNM = gpif_net_out; +INST "GPIF_CTL8" TNM = gpif_net_in; +INST "GPIF_CTL11" TNM = gpif_net_out; +INST "GPIF_CTL12" TNM = gpif_net_out; + +#NET "gpif_clk" TNM_NET = "TNM_gpif_clk"; +#OFFSET = OUT 5 ns AFTER "gpif_clk"; +#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %; +#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING; +#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING; diff --git a/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..b379066c6 --- /dev/null +++ b/fpga/usrp3/top/b200/planahead/planahead.srcs/sources_1/imports/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b200/sim/b200_io_tb.v b/fpga/usrp3/top/b200/sim/b200_io_tb.v new file mode 100644 index 000000000..647612a2d --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b200_io_tb.v @@ -0,0 +1,155 @@ +`timescale 1ns/1ps + + module b200_io_tb(); + + // + // Xilinx Mandatory Simulation Primitive for global signals. + // + wire GSR, GTS; + glbl glbl( ); + + // + // Test bench declarations + // + reg [7:0] count; + wire [11:0] i0 = {4'hA,count}; + wire [11:0] q0 = {4'hB,count}; + wire [11:0] i1 = {4'hC,count}; + wire [11:0] q1 = {4'hD,count}; + reg tb_clk = 0; + + // RX sample bus. + reg rx_clk = 0; // Simulated clock from AD9361 for RX sample interface, radio_clk derived from this. + reg rx_frame; + reg [11:0] rx_data; + // TX sample bus. + wire tx_clk; + wire tx_frame; + wire [11:0] tx_data; + // Internal FPGA interface(s) + reg reset = 1; + wire radio_clk; + reg mimo; + wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1; + reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1; + + + // Set tb_clk to 100MHz. + // rx_clk is half the frequency of tb_clk, and tb_clk posedges are miday between edges on the rx_clk + always #10 tb_clk = ~tb_clk; + always @(negedge tb_clk) rx_clk <= ~rx_clk; + + + b200_io dut + ( + .reset(reset), + .mimo(mimo), + + // Baseband sample interface + .radio_clk(radio_clk), + .rx_i0(rx_i0), + .rx_q0(rx_q0), + .rx_i1(rx_i1), + .rx_q1(rx_q1), + .tx_i0(tx_i0), + .tx_q0(tx_q0), + .tx_i1(tx_i1), + .tx_q1(tx_q1), + + // Catalina interface + .rx_clk(rx_clk), + .rx_frame(rx_frame), + .rx_data(rx_data), + .tx_clk(tx_clk), + .tx_frame(tx_frame), + .tx_data(tx_data) + ); + + // Internal Loopback Rx -> Tx. + always @(posedge radio_clk) + begin + tx_i0 <= rx_i0; + tx_q0 <= rx_q0; + tx_i1 <= rx_i1; + tx_q1 <= rx_q1; + end + + // + // Task's for stimulus + // + + task siso_burst; + input [7:0] len; + begin + rx_frame <= 0; + mimo <= 0; + count <= 0; + // Now give configuration a chance to perculate + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + // Now entering main stimulus loop just after rising edge of rx_clk + repeat(len) + begin + // Drive I data so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i0; + rx_frame <= 1; + // Drive Q data so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q0; + rx_frame <= 0; + // Increment test data pattern + count <= count + 1; + end // repeat (len) + @(posedge rx_clk); + @(posedge rx_clk); + end + + endtask // BURST + + + task mimo_burst; + input [7:0] len; + begin + rx_frame <= 0; + mimo <= 1; + count <= 0; + // Now give configuration a chance to perculate + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + @(posedge rx_clk); + // Now entering main stimulus loop just after rising edge of rx_clk + repeat(len) + // REMEMBER! B210 PCB markings for radio channels are swapped w.r.t AD9361's channels. + // "Ch0" as indicated here is "Ch1" inside AD9361 + begin + // Drive I data for Ch1 so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i1; + rx_frame <= 1; + // Drive Q data for Ch1 so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q1; + // Drive I data for Ch0 so that it surrounds a falling edge on rx_clk + @(posedge tb_clk); + rx_data <= i0; + rx_frame <= 0; + // Drive Q data for Ch0 so that it surrounds a rising edge on rx_clk + @(posedge tb_clk); + rx_data <= q0; + // Increment test data pattern + count <= count + 1; + end + @(posedge rx_clk); + @(posedge rx_clk); + end + endtask // MIMO_BURST + + // Pull in local simulation script here. +`include "simulation_script.v" + + +endmodule // b200_io_tb diff --git a/fpga/usrp3/top/b200/sim/b200_tb.v b/fpga/usrp3/top/b200/sim/b200_tb.v new file mode 100644 index 000000000..62037ba94 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b200_tb.v @@ -0,0 +1,213 @@ +module b200_tb (); + + wire cat_ce; + wire cat_miso; + wire cat_mosi; + wire cat_sclk; + + wire fx3_ce; + wire fx3_miso; + wire fx3_mosi; + wire fx3_sclk; + + wire pll_ce; + wire pll_mosi; + wire pll_sclk; + + // UART + wire FPGA_RXD0; + wire FPGA_TXD0; + + // Catalina Controls + wire codec_enable; + wire codec_en_agc; + wire codec_reset; + wire codec_sync; + wire codec_txrx; + wire [3:0] codec_ctrl_in; // These should be outputs + wire [7:0] codec_ctrl_out; // MUST BE INPUT + + // Catalina Data + wire codec_data_clk_p; // Clock from CAT (RX) + wire codec_fb_clk_p; // Clock to CAT (TX) + wire [11:0] rx_codec_d; + wire [11:0] tx_codec_d; + wire rx_frame_p; + wire tx_frame_p; + + wire cat_clkout_fpga; + + //always on 40MHz clock + wire codec_main_clk_p; + wire codec_main_clk_n; + + // Debug Bus + wire [31:0] debug; + wire [1:0] debug_clk; + + // GPIF; FX3 Slave FIFO + wire IFCLK; // pclk + wire FX3_EXTINT; + wire GPIF_CTL0; // n_slcs + wire GPIF_CTL1; // n_slwr + wire GPIF_CTL2; // n_sloe + wire GPIF_CTL3; // n_slrd + wire GPIF_CTL7; // n_pktend + wire GPIF_CTL4; // slfifo_flags[0] + wire GPIF_CTL5; // slfifo_flags[1] + wire GPIF_CTL6; // slfifo_flags[2] + wire GPIF_CTL8; // slfifo_flags[3] + wire GPIF_CTL11; // slfifo_addr[1] + wire GPIF_CTL12; // slfifo_addr[0] + wire [31:0] GPIF_D; + wire GPIF_CTL9; // global_reset + + // GPS + wire gps_lock; + wire gps_rxd; + wire gps_txd; + wire gps_txd_nmea; + + // LEDS + wire LED_RX1; + wire LED_RX2; + wire LED_TXRX1_RX; + wire LED_TXRX1_TX; + wire LED_TXRX2_RX; + wire LED_TXRX2_TX; + + // Misc Hardware Control + wire ref_sel; + wire pll_lock; + wire FPGA_CFG_CS; // Driven by FX3 gpio. + wire AUX_PWR_ON; // Driven by FX3 gpio. + + // PPS + wire PPS_IN_EXT; + wire PPS_IN_INT; + + // RF Hardware Control + wire SFDX1_RX; + wire SFDX1_TX; + wire SFDX2_RX; + wire SFDX2_TX; + wire SRX1_RX; + wire SRX1_TX; + wire SRX2_RX; + wire SRX2_TX; + wire tx_bandsel_a; + wire tx_bandsel_b; + wire tx_enable1; + wire tx_enable2; + wire rx_bandsel_a; + wire rx_bandsel_b; + wire rx_bandsel_c; + + + b200 b200_i1( + // SPI Interfaces + .cat_ce(), + .cat_miso(), + .cat_mosi(), + .cat_sclk(), + + .fx3_ce(), + .fx3_miso(), + .fx3_mosi(), + .fx3_sclk(), + + .pll_ce(), + .pll_mosi(), + .pll_sclk(), + + // UART + .FPGA_RXD0(), + .FPGA_TXD0(), + + // Catalina Controls + .codec_enable(), + .codec_en_agc(), + .codec_reset(), + .codec_sync(), + .codec_txrx(), + .codec_ctrl_in(), // These should be outputs + .codec_ctrl_out(), // MUST BE INPUT + + // Catalina Data + .codec_data_clk_p(), // Clock from CAT (RX) + .codec_fb_clk_p(), // Clock to CAT (TX) + .rx_codec_d(), + .tx_codec_d(), + .rx_frame_p(), + .tx_frame_p(), + + .cat_clkout_fpga(), + + //always on 40MHz clock + .codec_main_clk_p(), + .codec_main_clk_n(), + + // Debug Bus + .debug(), + .debug_clk(), + + // GPIF, FX3 Slave FIFO + .IFCLK(), // pclk + .FX3_EXTINT(), + .GPIF_CTL0(), // n_slcs + .GPIF_CTL1(), // n_slwr + .GPIF_CTL2(), // n_sloe + .GPIF_CTL3(), // n_slrd + .GPIF_CTL7(), // n_pktend + .GPIF_CTL4(), // slfifo_flags[0] + .GPIF_CTL5(), // slfifo_flags[1] + .GPIF_CTL6(), // slfifo_flags[2] + .GPIF_CTL8(), // slfifo_flags[3] + .GPIF_CTL11(), // slfifo_addr[1] + .GPIF_CTL12(), // slfifo_addr[0] + .GPIF_D(), + .GPIF_CTL9(), // global_reset + + // GPS + .gps_lock(), + .gps_rxd(), + .gps_txd(), + .gps_txd_nmea(), + + // LEDS + .LED_RX1(), + .LED_RX2(), + .LED_TXRX1_RX(), + .LED_TXRX1_TX(), + .LED_TXRX2_RX(), + .LED_TXRX2_TX(), + + // Misc Hardware Control + .ref_sel(), + .pll_lock(), + .FPGA_CFG_CS(), // Driven by FX3 gpio. + .AUX_PWR_ON(), // Driven by FX3 gpio. + + // PPS + .PPS_IN_EXT(), + .PPS_IN_INT(), + + // RF Hardware Control + .SFDX1_RX(), + .SFDX1_TX(), + .SFDX2_RX(), + .SFDX2_TX(), + .SRX1_RX(), + .SRX1_TX(), + .SRX2_RX(), + .SRX2_TX(), + .tx_bandsel_a(), + .tx_bandsel_b(), + .tx_enable1(), + .tx_enable2(), + .rx_bandsel_a(), + .rx_bandsel_b(), + .rx_bandsel_c() + ); + +endmodule // b200_tb diff --git a/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim new file mode 100755 index 000000000..dd9215934 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../lib/axi \ + --sourcelibdir ../../../lib/fifo \ + --sourcelibdir ../../../lib/control \ + --sourcelibdir ../../../top/b200/coregen \ + --sourcelibdir ../../../top/b200 \ + --sourcelibdir ../../../lib/timing \ + --sourcelibdir ../../../lib/vita \ + --sourcelibdir ../../../lib/packet_proc \ + --sourcelibdir ../../../lib/dsp \ + --sourcelibdir ../../../lib/wishbone \ + --sourcelibdir ../../../lib/gpif2 \ + ../../../top/b200/b200_tb.v + + + +fuse work.b200_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_tb.exe + +# run the simulation scrip +./b200_tb.exe # -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg new file mode 100644 index 000000000..4ecabdecf --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/mimo.wcfg @@ -0,0 +1,112 @@ + + + + + + + + + + + + + + + Test Bench + label + + tb_clk + tb_clk + + + reset + reset + + + mimo + mimo + + + + RX + label + + rx_clk + rx_clk + + + rx_frame + rx_frame + + + rx_data[11:0] + rx_data[11:0] + HEXRADIX + + + + TX + label + + tx_clk + tx_clk + + + tx_frame + tx_frame + + + tx_data[11:0] + tx_data[11:0] + HEXRADIX + + + + Internal + label + + radio_clk + radio_clk + + + rx_i0[11:0] + rx_i0[11:0] + HEXRADIX + + + rx_q0[11:0] + rx_q0[11:0] + HEXRADIX + + + rx_i1[11:0] + rx_i1[11:0] + HEXRADIX + + + rx_q1[11:0] + rx_q1[11:0] + HEXRADIX + + + tx_i0[11:0] + tx_i0[11:0] + HEXRADIX + + + tx_q0[11:0] + tx_q0[11:0] + HEXRADIX + + + tx_i1[11:0] + tx_i1[11:0] + HEXRADIX + + + tx_q1[11:0] + tx_q1[11:0] + HEXRADIX + + + diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v new file mode 100644 index 000000000..04e9079e1 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/mimo/simulation_script.v @@ -0,0 +1,14 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + + repeat(10) @(posedge rx_clk); + + mimo_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim new file mode 100755 index 000000000..dc0ec02b7 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/run_isim @@ -0,0 +1,22 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v + +# usrp3/top/b200/sim/sim_b200_io/siso +vlogcomp -work work --sourcelibext .v \ + --sourcelibdir ../../../../../lib/axi \ + --sourcelibdir ../../../../../lib/fifo \ + --sourcelibdir ../../../../../lib/control \ + --sourcelibdir ../../../coregen \ + --sourcelibdir ../../../ \ + --sourcelibdir ../../../../../lib/timing \ + --sourcelibdir ../../../../../lib/vita \ + --sourcelibdir ../../../../../lib/packet_proc \ + --sourcelibdir ../../../../../lib/dsp \ + --sourcelibdir ../../../../../lib/wishbone \ + --sourcelibdir ../../../../../lib/gpif2 \ + --sourcelibdir ../../../../../lib/io \ + ../../b200_io_tb.v + +fuse work.b200_io_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o b200_io_tb.exe + +# run the simulation scrip +./b200_io_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v new file mode 100644 index 000000000..ad2e7fc57 --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/simulation_script.v @@ -0,0 +1,13 @@ + + initial + begin + reset <= 1; + mimo <= 0; + repeat(10) @(posedge rx_clk); + reset <= 0; + repeat(10) @(posedge rx_clk); + + siso_burst(20); + repeat(10) @(posedge rx_clk); + $finish; + end diff --git a/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg new file mode 100644 index 000000000..7ef57498f --- /dev/null +++ b/fpga/usrp3/top/b200/sim/sim_b200_io/siso/siso.wcfg @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + Test Bench + label + + tb_clk + tb_clk + + + reset + reset + + + mimo + mimo + + + + RX + label + + rx_clk + rx_clk + + + rx_frame + rx_frame + + + rx_data[11:0] + rx_data[11:0] + HEXRADIX + + + + TX + label + + tx_clk + tx_clk + + + tx_frame + tx_frame + + + tx_data[11:0] + tx_data[11:0] + HEXRADIX + + + diff --git a/fpga/usrp3/top/b200/timing.ucf b/fpga/usrp3/top/b200/timing.ucf new file mode 100644 index 000000000..6264449da --- /dev/null +++ b/fpga/usrp3/top/b200/timing.ucf @@ -0,0 +1,46 @@ + +# codec_main_clk is 40 MHz main tcxo clock +NET "codec_main_clk*" TNM_NET = "codec_main_clk"; +TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %; + + +# IFCLK is 100 MHz GPIF clock +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %; + + +# codec_data_clk is the data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p"; +TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %; + +#always use IOB for GPIF pins for awesome timing +INST "GPIF_*" IOB = TRUE; + +#low speed misc output group +INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain +INST "SRX*" TNM = radio_misc_out; # Radio Clk domain +INST "LED_*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain +INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain +INST "ref_sel" TNM = ls_misc_out; # Bus clk domain +INST "pll_ce" TNM = ls_misc_out; # Bus clk domain +INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial +#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial +INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I) +INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "gps_*" TNM = ls_misc_out; # Bus clk domain +#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED + +#constrain the misc IOs to the clocks +NET "gpif_clk" TNM_NET = "gpif_clk"; +TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %; +# These next 2 constarints have never worked...either fix them or remove them. Probably need a virtual clock to make them work. +#TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING; +#TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING; + diff --git a/fpga/usrp3/top/b2xxmini/.gitignore b/fpga/usrp3/top/b2xxmini/.gitignore new file mode 100644 index 000000000..f61be8ab7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/.gitignore @@ -0,0 +1,7 @@ +build* +catcap_tb +catgen_tb +fuse* +isim* +_impact* +coregen.log diff --git a/fpga/usrp3/top/b2xxmini/Makefile b/fpga/usrp3/top/b2xxmini/Makefile new file mode 100644 index 000000000..9031b17db --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/Makefile @@ -0,0 +1,91 @@ +# +# Copyright 2015 Ettus Research LLC +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP B2XXXmini FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga.bit: Configuration bitstream with header +## build/usrp__fpga.bin: Configuration bitstream without header +## build/usrp__fpga.syr: Xilinx system report +## build/usrp__fpga.twr: Xilinx timing report + +print_report = \ + echo "========================================================================"; \ + cat $(1)/b205.syr | grep "Device utilization summary:" -A 30; \ + echo "========================================================================"; \ + echo "Timing Summary:\n"; \ + cat $(1)/b205.twr | grep constraint | grep met | grep -v "*"; \ + echo "========================================================================"; + +# pre_build($1=Device) +ifeq ($(EXPORT_ONLY),1) + pre_build = @test -s build-$(1)/b205.bit || { echo "EXPORT_ONLY requires the project in build-$(1) to be fully built."; false; } +else + pre_build = @echo "ISE Version: $(shell xtclsh -h | head -n1)" +endif + +# ise_build($1=Device, $2=Definitions) +ifeq ($(PROJECT_ONLY),1) + ise_build = make -f Makefile.b205.inc proj NAME=$@ DEVICE=$1 +else ifeq ($(EXPORT_ONLY),1) + ise_build = @echo "Skipping ISE build and exporting pre-built files."; +else + ise_build = make -f Makefile.b205.inc bin NAME=$@ DEVICE=$1 +endif + +# post_build($1=Device) +ifeq ($(PROJECT_ONLY),1) + post_build = \ + @echo "Generated $(shell pwd)/build-$(1)/b205.xise"; \ + echo "\nProject Generation DONE ... $(1)\n"; +else + post_build = \ + @$(call print_report,build-$(1)) \ + mkdir -p build; \ + echo "Exporting bitstream files..."; \ + cp build-$(1)/b205.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bin; \ + cp build-$(1)/b205.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga.bit; \ + echo "Exporting logs..."; \ + cp build-$(1)/b205.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.syr; \ + cp build-$(1)/b205.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga.twr; \ + echo "\nBuild DONE ... $(1)\n"; +endif + +## +##Supported Targets +##----------------- + +all: B200mini B205mini ##(Default target) + +B200mini: ##Build USRP B200mini design. + $(call pre_build,B200mini) + $(call ise_build,XC6SLX75) + $(call post_build,B200mini) + +B205mini: ##Build USRP B205mini design. + $(call pre_build,B205mini) + $(call ise_build,XC6SLX150) + $(call post_build,B205mini) + +clean: ##Clean up all build output. + rm -rf build-* + rm -rf build + +help: ## Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##PROJECT_ONLY=1 Only create a Xilinx project for the specified target(s). +## Useful for use with the ISE GUI. +##EXPORT_ONLY=1 Export build targets from a GUI build to the build directory. +## Requires the project in build-*_* to be built. + +.PHONY: all clean help B200mini B205mini diff --git a/fpga/usrp3/top/b2xxmini/Makefile.b205.inc b/fpga/usrp3/top/b2xxmini/Makefile.b205.inc new file mode 100644 index 000000000..a1da7f22f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/Makefile.b205.inc @@ -0,0 +1,129 @@ +# +# Copyright 2012-2013 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE := b205 +BUILD_DIR := build-$(NAME)/ +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +include ../Makefile.common +include ../../lib/gpif2/Makefile.srcs +include ../../lib/fifo/Makefile.srcs +include ../../lib/fifo_200/Makefile.srcs +include ../../lib/dsp/Makefile.srcs +include ../../lib/control/Makefile.srcs +include ../../lib/control_200/Makefile.srcs +include ../../lib/packet_proc/Makefile.srcs +include ../../lib/packet_proc_200/Makefile.srcs +include ../../lib/timing/Makefile.srcs +include ../../lib/vita_200/Makefile.srcs +include ../../lib/wishbone/Makefile.srcs +include ../../lib/axi/Makefile.srcs +include ../../lib/radio_200/Makefile.srcs +include coregen_dsp/Makefile.srcs + + +B205_COREGEN_SRCS = \ +coregen/b205_clk_gen.v \ +coregen/fifo_4k_2clk.xco \ +coregen/fifo_short_2clk.xco \ +coregen/chipscope_icon.xco \ +coregen/chipscope_ila.xco + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan6" \ +device $(DEVICE) \ +package csg484 \ +speed -3 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +b205.v \ +b205_ref_pll.v \ +b205_core.v \ +b205_io.v \ +b205.ucf \ +timing.ucf \ +../b200/S6CLK2PIN.v \ +$(B205_COREGEN_SRCS) + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) $(FIFO_200_SRCS) \ +$(CONTROL_LIB_SRCS) $(CONTROL_LIB_200_SRCS) $(SDR_LIB_SRCS) \ +$(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) \ +$(GPIF2_SRCS) $(PACKET_PROC_SRCS) $(PACKET_PROC_200_SRCS) \ +$(WISHBONE_SRCS) \ +$(TIMING_SRCS) \ +$(DSP_SRCS) \ +$(VITA_200_SRCS) \ +$(AXI_SRCS) \ +$(RADIO_200_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(COREGEN_DSP_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "SPARTAN6=1 $(EXTRA_DEFS) $(CUSTOM_DEFS)" \ +"Other XST Command Line Options" "-loop_iteration_limit 16385" + +#"Number of Clock Buffers" 8 \ + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Unused IOB Pins" "Pull Up" + +#"Configuration Rate" 6 \ +#"Enable Outputs (Output Events)" 6 \ + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp3/top/b2xxmini/b205.ucf b/fpga/usrp3/top/b2xxmini/b205.ucf new file mode 100644 index 000000000..9d1b89fd8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/b205.ucf @@ -0,0 +1,157 @@ + +#### FX3 Lines ############################################################## +# GPIF Data lines +NET "FX3_DQ<0>" LOC = "T22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<1>" LOC = "T21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<2>" LOC = "M19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<3>" LOC = "R22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<4>" LOC = "R20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<5>" LOC = "R19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<6>" LOC = "P20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<7>" LOC = "N19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<8>" LOC = "P22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<9>" LOC = "N20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<10>" LOC = "P21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<11>" LOC = "M21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<12>" LOC = "N22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<13>" LOC = "L22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<14>" LOC = "M22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<15>" LOC = "P19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<16>" LOC = "D21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<17>" LOC = "F22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<18>" LOC = "C22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<19>" LOC = "D22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<20>" LOC = "E22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<21>" LOC = "B22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<22>" LOC = "B21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<23>" LOC = "F20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<24>" LOC = "G19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<25>" LOC = "D20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<26>" LOC = "E20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<27>" LOC = "D19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<28>" LOC = "J19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<29>" LOC = "C20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<30>" LOC = "F19" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data +NET "FX3_DQ<31>" LOC = "C18" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # FX3 Parallel Data + +NET "FX3_PCLK" LOC = "H20" | IOSTANDARD = LVCMOS18 | DRIVE = 6 | SLEW = SLOW; # FX3 Data Synchronization Clock, called IFCLK in B200 + +# GPIF Control Lines +NET "FX3_CTL0" LOC = "M20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLCSn +NET "FX3_CTL1" LOC = "J22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLWRn +NET "FX3_CTL2" LOC = "J21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLOEn +NET "FX3_CTL3" LOC = "K22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # SLRDn +NET "FX3_CTL4" LOC = "M18" | IOSTANDARD = LVCMOS18 ; # FLAG_A +NET "FX3_CTL5" LOC = "L19" | IOSTANDARD = LVCMOS18 ; # FLAG_B +NET "FX3_CTL6" LOC = "H22" | IOSTANDARD = LVCMOS18 ; # +NET "FX3_CTL7" LOC = "L20" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # PKTENDn +NET "FX3_CTL8" LOC = "K19" | IOSTANDARD = LVCMOS18 ; # +NET "FX3_CTL9" LOC = "K20" | IOSTANDARD = LVCMOS18 ; # +##FX3_CTL10 is not for general signaling +NET "FX3_CTL11" LOC = "H21" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # A1 +NET "FX3_CTL12" LOC = "G22" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # A0 + + +#### AD9364 ################################################################# +NET "CAT_RESETn" LOC = "T3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Global Reset +NET "CAT_EN_AGC" LOC = "AA4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver AGC Enable +NET "CAT_EN" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Globe Enable +NET "CAT_TXnRX" LOC = "Y4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Globe TX and RX control + +# SPI +NET "CAT_SPI_EN" LOC = "T4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Latch +NET "CAT_SPI_CLK" LOC = "Y3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Serial Clock +NET "CAT_SPI_DI" LOC = "AA2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Controller SPI Data In +NET "CAT_SPI_DO" LOC = "U4" | IOSTANDARD = LVCMOS18 | PULLUP; # Transceiver Controller SPI Data Out + +# Control Lines +NET "CAT_CTL_OUT<0>" LOC = "D2" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<1>" LOC = "AB4" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<2>" LOC = "AB3" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<3>" LOC = "K3" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<4>" LOC = "AB2" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<5>" LOC = "T7" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<6>" LOC = "U8" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_OUT<7>" LOC = "W4" | IOSTANDARD = LVCMOS18 ; # +NET "CAT_CTL_IN<0>" LOC = "H5" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # +NET "CAT_CTL_IN<1>" LOC = "H3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # +NET "CAT_CTL_IN<2>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # +NET "CAT_CTL_IN<3>" LOC = "D1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # + +# Rx Bus +NET "CAT_P0_D<0>" LOC = "H1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P0_D<1>" LOC = "H2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P0_D<2>" LOC = "G1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<3>" LOC = "G3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<4>" LOC = "F1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<5>" LOC = "F2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<6>" LOC = "E1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<7>" LOC = "E3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LT. +NET "CAT_P0_D<8>" LOC = "L1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P0_D<9>" LOC = "L3" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P0_D<10>" LOC = "M1" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P0_D<11>" LOC = "M2" | IOSTANDARD = LVCMOS18; # Transceiver Parallel Data. Bank3 LB. + +# Tx Bus +NET "CAT_P1_D<0>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<1>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<2>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<3>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<4>" LOC = "V1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<5>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<7>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<8>" LOC = "Y1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<9>" LOC = "Y2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<10>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. +NET "CAT_P1_D<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Transceiver Parallel Data. Bank3 LB. + +# Frame syncs +NET "CAT_TX_FR_N" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Bank3 LB. +NET "CAT_TX_FR_P" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Bank3 LB. +#NET "CAT_RX_FR_N" LOC = "P1" | IOSTANDARD = LVCMOS18; # Bank3 LB. +NET "CAT_RX_FR_P" LOC = "P2" | IOSTANDARD = LVCMOS18; # Bank3 LB. + +# Clocks ('N' clock lines are currently unused) +#NET "CAT_DCLK_N" LOC = "P3" | IOSTANDARD = LVCMOS18; # Data Clock +NET "CAT_DCLK_P" LOC = "N4" | IOSTANDARD = LVCMOS18; # Data Clock +NET "CAT_FBCLK_P" LOC = "J3" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Clock to AD9364. Bank3 LB. +NET "CAT_FBCLK_N" LOC = "J1" | IOSTANDARD = LVCMOS18 | DRIVE = 2 | SLEW = SLOW; # Clock to AD9364. Bank3 LB. + +#### Peripherals ############################################################ +# Radio Switchery +NET "cFE_SEL_TRX_TX" LOC = "A5" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # TRX Switch, high to enable TX path (Always on for Duplex) (high for now) +NET "cFE_SEL_TRX_RX" LOC = "A6" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # TRX Switch, high to enable RX path (Always off for Duplex) (low for now) +NET "cFE_SEL_RX_TRX" LOC = "B3" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # high to enable RX path to TRX switch (Always off for Duplex) (low for now) +NET "cFE_SEL_RX_RX2" LOC = "C5" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # high to enable RX path to RX2 port (Always on for Duplex) (high for now) +NET "cTXDRV_PWEN" LOC = "A4" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW; # high to enable power to TX power amplifier (high for now) + +# LEDs R: 5mA / G: 1.25mA / B: 2.5mA (the mcd is equalized with this number), set by resistor already, with LVTTL logic (3.3V) +NET "cLED_TRX_G" LOC = "A7" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED green +NET "cLED_TRX_B" LOC = "B6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED blue +NET "cLED_TRX_R" LOC = "C6" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on TRX port LED red +NET "cLED_RX2_G" LOC = "A9" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED green +NET "cLED_RX2_B" LOC = "B8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED blue +NET "cLED_RX2_R" LOC = "A8" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on RX2 port LED red +NET "cLED_S0" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on S0 port LED red +NET "cLED_S1" LOC = "A10" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW; # low to turn on S1 port LED red + + +# Clocking +NET "CLK_40MHz_FPGA" LOC = "AA10" | IOSTANDARD = LVCMOS18; # 40MHz VCTCXO clock feed back +NET "PPS_IN" LOC = "B12" | IOSTANDARD = LVCMOS33; # Pulse per second input (external) +NET "CLKIN_10MHz" LOC = "E6" | IOSTANDARD = LVCMOS18; # 10MHz from external source +NET "CLKIN_10MHz_REQ" LOC = "E5" | IOSTANDARD = LVCMOS18; # select 10MHz from external source +NET "CLK_40M_DAC_nSYNC" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial frame/data latch (high for now) +NET "CLK_40M_DAC_SCLK" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial data clock (low for now) +NET "CLK_40M_DAC_DIN" LOC = "C16" | IOSTANDARD = LVCMOS33 | DRIVE = 2 | SLEW = SLOW; # 40MHz VCTCXO triming DAC serial data (low for now) + +## GPIO bus +NET "fp_gpio<0>" LOC = "A18" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<1>" LOC = "A17" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<2>" LOC = "B16" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<3>" LOC = "B18" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<4>" LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<5>" LOC = "A15" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<6>" LOC = "A16" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "fp_gpio<7>" LOC = "A13" | IOSTANDARD = LVCMOS33 | PULLUP; diff --git a/fpga/usrp3/top/b2xxmini/b205.v b/fpga/usrp3/top/b2xxmini/b205.v new file mode 100644 index 000000000..3b95521c4 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/b205.v @@ -0,0 +1,298 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +/*********************************************************** + * B205 Module Declaration + **********************************************************/ +module b205 ( + // AD9364 - SPI Interface: + output CAT_SPI_EN, // Enable + input CAT_SPI_DO, // MISO + output CAT_SPI_DI, // MOSI + output CAT_SPI_CLK, // SPI Clk + + // AD9364 - Control: + output CAT_EN, + output CAT_EN_AGC, + output CAT_RESETn, + output CAT_TXnRX, + output [3:0] CAT_CTL_IN, // These should be outputs + input [7:0] CAT_CTL_OUT, // MUST BE INPUT + + // AD9364 - Data: + input CAT_DCLK_P, // Clock from AD9364 (RX) + output CAT_FBCLK_P, // Clock to AD9364 (TX) + output CAT_FBCLK_N, + input [11:0] CAT_P0_D, // RX data is on Port 0 + output [11:0] CAT_P1_D, // TX data is on Port 1 + input CAT_RX_FR_P, + output CAT_TX_FR_P, + output CAT_TX_FR_N, + + // AD9364 - Always on 40MHz clock: + input CLK_40MHz_FPGA, + + // GPIF, FX3 Slave FIFO + output FX3_PCLK, // pclk + output FX3_CTL0, // n_slcs + output FX3_CTL1, // n_slwr + output FX3_CTL2, // n_sloe + output FX3_CTL3, // n_slrd + output FX3_CTL7, // n_pktend + input FX3_CTL4, // slfifo_flags[0] + input FX3_CTL5, // slfifo_flags[1] + input FX3_CTL6, // Serial settings bus from FX3. SDA + input FX3_CTL8, // Serial settings bus from FX3. SCL + output FX3_CTL11, // slfifo_addr[1] + output FX3_CTL12, // slfifo_addr[0] + inout [31:0] FX3_DQ, + input FX3_CTL9, // global_reset + + // LEDs + output cLED_TRX_G, + output cLED_TRX_B, + output cLED_TRX_R, + output cLED_RX2_G, + output cLED_RX2_B, + output cLED_RX2_R, + output cLED_S0, + output cLED_S1, + + // GPIO + inout [7:0] fp_gpio, + + // PPS or 10 MHz (need to choose from SW) + input PPS_IN, + input CLKIN_10MHz, + output CLKIN_10MHz_REQ, + + // Clock disciplining / AD5662 controls + output CLK_40M_DAC_nSYNC, + output CLK_40M_DAC_SCLK, + output CLK_40M_DAC_DIN, + + // RF Hardware Control + output cFE_SEL_TRX_TX, // Select TX/RX port for Tx + output cFE_SEL_TRX_RX, // Select TX/RX port for Rx + output cFE_SEL_RX_TRX, // Select TX/RX port for Rx + output cFE_SEL_RX_RX2, // Select RX2 port for Rx + output cTXDRV_PWEN // Tx PA enable + + ); + + wire reset_global = FX3_CTL9; + + /////////////////////////////////////////////////////////////////////// + // generate clocks from always on codec main clk + /////////////////////////////////////////////////////////////////////// + wire bus_clk, radio_clk; + wire locked; + wire int_40mhz; + wire ref_pll_clk; + b205_clk_gen gen_clks + ( + .CLK_IN1_40(CLK_40MHz_FPGA), // No differential input! + .CLK_OUT1_40_int(int_40mhz), .CLK_OUT2_100_bus(bus_clk), .CLK_OUT3_200_ref_pll(ref_pll_clk), + .RESET(reset_global), .LOCKED(locked) + ); + + //hold-off logic for clocks ready + reg [15:0] clocks_ready_count; + reg clocks_ready; + always @(posedge bus_clk or posedge reset_global or negedge locked) begin + if (reset_global | !locked) begin + clocks_ready_count <= 16'b0; + clocks_ready <= 1'b0; + end + else if (!clocks_ready) begin + clocks_ready_count <= clocks_ready_count + 1'b1; + clocks_ready <= (clocks_ready_count == 16'hffff); + end + end + + /////////////////////////////////////////////////////////////////////// + // drive output clocks + /////////////////////////////////////////////////////////////////////// + ODDR2 #( + .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1" + .INIT(1'b0), // output to 1'b0 or 1'b1 + .SRTYPE("ASYNC") // set/reset "SYNC" or "ASYNC" + ) + ODDR2_S6CLK2PIN + ( + .Q(FX3_PCLK), // 1-bit DDR output data + .C0(bus_clk), // 1-bit clock input + .C1(~bus_clk), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b1), // 1-bit data input (associated with C0) + .D1(1'b0), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) // 1-bit set input + ); + + /////////////////////////////////////////////////////////////////////// + // Create sync reset signals + /////////////////////////////////////////////////////////////////////// + wire bus_rst, ref_pll_rst, radio_rst; + reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); + reset_sync ref_pll_sync(.clk(ref_pll_clk), .reset_in(!clocks_ready), .reset_out(ref_pll_rst)); + reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst)); + + /////////////////////////////////////////////////////////////////////// + // reference clock PLL + /////////////////////////////////////////////////////////////////////// + wire ref_sel; + wire ext_ref_is_pps; + wire ext_ref_locked; + wire ext_ref = ext_ref_is_pps ? PPS_IN : ref_sel ? CLKIN_10MHz : 1'b0; + b205_ref_pll ref_pll + ( + .reset(ref_pll_rst), + .clk(ref_pll_clk), + .refclk(int_40mhz), + .ref(ext_ref), + .locked(ext_ref_locked), + .sclk(CLK_40M_DAC_SCLK), + .mosi(CLK_40M_DAC_DIN), + .sync_n(CLK_40M_DAC_nSYNC) + ); + assign CLKIN_10MHz_REQ = ref_sel; + + /////////////////////////////////////////////////////////////////////// + // AD9364 I/O + /////////////////////////////////////////////////////////////////////// + wire [31:0] rx_data; + wire [31:0] tx_data; + + b205_io b205_io_i0 + ( + .reset(reset_global), + // Baseband sample interface + .radio_clk(radio_clk), + .rx_i0(rx_data[31:20]), + .rx_q0(rx_data[15:4]), + .tx_i0(tx_data[31:20]), + .tx_q0(tx_data[15:4]), + // Catalina interface + .rx_clk(CAT_DCLK_P), + .rx_frame(CAT_RX_FR_P), + .rx_data(CAT_P0_D), + + .tx_clk(CAT_FBCLK_P), + .tx_frame(CAT_TX_FR_P), + .tx_data(CAT_P1_D) + ); + + assign {rx_data[19:16],rx_data[3:0]} = 8'h0; + assign CAT_FBCLK_N = 1'b0; + assign CAT_TX_FR_N = 1'b0; + + /////////////////////////////////////////////////////////////////////// + // SPI connections + /////////////////////////////////////////////////////////////////////// + wire mosi, miso, sclk; + wire [7:0] sen; + + // AD9364 Slave (it's the only slave for B205) + assign CAT_SPI_EN = sen[0]; + assign CAT_SPI_DI = ~sen[0] & mosi; + assign CAT_SPI_CLK = ~sen[0] & sclk; + assign miso = CAT_SPI_DO; + + /////////////////////////////////////////////////////////////////////// + // bus signals + /////////////////////////////////////////////////////////////////////// + wire [63:0] ctrl_tdata, resp_tdata, rx_tdata, tx_tdata; + wire ctrl_tlast, resp_tlast, rx_tlast, tx_tlast; + wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid; + wire ctrl_tready, resp_tready, rx_tready, tx_tready; + + /////////////////////////////////////////////////////////////////////// + // frontend assignments + /////////////////////////////////////////////////////////////////////// + wire [7:0] fe_gpio_out; + reg [7:0] fe_gpio_reg; + + //Register in IOB + always @(posedge radio_clk) + fe_gpio_reg <= fe_gpio_out; + + assign {cTXDRV_PWEN, cFE_SEL_RX_RX2, cFE_SEL_TRX_TX, cFE_SEL_RX_TRX, cFE_SEL_TRX_RX} = fe_gpio_reg[7:3]; + assign cLED_TRX_R = ~fe_gpio_reg[0]; + assign cLED_TRX_G = ~fe_gpio_reg[1]; + assign cLED_TRX_B = 1'b1; + assign cLED_RX2_R = 1'b1; + assign cLED_RX2_G = ~fe_gpio_reg[2]; + assign cLED_RX2_B = 1'b1; + assign cLED_S0 = ~ext_ref_locked; + assign cLED_S1 = ~(ext_ref); + + wire [31:0] misc_outs; + reg [31:0] misc_outs_r; + always @(posedge bus_clk) misc_outs_r <= misc_outs; //register misc ios to ease routing to flop + assign ref_sel = misc_outs_r[0]; + + wire codec_arst = misc_outs_r[2]; + + assign CAT_CTL_IN = 4'b1; + assign CAT_EN_AGC = 1'b1; + assign CAT_TXnRX = 1'b1; + assign CAT_EN = 1'b1; + assign CAT_RESETn = ~codec_arst; // Codec Reset // RESETB // Operates active-low + + /////////////////////////////////////////////////////////////////////// + // b205 core + /////////////////////////////////////////////////////////////////////// + wire [7:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr; + b205_core #(.EXTRA_BUFF_SIZE(12)) b205_core + ( + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx0(rx_data), + .tx0(tx_data), + .fe_gpio_out(fe_gpio_out), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + .ext_ref_is_pps(ext_ref_is_pps), + .pps_ext(PPS_IN), + + .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso), + .rb_misc({31'b0,ext_ref_locked}), .misc_outs(misc_outs), + + .lock_signals(CAT_CTL_OUT[7:6]), + + .debug() + ); + + gpio_atr_io #(.WIDTH(8)) gpio_atr_io_inst ( + .clk(radio_clk), .gpio_pins(fp_gpio), + .gpio_ddr(fp_gpio_ddr), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in) + ); + + /////////////////////////////////////////////////////////////////////// + // GPIF2 + /////////////////////////////////////////////////////////////////////// + gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(13), .DATA_TX_FIFO_SIZE(13)) slave_fifo32 + ( + .gpif_clk(bus_clk), .gpif_rst(bus_rst), .gpif_enb(1'b1), + .gpif_ctl({FX3_CTL8, FX3_CTL6, FX3_CTL5, FX3_CTL4}), .fifoadr({FX3_CTL11, FX3_CTL12}), + .slwr(FX3_CTL1), .sloe(FX3_CTL2), .slcs(FX3_CTL0), .slrd(FX3_CTL3), .pktend(FX3_CTL7), + .gpif_d(FX3_DQ), + + .fifo_clk(bus_clk), .fifo_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready), + .resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready), + + .debug() + ); + +endmodule // B205 diff --git a/fpga/usrp3/top/b2xxmini/b205_core.v b/fpga/usrp3/top/b2xxmini/b205_core.v new file mode 100644 index 000000000..d78ff374c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/b205_core.v @@ -0,0 +1,250 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + + +/*********************************************************** + * B205 Core Guts + **********************************************************/ +module b205_core +#( + parameter R0_CTRL_SID = 8'h10, + parameter U0_CTRL_SID = 8'h30, + parameter L0_CTRL_SID = 8'h40, + parameter R0_DATA_SID = 8'h50, + parameter R1_DATA_SID = 8'h60, + parameter DEMUX_SID_MASK = 8'hf0, + parameter EXTRA_BUFF_SIZE = 0, + parameter RADIO_FIFO_SIZE = 11, + parameter SAMPLE_FIFO_SIZE = 11 + +) +( + //////////////////////////////////////////////////////////////////// + // bus interfaces + //////////////////////////////////////////////////////////////////// + input bus_clk, + input bus_rst, + + input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, + output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, + input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready, + output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready, + + //////////////////////////////////////////////////////////////////// + // radio interfaces + //////////////////////////////////////////////////////////////////// + input radio_clk, + input radio_rst, + + input [31:0] rx0, + output [31:0] tx0, + output [7:0] fe_gpio_out, + input [7:0] fp_gpio_in, output [7:0] fp_gpio_out, output [7:0] fp_gpio_ddr, + output ext_ref_is_pps, + input pps_ext, + + //////////////////////////////////////////////////////////////////// + // core interfaces + //////////////////////////////////////////////////////////////////// + output [7:0] sen, output sclk, output mosi, input miso, + input [31:0] rb_misc, + output [31:0] misc_outs, + + //////////////////////////////////////////////////////////////////// + // fe lock signals + //////////////////////////////////////////////////////////////////// + input [1:0] lock_signals, + + //////////////////////////////////////////////////////////////////// + // debug signals + //////////////////////////////////////////////////////////////////// + output [63:0] debug +); + localparam SR_CORE_SPI = 8'd8; + localparam SR_CORE_MISC = 8'd16; + localparam SR_CORE_COMPAT = 8'd24; + localparam SR_CORE_READBACK = 8'd32; + localparam SR_CORE_GPSDO_ST = 8'd40; + localparam SR_CORE_SYNC = 8'd48; + localparam COMPAT_MAJOR = 16'h0007; + localparam COMPAT_MINOR = 16'h0000; + + reg [1:0] lock_state; + reg [1:0] lock_state_r; + + always @(posedge bus_clk) + if (bus_rst) + {lock_state_r, lock_state} <= 4'h0; + else + {lock_state_r, lock_state} <= {lock_state, lock_signals}; + + + /******************************************************************* + * PPS Timing stuff + ******************************************************************/ + + // Generate an internal PPS signal + wire int_pps; + pps_generator #(.CLK_FREQ(100000000)) pps_gen + (.clk(bus_clk), .pps(int_pps)); + + // Flop PPS signals into radio clock domain + reg [1:0] ext_pps_del, int_pps_del; + always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext}; + always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps}; + + // PPS mux + wire [1:0] pps_select; + wire pps = (pps_select == 2'b01)? ext_pps_del[1] : + (pps_select == 2'b10)? int_pps_del[1] : + 1'b0; + assign ext_ref_is_pps = (pps_select == 2'b01); + + /******************************************************************* + * Response mux Routing logic + ******************************************************************/ + wire [63:0] r0_resp_tdata; wire r0_resp_tlast, r0_resp_tvalid, r0_resp_tready; + wire [63:0] l0_resp_tdata; wire l0_resp_tlast, l0_resp_tvalid, l0_resp_tready; + + axi_mux4 #(.WIDTH(64), .BUFFER(1)) mux_for_resp + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp_tready), + .i1_tdata(l0_resp_tdata), .i1_tlast(l0_resp_tlast), .i1_tvalid(l0_resp_tvalid), .i1_tready(l0_resp_tready), + .i2_tdata(64'd0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), + .i3_tdata(64'd0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata(resp_tdata), .o_tlast(resp_tlast), .o_tvalid(resp_tvalid), .o_tready(resp_tready) + ); + + /******************************************************************* + * Control demux Routing logic + ******************************************************************/ + wire [63:0] r0_ctrl_tdata; wire r0_ctrl_tlast, r0_ctrl_tvalid, r0_ctrl_tready; + wire [63:0] l0_ctrl_tdata; wire l0_ctrl_tlast, l0_ctrl_tvalid, l0_ctrl_tready; + + wire [63:0] ctrl_hdr; + wire [1:0] ctrl_dst = + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == R0_CTRL_SID)? 0 : ( + ((ctrl_hdr[7:0] & DEMUX_SID_MASK) == L0_CTRL_SID)? 1 : ( + 3)); + axi_demux4 #(.ACTIVE_CHAN(4'b1111), .WIDTH(64), .BUFFER(1)) demux_for_ctrl + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .header(ctrl_hdr), .dest(ctrl_dst), + .i_tdata(ctrl_tdata), .i_tlast(ctrl_tlast), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), + .o0_tdata(r0_ctrl_tdata), .o0_tlast(r0_ctrl_tlast), .o0_tvalid(r0_ctrl_tvalid), .o0_tready(r0_ctrl_tready), + .o1_tdata(l0_ctrl_tdata), .o1_tlast(l0_ctrl_tlast), .o1_tvalid(l0_ctrl_tvalid), .o1_tready(l0_ctrl_tready), + .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), + .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1) + ); + + /******************************************************************* + * Misc controls + ******************************************************************/ + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire spi_ready; + wire [31:0] spi_readback; + + wire [1:0] rb_addr; + reg [63:0] rb_data; + + wire [63:0] l0i_ctrl_tdata; wire l0i_ctrl_tlast, l0i_ctrl_tvalid, l0i_ctrl_tready; + + wire time_sync, time_sync_r; + + synchronizer time_sync_synchronizer + (.clk(radio_clk), .rst(radio_rst), .in(time_sync), .out(time_sync_r)); + + axi_fifo #(.WIDTH(65), .SIZE(0)) radio_ctrl_proc_timing_fifo + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({l0_ctrl_tlast, l0_ctrl_tdata}), .i_tvalid(l0_ctrl_tvalid), .i_tready(l0_ctrl_tready), .space(), + .o_tdata({l0i_ctrl_tlast, l0i_ctrl_tdata}), .o_tvalid(l0i_ctrl_tvalid), .o_tready(l0i_ctrl_tready), .occupied() + ); + + radio_ctrl_proc radio_ctrl_proc + ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .ctrl_tdata(l0i_ctrl_tdata), .ctrl_tlast(l0i_ctrl_tlast), .ctrl_tvalid(l0i_ctrl_tvalid), .ctrl_tready(l0i_ctrl_tready), + .resp_tdata(l0_resp_tdata), .resp_tlast(l0_resp_tlast), .resp_tvalid(l0_resp_tvalid), .resp_tready(l0_resp_tready), + .vita_time(64'b0), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .ready(spi_ready), .readback(rb_data), + .debug() + ); + + setting_reg #(.my_addr(SR_CORE_MISC), .awidth(8), .width(32), .at_reset(8'h0)) sr_misc + ( + .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(misc_outs), .changed() + ); + + setting_reg #(.my_addr(SR_CORE_READBACK), .awidth(8), .width(2)) sr_rdback + ( + .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(rb_addr), .changed() + ); + + setting_reg #(.my_addr(SR_CORE_SYNC), .awidth(8), .width(3)) sr_sync + ( + .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out({time_sync,pps_select}), .changed() + ); + + simple_spi_core #(.BASE(SR_CORE_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) misc_spi + ( + .clock(bus_clk), .reset(bus_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(spi_readback), .ready(spi_ready), + .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso), + .debug() + ); + + always @* + case(rb_addr) + 2'd0 : rb_data <= { 32'hACE0BA5E, COMPAT_MAJOR, COMPAT_MINOR }; + 2'd1 : rb_data <= { 32'b0, spi_readback }; + 2'd2 : rb_data <= { 16'b0, 8'd1, 8'd0, rb_misc }; + 2'd3 : rb_data <= { 30'h0, lock_state_r }; + default : rb_data <= 64'd0; + endcase // case (rb_addr) + + /******************************************************************* + * Radio + ******************************************************************/ + wire [31:0] fe_gpio_out32; + wire [9:0] fp_gpio_out10, fp_gpio_ddr10; + assign fe_gpio_out = fe_gpio_out32[7:0]; + assign fp_gpio_out = fp_gpio_out10[7:0]; + assign fp_gpio_ddr = fp_gpio_ddr10[7:0]; + + radio_legacy #( + .RADIO_FIFO_SIZE(RADIO_FIFO_SIZE), + .SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE), + .FP_GPIO(1), + .NEW_HB_INTERP(1), + .NEW_HB_DECIM(1), + .SOURCE_FLOW_CONTROL(0), + .USER_SETTINGS(0), + .DEVICE("SPARTAN6") + ) radio ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r), + .fe_gpio_in(32'h00000000), .fe_gpio_out(fe_gpio_out32), .fe_gpio_ddr(/* Always assumed to be outputs */), + .fp_gpio_in({2'b00, fp_gpio_in}), .fp_gpio_out(fp_gpio_out10), .fp_gpio_ddr(fp_gpio_ddr10), + .bus_clk(bus_clk), .bus_rst(bus_rst), + .tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready), + .rx_tdata(rx_tdata), .rx_tlast(rx_tlast), .rx_tvalid(rx_tvalid), .rx_tready(rx_tready), + .ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready), + .resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready), + .debug() + ); + + +endmodule // b205_core diff --git a/fpga/usrp3/top/b2xxmini/b205_io.v b/fpga/usrp3/top/b2xxmini/b205_io.v new file mode 100644 index 000000000..97e4cba24 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/b205_io.v @@ -0,0 +1,459 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +//------------------------------------------------------------------ +// NOTE: B205 is a SISO only device. MIMO references are unused code branches. +// +// In SISO mode, we output a clock thats 1x the frequency of the Catalina +// source-synchronous bus clock to be used as the radio_clk. +// +//------------------------------------------------------------------ + +module b205_io + ( + input reset, + + // Baseband sample interface + output radio_clk, + output [11:0] rx_i0, + output [11:0] rx_q0, + input [11:0] tx_i0, + input [11:0] tx_q0, + + // Catalina interface + input rx_clk, + input rx_frame, + input [11:0] rx_data, + output tx_clk, + output tx_frame, + output [11:0] tx_data + ); + + + genvar z; + + + //------------------------------------------------------------------ + // Clock Buffering. + // BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3. + // Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks. + //------------------------------------------------------------------ + wire rx_clk_buf; + wire siso_clk_unbuf; + wire siso_clk2_unbuf; + + IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk)); + + //------------------------------------------------------------------ + // + // Buffers for LEFT TOP half bank pins + // BUFIO2_X0Y22 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(4), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("TRUE")) + clk_bufio_lt + ( + .IOCLK(io_clk_lt), + .DIVCLK(), + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X0Y23 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lt_b + ( + .IOCLK(io_clk_lt_b), + .DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // + // Buffers for LEFT BOTTOM half bank pins + // BUFIO2_X1Y14 + // + //------------------------------------------------------------------ + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("FALSE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb + ( + .IOCLK(io_clk_lb), + .DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + // BUFIO2_X1Y15 + BUFIO2 #( + .DIVIDE(1), + .DIVIDE_BYPASS("FALSE"), + .I_INVERT("TRUE"), + .USE_DOUBLER("FALSE")) + clk_bufio_lb_b + ( + .IOCLK(io_clk_lb_b), + .DIVCLK(/*siso_clk2_unbuf*/), + .SERDESSTROBE(), + .I(rx_clk_buf) + ); + + //------------------------------------------------------------------ + // Always-on SISO clk needed to load/unload DDR2 I/O Regs + //------------------------------------------------------------------ + BUFG siso_clk_bufg ( + .I(siso_clk_unbuf), + .O(siso_clk) + ); + + //------------------------------------------------------------------ + // BUFG to drive global radio_clk. + //------------------------------------------------------------------ + BUFG radio_clk_bufg ( + .I(siso_clk2_unbuf), + .O(radio_clk) + ); + + //------------------------------------------------------------------ + // RX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + wire rx_frame_0, rx_frame_1; + + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_frame ( + .Q0(rx_frame_1), + .Q1(rx_frame_0), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_frame), + .R(1'b0), + .S(1'b0)); + + reg rx_frame_d1, rx_frame_d2; + always @(posedge siso_clk) + { rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 }; + + + //------------------------------------------------------------------ + // RX Data Bus - In bank3 both LT and LB + //------------------------------------------------------------------ + wire [11:0] rx_i,rx_q; + + // Bit0 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i0 ( + .Q0(rx_q[0]), + .Q1(rx_i[0]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[0]), + .R(1'b0), + .S(1'b0)); + + // Bit1 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i1 ( + .Q0(rx_q[1]), + .Q1(rx_i[1]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[1]), + .R(1'b0), + .S(1'b0)); + + // Bit2 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i2 ( + .Q0(rx_q[2]), + .Q1(rx_i[2]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[2]), + .R(1'b0), + .S(1'b0)); + + // Bit3 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i3 ( + .Q0(rx_q[3]), + .Q1(rx_i[3]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[3]), + .R(1'b0), + .S(1'b0)); + + // Bit4 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i4 ( + .Q0(rx_q[4]), + .Q1(rx_i[4]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[4]), + .R(1'b0), + .S(1'b0)); + + // Bit5 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i5 ( + .Q0(rx_q[5]), + .Q1(rx_i[5]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[5]), + .R(1'b0), + .S(1'b0)); + + // Bit6 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i6 ( + .Q0(rx_q[6]), + .Q1(rx_i[6]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[6]), + .R(1'b0), + .S(1'b0)); + + // Bit7 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i7 ( + .Q0(rx_q[7]), + .Q1(rx_i[7]), + .C0(io_clk_lt), + .C1(io_clk_lt_b), + .CE(1'b1), + .D(rx_data[7]), + .R(1'b0), + .S(1'b0)); + + // Bit8 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i8 ( + .Q0(rx_q[8]), + .Q1(rx_i[8]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[8]), + .R(1'b0), + .S(1'b0)); + + // Bit9 LT + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i9 ( + .Q0(rx_q[9]), + .Q1(rx_i[9]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[9]), + .R(1'b0), + .S(1'b0)); + + // Bit10 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i10 ( + .Q0(rx_q[10]), + .Q1(rx_i[10]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[10]), + .R(1'b0), + .S(1'b0)); + + // Bit11 LB + IDDR2 #( + .DDR_ALIGNMENT("C0")) + iddr2_i11 ( + .Q0(rx_q[11]), + .Q1(rx_i[11]), + .C0(io_clk_lb), + .C1(io_clk_lb_b), + .CE(1'b1), + .D(rx_data[11]), + .R(1'b0), + .S(1'b0)); + + //------------------------------------------------------------------ + // + // De-mux I & Q onto fullrate clock. + // + // We grab data from the IDDR2 using negedge of siso_clk. + // IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase + // with io_clk...siso_clk is always a little more delayed than io_clk. + // This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs + // with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register). + // + //------------------------------------------------------------------ + reg [11:0] rx_i_del, rx_q_del; + reg [11:0] rx_i0_siso_pos; + reg [11:0] rx_q0_siso_pos; + reg [11:0] rx_i0_siso_neg; + reg [11:0] rx_q0_siso_neg; + reg [11:0] rx_i0_siso; + reg [11:0] rx_q0_siso; + + always @(negedge siso_clk) + begin + rx_i0_siso[11:0] <= rx_i[11:0]; + rx_q0_siso[11:0] <= rx_q[11:0]; + end // else: !if(rx_frame_0) + + //------------------------------------------------------------------ + // + // Now prepare data for crossing into radio_clk domain which is always for SISO mode (inverted) siso_clk. + // (Note: posedge is used so that we have massive margin against a fast-path race condition + // betwwen siso_clk and radio_clk). + // + //------------------------------------------------------------------ + + // This code block only relevent in SISO mode. + always @(posedge siso_clk) + begin + rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0]; + rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0]; + end + + assign rx_i0 = rx_i0_siso_pos; + assign rx_q0 = rx_q0_siso_pos; + + + //------------------------------------------------------------------ + // TX Data Bus - In bank3 LB + //------------------------------------------------------------------ + reg [11:0] tx_i,tx_q; + + generate + for(z = 0; z < 12; z = z + 1) + begin : gen_pins + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2 ( + .Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0)); + end + endgenerate + + //------------------------------------------------------------------ + // TX Frame Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_frame ( + .Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // TX Clock Signal - In bank 3 LB + //------------------------------------------------------------------ + ODDR2 #( + .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) + oddr2_clk ( + .Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b), + .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); + + //------------------------------------------------------------------ + // + // Mux I & Q, onto fullrate clock TX bus to AD9361 + // + //------------------------------------------------------------------ + + always @(posedge siso_clk) + begin + {tx_i,tx_q} <= {tx_i0,tx_q0}; + end + + // + // Debug + // +/* -----\/----- EXCLUDED -----\/----- + wire [35:0] CONTROL0; + reg [11:0] tx_i_del_debug, tx_q_del_debug; + reg [11:0] tx_i_debug,tx_q_debug; + reg [11:0] tx_i0_debug,tx_q0_debug; + reg find_radio_clk_phase_debug; + reg find_radio_clk_phase_del_debug; + reg tx_strobe_debug; + reg tx_strobe_del_debug; + + + always @(posedge siso_clk) begin + tx_i_del_debug <= tx_i_del; + tx_q_del_debug <= tx_q_del; + tx_i_debug <= tx_i; + tx_q_debug <= tx_q; + tx_i0_debug <=tx_i0; + tx_q0_debug <= tx_q0; + find_radio_clk_phase_debug <= find_radio_clk_phase; + find_radio_clk_phase_del_debug <= find_radio_clk_phase_del; + tx_strobe_debug <= tx_strobe; + tx_strobe_del_debug <= tx_strobe_del; + end + + + + chipscope_icon chipscope_icon_i0 + ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] + ); + + chipscope_ila_128 chipscope_ila_i0 + ( + .CONTROL(CONTROL0), // INOUT BUS [35:0] + .CLK(siso_clk), // IN + .TRIG0( + { + tx_i_del_debug[11:0], + tx_q_del_debug[11:0], + tx_i_debug[11:0], + tx_q_debug[11:0], + tx_i0_debug[11:0], + tx_q0_debug[11:0], + find_radio_clk_phase_debug, + find_radio_clk_phase_del_debug, + tx_strobe_debug, + tx_strobe_del_debug + } + ) + + ); + -----/\----- EXCLUDED -----/\----- */ +endmodule diff --git a/fpga/usrp3/top/b2xxmini/b205_ref_pll.v b/fpga/usrp3/top/b2xxmini/b205_ref_pll.v new file mode 100644 index 000000000..0483bc93b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/b205_ref_pll.v @@ -0,0 +1,278 @@ +// +// Copyright 2015 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module b205_ref_pll( + input reset, + input clk, // 200 MHz sample clock + input refclk, // 40 MHz reference clock + input ref, // PPS or 10 MHz external reference + output reg locked, + + // SPI lines to AD5662 + output sclk, + output mosi, + output sync_n + ); + + // Base parameters + localparam SAMPLE_CLOCK_FREQ=200_000_000; + localparam REF_FREQ_PPS=1; + localparam REF_FREQ_10MHZ=10_000_000; + localparam REF_CLK_FREQ=40_000_000; + localparam PFD_FREQ_PPS=1; + localparam PFD_FREQ_10MHZ=10; + + // Lock detection parameters + localparam LOCK_TOLERANCE_PPM=1; + localparam LOCK_MARGIN_PPS=(SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS)*LOCK_TOLERANCE_PPM/1_000_000; + localparam LOCK_MARGIN_10MHZ=(SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ)*LOCK_TOLERANCE_PPM/1_000_000; + + // Reference frequency detection parameters + // References are only valid if they are +/-5ppm because that is the range of the VCTXCO + localparam REF_PERIOD_PPS=SAMPLE_CLOCK_FREQ/REF_FREQ_PPS; + localparam REF_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/REF_FREQ_10MHZ; + localparam REF_PERIOD_PPS_MIN=REF_PERIOD_PPS-(REF_PERIOD_PPS*5/1_000_000)-1; + localparam REF_PERIOD_PPS_MAX=REF_PERIOD_PPS+(REF_PERIOD_PPS*5/1_000_000)+1; + localparam REF_PERIOD_10MHZ_MIN=REF_PERIOD_10MHZ-(REF_PERIOD_10MHZ*5/1_000_000)-1; + localparam REF_PERIOD_10MHZ_MAX=REF_PERIOD_10MHZ+(REF_PERIOD_10MHZ*5/1_000_000)+1; + + // R divider parameters + localparam RDIV_PPS=REF_FREQ_PPS/PFD_FREQ_PPS; + localparam RDIV_10MHZ=REF_FREQ_10MHZ/PFD_FREQ_10MHZ; + + // N divider parameters (refclk is divided by 2) + localparam NDIV_PPS=REF_CLK_FREQ/2/PFD_FREQ_PPS; + localparam NDIV_10MHZ=REF_CLK_FREQ/2/PFD_FREQ_10MHZ; + + // PFD parameters + localparam PFD_PERIOD_PPS=SAMPLE_CLOCK_FREQ/PFD_FREQ_PPS; + localparam PFD_PERIOD_10MHZ=SAMPLE_CLOCK_FREQ/PFD_FREQ_10MHZ; + + + // Initial divide by 2 for 40 MHz clock + // (since refclk cannot be sampled directly) + reg refclk_div; + always @(posedge refclk) begin + refclk_div <= ~refclk_div; + end + + // flop signals into sample clock domain together + reg [3:0] refsmp; + reg [3:0] refclksmp; + always @(posedge clk) begin + refsmp <= {refsmp[2:0],ref}; + refclksmp <= {refclksmp[2:0],refclk_div}; + end + + // rising edge detection + wire ref_rising = (refsmp[3:2] == 2'b01); + wire refclk_rising = (refclksmp[3:2] == 2'b01); + + // reference frequency detection + reg [27:0] refcnt; + reg ref_detected; + reg ref_is_10M; + reg ref_is_pps; + wire valid_ref = ref_is_10M | ref_is_pps; + always @(posedge clk) begin + if (reset) begin + refcnt <= 28'd0; + ref_detected <= 1'b0; + ref_is_10M <= 1'b0; + ref_is_pps <= 1'b0; + end + else if (ref_rising) begin + refcnt <= 28'd1; + ref_detected <= 1'b1; + ref_is_10M <= ((refcnt >= REF_PERIOD_10MHZ_MIN) && (refcnt <= REF_PERIOD_10MHZ_MAX)); + ref_is_pps <= ((refcnt >= REF_PERIOD_PPS_MIN) && (refcnt <= REF_PERIOD_PPS_MAX)); + end + else if ((ref_is_10M && (refcnt > REF_PERIOD_10MHZ_MAX)) || (refcnt > REF_PERIOD_PPS_MAX)) begin + // consider the reference lost + refcnt <= 28'd0; + ref_detected <= 1'b0; + ref_is_10M <= 1'b0; + ref_is_pps <= 1'b0; + end + else if (ref_detected) + refcnt <= refcnt + 28'd1; + end + + // R divider + wire [23:0] rdiv = ref_is_10M ? RDIV_10MHZ : RDIV_PPS; + reg [23:0] rcnt; + wire [23:0] next_rcnt = ~valid_ref ? 24'd0 : (rcnt == rdiv) ? 24'd1 : rcnt + 1'b1; + reg r_rising; + always @(posedge clk) begin + if (ref_rising) + rcnt <= next_rcnt; + r_rising <= (ref_rising && ((ref_is_10M && (rcnt == rdiv)) || ref_is_pps)); + end + + // N divider + // Enable on rising edge of R after valid_ref + // is asserted so R and N signals start aligned. + // Disable if reference lost. + wire [25:0] ndiv = ref_is_10M ? NDIV_10MHZ : NDIV_PPS; + reg [25:0] ncnt; + wire [25:0] next_ncnt = ~valid_ref ? 26'd0 : ncnt == ndiv ? 26'd1 : ncnt + 1'b1; + reg n_rising; + always @(posedge clk) begin + if (refclk_rising) + ncnt <= next_ncnt; + n_rising <= (refclk_rising && (ncnt == ndiv)); + end + + // Frequency Counter + wire signed [28:0] period = ref_is_10M ? PFD_PERIOD_10MHZ : PFD_PERIOD_PPS; + reg signed [28:0] r_period_cnt; + reg signed [28:0] freq_err; + always @(posedge clk) begin + if (reset | ~valid_ref) begin + r_period_cnt <= 28'd0; + freq_err <= 29'sd0; + end + else if (r_rising) begin + r_period_cnt <= 28'd1; + freq_err <= period - r_period_cnt; + end + else + r_period_cnt <= r_period_cnt + 28'd1; + end + + // Phase Counter + reg signed [28:0] lead_cnt; + reg lead_cnt_ena; + reg signed [28:0] lead; + always @(posedge clk) begin + // Count how much N leads R + // The count is negative because it measures + // how much the VCTCXO must be slowed down. + if (~valid_ref | n_rising) begin + lead_cnt <= 29'sd0; + lead_cnt_ena <= 1'b1; + if (r_rising) + lead <= 29'sd0; + end + else if (r_rising) begin + if (lead_cnt_ena) + lead <= lead_cnt - 29'sd1; + else begin + // R rising with no preceding N rising. + // N has changed from leading to lagging R, + // but we don't yet know by how much so + // assume 1. + lead <= 29'sd1; + end + lead_cnt_ena <= 1'b0; + end + else if (lead_cnt_ena) + lead_cnt <= lead_cnt - 29'sd1; + end + + // PFD State Machine + localparam MEASURE=4'd0; + localparam CAPTURE=4'd1; + localparam CAPTURE_LAG=4'd2; + localparam CAPTURE_LEAD=4'd3; + localparam CALCULATE_ERROR=4'd4; + localparam CALCULATE_10M_GAIN=4'd5; + localparam CALCULATE_ADJUSTMENT=4'd6; + localparam CALCULATE_OUTPUT_VALUE=4'd7; + localparam APPLY_OUTPUT_VALUE=4'd8; + reg [3:0] state; + reg [15:0] daco = 16'd32767; + wire signed [28:0] lock_margin = ref_is_10M ? LOCK_MARGIN_10MHZ : LOCK_MARGIN_PPS; + wire signed [28:0] lag = lead + period; + reg signed [28:0] phase_err; + reg signed [28:0] err; + reg signed [28:0] shift; + reg signed [28:0] adj; + wire signed [28:0] dacv = {13'd0, daco}; + reg signed [28:0] sum; + reg [2:0] ld; + always @(posedge clk) begin + if (reset || ~valid_ref) begin + state <= MEASURE; + daco <= 16'd32767; + err <= 29'sd0; + shift <= 29'sd0; + adj <= 29'sd0; + ld <= 3'd0; + end + else begin + case(state) + MEASURE: begin + if (r_rising) + state <= CAPTURE; + end + CAPTURE: begin + if (lag < -lead) + state <= CAPTURE_LAG; + else + state <= CAPTURE_LEAD; + end + CAPTURE_LAG: begin + phase_err <= lag; + ld <= {ld[1:0], (lag <= lock_margin)}; + state <= CALCULATE_ERROR; + end + CAPTURE_LEAD: begin + phase_err <= lead; + ld <= {ld[1:0], (-lead <= lock_margin)}; + state <= CALCULATE_ERROR; + end + CALCULATE_ERROR: begin + err <= phase_err + freq_err; + state <= ref_is_10M ? CALCULATE_10M_GAIN : CALCULATE_ADJUSTMENT; + end + CALCULATE_10M_GAIN: begin + shift <= (err < -7 || err > 7) ? 7 : (err < 0 ? -err : err); + state <= CALCULATE_ADJUSTMENT; + end + CALCULATE_ADJUSTMENT: begin + // The VCTCXO is +/-5 ppm from 0.3V to 1.5V and the DAC is 16 bits, + // which works out to 0.000228885 ppm per DAC unit. + // The 200 MHz sampling clock means each unit of error is 0.005 ppm, + // which works out to 21.845 DAC units to correct each unit of error. + // Theory is nice, but the proportional and integral gains used here + // were determined through manual tuning. + if (ref_is_10M) + adj <= (err <<< shift); + else + adj <= (err <<< 4) - err; + state <= CALCULATE_OUTPUT_VALUE; + end + CALCULATE_OUTPUT_VALUE: begin + sum <= dacv + adj; + state <= APPLY_OUTPUT_VALUE; + end + APPLY_OUTPUT_VALUE: begin + // Clip and apply + if (sum < 29'sd0) + daco <= 16'd0; + else if (sum > 29'sd65535) + daco <= 16'd65535; + else + daco <= sum[15:0]; + state <= MEASURE; + end + endcase + end + end + + always @(posedge clk) + locked <= (ld == 3'b111); + + ad5662_auto_spi dac + ( + .clk(clk), + .dat(daco), + .sclk(sclk), + .mosi(mosi), + .sync_n(sync_n) + ); +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/.gitignore b/fpga/usrp3/top/b2xxmini/coregen/.gitignore new file mode 100644 index 000000000..bdeac28ca --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/.gitignore @@ -0,0 +1,5 @@ +/tmp +/_xmsgs +/*.log +/*.gise +/*.xise diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.asy b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.asy new file mode 100644 index 000000000..c2995765a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.asy @@ -0,0 +1,29 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 b205_clk_gen +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 176 576 176 +PIN 608 176 RIGHT 36 +PINATTR PinName clk_out2 +PINATTR Polarity OUT +LINE Normal 608 272 576 272 +PIN 608 272 RIGHT 36 +PINATTR PinName clk_out3 +PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.ucf b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.ucf new file mode 100755 index 000000000..9b318e829 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.ucf @@ -0,0 +1,59 @@ +# file: b205_clk_gen.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.v b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.v new file mode 100755 index 000000000..e4184e6fc --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.v @@ -0,0 +1,158 @@ +// file: b205_clk_gen.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______312.078____259.584 +// CLK_OUT2___100.000______0.000______50.0______255.594____259.584 +// CLK_OUT3___200.000______0.000______50.0______225.630____259.584 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +`timescale 1ps/1ps + +(* CORE_GENERATION_INFO = "b205_clk_gen,clk_wiz_v3_6,{component_name=b205_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=25.0,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) +module b205_clk_gen + (// Clock in ports + input CLK_IN1_40, + // Clock out ports + output CLK_OUT1_40_int, + output CLK_OUT2_100_bus, + output CLK_OUT3_200_ref_pll, + // Status and control signals + input RESET, + output LOCKED + ); + + // Input buffering + //------------------------------------ + IBUFG clkin1_buf + (.O (clkin1), + .I (CLK_IN1_40)); + + + // Clocking primitive + //------------------------------------ + // Instantiation of the PLL primitive + // * Unused inputs are tied off + // * Unused outputs are labeled unused + wire [15:0] do_unused; + wire drdy_unused; + wire clkfbout; + wire clkfbout_buf; + wire clkout3_unused; + wire clkout4_unused; + wire clkout5_unused; + + PLL_BASE + #(.BANDWIDTH ("OPTIMIZED"), + .CLK_FEEDBACK ("CLKFBOUT"), + .COMPENSATION ("SYSTEM_SYNCHRONOUS"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT (10), + .CLKFBOUT_PHASE (0.000), + .CLKOUT0_DIVIDE (10), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT1_DIVIDE (4), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT2_DIVIDE (2), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKIN_PERIOD (25.0), + .REF_JITTER (0.010)) + pll_base_inst + // Output clocks + (.CLKFBOUT (clkfbout), + .CLKOUT0 (clkout0), + .CLKOUT1 (clkout1), + .CLKOUT2 (clkout2), + .CLKOUT3 (clkout3_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + // Status and control signals + .LOCKED (LOCKED), + .RST (RESET), + // Input clock control + .CLKFBIN (clkfbout_buf), + .CLKIN (clkin1)); + + + // Output buffering + //----------------------------------- + BUFG clkf_buf + (.O (clkfbout_buf), + .I (clkfbout)); + + BUFG clkout1_buf + (.O (CLK_OUT1_40_int), + .I (clkout0)); + + + BUFG clkout2_buf + (.O (CLK_OUT2_100_bus), + .I (clkout1)); + + BUFG clkout3_buf + (.O (CLK_OUT3_200_ref_pll), + .I (clkout2)); + + + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.veo b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.veo new file mode 100755 index 000000000..874e6b65c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.veo @@ -0,0 +1,82 @@ +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// "Output Output Phase Duty Pk-to-Pk Phase" +// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +//---------------------------------------------------------------------------- +// CLK_OUT1____40.000______0.000______50.0______312.078____259.584 +// CLK_OUT2___100.000______0.000______50.0______255.594____259.584 +// CLK_OUT3___200.000______0.000______50.0______225.630____259.584 +// +//---------------------------------------------------------------------------- +// "Input Clock Freq (MHz) Input Jitter (UI)" +//---------------------------------------------------------------------------- +// __primary__________40.000____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + b205_clk_gen instance_name + (// Clock in ports + .CLK_IN1_40(CLK_IN1_40), // IN + // Clock out ports + .CLK_OUT1_40_int(CLK_OUT1_40_int), // OUT + .CLK_OUT2_100_bus(CLK_OUT2_100_bus), // OUT + .CLK_OUT3_200_ref_pll(CLK_OUT3_200_ref_pll), // OUT + // Status and control signals + .RESET(RESET),// IN + .LOCKED(LOCKED)); // OUT +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xco b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xco new file mode 100644 index 000000000..d3688079a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xco @@ -0,0 +1,269 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jul 14 00:18:05 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:clk_wiz:3.6 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6 +# END Select +# BEGIN Parameters +CSET calc_done=DONE +CSET clk_in_sel_port=CLK_IN_SEL +CSET clk_out1_port=CLK_OUT1_40_int +CSET clk_out1_use_fine_ps_gui=false +CSET clk_out2_port=CLK_OUT2_100_bus +CSET clk_out2_use_fine_ps_gui=false +CSET clk_out3_port=CLK_OUT3_200_ref_pll +CSET clk_out3_use_fine_ps_gui=false +CSET clk_out4_port=CLK_OUT4_gpif +CSET clk_out4_use_fine_ps_gui=false +CSET clk_out5_port=CLK_OUT5 +CSET clk_out5_use_fine_ps_gui=false +CSET clk_out6_port=CLK_OUT6 +CSET clk_out6_use_fine_ps_gui=false +CSET clk_out7_port=CLK_OUT7 +CSET clk_out7_use_fine_ps_gui=false +CSET clk_valid_port=CLK_VALID +CSET clkfb_in_n_port=CLKFB_IN_N +CSET clkfb_in_p_port=CLKFB_IN_P +CSET clkfb_in_port=CLKFB_IN +CSET clkfb_in_signaling=SINGLE +CSET clkfb_out_n_port=CLKFB_OUT_N +CSET clkfb_out_p_port=CLKFB_OUT_P +CSET clkfb_out_port=CLKFB_OUT +CSET clkfb_stopped_port=CLKFB_STOPPED +CSET clkin1_jitter_ps=250.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 +CSET clkout1_drives=BUFG +CSET clkout1_requested_duty_cycle=50.000 +CSET clkout1_requested_out_freq=40.000 +CSET clkout1_requested_phase=0.000 +CSET clkout2_drives=BUFG +CSET clkout2_requested_duty_cycle=50.000 +CSET clkout2_requested_out_freq=100.000 +CSET clkout2_requested_phase=0.000 +CSET clkout2_used=true +CSET clkout3_drives=BUFG +CSET clkout3_requested_duty_cycle=50.000 +CSET clkout3_requested_out_freq=200.000 +CSET clkout3_requested_phase=0.000 +CSET clkout3_used=true +CSET clkout4_drives=BUFG +CSET clkout4_requested_duty_cycle=50.000 +CSET clkout4_requested_out_freq=80.000 +CSET clkout4_requested_phase=0.000 +CSET clkout4_used=false +CSET clkout5_drives=BUFG +CSET clkout5_requested_duty_cycle=50.000 +CSET clkout5_requested_out_freq=100.000 +CSET clkout5_requested_phase=0.000 +CSET clkout5_used=false +CSET clkout6_drives=BUFG +CSET clkout6_requested_duty_cycle=50.000 +CSET clkout6_requested_out_freq=100.000 +CSET clkout6_requested_phase=0.000 +CSET clkout6_used=false +CSET clkout7_drives=BUFG +CSET clkout7_requested_duty_cycle=50.000 +CSET clkout7_requested_out_freq=100.000 +CSET clkout7_requested_phase=0.000 +CSET clkout7_used=false +CSET clock_mgr_type=AUTO +CSET component_name=b205_clk_gen +CSET daddr_port=DADDR +CSET dclk_port=DCLK +CSET dcm_clk_feedback=1X +CSET dcm_clk_out1_port=CLK0 +CSET dcm_clk_out2_port=CLKFX +CSET dcm_clk_out3_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 +CSET dcm_clk_out6_port=CLK0 +CSET dcm_clkdv_divide=2.0 +CSET dcm_clkfx_divide=2 +CSET dcm_clkfx_multiply=5 +CSET dcm_clkgen_clk_out1_port=CLKFX +CSET dcm_clkgen_clk_out2_port=CLKFX +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 +CSET dcm_clkgen_clkfx_md_max=0.000 +CSET dcm_clkgen_clkfx_multiply=4 +CSET dcm_clkgen_clkfxdv_divide=2 +CSET dcm_clkgen_clkin_period=10.000 +CSET dcm_clkgen_notes=None +CSET dcm_clkgen_spread_spectrum=NONE +CSET dcm_clkgen_startup_wait=false +CSET dcm_clkin_divide_by_2=false +CSET dcm_clkin_period=25.000 +CSET dcm_clkout_phase_shift=NONE +CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS +CSET dcm_notes=None +CSET dcm_phase_shift=0 +CSET dcm_pll_cascade=NONE +CSET dcm_startup_wait=false +CSET den_port=DEN +CSET din_port=DIN +CSET dout_port=DOUT +CSET drdy_port=DRDY +CSET dwe_port=DWE +CSET feedback_source=FDBK_AUTO +CSET in_freq_units=Units_MHz +CSET in_jitter_units=Units_UI +CSET input_clk_stopped_port=INPUT_CLK_STOPPED +CSET jitter_options=UI +CSET jitter_sel=No_Jitter +CSET locked_port=LOCKED +CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_clkfbout_mult_f=4.000 +CSET mmcm_clkfbout_phase=0.000 +CSET mmcm_clkfbout_use_fine_ps=false +CSET mmcm_clkin1_period=10.000 +CSET mmcm_clkin2_period=10.000 +CSET mmcm_clkout0_divide_f=4.000 +CSET mmcm_clkout0_duty_cycle=0.500 +CSET mmcm_clkout0_phase=0.000 +CSET mmcm_clkout0_use_fine_ps=false +CSET mmcm_clkout1_divide=1 +CSET mmcm_clkout1_duty_cycle=0.500 +CSET mmcm_clkout1_phase=0.000 +CSET mmcm_clkout1_use_fine_ps=false +CSET mmcm_clkout2_divide=1 +CSET mmcm_clkout2_duty_cycle=0.500 +CSET mmcm_clkout2_phase=0.000 +CSET mmcm_clkout2_use_fine_ps=false +CSET mmcm_clkout3_divide=1 +CSET mmcm_clkout3_duty_cycle=0.500 +CSET mmcm_clkout3_phase=0.000 +CSET mmcm_clkout3_use_fine_ps=false +CSET mmcm_clkout4_cascade=false +CSET mmcm_clkout4_divide=1 +CSET mmcm_clkout4_duty_cycle=0.500 +CSET mmcm_clkout4_phase=0.000 +CSET mmcm_clkout4_use_fine_ps=false +CSET mmcm_clkout5_divide=1 +CSET mmcm_clkout5_duty_cycle=0.500 +CSET mmcm_clkout5_phase=0.000 +CSET mmcm_clkout5_use_fine_ps=false +CSET mmcm_clkout6_divide=1 +CSET mmcm_clkout6_duty_cycle=0.500 +CSET mmcm_clkout6_phase=0.000 +CSET mmcm_clkout6_use_fine_ps=false +CSET mmcm_clock_hold=false +CSET mmcm_compensation=ZHOLD +CSET mmcm_divclk_divide=1 +CSET mmcm_notes=None +CSET mmcm_ref_jitter1=0.010 +CSET mmcm_ref_jitter2=0.010 +CSET mmcm_startup_wait=false +CSET num_out_clks=3 +CSET override_dcm=false +CSET override_dcm_clkgen=false +CSET override_mmcm=false +CSET override_pll=false +CSET platform=lin64 +CSET pll_bandwidth=OPTIMIZED +CSET pll_clk_feedback=CLKFBOUT +CSET pll_clkfbout_mult=10 +CSET pll_clkfbout_phase=0.000 +CSET pll_clkin_period=25.0 +CSET pll_clkout0_divide=10 +CSET pll_clkout0_duty_cycle=0.500 +CSET pll_clkout0_phase=0.000 +CSET pll_clkout1_divide=4 +CSET pll_clkout1_duty_cycle=0.500 +CSET pll_clkout1_phase=0.000 +CSET pll_clkout2_divide=2 +CSET pll_clkout2_duty_cycle=0.500 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=5 +CSET pll_clkout3_duty_cycle=0.500 +CSET pll_clkout3_phase=0.000 +CSET pll_clkout4_divide=1 +CSET pll_clkout4_duty_cycle=0.500 +CSET pll_clkout4_phase=0.000 +CSET pll_clkout5_divide=1 +CSET pll_clkout5_duty_cycle=0.500 +CSET pll_clkout5_phase=0.000 +CSET pll_compensation=SYSTEM_SYNCHRONOUS +CSET pll_divclk_divide=1 +CSET pll_notes=None +CSET pll_ref_jitter=0.010 +CSET power_down_port=POWER_DOWN +CSET prim_in_freq=40.000 +CSET prim_in_jitter=0.010 +CSET prim_source=Single_ended_clock_capable_pin +CSET primary_port=CLK_IN1_40 +CSET primitive=MMCM +CSET primtype_sel=PLL_BASE +CSET psclk_port=PSCLK +CSET psdone_port=PSDONE +CSET psen_port=PSEN +CSET psincdec_port=PSINCDEC +CSET relative_inclk=REL_PRIMARY +CSET reset_port=RESET +CSET secondary_in_freq=100.000 +CSET secondary_in_jitter=0.010 +CSET secondary_port=CLK_IN2 +CSET secondary_source=Single_ended_clock_capable_pin +CSET ss_mod_freq=250 +CSET ss_mode=CENTER_HIGH +CSET status_port=STATUS +CSET summary_strings=empty +CSET use_clk_valid=false +CSET use_clkfb_stopped=false +CSET use_dyn_phase_shift=false +CSET use_dyn_reconfig=false +CSET use_freeze=false +CSET use_freq_synth=true +CSET use_inclk_stopped=false +CSET use_inclk_switchover=false +CSET use_locked=true +CSET use_max_i_jitter=false +CSET use_min_o_jitter=false +CSET use_min_power=false +CSET use_phase_alignment=true +CSET use_power_down=false +CSET use_reset=true +CSET use_spread_spectrum=false +CSET use_spread_spectrum_1=false +CSET use_status=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-05-10T12:44:55Z +# END Extra information +GENERATE +# CRC: 14fd4cf9 diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xdc b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xdc new file mode 100755 index 000000000..992f39959 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen.xdc @@ -0,0 +1,67 @@ +# file: b205_clk_gen.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 25.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.25 + +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..91dcdd01f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_readme.txt new file mode 100644 index 000000000..91dcdd01f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_readme.txt @@ -0,0 +1,184 @@ +CHANGE LOG for LogiCORE Clocking Wizard V3.6 + + Release Date: June 19, 2013 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/ + +................................................................................ + +2. DEVICE SUPPORT + + + 2.1 ISE + + + The following device families are supported by the core for this release. + + All 7 Series devices + + + Zynq-7000 devices + Zynq-7000 + Defense Grade Zynq-7000Q (XQ) + + + All Virtex-6 devices + + + All Spartan-6 devices + + +................................................................................ + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - Spread Spectrum support for 7 series MMCME2 + + - ISE 14.2 software support + +................................................................................ + +4. RESOLVED ISSUES + + + 4.1 ISE + + Resolved issue with example design becoming core top in planAhead + + Resolved issue with Virtex6 MMCM instantiation for VHDL project + Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +................................................................................ + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + +................................................................................ + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support +10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support +07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support +04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support +01/18/2012 Xilinx, Inc. 3.3 ISE 13.4 support +06/22/2011 Xilinx, Inc. 3.2 ISE 13.2 support +03/01/2011 Xilinx, Inc. 3.1 ISE 13.1 support +12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support +09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support +07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support +04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support +12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support +09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support +06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support +04/24/2009 Xilinx, Inc. 1.1 Initial release; 11.1 support +================================================================================ + +................................................................................ + +8. LEGAL DISCLAIMER + +(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. + +This file contains confidential and proprietary information +of Xilinx, Inc. and is protected under U.S. and +international copyright and other intellectual property +laws. + +DISCLAIMER +This disclaimer is not a license and does not grant any +rights to the materials distributed herewith. Except as +otherwise provided in a valid license issued to you by +Xilinx, and to the maximum extent permitted by applicable +law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +(2) Xilinx shall not be liable (whether in contract or tort, +including negligence, or under any other theory of +liability) for any loss or damage of any kind or nature +related to, arising under or in connection with these +materials, including for any direct, or any indirect, +special, incidental, or consequential loss or damage +(including loss of data, profits, goodwill, or any type of +loss or damage suffered as a result of any action brought +by a third party) even if such damage or loss was +reasonably foreseeable or Xilinx had been advised of the +possibility of the same. + +CRITICAL APPLICATIONS +Xilinx products are not designed or intended to be fail- +safe, or for use in any application requiring fail-safe +performance, such as life-support or safety devices or +systems, Class III medical devices, nuclear facilities, +applications related to the deployment of airbags, or any +other applications that could lead to death, personal +injury, or severe property or environmental damage +(individually and collectively, "Critical +Applications"). Customer assumes the sole risk and +liability of any use of Xilinx products in Critical +Applications, subject only to applicable laws and +regulations governing limitations on product liability. + +THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +PART OF THIS FILE AT ALL TIMES. + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_vinfo.html b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_vinfo.html new file mode 100644 index 000000000..d6deba06c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/clk_wiz_v3_6_vinfo.html @@ -0,0 +1,195 @@ + + +clk_wiz_v3_6_vinfo + + + +

+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+
+
+ + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/pg065_clk_wiz.pdf b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/pg065_clk_wiz.pdf new file mode 100644 index 000000000..a7daa6089 Binary files /dev/null and b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/doc/pg065_clk_wiz.pdf differ diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.ucf b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.ucf new file mode 100755 index 000000000..c98fa6f8c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.ucf @@ -0,0 +1,60 @@ +# file: b205_clk_gen_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.0 ns HIGH 50% INPUT_JITTER 250.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.v b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.v new file mode 100755 index 000000000..45b605d7f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.v @@ -0,0 +1,178 @@ +// file: b205_clk_gen_exdes.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard example design +//---------------------------------------------------------------------------- +// This example design instantiates the created clocking network, where each +// output clock drives a counter. The high bit of each counter is ported. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +module b205_clk_gen_exdes + #( + parameter TCQ = 100 + ) + (// Clock in ports + input CLK_IN1, + // Reset that only drives logic in example design + input COUNTER_RESET, + output [3:1] CLK_OUT, + // High bits of counters driven by clocks + output [3:1] COUNT, + // Status and control signals + input RESET, + output LOCKED + ); + + // Parameters for the counters + //------------------------------- + // Counter width + localparam C_W = 16; + // Number of counters + localparam NUM_C = 3; + genvar count_gen; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || RESET || COUNTER_RESET; + + reg [NUM_C:1] rst_sync; + reg [NUM_C:1] rst_sync_int; + reg [NUM_C:1] rst_sync_int1; + reg [NUM_C:1] rst_sync_int2; + + + // Declare the clocks and counters + wire [NUM_C:1] clk_int; + wire [NUM_C:1] clk_n; + wire [NUM_C:1] clk; + reg [C_W-1:0] counter [NUM_C:1]; + + // Instantiation of the clocking network + //-------------------------------------- + b205_clk_gen clknetwork + (// Clock in ports + .CLK_IN1_40 (CLK_IN1), + // Clock out ports + .CLK_OUT1_40_int (clk_int[1]), + .CLK_OUT2_100_bus (clk_int[2]), + .CLK_OUT3_200_ref_pll (clk_int[3]), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +genvar clk_out_pins; + +generate + for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1) + begin: gen_outclk_oddr + assign clk_n[clk_out_pins] = ~clk[clk_out_pins]; + + ODDR2 clkout_oddr + (.Q (CLK_OUT[clk_out_pins]), + .C0 (clk[clk_out_pins]), + .C1 (clk_n[clk_out_pins]), + .CE (1'b1), + .D0 (1'b1), + .D1 (1'b0), + .R (1'b0), + .S (1'b0)); + end +endgenerate + + // Connect the output clocks to the design + //----------------------------------------- + assign clk[1] = clk_int[1]; + assign clk[2] = clk_int[2]; + assign clk[3] = clk_int[3]; + + + // Reset synchronizer + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1 + always @(posedge reset_int or posedge clk[count_gen]) begin + if (reset_int) begin + rst_sync[count_gen] <= 1'b1; + rst_sync_int[count_gen]<= 1'b1; + rst_sync_int1[count_gen]<= 1'b1; + rst_sync_int2[count_gen]<= 1'b1; + end + else begin + rst_sync[count_gen] <= 1'b0; + rst_sync_int[count_gen] <= rst_sync[count_gen]; + rst_sync_int1[count_gen] <= rst_sync_int[count_gen]; + rst_sync_int2[count_gen] <= rst_sync_int1[count_gen]; + end + end + end + endgenerate + + + // Output clock sampling + //----------------------------------- + generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters + + always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin + if (rst_sync_int2[count_gen]) begin + counter[count_gen] <= #TCQ { C_W { 1'b 0 } }; + end else begin + counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1; + end + end + // alias the high bit of each counter to the corresponding + // bit in the output bus + assign COUNT[count_gen] = counter[count_gen][C_W-1]; + end + endgenerate + + + + + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.xdc b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.xdc new file mode 100755 index 000000000..0678543c6 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/example_design/b205_clk_gen_exdes.xdc @@ -0,0 +1,69 @@ +# file: b205_clk_gen_exdes.xdc +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +create_clock -name CLK_IN1 -period 25.0 [get_ports CLK_IN1] +set_propagated_clock CLK_IN1 +set_input_jitter CLK_IN1 0.25 + +# FALSE PATH constraint added on COUNTER_RESET +set_false_path -from [get_ports "COUNTER_RESET"] +set_false_path -from [get_ports "RESET"] + +# Derived clock periods. These are commented out because they are +# automatically propogated by the tools +# However, if you'd like to use them for module level testing, you +# can copy them into your module level timing checks +#----------------------------------------------------------------- + +#----------------------------------------------------------------- + +#----------------------------------------------------------------- diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.bat new file mode 100755 index 000000000..729bfef85 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.bat @@ -0,0 +1,90 @@ +REM file: implement.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM ----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM ----------------------------------------------------------------------------- + +REM Clean up the results directory +rmdir /S /Q results +mkdir results + +REM Copy unisim_comp.v file to results directory +copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ + +REM Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +move b205_clk_gen_exdes.ngc results\ + +REM Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\b205_clk_gen_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b205_clk_gen_exdes.ucf b205_clk_gen_exdes + +echo 'Running map' +map -timing -pr b b205_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b205_clk_gen_exdes -w routed.ncd routed.v +cd .. + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.sh new file mode 100755 index 000000000..ffac9e81c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/implement.sh @@ -0,0 +1,91 @@ +#!/bin/sh +# file: implement.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +# Clean up the results directory +rm -rf results +mkdir results + +# Copy unisim_comp.v file to results directory +cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ + +# Synthesize the Verilog Wrapper Files +echo 'Synthesizing Clocking Wizard design with XST' +xst -ifn xst.scr +mv b205_clk_gen_exdes.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/b205_clk_gen_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -uc b205_clk_gen_exdes.ucf b205_clk_gen_exdes + +echo 'Running map' +map -timing b205_clk_gen_exdes -o mapped.ncd + +echo 'Running par' +par -w mapped.ncd routed mapped.pcf + +echo 'Running trce' +trce -e 10 routed -o routed mapped.pcf + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level model for the clocking wizard example design' +netgen -ofmt verilog -sim -sdf_anno false -tm b205_clk_gen_exdes -w routed.ncd routed.v + +cd .. diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.bat new file mode 100755 index 000000000..8ac771810 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.bat @@ -0,0 +1,58 @@ +REM file: planAhead_ise.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the clocking wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.sh new file mode 100755 index 000000000..6c8c837d3 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.sh @@ -0,0 +1,59 @@ +#!/bin/sh +# file: planAhead_ise.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the clocking wizard +#----------------------------------------------------------------------------- + +rm -rf results +mkdir results +cd results + +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.tcl new file mode 100755 index 000000000..74ddb6a1a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_ise.tcl @@ -0,0 +1,78 @@ +# file: planAhead_ise.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set projDir [file dirname [info script]] +set projName b205_clk_gen +set topName b205_clk_gen_exdes +set device xc6slx75csg484-3 + +create_project $projName $projDir/results/$projName -part $device + +set_property design_mode RTL [get_filesets sources_1] + +## Source files +#set verilogSources [glob $srcDir/*.v] +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/b205_clk_gen_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../b205_clk_gen.v + + +#UCF file +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/b205_clk_gen_exdes.ucf + +set_property top $topName [get_property srcset [current_run]] + +launch_runs -runs synth_1 +wait_on_run synth_1 + +set_property add_step Bitgen [get_runs impl_1] +launch_runs -runs impl_1 +wait_on_run impl_1 + + + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.bat new file mode 100755 index 000000000..42273f5d4 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.bat @@ -0,0 +1,58 @@ +REM file: planAhead_rdn.sh +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM----------------------------------------------------------------------------- +REM Script to synthesize and implement the RTL provided for the XADC wizard +REM----------------------------------------------------------------------------- + +del \f results +mkdir results +cd results + +planAhead -mode batch -source ..\planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.sh new file mode 100755 index 000000000..f4c14729e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.sh @@ -0,0 +1,57 @@ +#!/bin/sh +# file: planAhead_rdn.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the RTL provided for the XADC wizard +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +planAhead -mode batch -source ../planAhead_rdn.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.tcl new file mode 100755 index 000000000..8c4276049 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/planAhead_rdn.tcl @@ -0,0 +1,69 @@ +# file : planAhead_rdn.tcl +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +set device xc6slx75csg484-3 +set projName b205_clk_gen +set design b205_clk_gen +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module b205_clk_gen_exdes +set_property top b205_clk_gen_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../b205_clk_gen.v} +add_files -norecurse {../../example_design/b205_clk_gen_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/b205_clk_gen_exdes.xdc} +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module b205_clk_gen_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module b205_clk_gen_exdes -file routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.prj b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.prj new file mode 100755 index 000000000..0579440e0 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../b205_clk_gen.v +verilog work ../example_design/b205_clk_gen_exdes.v diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.scr b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.scr new file mode 100755 index 000000000..ce30cf255 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/implement/xst.scr @@ -0,0 +1,9 @@ +run +-ifmt MIXED +-top b205_clk_gen_exdes +-p xc6slx75-csg484-3 +-ifn xst.prj +-ofn b205_clk_gen_exdes +-keep_hierarchy soft +-equivalent_register_removal no +-max_fanout 65535 diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/b205_clk_gen_tb.v b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/b205_clk_gen_tb.v new file mode 100755 index 000000000..a324a5983 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/b205_clk_gen_tb.v @@ -0,0 +1,143 @@ +// file: b205_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b205_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*20) + COUNTER_RESET = 0; + + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b205_clk_gen_exdes + #( + .TCQ (TCQ) + ) dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simcmds.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simcmds.tcl new file mode 100755 index 000000000..0c370db66 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simcmds.tcl @@ -0,0 +1,8 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b205_clk_gen_tb -l 0 +wave add / +run 50000ns +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..63b151629 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.bat @@ -0,0 +1,59 @@ +REM file: simulate_isim.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +vlogcomp -work work %XILINX%\verilog\src\glbl.v +vlogcomp -work work ..\..\..\b205_clk_gen.v +vlogcomp -work work ..\..\example_design\b205_clk_gen_exdes.v +vlogcomp -work work ..\b205_clk_gen_tb.v + +REM compile the project +fuse work.b205_clk_gen_tb work.glbl -L unisims_ver -o b205_clk_gen_isim.exe + +REM run the simulation script +.\b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..9ea0bb115 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_isim.sh @@ -0,0 +1,61 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# lin64 +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../../b205_clk_gen.v +vlogcomp -work work ../../example_design/b205_clk_gen_exdes.v +vlogcomp -work work ../b205_clk_gen_tb.v + +# compile the project +fuse work.b205_clk_gen_tb work.glbl -L unisims_ver -o b205_clk_gen_isim.exe + +# run the simulation script +./b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..74786e3eb --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.bat @@ -0,0 +1,61 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM + +REM set up the working directory +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\..\b205_clk_gen.v +vlog -work work ..\..\example_design\b205_clk_gen_exdes.v +vlog -work work ..\b205_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b205_clk_gen_tb work.glbl + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..2a9f3b03c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../../b205_clk_gen.v +vlog -work work ../../example_design/b205_clk_gen_exdes.v +vlog -work work ../b205_clk_gen_tb.v + +# run the simulation +vsim -t ps -voptargs="+acc" -L unisims_ver work.b205_clk_gen_tb work.glbl +do wave.do +log b205_clk_gen_tb/dut/counter +log -r /* +run 50000ns diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..0fe952789 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../../b205_clk_gen.v +vlog -work work ../../example_design/b205_clk_gen_exdes.v +vlog -work work ../b205_clk_gen_tb.v + +# run the simulation +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.b205_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..0ca92d135 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,62 @@ +#/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../../b205_clk_gen.v +ncvlog -work work ../../example_design/b205_clk_gen_exdes.v +ncvlog -work work ../b205_clk_gen_tb.v + +# elaborate and run the simulation +ncelab -work work -access +wc work.b205_clk_gen_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.b205_clk_gen_tb diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..13f45cebf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time +vlogan -sverilog \ + ${XILINX}/verilog/src/glbl.v \ + ../../../b205_clk_gen.v \ + ../../example_design/b205_clk_gen_exdes.v \ + ../b205_clk_gen_tb.v + +# prepare the simulation +vcs +vcs+lic+wait -debug b205_clk_gen_tb glbl + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..d125f20f1 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/ucli_commands.key @@ -0,0 +1,5 @@ +call {$vcdpluson} +call {$vcdplusmemon(b205_clk_gen_tb.dut.counter)} +run +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..eedc9fa49 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/vcs_session.tcl @@ -0,0 +1,18 @@ +gui_open_window Wave +gui_sg_create b205_clk_gen_group +gui_list_add_group -id Wave.1 {b205_clk_gen_group} +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.test_phase} +gui_set_radix -radix {ascii} -signals {b205_clk_gen_tb.test_phase} +gui_sg_addsignal -group b205_clk_gen_group {{Input_clocks}} -divider +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.CLK_IN1} +gui_sg_addsignal -group b205_clk_gen_group {{Output_clocks}} -divider +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.dut.clk} +gui_list_expand -id Wave.1 b205_clk_gen_tb.dut.clk +gui_sg_addsignal -group b205_clk_gen_group {{Status_control}} -divider +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.RESET} +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.LOCKED} +gui_sg_addsignal -group b205_clk_gen_group {{Counters}} -divider +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.COUNT} +gui_sg_addsignal -group b205_clk_gen_group {b205_clk_gen_tb.dut.counter} +gui_list_expand -id Wave.1 b205_clk_gen_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.do b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.do new file mode 100755 index 000000000..4549dbf6e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.do @@ -0,0 +1,60 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +add wave -noupdate -format Literal -radix ascii /b205_clk_gen_tb/test_phase +add wave -noupdate -divider {Input clocks} +add wave -noupdate -format Logic /b205_clk_gen_tb/CLK_IN1 +add wave -noupdate -divider {Output clocks} +add wave -noupdate -format Literal -expand /b205_clk_gen_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /b205_clk_gen_tb/RESET +add wave -noupdate -format Logic /b205_clk_gen_tb/LOCKED +add wave -noupdate -divider Counters +add wave -noupdate -format Literal -radix hexadecimal /b205_clk_gen_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal -expand /b205_clk_gen_tb/dut/counter diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.sv b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.sv new file mode 100755 index 000000000..a785ec556 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/wave.sv @@ -0,0 +1,119 @@ +# file: wave.sv +# +# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +# Get the windows set up +# +if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} { + window geometry "Design Browser 1" 1054x819+536+322 +} +window target "Design Browser 1" on +browser using {Design Browser 1} +browser set \ + -scope nc::b205_clk_gen_tb +browser yview see nc::b205_clk_gen_tb +browser timecontrol set -lock 0 + +if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { + window geometry "Waveform 1" 1010x600+0+541 +} +window target "Waveform 1" on +waveform using {Waveform 1} +waveform sidebar visibility partial +waveform set \ + -primarycursor TimeA \ + -signalnames name \ + -signalwidth 175 \ + -units ns \ + -valuewidth 75 +cursor set -using TimeA -time 0 +waveform baseline set -time 0 +waveform xview limits 0 20000n + +# +# Define signal groups +# +catch {group new -name {Output clocks} -overlay 0} +catch {group new -name {Status/control} -overlay 0} +catch {group new -name {Counters} -overlay 0} + +set id [waveform add -signals [list {nc::b205_clk_gen_tb.CLK_IN1}]] + +group using {Output clocks} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b205_clk_gen_tb.dut.clk[1]} \ + {b205_clk_gen_tb.dut.clk[2]} \ {b205_clk_gen_tb.dut.clk[3]} +group using {Counters} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {b205_clk_gen_tb.dut.counter[1]} \ + {b205_clk_gen_tb.dut.counter[2]} \ {b205_clk_gen_tb.dut.counter[3]} +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::b205_clk_gen_tb.RESET} {nc::b205_clk_gen_tb.LOCKED} + + +set id [waveform add -signals [list {nc::b205_clk_gen_tb.COUNT} ]] + +set id [waveform add -signals [list {nc::b205_clk_gen_tb.test_phase} ]] +waveform format $id -radix %a + +set groupId [waveform add -groups {{Input clocks}}] +set groupId [waveform add -groups {{Output clocks}}] +set groupId [waveform add -groups {{Status/control}}] +set groupId [waveform add -groups {{Counters}}] diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/b205_clk_gen_tb.v b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/b205_clk_gen_tb.v new file mode 100755 index 000000000..04a2cf036 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/b205_clk_gen_tb.v @@ -0,0 +1,157 @@ +// file: b205_clk_gen_tb.v +// +// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// + +//---------------------------------------------------------------------------- +// Clocking wizard demonstration testbench +//---------------------------------------------------------------------------- +// This demonstration testbench instantiates the example design for the +// clocking wizard. Input clocks are toggled, which cause the clocking +// network to lock and the counters to increment. +//---------------------------------------------------------------------------- + +`timescale 1ps/1ps + +`define wait_lock @(posedge LOCKED) + +module b205_clk_gen_tb (); + + // Clock to Q delay of 100ps + localparam TCQ = 100; + + + // timescale is 1ps/1ps + localparam ONE_NS = 1000; + localparam PHASE_ERR_MARGIN = 100; // 100ps + // how many cycles to run + localparam COUNT_PHASE = 1024; + // we'll be using the period in many locations + localparam time PER1 = 25.0*ONE_NS; + localparam time PER1_1 = PER1/2; + localparam time PER1_2 = PER1 - PER1/2; + + // Declare the input clock signals + reg CLK_IN1 = 1; + + // The high bits of the sampling counters + wire [3:1] COUNT; + // Status and control signals + reg RESET = 0; + wire LOCKED; + reg COUNTER_RESET = 0; +wire [3:1] CLK_OUT; +//Freq Check using the M & D values setting and actual Frequency generated + + reg [13:0] timeout_counter = 14'b00000000000000; + + // Input clock generation + //------------------------------------ + always begin + CLK_IN1 = #PER1_1 ~CLK_IN1; + CLK_IN1 = #PER1_2 ~CLK_IN1; + end + + // Test sequence + reg [15*8-1:0] test_phase = ""; + initial begin + // Set up any display statements using time to be readable + $timeformat(-12, 2, "ps", 10); + $display ("Timing checks are not valid"); + COUNTER_RESET = 0; + test_phase = "reset"; + RESET = 1; + #(PER1*6); + RESET = 0; + test_phase = "wait lock"; + `wait_lock; + #(PER1*6); + COUNTER_RESET = 1; + #(PER1*19.5) + COUNTER_RESET = 0; + #(PER1*1) + $display ("Timing checks are valid"); + test_phase = "counting"; + #(PER1*COUNT_PHASE); + + $display("SIMULATION PASSED"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + + + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end + + // Instantiation of the example design containing the clock + // network and sampling counters + //--------------------------------------------------------- + b205_clk_gen_exdes + dut + (// Clock in ports + .CLK_IN1 (CLK_IN1), + // Reset for logic in example design + .COUNTER_RESET (COUNTER_RESET), + .CLK_OUT (CLK_OUT), + // High bits of the counters + .COUNT (COUNT), + // Status and control signals + .RESET (RESET), + .LOCKED (LOCKED)); + + +// Freq Check + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/sdf_cmd_file b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/sdf_cmd_file new file mode 100755 index 000000000..755ed5bcf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/sdf_cmd_file @@ -0,0 +1,2 @@ +COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", +SCOPE = b205_clk_gen_tb.dut; diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simcmds.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simcmds.tcl new file mode 100755 index 000000000..8d4b92771 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simcmds.tcl @@ -0,0 +1,9 @@ +# file: simcmds.tcl + +# create the simulation script +vcd dumpfile isim.vcd +vcd dumpvars -m /b205_clk_gen_tb -l 0 +wave add / +run 50000ns +quit + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..45cf4fe5e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_isim.sh @@ -0,0 +1,62 @@ +# file: simulate_isim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# create the project +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../implement/results/routed.v +vlogcomp -work work b205_clk_gen_tb.v + +# compile the project +fuse work.b205_clk_gen_tb work.glbl -L secureip -L simprims_ver -o b205_clk_gen_isim.exe + +# run the simulation script +./b205_clk_gen_isim.exe -tclbatch simcmds.tcl -sdfmax /b205_clk_gen_tb/dut=../../implement/results/routed.sdf + +# run the simulation script +#./b205_clk_gen_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..51d1d37d6 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.bat @@ -0,0 +1,59 @@ +REM file: simulate_mti.bat +REM +REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +REM +REM This file contains confidential and proprietary information +REM of Xilinx, Inc. and is protected under U.S. and +REM international copyright and other intellectual property +REM laws. +REM +REM DISCLAIMER +REM This disclaimer is not a license and does not grant any +REM rights to the materials distributed herewith. Except as +REM otherwise provided in a valid license issued to you by +REM Xilinx, and to the maximum extent permitted by applicable +REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +REM (2) Xilinx shall not be liable (whether in contract or tort, +REM including negligence, or under any other theory of +REM liability) for any loss or damage of any kind or nature +REM related to, arising under or in connection with these +REM materials, including for any direct, or any indirect, +REM special, incidental, or consequential loss or damage +REM (including loss of data, profits, goodwill, or any type of +REM loss or damage suffered as a result of any action brought +REM by a third party) even if such damage or loss was +REM reasonably foreseeable or Xilinx had been advised of the +REM possibility of the same. +REM +REM CRITICAL APPLICATIONS +REM Xilinx products are not designed or intended to be fail- +REM safe, or for use in any application requiring fail-safe +REM performance, such as life-support or safety devices or +REM systems, Class III medical devices, nuclear facilities, +REM applications related to the deployment of airbags, or any +REM other applications that could lead to death, personal +REM injury, or severe property or environmental damage +REM (individually and collectively, "Critical +REM Applications"). Customer assumes the sole risk and +REM liability of any use of Xilinx products in Critical +REM Applications, subject only to applicable laws and +REM regulations governing limitations on product liability. +REM +REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +REM PART OF THIS FILE AT ALL TIMES. +REM +# set up the working directory +set work work +vlib work + +REM compile all of the files +vlog -work work %XILINX%\verilog\src\glbl.v +vlog -work work ..\..\implement\results\routed.v +vlog -work work b205_clk_gen_tb.v + +REM run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..a984ba095 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.do @@ -0,0 +1,65 @@ +# file: simulate_mti.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $env(XILINX)/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b205_clk_gen_tb.v + +# run the simulation +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl +#do wave.do +#log -r /* +run 50000ns + + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..379eb7600 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_mti.sh @@ -0,0 +1,61 @@ +#/bin/sh +# file: simulate_mti.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +set work work +vlib work + +# compile all of the files +vlog -work work $XILINX/verilog/src/glbl.v +vlog -work work ../../implement/results/routed.v +vlog -work work b205_clk_gen_tb.v + +# run the simulation +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax b205_clk_gen_tb/dut=../../implement/results/routed.sdf +no_notifier work.b205_clk_gen_tb work.glbl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..8b73dc5c6 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,64 @@ +#!/bin/sh +# file: simulate_ncsim.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# set up the working directory +mkdir work + +# compile all of the files +ncvlog -work work ${XILINX}/verilog/src/glbl.v +ncvlog -work work ../../implement/results/routed.v +ncvlog -work work b205_clk_gen_tb.v + +# elaborate and run the simulation +ncsdfc ../../implement/results/routed.sdf + +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.b205_clk_gen_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.b205_clk_gen_tb + diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..7ead02584 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/simulate_vcs.sh @@ -0,0 +1,72 @@ +#!/bin/sh +# file: simulate_vcs.sh +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# remove old files +rm -rf simv* csrc DVEfiles AN.DB + +# compile all of the files +# Note that -sverilog is not strictly required- You can +# remove the -sverilog if you change the type of the +# localparam for the periods in the testbench file to +# [63:0] from time + vlogan -sverilog \ + b205_clk_gen_tb.v \ + ../../implement/results/routed.v + + +# prepare the simulation +vcs -sdf max:b205_clk_gen_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug b205_clk_gen_tb.v ../../implement/results/routed.v + +# run the simulation +./simv -ucli -i ucli_commands.key + +# launch the viewer +#dve -vpd vcdplus.vpd -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..0548d1733 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/ucli_commands.key @@ -0,0 +1,5 @@ + +call {$vcdpluson} +run 50000ns +call {$vcdplusclose} +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..1438f6bed --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/vcs_session.tcl @@ -0,0 +1 @@ +gui_open_window Wave diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/wave.do b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/wave.do new file mode 100755 index 000000000..440a8384f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/wave.do @@ -0,0 +1,72 @@ +# file: wave.do +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /b205_clk_gen_tb/CLK_IN1 +add wave -noupdate /b205_clk_gen_tb/COUNT +add wave -noupdate /b205_clk_gen_tb/LOCKED +add wave -noupdate /b205_clk_gen_tb/RESET +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} +configure wave -namecolwidth 238 +configure wave -valuecolwidth 107 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {74848022 ps} diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_flist.txt b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_flist.txt new file mode 100644 index 000000000..2028a2ab7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_flist.txt @@ -0,0 +1,54 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +b205_clk_gen/clk_wiz_v3_6_readme.txt +b205_clk_gen/doc/clk_wiz_v3_6_readme.txt +b205_clk_gen/doc/clk_wiz_v3_6_vinfo.html +b205_clk_gen/doc/pg065_clk_wiz.pdf +b205_clk_gen/example_design/b205_clk_gen_exdes.ucf +b205_clk_gen/example_design/b205_clk_gen_exdes.v +b205_clk_gen/example_design/b205_clk_gen_exdes.xdc +b205_clk_gen/implement/implement.bat +b205_clk_gen/implement/implement.sh +b205_clk_gen/implement/planAhead_ise.bat +b205_clk_gen/implement/planAhead_ise.sh +b205_clk_gen/implement/planAhead_ise.tcl +b205_clk_gen/implement/planAhead_rdn.bat +b205_clk_gen/implement/planAhead_rdn.sh +b205_clk_gen/implement/planAhead_rdn.tcl +b205_clk_gen/implement/xst.prj +b205_clk_gen/implement/xst.scr +b205_clk_gen/simulation/b205_clk_gen_tb.v +b205_clk_gen/simulation/functional/simcmds.tcl +b205_clk_gen/simulation/functional/simulate_isim.bat +b205_clk_gen/simulation/functional/simulate_isim.sh +b205_clk_gen/simulation/functional/simulate_mti.bat +b205_clk_gen/simulation/functional/simulate_mti.do +b205_clk_gen/simulation/functional/simulate_mti.sh +b205_clk_gen/simulation/functional/simulate_ncsim.sh +b205_clk_gen/simulation/functional/simulate_vcs.sh +b205_clk_gen/simulation/functional/ucli_commands.key +b205_clk_gen/simulation/functional/vcs_session.tcl +b205_clk_gen/simulation/functional/wave.do +b205_clk_gen/simulation/functional/wave.sv +b205_clk_gen/simulation/timing/b205_clk_gen_tb.v +b205_clk_gen/simulation/timing/sdf_cmd_file +b205_clk_gen/simulation/timing/simcmds.tcl +b205_clk_gen/simulation/timing/simulate_isim.sh +b205_clk_gen/simulation/timing/simulate_mti.bat +b205_clk_gen/simulation/timing/simulate_mti.do +b205_clk_gen/simulation/timing/simulate_mti.sh +b205_clk_gen/simulation/timing/simulate_ncsim.sh +b205_clk_gen/simulation/timing/simulate_vcs.sh +b205_clk_gen/simulation/timing/ucli_commands.key +b205_clk_gen/simulation/timing/vcs_session.tcl +b205_clk_gen/simulation/timing/wave.do +b205_clk_gen.asy +b205_clk_gen.gise +b205_clk_gen.ucf +b205_clk_gen.v +b205_clk_gen.veo +b205_clk_gen.xco +b205_clk_gen.xdc +b205_clk_gen.xise +b205_clk_gen_flist.txt +b205_clk_gen_xmdf.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_xmdf.tcl new file mode 100755 index 000000000..9b1f239ac --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen_xmdf.tcl @@ -0,0 +1,140 @@ +# The package naming convention is _xmdf +package provide b205_clk_gen_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::b205_clk_gen_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::b205_clk_gen_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name b205_clk_gen +} +# ::b205_clk_gen_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::b205_clk_gen_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/b205_clk_gen_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path b205_clk_gen_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module b205_clk_gen +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.asy b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.asy new file mode 100644 index 000000000..a0153d32c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.asy @@ -0,0 +1,9 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_icon +RECTANGLE Normal 32 32 544 864 +LINE Wide 576 112 544 112 +PIN 576 112 RIGHT 36 +PINATTR PinName control0[35:0] +PINATTR Polarity BOTH + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.ucf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.xdc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ncf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ngc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ngc new file mode 100644 index 000000000..1beaa38c9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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3`=92c:i7>5;h03>5<1<75f5e83>>i?j3:17pl6e;291?6=8r.2m78=;I3;6>N6?m1/4>4>b49'2c<63`;n6=44i3294?=n;=0;66g:d;29?j>e2900qo7i:186>5<7s-3j6;<4H0:1?M70l2.3?7?m5:&5b?7>o4<3:17d;k:188k=d=831vnl>50;794?6|,0k1:?5G1908L41c3-2864=n9l0;66g=0;29?l532900e8j50;9l5}#1h0=>6F>839K52b<,191=o;4$7d95>o6m3:17d7>55;294~">i3<97E?72:J23a=#0:0:n85+6g82?l7b2900e?>50;9j71<722c>h7>5;n:a>5<"?;3;i96*9f;38m4c=831b>=4?::k00?6=3`?o6=44o9`94?=zjho1<7;50;2x 428h>7)8i:0;8 =?=91h0e;750;9j2d<722c=n7>5;h4`>5<428h>7)8i:018 =?=90<0e;750;9j2d<722c=n7>5;h4`>5<428h>7)8i:d9'<<<61m1b:44?::k5e?6=3`0<729q/5l489:J2<7=O9>n0(5=51c78 3`=l2.357?6d:k5=?6=3`j0;66a72;29?xde?3:197>50z&:e?1>3A;3>6F>7e9'<6<6j<1/:k4l;%::>4?b3`<26=44i7c94?=n>k0;66g9c;29?j>52900qol9:186>5<7s-3j6:74H0:1?M70l2.3?7?m5:&5b?g<,131=4k4i7;94?=n>h0;66g9b;29?l0d2900c5<50;9~fg3=83?1<7>t$8c93<=O9180D<9k;%:0>4d23-00;66g9a;29?l0e2900e;m50;9l<7<722win94?:483>5}#1h0<56F>839K52b<,191=o;4$7d9<>"?13;2j6g99;29?l0f2900e;l50;9j2f<722e3>7>5;|`a7?6==3:1o0<7)66:0c3?l0>2900e;o50;9j2g<722c=o7>5;n:1>5<30D<6=;I34`>"?;3;i96*9f;48 =?=9h:0e;750;9j2d<722c=n7>5;h4`>5<a09j2<<722c=m7>5;h4a>5<>{ej90;684?:1y'=d<012B:4?5G16f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ucf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ucf new file mode 100644 index 000000000..b83296f8e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.ucf @@ -0,0 +1,9 @@ +NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ; +TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ; +#Update Constraints +NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ; +NET "U0/iSHIFT_OUT" TIG ; +TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ; +TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ; +TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ; +TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ; diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.v b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.v new file mode 100644 index 000000000..24282de22 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.v @@ -0,0 +1,27 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2015 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.6 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.v +// /___/ /\ Timestamp : Tue Apr 14 17:06:06 PDT 2015 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_icon( + CONTROL0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL0; + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.veo b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.veo new file mode 100644 index 000000000..094dbf8de --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.veo @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2015 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.6 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_icon.veo +// /___/ /\ Timestamp : Tue Apr 14 17:06:06 PDT 2015 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_icon YourInstanceName ( + .CONTROL0(CONTROL0) // INOUT BUS [35:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xco b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xco new file mode 100644 index 000000000..211cf181f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xco @@ -0,0 +1,56 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Wed Apr 15 00:05:36 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a +# END Select +# BEGIN Parameters +CSET component_name=chipscope_icon +CSET constraint_type=external +CSET enable_jtag_bufg=true +CSET example_design=false +CSET number_control_ports=1 +CSET use_ext_bscan=false +CSET use_softbscan=false +CSET use_unused_bscan=false +CSET user_scan_chain=USER1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-06-08T17:28:33Z +# END Extra information +GENERATE +# CRC: b52cbe62 diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xdc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xdc new file mode 100644 index 000000000..903799425 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.xdc @@ -0,0 +1,7 @@ +# icon XDC +create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] +create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}] +set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}] +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2 +set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1 +set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK} diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_flist.txt b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_flist.txt new file mode 100644 index 000000000..bf55dc492 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_flist.txt @@ -0,0 +1,15 @@ +# Output products list for +chipscope_icon.asy +chipscope_icon.constraints/chipscope_icon.ucf +chipscope_icon.constraints/chipscope_icon.xdc +chipscope_icon.gise +chipscope_icon.ngc +chipscope_icon.ucf +chipscope_icon.v +chipscope_icon.veo +chipscope_icon.xco +chipscope_icon.xdc +chipscope_icon.xise +chipscope_icon_flist.txt +chipscope_icon_readme.txt +chipscope_icon_xmdf.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_readme.txt new file mode 100644 index 000000000..304eb5252 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_readme.txt @@ -0,0 +1,45 @@ +The following files were generated for 'chipscope_icon' in directory +/home/mwest/git/fpgadev/usrp3/top/b205/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_icon.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_icon.constraints/chipscope_icon.ucf + * chipscope_icon.constraints/chipscope_icon.xdc + * chipscope_icon.ngc + * chipscope_icon.ucf + * chipscope_icon.v + * chipscope_icon.veo + * chipscope_icon.xdc + * chipscope_icon_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_icon.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * chipscope_icon.gise + * chipscope_icon.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_icon_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_icon_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_xmdf.tcl new file mode 100755 index 000000000..241f4d5ae --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon_xmdf.tcl @@ -0,0 +1,88 @@ +# The package naming convention is _xmdf +package provide chipscope_icon_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_icon_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_icon_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_icon +} +# ::chipscope_icon_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_icon_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.constraints/chipscope_icon.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xcf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_icon_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_icon +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.asy b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.asy new file mode 100644 index 000000000..4b7848a2a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.asy @@ -0,0 +1,17 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 chipscope_ila +RECTANGLE Normal 32 32 288 704 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName control[35:0] +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName trig0[127:0] +PINATTR Polarity IN + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.cdc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.cdc new file mode 100644 index 000000000..3cb2c112f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.cdc @@ -0,0 +1,144 @@ +#ChipScope Core Generator Project File Version 3.0 +#Tue Jun 30 11:48:11 PDT 2015 +SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 +SignalExport.bus<0000>.name=TRIG0 +SignalExport.bus<0000>.offset=0.0 +SignalExport.bus<0000>.precision=0 +SignalExport.bus<0000>.radix=Bin +SignalExport.bus<0000>.scaleFactor=1.0 +SignalExport.clockChannel=CLK +SignalExport.dataEqualsTrigger=true +SignalExport.triggerChannel<0000><0000>=TRIG0[0] +SignalExport.triggerChannel<0000><0001>=TRIG0[1] +SignalExport.triggerChannel<0000><0002>=TRIG0[2] +SignalExport.triggerChannel<0000><0003>=TRIG0[3] +SignalExport.triggerChannel<0000><0004>=TRIG0[4] +SignalExport.triggerChannel<0000><0005>=TRIG0[5] +SignalExport.triggerChannel<0000><0006>=TRIG0[6] +SignalExport.triggerChannel<0000><0007>=TRIG0[7] +SignalExport.triggerChannel<0000><0008>=TRIG0[8] +SignalExport.triggerChannel<0000><0009>=TRIG0[9] +SignalExport.triggerChannel<0000><0010>=TRIG0[10] +SignalExport.triggerChannel<0000><0011>=TRIG0[11] +SignalExport.triggerChannel<0000><0012>=TRIG0[12] +SignalExport.triggerChannel<0000><0013>=TRIG0[13] +SignalExport.triggerChannel<0000><0014>=TRIG0[14] +SignalExport.triggerChannel<0000><0015>=TRIG0[15] +SignalExport.triggerChannel<0000><0016>=TRIG0[16] +SignalExport.triggerChannel<0000><0017>=TRIG0[17] +SignalExport.triggerChannel<0000><0018>=TRIG0[18] +SignalExport.triggerChannel<0000><0019>=TRIG0[19] +SignalExport.triggerChannel<0000><0020>=TRIG0[20] +SignalExport.triggerChannel<0000><0021>=TRIG0[21] +SignalExport.triggerChannel<0000><0022>=TRIG0[22] +SignalExport.triggerChannel<0000><0023>=TRIG0[23] +SignalExport.triggerChannel<0000><0024>=TRIG0[24] +SignalExport.triggerChannel<0000><0025>=TRIG0[25] +SignalExport.triggerChannel<0000><0026>=TRIG0[26] +SignalExport.triggerChannel<0000><0027>=TRIG0[27] +SignalExport.triggerChannel<0000><0028>=TRIG0[28] +SignalExport.triggerChannel<0000><0029>=TRIG0[29] +SignalExport.triggerChannel<0000><0030>=TRIG0[30] +SignalExport.triggerChannel<0000><0031>=TRIG0[31] +SignalExport.triggerChannel<0000><0032>=TRIG0[32] +SignalExport.triggerChannel<0000><0033>=TRIG0[33] +SignalExport.triggerChannel<0000><0034>=TRIG0[34] +SignalExport.triggerChannel<0000><0035>=TRIG0[35] +SignalExport.triggerChannel<0000><0036>=TRIG0[36] +SignalExport.triggerChannel<0000><0037>=TRIG0[37] +SignalExport.triggerChannel<0000><0038>=TRIG0[38] +SignalExport.triggerChannel<0000><0039>=TRIG0[39] +SignalExport.triggerChannel<0000><0040>=TRIG0[40] +SignalExport.triggerChannel<0000><0041>=TRIG0[41] +SignalExport.triggerChannel<0000><0042>=TRIG0[42] +SignalExport.triggerChannel<0000><0043>=TRIG0[43] +SignalExport.triggerChannel<0000><0044>=TRIG0[44] +SignalExport.triggerChannel<0000><0045>=TRIG0[45] +SignalExport.triggerChannel<0000><0046>=TRIG0[46] +SignalExport.triggerChannel<0000><0047>=TRIG0[47] +SignalExport.triggerChannel<0000><0048>=TRIG0[48] +SignalExport.triggerChannel<0000><0049>=TRIG0[49] +SignalExport.triggerChannel<0000><0050>=TRIG0[50] +SignalExport.triggerChannel<0000><0051>=TRIG0[51] +SignalExport.triggerChannel<0000><0052>=TRIG0[52] +SignalExport.triggerChannel<0000><0053>=TRIG0[53] +SignalExport.triggerChannel<0000><0054>=TRIG0[54] +SignalExport.triggerChannel<0000><0055>=TRIG0[55] +SignalExport.triggerChannel<0000><0056>=TRIG0[56] +SignalExport.triggerChannel<0000><0057>=TRIG0[57] +SignalExport.triggerChannel<0000><0058>=TRIG0[58] +SignalExport.triggerChannel<0000><0059>=TRIG0[59] +SignalExport.triggerChannel<0000><0060>=TRIG0[60] +SignalExport.triggerChannel<0000><0061>=TRIG0[61] +SignalExport.triggerChannel<0000><0062>=TRIG0[62] +SignalExport.triggerChannel<0000><0063>=TRIG0[63] +SignalExport.triggerChannel<0000><0064>=TRIG0[64] +SignalExport.triggerChannel<0000><0065>=TRIG0[65] +SignalExport.triggerChannel<0000><0066>=TRIG0[66] +SignalExport.triggerChannel<0000><0067>=TRIG0[67] +SignalExport.triggerChannel<0000><0068>=TRIG0[68] +SignalExport.triggerChannel<0000><0069>=TRIG0[69] +SignalExport.triggerChannel<0000><0070>=TRIG0[70] +SignalExport.triggerChannel<0000><0071>=TRIG0[71] +SignalExport.triggerChannel<0000><0072>=TRIG0[72] +SignalExport.triggerChannel<0000><0073>=TRIG0[73] +SignalExport.triggerChannel<0000><0074>=TRIG0[74] +SignalExport.triggerChannel<0000><0075>=TRIG0[75] +SignalExport.triggerChannel<0000><0076>=TRIG0[76] +SignalExport.triggerChannel<0000><0077>=TRIG0[77] +SignalExport.triggerChannel<0000><0078>=TRIG0[78] +SignalExport.triggerChannel<0000><0079>=TRIG0[79] +SignalExport.triggerChannel<0000><0080>=TRIG0[80] +SignalExport.triggerChannel<0000><0081>=TRIG0[81] +SignalExport.triggerChannel<0000><0082>=TRIG0[82] +SignalExport.triggerChannel<0000><0083>=TRIG0[83] +SignalExport.triggerChannel<0000><0084>=TRIG0[84] +SignalExport.triggerChannel<0000><0085>=TRIG0[85] +SignalExport.triggerChannel<0000><0086>=TRIG0[86] +SignalExport.triggerChannel<0000><0087>=TRIG0[87] +SignalExport.triggerChannel<0000><0088>=TRIG0[88] +SignalExport.triggerChannel<0000><0089>=TRIG0[89] +SignalExport.triggerChannel<0000><0090>=TRIG0[90] +SignalExport.triggerChannel<0000><0091>=TRIG0[91] +SignalExport.triggerChannel<0000><0092>=TRIG0[92] +SignalExport.triggerChannel<0000><0093>=TRIG0[93] +SignalExport.triggerChannel<0000><0094>=TRIG0[94] +SignalExport.triggerChannel<0000><0095>=TRIG0[95] +SignalExport.triggerChannel<0000><0096>=TRIG0[96] +SignalExport.triggerChannel<0000><0097>=TRIG0[97] +SignalExport.triggerChannel<0000><0098>=TRIG0[98] +SignalExport.triggerChannel<0000><0099>=TRIG0[99] +SignalExport.triggerChannel<0000><0100>=TRIG0[100] +SignalExport.triggerChannel<0000><0101>=TRIG0[101] +SignalExport.triggerChannel<0000><0102>=TRIG0[102] +SignalExport.triggerChannel<0000><0103>=TRIG0[103] +SignalExport.triggerChannel<0000><0104>=TRIG0[104] +SignalExport.triggerChannel<0000><0105>=TRIG0[105] +SignalExport.triggerChannel<0000><0106>=TRIG0[106] +SignalExport.triggerChannel<0000><0107>=TRIG0[107] +SignalExport.triggerChannel<0000><0108>=TRIG0[108] +SignalExport.triggerChannel<0000><0109>=TRIG0[109] +SignalExport.triggerChannel<0000><0110>=TRIG0[110] +SignalExport.triggerChannel<0000><0111>=TRIG0[111] +SignalExport.triggerChannel<0000><0112>=TRIG0[112] +SignalExport.triggerChannel<0000><0113>=TRIG0[113] +SignalExport.triggerChannel<0000><0114>=TRIG0[114] +SignalExport.triggerChannel<0000><0115>=TRIG0[115] +SignalExport.triggerChannel<0000><0116>=TRIG0[116] +SignalExport.triggerChannel<0000><0117>=TRIG0[117] +SignalExport.triggerChannel<0000><0118>=TRIG0[118] +SignalExport.triggerChannel<0000><0119>=TRIG0[119] +SignalExport.triggerChannel<0000><0120>=TRIG0[120] +SignalExport.triggerChannel<0000><0121>=TRIG0[121] +SignalExport.triggerChannel<0000><0122>=TRIG0[122] +SignalExport.triggerChannel<0000><0123>=TRIG0[123] +SignalExport.triggerChannel<0000><0124>=TRIG0[124] +SignalExport.triggerChannel<0000><0125>=TRIG0[125] +SignalExport.triggerChannel<0000><0126>=TRIG0[126] +SignalExport.triggerChannel<0000><0127>=TRIG0[127] +SignalExport.triggerPort<0000>.name=TRIG0 +SignalExport.triggerPortCount=1 +SignalExport.triggerPortIsData<0000>=true +SignalExport.triggerPortWidth<0000>=128 +SignalExport.type=ila + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.ucf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.ucf new file mode 100644 index 000000000..c94e639df --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.xdc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.constraints/chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ncf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ncf new file mode 100644 index 000000000..6be9051a2 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ncf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ngc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ngc new file mode 100644 index 000000000..1c4da9412 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ucf b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ucf new file mode 100644 index 000000000..c94e639df --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.ucf @@ -0,0 +1,15 @@ +# +# Clock constraints +# +NET "CLK" TNM_NET = D_CLK ; +INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK; +TIMESPEC TS_D2_TO_T2_chipscope_ila = FROM D2_CLK TO "FFS" TIG; +TIMESPEC TS_J2_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J3_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; +TIMESPEC TS_J4_TO_D2_chipscope_ila = FROM "FFS" TO D2_CLK TIG; + +# +# Input keep/save net constraints +# +NET "TRIG0<*" S; +NET "TRIG0<*" KEEP; diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.v b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.v new file mode 100644 index 000000000..e231eaf35 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2015 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.7 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila.v +// /___/ /\ Timestamp : Tue Jun 30 11:48:11 PDT 2015 +// \ \ / \ +// \___\/\___\ +// +// Design Name: Verilog Synthesis Wrapper +/////////////////////////////////////////////////////////////////////////////// +// This wrapper is used to integrate with Project Navigator and PlanAhead + +`timescale 1ns/1ps + +module chipscope_ila( + CONTROL, + CLK, + TRIG0) /* synthesis syn_black_box syn_noprune=1 */; + + +inout [35 : 0] CONTROL; +input CLK; +input [127 : 0] TRIG0; + +endmodule diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.veo b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.veo new file mode 100644 index 000000000..4c4ce1250 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.veo @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2015 Xilinx, Inc. +// All Rights Reserved +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 14.7 +// \ \ Application: Xilinx CORE Generator +// / / Filename : chipscope_ila.veo +// /___/ /\ Timestamp : Tue Jun 30 11:48:11 PDT 2015 +// \ \ / \ +// \___\/\___\ +// +// Design Name: ISE Instantiation template +/////////////////////////////////////////////////////////////////////////////// + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +chipscope_ila YourInstanceName ( + .CONTROL(CONTROL), // INOUT BUS [35:0] + .CLK(CLK), // IN + .TRIG0(TRIG0) // IN BUS [127:0] +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xco b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xco new file mode 100644 index 000000000..823a5cccf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xco @@ -0,0 +1,141 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jun 30 18:46:21 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Structural +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a +# END Select +# BEGIN Parameters +CSET check_bramcount=false +CSET component_name=chipscope_ila +CSET constraint_type=external +CSET counter_width_1=Disabled +CSET counter_width_10=Disabled +CSET counter_width_11=Disabled +CSET counter_width_12=Disabled +CSET counter_width_13=Disabled +CSET counter_width_14=Disabled +CSET counter_width_15=Disabled +CSET counter_width_16=Disabled +CSET counter_width_2=Disabled +CSET counter_width_3=Disabled +CSET counter_width_4=Disabled +CSET counter_width_5=Disabled +CSET counter_width_6=Disabled +CSET counter_width_7=Disabled +CSET counter_width_8=Disabled +CSET counter_width_9=Disabled +CSET data_port_width=0 +CSET data_same_as_trigger=true +CSET disable_save_keep=false +CSET enable_storage_qualification=true +CSET enable_trigger_output_port=false +CSET example_design=false +CSET exclude_from_data_storage_1=false +CSET exclude_from_data_storage_10=false +CSET exclude_from_data_storage_11=false +CSET exclude_from_data_storage_12=false +CSET exclude_from_data_storage_13=false +CSET exclude_from_data_storage_14=false +CSET exclude_from_data_storage_15=false +CSET exclude_from_data_storage_16=false +CSET exclude_from_data_storage_2=false +CSET exclude_from_data_storage_3=false +CSET exclude_from_data_storage_4=false +CSET exclude_from_data_storage_5=false +CSET exclude_from_data_storage_6=false +CSET exclude_from_data_storage_7=false +CSET exclude_from_data_storage_8=false +CSET exclude_from_data_storage_9=false +CSET match_type_1=basic_with_edges +CSET match_type_10=basic_with_edges +CSET match_type_11=basic_with_edges +CSET match_type_12=basic_with_edges +CSET match_type_13=basic_with_edges +CSET match_type_14=basic_with_edges +CSET match_type_15=basic_with_edges +CSET match_type_16=basic_with_edges +CSET match_type_2=basic_with_edges +CSET match_type_3=basic_with_edges +CSET match_type_4=basic_with_edges +CSET match_type_5=basic_with_edges +CSET match_type_6=basic_with_edges +CSET match_type_7=basic_with_edges +CSET match_type_8=basic_with_edges +CSET match_type_9=basic_with_edges +CSET match_units_1=1 +CSET match_units_10=1 +CSET match_units_11=1 +CSET match_units_12=1 +CSET match_units_13=1 +CSET match_units_14=1 +CSET match_units_15=1 +CSET match_units_16=1 +CSET match_units_2=1 +CSET match_units_3=1 +CSET match_units_4=1 +CSET match_units_5=1 +CSET match_units_6=1 +CSET match_units_7=1 +CSET match_units_8=1 +CSET match_units_9=1 +CSET max_sequence_levels=1 +CSET number_of_trigger_ports=1 +CSET sample_data_depth=1024 +CSET sample_on=Rising +CSET trigger_port_width_1=128 +CSET trigger_port_width_10=8 +CSET trigger_port_width_11=8 +CSET trigger_port_width_12=8 +CSET trigger_port_width_13=8 +CSET trigger_port_width_14=8 +CSET trigger_port_width_15=8 +CSET trigger_port_width_16=8 +CSET trigger_port_width_2=8 +CSET trigger_port_width_3=8 +CSET trigger_port_width_4=8 +CSET trigger_port_width_5=8 +CSET trigger_port_width_6=8 +CSET trigger_port_width_7=8 +CSET trigger_port_width_8=8 +CSET trigger_port_width_9=8 +CSET use_rpms=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-10-13T14:13:15Z +# END Extra information +GENERATE +# CRC: 76868b6e diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xdc b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xdc new file mode 100644 index 000000000..49e2b9e7b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila.xdc @@ -0,0 +1,6 @@ +# +# Clock constraints +# +set_false_path -from [get_cells U0/*/U_STAT/U_DIRTY_LDC] -to [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] +set_false_path -from [get_cells -of_objects [filter [all_fanout -flat -endpoints_only -from [get_nets CONTROL[0]]] IS_CLOCK]] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] +set_false_path -from [get_cells U0/*/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD] -to [get_cells U0/*/U_STAT/U_DIRTY_LDC] diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_flist.txt b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_flist.txt new file mode 100644 index 000000000..5c3195e53 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +chipscope_ila.asy +chipscope_ila.cdc +chipscope_ila.constraints/chipscope_ila.ucf +chipscope_ila.constraints/chipscope_ila.xdc +chipscope_ila.gise +chipscope_ila.ncf +chipscope_ila.ngc +chipscope_ila.ucf +chipscope_ila.v +chipscope_ila.veo +chipscope_ila.xco +chipscope_ila.xdc +chipscope_ila.xise +chipscope_ila_flist.txt +chipscope_ila_readme.txt +chipscope_ila_xmdf.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_readme.txt new file mode 100644 index 000000000..9d997cd6f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_readme.txt @@ -0,0 +1,48 @@ +The following files were generated for 'chipscope_ila' in directory +/home/mwest/git/fpgadev/usrp3/top/b205/coregen/ + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * chipscope_ila.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * chipscope_ila.cdc + * chipscope_ila.constraints/chipscope_ila.ucf + * chipscope_ila.constraints/chipscope_ila.xdc + * chipscope_ila.ncf + * chipscope_ila.ngc + * chipscope_ila.ucf + * chipscope_ila.v + * chipscope_ila.veo + * chipscope_ila.xdc + * chipscope_ila_xmdf.tcl + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * chipscope_ila.asy + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * _xmsgs/pn_parser.xmsgs + * chipscope_ila.gise + * chipscope_ila.xise + +Deliver Readme: + Readme file for the IP. + + * chipscope_ila_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * chipscope_ila_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_xmdf.tcl new file mode 100755 index 000000000..b18241e0b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/chipscope_ila_xmdf.tcl @@ -0,0 +1,87 @@ +# The package naming convention is _xmdf +package provide chipscope_ila_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::chipscope_ila_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::chipscope_ila_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name chipscope_ila +} +# ::chipscope_ila_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::chipscope_ila_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.cdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ucf +incr fcount + + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ncf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ncf +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.constraints/chipscope_ila.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Xdc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path chipscope_ila_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module chipscope_ila +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams + diff --git a/fpga/usrp3/top/b2xxmini/coregen/coregen.cgp b/fpga/usrp3/top/b2xxmini/coregen/coregen.cgp new file mode 100644 index 000000000..127790678 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx150 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET package = csg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.asy b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.asy new file mode 100644 index 000000000..fd6eef6f7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_4k_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[9:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[9:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.ncf b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.ngc b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.ngc new file mode 100644 index 000000000..61795f415 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ +fifo_generator_v9_3_vinfo + + + + + + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd new file mode 100755 index 000000000..2674443c8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_4k_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_4k_2clk_exdes; + + + +architecture xilinx of fifo_4k_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_4k_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_4k_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.bat new file mode 100755 index 000000000..e6d9fb0f6 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_4k_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.sh new file mode 100755 index 000000000..0b56fa62c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_4k_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..e0e613a94 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_4k_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_4k_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..fa07eb47d --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_4k_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_4k_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_4k_2clk_exdes + +echo 'Running map' +map fifo_4k_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_4k_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..a48fea790 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_4k_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..7171a0e5e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_4k_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..98c6556e8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75csg484-3 +set projName fifo_4k_2clk +set design fifo_4k_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_4k_2clk_exdes +add_files -norecurse {../../example_design/fifo_4k_2clk_exdes.vhd} +add_files -norecurse {./fifo_4k_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_4k_2clk_exdes.xdc} +set_property top fifo_4k_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_4k_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_4k_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.prj b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.prj new file mode 100755 index 000000000..573a1716f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_4k_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.scr b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.scr new file mode 100755 index 000000000..11c7d5a89 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_4k_2clk_exdes +-p xc6slx75-csg484-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_4k_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd new file mode 100755 index 000000000..d14bb7a51 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_4k_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd new file mode 100755 index 000000000..0a7c2aa87 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_4k_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd new file mode 100755 index 000000000..fa32e4781 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_4k_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_4k_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd new file mode 100755 index 000000000..46d4ac9cf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_4k_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_4k_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_4k_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_4k_2clk_pkg; + + + +PACKAGE BODY fifo_4k_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_4k_2clk_pkg; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd new file mode 100755 index 000000000..bed58d88e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_4k_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_4k_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd new file mode 100755 index 000000000..4149735c5 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_4k_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_4k_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_4k_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_4k_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_4k_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 9, + C_RD_PNTR_WIDTH => 9, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_4k_2clk_inst : fifo_4k_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd new file mode 100755 index 000000000..51d699e21 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_4k_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_4k_2clk_pkg.ALL; + +ENTITY fifo_4k_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_4k_2clk_arch OF fifo_4k_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_4k_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_4k_2clk_synth + + fifo_4k_2clk_synth_inst:fifo_4k_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 76 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..3d0783055 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_4k_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..c3abd5a51 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_4k_2clk.v +vhpcomp -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_4k_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..af53abefb --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_4k_2clk.v +vcom -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..0d3376452 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_4k_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..8c26af20c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_4k_2clk.v +vhdlan ../../example_design/fifo_4k_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..b9ef9837a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..a6f8ce91f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_4k_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_4k_2clk_rng.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_4k_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_4k_2clk_synth.vhd +vhpcomp -work work ..\\fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +.\\fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..f5ad36b7e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_4k_2clk_pkg.vhd +vhpcomp -work work ../fifo_4k_2clk_rng.vhd +vhpcomp -work work ../fifo_4k_2clk_dgen.vhd +vhpcomp -work work ../fifo_4k_2clk_dverif.vhd +vhpcomp -work work ../fifo_4k_2clk_pctrl.vhd +vhpcomp -work work ../fifo_4k_2clk_synth.vhd +vhpcomp -work work ../fifo_4k_2clk_tb.vhd + +fuse work.fifo_4k_2clk_tb work.glbl -L simprims_ver -o fifo_4k_2clk_tb.exe + +./fifo_4k_2clk_tb.exe -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..74e930a13 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_4k_2clk_pkg.vhd +vcom -work work ../fifo_4k_2clk_rng.vhd +vcom -work work ../fifo_4k_2clk_dgen.vhd +vcom -work work ../fifo_4k_2clk_dverif.vhd +vcom -work work ../fifo_4k_2clk_pctrl.vhd +vcom -work work ../fifo_4k_2clk_synth.vhd +vcom -work work ../fifo_4k_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst=../../implement/results/routed.sdf work.fifo_4k_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..a1967adcf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_4k_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_4k_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_4k_2clk_synth_inst:fifo_4k_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_4k_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_4k_2clk_tb diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..f62f540be --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_4k_2clk_pkg.vhd +vhdlan ../fifo_4k_2clk_rng.vhd +vhdlan ../fifo_4k_2clk_dgen.vhd +vhdlan ../fifo_4k_2clk_dverif.vhd +vhdlan ../fifo_4k_2clk_pctrl.vhd +vhdlan ../fifo_4k_2clk_synth.vhd +vhdlan ../fifo_4k_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_4k_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..9c95a2ade --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_4k_2clk.vpd -type VPD +dump -add fifo_4k_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..28ebc1163 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_4k_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_4k_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_4k_2clk_Group +gui_list_add_group -id Wave.1 {fifo_4k_2clk_Group} + +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +gui_sg_addsignal -group fifo_4k_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +gui_sg_addsignal -group fifo_4k_2clk_Group READ -divider +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_4k_2clk_Group /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..10be1a965 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +wave add /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..adc4cb8d7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +add wave -noupdate /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..51819bad9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/WR_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_CLK +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/RD_EN +waveform add -signals /fifo_4k_2clk_tb/fifo_4k_2clk_synth_inst/fifo_4k_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_flist.txt b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_flist.txt new file mode 100644 index 000000000..a0152ac70 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_flist.txt @@ -0,0 +1,57 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_4k_2clk/doc/pg057-fifo-generator.pdf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +fifo_4k_2clk/fifo_generator_v9_3_readme.txt +fifo_4k_2clk/implement/implement.bat +fifo_4k_2clk/implement/implement.sh +fifo_4k_2clk/implement/implement_synplify.bat +fifo_4k_2clk/implement/implement_synplify.sh +fifo_4k_2clk/implement/planAhead_ise.bat +fifo_4k_2clk/implement/planAhead_ise.sh +fifo_4k_2clk/implement/planAhead_ise.tcl +fifo_4k_2clk/implement/xst.prj +fifo_4k_2clk/implement/xst.scr +fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +fifo_4k_2clk/simulation/functional/simulate_isim.bat +fifo_4k_2clk/simulation/functional/simulate_isim.sh +fifo_4k_2clk/simulation/functional/simulate_mti.bat +fifo_4k_2clk/simulation/functional/simulate_mti.do +fifo_4k_2clk/simulation/functional/simulate_mti.sh +fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +fifo_4k_2clk/simulation/functional/simulate_vcs.sh +fifo_4k_2clk/simulation/functional/ucli_commands.key +fifo_4k_2clk/simulation/functional/vcs_session.tcl +fifo_4k_2clk/simulation/functional/wave_isim.tcl +fifo_4k_2clk/simulation/functional/wave_mti.do +fifo_4k_2clk/simulation/functional/wave_ncsim.sv +fifo_4k_2clk/simulation/timing/simulate_isim.bat +fifo_4k_2clk/simulation/timing/simulate_isim.sh +fifo_4k_2clk/simulation/timing/simulate_mti.bat +fifo_4k_2clk/simulation/timing/simulate_mti.do +fifo_4k_2clk/simulation/timing/simulate_mti.sh +fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +fifo_4k_2clk/simulation/timing/simulate_vcs.sh +fifo_4k_2clk/simulation/timing/ucli_commands.key +fifo_4k_2clk/simulation/timing/vcs_session.tcl +fifo_4k_2clk/simulation/timing/wave_isim.tcl +fifo_4k_2clk/simulation/timing/wave_mti.do +fifo_4k_2clk/simulation/timing/wave_ncsim.sv +fifo_4k_2clk.asy +fifo_4k_2clk.gise +fifo_4k_2clk.ngc +fifo_4k_2clk.v +fifo_4k_2clk.veo +fifo_4k_2clk.xco +fifo_4k_2clk.xise +fifo_4k_2clk_flist.txt +fifo_4k_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_xmdf.tcl new file mode 100644 index 000000000..bdc5c355d --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_4k_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_4k_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_4k_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_4k_2clk +} +# ::fifo_4k_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_4k_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/example_design/fifo_4k_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/fifo_4k_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_4k_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_4k_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.asy b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.asy new file mode 100644 index 000000000..1c03599f3 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_short_2clk +RECTANGLE Normal 32 32 800 4064 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din[71:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 464 32 464 +PIN 0 464 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName wr_data_count[5:0] +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[71:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 832 656 800 656 +PIN 832 656 RIGHT 36 +PINATTR PinName rd_data_count[5:0] +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.ncf b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.ncf new file mode 100644 index 000000000..e69de29bb diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.ngc b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.ngc new file mode 100644 index 000000000..6d6ba3499 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ +fifo_generator_v9_3_vinfo + + + +

+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf new file mode 100644 index 000000000..5ec45fbcb Binary files /dev/null and b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/doc/pg057-fifo-generator.pdf differ diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf new file mode 100755 index 000000000..62e5058ab --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. + NET "RD_CLK" TNM_NET = "RD_CLK"; + NET "WR_CLK" TNM_NET = "WR_CLK"; + TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" 50 MHZ; + TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 50 MHZ; +################################################################################ diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd new file mode 100755 index 000000000..9e38bcb7c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core - core top file for implementation +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_exdes.vhd +-- +-- Description: +-- This is the FIFO core wrapper with BUFG instances for clock connections. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity fifo_short_2clk_exdes is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + +end fifo_short_2clk_exdes; + + + +architecture xilinx of fifo_short_2clk_exdes is + + signal wr_clk_i : std_logic; + signal rd_clk_i : std_logic; + + + + component fifo_short_2clk is + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + end component; + + +begin + + wr_clk_buf: bufg + PORT map( + i => WR_CLK, + o => wr_clk_i + ); + + rd_clk_buf: bufg + PORT map( + i => RD_CLK, + o => rd_clk_i + ); + + + exdes_inst : fifo_short_2clk + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +end xilinx; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt new file mode 100644 index 000000000..7853ebde8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/fifo_generator_v9_3_readme.txt @@ -0,0 +1,236 @@ +CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + - IP level constraint for Built-in FIFO reset synchronizer + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Importing an XCO file alters the XCO configurations + + Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + + CR 467240 + AR 31379 + + 2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed + + Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, + correct behavior of the FIFO status flags cannot be guaranteed after the first write. + + Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK. + For more information and additional workaround see Answer Record 41099. + + 5.2 Vivado + + The following are known issues for v9.3 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes User Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer +10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO +07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO +04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support + AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO +01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support +10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support +06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support +10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.bat new file mode 100755 index 000000000..8745ae5d9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.bat @@ -0,0 +1,88 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy fifo_short_2clk_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.sh new file mode 100755 index 000000000..3a143e17c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement.sh @@ -0,0 +1,87 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp fifo_short_2clk_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.bat new file mode 100755 index 000000000..ac8f61fea --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.bat @@ -0,0 +1,87 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\fifo_short_2clk.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\fifo_short_2clk_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.sh new file mode 100755 index 000000000..0ae5d7af5 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/implement_synplify.sh @@ -0,0 +1,86 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../fifo_short_2clk.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/fifo_short_2clk_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' + +ngdbuild -p xc6slx75-csg484-3 -sd ../../../ fifo_short_2clk_exdes + +echo 'Running map' +map fifo_short_2clk_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm fifo_short_2clk_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.bat new file mode 100755 index 000000000..49053fd63 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\fifo_short_2clk.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.sh new file mode 100755 index 000000000..42916c2bc --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../fifo_short_2clk.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.tcl new file mode 100755 index 000000000..d2c954858 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx75csg484-3 +set projName fifo_short_2clk +set design fifo_short_2clk +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module fifo_short_2clk_exdes +add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd} +add_files -norecurse {./fifo_short_2clk.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc} +set_property top fifo_short_2clk_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.prj b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.prj new file mode 100755 index 000000000..f16af4308 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/fifo_short_2clk_exdes.vhd diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.scr b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.scr new file mode 100755 index 000000000..7dcd7b83c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent fifo_short_2clk_exdes +-p xc6slx75-csg484-3 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn fifo_short_2clk_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd new file mode 100755 index 000000000..bc7a1b525 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd @@ -0,0 +1,123 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dgen.vhd +-- +-- Description: +-- Used for write interface stimulus generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_dg_arch OF fifo_short_2clk_dgen IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + + SIGNAL pr_w_en : STD_LOGIC := '0'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + BEGIN + + WR_EN <= PRC_WR_EN ; + WR_DATA <= wr_data_i AFTER 100 ns; + + ---------------------------------------------- + -- Generation of DATA + ---------------------------------------------- + gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst1:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_w_en + ); + END GENERATE; + + pr_w_en <= PRC_WR_EN AND NOT FULL; + wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0); + + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd new file mode 100755 index 000000000..b0465d84f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd @@ -0,0 +1,150 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_dverif.vhd +-- +-- Description: +-- Used for FIFO read interface stimulus generation and data checking +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); +END ENTITY; + + +ARCHITECTURE fg_dv_arch OF fifo_short_2clk_dverif IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8); + + SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_chk : STD_LOGIC := '1'; + SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0); + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL pr_r_en : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '1'; +BEGIN + + + DOUT_CHK <= data_chk; + RD_EN <= rd_en_i; + rd_en_i <= PRC_RD_EN; + rd_en_d1 <= '1'; + + + data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE + ------------------------------------------------------- + -- Expected data generation and checking for data_fifo + ------------------------------------------------------- + + pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1; + expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0); + + gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + rd_gen_inst2:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+N + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET, + RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N), + ENABLE => pr_r_en + ); + END GENERATE; + + PROCESS (RD_CLK,RESET) + BEGIN + IF(RESET = '1') THEN + data_chk <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + IF(EMPTY = '0') THEN + IF(DATA_OUT = expected_dout) THEN + data_chk <= '0'; + ELSE + data_chk <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE data_fifo_chk; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd new file mode 100755 index 000000000..5d6506398 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd @@ -0,0 +1,541 @@ + +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pctrl.vhd +-- +-- Description: +-- Used for protocol control on write and read interface stimulus and status generation +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING :="NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE fg_pc_arch OF fifo_short_2clk_pctrl IS + + CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); + CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); + CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH); + + SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); + SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); + SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL state : STD_LOGIC := '0'; + SIGNAL wr_control : STD_LOGIC := '0'; + SIGNAL rd_control : STD_LOGIC := '0'; + SIGNAL stop_on_err : STD_LOGIC := '0'; + SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); + SIGNAL sim_done_i : STD_LOGIC := '0'; + SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); + SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL reset_en_i : STD_LOGIC := '0'; + SIGNAL sim_done_d1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr1 : STD_LOGIC := '0'; + SIGNAL sim_done_wr2 : STD_LOGIC := '0'; + SIGNAL empty_d1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; + SIGNAL state_d1 : STD_LOGIC := '0'; + SIGNAL state_rd_dom1 : STD_LOGIC := '0'; + SIGNAL rd_en_d1 : STD_LOGIC := '0'; + SIGNAL rd_en_wr1 : STD_LOGIC := '0'; + SIGNAL wr_en_d1 : STD_LOGIC := '0'; + SIGNAL wr_en_rd1 : STD_LOGIC := '0'; + SIGNAL full_chk_d1 : STD_LOGIC := '0'; + SIGNAL full_chk_rd1 : STD_LOGIC := '0'; + SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; + + SIGNAL state_rd_dom2 : STD_LOGIC := '0'; + SIGNAL state_rd_dom3 : STD_LOGIC := '0'; + SIGNAL rd_en_wr2 : STD_LOGIC := '0'; + SIGNAL wr_en_rd2 : STD_LOGIC := '0'; + SIGNAL full_chk_rd2 : STD_LOGIC := '0'; + SIGNAL reset_en_d1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd1 : STD_LOGIC := '0'; + SIGNAL reset_en_rd2 : STD_LOGIC := '0'; + + SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd1 : STD_LOGIC := '0'; + SIGNAL data_chk_rd2 : STD_LOGIC := '0'; + SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); + SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); +BEGIN + status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0'; + STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); + + prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; + prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; + + SIM_DONE <= sim_done_i; + rdw_gt_wrw <= (OTHERS => '1'); + wrw_gt_rdw <= (OTHERS => '1'); + + PROCESS(RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(prc_re_i = '1') THEN + rd_activ_cont <= rd_activ_cont + "1"; + END IF; + END IF; + END PROCESS; + + + PROCESS(sim_done_i) + BEGIN + assert sim_done_i = '0' + report "Simulation Complete for:" & AXI_CHANNEL + severity note; + END PROCESS; + +----------------------------------------------------- +-- SIM_DONE SIGNAL GENERATION +----------------------------------------------------- +PROCESS (RD_CLK,RESET_RD) +BEGIN + IF(RESET_RD = '1') THEN + --sim_done_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN + sim_done_i <= '1'; + END IF; + END IF; +END PROCESS; + + -- TB Timeout/Stop + fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN + sim_stop_cntr <= sim_stop_cntr - "1"; + END IF; + END IF; + END PROCESS; + END GENERATE fifo_tb_stop_run; + + + -- Stop when error found + PROCESS (RD_CLK) + BEGIN + IF (RD_CLK'event AND RD_CLK='1') THEN + IF(sim_done_i = '0') THEN + status_d1_i <= status_i OR status_d1_i; + END IF; + IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN + stop_on_err <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------- + + ----------------------------------------------------- + -- CHECKS FOR FIFO + ----------------------------------------------------- + + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + post_rst_dly_rd <= (OTHERS => '1'); + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); + END IF; + END PROCESS; + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + post_rst_dly_wr <= (OTHERS => '1'); + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); + END IF; + END PROCESS; + + + -- FULL de-assert Counter + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_ds_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN + full_ds_timeout <= full_ds_timeout + '1'; + END IF; + ELSE + full_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + + -- EMPTY deassert counter + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_ds_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state = '0') THEN + IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN + empty_ds_timeout <= empty_ds_timeout + '1'; + END IF; + ELSE + empty_ds_timeout <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + -- Full check signal generation + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + full_chk_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + full_chk_i <= '0'; + ELSE + full_chk_i <= AND_REDUCE(full_as_timeout) OR + AND_REDUCE(full_ds_timeout); + END IF; + END IF; + END PROCESS; + + -- Empty checks + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_chk_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN + empty_chk_i <= '0'; + ELSE + empty_chk_i <= AND_REDUCE(empty_as_timeout) OR + AND_REDUCE(empty_ds_timeout); + END IF; + END IF; + END PROCESS; + + fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE + PRC_WR_EN <= prc_we_i AFTER 100 ns; + PRC_RD_EN <= prc_re_i AFTER 50 ns; + data_chk_i <= dout_chk; + END GENERATE fifo_d_chk; + ----------------------------------------------------- + + + ----------------------------------------------------- + -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + empty_wr_dom1 <= '1'; + empty_wr_dom2 <= '1'; + state_d1 <= '0'; + wr_en_d1 <= '0'; + rd_en_wr1 <= '0'; + rd_en_wr2 <= '0'; + full_chk_d1 <= '0'; + reset_en_d1 <= '0'; + sim_done_wr1 <= '0'; + sim_done_wr2 <= '0'; + ELSIF (WR_CLK'event AND WR_CLK='1') THEN + sim_done_wr1 <= sim_done_d1; + sim_done_wr2 <= sim_done_wr1; + reset_en_d1 <= reset_en_i; + state_d1 <= state; + empty_wr_dom1 <= empty_d1; + empty_wr_dom2 <= empty_wr_dom1; + wr_en_d1 <= wr_en_i; + rd_en_wr1 <= rd_en_d1; + rd_en_wr2 <= rd_en_wr1; + full_chk_d1 <= full_chk_i; + END IF; + END PROCESS; + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + empty_d1 <= '1'; + state_rd_dom1 <= '0'; + state_rd_dom2 <= '0'; + state_rd_dom3 <= '0'; + wr_en_rd1 <= '0'; + wr_en_rd2 <= '0'; + rd_en_d1 <= '0'; + full_chk_rd1 <= '0'; + full_chk_rd2 <= '0'; + reset_en_rd1 <= '0'; + reset_en_rd2 <= '0'; + sim_done_d1 <= '0'; + ELSIF (RD_CLK'event AND RD_CLK='1') THEN + sim_done_d1 <= sim_done_i; + reset_en_rd1 <= reset_en_d1; + reset_en_rd2 <= reset_en_rd1; + empty_d1 <= EMPTY; + rd_en_d1 <= rd_en_i; + state_rd_dom1 <= state_d1; + state_rd_dom2 <= state_rd_dom1; + state_rd_dom3 <= state_rd_dom2; + wr_en_rd1 <= wr_en_d1; + wr_en_rd2 <= wr_en_rd1; + full_chk_rd1 <= full_chk_d1; + full_chk_rd2 <= full_chk_rd1; + END IF; + END PROCESS; + + RESET_EN <= reset_en_rd2; + + + data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE + ----------------------------------------------------- + -- WR_EN GENERATION + ----------------------------------------------------- + gen_rand_wr_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED+1 + ) + PORT MAP( + CLK => WR_CLK, + RESET => RESET_WR, + RANDOM_NUM => wr_en_gen, + ENABLE => '1' + ); + + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; + ELSE + wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- WR_EN CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + wr_cntr <= (OTHERS => '0'); + wr_control <= '1'; + full_as_timeout <= (OTHERS => '0'); + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + IF(state = '1') THEN + IF(wr_en_i = '1') THEN + wr_cntr <= wr_cntr + "1"; + END IF; + full_as_timeout <= (OTHERS => '0'); + ELSE + wr_cntr <= (OTHERS => '0'); + IF(rd_en_wr2 = '0') THEN + IF(wr_en_i = '1') THEN + full_as_timeout <= full_as_timeout + "1"; + END IF; + ELSE + full_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + wr_control <= NOT wr_cntr(wr_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN GENERATION + ----------------------------------------------------- + gen_rand_rd_en:fifo_short_2clk_rng + GENERIC MAP( + WIDTH => 8, + SEED => TB_SEED + ) + PORT MAP( + CLK => RD_CLK, + RESET => RESET_RD, + RANDOM_NUM => rd_en_gen, + ENABLE => '1' + ); + + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_en_i <= '0'; + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); + ELSE + rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------- + -- RD_EN CONTROL + ----------------------------------------------------- + PROCESS(RD_CLK,RESET_RD) + BEGIN + IF(RESET_RD = '1') THEN + rd_cntr <= (OTHERS => '0'); + rd_control <= '1'; + empty_as_timeout <= (OTHERS => '0'); + ELSIF(RD_CLK'event AND RD_CLK='1') THEN + IF(state_rd_dom2 = '0') THEN + IF(rd_en_i = '1') THEN + rd_cntr <= rd_cntr + "1"; + END IF; + empty_as_timeout <= (OTHERS => '0'); + ELSE + rd_cntr <= (OTHERS => '0'); + IF(wr_en_rd2 = '0') THEN + IF(rd_en_i = '1') THEN + empty_as_timeout <= empty_as_timeout + "1"; + END IF; + ELSE + empty_as_timeout <= (OTHERS => '0'); + END IF; + END IF; + + rd_control <= NOT rd_cntr(rd_cntr'high); + + END IF; + END PROCESS; + + ----------------------------------------------------- + -- STIMULUS CONTROL + ----------------------------------------------------- + PROCESS(WR_CLK,RESET_WR) + BEGIN + IF(RESET_WR = '1') THEN + state <= '0'; + reset_en_i <= '0'; + ELSIF(WR_CLK'event AND WR_CLK='1') THEN + CASE state IS + WHEN '0' => + IF(FULL = '1' AND empty_wr_dom2 = '0') THEN + state <= '1'; + reset_en_i <= '0'; + END IF; + WHEN '1' => + IF(empty_wr_dom2 = '1' AND FULL = '0') THEN + state <= '0'; + reset_en_i <= '1'; + END IF; + WHEN OTHERS => state <= state; + END CASE; + END IF; + END PROCESS; + END GENERATE data_fifo_en; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd new file mode 100755 index 000000000..4c0e4035b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd @@ -0,0 +1,350 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_pkg.vhd +-- +-- Description: +-- This is the demo testbench package file for FIFO Generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.std_logic_arith.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME; + ------------------------ + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector; + ------------------------ + COMPONENT fifo_short_2clk_rng IS + GENERIC (WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dgen IS + GENERIC ( + C_DIN_WIDTH : INTEGER := 32; + C_DOUT_WIDTH : INTEGER := 32; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT ( + RESET : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + PRC_WR_EN : IN STD_LOGIC; + FULL : IN STD_LOGIC; + WR_EN : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_dverif IS + GENERIC( + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_USE_EMBEDDED_REG : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + PRC_RD_EN : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + RD_EN : OUT STD_LOGIC; + DOUT_CHK : OUT STD_LOGIC + ); + END COMPONENT; + ------------------------ + + COMPONENT fifo_short_2clk_pctrl IS + GENERIC( + AXI_CHANNEL : STRING := "NONE"; + C_APPLICATION_TYPE : INTEGER := 0; + C_DIN_WIDTH : INTEGER := 0; + C_DOUT_WIDTH : INTEGER := 0; + C_WR_PNTR_WIDTH : INTEGER := 0; + C_RD_PNTR_WIDTH : INTEGER := 0; + C_CH_TYPE : INTEGER := 0; + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 2; + TB_SEED : INTEGER := 2 + ); + PORT( + RESET_WR : IN STD_LOGIC; + RESET_RD : IN STD_LOGIC; + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + FULL : IN STD_LOGIC; + EMPTY : IN STD_LOGIC; + ALMOST_FULL : IN STD_LOGIC; + ALMOST_EMPTY : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); + DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); + DOUT_CHK : IN STD_LOGIC; + PRC_WR_EN : OUT STD_LOGIC; + PRC_RD_EN : OUT STD_LOGIC; + RESET_EN : OUT STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); + END COMPONENT; + ------------------------ + COMPONENT fifo_short_2clk_exdes IS + PORT ( + WR_CLK : IN std_logic; + RD_CLK : IN std_logic; + WR_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RD_DATA_COUNT : OUT std_logic_vector(6-1 DOWNTO 0); + RST : IN std_logic; + WR_EN : IN std_logic; + RD_EN : IN std_logic; + DIN : IN std_logic_vector(72-1 DOWNTO 0); + DOUT : OUT std_logic_vector(72-1 DOWNTO 0); + FULL : OUT std_logic; + EMPTY : OUT std_logic); + + END COMPONENT; + ------------------------ + + +END fifo_short_2clk_pkg; + + + +PACKAGE BODY fifo_short_2clk_pkg IS + + FUNCTION divroundup ( + data_value : INTEGER; + divisor : INTEGER) + RETURN INTEGER IS + VARIABLE div : INTEGER; + BEGIN + div := data_value/divisor; + IF ( (data_value MOD divisor) /= 0) THEN + div := div+1; + END IF; + RETURN div; + END divroundup; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : INTEGER; + false_case : INTEGER) + RETURN INTEGER IS + VARIABLE retval : INTEGER := 0; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : STD_LOGIC; + false_case : STD_LOGIC) + RETURN STD_LOGIC IS + VARIABLE retval : STD_LOGIC := '0'; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + --------------------------------- + FUNCTION if_then_else ( + condition : BOOLEAN; + true_case : TIME; + false_case : TIME) + RETURN TIME IS + VARIABLE retval : TIME := 0 ps; + BEGIN + IF condition=false THEN + retval:=false_case; + ELSE + retval:=true_case; + END IF; + RETURN retval; + END if_then_else; + ------------------------------- + FUNCTION log2roundup ( + data_value : INTEGER) + RETURN INTEGER IS + + VARIABLE width : INTEGER := 0; + VARIABLE cnt : INTEGER := 1; + BEGIN + IF (data_value <= 1) THEN + width := 1; + ELSE + WHILE (cnt < data_value) LOOP + width := width + 1; + cnt := cnt *2; + END LOOP; + END IF; + + RETURN width; + END log2roundup; + ------------------------------------------------------------------------------ + -- hexstr_to_std_logic_vec + -- This function converts a hex string to a std_logic_vector + ------------------------------------------------------------------------------ + FUNCTION hexstr_to_std_logic_vec( + arg1 : string; + size : integer ) + RETURN std_logic_vector IS + VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE bin : std_logic_vector(3 DOWNTO 0); + VARIABLE index : integer := 0; + BEGIN + FOR i IN arg1'reverse_range LOOP + CASE arg1(i) IS + WHEN '0' => bin := (OTHERS => '0'); + WHEN '1' => bin := (0 => '1', OTHERS => '0'); + WHEN '2' => bin := (1 => '1', OTHERS => '0'); + WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); + WHEN '4' => bin := (2 => '1', OTHERS => '0'); + WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); + WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); + WHEN '7' => bin := (3 => '0', OTHERS => '1'); + WHEN '8' => bin := (3 => '1', OTHERS => '0'); + WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); + WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); + WHEN 'B' => bin := (2 => '0', OTHERS => '1'); + WHEN 'b' => bin := (2 => '0', OTHERS => '1'); + WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); + WHEN 'D' => bin := (1 => '0', OTHERS => '1'); + WHEN 'd' => bin := (1 => '0', OTHERS => '1'); + WHEN 'E' => bin := (0 => '0', OTHERS => '1'); + WHEN 'e' => bin := (0 => '0', OTHERS => '1'); + WHEN 'F' => bin := (OTHERS => '1'); + WHEN 'f' => bin := (OTHERS => '1'); + WHEN OTHERS => + FOR j IN 0 TO 3 LOOP + bin(j) := 'X'; + END LOOP; + END CASE; + FOR j IN 0 TO 3 LOOP + IF (index*4)+j < size THEN + result((index*4)+j) := bin(j); + END IF; + END LOOP; + index := index + 1; + END LOOP; + RETURN result; + END hexstr_to_std_logic_vec; + +END fifo_short_2clk_pkg; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd new file mode 100755 index 000000000..80c201c3b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd @@ -0,0 +1,100 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_rng.vhd +-- +-- Description: +-- Used for generation of pseudo random numbers +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE IEEE.std_logic_arith.all; +USE IEEE.std_logic_misc.all; + +ENTITY fifo_short_2clk_rng IS + GENERIC ( + WIDTH : integer := 8; + SEED : integer := 3); + PORT ( + CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + ENABLE : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)); +END ENTITY; + +ARCHITECTURE rg_arch OF fifo_short_2clk_rng IS +BEGIN +PROCESS (CLK,RESET) + VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width); + VARIABLE temp : STD_LOGIC := '0'; +BEGIN + IF(RESET = '1') THEN + rand_temp := conv_std_logic_vector(SEED,width); + temp := '0'; + ELSIF (CLK'event AND CLK = '1') THEN + IF (ENABLE = '1') THEN + temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5); + rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0); + rand_temp(0) := temp; + END IF; + END IF; + + RANDOM_NUM <= rand_temp; + +END PROCESS; + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd new file mode 100755 index 000000000..e9139fc96 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_synth.vhd +-- +-- Description: +-- This is the demo testbench for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.STD_LOGIC_1164.ALL; +USE ieee.STD_LOGIC_unsigned.ALL; +USE IEEE.STD_LOGIC_arith.ALL; +USE ieee.numeric_std.ALL; +USE ieee.STD_LOGIC_misc.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY fifo_short_2clk_synth IS + GENERIC( + FREEZEON_ERROR : INTEGER := 0; + TB_STOP_CNT : INTEGER := 0; + TB_SEED : INTEGER := 1 + ); + PORT( + WR_CLK : IN STD_LOGIC; + RD_CLK : IN STD_LOGIC; + RESET : IN STD_LOGIC; + SIM_DONE : OUT STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END ENTITY; + +ARCHITECTURE simulation_arch OF fifo_short_2clk_synth IS + + -- FIFO interface signal declarations + SIGNAL wr_clk_i : STD_LOGIC; + SIGNAL rd_clk_i : STD_LOGIC; + SIGNAL wr_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rd_data_count : STD_LOGIC_VECTOR(6-1 DOWNTO 0); + SIGNAL rst : STD_LOGIC; + SIGNAL wr_en : STD_LOGIC; + SIGNAL rd_en : STD_LOGIC; + SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL full : STD_LOGIC; + SIGNAL empty : STD_LOGIC; + -- TB Signals + SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0); + SIGNAL wr_en_i : STD_LOGIC := '0'; + SIGNAL rd_en_i : STD_LOGIC := '0'; + SIGNAL full_i : STD_LOGIC := '0'; + SIGNAL empty_i : STD_LOGIC := '0'; + SIGNAL almost_full_i : STD_LOGIC := '0'; + SIGNAL almost_empty_i : STD_LOGIC := '0'; + SIGNAL prc_we_i : STD_LOGIC := '0'; + SIGNAL prc_re_i : STD_LOGIC := '0'; + SIGNAL dout_chk_i : STD_LOGIC := '0'; + SIGNAL rst_int_rd : STD_LOGIC := '0'; + SIGNAL rst_int_wr : STD_LOGIC := '0'; + SIGNAL rst_s_wr1 : STD_LOGIC := '0'; + SIGNAL rst_s_wr2 : STD_LOGIC := '0'; + SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL rst_s_wr3 : STD_LOGIC := '0'; + SIGNAL rst_s_rd : STD_LOGIC := '0'; + SIGNAL reset_en : STD_LOGIC := '0'; + SIGNAL rst_async_wr1 : STD_LOGIC := '0'; + SIGNAL rst_async_wr2 : STD_LOGIC := '0'; + SIGNAL rst_async_wr3 : STD_LOGIC := '0'; + SIGNAL rst_async_rd1 : STD_LOGIC := '0'; + SIGNAL rst_async_rd2 : STD_LOGIC := '0'; + SIGNAL rst_async_rd3 : STD_LOGIC := '0'; + + + BEGIN + + ---- Reset generation logic ----- + rst_int_wr <= rst_async_wr3 OR rst_s_wr3; + rst_int_rd <= rst_async_rd3 OR rst_s_rd; + + --Testbench reset synchronization + PROCESS(rd_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_rd1 <= '1'; + rst_async_rd2 <= '1'; + rst_async_rd3 <= '1'; + ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_async_rd1 <= RESET; + rst_async_rd2 <= rst_async_rd1; + rst_async_rd3 <= rst_async_rd2; + END IF; + END PROCESS; + + PROCESS(wr_clk_i,RESET) + BEGIN + IF(RESET = '1') THEN + rst_async_wr1 <= '1'; + rst_async_wr2 <= '1'; + rst_async_wr3 <= '1'; + ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_async_wr1 <= RESET; + rst_async_wr2 <= rst_async_wr1; + rst_async_wr3 <= rst_async_wr2; + END IF; + END PROCESS; + + --Soft reset for core and testbench + PROCESS(rd_clk_i) + BEGIN + IF(rd_clk_i'event AND rd_clk_i='1') THEN + rst_gen_rd <= rst_gen_rd + "1"; + IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN + rst_s_rd <= '1'; + assert false + report "Reset applied..Memory Collision checks are not valid" + severity note; + ELSE + IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN + rst_s_rd <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(wr_clk_i) + BEGIN + IF(wr_clk_i'event AND wr_clk_i='1') THEN + rst_s_wr1 <= rst_s_rd; + rst_s_wr2 <= rst_s_wr1; + rst_s_wr3 <= rst_s_wr2; + IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN + assert false + report "Reset removed..Memory Collision checks are valid" + severity note; + END IF; + END IF; + END PROCESS; + ------------------ + + ---- Clock buffers for testbench ---- + wr_clk_i <= WR_CLK; + rd_clk_i <= RD_CLK; + ------------------ + + rst <= RESET OR rst_s_rd AFTER 12 ns; + din <= wr_data; + dout_i <= dout; + wr_en <= wr_en_i; + rd_en <= rd_en_i; + full_i <= full; + empty_i <= empty; + + fg_dg_nv: fifo_short_2clk_dgen + GENERIC MAP ( + C_DIN_WIDTH => 72, + C_DOUT_WIDTH => 72, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP ( -- Write Port + RESET => rst_int_wr, + WR_CLK => wr_clk_i, + PRC_WR_EN => prc_we_i, + FULL => full_i, + WR_EN => wr_en_i, + WR_DATA => wr_data + ); + + fg_dv_nv: fifo_short_2clk_dverif + GENERIC MAP ( + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_USE_EMBEDDED_REG => 0, + TB_SEED => TB_SEED, + C_CH_TYPE => 0 + ) + PORT MAP( + RESET => rst_int_rd, + RD_CLK => rd_clk_i, + PRC_RD_EN => prc_re_i, + RD_EN => rd_en_i, + EMPTY => empty_i, + DATA_OUT => dout_i, + DOUT_CHK => dout_chk_i + ); + + fg_pc_nv: fifo_short_2clk_pctrl + GENERIC MAP ( + AXI_CHANNEL => "Native", + C_APPLICATION_TYPE => 0, + C_DOUT_WIDTH => 72, + C_DIN_WIDTH => 72, + C_WR_PNTR_WIDTH => 5, + C_RD_PNTR_WIDTH => 5, + C_CH_TYPE => 0, + FREEZEON_ERROR => FREEZEON_ERROR, + TB_SEED => TB_SEED, + TB_STOP_CNT => TB_STOP_CNT + ) + PORT MAP( + RESET_WR => rst_int_wr, + RESET_RD => rst_int_rd, + RESET_EN => reset_en, + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + PRC_WR_EN => prc_we_i, + PRC_RD_EN => prc_re_i, + FULL => full_i, + ALMOST_FULL => almost_full_i, + ALMOST_EMPTY => almost_empty_i, + DOUT_CHK => dout_chk_i, + EMPTY => empty_i, + DATA_IN => wr_data, + DATA_OUT => dout, + SIM_DONE => SIM_DONE, + STATUS => STATUS + ); + + + + + + fifo_short_2clk_inst : fifo_short_2clk_exdes + PORT MAP ( + WR_CLK => wr_clk_i, + RD_CLK => rd_clk_i, + WR_DATA_COUNT => wr_data_count, + RD_DATA_COUNT => rd_data_count, + RST => rst, + WR_EN => wr_en, + RD_EN => rd_en, + DIN => din, + DOUT => dout, + FULL => full, + EMPTY => empty); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd new file mode 100755 index 000000000..6d86157db --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd @@ -0,0 +1,208 @@ +-------------------------------------------------------------------------------- +-- +-- FIFO Generator Core Demo Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- +-- Filename: fifo_short_2clk_tb.vhd +-- +-- Description: +-- This is the demo testbench top file for fifo_generator core. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY ieee; +LIBRARY std; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE IEEE.std_logic_arith.ALL; +USE IEEE.std_logic_misc.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_textio.ALL; +USE std.textio.ALL; + +LIBRARY work; +USE work.fifo_short_2clk_pkg.ALL; + +ENTITY fifo_short_2clk_tb IS +END ENTITY; + + +ARCHITECTURE fifo_short_2clk_arch OF fifo_short_2clk_tb IS + SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; + SIGNAL wr_clk : STD_LOGIC; + SIGNAL rd_clk : STD_LOGIC; + SIGNAL reset : STD_LOGIC; + SIGNAL sim_done : STD_LOGIC := '0'; + SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + -- Write and Read clock periods + CONSTANT wr_clk_period_by_2 : TIME := 200 ns; + CONSTANT rd_clk_period_by_2 : TIME := 100 ns; + -- Procedures to display strings + PROCEDURE disp_str(CONSTANT str:IN STRING) IS + variable dp_l : line := null; + BEGIN + write(dp_l,str); + writeline(output,dp_l); + END PROCEDURE; + + PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS + variable dp_lx : line := null; + BEGIN + hwrite(dp_lx,hex); + writeline(output,dp_lx); + END PROCEDURE; + +BEGIN + + -- Generation of clock + + PROCESS BEGIN + WAIT FOR 400 ns; -- Wait for global reset + WHILE 1 = 1 LOOP + wr_clk <= '0'; + WAIT FOR wr_clk_period_by_2; + wr_clk <= '1'; + WAIT FOR wr_clk_period_by_2; + END LOOP; + END PROCESS; + + PROCESS BEGIN + WAIT FOR 200 ns;-- Wait for global reset + WHILE 1 = 1 LOOP + rd_clk <= '0'; + WAIT FOR rd_clk_period_by_2; + rd_clk <= '1'; + WAIT FOR rd_clk_period_by_2; + END LOOP; + END PROCESS; + + -- Generation of Reset + + PROCESS BEGIN + reset <= '1'; + WAIT FOR 4200 ns; + reset <= '0'; + WAIT; + END PROCESS; + + + -- Error message printing based on STATUS signal from fifo_short_2clk_synth + + PROCESS(status) + BEGIN + IF(status /= "0" AND status /= "1") THEN + disp_str("STATUS:"); + disp_hex(status); + END IF; + + IF(status(7) = '1') THEN + assert false + report "Data mismatch found" + severity error; + END IF; + + IF(status(1) = '1') THEN + END IF; + + IF(status(5) = '1') THEN + assert false + report "Empty flag Mismatch/timeout" + severity error; + END IF; + + IF(status(6) = '1') THEN + assert false + report "Full Flag Mismatch/timeout" + severity error; + END IF; + END PROCESS; + + + PROCESS + BEGIN + wait until sim_done = '1'; + IF(status /= "0" AND status /= "1") THEN + assert false + report "Simulation failed" + severity failure; + ELSE + assert false + report "Test Completed Successfully" + severity failure; + END IF; + END PROCESS; + + PROCESS + BEGIN + wait for 400 ms; + assert false + report "Test bench timed out" + severity failure; + END PROCESS; + + -- Instance of fifo_short_2clk_synth + + fifo_short_2clk_synth_inst:fifo_short_2clk_synth + GENERIC MAP( + FREEZEON_ERROR => 0, + TB_STOP_CNT => 2, + TB_SEED => 108 + ) + PORT MAP( + WR_CLK => wr_clk, + RD_CLK => rd_clk, + RESET => reset, + SIM_DONE => sim_done, + STATUS => status + ); + +END ARCHITECTURE; diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat new file mode 100755 index 000000000..d40cb85cf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.bat @@ -0,0 +1,63 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\..\\fifo_short_2clk.v +vhpcomp -work work ..\\..\\example_design\\fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX\\verilog\\src\\glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh new file mode 100755 index 000000000..78f9ce588 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_isim.sh @@ -0,0 +1,65 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../../fifo_short_2clk.v +vhpcomp -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +vlogcomp -work work $XILINX/verilog/src/glbl.v +fuse work.fifo_short_2clk_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do new file mode 100755 index 000000000..8deb52187 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.do @@ -0,0 +1,74 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../fifo_short_2clk.v +vcom -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh new file mode 100755 index 000000000..749f9db06 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../fifo_short_2clk.v +ncvhdl -v93 -work work ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh new file mode 100755 index 000000000..71a568e24 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/simulate_vcs.sh @@ -0,0 +1,69 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../fifo_short_2clk.v +vhdlan ../../example_design/fifo_short_2clk_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs -time_res 1ps +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl new file mode 100755 index 000000000..7f3170d74 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/vcs_session.tcl @@ -0,0 +1,77 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/functional/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat new file mode 100755 index 000000000..536a7cfee --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.bat @@ -0,0 +1,61 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\\..\\implement\\results\\routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ..\\fifo_short_2clk_pkg.vhd +vhpcomp -work work ..\\fifo_short_2clk_rng.vhd +vhpcomp -work work ..\\fifo_short_2clk_dgen.vhd +vhpcomp -work work ..\\fifo_short_2clk_dverif.vhd +vhpcomp -work work ..\\fifo_short_2clk_pctrl.vhd +vhpcomp -work work ..\\fifo_short_2clk_synth.vhd +vhpcomp -work work ..\\fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +.\\fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=..\\..\\implement\\results\\routed.sdf -gui -tclbatch .\\wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh new file mode 100755 index 000000000..2d9404294 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_isim.sh @@ -0,0 +1,63 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhpcomp -work work ../fifo_short_2clk_pkg.vhd +vhpcomp -work work ../fifo_short_2clk_rng.vhd +vhpcomp -work work ../fifo_short_2clk_dgen.vhd +vhpcomp -work work ../fifo_short_2clk_dverif.vhd +vhpcomp -work work ../fifo_short_2clk_pctrl.vhd +vhpcomp -work work ../fifo_short_2clk_synth.vhd +vhpcomp -work work ../fifo_short_2clk_tb.vhd + +fuse work.fifo_short_2clk_tb work.glbl -L simprims_ver -o fifo_short_2clk_tb.exe + +./fifo_short_2clk_tb.exe -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf -gui -tclbatch ./wave_isim.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat new file mode 100755 index 000000000..35375ce20 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.bat @@ -0,0 +1,47 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do new file mode 100755 index 000000000..7ec785533 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.do @@ -0,0 +1,72 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vcom -work work ../fifo_short_2clk_pkg.vhd +vcom -work work ../fifo_short_2clk_rng.vhd +vcom -work work ../fifo_short_2clk_dgen.vhd +vcom -work work ../fifo_short_2clk_dverif.vhd +vcom -work work ../fifo_short_2clk_pctrl.vhd +vcom -work work ../fifo_short_2clk_synth.vhd +vcom -work work ../fifo_short_2clk_tb.vhd + +vsim -t ps -voptargs="+acc" +transport_int_delays -L simprims_ver glbl -sdfmax /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst=../../implement/results/routed.sdf work.fifo_short_2clk_tb + +add log -r /* +do wave_mti.do +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh new file mode 100755 index 000000000..edb1b0dd9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh new file mode 100755 index 000000000..e9dc952cf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +ncvhdl -v93 -work work ../fifo_short_2clk_pkg.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_rng.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dgen.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_dverif.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_pctrl.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_synth.vhd +ncvhdl -v93 -work work ../fifo_short_2clk_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :fifo_short_2clk_synth_inst:fifo_short_2clk_inst,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd work.fifo_short_2clk_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.fifo_short_2clk_tb diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh new file mode 100755 index 000000000..bbd548a74 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/simulate_vcs.sh @@ -0,0 +1,67 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../fifo_short_2clk_pkg.vhd +vhdlan ../fifo_short_2clk_rng.vhd +vhdlan ../fifo_short_2clk_dgen.vhd +vhdlan ../fifo_short_2clk_dverif.vhd +vhdlan ../fifo_short_2clk_pctrl.vhd +vhdlan ../fifo_short_2clk_synth.vhd +vhdlan ../fifo_short_2clk_tb.vhd + +echo "Elaborating Design" +vcs -time_res 1ps +neg_tchk -sdf max:/fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst:../../implement/results/routed.sdf +vcs+lic+wait -debug fifo_short_2clk_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key new file mode 100755 index 000000000..f90cccb67 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file fifo_short_2clk.vpd -type VPD +dump -add fifo_short_2clk_tb +run +quit diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl new file mode 100755 index 000000000..e27baa9d8 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/vcs_session.tcl @@ -0,0 +1,76 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {fifo_short_2clk.vpd}] } { + gui_open_db -design V1 -file fifo_short_2clk.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create fifo_short_2clk_Group +gui_list_add_group -id Wave.1 {fifo_short_2clk_Group} + +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +gui_sg_addsignal -group fifo_short_2clk_Group WRITE -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +gui_sg_addsignal -group fifo_short_2clk_Group READ -divider +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +gui_sg_addsignal -group fifo_short_2clk_Group /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl new file mode 100755 index 000000000..156aad172 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_isim.tcl @@ -0,0 +1,68 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_isim.tcl +# +# Description: +# This is the ISIM wave form file. +# +#-------------------------------------------------------------------------------- +wcfg new +isim set radix hex +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +wave add /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +run all +quit + diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_mti.do b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_mti.do new file mode 100755 index 000000000..eafc64cf2 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_mti.do @@ -0,0 +1,88 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +# Filename: wave_mti.do +# +# Description: +# This is the modelsim wave form file. +# +#-------------------------------------------------------------------------------- + +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +add wave -noupdate -divider WRITE +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DIN +add wave -noupdate -divider READ +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +add wave -noupdate /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +add wave -noupdate -radix hexadecimal /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/DOUT + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2164886 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv new file mode 100755 index 000000000..655d5c65a --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/timing/wave_ncsim.sv @@ -0,0 +1,70 @@ +#-------------------------------------------------------------------------------- +#-- +#-- FIFO Generator Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: wave_ncsim.sv +# +# Description: +# This is the IUS wave form file. +# +#-------------------------------------------------------------------------------- + +window new WaveWindow -name "Waves for FIFO Generator Example Design" +waveform using "Waves for FIFO Generator Example Design" + +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RST +waveform add -label WRITE +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/WR_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/FULL +waveform add -label READ +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_CLK +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/RD_EN +waveform add -signals /fifo_short_2clk_tb/fifo_short_2clk_synth_inst/fifo_short_2clk_inst/EMPTY +console submit -using simulator -wait no "run" diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_flist.txt b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_flist.txt new file mode 100644 index 000000000..4ab119a52 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_flist.txt @@ -0,0 +1,57 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +fifo_short_2clk/doc/pg057-fifo-generator.pdf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +fifo_short_2clk/fifo_generator_v9_3_readme.txt +fifo_short_2clk/implement/implement.bat +fifo_short_2clk/implement/implement.sh +fifo_short_2clk/implement/implement_synplify.bat +fifo_short_2clk/implement/implement_synplify.sh +fifo_short_2clk/implement/planAhead_ise.bat +fifo_short_2clk/implement/planAhead_ise.sh +fifo_short_2clk/implement/planAhead_ise.tcl +fifo_short_2clk/implement/xst.prj +fifo_short_2clk/implement/xst.scr +fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +fifo_short_2clk/simulation/functional/simulate_isim.bat +fifo_short_2clk/simulation/functional/simulate_isim.sh +fifo_short_2clk/simulation/functional/simulate_mti.bat +fifo_short_2clk/simulation/functional/simulate_mti.do +fifo_short_2clk/simulation/functional/simulate_mti.sh +fifo_short_2clk/simulation/functional/simulate_ncsim.sh +fifo_short_2clk/simulation/functional/simulate_vcs.sh +fifo_short_2clk/simulation/functional/ucli_commands.key +fifo_short_2clk/simulation/functional/vcs_session.tcl +fifo_short_2clk/simulation/functional/wave_isim.tcl +fifo_short_2clk/simulation/functional/wave_mti.do +fifo_short_2clk/simulation/functional/wave_ncsim.sv +fifo_short_2clk/simulation/timing/simulate_isim.bat +fifo_short_2clk/simulation/timing/simulate_isim.sh +fifo_short_2clk/simulation/timing/simulate_mti.bat +fifo_short_2clk/simulation/timing/simulate_mti.do +fifo_short_2clk/simulation/timing/simulate_mti.sh +fifo_short_2clk/simulation/timing/simulate_ncsim.sh +fifo_short_2clk/simulation/timing/simulate_vcs.sh +fifo_short_2clk/simulation/timing/ucli_commands.key +fifo_short_2clk/simulation/timing/vcs_session.tcl +fifo_short_2clk/simulation/timing/wave_isim.tcl +fifo_short_2clk/simulation/timing/wave_mti.do +fifo_short_2clk/simulation/timing/wave_ncsim.sv +fifo_short_2clk.asy +fifo_short_2clk.gise +fifo_short_2clk.ngc +fifo_short_2clk.v +fifo_short_2clk.veo +fifo_short_2clk.xco +fifo_short_2clk.xise +fifo_short_2clk_flist.txt +fifo_short_2clk_xmdf.tcl diff --git a/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_xmdf.tcl new file mode 100644 index 000000000..0abe2bb7c --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide fifo_short_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_short_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_short_2clk_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_short_2clk +} +# ::fifo_short_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_short_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/fifo_generator_v9_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/doc/pg057-fifo-generator.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/example_design/fifo_short_2clk_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/fifo_generator_v9_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_dverif.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pctrl.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/fifo_short_2clk_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_isim.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_short_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_short_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/.gitignore b/fpga/usrp3/top/b2xxmini/coregen_dsp/.gitignore new file mode 100644 index 000000000..f9823bca9 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/.gitignore @@ -0,0 +1,6 @@ +_xmsgs +*.log +*.ncf +*.xise +*.gise + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/b2xxmini/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..9d679ab2d --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/Makefile.srcs @@ -0,0 +1,15 @@ +# +# Copyright 2012, 2015 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/b2xxmini/coregen_dsp/, \ +hbdec1.v \ +hbdec1.xco \ +hbdec2.v \ +hbdec2.xco \ +)) + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/coregen.cgp b/fpga/usrp3/top/b2xxmini/coregen_dsp/coregen.cgp new file mode 100644 index 000000000..e849e744f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc6slx150 +SET devicefamily = spartan6 +SET flowvendor = Other +SET package = csg484 +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/filt2.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/filt2.coe new file mode 100644 index 000000000..e18b5daa7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/filt2.coe @@ -0,0 +1,36 @@ + Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb31.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb31.coe new file mode 100644 index 000000000..37f5a180e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb31.coe @@ -0,0 +1,32 @@ +Radix=10; +CoefData = -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb35.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb35.coe new file mode 100644 index 000000000..18078085d --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb35.coe @@ -0,0 +1,36 @@ +Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb39.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb39.coe new file mode 100644 index 000000000..1d99fa946 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb39.coe @@ -0,0 +1,40 @@ +Radix=10; +CoefData = -102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb43.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb43.coe new file mode 100644 index 000000000..c56c4c928 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb43.coe @@ -0,0 +1,44 @@ +Radix=10; +CoefData = 100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb47.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb47.coe new file mode 100644 index 000000000..4c9a6c406 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0 + 194, + 0, +-62; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb51.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb51.coe new file mode 100644 index 000000000..ebfddb7fb --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb51.coe @@ -0,0 +1,52 @@ +Radix=10; +CoefData = 300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb55.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb55.coe new file mode 100644 index 000000000..07f861818 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb55.coe @@ -0,0 +1,56 @@ +Radix=10; +CoefData = -400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb59.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb59.coe new file mode 100644 index 000000000..79f1e362b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb59.coe @@ -0,0 +1,60 @@ +Radix=10; +CoefData = 500, +0, +-400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400, +0 +500; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hb63.coe b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb63.coe new file mode 100644 index 000000000..3b312036d --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hb63.coe @@ -0,0 +1,67 @@ +; Generated with round((2^18-2)*halfgen_test(.22,16,1)) +; 88% effective BW, 64dB to 87dB rolloff +Radix=10; +CoefData = +-35, + 0, + 95, + 0, +-195, + 0, + 352, + 0, +-582, + 0, + 907, + 0, +-1354, + 0, + 1953, + 0, +-2751, + 0, + 3813, + 0, +-5249, + 0, + 7264, + 0, +-10296, + 0, + 15494, + 0, +-27083, + 0, + 83196, + 131071, + 83196, + 0, +-27083, + 0, + 15494, + 0, +-10296, + 0, + 7264, + 0, +-5249, + 0, + 3813, + 0, +-2751, + 0, + 1953, + 0, +-1354, + 0, + 907, + 0, +-582, + 0, + 352, + 0, + -195, + 0 + 95, + 0 +-35; diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.asy b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.asy new file mode 100644 index 000000000..7644e7bbe --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec1 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..0830a9f34 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$26b<~753-Xnzd}foo8#5+421).97 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\ No newline at end of file diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.v b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.v new file mode 100644 index 000000000..67742af64 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.v @@ -0,0 +1,45924 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.20131013 +// \ \ Application: netgen +// / / Filename: hbdec1.v +// /___/ /\ Timestamp: Tue Jun 9 16:48:04 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec1.ngc ./tmp/_cg/hbdec1.v +// Device : 6slx75fgg484-3 +// Input file : ./tmp/_cg/hbdec1.ngc +// Output file : ./tmp/_cg/hbdec1.v +// # of Modules : 1 +// Design Name : hbdec1 +// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec1 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000e8e ; + wire \blk00000003/sig00000e8d ; + wire \blk00000003/sig00000e8c ; + wire \blk00000003/sig00000e8b ; + wire \blk00000003/sig00000e8a ; + wire \blk00000003/sig00000e89 ; + wire \blk00000003/sig00000e88 ; + wire \blk00000003/sig00000e87 ; + wire \blk00000003/sig00000e86 ; + wire \blk00000003/sig00000e85 ; + wire \blk00000003/sig00000e84 ; + wire \blk00000003/sig00000e83 ; + wire \blk00000003/sig00000e82 ; + wire \blk00000003/sig00000e81 ; + wire \blk00000003/sig00000e80 ; + wire \blk00000003/sig00000e7f ; + wire \blk00000003/sig00000e7e ; + wire \blk00000003/sig00000e7d ; + wire \blk00000003/sig00000e7c ; + wire \blk00000003/sig00000e7b ; + wire \blk00000003/sig00000e7a ; + wire \blk00000003/sig00000e79 ; + wire \blk00000003/sig00000e78 ; + wire \blk00000003/sig00000e77 ; + wire \blk00000003/sig00000e76 ; + wire \blk00000003/sig00000e75 ; + wire \blk00000003/sig00000e74 ; + wire \blk00000003/sig00000e73 ; + wire \blk00000003/sig00000e72 ; + wire \blk00000003/sig00000e71 ; + wire \blk00000003/sig00000e70 ; + wire \blk00000003/sig00000e6f ; + wire \blk00000003/sig00000e6e ; + wire \blk00000003/sig00000e6d ; + wire \blk00000003/sig00000e6c ; + wire \blk00000003/sig00000e6b ; + wire \blk00000003/sig00000e6a ; + wire \blk00000003/sig00000e69 ; + wire \blk00000003/sig00000e68 ; + wire \blk00000003/sig00000e67 ; + wire \blk00000003/sig00000e66 ; + wire \blk00000003/sig00000e65 ; + wire \blk00000003/sig00000e64 ; + wire \blk00000003/sig00000e63 ; + wire \blk00000003/sig00000e62 ; + wire \blk00000003/sig00000e61 ; + wire \blk00000003/sig00000e60 ; + wire \blk00000003/sig00000e5f ; + wire \blk00000003/sig00000e5e ; + wire \blk00000003/sig00000e5d ; + wire \blk00000003/sig00000e5c ; + wire \blk00000003/sig00000e5b ; + wire \blk00000003/sig00000e5a ; + wire \blk00000003/sig00000e59 ; + wire \blk00000003/sig00000e58 ; + wire \blk00000003/sig00000e57 ; + wire \blk00000003/sig00000e56 ; + wire \blk00000003/sig00000e55 ; + wire \blk00000003/sig00000e54 ; + wire \blk00000003/sig00000e53 ; + wire \blk00000003/sig00000e52 ; + wire \blk00000003/sig00000e51 ; + wire \blk00000003/sig00000e50 ; + wire \blk00000003/sig00000e4f ; + wire \blk00000003/sig00000e4e ; + wire \blk00000003/sig00000e4d ; + wire \blk00000003/sig00000e4c ; + wire \blk00000003/sig00000e4b ; + wire \blk00000003/sig00000e4a ; + wire \blk00000003/sig00000e49 ; + wire \blk00000003/sig00000e48 ; + wire \blk00000003/sig00000e47 ; + wire \blk00000003/sig00000e46 ; + wire \blk00000003/sig00000e45 ; + wire \blk00000003/sig00000e44 ; + wire \blk00000003/sig00000e43 ; + wire \blk00000003/sig00000e42 ; + wire \blk00000003/sig00000e41 ; + wire \blk00000003/sig00000e40 ; + wire \blk00000003/sig00000e3f ; + wire \blk00000003/sig00000e3e ; + wire \blk00000003/sig00000e3d ; + wire \blk00000003/sig00000e3c ; + wire \blk00000003/sig00000e3b ; + wire \blk00000003/sig00000e3a ; + wire \blk00000003/sig00000e39 ; + wire \blk00000003/sig00000e38 ; + wire \blk00000003/sig00000e37 ; + wire \blk00000003/sig00000e36 ; + wire \blk00000003/sig00000e35 ; + wire \blk00000003/sig00000e34 ; + wire \blk00000003/sig00000e33 ; + wire \blk00000003/sig00000e32 ; + wire \blk00000003/sig00000e31 ; + wire \blk00000003/sig00000e30 ; + wire \blk00000003/sig00000e2f ; + wire \blk00000003/sig00000e2e ; + wire \blk00000003/sig00000e2d ; + wire \blk00000003/sig00000e2c ; + wire \blk00000003/sig00000e2b ; + wire \blk00000003/sig00000e2a ; + wire \blk00000003/sig00000e29 ; + wire \blk00000003/sig00000e28 ; + wire \blk00000003/sig00000e27 ; + wire \blk00000003/sig00000e26 ; + wire \blk00000003/sig00000e25 ; + wire \blk00000003/sig00000e24 ; + wire \blk00000003/sig00000e23 ; + wire \blk00000003/sig00000e22 ; + wire \blk00000003/sig00000e21 ; + wire \blk00000003/sig00000e20 ; + wire \blk00000003/sig00000e1f ; + wire \blk00000003/sig00000e1e ; + wire \blk00000003/sig00000e1d ; + wire \blk00000003/sig00000e1c ; + wire \blk00000003/sig00000e1b ; + wire \blk00000003/sig00000e1a ; + wire \blk00000003/sig00000e19 ; + wire \blk00000003/sig00000e18 ; + wire \blk00000003/sig00000e17 ; + wire \blk00000003/sig00000e16 ; + wire \blk00000003/sig00000e15 ; + wire \blk00000003/sig00000e14 ; + wire \blk00000003/sig00000e13 ; + wire \blk00000003/sig00000e12 ; + wire \blk00000003/sig00000e11 ; + wire \blk00000003/sig00000e10 ; + wire \blk00000003/sig00000e0f ; + wire \blk00000003/sig00000e0e ; + wire \blk00000003/sig00000e0d ; + wire \blk00000003/sig00000e0c ; + wire \blk00000003/sig00000e0b ; + wire \blk00000003/sig00000e0a ; + wire \blk00000003/sig00000e09 ; + wire \blk00000003/sig00000e08 ; + wire \blk00000003/sig00000e07 ; + wire \blk00000003/sig00000e06 ; + wire \blk00000003/sig00000e05 ; + wire \blk00000003/sig00000e04 ; + wire \blk00000003/sig00000e03 ; + wire \blk00000003/sig00000e02 ; + wire \blk00000003/sig00000e01 ; + wire \blk00000003/sig00000e00 ; + wire \blk00000003/sig00000dff ; + wire \blk00000003/sig00000dfe ; + wire \blk00000003/sig00000dfd ; + wire \blk00000003/sig00000dfc ; + wire \blk00000003/sig00000dfb ; + wire \blk00000003/sig00000dfa ; + wire \blk00000003/sig00000df9 ; + wire \blk00000003/sig00000df8 ; + wire \blk00000003/sig00000df7 ; + wire \blk00000003/sig00000df6 ; + wire \blk00000003/sig00000df5 ; + wire \blk00000003/sig00000df4 ; + wire \blk00000003/sig00000df3 ; + wire \blk00000003/sig00000df2 ; + wire \blk00000003/sig00000df1 ; + wire \blk00000003/sig00000df0 ; + wire \blk00000003/sig00000def ; + wire \blk00000003/sig00000dee ; + wire \blk00000003/sig00000ded ; + wire \blk00000003/sig00000dec ; + wire \blk00000003/sig00000deb ; + wire \blk00000003/sig00000dea ; + wire \blk00000003/sig00000de9 ; + wire \blk00000003/sig00000de8 ; + wire \blk00000003/sig00000de7 ; + wire \blk00000003/sig00000de6 ; + wire \blk00000003/sig00000de5 ; + wire \blk00000003/sig00000de4 ; + wire \blk00000003/sig00000de3 ; + wire \blk00000003/sig00000de2 ; + wire \blk00000003/sig00000de1 ; + wire \blk00000003/sig00000de0 ; + wire \blk00000003/sig00000ddf ; + wire \blk00000003/sig00000dde ; + wire \blk00000003/sig00000ddd ; + wire \blk00000003/sig00000ddc ; + wire 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\NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000add_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000999_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000997_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000995_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000993_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000991_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000989_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000987_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000985_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000983_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000981_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000979_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000977_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000975_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000973_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000971_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000969_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000967_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000965_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000963_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000961_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000959_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000957_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000955_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000953_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000951_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000858_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000007ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000109_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000108_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000103_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000102_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000100_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000de_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b5_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b3_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000aa_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000027_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000023_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000021_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8e ), + .Q(\blk00000003/sig00000bc2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000cc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8d ), + .Q(\blk00000003/sig00000bc1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000cc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8c ), + .Q(\blk00000003/sig00000bc0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000cbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbe ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8b ), + .Q(\blk00000003/sig00000bbf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000cbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbc ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e8a ), + .Q(\blk00000003/sig00000bbe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000cbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cba ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e89 ), + .Q(\blk00000003/sig00000bbc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000cb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e88 ), + .Q(\blk00000003/sig00000bbb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000cb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e87 ), + .Q(\blk00000003/sig00000bbd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000cb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb4 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e86 ), + .Q(\blk00000003/sig00000bd2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000cb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb2 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e85 ), + .Q(\blk00000003/sig00000bd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000cb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb0 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e84 ), + .Q(\blk00000003/sig00000bd0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000caf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000caf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cae ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e83 ), + .Q(\blk00000003/sig00000bcf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000cad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cac ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e82 ), + .Q(\blk00000003/sig00000bce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000cab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000caa ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e81 ), + .Q(\blk00000003/sig00000bcd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000ca9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca8 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e80 ), + .Q(\blk00000003/sig00000bcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/sig00000e80 ), + .Q15(\NLW_blk00000003/blk00000ca7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca6 ( + .C(clk), + .CE(\blk00000003/sig00000ca0 ), + .D(\blk00000003/sig00000e7f ), + .Q(\blk00000003/sig00000bcc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca0 ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/sig00000e7f ), + .Q15(\NLW_blk00000003/blk00000ca5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca4 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7e ), + .Q(\blk00000003/sig00000ad6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig00000e7e ), + .Q15(\NLW_blk00000003/blk00000ca3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca2 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7d ), + .Q(\blk00000003/sig00000ad5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ca1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig00000e7d ), + .Q15(\NLW_blk00000003/blk00000ca1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca0 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7c ), + .Q(\blk00000003/sig00000ad4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig00000e7c ), + .Q15(\NLW_blk00000003/blk00000c9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7b ), + .Q(\blk00000003/sig00000ad3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig00000e7b ), + .Q15(\NLW_blk00000003/blk00000c9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e7a ), + .Q(\blk00000003/sig00000ad1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c9b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig00000e7a ), + .Q15(\NLW_blk00000003/blk00000c9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e79 ), + .Q(\blk00000003/sig00000ad0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c99 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig00000e79 ), + .Q15(\NLW_blk00000003/blk00000c99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c98 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e78 ), + .Q(\blk00000003/sig00000ad2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c97 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig00000e78 ), + .Q15(\NLW_blk00000003/blk00000c97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c96 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e77 ), + .Q(\blk00000003/sig00000acf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c95 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig00000e77 ), + .Q15(\NLW_blk00000003/blk00000c95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c94 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e76 ), + .Q(\blk00000003/sig00000ace ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c93 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig00000e76 ), + .Q15(\NLW_blk00000003/blk00000c93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c92 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e75 ), + .Q(\blk00000003/sig00000acd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c91 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig00000e75 ), + .Q15(\NLW_blk00000003/blk00000c91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c90 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e74 ), + .Q(\blk00000003/sig00000acc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000e74 ), + .Q15(\NLW_blk00000003/blk00000c8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8e ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e73 ), + .Q(\blk00000003/sig00000aca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000e73 ), + .Q15(\NLW_blk00000003/blk00000c8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8c ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e72 ), + .Q(\blk00000003/sig00000ac9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c8b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000e72 ), + .Q15(\NLW_blk00000003/blk00000c8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8a ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e71 ), + .Q(\blk00000003/sig00000acb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c89 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig00000e71 ), + .Q15(\NLW_blk00000003/blk00000c89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c88 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e70 ), + .Q(\blk00000003/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c87 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000e70 ), + .Q15(\NLW_blk00000003/blk00000c87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c86 ( + .C(clk), + .CE(\blk00000003/sig00000c9f ), + .D(\blk00000003/sig00000e6f ), + .Q(\blk00000003/sig00000ac8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c85 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9f ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000e6f ), + .Q15(\NLW_blk00000003/blk00000c85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c84 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6e ), + .Q(\blk00000003/sig00000af5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c83 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig00000e6e ), + .Q15(\NLW_blk00000003/blk00000c83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c82 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6d ), + .Q(\blk00000003/sig00000af4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c81 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig00000e6d ), + .Q15(\NLW_blk00000003/blk00000c81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c80 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6c ), + .Q(\blk00000003/sig00000af6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig00000e6c ), + .Q15(\NLW_blk00000003/blk00000c7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6b ), + .Q(\blk00000003/sig00000af3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000c7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e6a ), + .Q(\blk00000003/sig00000af2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000c7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e69 ), + .Q(\blk00000003/sig00000af1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000c79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c78 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e68 ), + .Q(\blk00000003/sig00000af0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000c77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c76 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e67 ), + .Q(\blk00000003/sig00000aee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000c75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c74 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e66 ), + .Q(\blk00000003/sig00000aed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000c73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c72 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e65 ), + .Q(\blk00000003/sig00000aef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000c71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c70 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e64 ), + .Q(\blk00000003/sig00000aec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000c6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6e ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e63 ), + .Q(\blk00000003/sig00000aeb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig00000e63 ), + .Q15(\NLW_blk00000003/blk00000c6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6c ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e62 ), + .Q(\blk00000003/sig00000aea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig00000e62 ), + .Q15(\NLW_blk00000003/blk00000c6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6a ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e61 ), + .Q(\blk00000003/sig00000ae9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig00000e61 ), + .Q15(\NLW_blk00000003/blk00000c69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c68 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e60 ), + .Q(\blk00000003/sig00000ae7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig00000e60 ), + .Q15(\NLW_blk00000003/blk00000c67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c66 ( + .C(clk), + .CE(\blk00000003/sig00000c6c ), + .D(\blk00000003/sig00000e5f ), + .Q(\blk00000003/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6c ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig00000e5f ), + .Q15(\NLW_blk00000003/blk00000c65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c64 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5e ), + .Q(\blk00000003/sig00000baa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/sig00000e5e ), + .Q15(\NLW_blk00000003/blk00000c63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c62 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5d ), + .Q(\blk00000003/sig00000ba9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/sig00000e5d ), + .Q15(\NLW_blk00000003/blk00000c61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c60 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5c ), + .Q(\blk00000003/sig00000ba8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/sig00000e5c ), + .Q15(\NLW_blk00000003/blk00000c5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5b ), + .Q(\blk00000003/sig00000ba7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/sig00000e5b ), + .Q15(\NLW_blk00000003/blk00000c5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e5a ), + .Q(\blk00000003/sig00000ba5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/sig00000e5a ), + .Q15(\NLW_blk00000003/blk00000c5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e59 ), + .Q(\blk00000003/sig00000ba4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/sig00000e59 ), + .Q15(\NLW_blk00000003/blk00000c59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c58 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e58 ), + .Q(\blk00000003/sig00000ba6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/sig00000e58 ), + .Q15(\NLW_blk00000003/blk00000c57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c56 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e57 ), + .Q(\blk00000003/sig00000ba3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/sig00000e57 ), + .Q15(\NLW_blk00000003/blk00000c55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c54 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e56 ), + .Q(\blk00000003/sig00000bb2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/sig00000e56 ), + .Q15(\NLW_blk00000003/blk00000c53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c52 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e55 ), + .Q(\blk00000003/sig00000bb1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/sig00000e55 ), + .Q15(\NLW_blk00000003/blk00000c51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e54 ), + .Q(\blk00000003/sig00000bb0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/sig00000e54 ), + .Q15(\NLW_blk00000003/blk00000c4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4e ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e53 ), + .Q(\blk00000003/sig00000baf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/sig00000e53 ), + .Q15(\NLW_blk00000003/blk00000c4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4c ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e52 ), + .Q(\blk00000003/sig00000bae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/sig00000e52 ), + .Q15(\NLW_blk00000003/blk00000c4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c4a ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e51 ), + .Q(\blk00000003/sig00000bac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/sig00000e51 ), + .Q15(\NLW_blk00000003/blk00000c49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c48 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e50 ), + .Q(\blk00000003/sig00000bab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/sig00000e50 ), + .Q15(\NLW_blk00000003/blk00000c47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c46 ( + .C(clk), + .CE(\blk00000003/sig00000c9e ), + .D(\blk00000003/sig00000e4f ), + .Q(\blk00000003/sig00000bad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9e ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/sig00000e4f ), + .Q15(\NLW_blk00000003/blk00000c45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c44 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4e ), + .Q(\blk00000003/sig00000aa6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000e4e ), + .Q15(\NLW_blk00000003/blk00000c43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c42 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4d ), + .Q(\blk00000003/sig00000aa4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000e4d ), + .Q15(\NLW_blk00000003/blk00000c41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c40 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4c ), + .Q(\blk00000003/sig00000aa3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000e4c ), + .Q15(\NLW_blk00000003/blk00000c3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4b ), + .Q(\blk00000003/sig00000aa5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000e4b ), + .Q15(\NLW_blk00000003/blk00000c3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e4a ), + .Q(\blk00000003/sig00000aa2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000c3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c3a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e49 ), + .Q(\blk00000003/sig00000aa1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000c39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c38 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e48 ), + .Q(\blk00000003/sig00000aa0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000c37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c36 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e47 ), + .Q(\blk00000003/sig00000a9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000c35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c34 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e46 ), + .Q(\blk00000003/sig00000a9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000c33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c32 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e45 ), + .Q(\blk00000003/sig00000a9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000c31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c30 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e44 ), + .Q(\blk00000003/sig00000a9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000c2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2e ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e43 ), + .Q(\blk00000003/sig00000a9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000c2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2c ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e42 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000c2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c2a ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e41 ), + .Q(\blk00000003/sig00000a99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000c29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c28 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e40 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000c27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c26 ( + .C(clk), + .CE(\blk00000003/sig00000c9d ), + .D(\blk00000003/sig00000e3f ), + .Q(\blk00000003/sig00000a97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000c25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c24 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3e ), + .Q(\blk00000003/sig00000ab6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000c23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c22 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3d ), + .Q(\blk00000003/sig00000ab5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000c21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c20 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3c ), + .Q(\blk00000003/sig00000ab4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000c1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3b ), + .Q(\blk00000003/sig00000ab3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000c1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e3a ), + .Q(\blk00000003/sig00000ab2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000c1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e39 ), + .Q(\blk00000003/sig00000ab0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000c19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c18 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e38 ), + .Q(\blk00000003/sig00000aaf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000c17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c16 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e37 ), + .Q(\blk00000003/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000c15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c14 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e36 ), + .Q(\blk00000003/sig00000aae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000c13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c12 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e35 ), + .Q(\blk00000003/sig00000aad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000c11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e34 ), + .Q(\blk00000003/sig00000aac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000c0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0e ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e33 ), + .Q(\blk00000003/sig00000aab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000c0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0c ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e32 ), + .Q(\blk00000003/sig00000aa9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000e32 ), + .Q15(\NLW_blk00000003/blk00000c0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0a ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e31 ), + .Q(\blk00000003/sig00000aa8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000e31 ), + .Q15(\NLW_blk00000003/blk00000c09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c08 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e30 ), + .Q(\blk00000003/sig00000aaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000e30 ), + .Q15(\NLW_blk00000003/blk00000c07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c06 ( + .C(clk), + .CE(\blk00000003/sig00000c6b ), + .D(\blk00000003/sig00000e2f ), + .Q(\blk00000003/sig00000aa7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6b ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000e2f ), + .Q15(\NLW_blk00000003/blk00000c05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000e2e ), + .Q(\blk00000003/sig00000c61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c03 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig00000e2e ), + .Q15(\NLW_blk00000003/blk00000c03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c02 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2d ), + .Q(\blk00000003/sig00000b9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig00000e2d ), + .Q15(\NLW_blk00000003/blk00000c01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c00 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2c ), + .Q(\blk00000003/sig00000b99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig00000e2c ), + .Q15(\NLW_blk00000003/blk00000bff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfe ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2b ), + .Q(\blk00000003/sig00000b97 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000e2b ), + .Q15(\NLW_blk00000003/blk00000bfd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfc ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e2a ), + .Q(\blk00000003/sig00000b96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000e2a ), + .Q15(\NLW_blk00000003/blk00000bfb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfa ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e29 ), + .Q(\blk00000003/sig00000b98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig00000e29 ), + .Q15(\NLW_blk00000003/blk00000bf9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e28 ), + .Q(\blk00000003/sig00000b95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig00000e28 ), + .Q15(\NLW_blk00000003/blk00000bf7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e27 ), + .Q(\blk00000003/sig00000b94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000e27 ), + .Q15(\NLW_blk00000003/blk00000bf5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e26 ), + .Q(\blk00000003/sig00000b93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000e26 ), + .Q15(\NLW_blk00000003/blk00000bf3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf2 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e25 ), + .Q(\blk00000003/sig00000ba2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/sig00000e25 ), + .Q15(\NLW_blk00000003/blk00000bf1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf0 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e24 ), + .Q(\blk00000003/sig00000ba1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/sig00000e24 ), + .Q15(\NLW_blk00000003/blk00000bef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bee ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e23 ), + .Q(\blk00000003/sig00000ba0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/sig00000e23 ), + .Q15(\NLW_blk00000003/blk00000bed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bec ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e22 ), + .Q(\blk00000003/sig00000b9f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000beb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/sig00000e22 ), + .Q15(\NLW_blk00000003/blk00000beb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bea ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e21 ), + .Q(\blk00000003/sig00000b9d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000e21 ), + .Q15(\NLW_blk00000003/blk00000be9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be8 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e20 ), + .Q(\blk00000003/sig00000b9c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig00000e20 ), + .Q15(\NLW_blk00000003/blk00000be7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be6 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1f ), + .Q(\blk00000003/sig00000b9e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000e1f ), + .Q15(\NLW_blk00000003/blk00000be5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be4 ( + .C(clk), + .CE(\blk00000003/sig00000c9c ), + .D(\blk00000003/sig00000e1e ), + .Q(\blk00000003/sig00000b9b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9c ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig00000e1e ), + .Q15(\NLW_blk00000003/blk00000be3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1d ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000e1d ), + .Q15(\NLW_blk00000003/blk00000be1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1c ), + .Q(\blk00000003/sig00000a85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000e1c ), + .Q15(\NLW_blk00000003/blk00000bdf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bde ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1b ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000e1b ), + .Q15(\NLW_blk00000003/blk00000bdd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e1a ), + .Q(\blk00000003/sig00000a83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000e1a ), + .Q15(\NLW_blk00000003/blk00000bdb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bda ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e19 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000e19 ), + .Q15(\NLW_blk00000003/blk00000bd9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e18 ), + .Q(\blk00000003/sig00000a81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000e18 ), + .Q15(\NLW_blk00000003/blk00000bd7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e17 ), + .Q(\blk00000003/sig00000a7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000e17 ), + .Q15(\NLW_blk00000003/blk00000bd5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e16 ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000e16 ), + .Q15(\NLW_blk00000003/blk00000bd3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd2 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e15 ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000e15 ), + .Q15(\NLW_blk00000003/blk00000bd1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd0 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e14 ), + .Q(\blk00000003/sig00000a7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000e14 ), + .Q15(\NLW_blk00000003/blk00000bcf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bce ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e13 ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000e13 ), + .Q15(\NLW_blk00000003/blk00000bcd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcc ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e12 ), + .Q(\blk00000003/sig00000a7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000e12 ), + .Q15(\NLW_blk00000003/blk00000bcb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bca ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e11 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000e11 ), + .Q15(\NLW_blk00000003/blk00000bc9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc8 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e10 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000e10 ), + .Q15(\NLW_blk00000003/blk00000bc7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc6 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0f ), + .Q(\blk00000003/sig00000a77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000e0f ), + .Q15(\NLW_blk00000003/blk00000bc5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc4 ( + .C(clk), + .CE(\blk00000003/sig00000c9b ), + .D(\blk00000003/sig00000e0e ), + .Q(\blk00000003/sig00000a79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9b ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000e0e ), + .Q15(\NLW_blk00000003/blk00000bc3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0d ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000e0d ), + .Q15(\NLW_blk00000003/blk00000bc1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0c ), + .Q(\blk00000003/sig00000a95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000e0c ), + .Q15(\NLW_blk00000003/blk00000bbf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbe ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0b ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000e0b ), + .Q15(\NLW_blk00000003/blk00000bbd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbc ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e0a ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000e0a ), + .Q15(\NLW_blk00000003/blk00000bbb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bba ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e09 ), + .Q(\blk00000003/sig00000a91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000e09 ), + .Q15(\NLW_blk00000003/blk00000bb9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e08 ), + .Q(\blk00000003/sig00000a93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000e08 ), + .Q15(\NLW_blk00000003/blk00000bb7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e07 ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000e07 ), + .Q15(\NLW_blk00000003/blk00000bb5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e06 ), + .Q(\blk00000003/sig00000a8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000e06 ), + .Q15(\NLW_blk00000003/blk00000bb3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb2 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e05 ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000e05 ), + .Q15(\NLW_blk00000003/blk00000bb1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb0 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e04 ), + .Q(\blk00000003/sig00000a8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000e04 ), + .Q15(\NLW_blk00000003/blk00000baf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bae ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e03 ), + .Q(\blk00000003/sig00000a8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000e03 ), + .Q15(\NLW_blk00000003/blk00000bad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bac ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e02 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000e02 ), + .Q15(\NLW_blk00000003/blk00000bab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baa ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e01 ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000e01 ), + .Q15(\NLW_blk00000003/blk00000ba9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba8 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000e00 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000e00 ), + .Q15(\NLW_blk00000003/blk00000ba7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba6 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dff ), + .Q(\blk00000003/sig00000a87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000dff ), + .Q15(\NLW_blk00000003/blk00000ba5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba4 ( + .C(clk), + .CE(\blk00000003/sig00000c6a ), + .D(\blk00000003/sig00000dfe ), + .Q(\blk00000003/sig00000a89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c6a ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000dfe ), + .Q15(\NLW_blk00000003/blk00000ba3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfd ), + .Q(\blk00000003/sig000002ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig00000dfd ), + .Q15(\NLW_blk00000003/blk00000ba1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfc ), + .Q(\blk00000003/sig00000258 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d98 ), + .Q(\blk00000003/sig00000dfc ), + .Q15(\NLW_blk00000003/blk00000b9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfb ), + .Q(\blk00000003/sig00000257 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d96 ), + .Q(\blk00000003/sig00000dfb ), + .Q15(\NLW_blk00000003/blk00000b9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dfa ), + .Q(\blk00000003/sig00000259 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d9a ), + .Q(\blk00000003/sig00000dfa ), + .Q15(\NLW_blk00000003/blk00000b9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df9 ), + .Q(\blk00000003/sig00000255 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b99 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8e ), + .Q(\blk00000003/sig00000df9 ), + .Q15(\NLW_blk00000003/blk00000b99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b98 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df8 ), + .Q(\blk00000003/sig00000254 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b97 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d92 ), + .Q(\blk00000003/sig00000df8 ), + .Q15(\NLW_blk00000003/blk00000b97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b96 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df7 ), + .Q(\blk00000003/sig00000256 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b95 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d94 ), + .Q(\blk00000003/sig00000df7 ), + .Q15(\NLW_blk00000003/blk00000b95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b94 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df6 ), + .Q(\blk00000003/sig00000253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b93 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d90 ), + .Q(\blk00000003/sig00000df6 ), + .Q15(\NLW_blk00000003/blk00000b93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b92 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df5 ), + .Q(\blk00000003/sig00000252 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b91 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8c ), + .Q(\blk00000003/sig00000df5 ), + .Q15(\NLW_blk00000003/blk00000b91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b90 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df4 ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d8a ), + .Q(\blk00000003/sig00000df4 ), + .Q15(\NLW_blk00000003/blk00000b8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df3 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d88 ), + .Q(\blk00000003/sig00000df3 ), + .Q15(\NLW_blk00000003/blk00000b8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df2 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d80 ), + .Q(\blk00000003/sig00000df2 ), + .Q15(\NLW_blk00000003/blk00000b8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df1 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b89 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d84 ), + .Q(\blk00000003/sig00000df1 ), + .Q15(\NLW_blk00000003/blk00000b89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b88 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000df0 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b87 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d86 ), + .Q(\blk00000003/sig00000df0 ), + .Q15(\NLW_blk00000003/blk00000b87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b86 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000def ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b85 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d82 ), + .Q(\blk00000003/sig00000def ), + .Q15(\NLW_blk00000003/blk00000b85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b84 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dee ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b83 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7e ), + .Q(\blk00000003/sig00000dee ), + .Q15(\NLW_blk00000003/blk00000b83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b82 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ded ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b81 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7c ), + .Q(\blk00000003/sig00000ded ), + .Q15(\NLW_blk00000003/blk00000b81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b80 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dec ), + .Q(\blk00000003/sig00000219 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d7a ), + .Q(\blk00000003/sig00000dec ), + .Q15(\NLW_blk00000003/blk00000b7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000deb ), + .Q(\blk00000003/sig00000217 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d72 ), + .Q(\blk00000003/sig00000deb ), + .Q15(\NLW_blk00000003/blk00000b7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dea ), + .Q(\blk00000003/sig00000216 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d76 ), + .Q(\blk00000003/sig00000dea ), + .Q15(\NLW_blk00000003/blk00000b7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de9 ), + .Q(\blk00000003/sig00000218 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b79 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d78 ), + .Q(\blk00000003/sig00000de9 ), + .Q15(\NLW_blk00000003/blk00000b79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b78 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de8 ), + .Q(\blk00000003/sig00000215 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b77 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d74 ), + .Q(\blk00000003/sig00000de8 ), + .Q15(\NLW_blk00000003/blk00000b77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b76 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de7 ), + .Q(\blk00000003/sig00000214 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b75 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d70 ), + .Q(\blk00000003/sig00000de7 ), + .Q15(\NLW_blk00000003/blk00000b75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b74 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de6 ), + .Q(\blk00000003/sig00000213 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b73 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6e ), + .Q(\blk00000003/sig00000de6 ), + .Q15(\NLW_blk00000003/blk00000b73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b72 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de5 ), + .Q(\blk00000003/sig00000212 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b71 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6c ), + .Q(\blk00000003/sig00000de5 ), + .Q15(\NLW_blk00000003/blk00000b71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b70 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de4 ), + .Q(\blk00000003/sig000001d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d64 ), + .Q(\blk00000003/sig00000de4 ), + .Q15(\NLW_blk00000003/blk00000b6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de3 ), + .Q(\blk00000003/sig000001cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d68 ), + .Q(\blk00000003/sig00000de3 ), + .Q15(\NLW_blk00000003/blk00000b6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de2 ), + .Q(\blk00000003/sig000001d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d6a ), + .Q(\blk00000003/sig00000de2 ), + .Q15(\NLW_blk00000003/blk00000b6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de1 ), + .Q(\blk00000003/sig000001ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b69 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d66 ), + .Q(\blk00000003/sig00000de1 ), + .Q15(\NLW_blk00000003/blk00000b69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b68 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000de0 ), + .Q(\blk00000003/sig000001cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b67 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d62 ), + .Q(\blk00000003/sig00000de0 ), + .Q15(\NLW_blk00000003/blk00000b67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b66 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddf ), + .Q(\blk00000003/sig000001cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b65 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d60 ), + .Q(\blk00000003/sig00000ddf ), + .Q15(\NLW_blk00000003/blk00000b65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b64 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dde ), + .Q(\blk00000003/sig000001cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b63 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5e ), + .Q(\blk00000003/sig00000dde ), + .Q15(\NLW_blk00000003/blk00000b63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b62 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddd ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b61 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d56 ), + .Q(\blk00000003/sig00000ddd ), + .Q15(\NLW_blk00000003/blk00000b61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b60 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5a ), + .Q(\blk00000003/sig00000ddc ), + .Q15(\NLW_blk00000003/blk00000b5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ddb ), + .Q(\blk00000003/sig000001ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d5c ), + .Q(\blk00000003/sig00000ddb ), + .Q15(\NLW_blk00000003/blk00000b5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dda ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d58 ), + .Q(\blk00000003/sig00000dda ), + .Q15(\NLW_blk00000003/blk00000b5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd9 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b59 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d54 ), + .Q(\blk00000003/sig00000dd9 ), + .Q15(\NLW_blk00000003/blk00000b59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd8 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b57 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d52 ), + .Q(\blk00000003/sig00000dd8 ), + .Q15(\NLW_blk00000003/blk00000b57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd7 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b55 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d50 ), + .Q(\blk00000003/sig00000dd7 ), + .Q15(\NLW_blk00000003/blk00000b55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b53 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d48 ), + .Q(\blk00000003/sig00000dd6 ), + .Q15(\NLW_blk00000003/blk00000b53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd5 ), + .Q(\blk00000003/sig0000017f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b51 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4c ), + .Q(\blk00000003/sig00000dd5 ), + .Q15(\NLW_blk00000003/blk00000b51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4e ), + .Q(\blk00000003/sig00000dd4 ), + .Q15(\NLW_blk00000003/blk00000b4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd3 ), + .Q(\blk00000003/sig0000017e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d4a ), + .Q(\blk00000003/sig00000dd3 ), + .Q15(\NLW_blk00000003/blk00000b4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd2 ), + .Q(\blk00000003/sig0000017d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d46 ), + .Q(\blk00000003/sig00000dd2 ), + .Q15(\NLW_blk00000003/blk00000b4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd1 ), + .Q(\blk00000003/sig0000017c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b49 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d44 ), + .Q(\blk00000003/sig00000dd1 ), + .Q15(\NLW_blk00000003/blk00000b49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dd0 ), + .Q(\blk00000003/sig0000017b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b47 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d42 ), + .Q(\blk00000003/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk00000b47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcf ), + .Q(\blk00000003/sig00000179 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b45 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3c ), + .Q(\blk00000003/sig00000dcf ), + .Q15(\NLW_blk00000003/blk00000b45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dce ), + .Q(\blk00000003/sig00000178 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b43 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d3e ), + .Q(\blk00000003/sig00000dce ), + .Q15(\NLW_blk00000003/blk00000b43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000dcd ), + .Q(\blk00000003/sig0000017a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b41 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000d40 ), + .Q(\blk00000003/sig00000dcd ), + .Q15(\NLW_blk00000003/blk00000b41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b40 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcc ), + .Q(\blk00000003/sig00000b8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig00000dcc ), + .Q15(\NLW_blk00000003/blk00000b3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dcb ), + .Q(\blk00000003/sig00000b88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig00000dcb ), + .Q15(\NLW_blk00000003/blk00000b3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dca ), + .Q(\blk00000003/sig00000b87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig00000dca ), + .Q15(\NLW_blk00000003/blk00000b3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc9 ), + .Q(\blk00000003/sig00000b89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk00000b39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b38 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc8 ), + .Q(\blk00000003/sig00000b86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig00000dc8 ), + .Q15(\NLW_blk00000003/blk00000b37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b36 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc7 ), + .Q(\blk00000003/sig00000b85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig00000dc7 ), + .Q15(\NLW_blk00000003/blk00000b35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b34 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc6 ), + .Q(\blk00000003/sig00000b84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig00000dc6 ), + .Q15(\NLW_blk00000003/blk00000b33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b32 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc5 ), + .Q(\blk00000003/sig00000b83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig00000dc5 ), + .Q15(\NLW_blk00000003/blk00000b31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b30 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc4 ), + .Q(\blk00000003/sig00000b92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000dc4 ), + .Q15(\NLW_blk00000003/blk00000b2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2e ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc3 ), + .Q(\blk00000003/sig00000b91 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000dc3 ), + .Q15(\NLW_blk00000003/blk00000b2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2c ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc2 ), + .Q(\blk00000003/sig00000b90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000dc2 ), + .Q15(\NLW_blk00000003/blk00000b2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2a ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc1 ), + .Q(\blk00000003/sig00000b8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000dc1 ), + .Q15(\NLW_blk00000003/blk00000b29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b28 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dc0 ), + .Q(\blk00000003/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig00000dc0 ), + .Q15(\NLW_blk00000003/blk00000b27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b26 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbf ), + .Q(\blk00000003/sig00000b8f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000dbf ), + .Q15(\NLW_blk00000003/blk00000b25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b24 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbe ), + .Q(\blk00000003/sig00000b8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000dbe ), + .Q15(\NLW_blk00000003/blk00000b23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b22 ( + .C(clk), + .CE(\blk00000003/sig00000c9a ), + .D(\blk00000003/sig00000dbd ), + .Q(\blk00000003/sig00000b8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c9a ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig00000dbd ), + .Q15(\NLW_blk00000003/blk00000b21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b20 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbc ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000dbc ), + .Q15(\NLW_blk00000003/blk00000b1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dbb ), + .Q(\blk00000003/sig00000a65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000dbb ), + .Q15(\NLW_blk00000003/blk00000b1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dba ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000dba ), + .Q15(\NLW_blk00000003/blk00000b1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db9 ), + .Q(\blk00000003/sig00000a63 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000db9 ), + .Q15(\NLW_blk00000003/blk00000b19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b18 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db8 ), + .Q(\blk00000003/sig00000a61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000db8 ), + .Q15(\NLW_blk00000003/blk00000b17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b16 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db7 ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000db7 ), + .Q15(\NLW_blk00000003/blk00000b15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b14 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db6 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000db6 ), + .Q15(\NLW_blk00000003/blk00000b13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b12 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db5 ), + .Q(\blk00000003/sig00000a5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000db5 ), + .Q15(\NLW_blk00000003/blk00000b11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b10 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db4 ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000db4 ), + .Q15(\NLW_blk00000003/blk00000b0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0e ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db3 ), + .Q(\blk00000003/sig00000a5d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000db3 ), + .Q15(\NLW_blk00000003/blk00000b0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0c ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db2 ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000db2 ), + .Q15(\NLW_blk00000003/blk00000b0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0a ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db1 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig00000db1 ), + .Q15(\NLW_blk00000003/blk00000b09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b08 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000db0 ), + .Q(\blk00000003/sig00000a59 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig00000db0 ), + .Q15(\NLW_blk00000003/blk00000b07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b06 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000daf ), + .Q(\blk00000003/sig00000a5b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000daf ), + .Q15(\NLW_blk00000003/blk00000b05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b04 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dae ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig00000dae ), + .Q15(\NLW_blk00000003/blk00000b03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b02 ( + .C(clk), + .CE(\blk00000003/sig00000c99 ), + .D(\blk00000003/sig00000dad ), + .Q(\blk00000003/sig00000a57 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c99 ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig00000dad ), + .Q15(\NLW_blk00000003/blk00000b01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b00 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dac ), + .Q(\blk00000003/sig00000a75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000dac ), + .Q15(\NLW_blk00000003/blk00000aff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afe ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000dab ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000dab ), + .Q15(\NLW_blk00000003/blk00000afd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afc ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000daa ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000daa ), + .Q15(\NLW_blk00000003/blk00000afb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afa ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da9 ), + .Q(\blk00000003/sig00000a73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000da9 ), + .Q15(\NLW_blk00000003/blk00000af9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da8 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000da8 ), + .Q15(\NLW_blk00000003/blk00000af7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da7 ), + .Q(\blk00000003/sig00000a71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000da7 ), + .Q15(\NLW_blk00000003/blk00000af5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da6 ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000da6 ), + .Q15(\NLW_blk00000003/blk00000af3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da5 ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000da5 ), + .Q15(\NLW_blk00000003/blk00000af1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af0 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da4 ), + .Q(\blk00000003/sig00000a6d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000da4 ), + .Q15(\NLW_blk00000003/blk00000aef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aee ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da3 ), + .Q(\blk00000003/sig00000a6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000da3 ), + .Q15(\NLW_blk00000003/blk00000aed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aec ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da2 ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aeb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000da2 ), + .Q15(\NLW_blk00000003/blk00000aeb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aea ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da1 ), + .Q(\blk00000003/sig00000a6b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000da1 ), + .Q15(\NLW_blk00000003/blk00000ae9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae8 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000da0 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000da0 ), + .Q15(\NLW_blk00000003/blk00000ae7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae6 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9f ), + .Q(\blk00000003/sig00000a69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000d9f ), + .Q15(\NLW_blk00000003/blk00000ae5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae4 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9e ), + .Q(\blk00000003/sig00000a67 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000d9e ), + .Q15(\NLW_blk00000003/blk00000ae3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae2 ( + .C(clk), + .CE(\blk00000003/sig00000c69 ), + .D(\blk00000003/sig00000d9d ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000d9d ), + .Q15(\NLW_blk00000003/blk00000ae1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9c ), + .Q(\blk00000003/sig00000a16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002af ), + .Q(\blk00000003/sig00000d9c ), + .Q15(\NLW_blk00000003/blk00000adf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ade ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d9b ), + .Q(\blk00000003/sig00000c62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000add ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029c ), + .Q(\blk00000003/sig00000d9b ), + .Q15(\NLW_blk00000003/blk00000add_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d99 ), + .Q(\blk00000003/sig00000d9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000d99 ), + .Q15(\NLW_blk00000003/blk00000adb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ada ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d97 ), + .Q(\blk00000003/sig00000d98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000d97 ), + .Q15(\NLW_blk00000003/blk00000ad9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d95 ), + .Q(\blk00000003/sig00000d96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000d95 ), + .Q15(\NLW_blk00000003/blk00000ad7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d93 ), + .Q(\blk00000003/sig00000d94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000d93 ), + .Q15(\NLW_blk00000003/blk00000ad5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d91 ), + .Q(\blk00000003/sig00000d92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000d91 ), + .Q15(\NLW_blk00000003/blk00000ad3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8f ), + .Q(\blk00000003/sig00000d90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000d8f ), + .Q15(\NLW_blk00000003/blk00000ad1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8d ), + .Q(\blk00000003/sig00000d8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000d8d ), + .Q15(\NLW_blk00000003/blk00000acf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ace ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d8b ), + .Q(\blk00000003/sig00000d8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000d8b ), + .Q15(\NLW_blk00000003/blk00000acd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d89 ), + .Q(\blk00000003/sig00000d8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000d89 ), + .Q15(\NLW_blk00000003/blk00000acb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aca ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d87 ), + .Q(\blk00000003/sig00000d88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000d87 ), + .Q15(\NLW_blk00000003/blk00000ac9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d85 ), + .Q(\blk00000003/sig00000d86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000d85 ), + .Q15(\NLW_blk00000003/blk00000ac7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d83 ), + .Q(\blk00000003/sig00000d84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000d83 ), + .Q15(\NLW_blk00000003/blk00000ac5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d81 ), + .Q(\blk00000003/sig00000d82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000d81 ), + .Q15(\NLW_blk00000003/blk00000ac3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7f ), + .Q(\blk00000003/sig00000d80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000d7f ), + .Q15(\NLW_blk00000003/blk00000ac1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7d ), + .Q(\blk00000003/sig00000d7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000d7d ), + .Q15(\NLW_blk00000003/blk00000abf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abe ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d7b ), + .Q(\blk00000003/sig00000d7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abd ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000d7b ), + .Q15(\NLW_blk00000003/blk00000abd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abc ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d79 ), + .Q(\blk00000003/sig00000d7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abb ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000d79 ), + .Q15(\NLW_blk00000003/blk00000abb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aba ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d77 ), + .Q(\blk00000003/sig00000d78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000d77 ), + .Q15(\NLW_blk00000003/blk00000ab9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d75 ), + .Q(\blk00000003/sig00000d76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000d75 ), + .Q15(\NLW_blk00000003/blk00000ab7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d73 ), + .Q(\blk00000003/sig00000d74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000d73 ), + .Q15(\NLW_blk00000003/blk00000ab5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d71 ), + .Q(\blk00000003/sig00000d72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000d71 ), + .Q15(\NLW_blk00000003/blk00000ab3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6f ), + .Q(\blk00000003/sig00000d70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000d6f ), + .Q15(\NLW_blk00000003/blk00000ab1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6d ), + .Q(\blk00000003/sig00000d6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaf ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000d6d ), + .Q15(\NLW_blk00000003/blk00000aaf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aae ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d6b ), + .Q(\blk00000003/sig00000d6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aad ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000d6b ), + .Q15(\NLW_blk00000003/blk00000aad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aac ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d69 ), + .Q(\blk00000003/sig00000d6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aab ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000d69 ), + .Q15(\NLW_blk00000003/blk00000aab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaa ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d67 ), + .Q(\blk00000003/sig00000d68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa9 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000d67 ), + .Q15(\NLW_blk00000003/blk00000aa9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa8 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d65 ), + .Q(\blk00000003/sig00000d66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa7 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000d65 ), + .Q15(\NLW_blk00000003/blk00000aa7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa6 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d63 ), + .Q(\blk00000003/sig00000d64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa5 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000d63 ), + .Q15(\NLW_blk00000003/blk00000aa5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa4 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d61 ), + .Q(\blk00000003/sig00000d62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa3 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000d61 ), + .Q15(\NLW_blk00000003/blk00000aa3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa2 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5f ), + .Q(\blk00000003/sig00000d60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa1 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000d5f ), + .Q15(\NLW_blk00000003/blk00000aa1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa0 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5d ), + .Q(\blk00000003/sig00000d5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000d5d ), + .Q15(\NLW_blk00000003/blk00000a9f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d5b ), + .Q(\blk00000003/sig00000d5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000d5b ), + .Q15(\NLW_blk00000003/blk00000a9d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d59 ), + .Q(\blk00000003/sig00000d5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000d59 ), + .Q15(\NLW_blk00000003/blk00000a9b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d57 ), + .Q(\blk00000003/sig00000d58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a99 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000d57 ), + .Q15(\NLW_blk00000003/blk00000a99_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a98 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d55 ), + .Q(\blk00000003/sig00000d56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a97 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000d55 ), + .Q15(\NLW_blk00000003/blk00000a97_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a96 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d53 ), + .Q(\blk00000003/sig00000d54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a95 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000d53 ), + .Q15(\NLW_blk00000003/blk00000a95_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a94 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d51 ), + .Q(\blk00000003/sig00000d52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a93 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000d51 ), + .Q15(\NLW_blk00000003/blk00000a93_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a92 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4f ), + .Q(\blk00000003/sig00000d50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000d4f ), + .Q15(\NLW_blk00000003/blk00000a91_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a90 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4d ), + .Q(\blk00000003/sig00000d4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000d4d ), + .Q15(\NLW_blk00000003/blk00000a8f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d4b ), + .Q(\blk00000003/sig00000d4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000d4b ), + .Q15(\NLW_blk00000003/blk00000a8d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8c ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d49 ), + .Q(\blk00000003/sig00000d4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8b ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000d49 ), + .Q15(\NLW_blk00000003/blk00000a8b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8a ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d47 ), + .Q(\blk00000003/sig00000d48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a89 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000d47 ), + .Q15(\NLW_blk00000003/blk00000a89_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a88 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d45 ), + .Q(\blk00000003/sig00000d46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a87 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000d45 ), + .Q15(\NLW_blk00000003/blk00000a87_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a86 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d43 ), + .Q(\blk00000003/sig00000d44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a85 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000d43 ), + .Q15(\NLW_blk00000003/blk00000a85_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a84 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d41 ), + .Q(\blk00000003/sig00000d42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a83 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000d41 ), + .Q15(\NLW_blk00000003/blk00000a83_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a82 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3f ), + .Q(\blk00000003/sig00000d40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a81 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000d3f ), + .Q15(\NLW_blk00000003/blk00000a81_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a80 ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3d ), + .Q(\blk00000003/sig00000d3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7f ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000d3d ), + .Q15(\NLW_blk00000003/blk00000a7f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7e ( + .C(clk), + .CE(\blk00000003/sig00000c6d ), + .D(\blk00000003/sig00000d3b ), + .Q(\blk00000003/sig00000d3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7d ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig00000c6d ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000d3b ), + .Q15(\NLW_blk00000003/blk00000a7d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d3a ), + .Q(\blk00000003/sig00000b79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig00000d3a ), + .Q15(\NLW_blk00000003/blk00000a7b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d39 ), + .Q(\blk00000003/sig00000b78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a79 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig00000d39 ), + .Q15(\NLW_blk00000003/blk00000a79_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a78 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d38 ), + .Q(\blk00000003/sig00000b7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a77 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig00000d38 ), + .Q15(\NLW_blk00000003/blk00000a77_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a76 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d37 ), + .Q(\blk00000003/sig00000b77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a75 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig00000d37 ), + .Q15(\NLW_blk00000003/blk00000a75_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a74 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d36 ), + .Q(\blk00000003/sig00000b76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a73 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig00000d36 ), + .Q15(\NLW_blk00000003/blk00000a73_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a72 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d35 ), + .Q(\blk00000003/sig00000b75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a71 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig00000d35 ), + .Q15(\NLW_blk00000003/blk00000a71_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a70 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d34 ), + .Q(\blk00000003/sig00000b74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig00000d34 ), + .Q15(\NLW_blk00000003/blk00000a6f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d33 ), + .Q(\blk00000003/sig00000b73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig00000d33 ), + .Q15(\NLW_blk00000003/blk00000a6d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6c ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d32 ), + .Q(\blk00000003/sig00000b82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig00000d32 ), + .Q15(\NLW_blk00000003/blk00000a6b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6a ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d31 ), + .Q(\blk00000003/sig00000b81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a69 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig00000d31 ), + .Q15(\NLW_blk00000003/blk00000a69_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a68 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d30 ), + .Q(\blk00000003/sig00000b7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a67 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig00000d30 ), + .Q15(\NLW_blk00000003/blk00000a67_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a66 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2f ), + .Q(\blk00000003/sig00000b7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a65 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig00000d2f ), + .Q15(\NLW_blk00000003/blk00000a65_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a64 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2e ), + .Q(\blk00000003/sig00000b80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a63 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig00000d2e ), + .Q15(\NLW_blk00000003/blk00000a63_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a62 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2d ), + .Q(\blk00000003/sig00000b7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a61 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig00000d2d ), + .Q15(\NLW_blk00000003/blk00000a61_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a60 ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2c ), + .Q(\blk00000003/sig00000b7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig00000d2c ), + .Q15(\NLW_blk00000003/blk00000a5f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5e ( + .C(clk), + .CE(\blk00000003/sig00000ca2 ), + .D(\blk00000003/sig00000d2b ), + .Q(\blk00000003/sig00000b7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca2 ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig00000d2b ), + .Q15(\NLW_blk00000003/blk00000a5d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d2a ), + .Q(\blk00000003/sig00000c6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000299 ), + .Q(\blk00000003/sig00000d2a ), + .Q15(\NLW_blk00000003/blk00000a5b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d29 ), + .Q(\blk00000003/sig00000c6f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a59 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000297 ), + .Q(\blk00000003/sig00000d29 ), + .Q15(\NLW_blk00000003/blk00000a59_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a58 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d28 ), + .Q(\blk00000003/sig00000c71 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a57 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000296 ), + .Q(\blk00000003/sig00000d28 ), + .Q15(\NLW_blk00000003/blk00000a57_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a56 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d27 ), + .Q(\blk00000003/sig00000c70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a55 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000298 ), + .Q(\blk00000003/sig00000d27 ), + .Q15(\NLW_blk00000003/blk00000a55_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a54 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d26 ), + .Q(\blk00000003/sig00000c73 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a53 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000295 ), + .Q(\blk00000003/sig00000d26 ), + .Q15(\NLW_blk00000003/blk00000a53_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a52 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d25 ), + .Q(\blk00000003/sig00000c72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a51 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig00000d25 ), + .Q15(\NLW_blk00000003/blk00000a51_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a50 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d24 ), + .Q(\blk00000003/sig00000c74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000293 ), + .Q(\blk00000003/sig00000d24 ), + .Q15(\NLW_blk00000003/blk00000a4f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d23 ), + .Q(\blk00000003/sig00000c76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000292 ), + .Q(\blk00000003/sig00000d23 ), + .Q15(\NLW_blk00000003/blk00000a4d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d22 ), + .Q(\blk00000003/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000d22 ), + .Q15(\NLW_blk00000003/blk00000a4b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d21 ), + .Q(\blk00000003/sig00000c79 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a49 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000d21 ), + .Q15(\NLW_blk00000003/blk00000a49_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a48 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d20 ), + .Q(\blk00000003/sig00000c75 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a47 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000d20 ), + .Q15(\NLW_blk00000003/blk00000a47_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a46 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1f ), + .Q(\blk00000003/sig00000c78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a45 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000d1f ), + .Q15(\NLW_blk00000003/blk00000a45_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a44 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1e ), + .Q(\blk00000003/sig00000c7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a43 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000d1e ), + .Q15(\NLW_blk00000003/blk00000a43_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a42 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1d ), + .Q(\blk00000003/sig00000c7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a41 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000d1d ), + .Q15(\NLW_blk00000003/blk00000a41_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a40 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1c ), + .Q(\blk00000003/sig00000c7b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000d1c ), + .Q15(\NLW_blk00000003/blk00000a3f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1b ), + .Q(\blk00000003/sig00000c7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000d1b ), + .Q15(\NLW_blk00000003/blk00000a3d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d1a ), + .Q(\blk00000003/sig00000c7f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000d1a ), + .Q15(\NLW_blk00000003/blk00000a3b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d19 ), + .Q(\blk00000003/sig00000c7d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a39 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000d19 ), + .Q15(\NLW_blk00000003/blk00000a39_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a38 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d18 ), + .Q(\blk00000003/sig00000c80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a37 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000d18 ), + .Q15(\NLW_blk00000003/blk00000a37_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a36 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d17 ), + .Q(\blk00000003/sig00000c82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a35 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000d17 ), + .Q15(\NLW_blk00000003/blk00000a35_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a34 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d16 ), + .Q(\blk00000003/sig00000c81 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a33 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000d16 ), + .Q15(\NLW_blk00000003/blk00000a33_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a32 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d15 ), + .Q(\blk00000003/sig00000c83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a31 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000d15 ), + .Q15(\NLW_blk00000003/blk00000a31_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a30 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d14 ), + .Q(\blk00000003/sig00000c84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000d14 ), + .Q15(\NLW_blk00000003/blk00000a2f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d13 ), + .Q(\blk00000003/sig00000c86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000d13 ), + .Q15(\NLW_blk00000003/blk00000a2d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d12 ), + .Q(\blk00000003/sig00000c85 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000a2b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d11 ), + .Q(\blk00000003/sig00000c88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a29 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000a29_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a28 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d10 ), + .Q(\blk00000003/sig00000c87 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a27 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000a27_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a26 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0f ), + .Q(\blk00000003/sig00000c89 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a25 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000a25_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a24 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0e ), + .Q(\blk00000003/sig00000c8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a23 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000a23_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a22 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0d ), + .Q(\blk00000003/sig00000c8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a21 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000a21_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a20 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0c ), + .Q(\blk00000003/sig00000c8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000a1f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000d0b ), + .Q(\blk00000003/sig00000c8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000a1d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d0a ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000a1b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d09 ), + .Q(\blk00000003/sig00000a45 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a19 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000a19_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a18 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d08 ), + .Q(\blk00000003/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a17 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000a17_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a16 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d07 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a15 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000a15_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a14 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d06 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a13 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000a13_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a12 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d05 ), + .Q(\blk00000003/sig00000a41 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a11 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000a11_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a10 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d04 ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000a0f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0e ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d03 ), + .Q(\blk00000003/sig00000a3f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000a0d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0c ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d02 ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000a0b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0a ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d01 ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a09 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000a09_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a08 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000d00 ), + .Q(\blk00000003/sig00000a3b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a07 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000a07_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a06 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cff ), + .Q(\blk00000003/sig00000a3d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a05 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000a05_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a04 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfe ), + .Q(\blk00000003/sig00000a3a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a03 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000a03_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a02 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfd ), + .Q(\blk00000003/sig00000a39 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a01 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000a01_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a00 ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfc ), + .Q(\blk00000003/sig00000a38 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig00000cfc ), + .Q15(\NLW_blk00000003/blk000009ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fe ( + .C(clk), + .CE(\blk00000003/sig00000ca1 ), + .D(\blk00000003/sig00000cfb ), + .Q(\blk00000003/sig00000a37 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000ca1 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig00000cfb ), + .Q15(\NLW_blk00000003/blk000009fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fc ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cfa ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig00000cfa ), + .Q15(\NLW_blk00000003/blk000009fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fa ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf9 ), + .Q(\blk00000003/sig00000a55 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig00000cf9 ), + .Q15(\NLW_blk00000003/blk000009f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf8 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig00000cf8 ), + .Q15(\NLW_blk00000003/blk000009f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf7 ), + .Q(\blk00000003/sig00000a53 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig00000cf7 ), + .Q15(\NLW_blk00000003/blk000009f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf6 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig00000cf6 ), + .Q15(\NLW_blk00000003/blk000009f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf5 ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig00000cf5 ), + .Q15(\NLW_blk00000003/blk000009f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf4 ), + .Q(\blk00000003/sig00000a4f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig00000cf4 ), + .Q15(\NLW_blk00000003/blk000009ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ee ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf3 ), + .Q(\blk00000003/sig00000a51 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig00000cf3 ), + .Q15(\NLW_blk00000003/blk000009ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ec ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf2 ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig00000cf2 ), + .Q15(\NLW_blk00000003/blk000009eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ea ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf1 ), + .Q(\blk00000003/sig00000a4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig00000cf1 ), + .Q15(\NLW_blk00000003/blk000009e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cf0 ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig00000cf0 ), + .Q15(\NLW_blk00000003/blk000009e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e6 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cef ), + .Q(\blk00000003/sig00000a4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000cef ), + .Q15(\NLW_blk00000003/blk000009e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e4 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cee ), + .Q(\blk00000003/sig00000a49 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000cee ), + .Q15(\NLW_blk00000003/blk000009e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e2 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ced ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000ced ), + .Q15(\NLW_blk00000003/blk000009e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e0 ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000cec ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig00000cec ), + .Q15(\NLW_blk00000003/blk000009df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009de ( + .C(clk), + .CE(\blk00000003/sig00000c68 ), + .D(\blk00000003/sig00000ceb ), + .Q(\blk00000003/sig00000a47 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig00000c68 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000ceb ), + .Q15(\NLW_blk00000003/blk000009dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cea ), + .Q(\blk00000003/sig00000ac6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009db ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig00000cea ), + .Q15(\NLW_blk00000003/blk000009db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce9 ), + .Q(\blk00000003/sig00000ac5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/sig00000ce9 ), + .Q15(\NLW_blk00000003/blk000009d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce8 ), + .Q(\blk00000003/sig00000ac4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000ce8 ), + .Q15(\NLW_blk00000003/blk000009d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce7 ), + .Q(\blk00000003/sig00000ac2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000ce7 ), + .Q15(\NLW_blk00000003/blk000009d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce6 ), + .Q(\blk00000003/sig00000ac1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000ce6 ), + .Q15(\NLW_blk00000003/blk000009d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce5 ), + .Q(\blk00000003/sig00000ac3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000ce5 ), + .Q15(\NLW_blk00000003/blk000009d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce4 ), + .Q(\blk00000003/sig00000ac0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000ce4 ), + .Q15(\NLW_blk00000003/blk000009cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce3 ), + .Q(\blk00000003/sig00000abf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000ce3 ), + .Q15(\NLW_blk00000003/blk000009cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce2 ), + .Q(\blk00000003/sig00000abe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000ce2 ), + .Q15(\NLW_blk00000003/blk000009cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce1 ), + .Q(\blk00000003/sig00000abd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig00000ce1 ), + .Q15(\NLW_blk00000003/blk000009c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ce0 ), + .Q(\blk00000003/sig00000abb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig00000ce0 ), + .Q15(\NLW_blk00000003/blk000009c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdf ), + .Q(\blk00000003/sig00000aba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig00000cdf ), + .Q15(\NLW_blk00000003/blk000009c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cde ), + .Q(\blk00000003/sig00000abc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig00000cde ), + .Q15(\NLW_blk00000003/blk000009c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdd ), + .Q(\blk00000003/sig00000ab9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000cdd ), + .Q15(\NLW_blk00000003/blk000009c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdc ), + .Q(\blk00000003/sig00000ab8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bf ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig00000cdc ), + .Q15(\NLW_blk00000003/blk000009bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cdb ), + .Q(\blk00000003/sig00000ab7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bd ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig00000cdb ), + .Q15(\NLW_blk00000003/blk000009bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cda ), + .Q(\blk00000003/sig00000bba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000cda ), + .Q15(\NLW_blk00000003/blk000009bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd9 ), + .Q(\blk00000003/sig00000bb8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000cd9 ), + .Q15(\NLW_blk00000003/blk000009b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd8 ), + .Q(\blk00000003/sig00000bb7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000cd8 ), + .Q15(\NLW_blk00000003/blk000009b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd7 ), + .Q(\blk00000003/sig00000bb9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000cd7 ), + .Q15(\NLW_blk00000003/blk000009b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd6 ), + .Q(\blk00000003/sig00000bb6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000cd6 ), + .Q15(\NLW_blk00000003/blk000009b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd5 ), + .Q(\blk00000003/sig00000bb5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000cd5 ), + .Q15(\NLW_blk00000003/blk000009b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd4 ), + .Q(\blk00000003/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009af ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000cd4 ), + .Q15(\NLW_blk00000003/blk000009af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd3 ), + .Q(\blk00000003/sig00000bb3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ad ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig00000cd3 ), + .Q15(\NLW_blk00000003/blk000009ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd2 ), + .Q(\blk00000003/sig00000ae5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ab ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000cd2 ), + .Q15(\NLW_blk00000003/blk000009ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd1 ), + .Q(\blk00000003/sig00000ae4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a9 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig00000cd1 ), + .Q15(\NLW_blk00000003/blk000009a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cd0 ), + .Q(\blk00000003/sig00000ae6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a7 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000cd0 ), + .Q15(\NLW_blk00000003/blk000009a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccf ), + .Q(\blk00000003/sig00000ae3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a5 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig00000ccf ), + .Q15(\NLW_blk00000003/blk000009a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cce ), + .Q(\blk00000003/sig00000ae2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a3 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig00000cce ), + .Q15(\NLW_blk00000003/blk000009a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccd ), + .Q(\blk00000003/sig00000ae1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000ccd ), + .Q15(\NLW_blk00000003/blk000009a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccc ), + .Q(\blk00000003/sig00000ae0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig00000ccc ), + .Q15(\NLW_blk00000003/blk0000099f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ccb ), + .Q(\blk00000003/sig00000ade ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000ccb ), + .Q15(\NLW_blk00000003/blk0000099d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cca ), + .Q(\blk00000003/sig00000add ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000cca ), + .Q15(\NLW_blk00000003/blk0000099b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc9 ), + .Q(\blk00000003/sig00000adf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000999 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig00000cc9 ), + .Q15(\NLW_blk00000003/blk00000999_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000998 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc8 ), + .Q(\blk00000003/sig00000adc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000997 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000cc8 ), + .Q15(\NLW_blk00000003/blk00000997_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000996 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc7 ), + .Q(\blk00000003/sig00000adb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000995 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000cc7 ), + .Q15(\NLW_blk00000003/blk00000995_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000994 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc6 ), + .Q(\blk00000003/sig00000ada ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000993 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000cc6 ), + .Q15(\NLW_blk00000003/blk00000993_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000992 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc5 ), + .Q(\blk00000003/sig00000ad9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000991 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000cc5 ), + .Q15(\NLW_blk00000003/blk00000991_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000990 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc4 ), + .Q(\blk00000003/sig00000ad7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk0000098f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc3 ), + .Q(\blk00000003/sig00000bca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk0000098d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc2 ), + .Q(\blk00000003/sig00000ad8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk0000098b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc1 ), + .Q(\blk00000003/sig00000bc9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000989 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000989_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000988 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cc0 ), + .Q(\blk00000003/sig00000bc8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000987 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000987_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000986 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbf ), + .Q(\blk00000003/sig00000bc7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000985 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000985_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000984 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbe ), + .Q(\blk00000003/sig00000bc6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000983 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000983_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000982 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbd ), + .Q(\blk00000003/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000981 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000981_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000980 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbc ), + .Q(\blk00000003/sig00000bc3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097f ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000cbc ), + .Q15(\NLW_blk00000003/blk0000097f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cbb ), + .Q(\blk00000003/sig00000bc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000cbb ), + .Q15(\NLW_blk00000003/blk0000097d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cba ), + .Q(\blk00000003/sig00000378 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097b ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a6 ), + .Q(\blk00000003/sig00000cba ), + .Q15(\NLW_blk00000003/blk0000097b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb9 ), + .Q(\blk00000003/sig00000379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000979 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000373 ), + .Q(\blk00000003/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000979_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000978 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb8 ), + .Q(\blk00000003/sig00000c66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000977 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a2 ), + .Q(\blk00000003/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000977_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000976 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb7 ), + .Q(\blk00000003/sig00000b08 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000975 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000975_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000974 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb6 ), + .Q(\blk00000003/sig00000b06 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000973 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000973_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000972 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb5 ), + .Q(\blk00000003/sig00000b05 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000971 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000971_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000970 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb4 ), + .Q(\blk00000003/sig00000b07 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk0000096f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb3 ), + .Q(\blk00000003/sig00000b04 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk0000096d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb2 ), + .Q(\blk00000003/sig00000b03 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk0000096b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb1 ), + .Q(\blk00000003/sig00000b02 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000969 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000969_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000968 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cb0 ), + .Q(\blk00000003/sig00000b01 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000967 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000967_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000966 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caf ), + .Q(\blk00000003/sig00000aff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000965 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000965_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000964 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cae ), + .Q(\blk00000003/sig00000afe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000963 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000963_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000962 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cad ), + .Q(\blk00000003/sig00000b00 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000961_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000960 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cac ), + .Q(\blk00000003/sig00000afd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000cac ), + .Q15(\NLW_blk00000003/blk0000095f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000cab ), + .Q(\blk00000003/sig00000afc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000cab ), + .Q15(\NLW_blk00000003/blk0000095d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000caa ), + .Q(\blk00000003/sig00000afb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000caa ), + .Q15(\NLW_blk00000003/blk0000095b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca9 ), + .Q(\blk00000003/sig00000afa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000959 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000ca9 ), + .Q15(\NLW_blk00000003/blk00000959_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000958 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca8 ), + .Q(\blk00000003/sig00000af8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000957 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000ca8 ), + .Q15(\NLW_blk00000003/blk00000957_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000956 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca7 ), + .Q(\blk00000003/sig00000af7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000955 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000ca7 ), + .Q15(\NLW_blk00000003/blk00000955_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000954 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca6 ), + .Q(\blk00000003/sig00000af9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000953 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000ca6 ), + .Q15(\NLW_blk00000003/blk00000953_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000952 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca5 ), + .Q(\blk00000003/sig000002af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000951 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000ca5 ), + .Q15(\NLW_blk00000003/blk00000951_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000950 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca4 ), + .Q(\blk00000003/sig00000a15 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig00000ca4 ), + .Q15(\NLW_blk00000003/blk0000094f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ca3 ), + .Q(\blk00000003/sig00000bd5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094d ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a0 ), + .Q(\blk00000003/sig00000ca3 ), + .Q15(\NLW_blk00000003/blk0000094d_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk0000094c ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000034a ) + ); + INV \blk00000003/blk0000094b ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000306 ) + ); + INV \blk00000003/blk0000094a ( + .I(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000343 ) + ); + INV \blk00000003/blk00000949 ( + .I(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000349 ) + ); + INV \blk00000003/blk00000948 ( + .I(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig00000358 ) + ); + INV \blk00000003/blk00000947 ( + .I(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c60 ) + ); + INV \blk00000003/blk00000946 ( + .I(\blk00000003/sig0000031c ), + .O(\blk00000003/sig0000035b ) + ); + INV \blk00000003/blk00000945 ( + .I(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000344 ) + ); + INV \blk00000003/blk00000944 ( + .I(\blk00000003/sig000002ee ), + .O(\blk00000003/sig0000031d ) + ); + INV \blk00000003/blk00000943 ( + .I(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig00000304 ) + ); + INV \blk00000003/blk00000942 ( + .I(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016e ) + ); + INV \blk00000003/blk00000941 ( + .I(\blk00000003/sig00000161 ), + .O(\blk00000003/sig0000029d ) + ); + INV \blk00000003/blk00000940 ( + .I(\blk00000003/sig0000016b ), + .O(\blk00000003/sig0000016c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093f ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093e ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000bd4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093c ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000ca1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093b ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000ca0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000093a ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c9f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000939 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000938 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c9d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000937 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000936 ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000935 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c9a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000934 ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c99 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000933 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000325 ), + .I2(coef_ld), + .O(\blk00000003/sig00000321 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000932 ( + .I0(\blk00000003/sig00000322 ), + .I1(\blk00000003/sig00000316 ), + .I2(\blk00000003/sig00000325 ), + .I3(coef_ld), + .I4(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000319 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000931 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig0000030e ), + .O(\blk00000003/sig00000320 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000930 ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(\blk00000003/sig00000325 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092f ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000c90 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092e ( + .I0(\blk00000003/sig00000353 ), + .I1(ce), + .I2(\blk00000003/sig00000316 ), + .I3(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000c98 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092d ( + .I0(\blk00000003/sig0000035a ), + .I1(ce), + .I2(\blk00000003/sig00000314 ), + .I3(\blk00000003/sig0000034b ), + .O(\blk00000003/sig00000c97 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk0000092c ( + .I0(\blk00000003/sig00000c64 ), + .I1(ce), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000c92 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000092b ( + .I0(ce), + .I1(\blk00000003/sig00000325 ), + .I2(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000c8f ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk0000092a ( + .I0(\blk00000003/sig000002b3 ), + .I1(\blk00000003/sig000002a8 ), + .I2(\blk00000003/sig00000c94 ), + .I3(ce), + .O(\blk00000003/sig00000c96 ) + ); + LUT5 #( + .INIT ( 32'h7FFF8000 )) + \blk00000003/blk00000929 ( + .I0(nd), + .I1(ce), + .I2(\blk00000003/sig00000159 ), + .I3(\blk00000003/sig00000c63 ), + .I4(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000c95 ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk00000928 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig00000c94 ), + .I2(ce), + .O(\blk00000003/sig00000c93 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk00000927 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig00000159 ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig00000c91 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000926 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032a ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk00000925 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig000002f8 ), + .I2(coef_we), + .I3(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032d ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000924 ( + .C(clk), + .D(\blk00000003/sig00000c98 ), + .Q(\blk00000003/sig00000353 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000923 ( + .C(clk), + .D(\blk00000003/sig00000c97 ), + .Q(\blk00000003/sig0000035a ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000922 ( + .C(clk), + .D(\blk00000003/sig00000c96 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .D(\blk00000003/sig00000c95 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000920 ( + .C(clk), + .D(\blk00000003/sig00000c93 ), + .R(sclr), + .Q(\blk00000003/sig00000c94 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .D(\blk00000003/sig00000c92 ), + .R(sclr), + .Q(\blk00000003/sig00000c64 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091e ( + .C(clk), + .D(\blk00000003/sig00000c91 ), + .R(sclr), + .Q(\blk00000003/sig00000c63 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091d ( + .I0(\blk00000003/sig00000beb ), + .O(\blk00000003/sig00000be5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091c ( + .I0(\blk00000003/sig00000bea ), + .O(\blk00000003/sig00000be2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091b ( + .I0(\blk00000003/sig00000be9 ), + .O(\blk00000003/sig00000bdf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000091a ( + .I0(\blk00000003/sig00000be8 ), + .O(\blk00000003/sig00000bdc ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000919 ( + .I0(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd9 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000918 ( + .I0(\blk00000003/sig00000375 ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000917 ( + .I0(\blk00000003/sig00000369 ), + .O(\blk00000003/sig00000363 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000916 ( + .I0(\blk00000003/sig00000334 ), + .O(\blk00000003/sig00000335 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000915 ( + .I0(\blk00000003/sig0000029e ), + .O(\blk00000003/sig0000016f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000914 ( + .I0(\blk00000003/sig00000c63 ), + .O(\blk00000003/sig00000160 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c5a ), + .R(sclr), + .Q(\blk00000003/sig00000c5f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000912 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c57 ), + .R(sclr), + .Q(\blk00000003/sig00000c5e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c54 ), + .R(sclr), + .Q(\blk00000003/sig00000c5d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000910 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c51 ), + .R(sclr), + .Q(\blk00000003/sig00000c5c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4e ), + .R(sclr), + .Q(\blk00000003/sig00000c5b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bd7 ), + .S(sclr), + .Q(\blk00000003/sig00000bec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be6 ), + .R(sclr), + .Q(\blk00000003/sig00000beb ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be3 ), + .S(sclr), + .Q(\blk00000003/sig00000bea ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000be0 ), + .S(sclr), + .Q(\blk00000003/sig00000be9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bdd ), + .R(sclr), + .Q(\blk00000003/sig00000be8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bda ), + .S(sclr), + .Q(\blk00000003/sig00000be7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000908 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .R(\blk00000003/sig0000037a ), + .Q(\blk00000003/sig00000375 ) + ); + FDR \blk00000003/blk00000907 ( + .C(clk), + .D(\blk00000003/sig00000c90 ), + .R(ce), + .Q(\blk00000003/sig00000c67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000906 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036c ), + .S(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000036a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000904 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000364 ), + .S(sclr), + .Q(\blk00000003/sig00000369 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000367 ), + .R(sclr), + .Q(\blk00000003/sig00000368 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000902 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000035e ), + .R(sclr), + .Q(\blk00000003/sig000002ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000361 ), + .R(sclr), + .Q(\blk00000003/sig000002b9 ) + ); + FDR \blk00000003/blk00000900 ( + .C(clk), + .D(\blk00000003/sig00000c8f ), + .R(ce), + .Q(\blk00000003/sig00000c65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000336 ), + .R(\blk00000003/sig00000339 ), + .Q(\blk00000003/sig00000334 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000328 ), + .R(coef_ld), + .Q(\blk00000003/sig00000332 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032e ), + .R(coef_ld), + .Q(\blk00000003/sig00000331 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032b ), + .R(coef_ld), + .Q(\blk00000003/sig00000330 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f4 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk000008fa ( + .I0(\blk00000003/sig0000016b ), + .I1(sclr), + .O(\blk00000003/sig00000c8e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008f9 ( + .C(clk), + .D(\blk00000003/sig00000c8e ), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000163 ), + .R(sclr), + .Q(\blk00000003/sig00000161 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f7 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f6 ( + .I0(\blk00000003/sig00000c5c ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c50 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f5 ( + .I0(\blk00000003/sig00000c5d ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c53 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000008f4 ( + .I0(\blk00000003/sig00000c5e ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c56 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000008f3 ( + .I0(\blk00000003/sig00000c5f ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000c59 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000008f2 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000c4b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000c49 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008f0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000dd ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000c4a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ef ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000c48 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ee ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000c46 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ed ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000c47 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ec ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000c45 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008eb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig00000c43 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ea ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig00000c44 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000c42 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000c40 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000c41 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000c3f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000c3d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000c3e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000c3c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000c3a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000c3b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008e0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000c39 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008df ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000c37 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008de ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000c38 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000c36 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008dc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig00000c34 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008db ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000c35 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008da ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig00000c33 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000c31 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000c32 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000c30 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000c2e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000c2f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000c2d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8d ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000c2b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000c2c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000c2a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008d0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8b ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000c28 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c8a ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000c29 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ce ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c89 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000c27 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c88 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000c25 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c87 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000c26 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008cb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c86 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig00000c24 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c85 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000c22 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c84 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig00000c23 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c83 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000c21 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c82 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000c1f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c81 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000c20 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c80 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000c1e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7f ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000c1d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000c1b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7e ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000c1c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000c1a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000c18 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bf ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000c19 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008be ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000c17 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bd ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000c15 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bc ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000c16 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008bb ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig00000c14 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ba ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000c12 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000c13 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000c11 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000c0f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000c10 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000c0e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000c0c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000c0d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000c0b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000c09 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000c0a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000c08 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000c06 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ad ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000c07 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ac ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000c05 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008ab ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000c03 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008aa ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig00000c04 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a9 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000c02 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a8 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000c00 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a7 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000c01 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a6 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000bff ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a5 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000bfd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a4 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000bfe ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a3 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7d ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000bfc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a2 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7c ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000bfa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a1 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7b ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000bfb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000008a0 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c7a ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000bf9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089f ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c79 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000bf7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089e ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c78 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000bf8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089d ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c77 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000bf6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089c ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c76 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig00000bf4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089b ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c75 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000bf5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000089a ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c74 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000bf3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000899 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c73 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000bf1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000898 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c72 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000bf2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000897 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c71 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000bf0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000896 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c70 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000bee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000895 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6f ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000bef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000894 ( + .I0(\blk00000003/sig0000029e ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig00000c6e ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000bed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig00000bec ), + .I1(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig00000bd6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000892 ( + .I0(ce), + .I1(\blk00000003/sig000002af ), + .O(\blk00000003/sig00000c6d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000891 ( + .I0(ce), + .I1(\blk00000003/sig00000a0f ), + .O(\blk00000003/sig00000c6c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000890 ( + .I0(ce), + .I1(\blk00000003/sig00000a0a ), + .O(\blk00000003/sig00000c6b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088f ( + .I0(ce), + .I1(\blk00000003/sig00000a03 ), + .O(\blk00000003/sig00000c6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088e ( + .I0(ce), + .I1(\blk00000003/sig000009f7 ), + .O(\blk00000003/sig00000c69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000088d ( + .I0(ce), + .I1(\blk00000003/sig000009f8 ), + .O(\blk00000003/sig00000c68 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000088c ( + .I0(sclr), + .I1(\blk00000003/sig00000c67 ), + .O(\blk00000003/sig00000372 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .O(\blk00000003/sig0000036d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig0000036a ), + .I1(\blk00000003/sig00000378 ), + .O(\blk00000003/sig0000036b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig00000378 ), + .I1(\blk00000003/sig00000c66 ), + .I2(\blk00000003/sig0000036f ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig000002a8 ), + .O(\blk00000003/sig00000366 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000887 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .O(\blk00000003/sig00000362 ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000886 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002b9 ), + .O(\blk00000003/sig00000360 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000885 ( + .I0(nd), + .I1(\blk00000003/sig0000015f ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000035d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000359 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000356 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig00000354 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig0000031a ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig0000031a ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig0000031c ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000315 ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig00000318 ), + .I1(\blk00000003/sig00000314 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig0000031c ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000312 ), + .O(\blk00000003/sig00000341 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000318 ), + .O(\blk00000003/sig0000033d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig00000316 ), + .I1(\blk00000003/sig00000318 ), + .I2(\blk00000003/sig00000322 ), + .O(\blk00000003/sig0000033f ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig00000c65 ), + .O(\blk00000003/sig00000338 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000002f8 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .O(\blk00000003/sig0000032f ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig00000332 ), + .I1(\blk00000003/sig000002f8 ), + .I2(\blk00000003/sig00000302 ), + .I3(coef_we), + .O(\blk00000003/sig00000327 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000877 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000325 ), + .O(\blk00000003/sig0000031b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000876 ( + .I0(coef_we), + .I1(\blk00000003/sig00000302 ), + .O(\blk00000003/sig000002f9 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000875 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000323 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig00000330 ), + .I1(\blk00000003/sig00000331 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fe ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig00000331 ), + .I1(\blk00000003/sig00000330 ), + .I2(\blk00000003/sig00000332 ), + .O(\blk00000003/sig000002fc ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig00000325 ), + .I1(\blk00000003/sig0000030e ), + .I2(coef_ld), + .O(\blk00000003/sig000002f3 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig0000030e ), + .O(\blk00000003/sig000002f0 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000002f4 ), + .I1(coef_we), + .O(\blk00000003/sig000002f5 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig00000310 ), + .I1(coef_we), + .I2(\blk00000003/sig00000302 ), + .I3(\blk00000003/sig000002f8 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030f ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig0000030e ), + .I1(\blk00000003/sig00000310 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig0000030d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig00000159 ), + .I1(nd), + .O(\blk00000003/sig000002b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002b5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig00000173 ), + .I1(\blk00000003/sig00000be7 ), + .I2(\blk00000003/sig000002ad ), + .O(\blk00000003/sig00000174 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000086a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000be7 ), + .O(\blk00000003/sig000002ae ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig00000c5b ), + .I1(\blk00000003/sig00000c5c ), + .I2(\blk00000003/sig00000c5d ), + .I3(\blk00000003/sig00000c5e ), + .I4(\blk00000003/sig00000c5f ), + .O(\blk00000003/sig00000177 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000002a8 ), + .I1(\blk00000003/sig0000029c ), + .I2(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig00000369 ), + .I1(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002a9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000866 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000169 ), + .O(\blk00000003/sig00000168 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000865 ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000167 ), + .O(\blk00000003/sig00000166 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig00000161 ), + .I1(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000162 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig0000029c ), + .I1(\blk00000003/sig000002b6 ), + .I2(\blk00000003/sig000002a6 ), + .I3(\blk00000003/sig000002a8 ), + .I4(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig00000c64 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002b6 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig00000c63 ), + .I1(\blk00000003/sig000002b9 ), + .I2(\blk00000003/sig000002ba ), + .O(\blk00000003/sig0000015d ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000002a8 ), + .I3(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig00000368 ), + .I1(\blk00000003/sig00000369 ), + .I2(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002ab ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000085e ( + .I0(ce), + .I1(\blk00000003/sig00000c61 ), + .I2(\blk00000003/sig00000c62 ), + .I3(\blk00000003/sig00000165 ), + .O(\blk00000003/sig00000164 ) + ); + MUXCY \blk00000003/blk0000085d ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000c60 ), + .O(\blk00000003/sig00000c58 ) + ); + MUXCY_L \blk00000003/blk0000085c ( + .CI(\blk00000003/sig00000c58 ), + .DI(\blk00000003/sig00000c5f ), + .S(\blk00000003/sig00000c59 ), + .LO(\blk00000003/sig00000c55 ) + ); + MUXCY_L \blk00000003/blk0000085b ( + .CI(\blk00000003/sig00000c55 ), + .DI(\blk00000003/sig00000c5e ), + .S(\blk00000003/sig00000c56 ), + .LO(\blk00000003/sig00000c52 ) + ); + MUXCY_L \blk00000003/blk0000085a ( + .CI(\blk00000003/sig00000c52 ), + .DI(\blk00000003/sig00000c5d ), + .S(\blk00000003/sig00000c53 ), + .LO(\blk00000003/sig00000c4f ) + ); + MUXCY_L \blk00000003/blk00000859 ( + .CI(\blk00000003/sig00000c4f ), + .DI(\blk00000003/sig00000c5c ), + .S(\blk00000003/sig00000c50 ), + .LO(\blk00000003/sig00000c4c ) + ); + MUXCY_D \blk00000003/blk00000858 ( + .CI(\blk00000003/sig00000c4c ), + .DI(\blk00000003/sig00000c5b ), + .S(\blk00000003/sig00000c4d ), + .O(\NLW_blk00000003/blk00000858_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000858_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000857 ( + .CI(\blk00000003/sig00000c58 ), + .LI(\blk00000003/sig00000c59 ), + .O(\blk00000003/sig00000c5a ) + ); + XORCY \blk00000003/blk00000856 ( + .CI(\blk00000003/sig00000c55 ), + .LI(\blk00000003/sig00000c56 ), + .O(\blk00000003/sig00000c57 ) + ); + XORCY \blk00000003/blk00000855 ( + .CI(\blk00000003/sig00000c52 ), + .LI(\blk00000003/sig00000c53 ), + .O(\blk00000003/sig00000c54 ) + ); + XORCY \blk00000003/blk00000854 ( + .CI(\blk00000003/sig00000c4f ), + .LI(\blk00000003/sig00000c50 ), + .O(\blk00000003/sig00000c51 ) + ); + XORCY \blk00000003/blk00000853 ( + .CI(\blk00000003/sig00000c4c ), + .LI(\blk00000003/sig00000c4d ), + .O(\blk00000003/sig00000c4e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000852 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4b ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000851 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c4a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000850 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c49 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c48 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c47 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c46 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c45 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c44 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c43 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000849 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c42 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000848 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c41 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000847 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c40 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000846 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000845 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000844 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000843 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000842 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000841 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c3a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000840 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c39 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c38 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c37 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c36 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c35 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c34 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c33 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000839 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c32 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000838 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c31 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000837 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c30 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000836 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000835 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000834 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000833 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000832 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000831 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c2a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000830 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c29 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c28 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c27 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c26 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c25 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c24 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000082a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c23 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000829 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c22 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000828 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c21 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000827 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c20 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000826 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000825 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000824 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000823 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000822 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000821 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c1a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000820 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c19 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c18 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c17 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c16 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c15 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c14 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000081a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c13 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000819 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c12 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000818 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c11 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000817 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c10 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000816 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000815 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000814 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000813 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000812 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000811 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c0a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000810 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c09 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c08 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c07 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c06 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c05 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c04 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000080a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c03 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000809 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c02 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000808 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c01 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000c00 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000806 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bff ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000805 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfe ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000804 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000803 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000802 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000801 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bfa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bf0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000bed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000bec ), + .S(\blk00000003/sig00000bd6 ), + .LO(\blk00000003/sig00000be4 ) + ); + MUXCY_L \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig00000be4 ), + .DI(\blk00000003/sig00000beb ), + .S(\blk00000003/sig00000be5 ), + .LO(\blk00000003/sig00000be1 ) + ); + MUXCY_L \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig00000be1 ), + .DI(\blk00000003/sig00000bea ), + .S(\blk00000003/sig00000be2 ), + .LO(\blk00000003/sig00000bde ) + ); + MUXCY_L \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig00000bde ), + .DI(\blk00000003/sig00000be9 ), + .S(\blk00000003/sig00000bdf ), + .LO(\blk00000003/sig00000bdb ) + ); + MUXCY_L \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000bdb ), + .DI(\blk00000003/sig00000be8 ), + .S(\blk00000003/sig00000bdc ), + .LO(\blk00000003/sig00000bd8 ) + ); + MUXCY_D \blk00000003/blk000007ee ( + .CI(\blk00000003/sig00000bd8 ), + .DI(\blk00000003/sig00000be7 ), + .S(\blk00000003/sig00000bd9 ), + .O(\NLW_blk00000003/blk000007ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007ed ( + .CI(\blk00000003/sig00000be4 ), + .LI(\blk00000003/sig00000be5 ), + .O(\blk00000003/sig00000be6 ) + ); + XORCY \blk00000003/blk000007ec ( + .CI(\blk00000003/sig00000be1 ), + .LI(\blk00000003/sig00000be2 ), + .O(\blk00000003/sig00000be3 ) + ); + XORCY \blk00000003/blk000007eb ( + .CI(\blk00000003/sig00000bde ), + .LI(\blk00000003/sig00000bdf ), + .O(\blk00000003/sig00000be0 ) + ); + XORCY \blk00000003/blk000007ea ( + .CI(\blk00000003/sig00000bdb ), + .LI(\blk00000003/sig00000bdc ), + .O(\blk00000003/sig00000bdd ) + ); + XORCY \blk00000003/blk000007e9 ( + .CI(\blk00000003/sig00000bd8 ), + .LI(\blk00000003/sig00000bd9 ), + .O(\blk00000003/sig00000bda ) + ); + XORCY \blk00000003/blk000007e8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000bd6 ), + .O(\blk00000003/sig00000bd7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000777 ), + .R(sclr), + .Q(\blk00000003/sig00000a26 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000776 ), + .R(sclr), + .Q(\blk00000003/sig00000a25 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000775 ), + .R(sclr), + .Q(\blk00000003/sig00000a24 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000774 ), + .R(sclr), + .Q(\blk00000003/sig00000a23 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000773 ), + .R(sclr), + .Q(\blk00000003/sig00000a22 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000772 ), + .R(sclr), + .Q(\blk00000003/sig00000a21 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000771 ), + .R(sclr), + .Q(\blk00000003/sig00000a20 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000770 ), + .R(sclr), + .Q(\blk00000003/sig00000a1f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076f ), + .R(sclr), + .Q(\blk00000003/sig00000a1e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076e ), + .R(sclr), + .Q(\blk00000003/sig00000a1d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076d ), + .R(sclr), + .Q(\blk00000003/sig00000a1c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076c ), + .R(sclr), + .Q(\blk00000003/sig00000a1b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076b ), + .R(sclr), + .Q(\blk00000003/sig00000a1a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig0000076a ), + .R(sclr), + .Q(\blk00000003/sig00000a19 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000769 ), + .R(sclr), + .Q(\blk00000003/sig00000a18 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig00000768 ), + .R(sclr), + .Q(\blk00000003/sig00000a17 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig00000b6a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ec ), + .R(sclr), + .Q(\blk00000003/sig00000b69 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig00000b68 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004ea ), + .R(sclr), + .Q(\blk00000003/sig00000b67 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig00000b66 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e8 ), + .R(sclr), + .Q(\blk00000003/sig00000b65 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig00000b64 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000004e6 ), + .R(sclr), + .Q(\blk00000003/sig00000b63 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(\blk00000003/sig00000a36 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(\blk00000003/sig00000a35 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(\blk00000003/sig00000a34 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(\blk00000003/sig00000a33 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(\blk00000003/sig00000a32 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(\blk00000003/sig00000a31 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(\blk00000003/sig00000a30 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(\blk00000003/sig00000bd4 ), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(\blk00000003/sig00000a2f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(\blk00000003/sig00000a2e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(\blk00000003/sig00000a2d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(\blk00000003/sig00000a2c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(\blk00000003/sig00000a2b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(\blk00000003/sig00000a2a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(\blk00000003/sig00000a29 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(\blk00000003/sig00000a28 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(\blk00000003/sig00000a27 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(\blk00000003/sig00000b72 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(\blk00000003/sig00000b71 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(\blk00000003/sig00000b70 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(\blk00000003/sig00000b6f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(\blk00000003/sig00000b6e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(\blk00000003/sig00000b6d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(\blk00000003/sig00000b6c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(\blk00000003/sig00000bd3 ), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(\blk00000003/sig00000b6b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000375 ), + .R(sclr), + .Q(\blk00000003/sig00000a12 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037b ), + .R(sclr), + .Q(\blk00000003/sig00000a11 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036a ), + .R(sclr), + .Q(\blk00000003/sig00000a14 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a16 ), + .R(sclr), + .Q(\blk00000003/sig00000a10 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a15 ), + .R(sclr), + .Q(\blk00000003/sig00000a0f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036f ), + .R(sclr), + .Q(\blk00000003/sig00000a13 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a14 ), + .R(sclr), + .Q(\blk00000003/sig00000a0d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a13 ), + .R(sclr), + .Q(\blk00000003/sig00000a0e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a12 ), + .R(sclr), + .Q(\blk00000003/sig00000a0c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a11 ), + .R(sclr), + .Q(\blk00000003/sig00000a0b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a10 ), + .R(sclr), + .Q(\blk00000003/sig00000a09 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0f ), + .R(sclr), + .Q(\blk00000003/sig00000a0a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0e ), + .R(sclr), + .Q(\blk00000003/sig00000a08 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0d ), + .R(sclr), + .Q(\blk00000003/sig00000a07 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0c ), + .R(sclr), + .Q(\blk00000003/sig00000a05 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .R(sclr), + .Q(\blk00000003/sig00000a04 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0a ), + .R(sclr), + .Q(\blk00000003/sig00000a03 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .R(sclr), + .Q(\blk00000003/sig00000a06 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .R(sclr), + .Q(\blk00000003/sig00000a01 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .R(sclr), + .Q(\blk00000003/sig000009ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .R(sclr), + .Q(\blk00000003/sig000009f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .R(sclr), + .Q(\blk00000003/sig000009fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .R(sclr), + .Q(\blk00000003/sig000009fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .R(sclr), + .Q(\blk00000003/sig000009f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .R(sclr), + .Q(\blk00000003/sig00000a02 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .R(sclr), + .Q(\blk00000003/sig00000a00 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .R(sclr), + .Q(\blk00000003/sig000009fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .R(sclr), + .Q(\blk00000003/sig000009fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .R(sclr), + .Q(\blk00000003/sig000009fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .R(sclr), + .Q(\blk00000003/sig000009f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000337 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000009e8 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000009c8 , \blk00000003/sig000009c9 , \blk00000003/sig000009ca , +\blk00000003/sig000009cb , \blk00000003/sig000009cc , \blk00000003/sig000009cd , \blk00000003/sig000009ce , \blk00000003/sig000009cf , +\blk00000003/sig000009d0 , \blk00000003/sig000009d1 , \blk00000003/sig000009d2 , \blk00000003/sig000009d3 , \blk00000003/sig000009d4 , +\blk00000003/sig000009d5 , \blk00000003/sig000009d6 , \blk00000003/sig000009d7 }), + .BCOUT({\NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .C({\NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , 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\blk00000003/sig000009e6 , \blk00000003/sig000009e7 }), + .PCOUT({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , 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.RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000978 , \blk00000003/sig00000979 , \blk00000003/sig0000097a , +\blk00000003/sig0000097b , \blk00000003/sig0000097c , \blk00000003/sig0000097d , \blk00000003/sig0000097e , \blk00000003/sig0000097f , +\blk00000003/sig00000980 , \blk00000003/sig00000981 , \blk00000003/sig00000982 , \blk00000003/sig00000983 , \blk00000003/sig00000984 , +\blk00000003/sig00000985 , \blk00000003/sig00000986 , \blk00000003/sig00000987 }), + .BCOUT({\NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , 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\NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000988 , \blk00000003/sig00000989 , \blk00000003/sig0000098a , +\blk00000003/sig0000098b , \blk00000003/sig0000098c , \blk00000003/sig0000098d , \blk00000003/sig0000098e , \blk00000003/sig0000098f , +\blk00000003/sig00000990 , \blk00000003/sig00000991 , \blk00000003/sig00000992 , \blk00000003/sig00000993 , \blk00000003/sig00000994 , +\blk00000003/sig00000995 , \blk00000003/sig00000996 , \blk00000003/sig00000997 }), + .PCOUT({\blk00000003/sig00000998 , \blk00000003/sig00000999 , \blk00000003/sig0000099a , \blk00000003/sig0000099b , \blk00000003/sig0000099c , +\blk00000003/sig0000099d , \blk00000003/sig0000099e , \blk00000003/sig0000099f , \blk00000003/sig000009a0 , \blk00000003/sig000009a1 , +\blk00000003/sig000009a2 , \blk00000003/sig000009a3 , \blk00000003/sig000009a4 , \blk00000003/sig000009a5 , \blk00000003/sig000009a6 , +\blk00000003/sig000009a7 , \blk00000003/sig000009a8 , \blk00000003/sig000009a9 , \blk00000003/sig000009aa , \blk00000003/sig000009ab , +\blk00000003/sig000009ac , \blk00000003/sig000009ad , \blk00000003/sig000009ae , \blk00000003/sig000009af , \blk00000003/sig000009b0 , +\blk00000003/sig000009b1 , \blk00000003/sig000009b2 , \blk00000003/sig000009b3 , \blk00000003/sig000009b4 , \blk00000003/sig000009b5 , +\blk00000003/sig000009b6 , \blk00000003/sig000009b7 , \blk00000003/sig000009b8 , \blk00000003/sig000009b9 , \blk00000003/sig000009ba , +\blk00000003/sig000009bb , \blk00000003/sig000009bc , \blk00000003/sig000009bd , \blk00000003/sig000009be , \blk00000003/sig000009bf , +\blk00000003/sig000009c0 , \blk00000003/sig000009c1 , \blk00000003/sig000009c2 , \blk00000003/sig000009c3 , \blk00000003/sig000009c4 , +\blk00000003/sig000009c5 , \blk00000003/sig000009c6 , \blk00000003/sig000009c7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000928 , \blk00000003/sig00000929 , \blk00000003/sig0000092a , +\blk00000003/sig0000092b , \blk00000003/sig0000092c , \blk00000003/sig0000092d , \blk00000003/sig0000092e , \blk00000003/sig0000092f , +\blk00000003/sig00000930 , \blk00000003/sig00000931 , \blk00000003/sig00000932 , \blk00000003/sig00000933 , \blk00000003/sig00000934 , +\blk00000003/sig00000935 , \blk00000003/sig00000936 , \blk00000003/sig00000937 }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000008f8 , \blk00000003/sig000008f9 , \blk00000003/sig000008fa , \blk00000003/sig000008fb , \blk00000003/sig000008fc , +\blk00000003/sig000008fd , \blk00000003/sig000008fe , \blk00000003/sig000008ff , \blk00000003/sig00000900 , \blk00000003/sig00000901 , +\blk00000003/sig00000902 , \blk00000003/sig00000903 , \blk00000003/sig00000904 , \blk00000003/sig00000905 , \blk00000003/sig00000906 , +\blk00000003/sig00000907 , \blk00000003/sig00000908 , \blk00000003/sig00000909 , \blk00000003/sig0000090a , \blk00000003/sig0000090b , +\blk00000003/sig0000090c , \blk00000003/sig0000090d , \blk00000003/sig0000090e , \blk00000003/sig0000090f , \blk00000003/sig00000910 , +\blk00000003/sig00000911 , \blk00000003/sig00000912 , \blk00000003/sig00000913 , \blk00000003/sig00000914 , \blk00000003/sig00000915 , +\blk00000003/sig00000916 , \blk00000003/sig00000917 , \blk00000003/sig00000918 , \blk00000003/sig00000919 , \blk00000003/sig0000091a , +\blk00000003/sig0000091b , \blk00000003/sig0000091c , \blk00000003/sig0000091d , \blk00000003/sig0000091e , \blk00000003/sig0000091f , +\blk00000003/sig00000920 , \blk00000003/sig00000921 , \blk00000003/sig00000922 , \blk00000003/sig00000923 , \blk00000003/sig00000924 , +\blk00000003/sig00000925 , \blk00000003/sig00000926 , \blk00000003/sig00000927 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000938 , \blk00000003/sig00000939 , \blk00000003/sig0000093a , +\blk00000003/sig0000093b , \blk00000003/sig0000093c , \blk00000003/sig0000093d , \blk00000003/sig0000093e , \blk00000003/sig0000093f , +\blk00000003/sig00000940 , \blk00000003/sig00000941 , \blk00000003/sig00000942 , \blk00000003/sig00000943 , \blk00000003/sig00000944 , +\blk00000003/sig00000945 , \blk00000003/sig00000946 , \blk00000003/sig00000947 }), + .PCOUT({\blk00000003/sig00000948 , \blk00000003/sig00000949 , \blk00000003/sig0000094a , \blk00000003/sig0000094b , \blk00000003/sig0000094c , +\blk00000003/sig0000094d , \blk00000003/sig0000094e , \blk00000003/sig0000094f , \blk00000003/sig00000950 , \blk00000003/sig00000951 , +\blk00000003/sig00000952 , \blk00000003/sig00000953 , \blk00000003/sig00000954 , \blk00000003/sig00000955 , \blk00000003/sig00000956 , +\blk00000003/sig00000957 , \blk00000003/sig00000958 , \blk00000003/sig00000959 , \blk00000003/sig0000095a , \blk00000003/sig0000095b , +\blk00000003/sig0000095c , \blk00000003/sig0000095d , \blk00000003/sig0000095e , \blk00000003/sig0000095f , \blk00000003/sig00000960 , +\blk00000003/sig00000961 , \blk00000003/sig00000962 , \blk00000003/sig00000963 , \blk00000003/sig00000964 , \blk00000003/sig00000965 , +\blk00000003/sig00000966 , \blk00000003/sig00000967 , \blk00000003/sig00000968 , \blk00000003/sig00000969 , \blk00000003/sig0000096a , +\blk00000003/sig0000096b , \blk00000003/sig0000096c , \blk00000003/sig0000096d , \blk00000003/sig0000096e , \blk00000003/sig0000096f , +\blk00000003/sig00000970 , \blk00000003/sig00000971 , \blk00000003/sig00000972 , \blk00000003/sig00000973 , \blk00000003/sig00000974 , +\blk00000003/sig00000975 , \blk00000003/sig00000976 , \blk00000003/sig00000977 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008d8 , \blk00000003/sig000008d9 , \blk00000003/sig000008da , +\blk00000003/sig000008db , \blk00000003/sig000008dc , \blk00000003/sig000008dd , \blk00000003/sig000008de , \blk00000003/sig000008df , +\blk00000003/sig000008e0 , \blk00000003/sig000008e1 , \blk00000003/sig000008e2 , \blk00000003/sig000008e3 , \blk00000003/sig000008e4 , +\blk00000003/sig000008e5 , \blk00000003/sig000008e6 , \blk00000003/sig000008e7 }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , 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\blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad }), + .C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED , 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+\NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , 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.A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008b8 , \blk00000003/sig000008b9 , \blk00000003/sig000008ba , +\blk00000003/sig000008bb , \blk00000003/sig000008bc , \blk00000003/sig000008bd , \blk00000003/sig000008be , \blk00000003/sig000008bf , +\blk00000003/sig000008c0 , \blk00000003/sig000008c1 , \blk00000003/sig000008c2 , \blk00000003/sig000008c3 , \blk00000003/sig000008c4 , +\blk00000003/sig000008c5 , \blk00000003/sig000008c6 , \blk00000003/sig000008c7 }), + .BCOUT({\NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .C({\NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED , 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\NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000008c8 , \blk00000003/sig000008c9 , \blk00000003/sig000008ca , +\blk00000003/sig000008cb , \blk00000003/sig000008cc , \blk00000003/sig000008cd , \blk00000003/sig000008ce , \blk00000003/sig000008cf , +\blk00000003/sig000008d0 , \blk00000003/sig000008d1 , \blk00000003/sig000008d2 , \blk00000003/sig000008d3 , \blk00000003/sig000008d4 , +\blk00000003/sig000008d5 , \blk00000003/sig000008d6 , \blk00000003/sig000008d7 }), + .PCOUT({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , 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\NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010a ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000868 , \blk00000003/sig00000869 , \blk00000003/sig0000086a , +\blk00000003/sig0000086b , \blk00000003/sig0000086c , \blk00000003/sig0000086d , \blk00000003/sig0000086e , \blk00000003/sig0000086f , +\blk00000003/sig00000870 , \blk00000003/sig00000871 , \blk00000003/sig00000872 , \blk00000003/sig00000873 , \blk00000003/sig00000874 , +\blk00000003/sig00000875 , \blk00000003/sig00000876 , \blk00000003/sig00000877 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000878 , \blk00000003/sig00000879 , \blk00000003/sig0000087a , +\blk00000003/sig0000087b , \blk00000003/sig0000087c , \blk00000003/sig0000087d , \blk00000003/sig0000087e , \blk00000003/sig0000087f , +\blk00000003/sig00000880 , \blk00000003/sig00000881 , \blk00000003/sig00000882 , \blk00000003/sig00000883 , \blk00000003/sig00000884 , +\blk00000003/sig00000885 , \blk00000003/sig00000886 , \blk00000003/sig00000887 }), + .PCOUT({\blk00000003/sig00000888 , \blk00000003/sig00000889 , \blk00000003/sig0000088a , \blk00000003/sig0000088b , \blk00000003/sig0000088c , +\blk00000003/sig0000088d , \blk00000003/sig0000088e , \blk00000003/sig0000088f , \blk00000003/sig00000890 , \blk00000003/sig00000891 , +\blk00000003/sig00000892 , \blk00000003/sig00000893 , \blk00000003/sig00000894 , \blk00000003/sig00000895 , \blk00000003/sig00000896 , +\blk00000003/sig00000897 , \blk00000003/sig00000898 , \blk00000003/sig00000899 , \blk00000003/sig0000089a , \blk00000003/sig0000089b , +\blk00000003/sig0000089c , \blk00000003/sig0000089d , \blk00000003/sig0000089e , \blk00000003/sig0000089f , \blk00000003/sig000008a0 , +\blk00000003/sig000008a1 , \blk00000003/sig000008a2 , \blk00000003/sig000008a3 , \blk00000003/sig000008a4 , \blk00000003/sig000008a5 , +\blk00000003/sig000008a6 , \blk00000003/sig000008a7 , \blk00000003/sig000008a8 , \blk00000003/sig000008a9 , \blk00000003/sig000008aa , +\blk00000003/sig000008ab , \blk00000003/sig000008ac , \blk00000003/sig000008ad , \blk00000003/sig000008ae , \blk00000003/sig000008af , +\blk00000003/sig000008b0 , \blk00000003/sig000008b1 , \blk00000003/sig000008b2 , \blk00000003/sig000008b3 , \blk00000003/sig000008b4 , +\blk00000003/sig000008b5 , \blk00000003/sig000008b6 , \blk00000003/sig000008b7 }), + .A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000109 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000109_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000109_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000818 , \blk00000003/sig00000819 , \blk00000003/sig0000081a , +\blk00000003/sig0000081b , \blk00000003/sig0000081c , \blk00000003/sig0000081d , \blk00000003/sig0000081e , \blk00000003/sig0000081f , +\blk00000003/sig00000820 , \blk00000003/sig00000821 , \blk00000003/sig00000822 , \blk00000003/sig00000823 , \blk00000003/sig00000824 , +\blk00000003/sig00000825 , \blk00000003/sig00000826 , \blk00000003/sig00000827 }), + .BCOUT({\NLW_blk00000003/blk00000109_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000109_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000109_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000007e8 , \blk00000003/sig000007e9 , \blk00000003/sig000007ea , \blk00000003/sig000007eb , \blk00000003/sig000007ec , +\blk00000003/sig000007ed , \blk00000003/sig000007ee , \blk00000003/sig000007ef , \blk00000003/sig000007f0 , \blk00000003/sig000007f1 , +\blk00000003/sig000007f2 , \blk00000003/sig000007f3 , \blk00000003/sig000007f4 , \blk00000003/sig000007f5 , \blk00000003/sig000007f6 , +\blk00000003/sig000007f7 , \blk00000003/sig000007f8 , \blk00000003/sig000007f9 , \blk00000003/sig000007fa , \blk00000003/sig000007fb , +\blk00000003/sig000007fc , \blk00000003/sig000007fd , \blk00000003/sig000007fe , \blk00000003/sig000007ff , \blk00000003/sig00000800 , +\blk00000003/sig00000801 , \blk00000003/sig00000802 , \blk00000003/sig00000803 , \blk00000003/sig00000804 , \blk00000003/sig00000805 , +\blk00000003/sig00000806 , \blk00000003/sig00000807 , \blk00000003/sig00000808 , \blk00000003/sig00000809 , \blk00000003/sig0000080a , +\blk00000003/sig0000080b , \blk00000003/sig0000080c , \blk00000003/sig0000080d , \blk00000003/sig0000080e , \blk00000003/sig0000080f , +\blk00000003/sig00000810 , \blk00000003/sig00000811 , \blk00000003/sig00000812 , \blk00000003/sig00000813 , \blk00000003/sig00000814 , +\blk00000003/sig00000815 , \blk00000003/sig00000816 , \blk00000003/sig00000817 }), + .C({\NLW_blk00000003/blk00000109_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000109_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000828 , \blk00000003/sig00000829 , \blk00000003/sig0000082a , +\blk00000003/sig0000082b , \blk00000003/sig0000082c , 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\blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk00000109_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000109_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000109_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000108 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000108_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000108_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007c8 , \blk00000003/sig000007c9 , \blk00000003/sig000007ca , +\blk00000003/sig000007cb , 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+\NLW_blk00000003/blk00000108_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000108_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000108_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , 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\NLW_blk00000003/blk00000108_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_C<22>_UNCONNECTED , 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\blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000108_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000108_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000108_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000107 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000107_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000107_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000778 , \blk00000003/sig00000779 , \blk00000003/sig0000077a , +\blk00000003/sig0000077b , \blk00000003/sig0000077c , \blk00000003/sig0000077d , \blk00000003/sig0000077e , \blk00000003/sig0000077f , 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+\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000788 , \blk00000003/sig00000789 , \blk00000003/sig0000078a , \blk00000003/sig0000078b , \blk00000003/sig0000078c , +\blk00000003/sig0000078d , \blk00000003/sig0000078e , \blk00000003/sig0000078f , \blk00000003/sig00000790 , \blk00000003/sig00000791 , +\blk00000003/sig00000792 , \blk00000003/sig00000793 , \blk00000003/sig00000794 , \blk00000003/sig00000795 , \blk00000003/sig00000796 , +\blk00000003/sig00000797 , \blk00000003/sig00000798 , \blk00000003/sig00000799 , \blk00000003/sig0000079a , \blk00000003/sig0000079b , +\blk00000003/sig0000079c , \blk00000003/sig0000079d , \blk00000003/sig0000079e , \blk00000003/sig0000079f , \blk00000003/sig000007a0 , +\blk00000003/sig000007a1 , \blk00000003/sig000007a2 , \blk00000003/sig000007a3 , \blk00000003/sig000007a4 , \blk00000003/sig000007a5 , +\blk00000003/sig000007a6 , \blk00000003/sig000007a7 , \blk00000003/sig000007a8 , \blk00000003/sig000007a9 , \blk00000003/sig000007aa , +\blk00000003/sig000007ab , \blk00000003/sig000007ac , \blk00000003/sig000007ad , \blk00000003/sig000007ae , \blk00000003/sig000007af , +\blk00000003/sig000007b0 , \blk00000003/sig000007b1 , \blk00000003/sig000007b2 , \blk00000003/sig000007b3 , \blk00000003/sig000007b4 , +\blk00000003/sig000007b5 , \blk00000003/sig000007b6 , \blk00000003/sig000007b7 }), + .C({\NLW_blk00000003/blk00000107_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000007b8 , \blk00000003/sig000007b9 , \blk00000003/sig000007ba , +\blk00000003/sig000007bb , \blk00000003/sig000007bc , \blk00000003/sig000007bd , \blk00000003/sig000007be , \blk00000003/sig000007bf , +\blk00000003/sig000007c0 , \blk00000003/sig000007c1 , \blk00000003/sig000007c2 , \blk00000003/sig000007c3 , \blk00000003/sig000007c4 , +\blk00000003/sig000007c5 , \blk00000003/sig000007c6 , \blk00000003/sig000007c7 }), + .PCOUT({\blk00000003/sig000001d2 , \blk00000003/sig000001d3 , \blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , +\blk00000003/sig000001d7 , \blk00000003/sig000001d8 , \blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , +\blk00000003/sig000001dc , \blk00000003/sig000001dd , \blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , +\blk00000003/sig000001e1 , \blk00000003/sig000001e2 , \blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , +\blk00000003/sig000001e6 , \blk00000003/sig000001e7 , \blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , +\blk00000003/sig000001eb , \blk00000003/sig000001ec , \blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , +\blk00000003/sig000001f0 , \blk00000003/sig000001f1 , \blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , +\blk00000003/sig000001f5 , \blk00000003/sig000001f6 , \blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000107_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000106 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000106_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000106_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000728 , \blk00000003/sig00000729 , \blk00000003/sig0000072a , +\blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , \blk00000003/sig0000072e , \blk00000003/sig0000072f , +\blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 , \blk00000003/sig00000733 , \blk00000003/sig00000734 , +\blk00000003/sig00000735 , \blk00000003/sig00000736 , \blk00000003/sig00000737 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000738 , \blk00000003/sig00000739 , \blk00000003/sig0000073a , \blk00000003/sig0000073b , \blk00000003/sig0000073c , +\blk00000003/sig0000073d , \blk00000003/sig0000073e , \blk00000003/sig0000073f , \blk00000003/sig00000740 , \blk00000003/sig00000741 , +\blk00000003/sig00000742 , \blk00000003/sig00000743 , \blk00000003/sig00000744 , \blk00000003/sig00000745 , \blk00000003/sig00000746 , +\blk00000003/sig00000747 , \blk00000003/sig00000748 , \blk00000003/sig00000749 , \blk00000003/sig0000074a , \blk00000003/sig0000074b , +\blk00000003/sig0000074c , \blk00000003/sig0000074d , \blk00000003/sig0000074e , \blk00000003/sig0000074f , \blk00000003/sig00000750 , +\blk00000003/sig00000751 , \blk00000003/sig00000752 , \blk00000003/sig00000753 , \blk00000003/sig00000754 , \blk00000003/sig00000755 , +\blk00000003/sig00000756 , \blk00000003/sig00000757 , \blk00000003/sig00000758 , \blk00000003/sig00000759 , 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\NLW_blk00000003/blk00000106_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000768 , \blk00000003/sig00000769 , \blk00000003/sig0000076a , +\blk00000003/sig0000076b , \blk00000003/sig0000076c , \blk00000003/sig0000076d , \blk00000003/sig0000076e , \blk00000003/sig0000076f , +\blk00000003/sig00000770 , \blk00000003/sig00000771 , \blk00000003/sig00000772 , \blk00000003/sig00000773 , \blk00000003/sig00000774 , +\blk00000003/sig00000775 , \blk00000003/sig00000776 , \blk00000003/sig00000777 }), + .PCOUT({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk00000106_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000105 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000105_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000105_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , \blk00000003/sig00000718 , +\blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a , \blk00000003/sig0000071b , \blk00000003/sig0000071c , +\blk00000003/sig0000071d , \blk00000003/sig0000071e , \blk00000003/sig0000071f }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , \blk00000003/sig000006f6 , +\blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , \blk00000003/sig000006fb , +\blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , \blk00000003/sig00000700 , +\blk00000003/sig00000701 , \blk00000003/sig00000702 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , +\blk00000003/sig00000706 , \blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , +\blk00000003/sig0000070b , \blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , +\blk00000003/sig00000710 , \blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , +\blk00000003/sig00000715 , \blk00000003/sig00000716 , \blk00000003/sig00000717 }), + .C({\NLW_blk00000003/blk00000105_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , \blk00000003/sig00000720 , +\blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , \blk00000003/sig00000724 , +\blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 }), + .PCOUT({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .A({\blk00000003/sig00000646 , \blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , +\blk00000003/sig0000064b , \blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , +\blk00000003/sig00000650 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , +\blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 }), + .M({\NLW_blk00000003/blk00000105_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000104 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000104_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000104_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , \blk00000003/sig000006d8 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , 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\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , +\blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 }), + .C({\NLW_blk00000003/blk00000104_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , \blk00000003/sig000006e0 , +\blk00000003/sig000006e0 , \blk00000003/sig000006e1 , \blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , +\blk00000003/sig000006e5 , \blk00000003/sig000006e6 , \blk00000003/sig000006e7 }), + .PCOUT({\blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , \blk00000003/sig000006ec , +\blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , \blk00000003/sig000006f1 , +\blk00000003/sig000006f2 , \blk00000003/sig000006f3 , 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.A({\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , +\blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 }), + .M({\NLW_blk00000003/blk00000104_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000103 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000103_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000103_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , \blk00000003/sig00000698 , +\blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , \blk00000003/sig0000069b , \blk00000003/sig0000069c , +\blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f }), + .BCOUT({\NLW_blk00000003/blk00000103_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000103_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000103_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , 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\blk00000003/sig00000697 }), + .C({\NLW_blk00000003/blk00000103_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000103_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000103_C<9>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , \blk00000003/sig000006a0 , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , +\blk00000003/sig000006a5 , \blk00000003/sig000006a6 , \blk00000003/sig000006a7 }), + .PCOUT({\blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , \blk00000003/sig000006ac , +\blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , \blk00000003/sig000006b1 , +\blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , \blk00000003/sig000006b6 , +\blk00000003/sig000006b7 , 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.RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , \blk00000003/sig00000658 , +\blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , +\blk00000003/sig0000065d , \blk00000003/sig0000065e , \blk00000003/sig0000065f }), + .BCOUT({\NLW_blk00000003/blk00000102_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000102_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000102_BCOUT<11>_UNCONNECTED , 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\NLW_blk00000003/blk00000102_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , \blk00000003/sig00000660 , +\blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , \blk00000003/sig00000664 , +\blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 }), + .PCOUT({\blk00000003/sig00000668 , \blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , +\blk00000003/sig0000066d , \blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , +\blk00000003/sig00000672 , \blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , +\blk00000003/sig00000677 , \blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , +\blk00000003/sig0000067c , \blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , +\blk00000003/sig00000681 , \blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , +\blk00000003/sig00000686 , \blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , +\blk00000003/sig0000068b , \blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , +\blk00000003/sig00000690 , \blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , +\blk00000003/sig00000695 , \blk00000003/sig00000696 , \blk00000003/sig00000697 }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk00000102_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000102_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000102_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000101 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000101_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000101_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , \blk00000003/sig00000636 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d }), + .BCOUT({\NLW_blk00000003/blk00000101_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000101_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000101_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005f4 , \blk00000003/sig000005f5 , \blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , +\blk00000003/sig000005f9 , \blk00000003/sig000005fa , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , +\blk00000003/sig000005fe , \blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , +\blk00000003/sig00000603 , \blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , +\blk00000003/sig00000608 , \blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , +\blk00000003/sig0000060d , \blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , +\blk00000003/sig00000612 , \blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , +\blk00000003/sig00000617 , \blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , +\blk00000003/sig0000061c , \blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , +\blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 }), + .C({\NLW_blk00000003/blk00000101_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000101_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000101_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000101_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , \blk00000003/sig0000063e , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 , +\blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 }), + .PCOUT({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , 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\blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .C({\NLW_blk00000003/blk000000ff_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000ff_P<47>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_P<7>_UNCONNECTED , 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\blk00000003/sig000005a0 , \blk00000003/sig000005a1 }), + .PCOUT({\blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , \blk00000003/sig000005a6 , +\blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , \blk00000003/sig000005ab , +\blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , \blk00000003/sig000005b0 , +\blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , +\blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , +\blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , +\blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , +\blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , +\blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 }), + .A({\blk00000003/sig000005d2 , \blk00000003/sig000005d3 , \blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , +\blk00000003/sig000005d7 , \blk00000003/sig000005d8 , \blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , +\blk00000003/sig000005dc , \blk00000003/sig000005dd , \blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , +\blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 }), + .M({\NLW_blk00000003/blk000000ff_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<34>_UNCONNECTED , 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\NLW_blk00000003/blk000000ff_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000ff_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ff_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fe ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fe_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fe_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , \blk00000003/sig00000540 , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , 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\NLW_blk00000003/blk000000fe_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , +\blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , +\blk00000003/sig00000396 , \blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , +\blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , 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+\NLW_blk00000003/blk000000fe_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fe_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , \blk00000003/sig00000548 , +\blk00000003/sig00000548 , \blk00000003/sig00000549 , \blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , +\blk00000003/sig0000054d , \blk00000003/sig0000054e , \blk00000003/sig0000054f }), + .PCOUT({\blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , \blk00000003/sig00000554 , +\blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 , \blk00000003/sig00000559 , +\blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , \blk00000003/sig0000055d , \blk00000003/sig0000055e , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , \blk00000003/sig00000567 , \blk00000003/sig00000568 , +\blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , \blk00000003/sig0000056c , \blk00000003/sig0000056d , +\blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , +\blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , +\blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , +\blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f }), + .A({\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 }), + .M({\NLW_blk00000003/blk000000fe_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fe_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fe_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fd ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fd_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fd_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , \blk00000003/sig00000500 , +\blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , \blk00000003/sig00000504 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 }), + .BCOUT({\NLW_blk00000003/blk000000fd_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fd_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000508 , \blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , +\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , +\blk00000003/sig00000521 , \blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , +\blk00000003/sig00000526 , \blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , +\blk00000003/sig0000052b , \blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , +\blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , +\blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 }), + .C({\NLW_blk00000003/blk000000fd_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_C<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , \blk00000003/sig00000538 , +\blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , +\blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f }), + .PCOUT({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fd_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<29>_UNCONNECTED , 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\NLW_blk00000003/blk000000fd_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fd_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fd_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fc ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fc_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fc_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , \blk00000003/sig000004ae , +\blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , +\blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , 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\blk00000003/sig000004e1 , \blk00000003/sig000004e2 , +\blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 }), + .C({\NLW_blk00000003/blk000000fc_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , 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\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , \blk00000003/sig000004e6 , +\blk00000003/sig000004e6 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed }), + .PCOUT({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , 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.A({\blk00000003/sig000004ee , \blk00000003/sig000004ef , \blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , +\blk00000003/sig000004f3 , \blk00000003/sig000004f4 , \blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , +\blk00000003/sig000004f8 , \blk00000003/sig000004f9 , \blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , +\blk00000003/sig000004fd , \blk00000003/sig000004fe , \blk00000003/sig000004ff }), + .M({\NLW_blk00000003/blk000000fc_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<26>_UNCONNECTED , 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\NLW_blk00000003/blk000000fc_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000fb ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000fb_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000fb_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , 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\NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , +\blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , +\blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d }), + .PCOUT({\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , +\blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , +\blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , +\blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , +\blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , +\blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000fa_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f9 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f9_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f9_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , \blk00000003/sig000003ce , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f9_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , +\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .PCOUT({\blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , +\blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , +\blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec , +\blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 , \blk00000003/sig000003f6 , +\blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , \blk00000003/sig000003fa , \blk00000003/sig000003fb , +\blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , +\blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , +\blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , +\blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f9_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk000000f8 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk000000f8_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk000000f8_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , \blk00000003/sig0000037c , +\blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , +\blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk000000f8_C<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_C<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , +\blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , \blk00000003/sig00000384 , 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\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , +\blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , +\blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , +\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb }), + .A({\blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , +\blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 , +\blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , +\blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd }), + .M({\NLW_blk00000003/blk000000f8_M<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_M<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000378 ), + .Q(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig00000374 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000374 ), + .DI(\blk00000003/sig00000375 ), + .S(\blk00000003/sig00000376 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000372 ), + .Q(\blk00000003/sig00000373 ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig0000036e ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + MUXCY_D \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036e ), + .DI(\blk00000003/sig0000036f ), + .S(\blk00000003/sig00000370 ), + .O(\NLW_blk00000003/blk000000f0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000036d ), + .O(\blk00000003/sig0000036e ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000036b ), + .O(\blk00000003/sig0000036c ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000036a ), + .S(\blk00000003/sig0000036b ), + .O(\NLW_blk00000003/blk000000ed_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000369 ), + .S(\blk00000003/sig00000363 ), + .LO(\blk00000003/sig00000365 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000365 ), + .DI(\blk00000003/sig00000368 ), + .S(\blk00000003/sig00000366 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000365 ), + .LI(\blk00000003/sig00000366 ), + .O(\blk00000003/sig00000367 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000364 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig0000035c ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig0000035d ), + .LO(\blk00000003/sig0000035f ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig0000035f ), + .DI(\blk00000003/sig000002b9 ), + .S(\blk00000003/sig00000360 ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035c ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig0000035f ), + .LI(\blk00000003/sig00000360 ), + .O(\blk00000003/sig00000361 ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035c ), + .LI(\blk00000003/sig0000035d ), + .O(\blk00000003/sig0000035e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034d ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000034c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ef ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig0000035a ), + .S(\blk00000003/sig0000035b ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig00000358 ), + .S(\blk00000003/sig00000359 ), + .O(\blk00000003/sig00000355 ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000355 ), + .DI(\blk00000003/sig0000034b ), + .S(\blk00000003/sig00000356 ), + .O(\blk00000003/sig00000352 ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000352 ), + .DI(\blk00000003/sig00000353 ), + .S(\blk00000003/sig00000354 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000de_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000031e ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig000002ec ), + .S(\blk00000003/sig0000034f ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\blk00000003/sig0000034c ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000034d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000034b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029f ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig00000349 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig00000348 ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000342 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000342 ), + .DI(\blk00000003/sig00000343 ), + .S(\blk00000003/sig00000344 ), + .O(\blk00000003/sig00000340 ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig00000340 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig00000341 ), + .O(\blk00000003/sig0000033c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000033e ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig0000033f ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000033a ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033c ), + .DI(\blk00000003/sig00000313 ), + .S(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033a ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000033b ) + ); + FDE \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000324 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000333 ) + ); + XORCY \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000333 ), + .LI(\blk00000003/sig00000335 ), + .O(\blk00000003/sig00000336 ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000333 ), + .DI(\blk00000003/sig00000334 ), + .S(\blk00000003/sig00000335 ), + .O(\NLW_blk00000003/blk000000cc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000326 ), + .DI(\blk00000003/sig00000332 ), + .S(\blk00000003/sig00000327 ), + .LO(\blk00000003/sig0000032c ) + ); + MUXCY_L \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032c ), + .DI(\blk00000003/sig00000331 ), + .S(\blk00000003/sig0000032d ), + .LO(\blk00000003/sig00000329 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000329 ), + .DI(\blk00000003/sig00000330 ), + .S(\blk00000003/sig0000032a ), + .O(\NLW_blk00000003/blk000000c9_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000032f ), + .O(\blk00000003/sig00000326 ) + ); + XORCY \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig0000032c ), + .LI(\blk00000003/sig0000032d ), + .O(\blk00000003/sig0000032e ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000329 ), + .LI(\blk00000003/sig0000032a ), + .O(\blk00000003/sig0000032b ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000326 ), + .LI(\blk00000003/sig00000327 ), + .O(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/sig0000030b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030e ), + .Q(\blk00000003/sig00000312 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b5_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000305 ), + .R(coef_ld), + .Q(\blk00000003/sig00000302 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b3_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ef ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000311 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000310 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030a ) + ); + XORCY \blk00000003/blk000000ac ( + .CI(\blk00000003/sig00000307 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000308 ) + ); + MUXCY \blk00000003/blk000000ab ( + .CI(\blk00000003/sig00000307 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002fd ) + ); + MUXCY_D \blk00000003/blk000000aa ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000306 ), + .O(\blk00000003/sig00000307 ), + .LO(\NLW_blk00000003/blk000000aa_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000303 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000305 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000303 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000304 ), + .O(\blk00000003/sig00000301 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig00000301 ), + .DI(\blk00000003/sig00000302 ), + .S(coef_we), + .O(\blk00000003/sig00000303 ), + .LO(\NLW_blk00000003/blk000000a6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002ff ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a4 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a4_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000002fd ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fe ), + .O(\blk00000003/sig000002ff ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a2 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f7 ), + .LO(\NLW_blk00000003/blk000000a2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk000000a0_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000002f7 ), + .DI(\blk00000003/sig000002f8 ), + .S(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002f5 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY_D \blk00000003/blk0000009d ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002f4 ), + .S(\blk00000003/sig000002f5 ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000009d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002ed ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002f1 ), + .DI(\blk00000003/sig000002f2 ), + .S(\blk00000003/sig000002f3 ), + .O(\NLW_blk00000003/blk0000009b_O_UNCONNECTED ), + .LO(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ee ), + .DI(\blk00000003/sig000002ef ), + .S(\blk00000003/sig000002f0 ), + .O(\blk00000003/sig000002f1 ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ee ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(\blk00000003/sig000002ae ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .R(sclr), + .Q(\blk00000003/sig000002b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000002b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ad ), + .R(\blk00000003/sig000002ae ), + .Q(rdy) + ); + FDRE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(sclr), + .Q(\blk00000003/sig000002ac ) + ); + FDSE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a9 ), + .S(sclr), + .Q(\blk00000003/sig000002aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .R(sclr), + .Q(\blk00000003/sig0000029c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a5 ), + .R(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .R(sclr), + .Q(\blk00000003/sig000002a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000027_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000176 ), + .R(sclr), + .Q(\blk00000003/sig00000173 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000170 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000023_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000171 ), + .S(sclr), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk00000021 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029a ), + .LO(\NLW_blk00000003/blk00000021_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000020 ( + .CI(\blk00000003/sig0000029a ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\NLW_blk00000003/blk00000020_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000001f ( + .CI(\blk00000003/sig0000029a ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029b ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001e ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001e_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001e_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000024a , \blk00000003/sig0000024b , \blk00000003/sig0000024c , +\blk00000003/sig0000024d , \blk00000003/sig0000024e , \blk00000003/sig0000024f , \blk00000003/sig00000250 , \blk00000003/sig00000251 , +\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 }), + .BCOUT({\NLW_blk00000003/blk0000001e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000025a , \blk00000003/sig0000025b , \blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , +\blk00000003/sig0000025f , \blk00000003/sig00000260 , \blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , +\blk00000003/sig00000264 , \blk00000003/sig00000265 , \blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , +\blk00000003/sig00000269 , \blk00000003/sig0000026a , \blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , +\blk00000003/sig0000026e , \blk00000003/sig0000026f , \blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , +\blk00000003/sig00000273 , \blk00000003/sig00000274 , \blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , +\blk00000003/sig00000278 , \blk00000003/sig00000279 , \blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , +\blk00000003/sig0000027d , \blk00000003/sig0000027e , \blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 , +\blk00000003/sig00000282 , \blk00000003/sig00000283 , \blk00000003/sig00000284 , \blk00000003/sig00000285 , \blk00000003/sig00000286 , +\blk00000003/sig00000287 , \blk00000003/sig00000288 , \blk00000003/sig00000289 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_P<40>_UNCONNECTED , +\blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , +\blk00000003/sig00000157 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , +\blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , +\blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , +\blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig0000028a , +\blk00000003/sig0000028b , \blk00000003/sig0000028c , \blk00000003/sig0000028d , \blk00000003/sig0000028e , \blk00000003/sig0000028f , +\blk00000003/sig00000290 , \blk00000003/sig00000291 , \blk00000003/sig00000292 , \blk00000003/sig00000293 , \blk00000003/sig00000294 , +\blk00000003/sig00000295 , \blk00000003/sig00000296 , \blk00000003/sig00000297 , \blk00000003/sig00000298 , \blk00000003/sig00000299 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001e_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , \blk00000003/sig00000212 , +\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 }), + .BCOUT({\NLW_blk00000003/blk0000001d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000021a , \blk00000003/sig0000021b , \blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , +\blk00000003/sig0000021f , \blk00000003/sig00000220 , \blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , +\blk00000003/sig00000224 , \blk00000003/sig00000225 , \blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , +\blk00000003/sig00000229 , \blk00000003/sig0000022a , \blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , +\blk00000003/sig0000022e , \blk00000003/sig0000022f , \blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , +\blk00000003/sig00000233 , \blk00000003/sig00000234 , \blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , +\blk00000003/sig00000238 , \blk00000003/sig00000239 , \blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , +\blk00000003/sig0000023d , \blk00000003/sig0000023e , \blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 , +\blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , \blk00000003/sig00000245 , \blk00000003/sig00000246 , +\blk00000003/sig00000247 , \blk00000003/sig00000248 , \blk00000003/sig00000249 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_P<31>_UNCONNECTED , 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+\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001d_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001d_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 , +\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 }), + .BCOUT({\NLW_blk00000003/blk0000001c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001d2 , 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\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 , +\blk00000003/sig000001fa , \blk00000003/sig000001fb , \blk00000003/sig000001fc , \blk00000003/sig000001fd , \blk00000003/sig000001fe , +\blk00000003/sig000001ff , \blk00000003/sig00000200 , \blk00000003/sig00000201 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , 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\NLW_blk00000003/blk0000001c_P<40>_UNCONNECTED , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , +\blk00000003/sig000000b0 , \blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b5 , \blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , +\blk00000003/sig000000ba , \blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig00000202 , +\blk00000003/sig00000203 , \blk00000003/sig00000204 , \blk00000003/sig00000205 , \blk00000003/sig00000206 , \blk00000003/sig00000207 , +\blk00000003/sig00000208 , \blk00000003/sig00000209 , \blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , +\blk00000003/sig0000020d , \blk00000003/sig0000020e , \blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001c_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<46>_UNCONNECTED , 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+\NLW_blk00000003/blk0000001c_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001c_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000001b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000001b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000001b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , \blk00000003/sig00000178 , +\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f }), + .BCOUT({\NLW_blk00000003/blk0000001b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , +\blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , +\blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , +\blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , +\blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , +\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk0000001b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_P<31>_UNCONNECTED , +\blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , +\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000165 , \blk00000003/sig00000167 , \blk00000003/sig00000169 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk0000001b_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000001b_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 }), + .M({\NLW_blk00000003/blk0000001b_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000001b_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000001b_M<0>_UNCONNECTED }) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000177 ), + .O(\blk00000003/sig00000172 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000175 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000176 ) + ); + MUXCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000175 ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000016a ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig00000172 ), + .DI(\blk00000003/sig00000173 ), + .S(\blk00000003/sig00000174 ), + .O(\blk00000003/sig00000175 ), + .LO(\NLW_blk00000003/blk00000017_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000016 ( + .CI(\blk00000003/sig00000170 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000171 ) + ); + MUXCY_D \blk00000003/blk00000015 ( + .CI(\blk00000003/sig0000016d ), + .DI(\blk00000003/sig0000016e ), + .S(\blk00000003/sig0000016f ), + .O(\NLW_blk00000003/blk00000015_O_UNCONNECTED ), + .LO(\blk00000003/sig00000170 ) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(\blk00000003/sig0000016a ), + .DI(\blk00000003/sig0000016b ), + .S(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000013 ( + .C(clk), + .D(\blk00000003/sig00000168 ), + .Q(\blk00000003/sig00000169 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000012 ( + .C(clk), + .D(\blk00000003/sig00000166 ), + .Q(\blk00000003/sig00000167 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000011 ( + .C(clk), + .D(\blk00000003/sig00000164 ), + .Q(\blk00000003/sig00000165 ) + ); + XORCY \blk00000003/blk00000010 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000162 ), + .O(\blk00000003/sig00000163 ) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000161 ), + .S(\blk00000003/sig00000162 ), + .O(\NLW_blk00000003/blk0000000f_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig0000015c ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000160 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig0000015e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015e ), + .R(sclr), + .Q(\blk00000003/sig0000015f ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015a ), + .LO(\NLW_blk00000003/blk0000000c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig0000015b ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000158 ) + ); + MUXCY \blk00000003/blk0000000a ( + .CI(\blk00000003/sig0000015b ), + .DI(\blk00000003/sig00000049 ), + .S(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000015c ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig0000015a ), + .DI(\blk00000003/sig00000159 ), + .S(nd), + .O(\blk00000003/sig0000015b ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000158 ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000007 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , +\blk00000003/sig00000107 , \blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , +\blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , +\blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 }), + .BCOUT({\NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , +\blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 }), + .P({\NLW_blk00000003/blk00000007_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED , +\blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , +\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , +\blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , +\blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 }), + .M({\NLW_blk00000003/blk00000007_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000007_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000006 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000000ac , \blk00000003/sig000000ad , \blk00000003/sig000000ae , \blk00000003/sig000000af , \blk00000003/sig000000b0 , +\blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , \blk00000003/sig000000b4 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd }), + .BCOUT({\NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , +\blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000be , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , +\blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , +\blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , +\blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , +\blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , +\blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , +\blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc }), + .P({\NLW_blk00000003/blk00000006_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED , +\blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , +\blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , +\blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , +\blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , +\blk00000003/sig000000f1 , \blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , +\blk00000003/sig000000f6 , \blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , +\blk00000003/sig000000fb }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd}), + .D({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc }), + .PCOUT({\NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , +\blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000035/blk00000097 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000035/sig00000f29 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000096 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000096_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f27 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000095 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f26 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000094 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f28 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000093 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000092 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000091 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000090 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000008a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000089 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000088 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000087 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000086 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000085 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000084 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f15 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000083 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000082 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000081 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f12 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000080 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f11 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f10 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000007a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000079 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000078 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f09 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000077 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f08 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000076 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f0a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000075 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f06 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000074 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f05 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000073 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f07 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000072 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f03 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000071 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f02 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000070 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f04 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006f ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f00 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006e ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000eff ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006d ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000f01 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006c ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006b ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk0000006a ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efe ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000069 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000068 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000ef9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000035/blk00000067 ( + .A0(\blk00000003/sig000002ba ), + .A1(\blk00000003/sig000002b9 ), + .A2(\blk00000003/sig000002b8 ), + .A3(\blk00000003/blk00000035/sig00000ef8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002aa ), + .DPRA1(\blk00000003/sig000002ac ), + .DPRA2(\blk00000003/sig000002b4 ), + .DPRA3(\blk00000003/blk00000035/sig00000ef8 ), + .WCLK(clk), + .WE(\blk00000003/blk00000035/sig00000f29 ), + .SPO(\NLW_blk00000003/blk00000035/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000035/sig00000efb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000066 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f28 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f27 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f26 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f25 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f24 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f23 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f22 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f21 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f20 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1f ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1e ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1d ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1c ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1b ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f1a ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f19 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f18 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f17 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f16 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f15 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f14 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f13 ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f12 ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f11 ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f10 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0f ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0e ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0d ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0c ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0b ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f0a ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f09 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f08 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f07 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f06 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f05 ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f04 ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f03 ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f02 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f01 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000f00 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000eff ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efe ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efd ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efc ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efb ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000efa ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000035/sig00000ef9 ), + .Q(\blk00000003/sig000002ea ) + ); + GND \blk00000003/blk00000035/blk00000036 ( + .G(\blk00000003/blk00000035/sig00000ef8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000013d/blk0000015f ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk0000013d/sig00000f5f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/blk0000013d/sig00000f5e ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/blk0000013d/sig00000f5d ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/blk0000013d/sig00000f5c ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/blk0000013d/sig00000f5b ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000015a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/blk0000013d/sig00000f5a ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000015a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000159 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/blk0000013d/sig00000f59 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000159_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000158 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/blk0000013d/sig00000f58 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000158_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000157 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/blk0000013d/sig00000f57 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000157_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000156 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/blk0000013d/sig00000f56 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000156_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000155 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/blk0000013d/sig00000f55 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000155_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000154 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/blk0000013d/sig00000f54 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000154_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000153 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/blk0000013d/sig00000f53 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000153_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000152 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/blk0000013d/sig00000f52 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000152_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000151 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/blk0000013d/sig00000f51 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk00000150 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/blk0000013d/sig00000f50 ), + .Q15(\NLW_blk00000003/blk0000013d/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000013d/blk0000014f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk0000013d/sig00000f4e ), + .A2(\blk00000003/blk0000013d/sig00000f4e ), + .A3(\blk00000003/blk0000013d/sig00000f4e ), + .CE(\blk00000003/blk0000013d/sig00000f5f ), + .CLK(clk), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/blk0000013d/sig00000f4f ), + .Q15(\NLW_blk00000003/blk0000013d/blk0000014f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5e ), + .Q(\blk00000003/sig00000768 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5d ), + .Q(\blk00000003/sig00000769 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5c ), + .Q(\blk00000003/sig0000076a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5b ), + .Q(\blk00000003/sig0000076b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000014a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f5a ), + .Q(\blk00000003/sig0000076c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000149 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f59 ), + .Q(\blk00000003/sig0000076d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000148 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f58 ), + .Q(\blk00000003/sig0000076e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000147 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f57 ), + .Q(\blk00000003/sig0000076f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000146 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f56 ), + .Q(\blk00000003/sig00000770 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000145 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f55 ), + .Q(\blk00000003/sig00000771 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000144 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f54 ), + .Q(\blk00000003/sig00000772 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000143 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f53 ), + .Q(\blk00000003/sig00000773 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000142 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f52 ), + .Q(\blk00000003/sig00000774 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f51 ), + .Q(\blk00000003/sig00000775 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f50 ), + .Q(\blk00000003/sig00000776 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000013d/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000013d/sig00000f4f ), + .Q(\blk00000003/sig00000777 ) + ); + GND \blk00000003/blk0000013d/blk0000013e ( + .G(\blk00000003/blk0000013d/sig00000f4e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000160/blk00000182 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000160/sig00000f95 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000181 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/blk00000160/sig00000f94 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000180 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/blk00000160/sig00000f93 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/blk00000160/sig00000f92 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/blk00000160/sig00000f91 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/blk00000160/sig00000f90 ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/blk00000160/sig00000f8f ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017b ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/blk00000160/sig00000f8e ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk0000017a ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/blk00000160/sig00000f8d ), + .Q15(\NLW_blk00000003/blk00000160/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000179 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/blk00000160/sig00000f8c ), + .Q15(\NLW_blk00000003/blk00000160/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000178 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/blk00000160/sig00000f8b ), + .Q15(\NLW_blk00000003/blk00000160/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000177 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/blk00000160/sig00000f8a ), + .Q15(\NLW_blk00000003/blk00000160/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000176 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/blk00000160/sig00000f89 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000175 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/blk00000160/sig00000f88 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000174 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/blk00000160/sig00000f87 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000173 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/blk00000160/sig00000f86 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000160/blk00000172 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000160/sig00000f84 ), + .A2(\blk00000003/blk00000160/sig00000f84 ), + .A3(\blk00000003/blk00000160/sig00000f84 ), + .CE(\blk00000003/blk00000160/sig00000f95 ), + .CLK(clk), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/blk00000160/sig00000f85 ), + .Q15(\NLW_blk00000003/blk00000160/blk00000172_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000171 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f94 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000170 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f93 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f92 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f91 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f90 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8f ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8e ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8d ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8c ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8b ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f8a ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f89 ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f88 ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f87 ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f86 ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000160/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000160/sig00000f85 ), + .Q(\blk00000003/sig00000737 ) + ); + GND \blk00000003/blk00000160/blk00000161 ( + .G(\blk00000003/blk00000160/sig00000f84 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000183/blk000001a5 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk00000183/sig00000fcb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/blk00000183/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/blk00000183/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a2 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/blk00000183/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a1 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/blk00000183/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk000001a0 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/blk00000183/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000183/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019f ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/blk00000183/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019e ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/blk00000183/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019d ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/blk00000183/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019c ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/blk00000183/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019b ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/blk00000183/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk0000019a ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/blk00000183/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000183/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000199 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/blk00000183/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000183/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000198 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/blk00000183/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000183/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000197 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/blk00000183/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000183/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000196 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/blk00000183/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000183/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000183/blk00000195 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk00000183/sig00000fba ), + .A2(\blk00000003/blk00000183/sig00000fba ), + .A3(\blk00000003/blk00000183/sig00000fba ), + .CE(\blk00000003/blk00000183/sig00000fcb ), + .CLK(clk), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/blk00000183/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000183/blk00000195_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fca ), + .Q(\blk00000003/sig000007b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc9 ), + .Q(\blk00000003/sig000007b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc8 ), + .Q(\blk00000003/sig000007ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc7 ), + .Q(\blk00000003/sig000007bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc6 ), + .Q(\blk00000003/sig000007bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc5 ), + .Q(\blk00000003/sig000007bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc4 ), + .Q(\blk00000003/sig000007be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc3 ), + .Q(\blk00000003/sig000007bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc2 ), + .Q(\blk00000003/sig000007c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc1 ), + .Q(\blk00000003/sig000007c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fc0 ), + .Q(\blk00000003/sig000007c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbf ), + .Q(\blk00000003/sig000007c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbe ), + .Q(\blk00000003/sig000007c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbd ), + .Q(\blk00000003/sig000007c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbc ), + .Q(\blk00000003/sig000007c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000183/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000183/sig00000fbb ), + .Q(\blk00000003/sig000007c7 ) + ); + GND \blk00000003/blk00000183/blk00000184 ( + .G(\blk00000003/blk00000183/sig00000fba ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001a6/blk000001c8 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000001a6/sig00001001 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/blk000001a6/sig00001000 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/blk000001a6/sig00000fff ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c5 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/blk000001a6/sig00000ffe ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c4 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/blk000001a6/sig00000ffd ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c3 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/blk000001a6/sig00000ffc ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c2 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/blk000001a6/sig00000ffb ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c1 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/blk000001a6/sig00000ffa ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001c0 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/blk000001a6/sig00000ff9 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001c0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bf ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/blk000001a6/sig00000ff8 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001be ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/blk000001a6/sig00000ff7 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bd ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/blk000001a6/sig00000ff6 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bc ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/blk000001a6/sig00000ff5 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001bb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/blk000001a6/sig00000ff4 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001ba ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/blk000001a6/sig00000ff3 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/blk000001a6/sig00000ff2 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a6/blk000001b8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000001a6/sig00000ff0 ), + .A2(\blk00000003/blk000001a6/sig00000ff0 ), + .A3(\blk00000003/blk000001a6/sig00000ff0 ), + .CE(\blk00000003/blk000001a6/sig00001001 ), + .CLK(clk), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/blk000001a6/sig00000ff1 ), + .Q15(\NLW_blk00000003/blk000001a6/blk000001b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00001000 ), + .Q(\blk00000003/sig00000778 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000fff ), + .Q(\blk00000003/sig00000779 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffe ), + .Q(\blk00000003/sig0000077a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffd ), + .Q(\blk00000003/sig0000077b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffc ), + .Q(\blk00000003/sig0000077c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffb ), + .Q(\blk00000003/sig0000077d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ffa ), + .Q(\blk00000003/sig0000077e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff9 ), + .Q(\blk00000003/sig0000077f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff8 ), + .Q(\blk00000003/sig00000780 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff7 ), + .Q(\blk00000003/sig00000781 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff6 ), + .Q(\blk00000003/sig00000782 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff5 ), + .Q(\blk00000003/sig00000783 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff4 ), + .Q(\blk00000003/sig00000784 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff3 ), + .Q(\blk00000003/sig00000785 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff2 ), + .Q(\blk00000003/sig00000786 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a6/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001a6/sig00000ff1 ), + .Q(\blk00000003/sig00000787 ) + ); + GND \blk00000003/blk000001a6/blk000001a7 ( + .G(\blk00000003/blk000001a6/sig00000ff0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001c9/blk000001eb ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk000001c9/sig00001037 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001ea ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk000001c9/sig00001036 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e9 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk000001c9/sig00001035 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e8 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk000001c9/sig00001034 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e7 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk000001c9/sig00001033 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e6 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk000001c9/sig00001032 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e5 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk000001c9/sig00001031 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e4 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk000001c9/sig00001030 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e3 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk000001c9/sig0000102f ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e2 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk000001c9/sig0000102e ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e1 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk000001c9/sig0000102d ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001e0 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk000001c9/sig0000102c ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001df ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk000001c9/sig0000102b ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001de ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk000001c9/sig0000102a ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dd ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk000001c9/sig00001029 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001dc ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk000001c9/sig00001028 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9/blk000001db ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk000001c9/sig00001026 ), + .A2(\blk00000003/blk000001c9/sig00001026 ), + .A3(\blk00000003/blk000001c9/sig00001026 ), + .CE(\blk00000003/blk000001c9/sig00001037 ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk000001c9/sig00001027 ), + .Q15(\NLW_blk00000003/blk000001c9/blk000001db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001036 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001035 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001034 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001033 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001032 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001031 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001030 ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102f ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102e ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102d ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102c ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102b ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig0000102a ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001029 ), + .Q(\blk00000003/sig000008d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001028 ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001c9/sig00001027 ), + .Q(\blk00000003/sig000008d7 ) + ); + GND \blk00000003/blk000001c9/blk000001ca ( + .G(\blk00000003/blk000001c9/sig00001026 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000020e ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk000001ec/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/blk000001ec/sig0000106c ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/blk000001ec/sig0000106b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/blk000001ec/sig0000106a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/blk000001ec/sig00001069 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/blk000001ec/sig00001068 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/blk000001ec/sig00001067 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/blk000001ec/sig00001066 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/blk000001ec/sig00001065 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000205 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/blk000001ec/sig00001064 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000204 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/blk000001ec/sig00001063 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000203 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/blk000001ec/sig00001062 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000202 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/blk000001ec/sig00001061 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000201 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/blk000001ec/sig00001060 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000200 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/blk000001ec/sig0000105f ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001ff ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/blk000001ec/sig0000105e ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk000001fe ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk000001ec/sig0000105c ), + .A2(\blk00000003/blk000001ec/sig0000105c ), + .A3(\blk00000003/blk000001ec/sig0000105c ), + .CE(\blk00000003/blk000001ec/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/blk000001ec/sig0000105d ), + .Q15(\NLW_blk00000003/blk000001ec/blk000001fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106c ), + .Q(\blk00000003/sig000008b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106b ), + .Q(\blk00000003/sig000008b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000106a ), + .Q(\blk00000003/sig000008ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001069 ), + .Q(\blk00000003/sig000008bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001068 ), + .Q(\blk00000003/sig000008bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001067 ), + .Q(\blk00000003/sig000008bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001066 ), + .Q(\blk00000003/sig000008be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001065 ), + .Q(\blk00000003/sig000008bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001064 ), + .Q(\blk00000003/sig000008c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001063 ), + .Q(\blk00000003/sig000008c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001062 ), + .Q(\blk00000003/sig000008c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001061 ), + .Q(\blk00000003/sig000008c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00001060 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105f ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105e ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig0000105d ), + .Q(\blk00000003/sig000008c7 ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig0000105c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000020f/blk00000231 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000020f/sig000010a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000230 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000988 ), + .Q(\blk00000003/blk0000020f/sig000010a2 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000230_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000989 ), + .Q(\blk00000003/blk0000020f/sig000010a1 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022e ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098a ), + .Q(\blk00000003/blk0000020f/sig000010a0 ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022d ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098b ), + .Q(\blk00000003/blk0000020f/sig0000109f ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098c ), + .Q(\blk00000003/blk0000020f/sig0000109e ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098d ), + .Q(\blk00000003/blk0000020f/sig0000109d ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk0000022a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098e ), + .Q(\blk00000003/blk0000020f/sig0000109c ), + .Q15(\NLW_blk00000003/blk0000020f/blk0000022a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000229 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig0000098f ), + .Q(\blk00000003/blk0000020f/sig0000109b ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000229_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000228 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000990 ), + .Q(\blk00000003/blk0000020f/sig0000109a ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000228_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000227 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000991 ), + .Q(\blk00000003/blk0000020f/sig00001099 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000227_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000226 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000992 ), + .Q(\blk00000003/blk0000020f/sig00001098 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000226_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000225 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000993 ), + .Q(\blk00000003/blk0000020f/sig00001097 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000225_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000224 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000994 ), + .Q(\blk00000003/blk0000020f/sig00001096 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000224_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000223 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000995 ), + .Q(\blk00000003/blk0000020f/sig00001095 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000222 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000996 ), + .Q(\blk00000003/blk0000020f/sig00001094 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000020f/blk00000221 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000020f/sig00001092 ), + .A2(\blk00000003/blk0000020f/sig00001092 ), + .A3(\blk00000003/blk0000020f/sig00001092 ), + .CE(\blk00000003/blk0000020f/sig000010a3 ), + .CLK(clk), + .D(\blk00000003/sig00000997 ), + .Q(\blk00000003/blk0000020f/sig00001093 ), + .Q15(\NLW_blk00000003/blk0000020f/blk00000221_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a2 ), + .Q(\blk00000003/sig000009d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a1 ), + .Q(\blk00000003/sig000009d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig000010a0 ), + .Q(\blk00000003/sig000009da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109f ), + .Q(\blk00000003/sig000009db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109e ), + .Q(\blk00000003/sig000009dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109d ), + .Q(\blk00000003/sig000009dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109c ), + .Q(\blk00000003/sig000009de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109b ), + .Q(\blk00000003/sig000009df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig0000109a ), + .Q(\blk00000003/sig000009e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000217 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001099 ), + .Q(\blk00000003/sig000009e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000216 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001098 ), + .Q(\blk00000003/sig000009e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000215 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001097 ), + .Q(\blk00000003/sig000009e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000214 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001096 ), + .Q(\blk00000003/sig000009e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001095 ), + .Q(\blk00000003/sig000009e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001094 ), + .Q(\blk00000003/sig000009e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000020f/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000020f/sig00001093 ), + .Q(\blk00000003/sig000009e7 ) + ); + GND \blk00000003/blk0000020f/blk00000210 ( + .G(\blk00000003/blk0000020f/sig00001092 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000232/blk00000254 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000232/sig000010d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000253 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/blk00000232/sig000010d8 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000253_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000252 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/blk00000232/sig000010d7 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000252_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000251 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/blk00000232/sig000010d6 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000251_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000250 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/blk00000232/sig000010d5 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/blk00000232/sig000010d4 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/blk00000232/sig000010d3 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/blk00000232/sig000010d2 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/blk00000232/sig000010d1 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/blk00000232/sig000010d0 ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk0000024a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/blk00000232/sig000010cf ), + .Q15(\NLW_blk00000003/blk00000232/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000249 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/blk00000232/sig000010ce ), + .Q15(\NLW_blk00000003/blk00000232/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000248 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/blk00000232/sig000010cd ), + .Q15(\NLW_blk00000003/blk00000232/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000247 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/blk00000232/sig000010cc ), + .Q15(\NLW_blk00000003/blk00000232/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000246 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/blk00000232/sig000010cb ), + .Q15(\NLW_blk00000003/blk00000232/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000245 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/blk00000232/sig000010ca ), + .Q15(\NLW_blk00000003/blk00000232/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000232/blk00000244 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000232/sig000010c8 ), + .A2(\blk00000003/blk00000232/sig000010c8 ), + .A3(\blk00000003/blk00000232/sig000010c8 ), + .CE(\blk00000003/blk00000232/sig000010d9 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/blk00000232/sig000010c9 ), + .Q15(\NLW_blk00000003/blk00000232/blk00000244_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000243 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d8 ), + .Q(\blk00000003/sig000009c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000242 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d7 ), + .Q(\blk00000003/sig000009c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000241 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d6 ), + .Q(\blk00000003/sig000009ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000240 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d5 ), + .Q(\blk00000003/sig000009cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d4 ), + .Q(\blk00000003/sig000009cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d3 ), + .Q(\blk00000003/sig000009cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d2 ), + .Q(\blk00000003/sig000009ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d1 ), + .Q(\blk00000003/sig000009cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010d0 ), + .Q(\blk00000003/sig000009d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk0000023a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cf ), + .Q(\blk00000003/sig000009d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000239 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ce ), + .Q(\blk00000003/sig000009d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cd ), + .Q(\blk00000003/sig000009d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cc ), + .Q(\blk00000003/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010cb ), + .Q(\blk00000003/sig000009d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010ca ), + .Q(\blk00000003/sig000009d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000232/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000232/sig000010c9 ), + .Q(\blk00000003/sig000009d7 ) + ); + GND \blk00000003/blk00000232/blk00000233 ( + .G(\blk00000003/blk00000232/sig000010c8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000255/blk00000277 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000255/sig0000110f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000276 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000255/sig0000110e ), + .Q15(\NLW_blk00000003/blk00000255/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000275 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000255/sig0000110d ), + .Q15(\NLW_blk00000003/blk00000255/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000274 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000255/sig0000110c ), + .Q15(\NLW_blk00000003/blk00000255/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000273 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000255/sig0000110b ), + .Q15(\NLW_blk00000003/blk00000255/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000272 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000255/sig0000110a ), + .Q15(\NLW_blk00000003/blk00000255/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000271 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000255/sig00001109 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000270 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000255/sig00001108 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000255/sig00001107 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000255/sig00001106 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000255/sig00001105 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000255/sig00001104 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000255/sig00001103 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk0000026a ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000255/sig00001102 ), + .Q15(\NLW_blk00000003/blk00000255/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000269 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000255/sig00001101 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000268 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000255/sig00001100 ), + .Q15(\NLW_blk00000003/blk00000255/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000255/blk00000267 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000255/sig000010fe ), + .A2(\blk00000003/blk00000255/sig000010fe ), + .A3(\blk00000003/blk00000255/sig000010fe ), + .CE(\blk00000003/blk00000255/sig0000110f ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000255/sig000010ff ), + .Q15(\NLW_blk00000003/blk00000255/blk00000267_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110e ), + .Q(\blk00000003/sig00000878 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110d ), + .Q(\blk00000003/sig00000879 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110c ), + .Q(\blk00000003/sig0000087a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110b ), + .Q(\blk00000003/sig0000087b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig0000110a ), + .Q(\blk00000003/sig0000087c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001109 ), + .Q(\blk00000003/sig0000087d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001108 ), + .Q(\blk00000003/sig0000087e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001107 ), + .Q(\blk00000003/sig0000087f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001106 ), + .Q(\blk00000003/sig00000880 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001105 ), + .Q(\blk00000003/sig00000881 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001104 ), + .Q(\blk00000003/sig00000882 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001103 ), + .Q(\blk00000003/sig00000883 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001102 ), + .Q(\blk00000003/sig00000884 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001101 ), + .Q(\blk00000003/sig00000885 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig00001100 ), + .Q(\blk00000003/sig00000886 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000255/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000255/sig000010ff ), + .Q(\blk00000003/sig00000887 ) + ); + GND \blk00000003/blk00000255/blk00000256 ( + .G(\blk00000003/blk00000255/sig000010fe ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000278/blk0000029a ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000278/sig00001145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000299 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/blk00000278/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000298 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/blk00000278/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000297 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/blk00000278/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000296 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/blk00000278/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000296_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000295 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/blk00000278/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000278/blk00000295_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000294 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/blk00000278/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000278/blk00000294_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000293 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/blk00000278/sig0000113e ), + .Q15(\NLW_blk00000003/blk00000278/blk00000293_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000292 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/blk00000278/sig0000113d ), + .Q15(\NLW_blk00000003/blk00000278/blk00000292_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000291 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/blk00000278/sig0000113c ), + .Q15(\NLW_blk00000003/blk00000278/blk00000291_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk00000290 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/blk00000278/sig0000113b ), + .Q15(\NLW_blk00000003/blk00000278/blk00000290_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/blk00000278/sig0000113a ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/blk00000278/sig00001139 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028d ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/blk00000278/sig00001138 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028c ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/blk00000278/sig00001137 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028b ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/blk00000278/sig00001136 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000278/blk0000028a ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000278/sig00001134 ), + .A2(\blk00000003/blk00000278/sig00001134 ), + .A3(\blk00000003/blk00000278/sig00001134 ), + .CE(\blk00000003/blk00000278/sig00001145 ), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/blk00000278/sig00001135 ), + .Q15(\NLW_blk00000003/blk00000278/blk0000028a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001144 ), + .Q(\blk00000003/sig00000868 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001143 ), + .Q(\blk00000003/sig00000869 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001142 ), + .Q(\blk00000003/sig0000086a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001141 ), + .Q(\blk00000003/sig0000086b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001140 ), + .Q(\blk00000003/sig0000086c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113f ), + .Q(\blk00000003/sig0000086d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113e ), + .Q(\blk00000003/sig0000086e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113d ), + .Q(\blk00000003/sig0000086f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113c ), + .Q(\blk00000003/sig00000870 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113b ), + .Q(\blk00000003/sig00000871 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig0000113a ), + .Q(\blk00000003/sig00000872 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001139 ), + .Q(\blk00000003/sig00000873 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001138 ), + .Q(\blk00000003/sig00000874 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001137 ), + .Q(\blk00000003/sig00000875 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001136 ), + .Q(\blk00000003/sig00000876 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000278/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000278/sig00001135 ), + .Q(\blk00000003/sig00000877 ) + ); + GND \blk00000003/blk00000278/blk00000279 ( + .G(\blk00000003/blk00000278/sig00001134 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000029b/blk000002bd ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk0000029b/sig0000117b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bc ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/blk0000029b/sig0000117a ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002bb ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/blk0000029b/sig00001179 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ba ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/blk0000029b/sig00001178 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b9 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/blk0000029b/sig00001177 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b8 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/blk0000029b/sig00001176 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b7 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093d ), + .Q(\blk00000003/blk0000029b/sig00001175 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b6 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093e ), + .Q(\blk00000003/blk0000029b/sig00001174 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b5 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig0000093f ), + .Q(\blk00000003/blk0000029b/sig00001173 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b4 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000940 ), + .Q(\blk00000003/blk0000029b/sig00001172 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b3 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000941 ), + .Q(\blk00000003/blk0000029b/sig00001171 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b2 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000942 ), + .Q(\blk00000003/blk0000029b/sig00001170 ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b1 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000943 ), + .Q(\blk00000003/blk0000029b/sig0000116f ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002b0 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000944 ), + .Q(\blk00000003/blk0000029b/sig0000116e ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002af ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000945 ), + .Q(\blk00000003/blk0000029b/sig0000116d ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ae ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000946 ), + .Q(\blk00000003/blk0000029b/sig0000116c ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000029b/blk000002ad ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk0000029b/sig0000116a ), + .A2(\blk00000003/blk0000029b/sig0000116a ), + .A3(\blk00000003/blk0000029b/sig0000116a ), + .CE(\blk00000003/blk0000029b/sig0000117b ), + .CLK(clk), + .D(\blk00000003/sig00000947 ), + .Q(\blk00000003/blk0000029b/sig0000116b ), + .Q15(\NLW_blk00000003/blk0000029b/blk000002ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000117a ), + .Q(\blk00000003/sig00000988 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001179 ), + .Q(\blk00000003/sig00000989 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001178 ), + .Q(\blk00000003/sig0000098a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001177 ), + .Q(\blk00000003/sig0000098b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001176 ), + .Q(\blk00000003/sig0000098c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001175 ), + .Q(\blk00000003/sig0000098d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001174 ), + .Q(\blk00000003/sig0000098e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001173 ), + .Q(\blk00000003/sig0000098f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001172 ), + .Q(\blk00000003/sig00000990 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001171 ), + .Q(\blk00000003/sig00000991 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig00001170 ), + .Q(\blk00000003/sig00000992 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116f ), + .Q(\blk00000003/sig00000993 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk000002a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116e ), + .Q(\blk00000003/sig00000994 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116d ), + .Q(\blk00000003/sig00000995 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116c ), + .Q(\blk00000003/sig00000996 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000029b/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000029b/sig0000116b ), + .Q(\blk00000003/sig00000997 ) + ); + GND \blk00000003/blk0000029b/blk0000029c ( + .G(\blk00000003/blk0000029b/sig0000116a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002be/blk000002e0 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk000002be/sig000011b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002df ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/blk000002be/sig000011b0 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002de ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/blk000002be/sig000011af ), + .Q15(\NLW_blk00000003/blk000002be/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dd ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/blk000002be/sig000011ae ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002dc ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/blk000002be/sig000011ad ), + .Q15(\NLW_blk00000003/blk000002be/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002db ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/blk000002be/sig000011ac ), + .Q15(\NLW_blk00000003/blk000002be/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002da ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/blk000002be/sig000011ab ), + .Q15(\NLW_blk00000003/blk000002be/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/blk000002be/sig000011aa ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/blk000002be/sig000011a9 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/blk000002be/sig000011a8 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/blk000002be/sig000011a7 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/blk000002be/sig000011a6 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/blk000002be/sig000011a5 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d3 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/blk000002be/sig000011a4 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d2 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/blk000002be/sig000011a3 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d1 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/blk000002be/sig000011a2 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002be/blk000002d0 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk000002be/sig000011a0 ), + .A2(\blk00000003/blk000002be/sig000011a0 ), + .A3(\blk00000003/blk000002be/sig000011a0 ), + .CE(\blk00000003/blk000002be/sig000011b1 ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/blk000002be/sig000011a1 ), + .Q15(\NLW_blk00000003/blk000002be/blk000002d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011b0 ), + .Q(\blk00000003/sig00000978 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011af ), + .Q(\blk00000003/sig00000979 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ae ), + .Q(\blk00000003/sig0000097a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ad ), + .Q(\blk00000003/sig0000097b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ac ), + .Q(\blk00000003/sig0000097c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011ab ), + .Q(\blk00000003/sig0000097d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011aa ), + .Q(\blk00000003/sig0000097e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a9 ), + .Q(\blk00000003/sig0000097f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a8 ), + .Q(\blk00000003/sig00000980 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a7 ), + .Q(\blk00000003/sig00000981 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a6 ), + .Q(\blk00000003/sig00000982 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a5 ), + .Q(\blk00000003/sig00000983 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a4 ), + .Q(\blk00000003/sig00000984 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a3 ), + .Q(\blk00000003/sig00000985 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a2 ), + .Q(\blk00000003/sig00000986 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002be/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002be/sig000011a1 ), + .Q(\blk00000003/sig00000987 ) + ); + GND \blk00000003/blk000002be/blk000002bf ( + .G(\blk00000003/blk000002be/sig000011a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e1/blk00000303 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000002e1/sig000011e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000302 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002e1/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000301 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002e1/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk00000300 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk000002e1/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000002e1/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002ff ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk000002e1/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fe ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk000002e1/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk000002e1/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk000002e1/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk000002e1/sig000011df ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002fa ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk000002e1/sig000011de ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk000002e1/sig000011dd ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk000002e1/sig000011dc ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk000002e1/sig000011db ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f6 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk000002e1/sig000011da ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f5 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk000002e1/sig000011d9 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk000002e1/sig000011d8 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e1/blk000002f3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000002e1/sig000011d6 ), + .A2(\blk00000003/blk000002e1/sig000011d6 ), + .A3(\blk00000003/blk000002e1/sig000011d6 ), + .CE(\blk00000003/blk000002e1/sig000011e7 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk000002e1/sig000011d7 ), + .Q15(\NLW_blk00000003/blk000002e1/blk000002f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e6 ), + .Q(\blk00000003/sig00000828 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e5 ), + .Q(\blk00000003/sig00000829 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e4 ), + .Q(\blk00000003/sig0000082a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e3 ), + .Q(\blk00000003/sig0000082b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e2 ), + .Q(\blk00000003/sig0000082c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e1 ), + .Q(\blk00000003/sig0000082d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011e0 ), + .Q(\blk00000003/sig0000082e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011df ), + .Q(\blk00000003/sig0000082f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011de ), + .Q(\blk00000003/sig00000830 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dd ), + .Q(\blk00000003/sig00000831 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011dc ), + .Q(\blk00000003/sig00000832 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011db ), + .Q(\blk00000003/sig00000833 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011da ), + .Q(\blk00000003/sig00000834 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d9 ), + .Q(\blk00000003/sig00000835 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d8 ), + .Q(\blk00000003/sig00000836 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e1/sig000011d7 ), + .Q(\blk00000003/sig00000837 ) + ); + GND \blk00000003/blk000002e1/blk000002e2 ( + .G(\blk00000003/blk000002e1/sig000011d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000304/blk00000326 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk00000304/sig0000121d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000325 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/blk00000304/sig0000121c ), + .Q15(\NLW_blk00000003/blk00000304/blk00000325_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000324 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/blk00000304/sig0000121b ), + .Q15(\NLW_blk00000003/blk00000304/blk00000324_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000323 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/blk00000304/sig0000121a ), + .Q15(\NLW_blk00000003/blk00000304/blk00000323_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000322 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/blk00000304/sig00001219 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000322_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000321 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/blk00000304/sig00001218 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000321_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000320 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/blk00000304/sig00001217 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000320_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/blk00000304/sig00001216 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/blk00000304/sig00001215 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/blk00000304/sig00001214 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/blk00000304/sig00001213 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/blk00000304/sig00001212 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk0000031a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/blk00000304/sig00001211 ), + .Q15(\NLW_blk00000003/blk00000304/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000319 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/blk00000304/sig00001210 ), + .Q15(\NLW_blk00000003/blk00000304/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000318 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/blk00000304/sig0000120f ), + .Q15(\NLW_blk00000003/blk00000304/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000317 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/blk00000304/sig0000120e ), + .Q15(\NLW_blk00000003/blk00000304/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000304/blk00000316 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk00000304/sig0000120c ), + .A2(\blk00000003/blk00000304/sig0000120c ), + .A3(\blk00000003/blk00000304/sig0000120c ), + .CE(\blk00000003/blk00000304/sig0000121d ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/blk00000304/sig0000120d ), + .Q15(\NLW_blk00000003/blk00000304/blk00000316_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121c ), + .Q(\blk00000003/sig00000818 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121b ), + .Q(\blk00000003/sig00000819 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000121a ), + .Q(\blk00000003/sig0000081a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001219 ), + .Q(\blk00000003/sig0000081b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001218 ), + .Q(\blk00000003/sig0000081c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001217 ), + .Q(\blk00000003/sig0000081d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001216 ), + .Q(\blk00000003/sig0000081e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001215 ), + .Q(\blk00000003/sig0000081f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001214 ), + .Q(\blk00000003/sig00000820 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001213 ), + .Q(\blk00000003/sig00000821 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001212 ), + .Q(\blk00000003/sig00000822 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk0000030a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001211 ), + .Q(\blk00000003/sig00000823 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000309 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig00001210 ), + .Q(\blk00000003/sig00000824 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000308 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120f ), + .Q(\blk00000003/sig00000825 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000307 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120e ), + .Q(\blk00000003/sig00000826 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000304/blk00000306 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000304/sig0000120d ), + .Q(\blk00000003/sig00000827 ) + ); + GND \blk00000003/blk00000304/blk00000305 ( + .G(\blk00000003/blk00000304/sig0000120c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000327/blk00000349 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk00000327/sig00001253 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000348 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/blk00000327/sig00001252 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000347 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/blk00000327/sig00001251 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000346 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/blk00000327/sig00001250 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000345 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/blk00000327/sig0000124f ), + .Q15(\NLW_blk00000003/blk00000327/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000344 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/blk00000327/sig0000124e ), + .Q15(\NLW_blk00000003/blk00000327/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000343 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/blk00000327/sig0000124d ), + .Q15(\NLW_blk00000003/blk00000327/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000342 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/blk00000327/sig0000124c ), + .Q15(\NLW_blk00000003/blk00000327/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000341 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/blk00000327/sig0000124b ), + .Q15(\NLW_blk00000003/blk00000327/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000340 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/blk00000327/sig0000124a ), + .Q15(\NLW_blk00000003/blk00000327/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033f ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/blk00000327/sig00001249 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033e ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/blk00000327/sig00001248 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033d ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/blk00000327/sig00001247 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033c ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/blk00000327/sig00001246 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033b ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/blk00000327/sig00001245 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk0000033a ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/blk00000327/sig00001244 ), + .Q15(\NLW_blk00000003/blk00000327/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000327/blk00000339 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk00000327/sig00001242 ), + .A2(\blk00000003/blk00000327/sig00001242 ), + .A3(\blk00000003/blk00000327/sig00001242 ), + .CE(\blk00000003/blk00000327/sig00001253 ), + .CLK(clk), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/blk00000327/sig00001243 ), + .Q15(\NLW_blk00000003/blk00000327/blk00000339_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000338 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001252 ), + .Q(\blk00000003/sig00000938 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001251 ), + .Q(\blk00000003/sig00000939 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001250 ), + .Q(\blk00000003/sig0000093a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124f ), + .Q(\blk00000003/sig0000093b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124e ), + .Q(\blk00000003/sig0000093c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124d ), + .Q(\blk00000003/sig0000093d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124c ), + .Q(\blk00000003/sig0000093e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124b ), + .Q(\blk00000003/sig0000093f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig0000124a ), + .Q(\blk00000003/sig00000940 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001249 ), + .Q(\blk00000003/sig00000941 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001248 ), + .Q(\blk00000003/sig00000942 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001247 ), + .Q(\blk00000003/sig00000943 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001246 ), + .Q(\blk00000003/sig00000944 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001245 ), + .Q(\blk00000003/sig00000945 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001244 ), + .Q(\blk00000003/sig00000946 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000327/sig00001243 ), + .Q(\blk00000003/sig00000947 ) + ); + GND \blk00000003/blk00000327/blk00000328 ( + .G(\blk00000003/blk00000327/sig00001242 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000034a/blk0000036c ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk0000034a/sig00001289 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036b ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/blk0000034a/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000036a ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/blk0000034a/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000369 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/blk0000034a/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000368 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/blk0000034a/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000367 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/blk0000034a/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000366 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/blk0000034a/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000365 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/blk0000034a/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000364 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/blk0000034a/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000363 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/blk0000034a/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000362 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/blk0000034a/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000362_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000361 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/blk0000034a/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000361_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk00000360 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/blk0000034a/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000034a/blk00000360_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035f ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/blk0000034a/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035e ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/blk0000034a/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035d ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/blk0000034a/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000034a/blk0000035c ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk0000034a/sig00001278 ), + .A2(\blk00000003/blk0000034a/sig00001278 ), + .A3(\blk00000003/blk0000034a/sig00001278 ), + .CE(\blk00000003/blk0000034a/sig00001289 ), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/blk0000034a/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000034a/blk0000035c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001288 ), + .Q(\blk00000003/sig00000928 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001287 ), + .Q(\blk00000003/sig00000929 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001286 ), + .Q(\blk00000003/sig0000092a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001285 ), + .Q(\blk00000003/sig0000092b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001284 ), + .Q(\blk00000003/sig0000092c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001283 ), + .Q(\blk00000003/sig0000092d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001282 ), + .Q(\blk00000003/sig0000092e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001281 ), + .Q(\blk00000003/sig0000092f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001280 ), + .Q(\blk00000003/sig00000930 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127f ), + .Q(\blk00000003/sig00000931 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127e ), + .Q(\blk00000003/sig00000932 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127d ), + .Q(\blk00000003/sig00000933 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127c ), + .Q(\blk00000003/sig00000934 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127b ), + .Q(\blk00000003/sig00000935 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig0000127a ), + .Q(\blk00000003/sig00000936 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000034a/sig00001279 ), + .Q(\blk00000003/sig00000937 ) + ); + GND \blk00000003/blk0000034a/blk0000034b ( + .G(\blk00000003/blk0000034a/sig00001278 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000036d/blk0000038f ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000036d/sig000012bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041e ), + .Q(\blk00000003/blk0000036d/sig000012be ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000041f ), + .Q(\blk00000003/blk0000036d/sig000012bd ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000420 ), + .Q(\blk00000003/blk0000036d/sig000012bc ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000421 ), + .Q(\blk00000003/blk0000036d/sig000012bb ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000038a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000422 ), + .Q(\blk00000003/blk0000036d/sig000012ba ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000038a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000389 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000423 ), + .Q(\blk00000003/blk0000036d/sig000012b9 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000389_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000388 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000424 ), + .Q(\blk00000003/blk0000036d/sig000012b8 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000388_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000387 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000425 ), + .Q(\blk00000003/blk0000036d/sig000012b7 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000387_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000386 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000426 ), + .Q(\blk00000003/blk0000036d/sig000012b6 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000386_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000385 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000427 ), + .Q(\blk00000003/blk0000036d/sig000012b5 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000385_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000384 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000428 ), + .Q(\blk00000003/blk0000036d/sig000012b4 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000384_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000383 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig00000429 ), + .Q(\blk00000003/blk0000036d/sig000012b3 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000383_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000382 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042a ), + .Q(\blk00000003/blk0000036d/sig000012b2 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000381 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042b ), + .Q(\blk00000003/blk0000036d/sig000012b1 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk00000380 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042c ), + .Q(\blk00000003/blk0000036d/sig000012b0 ), + .Q15(\NLW_blk00000003/blk0000036d/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000036d/blk0000037f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000036d/sig000012ae ), + .A2(\blk00000003/blk0000036d/sig000012ae ), + .A3(\blk00000003/blk0000036d/sig000012ae ), + .CE(\blk00000003/blk0000036d/sig000012bf ), + .CLK(clk), + .D(\blk00000003/sig0000042d ), + .Q(\blk00000003/blk0000036d/sig000012af ), + .Q15(\NLW_blk00000003/blk0000036d/blk0000037f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012be ), + .Q(\blk00000003/sig000007d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bd ), + .Q(\blk00000003/sig000007d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bc ), + .Q(\blk00000003/sig000007da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012bb ), + .Q(\blk00000003/sig000007db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012ba ), + .Q(\blk00000003/sig000007dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b9 ), + .Q(\blk00000003/sig000007dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b8 ), + .Q(\blk00000003/sig000007de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b7 ), + .Q(\blk00000003/sig000007df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b6 ), + .Q(\blk00000003/sig000007e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b5 ), + .Q(\blk00000003/sig000007e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b4 ), + .Q(\blk00000003/sig000007e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b3 ), + .Q(\blk00000003/sig000007e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000372 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b2 ), + .Q(\blk00000003/sig000007e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000371 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b1 ), + .Q(\blk00000003/sig000007e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk00000370 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012b0 ), + .Q(\blk00000003/sig000007e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d/blk0000036f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000036d/sig000012af ), + .Q(\blk00000003/sig000007e7 ) + ); + GND \blk00000003/blk0000036d/blk0000036e ( + .G(\blk00000003/blk0000036d/sig000012ae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000390/blk000003b2 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000390/sig000012f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/blk00000390/sig000012f4 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003b0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/blk00000390/sig000012f3 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003af ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/blk00000390/sig000012f2 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ae ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/blk00000390/sig000012f1 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ad ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/blk00000390/sig000012f0 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ac ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/blk00000390/sig000012ef ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003ab ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/blk00000390/sig000012ee ), + .Q15(\NLW_blk00000003/blk00000390/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003aa ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/blk00000390/sig000012ed ), + .Q15(\NLW_blk00000003/blk00000390/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/blk00000390/sig000012ec ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/blk00000390/sig000012eb ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/blk00000390/sig000012ea ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/blk00000390/sig000012e9 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/blk00000390/sig000012e8 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/blk00000390/sig000012e7 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/blk00000390/sig000012e6 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk000003a2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000390/sig000012e4 ), + .A2(\blk00000003/blk00000390/sig000012e4 ), + .A3(\blk00000003/blk00000390/sig000012e4 ), + .CE(\blk00000003/blk00000390/sig000012f5 ), + .CLK(clk), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/blk00000390/sig000012e5 ), + .Q15(\NLW_blk00000003/blk00000390/blk000003a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f4 ), + .Q(\blk00000003/sig000007c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f3 ), + .Q(\blk00000003/sig000007c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f2 ), + .Q(\blk00000003/sig000007ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f1 ), + .Q(\blk00000003/sig000007cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012f0 ), + .Q(\blk00000003/sig000007cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ef ), + .Q(\blk00000003/sig000007cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ee ), + .Q(\blk00000003/sig000007ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ed ), + .Q(\blk00000003/sig000007cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ec ), + .Q(\blk00000003/sig000007d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012eb ), + .Q(\blk00000003/sig000007d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012ea ), + .Q(\blk00000003/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e9 ), + .Q(\blk00000003/sig000007d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e8 ), + .Q(\blk00000003/sig000007d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e7 ), + .Q(\blk00000003/sig000007d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e6 ), + .Q(\blk00000003/sig000007d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000390/sig000012e5 ), + .Q(\blk00000003/sig000007d7 ) + ); + GND \blk00000003/blk00000390/blk00000391 ( + .G(\blk00000003/blk00000390/sig000012e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b3/blk000003d5 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000003b3/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d4 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000003b3/sig0000132a ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d3 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000003b3/sig00001329 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d2 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000003b3/sig00001328 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d1 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000003b3/sig00001327 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003d0 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000003b3/sig00001326 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cf ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000003b3/sig00001325 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ce ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000003b3/sig00001324 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cd ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000003b3/sig00001323 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cc ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000003b3/sig00001322 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003cb ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000003b3/sig00001321 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003ca ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000003b3/sig00001320 ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c9 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000003b3/sig0000131f ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c8 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000003b3/sig0000131e ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c7 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000003b3/sig0000131d ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c6 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000003b3/sig0000131c ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b3/blk000003c5 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000003b3/sig0000131a ), + .A2(\blk00000003/blk000003b3/sig0000131a ), + .A3(\blk00000003/blk000003b3/sig0000131a ), + .CE(\blk00000003/blk000003b3/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000003b3/sig0000131b ), + .Q15(\NLW_blk00000003/blk000003b3/blk000003c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000132a ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001329 ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001328 ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001327 ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001326 ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001325 ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001324 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001323 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001322 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001321 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig00001320 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131f ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131e ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131d ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131c ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b3/sig0000131b ), + .Q(\blk00000003/sig000008f7 ) + ); + GND \blk00000003/blk000003b3/blk000003b4 ( + .G(\blk00000003/blk000003b3/sig0000131a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d6/blk000003f8 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk000003d6/sig00001361 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f7 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/blk000003d6/sig00001360 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f6 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/blk000003d6/sig0000135f ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f5 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/blk000003d6/sig0000135e ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f4 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/blk000003d6/sig0000135d ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f3 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/blk000003d6/sig0000135c ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f2 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/blk000003d6/sig0000135b ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f1 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/blk000003d6/sig0000135a ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003f0 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/blk000003d6/sig00001359 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003f0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ef ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/blk000003d6/sig00001358 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ef_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ee ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/blk000003d6/sig00001357 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ee_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ed ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/blk000003d6/sig00001356 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ec ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/blk000003d6/sig00001355 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003eb ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/blk000003d6/sig00001354 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003ea ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/blk000003d6/sig00001353 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e9 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/blk000003d6/sig00001352 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d6/blk000003e8 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk000003d6/sig00001350 ), + .A2(\blk00000003/blk000003d6/sig00001350 ), + .A3(\blk00000003/blk000003d6/sig00001350 ), + .CE(\blk00000003/blk000003d6/sig00001361 ), + .CLK(clk), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/blk000003d6/sig00001351 ), + .Q15(\NLW_blk00000003/blk000003d6/blk000003e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001360 ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135f ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135e ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135d ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135c ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135b ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig0000135a ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001359 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001358 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001357 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001356 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001355 ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001354 ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001353 ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001352 ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d6/sig00001351 ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk000003d6/blk000003d7 ( + .G(\blk00000003/blk000003d6/sig00001350 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000041b ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00001397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000041a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/blk000003f9/sig00001396 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000419 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/blk000003f9/sig00001395 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000418 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/blk000003f9/sig00001394 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000417 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/blk000003f9/sig00001393 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000416 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/blk000003f9/sig00001392 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000415 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/blk000003f9/sig00001391 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000414 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/blk000003f9/sig00001390 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000413 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/blk000003f9/sig0000138f ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000412 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/blk000003f9/sig0000138e ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000411 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/blk000003f9/sig0000138d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000410 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/blk000003f9/sig0000138c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/blk000003f9/sig0000138b ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/blk000003f9/sig0000138a ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/blk000003f9/sig00001389 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/blk000003f9/sig00001388 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk000003f9/sig00001386 ), + .A2(\blk00000003/blk000003f9/sig00001386 ), + .A3(\blk00000003/blk000003f9/sig00001386 ), + .CE(\blk00000003/blk000003f9/sig00001397 ), + .CLK(clk), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/blk000003f9/sig00001387 ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk0000040a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001396 ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000409 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001395 ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000408 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001394 ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000407 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001393 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000406 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001392 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000405 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001391 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000404 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001390 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138f ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138e ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138d ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138c ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138b ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig0000138a ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001389 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001388 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00001387 ), + .Q(\blk00000003/sig0000042d ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00001386 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041c/blk0000043e ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000041c/sig000013cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/blk0000041c/sig000013cc ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/blk0000041c/sig000013cb ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/blk0000041c/sig000013ca ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000043a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/blk0000041c/sig000013c9 ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000439 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/blk0000041c/sig000013c8 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000438 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/blk0000041c/sig000013c7 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000437 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/blk0000041c/sig000013c6 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000437_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000436 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/blk0000041c/sig000013c5 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000436_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000435 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/blk0000041c/sig000013c4 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000435_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000434 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/blk0000041c/sig000013c3 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000434_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000433 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/blk0000041c/sig000013c2 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000433_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000432 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/blk0000041c/sig000013c1 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000432_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000431 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/blk0000041c/sig000013c0 ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000431_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk00000430 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/blk0000041c/sig000013bf ), + .Q15(\NLW_blk00000003/blk0000041c/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/blk0000041c/sig000013be ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041c/blk0000042e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000041c/sig000013bc ), + .A2(\blk00000003/blk0000041c/sig000013bc ), + .A3(\blk00000003/blk0000041c/sig000013bc ), + .CE(\blk00000003/blk0000041c/sig000013cd ), + .CLK(clk), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/blk0000041c/sig000013bd ), + .Q15(\NLW_blk00000003/blk0000041c/blk0000042e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cc ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013cb ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013ca ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c9 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c8 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c7 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c6 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c5 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c4 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c3 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c2 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c1 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013c0 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bf ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013be ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c/blk0000041e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041c/sig000013bd ), + .Q(\blk00000003/sig0000041d ) + ); + GND \blk00000003/blk0000041c/blk0000041d ( + .G(\blk00000003/blk0000041c/sig000013bc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043f/blk00000461 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000043f/sig00001403 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000460 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/blk0000043f/sig00001402 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000460_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/blk0000043f/sig00001401 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045e ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/blk0000043f/sig00001400 ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045d ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/blk0000043f/sig000013ff ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/blk0000043f/sig000013fe ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/blk0000043f/sig000013fd ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk0000045a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/blk0000043f/sig000013fc ), + .Q15(\NLW_blk00000003/blk0000043f/blk0000045a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000459 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/blk0000043f/sig000013fb ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000459_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000458 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/blk0000043f/sig000013fa ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000458_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000457 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/blk0000043f/sig000013f9 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000457_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000456 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/blk0000043f/sig000013f8 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000455 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/blk0000043f/sig000013f7 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000454 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/blk0000043f/sig000013f6 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000453 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/blk0000043f/sig000013f5 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000452 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/blk0000043f/sig000013f4 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000043f/blk00000451 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000043f/sig000013f2 ), + .A2(\blk00000003/blk0000043f/sig000013f2 ), + .A3(\blk00000003/blk0000043f/sig000013f2 ), + .CE(\blk00000003/blk0000043f/sig00001403 ), + .CLK(clk), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/blk0000043f/sig000013f3 ), + .Q15(\NLW_blk00000003/blk0000043f/blk00000451_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001402 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001401 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig00001400 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013ff ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fe ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fd ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fc ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fb ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013fa ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f9 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000446 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f8 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000445 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f7 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000444 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f6 ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000443 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f5 ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000442 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f4 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f/blk00000441 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000043f/sig000013f3 ), + .Q(\blk00000003/sig0000047d ) + ); + GND \blk00000003/blk0000043f/blk00000440 ( + .G(\blk00000003/blk0000043f/sig000013f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000462/blk00000484 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000462/sig00001439 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000483 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/blk00000462/sig00001438 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000483_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000482 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/blk00000462/sig00001437 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000482_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000481 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/blk00000462/sig00001436 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000480 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/blk00000462/sig00001435 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/blk00000462/sig00001434 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/blk00000462/sig00001433 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/blk00000462/sig00001432 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/blk00000462/sig00001431 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/blk00000462/sig00001430 ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk0000047a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/blk00000462/sig0000142f ), + .Q15(\NLW_blk00000003/blk00000462/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000479 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/blk00000462/sig0000142e ), + .Q15(\NLW_blk00000003/blk00000462/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000478 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/blk00000462/sig0000142d ), + .Q15(\NLW_blk00000003/blk00000462/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000477 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/blk00000462/sig0000142c ), + .Q15(\NLW_blk00000003/blk00000462/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000476 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/blk00000462/sig0000142b ), + .Q15(\NLW_blk00000003/blk00000462/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000475 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/blk00000462/sig0000142a ), + .Q15(\NLW_blk00000003/blk00000462/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000462/blk00000474 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000462/sig00001428 ), + .A2(\blk00000003/blk00000462/sig00001428 ), + .A3(\blk00000003/blk00000462/sig00001428 ), + .CE(\blk00000003/blk00000462/sig00001439 ), + .CLK(clk), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/blk00000462/sig00001429 ), + .Q15(\NLW_blk00000003/blk00000462/blk00000474_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001438 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001437 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001436 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001435 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001434 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001433 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001432 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001431 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001430 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk0000046a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142f ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142e ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig0000142a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000462/sig00001429 ), + .Q(\blk00000003/sig0000046d ) + ); + GND \blk00000003/blk00000462/blk00000463 ( + .G(\blk00000003/blk00000462/sig00001428 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000485/blk000004bd ( + .I0(\blk00000003/sig0000030c ), + .I1(ce), + .O(\blk00000003/blk00000485/sig0000149c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bc ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001489 ), + .DPO(\blk00000003/blk00000485/sig0000149b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004bb ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001488 ), + .DPO(\blk00000003/blk00000485/sig0000149a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004ba ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001487 ), + .DPO(\blk00000003/blk00000485/sig00001499 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b9 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001486 ), + .DPO(\blk00000003/blk00000485/sig00001498 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b8 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001485 ), + .DPO(\blk00000003/blk00000485/sig00001497 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b7 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001484 ), + .DPO(\blk00000003/blk00000485/sig00001496 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b6 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001482 ), + .DPO(\blk00000003/blk00000485/sig00001494 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b5 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001481 ), + .DPO(\blk00000003/blk00000485/sig00001493 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b4 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001483 ), + .DPO(\blk00000003/blk00000485/sig00001495 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000485/blk000004b3 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001480 ), + .DPO(\blk00000003/blk00000485/sig00001492 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b2 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147f ), + .DPO(\blk00000003/blk00000485/sig00001491 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004b1 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147e ), + .DPO(\blk00000003/blk00000485/sig00001490 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004b0 ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147d ), + .DPO(\blk00000003/blk00000485/sig0000148f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004af ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147c ), + .DPO(\blk00000003/blk00000485/sig0000148e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ae ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147b ), + .DPO(\blk00000003/blk00000485/sig0000148d ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000485/blk000004ad ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001479 ), + .DPO(\blk00000003/blk00000485/sig0000148b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ac ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig00001478 ), + .DPO(\blk00000003/blk00000485/sig0000148a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000485/blk000004ab ( + .A0(\blk00000003/sig00000334 ), + .A1(\blk00000003/sig00000337 ), + .A2(\blk00000003/blk00000485/sig00001477 ), + .A3(\blk00000003/blk00000485/sig00001477 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000375 ), + .DPRA1(\blk00000003/sig0000037b ), + .DPRA2(\blk00000003/blk00000485/sig00001477 ), + .DPRA3(\blk00000003/blk00000485/sig00001477 ), + .WCLK(clk), + .WE(\blk00000003/blk00000485/sig0000149c ), + .SPO(\blk00000003/blk00000485/sig0000147a ), + .DPO(\blk00000003/blk00000485/sig0000148c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149b ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000149a ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001499 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001498 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001497 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001496 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001495 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001494 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001493 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001492 ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk000004a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001491 ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001490 ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148f ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148e ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148d ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148c ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148b ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000148a ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001489 ), + .Q(\blk00000003/sig00000b09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001488 ), + .Q(\blk00000003/sig00000b0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001487 ), + .Q(\blk00000003/sig00000b0b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001486 ), + .Q(\blk00000003/sig00000b0c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001485 ), + .Q(\blk00000003/sig00000b0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001484 ), + .Q(\blk00000003/sig00000b0e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001483 ), + .Q(\blk00000003/sig00000b0f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001482 ), + .Q(\blk00000003/sig00000b10 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001481 ), + .Q(\blk00000003/sig00000b11 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001480 ), + .Q(\blk00000003/sig00000b12 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147f ), + .Q(\blk00000003/sig00000b13 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147e ), + .Q(\blk00000003/sig00000b14 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147d ), + .Q(\blk00000003/sig00000b15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147c ), + .Q(\blk00000003/sig00000b16 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147b ), + .Q(\blk00000003/sig00000b17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig0000147a ), + .Q(\blk00000003/sig00000b18 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001479 ), + .Q(\blk00000003/sig00000b19 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000485/sig00001478 ), + .Q(\blk00000003/sig00000b1a ) + ); + GND \blk00000003/blk00000485/blk00000486 ( + .G(\blk00000003/blk00000485/sig00001477 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004be/blk000004f6 ( + .I0(\blk00000003/sig000009f2 ), + .I1(ce), + .O(\blk00000003/blk000004be/sig000014ff ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b09 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ec ), + .DPO(\blk00000003/blk000004be/sig000014fe ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014eb ), + .DPO(\blk00000003/blk000004be/sig000014fd ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f3 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0b ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014ea ), + .DPO(\blk00000003/blk000004be/sig000014fc ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f2 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0c ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e9 ), + .DPO(\blk00000003/blk000004be/sig000014fb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f1 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0d ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e8 ), + .DPO(\blk00000003/blk000004be/sig000014fa ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004f0 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0e ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e7 ), + .DPO(\blk00000003/blk000004be/sig000014f9 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ef ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b10 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e5 ), + .DPO(\blk00000003/blk000004be/sig000014f7 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ee ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b11 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e4 ), + .DPO(\blk00000003/blk000004be/sig000014f6 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004ed ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b0f ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e6 ), + .DPO(\blk00000003/blk000004be/sig000014f8 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004ec ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b12 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e3 ), + .DPO(\blk00000003/blk000004be/sig000014f5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004eb ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b13 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e2 ), + .DPO(\blk00000003/blk000004be/sig000014f4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004be/blk000004ea ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b14 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e1 ), + .DPO(\blk00000003/blk000004be/sig000014f3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004be/blk000004e9 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b15 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014e0 ), + .DPO(\blk00000003/blk000004be/sig000014f2 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e8 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b16 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014df ), + .DPO(\blk00000003/blk000004be/sig000014f1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004be/blk000004e7 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b17 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014de ), + .DPO(\blk00000003/blk000004be/sig000014f0 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e6 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b19 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dc ), + .DPO(\blk00000003/blk000004be/sig000014ee ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e5 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b1a ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014db ), + .DPO(\blk00000003/blk000004be/sig000014ed ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004be/blk000004e4 ( + .A0(\blk00000003/sig000009e8 ), + .A1(\blk00000003/sig000009e9 ), + .A2(\blk00000003/blk000004be/sig000014da ), + .A3(\blk00000003/blk000004be/sig000014da ), + .D(\blk00000003/sig00000b18 ), + .DPRA0(\blk00000003/sig00000a12 ), + .DPRA1(\blk00000003/sig00000a11 ), + .DPRA2(\blk00000003/blk000004be/sig000014da ), + .DPRA3(\blk00000003/blk000004be/sig000014da ), + .WCLK(clk), + .WE(\blk00000003/blk000004be/sig000014ff ), + .SPO(\blk00000003/blk000004be/sig000014dd ), + .DPO(\blk00000003/blk000004be/sig000014ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fe ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fd ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fc ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fb ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014fa ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f9 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f8 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f7 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f6 ), + .Q(\blk00000003/sig00000588 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f5 ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f4 ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f3 ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f2 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f1 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014f0 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ef ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ee ), + .Q(\blk00000003/sig00000590 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ed ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ec ), + .Q(\blk00000003/sig00000b1b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014eb ), + .Q(\blk00000003/sig00000b1c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014ea ), + .Q(\blk00000003/sig00000b1d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e9 ), + .Q(\blk00000003/sig00000b1e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e8 ), + .Q(\blk00000003/sig00000b1f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e7 ), + .Q(\blk00000003/sig00000b20 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e6 ), + .Q(\blk00000003/sig00000b21 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e5 ), + .Q(\blk00000003/sig00000b22 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e4 ), + .Q(\blk00000003/sig00000b23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e3 ), + .Q(\blk00000003/sig00000b24 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e2 ), + .Q(\blk00000003/sig00000b25 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e1 ), + .Q(\blk00000003/sig00000b26 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014e0 ), + .Q(\blk00000003/sig00000b27 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014df ), + .Q(\blk00000003/sig00000b28 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014de ), + .Q(\blk00000003/sig00000b29 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dd ), + .Q(\blk00000003/sig00000b2a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014dc ), + .Q(\blk00000003/sig00000b2b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004be/sig000014db ), + .Q(\blk00000003/sig00000b2c ) + ); + GND \blk00000003/blk000004be/blk000004bf ( + .G(\blk00000003/blk000004be/sig000014da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004f7/blk0000052f ( + .I0(\blk00000003/sig000009f3 ), + .I1(ce), + .O(\blk00000003/blk000004f7/sig00001562 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154f ), + .DPO(\blk00000003/blk000004f7/sig00001561 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154e ), + .DPO(\blk00000003/blk000004f7/sig00001560 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052c ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1d ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154d ), + .DPO(\blk00000003/blk000004f7/sig0000155f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052b ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1e ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154c ), + .DPO(\blk00000003/blk000004f7/sig0000155e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000052a ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b1f ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154b ), + .DPO(\blk00000003/blk000004f7/sig0000155d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000529 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b20 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000154a ), + .DPO(\blk00000003/blk000004f7/sig0000155c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000528 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b22 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001548 ), + .DPO(\blk00000003/blk000004f7/sig0000155a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000527 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b23 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001547 ), + .DPO(\blk00000003/blk000004f7/sig00001559 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000526 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b21 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001549 ), + .DPO(\blk00000003/blk000004f7/sig0000155b ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000525 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b24 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001546 ), + .DPO(\blk00000003/blk000004f7/sig00001558 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000524 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b25 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001545 ), + .DPO(\blk00000003/blk000004f7/sig00001557 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004f7/blk00000523 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b26 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001544 ), + .DPO(\blk00000003/blk000004f7/sig00001556 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000004f7/blk00000522 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b27 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001543 ), + .DPO(\blk00000003/blk000004f7/sig00001555 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk00000521 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b28 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001542 ), + .DPO(\blk00000003/blk000004f7/sig00001554 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk00000520 ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b29 ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001541 ), + .DPO(\blk00000003/blk000004f7/sig00001553 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051f ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2b ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153f ), + .DPO(\blk00000003/blk000004f7/sig00001551 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004f7/blk0000051e ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2c ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig0000153e ), + .DPO(\blk00000003/blk000004f7/sig00001550 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000004f7/blk0000051d ( + .A0(\blk00000003/sig000009ea ), + .A1(\blk00000003/sig000009eb ), + .A2(\blk00000003/blk000004f7/sig0000153d ), + .A3(\blk00000003/blk000004f7/sig0000153d ), + .D(\blk00000003/sig00000b2a ), + .DPRA0(\blk00000003/sig00000a0c ), + .DPRA1(\blk00000003/sig00000a0b ), + .DPRA2(\blk00000003/blk000004f7/sig0000153d ), + .DPRA3(\blk00000003/blk000004f7/sig0000153d ), + .WCLK(clk), + .WE(\blk00000003/blk000004f7/sig00001562 ), + .SPO(\blk00000003/blk000004f7/sig00001540 ), + .DPO(\blk00000003/blk000004f7/sig00001552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001561 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001560 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155f ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155e ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155d ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155c ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155b ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000155a ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001559 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001558 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001557 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001556 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001555 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001554 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001553 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001552 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001551 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001550 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154f ), + .Q(\blk00000003/sig00000b2d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154e ), + .Q(\blk00000003/sig00000b2e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154d ), + .Q(\blk00000003/sig00000b2f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154c ), + .Q(\blk00000003/sig00000b30 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154b ), + .Q(\blk00000003/sig00000b31 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000154a ), + .Q(\blk00000003/sig00000b32 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001549 ), + .Q(\blk00000003/sig00000b33 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001548 ), + .Q(\blk00000003/sig00000b34 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001547 ), + .Q(\blk00000003/sig00000b35 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001546 ), + .Q(\blk00000003/sig00000b36 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001545 ), + .Q(\blk00000003/sig00000b37 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001544 ), + .Q(\blk00000003/sig00000b38 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001543 ), + .Q(\blk00000003/sig00000b39 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001542 ), + .Q(\blk00000003/sig00000b3a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001541 ), + .Q(\blk00000003/sig00000b3b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig00001540 ), + .Q(\blk00000003/sig00000b3c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153f ), + .Q(\blk00000003/sig00000b3d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004f7/sig0000153e ), + .Q(\blk00000003/sig00000b3e ) + ); + GND \blk00000003/blk000004f7/blk000004f8 ( + .G(\blk00000003/blk000004f7/sig0000153d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000530/blk00000568 ( + .I0(\blk00000003/sig000009f4 ), + .I1(ce), + .O(\blk00000003/blk00000530/sig000015c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000567 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b2 ), + .DPO(\blk00000003/blk00000530/sig000015c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000566 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b1 ), + .DPO(\blk00000003/blk00000530/sig000015c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000565 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b2f ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015b0 ), + .DPO(\blk00000003/blk00000530/sig000015c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000564 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b30 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015af ), + .DPO(\blk00000003/blk00000530/sig000015c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk00000563 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b31 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ae ), + .DPO(\blk00000003/blk00000530/sig000015c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000562 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b32 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ad ), + .DPO(\blk00000003/blk00000530/sig000015bf ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000561 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b34 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ab ), + .DPO(\blk00000003/blk00000530/sig000015bd ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000560 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b35 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015aa ), + .DPO(\blk00000003/blk00000530/sig000015bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055f ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b33 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015ac ), + .DPO(\blk00000003/blk00000530/sig000015be ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055e ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b36 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a9 ), + .DPO(\blk00000003/blk00000530/sig000015bb ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000530/blk0000055d ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b37 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a8 ), + .DPO(\blk00000003/blk00000530/sig000015ba ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk0000055c ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b38 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a7 ), + .DPO(\blk00000003/blk00000530/sig000015b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk0000055b ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b39 ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a6 ), + .DPO(\blk00000003/blk00000530/sig000015b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk0000055a ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3a ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a5 ), + .DPO(\blk00000003/blk00000530/sig000015b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000559 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3b ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a4 ), + .DPO(\blk00000003/blk00000530/sig000015b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000530/blk00000558 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3d ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a2 ), + .DPO(\blk00000003/blk00000530/sig000015b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530/blk00000557 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3e ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a1 ), + .DPO(\blk00000003/blk00000530/sig000015b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000530/blk00000556 ( + .A0(\blk00000003/sig000009ec ), + .A1(\blk00000003/sig000009ed ), + .A2(\blk00000003/blk00000530/sig000015a0 ), + .A3(\blk00000003/blk00000530/sig000015a0 ), + .D(\blk00000003/sig00000b3c ), + .DPRA0(\blk00000003/sig00000a05 ), + .DPRA1(\blk00000003/sig00000a04 ), + .DPRA2(\blk00000003/blk00000530/sig000015a0 ), + .DPRA3(\blk00000003/blk00000530/sig000015a0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000530/sig000015c5 ), + .SPO(\blk00000003/blk00000530/sig000015a3 ), + .DPO(\blk00000003/blk00000530/sig000015b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c4 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c3 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c2 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c1 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015c0 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bf ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015be ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bd ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bc ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015bb ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ba ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b9 ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b8 ), + .Q(\blk00000003/sig00000630 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b7 ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b6 ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b5 ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b4 ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b3 ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b2 ), + .Q(\blk00000003/sig00000b3f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b1 ), + .Q(\blk00000003/sig00000b40 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015b0 ), + .Q(\blk00000003/sig00000b41 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015af ), + .Q(\blk00000003/sig00000b42 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ae ), + .Q(\blk00000003/sig00000b43 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ad ), + .Q(\blk00000003/sig00000b44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ac ), + .Q(\blk00000003/sig00000b45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015ab ), + .Q(\blk00000003/sig00000b46 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015aa ), + .Q(\blk00000003/sig00000b47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a9 ), + .Q(\blk00000003/sig00000b48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a8 ), + .Q(\blk00000003/sig00000b49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a7 ), + .Q(\blk00000003/sig00000b4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a6 ), + .Q(\blk00000003/sig00000b4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a5 ), + .Q(\blk00000003/sig00000b4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a4 ), + .Q(\blk00000003/sig00000b4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a3 ), + .Q(\blk00000003/sig00000b4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a2 ), + .Q(\blk00000003/sig00000b4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000530/sig000015a1 ), + .Q(\blk00000003/sig00000b50 ) + ); + GND \blk00000003/blk00000530/blk00000531 ( + .G(\blk00000003/blk00000530/sig000015a0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000569/blk000005a1 ( + .I0(\blk00000003/sig000009f5 ), + .I1(ce), + .O(\blk00000003/blk00000569/sig00001628 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk000005a0 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b3f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001615 ), + .DPO(\blk00000003/blk00000569/sig00001627 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b40 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001614 ), + .DPO(\blk00000003/blk00000569/sig00001626 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059e ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b41 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001613 ), + .DPO(\blk00000003/blk00000569/sig00001625 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059d ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b42 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001612 ), + .DPO(\blk00000003/blk00000569/sig00001624 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk0000059c ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b43 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001611 ), + .DPO(\blk00000003/blk00000569/sig00001623 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk0000059b ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b44 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001610 ), + .DPO(\blk00000003/blk00000569/sig00001622 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000059a ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b46 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160e ), + .DPO(\blk00000003/blk00000569/sig00001620 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000599 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b47 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160d ), + .DPO(\blk00000003/blk00000569/sig0000161f ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000598 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b45 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160f ), + .DPO(\blk00000003/blk00000569/sig00001621 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000597 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b48 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160c ), + .DPO(\blk00000003/blk00000569/sig0000161e ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000596 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b49 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160b ), + .DPO(\blk00000003/blk00000569/sig0000161d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000595 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4a ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig0000160a ), + .DPO(\blk00000003/blk00000569/sig0000161c ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000569/blk00000594 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4b ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001609 ), + .DPO(\blk00000003/blk00000569/sig0000161b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000593 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4c ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001608 ), + .DPO(\blk00000003/blk00000569/sig0000161a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk00000569/blk00000592 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4d ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001607 ), + .DPO(\blk00000003/blk00000569/sig00001619 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000569/blk00000591 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4f ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001605 ), + .DPO(\blk00000003/blk00000569/sig00001617 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk00000590 ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b50 ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001604 ), + .DPO(\blk00000003/blk00000569/sig00001616 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000569/blk0000058f ( + .A0(\blk00000003/sig000009ee ), + .A1(\blk00000003/sig000009ef ), + .A2(\blk00000003/blk00000569/sig00001603 ), + .A3(\blk00000003/blk00000569/sig00001603 ), + .D(\blk00000003/sig00000b4e ), + .DPRA0(\blk00000003/sig000009fd ), + .DPRA1(\blk00000003/sig000009fb ), + .DPRA2(\blk00000003/blk00000569/sig00001603 ), + .DPRA3(\blk00000003/blk00000569/sig00001603 ), + .WCLK(clk), + .WE(\blk00000003/blk00000569/sig00001628 ), + .SPO(\blk00000003/blk00000569/sig00001606 ), + .DPO(\blk00000003/blk00000569/sig00001618 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001627 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001626 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001625 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001624 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001623 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001622 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001621 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001620 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161f ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161e ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161d ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000582 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000161a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000580 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001619 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001618 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001617 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001616 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001615 ), + .Q(\blk00000003/sig00000b51 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001614 ), + .Q(\blk00000003/sig00000b52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000057a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001613 ), + .Q(\blk00000003/sig00000b53 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001612 ), + .Q(\blk00000003/sig00000b54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000578 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001611 ), + .Q(\blk00000003/sig00000b55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001610 ), + .Q(\blk00000003/sig00000b56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000576 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160f ), + .Q(\blk00000003/sig00000b57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160e ), + .Q(\blk00000003/sig00000b58 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000574 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160d ), + .Q(\blk00000003/sig00000b59 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160c ), + .Q(\blk00000003/sig00000b5a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000572 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160b ), + .Q(\blk00000003/sig00000b5b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig0000160a ), + .Q(\blk00000003/sig00000b5c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001609 ), + .Q(\blk00000003/sig00000b5d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001608 ), + .Q(\blk00000003/sig00000b5e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001607 ), + .Q(\blk00000003/sig00000b5f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001606 ), + .Q(\blk00000003/sig00000b60 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001605 ), + .Q(\blk00000003/sig00000b61 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000569/sig00001604 ), + .Q(\blk00000003/sig00000b62 ) + ); + GND \blk00000003/blk00000569/blk0000056a ( + .G(\blk00000003/blk00000569/sig00001603 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a2/blk000005c8 ( + .I0(\blk00000003/sig000009f6 ), + .I1(ce), + .O(\blk00000003/blk000005a2/sig00001667 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b51 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001666 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005c6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b52 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001665 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c5 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b53 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001664 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c4 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b54 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001663 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c3 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b55 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001662 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005c2 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b56 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001661 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005c1 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b58 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165f ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005c0 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b59 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005bf ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b57 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001660 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005be ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5a ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165d ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bd ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5b ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165c ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000005a2/blk000005bc ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5c ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165b ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005bb ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5d ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig0000165a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005ba ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5e ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001659 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005a2/blk000005b9 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b5f ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001658 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b8 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b61 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001656 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk000005a2/blk000005b7 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b62 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001655 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2/blk000005b6 ( + .A0(\blk00000003/sig000009f0 ), + .A1(\blk00000003/sig000009f1 ), + .A2(\blk00000003/blk000005a2/sig00001654 ), + .A3(\blk00000003/blk000005a2/sig00001654 ), + .D(\blk00000003/sig00000b60 ), + .DPRA0(\blk00000003/sig000009fe ), + .DPRA1(\blk00000003/sig000009fc ), + .DPRA2(\blk00000003/blk000005a2/sig00001654 ), + .DPRA3(\blk00000003/blk000005a2/sig00001654 ), + .WCLK(clk), + .WE(\blk00000003/blk000005a2/sig00001667 ), + .SPO(\NLW_blk00000003/blk000005a2/blk000005b6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000005a2/sig00001657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001666 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001665 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001664 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001663 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001662 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001661 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001660 ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165f ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165e ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165d ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165c ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165b ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig0000165a ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001659 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001658 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001657 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001656 ), + .Q(\blk00000003/sig000004fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a2/blk000005a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005a2/sig00001655 ), + .Q(\blk00000003/sig000004ff ) + ); + GND \blk00000003/blk000005a2/blk000005a3 ( + .G(\blk00000003/blk000005a2/sig00001654 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005c9/blk000005db ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005c9/sig00001685 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005da ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/blk000005c9/sig00001684 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/blk000005c9/sig00001683 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d8 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/blk000005c9/sig00001682 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d7 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk000005c9/sig00001681 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d6 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk000005c9/sig00001680 ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d5 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk000005c9/sig0000167f ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d4 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk000005c9/sig0000167e ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c9/blk000005d3 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005c9/sig0000167c ), + .A2(\blk00000003/blk000005c9/sig0000167c ), + .A3(\blk00000003/blk000005c9/sig0000167c ), + .CE(\blk00000003/blk000005c9/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk000005c9/sig0000167d ), + .Q15(\NLW_blk00000003/blk000005c9/blk000005d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001684 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001683 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001682 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001681 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig00001680 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167f ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167e ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005c9/sig0000167d ), + .Q(\blk00000003/sig000004ed ) + ); + GND \blk00000003/blk000005c9/blk000005ca ( + .G(\blk00000003/blk000005c9/sig0000167c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005dc/blk000005ee ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk000005dc/sig000016a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ed ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/blk000005dc/sig000016a2 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ed_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ec ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/blk000005dc/sig000016a1 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ec_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005eb ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/blk000005dc/sig000016a0 ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005eb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005ea ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/blk000005dc/sig0000169f ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e9 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/blk000005dc/sig0000169e ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e8 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/blk000005dc/sig0000169d ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e7 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/blk000005dc/sig0000169c ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc/blk000005e6 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk000005dc/sig0000169a ), + .A2(\blk00000003/blk000005dc/sig0000169a ), + .A3(\blk00000003/blk000005dc/sig0000169a ), + .CE(\blk00000003/blk000005dc/sig000016a3 ), + .CLK(clk), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/blk000005dc/sig0000169b ), + .Q15(\NLW_blk00000003/blk000005dc/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a2 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a1 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig000016a0 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169f ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169e ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169d ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169c ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dc/blk000005de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005dc/sig0000169b ), + .Q(\blk00000003/sig000004b5 ) + ); + GND \blk00000003/blk000005dc/blk000005dd ( + .G(\blk00000003/blk000005dc/sig0000169a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005ef/blk00000601 ( + .I0(\blk00000003/sig000009fa ), + .I1(ce), + .O(\blk00000003/blk000005ef/sig000016c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk00000600 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/blk000005ef/sig000016c0 ), + .Q15(\NLW_blk00000003/blk000005ef/blk00000600_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005ff ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/blk000005ef/sig000016bf ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fe ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/blk000005ef/sig000016be ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fd ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/blk000005ef/sig000016bd ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fc ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/blk000005ef/sig000016bc ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fb ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/blk000005ef/sig000016bb ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005fa ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/blk000005ef/sig000016ba ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ef/blk000005f9 ( + .A0(\blk00000003/sig00000a02 ), + .A1(\blk00000003/blk000005ef/sig000016b8 ), + .A2(\blk00000003/blk000005ef/sig000016b8 ), + .A3(\blk00000003/blk000005ef/sig000016b8 ), + .CE(\blk00000003/blk000005ef/sig000016c1 ), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/blk000005ef/sig000016b9 ), + .Q15(\NLW_blk00000003/blk000005ef/blk000005f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016c0 ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bf ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016be ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bd ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bc ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016bb ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016ba ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005ef/sig000016b9 ), + .Q(\blk00000003/sig0000053f ) + ); + GND \blk00000003/blk000005ef/blk000005f0 ( + .G(\blk00000003/blk000005ef/sig000016b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000602/blk00000614 ( + .I0(\blk00000003/sig000009f8 ), + .I1(ce), + .O(\blk00000003/blk00000602/sig000016df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000613 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/blk00000602/sig000016de ), + .Q15(\NLW_blk00000003/blk00000602/blk00000613_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000612 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/blk00000602/sig000016dd ), + .Q15(\NLW_blk00000003/blk00000602/blk00000612_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000611 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/blk00000602/sig000016dc ), + .Q15(\NLW_blk00000003/blk00000602/blk00000611_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk00000610 ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/blk00000602/sig000016db ), + .Q15(\NLW_blk00000003/blk00000602/blk00000610_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060f ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/blk00000602/sig000016da ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060e ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/blk00000602/sig000016d9 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060d ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/blk00000602/sig000016d8 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602/blk0000060c ( + .A0(\blk00000003/sig00000a00 ), + .A1(\blk00000003/blk00000602/sig000016d6 ), + .A2(\blk00000003/blk00000602/sig000016d6 ), + .A3(\blk00000003/blk00000602/sig000016d6 ), + .CE(\blk00000003/blk00000602/sig000016df ), + .CLK(clk), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/blk00000602/sig000016d7 ), + .Q15(\NLW_blk00000003/blk00000602/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016de ), + .Q(\blk00000003/sig00000500 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dd ), + .Q(\blk00000003/sig00000501 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016dc ), + .Q(\blk00000003/sig00000502 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016db ), + .Q(\blk00000003/sig00000503 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016da ), + .Q(\blk00000003/sig00000504 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d9 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d8 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000602/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000602/sig000016d7 ), + .Q(\blk00000003/sig00000507 ) + ); + GND \blk00000003/blk00000602/blk00000603 ( + .G(\blk00000003/blk00000602/sig000016d6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000615/blk00000627 ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk00000615/sig000016fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000626 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk00000615/sig000016fc ), + .Q15(\NLW_blk00000003/blk00000615/blk00000626_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000625 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk00000615/sig000016fb ), + .Q15(\NLW_blk00000003/blk00000615/blk00000625_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000624 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk00000615/sig000016fa ), + .Q15(\NLW_blk00000003/blk00000615/blk00000624_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000623 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk00000615/sig000016f9 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000623_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000622 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk00000615/sig000016f8 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000622_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000621 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk00000615/sig000016f7 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000621_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk00000620 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk00000615/sig000016f6 ), + .Q15(\NLW_blk00000003/blk00000615/blk00000620_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000615/blk0000061f ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk00000615/sig000016f4 ), + .A2(\blk00000003/blk00000615/sig000016f4 ), + .A3(\blk00000003/blk00000615/sig000016f4 ), + .CE(\blk00000003/blk00000615/sig000016fd ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk00000615/sig000016f5 ), + .Q15(\NLW_blk00000003/blk00000615/blk0000061f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fc ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fb ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016fa ), + .Q(\blk00000003/sig00000640 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f9 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk0000061a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f8 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f7 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000618 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f6 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000615/sig000016f5 ), + .Q(\blk00000003/sig00000645 ) + ); + GND \blk00000003/blk00000615/blk00000616 ( + .G(\blk00000003/blk00000615/sig000016f4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000628/blk0000063a ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk00000628/sig0000171b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000639 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/blk00000628/sig0000171a ), + .Q15(\NLW_blk00000003/blk00000628/blk00000639_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000638 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/blk00000628/sig00001719 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000638_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000637 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/blk00000628/sig00001718 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000637_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000636 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/blk00000628/sig00001717 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000636_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000635 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/blk00000628/sig00001716 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000635_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000634 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/blk00000628/sig00001715 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000634_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000633 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/blk00000628/sig00001714 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000633_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628/blk00000632 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk00000628/sig00001712 ), + .A2(\blk00000003/blk00000628/sig00001712 ), + .A3(\blk00000003/blk00000628/sig00001712 ), + .CE(\blk00000003/blk00000628/sig0000171b ), + .CLK(clk), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/blk00000628/sig00001713 ), + .Q15(\NLW_blk00000003/blk00000628/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig0000171a ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001719 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001718 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001717 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001716 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001715 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001714 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000628/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000628/sig00001713 ), + .Q(\blk00000003/sig0000063d ) + ); + GND \blk00000003/blk00000628/blk00000629 ( + .G(\blk00000003/blk00000628/sig00001712 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000063b/blk0000064d ( + .I0(\blk00000003/sig000009f9 ), + .I1(ce), + .O(\blk00000003/blk0000063b/sig00001739 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064c ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000063b/sig00001738 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064b ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000063b/sig00001737 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk0000064a ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000063b/sig00001736 ), + .Q15(\NLW_blk00000003/blk0000063b/blk0000064a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000649 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000063b/sig00001735 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000649_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000648 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000063b/sig00001734 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000648_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000647 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000063b/sig00001733 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000647_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000646 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000063b/sig00001732 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000646_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063b/blk00000645 ( + .A0(\blk00000003/sig00000a01 ), + .A1(\blk00000003/blk0000063b/sig00001730 ), + .A2(\blk00000003/blk0000063b/sig00001730 ), + .A3(\blk00000003/blk0000063b/sig00001730 ), + .CE(\blk00000003/blk0000063b/sig00001739 ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000063b/sig00001731 ), + .Q15(\NLW_blk00000003/blk0000063b/blk00000645_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001738 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001737 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001736 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001735 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001734 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001733 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001732 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000063b/sig00001731 ), + .Q(\blk00000003/sig00000727 ) + ); + GND \blk00000003/blk0000063b/blk0000063c ( + .G(\blk00000003/blk0000063b/sig00001730 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000064e/blk00000660 ( + .I0(\blk00000003/sig000009f7 ), + .I1(ce), + .O(\blk00000003/blk0000064e/sig00001757 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065f ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/blk0000064e/sig00001756 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065e ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/blk0000064e/sig00001755 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065d ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/blk0000064e/sig00001754 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065c ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/blk0000064e/sig00001753 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065b ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/blk0000064e/sig00001752 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk0000065a ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/blk0000064e/sig00001751 ), + .Q15(\NLW_blk00000003/blk0000064e/blk0000065a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000659 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/blk0000064e/sig00001750 ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000659_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e/blk00000658 ( + .A0(\blk00000003/sig000009ff ), + .A1(\blk00000003/blk0000064e/sig0000174e ), + .A2(\blk00000003/blk0000064e/sig0000174e ), + .A3(\blk00000003/blk0000064e/sig0000174e ), + .CE(\blk00000003/blk0000064e/sig00001757 ), + .CLK(clk), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/blk0000064e/sig0000174f ), + .Q15(\NLW_blk00000003/blk0000064e/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001756 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000656 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001755 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001754 ), + .Q(\blk00000003/sig0000071a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000654 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001753 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001752 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000652 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001751 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig00001750 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064e/blk00000650 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000064e/sig0000174f ), + .Q(\blk00000003/sig0000071f ) + ); + GND \blk00000003/blk0000064e/blk0000064f ( + .G(\blk00000003/blk0000064e/sig0000174e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000661/blk00000673 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000661/sig00001775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000672 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000661/sig00001774 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000672_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000671 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000661/sig00001773 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000671_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk00000670 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000661/sig00001772 ), + .Q15(\NLW_blk00000003/blk00000661/blk00000670_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066f ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000661/sig00001771 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066e ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000661/sig00001770 ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066d ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000661/sig0000176f ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066c ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000661/sig0000176e ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000661/blk0000066b ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000661/sig0000176c ), + .A2(\blk00000003/blk00000661/sig0000176c ), + .A3(\blk00000003/blk00000661/sig0000176c ), + .CE(\blk00000003/blk00000661/sig00001775 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000661/sig0000176d ), + .Q15(\NLW_blk00000003/blk00000661/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001774 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001773 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001772 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001771 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig00001770 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176f ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176e ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000661/sig0000176d ), + .Q(\blk00000003/sig000005f3 ) + ); + GND \blk00000003/blk00000661/blk00000662 ( + .G(\blk00000003/blk00000661/sig0000176c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000674/blk00000686 ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk00000674/sig00001793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000685 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/blk00000674/sig00001792 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000685_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000684 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/blk00000674/sig00001791 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000684_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000683 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/blk00000674/sig00001790 ), + .Q15(\NLW_blk00000003/blk00000674/blk00000683_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000682 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/blk00000674/sig0000178f ), + .Q15(\NLW_blk00000003/blk00000674/blk00000682_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000681 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/blk00000674/sig0000178e ), + .Q15(\NLW_blk00000003/blk00000674/blk00000681_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk00000680 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/blk00000674/sig0000178d ), + .Q15(\NLW_blk00000003/blk00000674/blk00000680_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067f ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/blk00000674/sig0000178c ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674/blk0000067e ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk00000674/sig0000178a ), + .A2(\blk00000003/blk00000674/sig0000178a ), + .A3(\blk00000003/blk00000674/sig0000178a ), + .CE(\blk00000003/blk00000674/sig00001793 ), + .CLK(clk), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/blk00000674/sig0000178b ), + .Q15(\NLW_blk00000003/blk00000674/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001792 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001791 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig00001790 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000674/sig0000178b ), + .Q(\blk00000003/sig000005eb ) + ); + GND \blk00000003/blk00000674/blk00000675 ( + .G(\blk00000003/blk00000674/sig0000178a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000687/blk00000699 ( + .I0(\blk00000003/sig00000a06 ), + .I1(ce), + .O(\blk00000003/blk00000687/sig000017b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000698 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000687/sig000017b0 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000698_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000697 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000687/sig000017af ), + .Q15(\NLW_blk00000003/blk00000687/blk00000697_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000696 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000687/sig000017ae ), + .Q15(\NLW_blk00000003/blk00000687/blk00000696_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000695 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000687/sig000017ad ), + .Q15(\NLW_blk00000003/blk00000687/blk00000695_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000694 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000687/sig000017ac ), + .Q15(\NLW_blk00000003/blk00000687/blk00000694_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000693 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000687/sig000017ab ), + .Q15(\NLW_blk00000003/blk00000687/blk00000693_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000692 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000687/sig000017aa ), + .Q15(\NLW_blk00000003/blk00000687/blk00000692_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687/blk00000691 ( + .A0(\blk00000003/sig00000a08 ), + .A1(\blk00000003/blk00000687/sig000017a8 ), + .A2(\blk00000003/blk00000687/sig000017a8 ), + .A3(\blk00000003/blk00000687/sig000017a8 ), + .CE(\blk00000003/blk00000687/sig000017b1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000687/sig000017a9 ), + .Q15(\NLW_blk00000003/blk00000687/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017b0 ), + .Q(\blk00000003/sig000006e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017af ), + .Q(\blk00000003/sig000006e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ae ), + .Q(\blk00000003/sig000006e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ad ), + .Q(\blk00000003/sig000006e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ac ), + .Q(\blk00000003/sig000006e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017ab ), + .Q(\blk00000003/sig000006e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017aa ), + .Q(\blk00000003/sig000006e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000687/sig000017a9 ), + .Q(\blk00000003/sig000006e7 ) + ); + GND \blk00000003/blk00000687/blk00000688 ( + .G(\blk00000003/blk00000687/sig000017a8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000069a/blk000006ac ( + .I0(\blk00000003/sig00000a03 ), + .I1(ce), + .O(\blk00000003/blk0000069a/sig000017cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006ab ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/blk0000069a/sig000017ce ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006aa ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/blk0000069a/sig000017cd ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a9 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/blk0000069a/sig000017cc ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a8 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/blk0000069a/sig000017cb ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a7 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b8f ), + .Q(\blk00000003/blk0000069a/sig000017ca ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a6 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b90 ), + .Q(\blk00000003/blk0000069a/sig000017c9 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a5 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b91 ), + .Q(\blk00000003/blk0000069a/sig000017c8 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a/blk000006a4 ( + .A0(\blk00000003/sig00000a07 ), + .A1(\blk00000003/blk0000069a/sig000017c6 ), + .A2(\blk00000003/blk0000069a/sig000017c6 ), + .A3(\blk00000003/blk0000069a/sig000017c6 ), + .CE(\blk00000003/blk0000069a/sig000017cf ), + .CLK(clk), + .D(\blk00000003/sig00000b92 ), + .Q(\blk00000003/blk0000069a/sig000017c7 ), + .Q15(\NLW_blk00000003/blk0000069a/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ce ), + .Q(\blk00000003/sig000006d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cd ), + .Q(\blk00000003/sig000006d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cc ), + .Q(\blk00000003/sig000006da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017cb ), + .Q(\blk00000003/sig000006db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017ca ), + .Q(\blk00000003/sig000006dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c9 ), + .Q(\blk00000003/sig000006dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c8 ), + .Q(\blk00000003/sig000006de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000069a/sig000017c7 ), + .Q(\blk00000003/sig000006df ) + ); + GND \blk00000003/blk0000069a/blk0000069b ( + .G(\blk00000003/blk0000069a/sig000017c6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006ad/blk000006bf ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006ad/sig000017ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006be ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000006ad/sig000017ec ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000006ad/sig000017eb ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bc ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000006ad/sig000017ea ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006bb ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000006ad/sig000017e9 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006ba ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000006ad/sig000017e8 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b9 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000006ad/sig000017e7 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b8 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000006ad/sig000017e6 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad/blk000006b7 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006ad/sig000017e4 ), + .A2(\blk00000003/blk000006ad/sig000017e4 ), + .A3(\blk00000003/blk000006ad/sig000017e4 ), + .CE(\blk00000003/blk000006ad/sig000017ed ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000006ad/sig000017e5 ), + .Q15(\NLW_blk00000003/blk000006ad/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ec ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017eb ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017ea ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e9 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e8 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e7 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e6 ), + .Q(\blk00000003/sig000005a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006ad/sig000017e5 ), + .Q(\blk00000003/sig000005a1 ) + ); + GND \blk00000003/blk000006ad/blk000006ae ( + .G(\blk00000003/blk000006ad/sig000017e4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006c0/blk000006d2 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006c0/sig0000180b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b93 ), + .Q(\blk00000003/blk000006c0/sig0000180a ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006d0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b94 ), + .Q(\blk00000003/blk000006c0/sig00001809 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cf ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b95 ), + .Q(\blk00000003/blk000006c0/sig00001808 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ce ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b96 ), + .Q(\blk00000003/blk000006c0/sig00001807 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cd ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b97 ), + .Q(\blk00000003/blk000006c0/sig00001806 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cc ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b98 ), + .Q(\blk00000003/blk000006c0/sig00001805 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006cb ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b99 ), + .Q(\blk00000003/blk000006c0/sig00001804 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0/blk000006ca ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006c0/sig00001802 ), + .A2(\blk00000003/blk000006c0/sig00001802 ), + .A3(\blk00000003/blk000006c0/sig00001802 ), + .CE(\blk00000003/blk000006c0/sig0000180b ), + .CLK(clk), + .D(\blk00000003/sig00000b9a ), + .Q(\blk00000003/blk000006c0/sig00001803 ), + .Q15(\NLW_blk00000003/blk000006c0/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig0000180a ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001809 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001808 ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001807 ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001806 ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001805 ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001804 ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006c0/sig00001803 ), + .Q(\blk00000003/sig00000599 ) + ); + GND \blk00000003/blk000006c0/blk000006c1 ( + .G(\blk00000003/blk000006c0/sig00001802 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006d3/blk000006e5 ( + .I0(\blk00000003/sig00000a09 ), + .I1(ce), + .O(\blk00000003/blk000006d3/sig00001829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e4 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/blk000006d3/sig00001828 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e3 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk000006d3/sig00001827 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e2 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk000006d3/sig00001826 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e1 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk000006d3/sig00001825 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006e0 ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk000006d3/sig00001824 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006df ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk000006d3/sig00001823 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006de ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk000006d3/sig00001822 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3/blk000006dd ( + .A0(\blk00000003/sig00000a0e ), + .A1(\blk00000003/blk000006d3/sig00001820 ), + .A2(\blk00000003/blk000006d3/sig00001820 ), + .A3(\blk00000003/blk000006d3/sig00001820 ), + .CE(\blk00000003/blk000006d3/sig00001829 ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk000006d3/sig00001821 ), + .Q15(\NLW_blk00000003/blk000006d3/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001828 ), + .Q(\blk00000003/sig000006a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001827 ), + .Q(\blk00000003/sig000006a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001826 ), + .Q(\blk00000003/sig000006a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001825 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001824 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001823 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001822 ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006d3/sig00001821 ), + .Q(\blk00000003/sig000006a7 ) + ); + GND \blk00000003/blk000006d3/blk000006d4 ( + .G(\blk00000003/blk000006d3/sig00001820 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006e6/blk000006f8 ( + .I0(\blk00000003/sig00000a0a ), + .I1(ce), + .O(\blk00000003/blk000006e6/sig00001847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f7 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9b ), + .Q(\blk00000003/blk000006e6/sig00001846 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f6 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9c ), + .Q(\blk00000003/blk000006e6/sig00001845 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f5 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9d ), + .Q(\blk00000003/blk000006e6/sig00001844 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f4 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9e ), + .Q(\blk00000003/blk000006e6/sig00001843 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f3 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000b9f ), + .Q(\blk00000003/blk000006e6/sig00001842 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f2 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba0 ), + .Q(\blk00000003/blk000006e6/sig00001841 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f1 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba1 ), + .Q(\blk00000003/blk000006e6/sig00001840 ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6/blk000006f0 ( + .A0(\blk00000003/sig00000a0d ), + .A1(\blk00000003/blk000006e6/sig0000183e ), + .A2(\blk00000003/blk000006e6/sig0000183e ), + .A3(\blk00000003/blk000006e6/sig0000183e ), + .CE(\blk00000003/blk000006e6/sig00001847 ), + .CLK(clk), + .D(\blk00000003/sig00000ba2 ), + .Q(\blk00000003/blk000006e6/sig0000183f ), + .Q15(\NLW_blk00000003/blk000006e6/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001846 ), + .Q(\blk00000003/sig00000698 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001845 ), + .Q(\blk00000003/sig00000699 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001844 ), + .Q(\blk00000003/sig0000069a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001843 ), + .Q(\blk00000003/sig0000069b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001842 ), + .Q(\blk00000003/sig0000069c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001841 ), + .Q(\blk00000003/sig0000069d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig00001840 ), + .Q(\blk00000003/sig0000069e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006e6/sig0000183f ), + .Q(\blk00000003/sig0000069f ) + ); + GND \blk00000003/blk000006e6/blk000006e7 ( + .G(\blk00000003/blk000006e6/sig0000183e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006f9/blk0000070b ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk000006f9/sig00001865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk0000070a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000384 ), + .Q(\blk00000003/blk000006f9/sig00001864 ), + .Q15(\NLW_blk00000003/blk000006f9/blk0000070a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000709 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000385 ), + .Q(\blk00000003/blk000006f9/sig00001863 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000709_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000708 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000386 ), + .Q(\blk00000003/blk000006f9/sig00001862 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000708_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000707 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000387 ), + .Q(\blk00000003/blk000006f9/sig00001861 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000707_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000706 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000388 ), + .Q(\blk00000003/blk000006f9/sig00001860 ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000706_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000705 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig00000389 ), + .Q(\blk00000003/blk000006f9/sig0000185f ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000705_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000704 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038a ), + .Q(\blk00000003/blk000006f9/sig0000185e ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000704_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9/blk00000703 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk000006f9/sig0000185c ), + .A2(\blk00000003/blk000006f9/sig0000185c ), + .A3(\blk00000003/blk000006f9/sig0000185c ), + .CE(\blk00000003/blk000006f9/sig00001865 ), + .CLK(clk), + .D(\blk00000003/sig0000038b ), + .Q(\blk00000003/blk000006f9/sig0000185d ), + .Q15(\NLW_blk00000003/blk000006f9/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000702 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001864 ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000701 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001863 ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk00000700 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001862 ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001861 ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig00001860 ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185f ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185e ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9/blk000006fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006f9/sig0000185d ), + .Q(\blk00000003/sig0000054f ) + ); + GND \blk00000003/blk000006f9/blk000006fa ( + .G(\blk00000003/blk000006f9/sig0000185c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000070c/blk0000071e ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk0000070c/sig00001883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba3 ), + .Q(\blk00000003/blk0000070c/sig00001882 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba4 ), + .Q(\blk00000003/blk0000070c/sig00001881 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071b ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba5 ), + .Q(\blk00000003/blk0000070c/sig00001880 ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk0000071a ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba6 ), + .Q(\blk00000003/blk0000070c/sig0000187f ), + .Q15(\NLW_blk00000003/blk0000070c/blk0000071a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000719 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba7 ), + .Q(\blk00000003/blk0000070c/sig0000187e ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000719_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000718 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba8 ), + .Q(\blk00000003/blk0000070c/sig0000187d ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000718_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000717 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000ba9 ), + .Q(\blk00000003/blk0000070c/sig0000187c ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000717_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c/blk00000716 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk0000070c/sig0000187a ), + .A2(\blk00000003/blk0000070c/sig0000187a ), + .A3(\blk00000003/blk0000070c/sig0000187a ), + .CE(\blk00000003/blk0000070c/sig00001883 ), + .CLK(clk), + .D(\blk00000003/sig00000baa ), + .Q(\blk00000003/blk0000070c/sig0000187b ), + .Q15(\NLW_blk00000003/blk0000070c/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001882 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001881 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig00001880 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187f ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187e ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187d ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187c ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000070c/sig0000187b ), + .Q(\blk00000003/sig00000547 ) + ); + GND \blk00000003/blk0000070c/blk0000070d ( + .G(\blk00000003/blk0000070c/sig0000187a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000071f/blk00000731 ( + .I0(\blk00000003/sig00000a10 ), + .I1(ce), + .O(\blk00000003/blk0000071f/sig000018a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000730 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d6 ), + .Q(\blk00000003/blk0000071f/sig000018a0 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000730_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072f ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d7 ), + .Q(\blk00000003/blk0000071f/sig0000189f ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072e ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d8 ), + .Q(\blk00000003/blk0000071f/sig0000189e ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072d ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003d9 ), + .Q(\blk00000003/blk0000071f/sig0000189d ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072c ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003da ), + .Q(\blk00000003/blk0000071f/sig0000189c ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072b ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003db ), + .Q(\blk00000003/blk0000071f/sig0000189b ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk0000072a ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dc ), + .Q(\blk00000003/blk0000071f/sig0000189a ), + .Q15(\NLW_blk00000003/blk0000071f/blk0000072a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f/blk00000729 ( + .A0(\blk00000003/sig00000a13 ), + .A1(\blk00000003/blk0000071f/sig00001898 ), + .A2(\blk00000003/blk0000071f/sig00001898 ), + .A3(\blk00000003/blk0000071f/sig00001898 ), + .CE(\blk00000003/blk0000071f/sig000018a1 ), + .CLK(clk), + .D(\blk00000003/sig000003dd ), + .Q(\blk00000003/blk0000071f/sig00001899 ), + .Q15(\NLW_blk00000003/blk0000071f/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000728 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig000018a0 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189f ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000726 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189e ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189d ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000724 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189c ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189b ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000722 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig0000189a ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000071f/sig00001899 ), + .Q(\blk00000003/sig00000667 ) + ); + GND \blk00000003/blk0000071f/blk00000720 ( + .G(\blk00000003/blk0000071f/sig00001898 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000732/blk00000744 ( + .I0(\blk00000003/sig00000a0f ), + .I1(ce), + .O(\blk00000003/blk00000732/sig000018bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000743 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bab ), + .Q(\blk00000003/blk00000732/sig000018be ), + .Q15(\NLW_blk00000003/blk00000732/blk00000743_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000742 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bac ), + .Q(\blk00000003/blk00000732/sig000018bd ), + .Q15(\NLW_blk00000003/blk00000732/blk00000742_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000741 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bad ), + .Q(\blk00000003/blk00000732/sig000018bc ), + .Q15(\NLW_blk00000003/blk00000732/blk00000741_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk00000740 ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bae ), + .Q(\blk00000003/blk00000732/sig000018bb ), + .Q15(\NLW_blk00000003/blk00000732/blk00000740_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073f ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000baf ), + .Q(\blk00000003/blk00000732/sig000018ba ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073e ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb0 ), + .Q(\blk00000003/blk00000732/sig000018b9 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073d ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb1 ), + .Q(\blk00000003/blk00000732/sig000018b8 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732/blk0000073c ( + .A0(\blk00000003/sig00000a14 ), + .A1(\blk00000003/blk00000732/sig000018b6 ), + .A2(\blk00000003/blk00000732/sig000018b6 ), + .A3(\blk00000003/blk00000732/sig000018b6 ), + .CE(\blk00000003/blk00000732/sig000018bf ), + .CLK(clk), + .D(\blk00000003/sig00000bb2 ), + .Q(\blk00000003/blk00000732/sig000018b7 ), + .Q15(\NLW_blk00000003/blk00000732/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018be ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk0000073a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bd ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bc ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000738 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018bb ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018ba ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000736 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b9 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b8 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732/blk00000734 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000732/sig000018b7 ), + .Q(\blk00000003/sig0000065f ) + ); + GND \blk00000003/blk00000732/blk00000733 ( + .G(\blk00000003/blk00000732/sig000018b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000745/blk00000757 ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk00000745/sig000018dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000756 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb3 ), + .Q(\blk00000003/blk00000745/sig000018dc ), + .Q15(\NLW_blk00000003/blk00000745/blk00000756_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000755 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb4 ), + .Q(\blk00000003/blk00000745/sig000018db ), + .Q15(\NLW_blk00000003/blk00000745/blk00000755_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000754 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb5 ), + .Q(\blk00000003/blk00000745/sig000018da ), + .Q15(\NLW_blk00000003/blk00000745/blk00000754_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000753 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb6 ), + .Q(\blk00000003/blk00000745/sig000018d9 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000753_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000752 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb7 ), + .Q(\blk00000003/blk00000745/sig000018d8 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000752_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000751 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb8 ), + .Q(\blk00000003/blk00000745/sig000018d7 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000751_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk00000750 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bb9 ), + .Q(\blk00000003/blk00000745/sig000018d6 ), + .Q15(\NLW_blk00000003/blk00000745/blk00000750_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745/blk0000074f ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk00000745/sig000018d4 ), + .A2(\blk00000003/blk00000745/sig000018d4 ), + .A3(\blk00000003/blk00000745/sig000018d4 ), + .CE(\blk00000003/blk00000745/sig000018dd ), + .CLK(clk), + .D(\blk00000003/sig00000bba ), + .Q(\blk00000003/blk00000745/sig000018d5 ), + .Q15(\NLW_blk00000003/blk00000745/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018dc ), + .Q(\blk00000003/sig00000384 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018db ), + .Q(\blk00000003/sig00000385 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018da ), + .Q(\blk00000003/sig00000386 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d9 ), + .Q(\blk00000003/sig00000387 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk0000074a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d8 ), + .Q(\blk00000003/sig00000388 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d7 ), + .Q(\blk00000003/sig00000389 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000748 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d6 ), + .Q(\blk00000003/sig0000038a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000745/sig000018d5 ), + .Q(\blk00000003/sig0000038b ) + ); + GND \blk00000003/blk00000745/blk00000746 ( + .G(\blk00000003/blk00000745/sig000018d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000758/blk0000076a ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk00000758/sig000018fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000769 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbb ), + .Q(\blk00000003/blk00000758/sig000018fa ), + .Q15(\NLW_blk00000003/blk00000758/blk00000769_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000768 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbc ), + .Q(\blk00000003/blk00000758/sig000018f9 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000768_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000767 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbd ), + .Q(\blk00000003/blk00000758/sig000018f8 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000767_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000766 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbe ), + .Q(\blk00000003/blk00000758/sig000018f7 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000766_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000765 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bbf ), + .Q(\blk00000003/blk00000758/sig000018f6 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000765_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000764 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc0 ), + .Q(\blk00000003/blk00000758/sig000018f5 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000764_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000763 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc1 ), + .Q(\blk00000003/blk00000758/sig000018f4 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000763_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758/blk00000762 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk00000758/sig000018f2 ), + .A2(\blk00000003/blk00000758/sig000018f2 ), + .A3(\blk00000003/blk00000758/sig000018f2 ), + .CE(\blk00000003/blk00000758/sig000018fb ), + .CLK(clk), + .D(\blk00000003/sig00000bc2 ), + .Q(\blk00000003/blk00000758/sig000018f3 ), + .Q15(\NLW_blk00000003/blk00000758/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018fa ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f9 ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f8 ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f7 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f6 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f5 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f4 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000758/sig000018f3 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk00000758/blk00000759 ( + .G(\blk00000003/blk00000758/sig000018f2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000076b/blk0000077d ( + .I0(\blk00000003/sig00000a16 ), + .I1(ce), + .O(\blk00000003/blk0000076b/sig00001919 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077c ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc3 ), + .Q(\blk00000003/blk0000076b/sig00001918 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077b ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc4 ), + .Q(\blk00000003/blk0000076b/sig00001917 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk0000077a ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc5 ), + .Q(\blk00000003/blk0000076b/sig00001916 ), + .Q15(\NLW_blk00000003/blk0000076b/blk0000077a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000779 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc6 ), + .Q(\blk00000003/blk0000076b/sig00001915 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000779_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000778 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc7 ), + .Q(\blk00000003/blk0000076b/sig00001914 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000778_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000777 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc8 ), + .Q(\blk00000003/blk0000076b/sig00001913 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000777_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000776 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bc9 ), + .Q(\blk00000003/blk0000076b/sig00001912 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000776_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b/blk00000775 ( + .A0(\blk00000003/sig0000036f ), + .A1(\blk00000003/blk0000076b/sig00001910 ), + .A2(\blk00000003/blk0000076b/sig00001910 ), + .A3(\blk00000003/blk0000076b/sig00001910 ), + .CE(\blk00000003/blk0000076b/sig00001919 ), + .CLK(clk), + .D(\blk00000003/sig00000bca ), + .Q(\blk00000003/blk0000076b/sig00001911 ), + .Q15(\NLW_blk00000003/blk0000076b/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001918 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001917 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001916 ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001915 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001914 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001913 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001912 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000076b/sig00001911 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk0000076b/blk0000076c ( + .G(\blk00000003/blk0000076b/sig00001910 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000077e/blk00000790 ( + .I0(\blk00000003/sig00000a15 ), + .I1(ce), + .O(\blk00000003/blk0000077e/sig00001937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078f ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcb ), + .Q(\blk00000003/blk0000077e/sig00001936 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078e ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcc ), + .Q(\blk00000003/blk0000077e/sig00001935 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078d ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcd ), + .Q(\blk00000003/blk0000077e/sig00001934 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078c ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bce ), + .Q(\blk00000003/blk0000077e/sig00001933 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078b ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bcf ), + .Q(\blk00000003/blk0000077e/sig00001932 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk0000078a ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd0 ), + .Q(\blk00000003/blk0000077e/sig00001931 ), + .Q15(\NLW_blk00000003/blk0000077e/blk0000078a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000789 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd1 ), + .Q(\blk00000003/blk0000077e/sig00001930 ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000789_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e/blk00000788 ( + .A0(\blk00000003/sig0000036a ), + .A1(\blk00000003/blk0000077e/sig0000192e ), + .A2(\blk00000003/blk0000077e/sig0000192e ), + .A3(\blk00000003/blk0000077e/sig0000192e ), + .CE(\blk00000003/blk0000077e/sig00001937 ), + .CLK(clk), + .D(\blk00000003/sig00000bd2 ), + .Q(\blk00000003/blk0000077e/sig0000192f ), + .Q15(\NLW_blk00000003/blk0000077e/blk00000788_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000787 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001936 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001935 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000785 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001934 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001933 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001932 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001931 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig00001930 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000077e/sig0000192f ), + .Q(\blk00000003/sig000003d5 ) + ); + GND \blk00000003/blk0000077e/blk0000077f ( + .G(\blk00000003/blk0000077e/sig0000192e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000007c1/blk000007e7 ( + .I0(\blk00000003/sig0000030a ), + .I1(ce), + .O(\blk00000003/blk000007c1/sig00001974 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1/blk000007e6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af7 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001973 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af8 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001972 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e4 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000af9 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001971 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e3 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afa ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001970 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e2 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afb ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e1 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afc ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007e0 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afe ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007e0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007df ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000aff ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007df_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007de ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000afd ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007de_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dd ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b00 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig0000196a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007dc ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b01 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007dc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001969 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007db ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b02 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007db_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001968 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007da ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b03 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007da_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001967 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d9 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b04 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001966 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d8 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b05 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001965 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d7 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b07 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001963 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d6 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b08 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001962 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000007c1/blk000007d5 ( + .A0(\blk00000003/sig00000311 ), + .A1(\blk00000003/blk000007c1/sig00001961 ), + .A2(\blk00000003/blk000007c1/sig00001961 ), + .A3(\blk00000003/blk000007c1/sig00001961 ), + .D(\blk00000003/sig00000b06 ), + .DPRA0(\blk00000003/sig00000bd5 ), + .DPRA1(\blk00000003/blk000007c1/sig00001961 ), + .DPRA2(\blk00000003/blk000007c1/sig00001961 ), + .DPRA3(\blk00000003/blk000007c1/sig00001961 ), + .WCLK(clk), + .WE(\blk00000003/blk000007c1/sig00001974 ), + .SPO(\NLW_blk00000003/blk000007c1/blk000007d5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000007c1/sig00001964 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001973 ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001972 ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001971 ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001970 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196f ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196e ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196d ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196c ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196b ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig0000196a ), + .Q(\blk00000003/sig000001b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001969 ), + .Q(\blk00000003/sig000001ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001968 ), + .Q(\blk00000003/sig000001bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001967 ), + .Q(\blk00000003/sig000001bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001966 ), + .Q(\blk00000003/sig000001bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001965 ), + .Q(\blk00000003/sig000001be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001964 ), + .Q(\blk00000003/sig000001bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001963 ), + .Q(\blk00000003/sig000001c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000007c1/sig00001962 ), + .Q(\blk00000003/sig000001c1 ) + ); + GND \blk00000003/blk000007c1/blk000007c2 ( + .G(\blk00000003/blk000007c1/sig00001961 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.veo b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.veo new file mode 100644 index 000000000..eb615e1ee --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec1 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec1.v when simulating +// the core, hbdec1. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.xco b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.xco new file mode 100644 index 000000000..5d6c03565 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jun 9 23:47:19 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=7 +CSET component_name=hbdec1 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=64 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-10-13T18:46:09Z +# END Extra information +GENERATE +# CRC: c82a9824 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_0.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_0.mif new file mode 100644 index 000000000..f19636daf --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_0.mif @@ -0,0 +1,5 @@ +111111111111000010 +000000000011000010 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_1.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_1.mif new file mode 100644 index 000000000..07e316dd3 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_1.mif @@ -0,0 +1,5 @@ +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_2.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_2.mif new file mode 100644 index 000000000..da84300d6 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_2.mif @@ -0,0 +1,5 @@ +111111101000011111 +000000100110101110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_3.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_3.mif new file mode 100644 index 000000000..ea92ca6c2 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_3.mif @@ -0,0 +1,5 @@ +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_4.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_4.mif new file mode 100644 index 000000000..9e9303211 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_4.mif @@ -0,0 +1,5 @@ +111101110000011101 +000011100100101000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_5.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_5.mif new file mode 100644 index 000000000..e0c3f05fe --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto0_5.mif @@ -0,0 +1,5 @@ +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_flist.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_flist.txt new file mode 100644 index 000000000..2bd535f92 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_flist.txt @@ -0,0 +1,22 @@ +# Output products list for +hbdec1.asy +hbdec1.gise +hbdec1.mif +hbdec1.ngc +hbdec1.v +hbdec1.veo +hbdec1.xco +hbdec1.xise +hbdec1COEFF_auto0_0.mif +hbdec1COEFF_auto0_1.mif +hbdec1COEFF_auto0_2.mif +hbdec1COEFF_auto0_3.mif +hbdec1COEFF_auto0_4.mif +hbdec1COEFF_auto0_5.mif +hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +hbdec1_flist.txt +hbdec1_readme.txt +hbdec1_reload_addrfilt_decode_rom.mif +hbdec1_reload_order.txt +hbdec1_xmdf.tcl +hbdec1filt_decode_rom.mif diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_readme.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_readme.txt new file mode 100644 index 000000000..7a62ed177 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_readme.txt @@ -0,0 +1,76 @@ +The following files were generated for 'hbdec1' in directory +/home/mwest/git/fpgadev/usrp3/top/b205/coregen_dsp/ + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec1_flist.txt + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec1.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec1.ngc + * hbdec1.v + * hbdec1.veo + * hbdec1COEFF_auto0_0.mif + * hbdec1COEFF_auto0_1.mif + * hbdec1COEFF_auto0_2.mif + * hbdec1COEFF_auto0_3.mif + * hbdec1COEFF_auto0_4.mif + * hbdec1COEFF_auto0_5.mif + * hbdec1COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec1_reload_addrfilt_decode_rom.mif + * hbdec1filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec1.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec1.asy + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec1_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec1.gise + * hbdec1.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec1_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec1_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_order.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_order.txt new file mode 100644 index 000000000..11f12084f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 20 +Reload index 1 = Index 22 +Reload index 2 = Index 16 +Reload index 3 = Index 18 +Reload index 4 = Index 12 +Reload index 5 = Index 14 +Reload index 6 = Index 8 +Reload index 7 = Index 10 +Reload index 8 = Index 4 +Reload index 9 = Index 6 +Reload index 10 = Index 0 +Reload index 11 = Index 2 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_xmdf.tcl new file mode 100644 index 000000000..7aa8f91c3 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1_xmdf.tcl @@ -0,0 +1,111 @@ +# The package naming convention is _xmdf +package provide hbdec1_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec1_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec1_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1 +} +# ::hbdec1_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec1_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1filt_decode_rom.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1filt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec1filt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.asy b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.asy new file mode 100644 index 000000000..e9bd5ec37 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec2 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..839be66eb --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$37:2~753-Xnzd}foo8#5+421).97 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\ No newline at end of file diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.v b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.v new file mode 100644 index 000000000..5d7fb7317 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.v @@ -0,0 +1,27912 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.20131013 +// \ \ Application: netgen +// / / Filename: hbdec2.v +// /___/ /\ Timestamp: Tue Jun 9 16:48:59 2015 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec2.ngc ./tmp/_cg/hbdec2.v +// Device : 6slx75fgg484-3 +// Input file : ./tmp/_cg/hbdec2.ngc +// Output file : ./tmp/_cg/hbdec2.v +// # of Modules : 1 +// Design Name : hbdec2 +// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec2 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig0000093c ; + wire \blk00000003/sig0000093b ; + wire \blk00000003/sig0000093a ; + wire \blk00000003/sig00000939 ; + wire \blk00000003/sig00000938 ; + wire \blk00000003/sig00000937 ; + wire \blk00000003/sig00000936 ; + wire \blk00000003/sig00000935 ; + wire \blk00000003/sig00000934 ; + wire \blk00000003/sig00000933 ; + wire \blk00000003/sig00000932 ; + wire \blk00000003/sig00000931 ; + wire \blk00000003/sig00000930 ; + wire \blk00000003/sig0000092f ; + wire \blk00000003/sig0000092e ; + wire \blk00000003/sig0000092d ; + wire \blk00000003/sig0000092c ; + wire \blk00000003/sig0000092b ; + wire \blk00000003/sig0000092a ; + wire \blk00000003/sig00000929 ; + wire \blk00000003/sig00000928 ; + wire \blk00000003/sig00000927 ; + wire \blk00000003/sig00000926 ; + wire \blk00000003/sig00000925 ; + wire \blk00000003/sig00000924 ; + wire \blk00000003/sig00000923 ; + wire \blk00000003/sig00000922 ; + wire \blk00000003/sig00000921 ; + wire \blk00000003/sig00000920 ; + wire \blk00000003/sig0000091f ; + wire \blk00000003/sig0000091e ; + wire \blk00000003/sig0000091d ; + wire \blk00000003/sig0000091c ; + wire \blk00000003/sig0000091b ; + wire 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\NLW_blk00000003/blk00000781_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000077b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000779_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000777_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000775_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000773_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000771_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000076b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000769_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000767_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000765_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000763_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000761_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000759_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000757_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000755_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000753_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000751_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000074f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000074d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000074b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000749_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000747_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000745_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000743_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000741_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000073f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000073d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000073b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000739_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000737_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000735_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000733_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000731_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000072f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000072d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000072b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000729_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000727_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000725_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000723_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000721_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000071b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000719_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000717_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000715_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000713_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000711_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000070b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000709_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000707_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000703_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000701_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ef_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ed_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006eb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006c1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006bf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000699_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000697_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000695_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000693_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000691_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000689_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000687_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000685_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000683_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000681_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000679_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000677_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000675_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000673_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000671_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000669_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000667_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000665_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000576_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000576_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000115_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000114_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000113_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000112_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000111_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000110_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010f_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010b_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000101_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009c_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000024_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000020_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000013_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUTF_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_M<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000800 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig0000093c ), + .Q15(\NLW_blk00000003/blk000007ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .Q(\blk00000003/sig000002ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig0000093b ), + .Q15(\NLW_blk00000003/blk000007fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/sig00000251 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e4 ), + .Q(\blk00000003/sig0000093a ), + .Q15(\NLW_blk00000003/blk000007fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .Q(\blk00000003/sig00000250 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/sig00000939 ), + .Q15(\NLW_blk00000003/blk000007f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .Q(\blk00000003/sig0000024f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e6 ), + .Q(\blk00000003/sig00000938 ), + .Q15(\NLW_blk00000003/blk000007f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig0000024d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e0 ), + .Q(\blk00000003/sig00000937 ), + .Q15(\NLW_blk00000003/blk000007f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000936 ), + .Q(\blk00000003/sig0000024c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008de ), + .Q(\blk00000003/sig00000936 ), + .Q15(\NLW_blk00000003/blk000007f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000935 ), + .Q(\blk00000003/sig0000024e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007f1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008e2 ), + .Q(\blk00000003/sig00000935 ), + .Q15(\NLW_blk00000003/blk000007f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000934 ), + .Q(\blk00000003/sig0000024a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ef ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/sig00000934 ), + .Q15(\NLW_blk00000003/blk000007ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000933 ), + .Q(\blk00000003/sig00000249 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ed ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008da ), + .Q(\blk00000003/sig00000933 ), + .Q15(\NLW_blk00000003/blk000007ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000932 ), + .Q(\blk00000003/sig0000024b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007eb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008dc ), + .Q(\blk00000003/sig00000932 ), + .Q15(\NLW_blk00000003/blk000007eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000931 ), + .Q(\blk00000003/sig00000247 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d0 ), + .Q(\blk00000003/sig00000931 ), + .Q15(\NLW_blk00000003/blk000007e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .Q(\blk00000003/sig00000246 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d4 ), + .Q(\blk00000003/sig00000930 ), + .Q15(\NLW_blk00000003/blk000007e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092f ), + .Q(\blk00000003/sig00000248 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d8 ), + .Q(\blk00000003/sig0000092f ), + .Q15(\NLW_blk00000003/blk000007e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092e ), + .Q(\blk00000003/sig00000245 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008d2 ), + .Q(\blk00000003/sig0000092e ), + .Q15(\NLW_blk00000003/blk000007e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .Q(\blk00000003/sig00000244 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007e1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ca ), + .Q(\blk00000003/sig0000092d ), + .Q15(\NLW_blk00000003/blk000007e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092c ), + .Q(\blk00000003/sig00000243 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007df ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ce ), + .Q(\blk00000003/sig0000092c ), + .Q15(\NLW_blk00000003/blk000007df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092b ), + .Q(\blk00000003/sig00000242 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008cc ), + .Q(\blk00000003/sig0000092b ), + .Q15(\NLW_blk00000003/blk000007dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .Q(\blk00000003/sig00000210 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007db ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c6 ), + .Q(\blk00000003/sig0000092a ), + .Q15(\NLW_blk00000003/blk000007db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000929 ), + .Q(\blk00000003/sig0000020f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c4 ), + .Q(\blk00000003/sig00000929 ), + .Q15(\NLW_blk00000003/blk000007d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000928 ), + .Q(\blk00000003/sig00000211 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c8 ), + .Q(\blk00000003/sig00000928 ), + .Q15(\NLW_blk00000003/blk000007d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .Q(\blk00000003/sig0000020d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008bc ), + .Q(\blk00000003/sig00000927 ), + .Q15(\NLW_blk00000003/blk000007d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000926 ), + .Q(\blk00000003/sig0000020c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c0 ), + .Q(\blk00000003/sig00000926 ), + .Q15(\NLW_blk00000003/blk000007d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000925 ), + .Q(\blk00000003/sig0000020e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007d1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008c2 ), + .Q(\blk00000003/sig00000925 ), + .Q15(\NLW_blk00000003/blk000007d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .Q(\blk00000003/sig0000020a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b6 ), + .Q(\blk00000003/sig00000924 ), + .Q15(\NLW_blk00000003/blk000007cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000923 ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ba ), + .Q(\blk00000003/sig00000923 ), + .Q15(\NLW_blk00000003/blk000007cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000922 ), + .Q(\blk00000003/sig0000020b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007cb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008be ), + .Q(\blk00000003/sig00000922 ), + .Q15(\NLW_blk00000003/blk000007cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b8 ), + .Q(\blk00000003/sig00000921 ), + .Q15(\NLW_blk00000003/blk000007c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000920 ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/sig00000920 ), + .Q15(\NLW_blk00000003/blk000007c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091f ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b4 ), + .Q(\blk00000003/sig0000091f ), + .Q15(\NLW_blk00000003/blk000007c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091e ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008b2 ), + .Q(\blk00000003/sig0000091e ), + .Q15(\NLW_blk00000003/blk000007c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091d ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007c1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/sig0000091d ), + .Q15(\NLW_blk00000003/blk000007c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091c ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bf ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/sig0000091c ), + .Q15(\NLW_blk00000003/blk000007bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091b ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/sig0000091b ), + .Q15(\NLW_blk00000003/blk000007bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000091a ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007bb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/sig0000091a ), + .Q15(\NLW_blk00000003/blk000007bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000919 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/sig00000919 ), + .Q15(\NLW_blk00000003/blk000007b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000918 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/sig00000918 ), + .Q15(\NLW_blk00000003/blk000007b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000917 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/sig00000917 ), + .Q15(\NLW_blk00000003/blk000007b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000916 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/sig00000916 ), + .Q15(\NLW_blk00000003/blk000007b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000915 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007b1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/sig00000915 ), + .Q15(\NLW_blk00000003/blk000007b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000914 ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007af ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/sig00000914 ), + .Q15(\NLW_blk00000003/blk000007af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000913 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ad ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/sig00000913 ), + .Q15(\NLW_blk00000003/blk000007ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000912 ), + .Q(\blk00000003/sig00000177 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007ab ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/sig00000912 ), + .Q15(\NLW_blk00000003/blk000007ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000911 ), + .Q(\blk00000003/sig00000176 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/sig00000911 ), + .Q15(\NLW_blk00000003/blk000007a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000910 ), + .Q(\blk00000003/sig00000174 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/sig00000910 ), + .Q15(\NLW_blk00000003/blk000007a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090f ), + .Q(\blk00000003/sig00000173 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a5 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/sig0000090f ), + .Q15(\NLW_blk00000003/blk000007a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090e ), + .Q(\blk00000003/sig00000175 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/sig0000090e ), + .Q15(\NLW_blk00000003/blk000007a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090d ), + .Q(\blk00000003/sig00000171 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007a1 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/sig0000090d ), + .Q15(\NLW_blk00000003/blk000007a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090c ), + .Q(\blk00000003/sig00000170 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/sig0000090c ), + .Q15(\NLW_blk00000003/blk0000079f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090b ), + .Q(\blk00000003/sig00000172 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/sig0000090b ), + .Q15(\NLW_blk00000003/blk0000079d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000090a ), + .Q(\blk00000003/sig0000068c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000079b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b0 ), + .Q(\blk00000003/sig0000090a ), + .Q15(\NLW_blk00000003/blk0000079b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000909 ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000799 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000290 ), + .Q(\blk00000003/sig00000909 ), + .Q15(\NLW_blk00000003/blk00000799_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000908 ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000797 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028f ), + .Q(\blk00000003/sig00000908 ), + .Q15(\NLW_blk00000003/blk00000797_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000907 ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000795 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000291 ), + .Q(\blk00000003/sig00000907 ), + .Q15(\NLW_blk00000003/blk00000795_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000906 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000793 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028d ), + .Q(\blk00000003/sig00000906 ), + .Q15(\NLW_blk00000003/blk00000793_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000905 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000791 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028c ), + .Q(\blk00000003/sig00000905 ), + .Q15(\NLW_blk00000003/blk00000791_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000904 ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028e ), + .Q(\blk00000003/sig00000904 ), + .Q15(\NLW_blk00000003/blk0000078f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000903 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028a ), + .Q(\blk00000003/sig00000903 ), + .Q15(\NLW_blk00000003/blk0000078d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000902 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000078b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000289 ), + .Q(\blk00000003/sig00000902 ), + .Q15(\NLW_blk00000003/blk0000078b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000901 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000789 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000028b ), + .Q(\blk00000003/sig00000901 ), + .Q15(\NLW_blk00000003/blk00000789_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000788 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000900 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000787 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000287 ), + .Q(\blk00000003/sig00000900 ), + .Q15(\NLW_blk00000003/blk00000787_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000786 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ff ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000785 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000286 ), + .Q(\blk00000003/sig000008ff ), + .Q15(\NLW_blk00000003/blk00000785_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000784 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fe ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000783 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000288 ), + .Q(\blk00000003/sig000008fe ), + .Q15(\NLW_blk00000003/blk00000783_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000782 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fd ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000781 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000284 ), + .Q(\blk00000003/sig000008fd ), + .Q15(\NLW_blk00000003/blk00000781_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000780 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fc ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000283 ), + .Q(\blk00000003/sig000008fc ), + .Q15(\NLW_blk00000003/blk0000077f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fb ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000285 ), + .Q(\blk00000003/sig000008fb ), + .Q15(\NLW_blk00000003/blk0000077d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008fa ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000008fa ), + .Q15(\NLW_blk00000003/blk0000077b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f9 ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000779 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000008f9 ), + .Q15(\NLW_blk00000003/blk00000779_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000778 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f8 ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000777 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000282 ), + .Q(\blk00000003/sig000008f8 ), + .Q15(\NLW_blk00000003/blk00000777_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000776 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000775 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000008f7 ), + .Q15(\NLW_blk00000003/blk00000775_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000774 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f6 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000773 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000008f6 ), + .Q15(\NLW_blk00000003/blk00000773_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000772 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f5 ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000771 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000008f5 ), + .Q15(\NLW_blk00000003/blk00000771_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000770 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000008f4 ), + .Q15(\NLW_blk00000003/blk0000076f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f3 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000008f3 ), + .Q15(\NLW_blk00000003/blk0000076d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f2 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000008f2 ), + .Q15(\NLW_blk00000003/blk0000076b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000769 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000008f1 ), + .Q15(\NLW_blk00000003/blk00000769_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008f0 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000767 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000008f0 ), + .Q15(\NLW_blk00000003/blk00000767_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ef ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000765 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000008ef ), + .Q15(\NLW_blk00000003/blk00000765_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000763 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000008ee ), + .Q15(\NLW_blk00000003/blk00000763_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ed ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000761 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000008ed ), + .Q15(\NLW_blk00000003/blk00000761_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ec ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000075f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000075d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008ea ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000075b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000008e9 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000759 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000294 ), + .Q(\blk00000003/sig000008e9 ), + .Q15(\NLW_blk00000003/blk00000759_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e7 ), + .Q(\blk00000003/sig000008e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000757 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig000008e7 ), + .Q15(\NLW_blk00000003/blk00000757_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e5 ), + .Q(\blk00000003/sig000008e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000755 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig000008e5 ), + .Q15(\NLW_blk00000003/blk00000755_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e3 ), + .Q(\blk00000003/sig000008e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000753 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig000008e3 ), + .Q15(\NLW_blk00000003/blk00000753_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008e1 ), + .Q(\blk00000003/sig000008e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000751 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig000008e1 ), + .Q15(\NLW_blk00000003/blk00000751_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008df ), + .Q(\blk00000003/sig000008e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig000008df ), + .Q15(\NLW_blk00000003/blk0000074f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008dd ), + .Q(\blk00000003/sig000008de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000074d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008db ), + .Q(\blk00000003/sig000008dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig000008db ), + .Q15(\NLW_blk00000003/blk0000074b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d9 ), + .Q(\blk00000003/sig000008da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000749 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000749_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/sig000008d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000747 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000747_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/sig000008d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000745 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000745_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d3 ), + .Q(\blk00000003/sig000008d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000743 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000743_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008d1 ), + .Q(\blk00000003/sig000008d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000741 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000741_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cf ), + .Q(\blk00000003/sig000008d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000008cf ), + .Q15(\NLW_blk00000003/blk0000073f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cd ), + .Q(\blk00000003/sig000008ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig000008cd ), + .Q15(\NLW_blk00000003/blk0000073d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008cb ), + .Q(\blk00000003/sig000008cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig000008cb ), + .Q15(\NLW_blk00000003/blk0000073b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c9 ), + .Q(\blk00000003/sig000008ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000739 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000739_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c7 ), + .Q(\blk00000003/sig000008c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000737 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000737_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c5 ), + .Q(\blk00000003/sig000008c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000735 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000735_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c3 ), + .Q(\blk00000003/sig000008c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000733 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig000008c3 ), + .Q15(\NLW_blk00000003/blk00000733_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008c1 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000731 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig000008c1 ), + .Q15(\NLW_blk00000003/blk00000731_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bf ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig000008bf ), + .Q15(\NLW_blk00000003/blk0000072f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bd ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig000008bd ), + .Q15(\NLW_blk00000003/blk0000072d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008bb ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig000008bb ), + .Q15(\NLW_blk00000003/blk0000072b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b9 ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000729 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig000008b9 ), + .Q15(\NLW_blk00000003/blk00000729_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000728 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b7 ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000727 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig000008b7 ), + .Q15(\NLW_blk00000003/blk00000727_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000726 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b5 ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000725 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig000008b5 ), + .Q15(\NLW_blk00000003/blk00000725_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000724 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b3 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000723 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig000008b3 ), + .Q15(\NLW_blk00000003/blk00000723_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000722 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000721 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig000008b1 ), + .Q15(\NLW_blk00000003/blk00000721_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000720 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig000008af ), + .Q15(\NLW_blk00000003/blk0000071f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig000008ad ), + .Q15(\NLW_blk00000003/blk0000071d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig000008ab ), + .Q15(\NLW_blk00000003/blk0000071b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000719 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig000008a9 ), + .Q15(\NLW_blk00000003/blk00000719_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000718 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000717 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig000008a7 ), + .Q15(\NLW_blk00000003/blk00000717_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000716 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000715 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig000008a5 ), + .Q15(\NLW_blk00000003/blk00000715_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000714 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000713 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig000008a3 ), + .Q15(\NLW_blk00000003/blk00000713_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000712 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000711 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig000008a1 ), + .Q15(\NLW_blk00000003/blk00000711_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000710 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000089f ), + .Q15(\NLW_blk00000003/blk0000070f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070e ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000070d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000070b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070a ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000709 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig00000899 ), + .Q15(\NLW_blk00000003/blk00000709_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000708 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000707 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000897 ), + .Q15(\NLW_blk00000003/blk00000707_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000706 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000705 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig00000895 ), + .Q15(\NLW_blk00000003/blk00000705_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000704 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000703 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig00000893 ), + .Q15(\NLW_blk00000003/blk00000703_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000702 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000701 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig00000891 ), + .Q15(\NLW_blk00000003/blk00000701_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000700 ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ff ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000088f ), + .Q15(\NLW_blk00000003/blk000006ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fe ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fd ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig0000088d ), + .Q15(\NLW_blk00000003/blk000006fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fc ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fb ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000088b ), + .Q15(\NLW_blk00000003/blk000006fb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fa ( + .C(clk), + .CE(\blk00000003/sig00000817 ), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f9 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000817 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000889 ), + .Q15(\NLW_blk00000003/blk000006f9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f7 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067b ), + .Q(\blk00000003/sig00000888 ), + .Q15(\NLW_blk00000003/blk000006f7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/sig000006dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig00000887 ), + .Q15(\NLW_blk00000003/blk000006f5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f3 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000067c ), + .Q(\blk00000003/sig00000886 ), + .Q15(\NLW_blk00000003/blk000006f3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/sig000006da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig00000885 ), + .Q15(\NLW_blk00000003/blk000006f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ef ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/sig00000884 ), + .Q15(\NLW_blk00000003/blk000006ef_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ed ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/sig00000883 ), + .Q15(\NLW_blk00000003/blk000006ed_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/sig000006d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006eb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig00000882 ), + .Q15(\NLW_blk00000003/blk000006eb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/sig00000881 ), + .Q15(\NLW_blk00000003/blk000006e9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/sig000006d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig00000880 ), + .Q15(\NLW_blk00000003/blk000006e7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/sig0000087f ), + .Q15(\NLW_blk00000003/blk000006e5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/sig000006d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig0000087e ), + .Q15(\NLW_blk00000003/blk000006e3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/sig000006d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig0000087d ), + .Q15(\NLW_blk00000003/blk000006e1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/sig000006d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006df ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig0000087c ), + .Q15(\NLW_blk00000003/blk000006df_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/sig000006d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig0000087b ), + .Q15(\NLW_blk00000003/blk000006dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/sig000006cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006db ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/sig0000087a ), + .Q15(\NLW_blk00000003/blk000006db_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/sig000006d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/sig00000879 ), + .Q15(\NLW_blk00000003/blk000006d9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/sig000006cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/sig00000878 ), + .Q15(\NLW_blk00000003/blk000006d7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/sig0000076c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig00000877 ), + .Q15(\NLW_blk00000003/blk000006d5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/sig000006ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig00000876 ), + .Q15(\NLW_blk00000003/blk000006d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/sig0000076b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/sig00000875 ), + .Q15(\NLW_blk00000003/blk000006d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/sig0000076a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig00000874 ), + .Q15(\NLW_blk00000003/blk000006cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/sig00000769 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d5 ), + .Q(\blk00000003/sig00000873 ), + .Q15(\NLW_blk00000003/blk000006cd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/sig00000768 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig00000872 ), + .Q15(\NLW_blk00000003/blk000006cb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/sig00000766 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig00000871 ), + .Q15(\NLW_blk00000003/blk000006c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/sig00000765 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d1 ), + .Q(\blk00000003/sig00000870 ), + .Q15(\NLW_blk00000003/blk000006c7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/sig00000767 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d3 ), + .Q(\blk00000003/sig0000086f ), + .Q15(\NLW_blk00000003/blk000006c5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/sig0000086e ), + .Q15(\NLW_blk00000003/blk000006c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/sig000006fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/sig0000086d ), + .Q15(\NLW_blk00000003/blk000006c1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/sig000006fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bf ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig0000086c ), + .Q15(\NLW_blk00000003/blk000006bf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/sig000006f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bd ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/sig0000086b ), + .Q15(\NLW_blk00000003/blk000006bd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bb ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/sig0000086a ), + .Q15(\NLW_blk00000003/blk000006bb_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/sig00000869 ), + .Q15(\NLW_blk00000003/blk000006b9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/sig000006f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/sig00000868 ), + .Q15(\NLW_blk00000003/blk000006b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/sig00000867 ), + .Q15(\NLW_blk00000003/blk000006b5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/sig000006f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/sig00000866 ), + .Q15(\NLW_blk00000003/blk000006b3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/sig00000865 ), + .Q15(\NLW_blk00000003/blk000006b1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006af ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/sig00000864 ), + .Q15(\NLW_blk00000003/blk000006af_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/sig000006f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ad ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/sig00000863 ), + .Q15(\NLW_blk00000003/blk000006ad_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/sig000006f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ab ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/sig00000862 ), + .Q15(\NLW_blk00000003/blk000006ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/sig000006ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a9 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig00000861 ), + .Q15(\NLW_blk00000003/blk000006a9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a7 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig00000860 ), + .Q15(\NLW_blk00000003/blk000006a7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a5 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig0000085f ), + .Q15(\NLW_blk00000003/blk000006a5_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/sig0000077b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a3 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/sig0000085e ), + .Q15(\NLW_blk00000003/blk000006a3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/sig0000077a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a1 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/sig0000085d ), + .Q15(\NLW_blk00000003/blk000006a1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/sig0000077c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069f ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/sig0000085c ), + .Q15(\NLW_blk00000003/blk0000069f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/sig00000779 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069d ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/sig0000085b ), + .Q15(\NLW_blk00000003/blk0000069d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/sig00000778 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069b ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/sig0000085a ), + .Q15(\NLW_blk00000003/blk0000069b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/sig00000777 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000699 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/sig00000859 ), + .Q15(\NLW_blk00000003/blk00000699_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/sig00000776 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000697 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/sig00000858 ), + .Q15(\NLW_blk00000003/blk00000697_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/sig00000397 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000695 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig00000857 ), + .Q15(\NLW_blk00000003/blk00000695_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000694 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/sig00000398 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000693 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000037e ), + .Q(\blk00000003/sig00000856 ), + .Q15(\NLW_blk00000003/blk00000693_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000692 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/sig00000775 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000691 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig00000855 ), + .Q15(\NLW_blk00000003/blk00000691_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000690 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/sig0000071e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig00000854 ), + .Q15(\NLW_blk00000003/blk0000068f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000853 ), + .Q15(\NLW_blk00000003/blk0000068d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a1 ), + .Q(\blk00000003/sig00000852 ), + .Q15(\NLW_blk00000003/blk0000068b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000689 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig00000851 ), + .Q15(\NLW_blk00000003/blk00000689_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000688 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig0000071a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000687 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000850 ), + .Q15(\NLW_blk00000003/blk00000687_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000686 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig0000071c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000685 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000084f ), + .Q15(\NLW_blk00000003/blk00000685_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000684 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000683 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000683_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000682 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000718 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000681 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000681_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000680 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig0000084c ), + .Q15(\NLW_blk00000003/blk0000067f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000716 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig0000084b ), + .Q15(\NLW_blk00000003/blk0000067d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000714 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig0000084a ), + .Q15(\NLW_blk00000003/blk0000067b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000679 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000679_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000677 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000677_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000675 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000675_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000710 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000673 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000673_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000712 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000671 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000671_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig0000070e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066f ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig00000844 ), + .Q15(\NLW_blk00000003/blk0000066f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066d ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig00000843 ), + .Q15(\NLW_blk00000003/blk0000066d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066b ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000842 ), + .Q15(\NLW_blk00000003/blk0000066b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig000002b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000669 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b2 ), + .Q(\blk00000003/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000669_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig0000068b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000667 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000667_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000786 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000665 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029f ), + .Q(\blk00000003/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000665_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000664 ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000353 ) + ); + INV \blk00000003/blk00000663 ( + .I(\blk00000003/sig0000035c ), + .O(\blk00000003/sig0000034c ) + ); + INV \blk00000003/blk00000662 ( + .I(\blk00000003/sig00000363 ), + .O(\blk00000003/sig00000352 ) + ); + INV \blk00000003/blk00000661 ( + .I(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000361 ) + ); + INV \blk00000003/blk00000660 ( + .I(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000080d ) + ); + INV \blk00000003/blk0000065f ( + .I(\blk00000003/sig00000317 ), + .O(\blk00000003/sig00000364 ) + ); + INV \blk00000003/blk0000065e ( + .I(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000034d ) + ); + INV \blk00000003/blk0000065d ( + .I(\blk00000003/sig000002ec ), + .O(\blk00000003/sig00000318 ) + ); + INV \blk00000003/blk0000065c ( + .I(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000166 ) + ); + INV \blk00000003/blk0000065b ( + .I(\blk00000003/sig00000159 ), + .O(\blk00000003/sig00000297 ) + ); + INV \blk00000003/blk0000065a ( + .I(\blk00000003/sig00000163 ), + .O(\blk00000003/sig00000164 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000659 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig0000031c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk00000658 ( + .I0(\blk00000003/sig0000031d ), + .I1(\blk00000003/sig00000311 ), + .I2(\blk00000003/sig00000320 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000309 ), + .O(\blk00000003/sig00000314 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000657 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000309 ), + .O(\blk00000003/sig0000031b ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000656 ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(\blk00000003/sig00000320 ), + .I4(coef_ld), + .O(\blk00000003/sig0000031a ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000655 ( + .I0(\blk00000003/sig0000035c ), + .I1(ce), + .I2(\blk00000003/sig00000311 ), + .I3(\blk00000003/sig000002ea ), + .O(\blk00000003/sig0000083e ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000654 ( + .I0(\blk00000003/sig00000363 ), + .I1(ce), + .I2(\blk00000003/sig0000030f ), + .I3(\blk00000003/sig00000354 ), + .O(\blk00000003/sig0000083d ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000653 ( + .I0(\blk00000003/sig00000810 ), + .I1(ce), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig0000083b ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000652 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000083a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000651 ( + .I0(ce), + .I1(\blk00000003/sig00000320 ), + .I2(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000839 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000650 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig00000366 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000083c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064f ( + .C(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig0000035c ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000064e ( + .C(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000363 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .D(\blk00000003/sig0000083c ), + .R(sclr), + .Q(\blk00000003/sig00000812 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064c ( + .C(clk), + .D(\blk00000003/sig0000083b ), + .R(sclr), + .Q(\blk00000003/sig00000810 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064b ( + .I0(\blk00000003/sig00000798 ), + .O(\blk00000003/sig00000793 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000064a ( + .I0(\blk00000003/sig00000797 ), + .O(\blk00000003/sig00000790 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000649 ( + .I0(\blk00000003/sig00000796 ), + .O(\blk00000003/sig0000078d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000648 ( + .I0(\blk00000003/sig00000795 ), + .O(\blk00000003/sig0000078a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000647 ( + .I0(\blk00000003/sig00000394 ), + .O(\blk00000003/sig00000395 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000646 ( + .I0(\blk00000003/sig00000390 ), + .O(\blk00000003/sig00000391 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000645 ( + .I0(\blk00000003/sig0000037c ), + .O(\blk00000003/sig00000376 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000644 ( + .I0(\blk00000003/sig00000812 ), + .O(\blk00000003/sig0000036c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000643 ( + .I0(\blk00000003/sig0000033d ), + .O(\blk00000003/sig0000033e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000642 ( + .I0(\blk00000003/sig00000339 ), + .O(\blk00000003/sig0000033a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000641 ( + .I0(\blk00000003/sig0000032b ), + .O(\blk00000003/sig00000329 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000640 ( + .I0(\blk00000003/sig00000324 ), + .O(\blk00000003/sig00000322 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000063f ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000063e ( + .I0(\blk00000003/sig0000029d ), + .O(\blk00000003/sig00000167 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000807 ), + .R(sclr), + .Q(\blk00000003/sig0000080c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000804 ), + .R(sclr), + .Q(\blk00000003/sig0000080b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000801 ), + .R(sclr), + .Q(\blk00000003/sig0000080a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fe ), + .R(sclr), + .Q(\blk00000003/sig00000809 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007fb ), + .R(sclr), + .Q(\blk00000003/sig00000808 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000788 ), + .R(sclr), + .Q(\blk00000003/sig00000799 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000794 ), + .R(sclr), + .Q(\blk00000003/sig00000798 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000791 ), + .R(sclr), + .Q(\blk00000003/sig00000797 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078e ), + .R(sclr), + .Q(\blk00000003/sig00000796 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000078b ), + .S(sclr), + .Q(\blk00000003/sig00000795 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000396 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000394 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000393 ), + .R(\blk00000003/sig00000399 ), + .Q(\blk00000003/sig00000390 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000389 ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038e ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038c ), + .S(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig0000038d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000381 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000387 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000384 ), + .R(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000386 ) + ); + FDR \blk00000003/blk0000062d ( + .C(clk), + .D(\blk00000003/sig0000083a ), + .R(ce), + .Q(\blk00000003/sig00000813 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000377 ), + .S(sclr), + .Q(\blk00000003/sig0000037c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037a ), + .R(sclr), + .Q(\blk00000003/sig0000037b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000371 ), + .R(sclr), + .Q(\blk00000003/sig000002b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000374 ), + .R(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDR \blk00000003/blk00000628 ( + .C(clk), + .D(\blk00000003/sig00000839 ), + .R(ce), + .Q(\blk00000003/sig00000811 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033f ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig0000033d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033c ), + .R(\blk00000003/sig00000342 ), + .Q(\blk00000003/sig00000339 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000331 ), + .R(coef_ld), + .Q(\blk00000003/sig00000337 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000334 ), + .R(coef_ld), + .Q(\blk00000003/sig00000336 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032d ), + .R(sclr), + .Q(\blk00000003/sig0000032e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000622 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000032a ), + .R(sclr), + .Q(\blk00000003/sig0000032b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000326 ), + .R(coef_ld), + .Q(\blk00000003/sig00000327 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000620 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000323 ), + .R(coef_ld), + .Q(\blk00000003/sig00000324 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000061f ( + .I0(\blk00000003/sig00000163 ), + .I1(sclr), + .O(\blk00000003/sig00000838 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk0000061e ( + .C(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000163 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000015b ), + .R(sclr), + .Q(\blk00000003/sig00000159 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061c ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig00000809 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007fd ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig0000080a ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000800 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000619 ( + .I0(\blk00000003/sig0000080b ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000803 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig0000080c ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig00000806 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig000002ae ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000007f8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000df ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig000007f6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000de ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig000007f7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000614 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e0 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig000007f5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000613 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e2 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig000007f3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e1 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig000007f4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000611 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e3 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig000007f2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000610 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e5 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig000007f0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060f ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e4 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig000007f1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060e ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e6 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig000007ef ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e8 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig000007ed ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e7 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig000007ee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000e9 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig000007ec ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000eb ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig000007ea ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ea ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig000007eb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ec ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig000007e9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ee ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig000007e7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ed ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig000007e8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000ef ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig000007e6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f1 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig000007e4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f0 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig000007e5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f2 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig000007e3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f4 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig000007e1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f3 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig000007e2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ff ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f5 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig000007e0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fe ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f7 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig000007de ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f6 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig000007df ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f8 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig000007dd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fa ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig000007db ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005fa ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000f9 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig000007dc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fb ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig000007da ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000837 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig000007d8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig000000fc ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig000007d9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000836 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig000007d7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000835 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig000007d5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000834 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig000007d6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000833 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig000007d4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000832 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig000007d2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000831 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig000007d3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005f0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000830 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig000007d1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ef ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082f ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig000007cf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ee ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082e ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig000007d0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ed ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082d ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig000007ce ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ec ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082c ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig000007cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005eb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082b ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig000007cd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ea ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000082a ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig000007cb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000829 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig000007ca ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig000007c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000828 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig000007c9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig000007c7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig000007c5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig000007c6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig000007c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig000007c2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig000007c3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013b ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig000007c1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013d ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig000007bf ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013c ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig000007c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013e ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig000007be ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000140 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig000007bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000013f ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig000007bd ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000141 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig000007bb ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000143 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig000007b9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000142 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig000007ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000144 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig000007b8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000146 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig000007b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000145 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig000007b7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000147 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig000007b5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000149 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig000007b3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000148 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig000007b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014a ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig000007b2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014c ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig000007b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014b ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig000007b1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014d ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig000007af ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014f ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig000007ad ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000014e ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig000007ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000150 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig000007ac ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000152 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig000007aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000151 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig000007ab ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000827 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig000007a9 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000826 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig000007a7 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000825 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig000007a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000824 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig000007a6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000823 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig000007a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000822 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig000007a5 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000821 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig000007a3 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000820 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig000007a1 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081f ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig000007a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081e ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig000007a0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081d ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000079e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081c ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000079f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081b ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000079d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000081a ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig0000079b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000819 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000079c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig0000029d ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig00000818 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig0000079a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig00000799 ), + .I1(\blk00000003/sig00000795 ), + .O(\blk00000003/sig00000787 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b7 ( + .I0(ce), + .I1(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig00000817 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b6 ( + .I0(ce), + .I1(\blk00000003/sig0000067a ), + .O(\blk00000003/sig00000785 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5 ( + .I0(ce), + .I1(\blk00000003/sig00000816 ), + .O(\blk00000003/sig00000744 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000815 ), + .O(\blk00000003/sig00000743 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig0000038d ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig0000038b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig0000038e ), + .I1(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000388 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig00000397 ), + .I1(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000385 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig00000386 ), + .I1(\blk00000003/sig00000397 ), + .I2(\blk00000003/sig00000814 ), + .O(\blk00000003/sig00000383 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig00000387 ), + .I1(\blk00000003/sig00000814 ), + .I2(\blk00000003/sig00000397 ), + .O(\blk00000003/sig00000380 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005ae ( + .I0(sclr), + .I1(\blk00000003/sig00000813 ), + .O(\blk00000003/sig0000037d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig000002a7 ), + .O(\blk00000003/sig00000379 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig0000036e ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000375 ) + ); + LUT4 #( + .INIT ( 16'hFF80 )) + \blk00000003/blk000005ab ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig00000373 ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk000005aa ( + .I0(nd), + .I1(\blk00000003/sig0000036e ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig00000370 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005a9 ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000368 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig00000812 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig0000036b ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000362 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000035f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig0000035d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000315 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000358 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig00000315 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig00000317 ), + .O(\blk00000003/sig0000035a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig00000310 ), + .O(\blk00000003/sig00000351 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig00000313 ), + .I1(\blk00000003/sig0000030f ), + .O(\blk00000003/sig0000034f ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig00000317 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000030d ), + .O(\blk00000003/sig0000034a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig00000312 ), + .I1(\blk00000003/sig00000313 ), + .O(\blk00000003/sig00000346 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig00000311 ), + .I1(\blk00000003/sig00000313 ), + .I2(\blk00000003/sig0000031d ), + .O(\blk00000003/sig00000348 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000811 ), + .O(\blk00000003/sig00000341 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000002f3 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig00000335 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig00000336 ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .O(\blk00000003/sig00000333 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig000002f3 ), + .I2(\blk00000003/sig000002f9 ), + .I3(coef_we), + .O(\blk00000003/sig00000330 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig0000032e ), + .I1(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000032c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig00000327 ), + .I1(coef_we), + .O(\blk00000003/sig00000325 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000597 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000320 ), + .O(\blk00000003/sig00000316 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000596 ( + .I0(coef_we), + .I1(\blk00000003/sig000002f9 ), + .O(\blk00000003/sig000002f4 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000595 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig0000030b ), + .O(\blk00000003/sig0000031e ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig00000336 ), + .I1(\blk00000003/sig00000337 ), + .O(\blk00000003/sig00000301 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig00000324 ), + .I1(\blk00000003/sig00000327 ), + .O(\blk00000003/sig000002fc ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig00000337 ), + .I1(\blk00000003/sig00000336 ), + .O(\blk00000003/sig000002f7 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig00000320 ), + .I1(\blk00000003/sig00000309 ), + .I2(coef_ld), + .O(\blk00000003/sig000002f1 ) + ); + LUT3 #( + .INIT ( 8'hBF )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig00000309 ), + .O(\blk00000003/sig000002ee ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig0000030b ), + .I1(coef_we), + .I2(\blk00000003/sig000002f9 ), + .I3(\blk00000003/sig000002f3 ), + .I4(coef_ld), + .O(\blk00000003/sig0000030a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig00000309 ), + .I1(\blk00000003/sig0000030b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000308 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk0000058d ( + .I0(nd), + .I1(\blk00000003/sig00000366 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig0000016b ), + .I1(\blk00000003/sig00000795 ), + .I2(\blk00000003/sig000002ae ), + .O(\blk00000003/sig0000016c ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000058a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000795 ), + .O(\blk00000003/sig000002af ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk00000589 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig0000032b ), + .I1(\blk00000003/sig0000032e ), + .O(\blk00000003/sig00000295 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig00000808 ), + .I1(\blk00000003/sig00000809 ), + .I2(\blk00000003/sig0000080a ), + .I3(\blk00000003/sig0000080b ), + .I4(\blk00000003/sig0000080c ), + .O(\blk00000003/sig0000016f ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000002a7 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig0000037c ), + .I1(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002ac ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000584 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig00000161 ), + .O(\blk00000003/sig00000160 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000583 ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000015f ), + .O(\blk00000003/sig0000015e ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000582 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000002a9 ), + .I3(\blk00000003/sig00000296 ), + .O(\blk00000003/sig000002a8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig00000159 ), + .I1(\blk00000003/sig00000296 ), + .O(\blk00000003/sig0000015a ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000002b5 ), + .I2(\blk00000003/sig000002a5 ), + .I3(\blk00000003/sig000002a7 ), + .I4(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig00000810 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000002b5 ), + .I1(\blk00000003/sig000002a5 ), + .I2(\blk00000003/sig000002a7 ), + .I3(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig0000037b ), + .I1(\blk00000003/sig0000037c ), + .I2(\blk00000003/sig000002b3 ), + .O(\blk00000003/sig000002aa ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000057c ( + .I0(ce), + .I1(\blk00000003/sig0000080e ), + .I2(\blk00000003/sig0000080f ), + .I3(\blk00000003/sig0000015d ), + .O(\blk00000003/sig0000015c ) + ); + MUXCY \blk00000003/blk0000057b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000080d ), + .O(\blk00000003/sig00000805 ) + ); + MUXCY_L \blk00000003/blk0000057a ( + .CI(\blk00000003/sig00000805 ), + .DI(\blk00000003/sig0000080c ), + .S(\blk00000003/sig00000806 ), + .LO(\blk00000003/sig00000802 ) + ); + MUXCY_L \blk00000003/blk00000579 ( + .CI(\blk00000003/sig00000802 ), + .DI(\blk00000003/sig0000080b ), + .S(\blk00000003/sig00000803 ), + .LO(\blk00000003/sig000007ff ) + ); + MUXCY_L \blk00000003/blk00000578 ( + .CI(\blk00000003/sig000007ff ), + .DI(\blk00000003/sig0000080a ), + .S(\blk00000003/sig00000800 ), + .LO(\blk00000003/sig000007fc ) + ); + MUXCY_L \blk00000003/blk00000577 ( + .CI(\blk00000003/sig000007fc ), + .DI(\blk00000003/sig00000809 ), + .S(\blk00000003/sig000007fd ), + .LO(\blk00000003/sig000007f9 ) + ); + MUXCY_D \blk00000003/blk00000576 ( + .CI(\blk00000003/sig000007f9 ), + .DI(\blk00000003/sig00000808 ), + .S(\blk00000003/sig000007fa ), + .O(\NLW_blk00000003/blk00000576_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000576_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000575 ( + .CI(\blk00000003/sig00000805 ), + .LI(\blk00000003/sig00000806 ), + .O(\blk00000003/sig00000807 ) + ); + XORCY \blk00000003/blk00000574 ( + .CI(\blk00000003/sig00000802 ), + .LI(\blk00000003/sig00000803 ), + .O(\blk00000003/sig00000804 ) + ); + XORCY \blk00000003/blk00000573 ( + .CI(\blk00000003/sig000007ff ), + .LI(\blk00000003/sig00000800 ), + .O(\blk00000003/sig00000801 ) + ); + XORCY \blk00000003/blk00000572 ( + .CI(\blk00000003/sig000007fc ), + .LI(\blk00000003/sig000007fd ), + .O(\blk00000003/sig000007fe ) + ); + XORCY \blk00000003/blk00000571 ( + .CI(\blk00000003/sig000007f9 ), + .LI(\blk00000003/sig000007fa ), + .O(\blk00000003/sig000007fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000570 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f8 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007f0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ef ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ee ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ed ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ec ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007eb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ea ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007e0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007df ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007de ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007dc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007db ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007da ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000550 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000548 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007d0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000546 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ce ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000544 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007cb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000542 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ca ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000540 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000538 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007c0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bf ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000536 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007be ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bd ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bc ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007bb ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ba ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007b0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007af ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ae ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ad ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ac ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007ab ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007aa ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a9 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a8 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a7 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a6 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a5 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a4 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a3 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a2 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a1 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000007a0 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000079a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + MUXCY_L \blk00000003/blk00000511 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000799 ), + .S(\blk00000003/sig00000787 ), + .LO(\blk00000003/sig00000792 ) + ); + MUXCY_L \blk00000003/blk00000510 ( + .CI(\blk00000003/sig00000792 ), + .DI(\blk00000003/sig00000798 ), + .S(\blk00000003/sig00000793 ), + .LO(\blk00000003/sig0000078f ) + ); + MUXCY_L \blk00000003/blk0000050f ( + .CI(\blk00000003/sig0000078f ), + .DI(\blk00000003/sig00000797 ), + .S(\blk00000003/sig00000790 ), + .LO(\blk00000003/sig0000078c ) + ); + MUXCY_L \blk00000003/blk0000050e ( + .CI(\blk00000003/sig0000078c ), + .DI(\blk00000003/sig00000796 ), + .S(\blk00000003/sig0000078d ), + .LO(\blk00000003/sig00000789 ) + ); + MUXCY_D \blk00000003/blk0000050d ( + .CI(\blk00000003/sig00000789 ), + .DI(\blk00000003/sig00000795 ), + .S(\blk00000003/sig0000078a ), + .O(\NLW_blk00000003/blk0000050d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000050d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000050c ( + .CI(\blk00000003/sig00000792 ), + .LI(\blk00000003/sig00000793 ), + .O(\blk00000003/sig00000794 ) + ); + XORCY \blk00000003/blk0000050b ( + .CI(\blk00000003/sig0000078f ), + .LI(\blk00000003/sig00000790 ), + .O(\blk00000003/sig00000791 ) + ); + XORCY \blk00000003/blk0000050a ( + .CI(\blk00000003/sig0000078c ), + .LI(\blk00000003/sig0000078d ), + .O(\blk00000003/sig0000078e ) + ); + XORCY \blk00000003/blk00000509 ( + .CI(\blk00000003/sig00000789 ), + .LI(\blk00000003/sig0000078a ), + .O(\blk00000003/sig0000078b ) + ); + XORCY \blk00000003/blk00000508 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000787 ), + .O(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005e0 ), + .R(sclr), + .Q(\blk00000003/sig0000069c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005df ), + .R(sclr), + .Q(\blk00000003/sig0000069b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005de ), + .R(sclr), + .Q(\blk00000003/sig0000069a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dd ), + .R(sclr), + .Q(\blk00000003/sig00000699 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005dc ), + .R(sclr), + .Q(\blk00000003/sig00000698 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005db ), + .R(sclr), + .Q(\blk00000003/sig00000697 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005da ), + .R(sclr), + .Q(\blk00000003/sig00000696 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d9 ), + .R(sclr), + .Q(\blk00000003/sig00000695 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d8 ), + .R(sclr), + .Q(\blk00000003/sig00000694 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d7 ), + .R(sclr), + .Q(\blk00000003/sig00000693 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d6 ), + .R(sclr), + .Q(\blk00000003/sig00000692 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d5 ), + .R(sclr), + .Q(\blk00000003/sig00000691 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d4 ), + .R(sclr), + .Q(\blk00000003/sig00000690 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d3 ), + .R(sclr), + .Q(\blk00000003/sig0000068f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d2 ), + .R(sclr), + .Q(\blk00000003/sig0000068e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig000005d1 ), + .R(sclr), + .Q(\blk00000003/sig0000068d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(\blk00000003/sig000006ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(\blk00000003/sig000006ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(\blk00000003/sig000006aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(\blk00000003/sig000006a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(\blk00000003/sig000006a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(\blk00000003/sig000006a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(\blk00000003/sig000006a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(\blk00000003/sig000006a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(\blk00000003/sig000006a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(\blk00000003/sig000006a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(\blk00000003/sig000006a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(\blk00000003/sig000006a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(\blk00000003/sig000006a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bb ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(\blk00000003/sig0000069f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(\blk00000003/sig0000069e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(\blk00000003/sig0000069d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(\blk00000003/sig00000785 ), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004af ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000565 ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ae ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000564 ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ad ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ac ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ab ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004aa ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a9 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a8 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a7 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a6 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a5 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000588 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000587 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000584 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000583 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000582 ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000581 ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(\blk00000003/sig00000761 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(\blk00000003/sig00000760 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000385 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(\blk00000003/sig000006ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(\blk00000003/sig000006eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000383 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(\blk00000003/sig000006ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000382 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(\blk00000003/sig000006e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000381 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(\blk00000003/sig000006e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000380 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(\blk00000003/sig000006e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(\blk00000003/sig000006e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(\blk00000003/sig000006e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(\blk00000003/sig000006e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(\blk00000003/sig000006e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(\blk00000003/sig000006e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(\blk00000003/sig000006e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000379 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(\blk00000003/sig000006e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000378 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(\blk00000003/sig000006df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000377 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(\blk00000003/sig000006de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000376 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(\blk00000003/sig000006dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000375 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005a0 ), + .R(sclr), + .Q(\blk00000003/sig000006bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000374 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059f ), + .R(sclr), + .Q(\blk00000003/sig000006bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000373 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059e ), + .R(sclr), + .Q(\blk00000003/sig000006ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000372 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059d ), + .R(sclr), + .Q(\blk00000003/sig000006b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059c ), + .R(sclr), + .Q(\blk00000003/sig000006b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059b ), + .R(sclr), + .Q(\blk00000003/sig000006b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig0000059a ), + .R(sclr), + .Q(\blk00000003/sig000006b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000599 ), + .R(sclr), + .Q(\blk00000003/sig000006b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000598 ), + .R(sclr), + .Q(\blk00000003/sig000006b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000597 ), + .R(sclr), + .Q(\blk00000003/sig000006b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000596 ), + .R(sclr), + .Q(\blk00000003/sig000006b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000595 ), + .R(sclr), + .Q(\blk00000003/sig000006b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000594 ), + .R(sclr), + .Q(\blk00000003/sig000006b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000593 ), + .R(sclr), + .Q(\blk00000003/sig000006af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000592 ), + .R(sclr), + .Q(\blk00000003/sig000006ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig00000591 ), + .R(sclr), + .Q(\blk00000003/sig000006ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(\blk00000003/sig0000070c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(\blk00000003/sig0000070b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(\blk00000003/sig0000070a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(\blk00000003/sig00000709 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(\blk00000003/sig00000708 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(\blk00000003/sig00000707 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(\blk00000003/sig00000706 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(\blk00000003/sig00000705 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(\blk00000003/sig00000704 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(\blk00000003/sig00000703 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(\blk00000003/sig00000702 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(\blk00000003/sig00000701 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(\blk00000003/sig00000700 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(\blk00000003/sig000006ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(\blk00000003/sig000006fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig00000744 ), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(\blk00000003/sig000006fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005f0 ), + .R(sclr), + .Q(\blk00000003/sig000006cc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ef ), + .R(sclr), + .Q(\blk00000003/sig000006cb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ee ), + .R(sclr), + .Q(\blk00000003/sig000006ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ed ), + .R(sclr), + .Q(\blk00000003/sig000006c9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ec ), + .R(sclr), + .Q(\blk00000003/sig000006c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005eb ), + .R(sclr), + .Q(\blk00000003/sig000006c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005ea ), + .R(sclr), + .Q(\blk00000003/sig000006c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e9 ), + .R(sclr), + .Q(\blk00000003/sig000006c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e8 ), + .R(sclr), + .Q(\blk00000003/sig000006c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e7 ), + .R(sclr), + .Q(\blk00000003/sig000006c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e6 ), + .R(sclr), + .Q(\blk00000003/sig000006c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e5 ), + .R(sclr), + .Q(\blk00000003/sig000006c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e4 ), + .R(sclr), + .Q(\blk00000003/sig000006c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e3 ), + .R(sclr), + .Q(\blk00000003/sig000006bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e2 ), + .R(sclr), + .Q(\blk00000003/sig000006be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig00000743 ), + .D(\blk00000003/sig000005e1 ), + .R(sclr), + .Q(\blk00000003/sig000006bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038e ), + .R(sclr), + .Q(\blk00000003/sig00000685 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000038d ), + .R(sclr), + .Q(\blk00000003/sig00000683 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000390 ), + .R(sclr), + .Q(\blk00000003/sig00000681 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000394 ), + .R(sclr), + .Q(\blk00000003/sig0000067f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000039a ), + .R(sclr), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .R(sclr), + .Q(\blk00000003/sig00000679 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000387 ), + .R(sclr), + .Q(\blk00000003/sig00000689 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000386 ), + .R(sclr), + .Q(\blk00000003/sig00000687 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000689 ), + .R(sclr), + .Q(\blk00000003/sig0000068a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig00000688 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000685 ), + .R(sclr), + .Q(\blk00000003/sig00000686 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000683 ), + .R(sclr), + .Q(\blk00000003/sig00000684 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000681 ), + .R(sclr), + .Q(\blk00000003/sig00000682 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067f ), + .R(sclr), + .Q(\blk00000003/sig00000680 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067d ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000067b ), + .R(sclr), + .Q(\blk00000003/sig0000067c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000679 ), + .R(sclr), + .Q(\blk00000003/sig0000067a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000677 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000678 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000307 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000673 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000671 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000340 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000033d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000672 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000339 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000671 ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000115 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000115_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000115_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , +\blk00000003/sig00000654 , \blk00000003/sig00000655 , \blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , +\blk00000003/sig00000659 , \blk00000003/sig0000065a , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , +\blk00000003/sig0000065e , \blk00000003/sig0000065f , \blk00000003/sig00000660 }), + .BCOUT({\NLW_blk00000003/blk00000115_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000115_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000115_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , +\blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , +\blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 , +\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc }), + .C({\NLW_blk00000003/blk00000115_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000115_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 }), + .PCOUT({\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa , +\blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , \blk00000003/sig000005ff , +\blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , \blk00000003/sig00000604 , +\blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , \blk00000003/sig00000609 , +\blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , \blk00000003/sig0000060e , +\blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 , \blk00000003/sig00000613 , +\blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , \blk00000003/sig00000618 , +\blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , \blk00000003/sig0000061d , +\blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 }), + .A({\blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , +\blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , +\blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , +\blk00000003/sig0000057e , \blk00000003/sig0000057f , \blk00000003/sig00000580 }), + .M({\NLW_blk00000003/blk00000115_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000115_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000115_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000114 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000114_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000114_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , +\blk00000003/sig00000634 , \blk00000003/sig00000635 , \blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , +\blk00000003/sig00000639 , \blk00000003/sig0000063a , \blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , +\blk00000003/sig0000063e , \blk00000003/sig0000063f , \blk00000003/sig00000640 }), + .BCOUT({\NLW_blk00000003/blk00000114_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000114_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000114_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 , +\blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , \blk00000003/sig00000479 , +\blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c }), + .C({\NLW_blk00000003/blk00000114_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000114_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000114_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000114_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000114_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000114_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000641 , \blk00000003/sig00000642 , \blk00000003/sig00000643 , +\blk00000003/sig00000644 , \blk00000003/sig00000645 , \blk00000003/sig00000646 , \blk00000003/sig00000647 , \blk00000003/sig00000648 , +\blk00000003/sig00000649 , \blk00000003/sig0000064a , \blk00000003/sig0000064b , \blk00000003/sig0000064c , \blk00000003/sig0000064d , +\blk00000003/sig0000064e , \blk00000003/sig0000064f , \blk00000003/sig00000650 }), + .PCOUT({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , +\blk00000003/sig000005b5 , \blk00000003/sig000005b6 , \blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , +\blk00000003/sig000005ba , \blk00000003/sig000005bb , \blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , +\blk00000003/sig000005bf , \blk00000003/sig000005c0 , \blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , +\blk00000003/sig000005c4 , \blk00000003/sig000005c5 , \blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , +\blk00000003/sig000005c9 , \blk00000003/sig000005ca , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , +\blk00000003/sig000005ce , \blk00000003/sig000005cf , \blk00000003/sig000005d0 }), + .A({\blk00000003/sig0000056f , \blk00000003/sig00000570 , \blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , +\blk00000003/sig00000574 , \blk00000003/sig00000575 , \blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , +\blk00000003/sig00000579 , \blk00000003/sig0000057a , \blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , +\blk00000003/sig0000057e , \blk00000003/sig0000057f , \blk00000003/sig00000580 }), + .M({\NLW_blk00000003/blk00000114_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000114_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000114_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000113 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000113_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000113_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000005e1 , \blk00000003/sig000005e2 , \blk00000003/sig000005e3 , +\blk00000003/sig000005e4 , \blk00000003/sig000005e5 , \blk00000003/sig000005e6 , \blk00000003/sig000005e7 , \blk00000003/sig000005e8 , +\blk00000003/sig000005e9 , \blk00000003/sig000005ea , \blk00000003/sig000005eb , \blk00000003/sig000005ec , \blk00000003/sig000005ed , +\blk00000003/sig000005ee , \blk00000003/sig000005ef , \blk00000003/sig000005f0 }), + .BCOUT({\NLW_blk00000003/blk00000113_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000113_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000113_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa , +\blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , \blk00000003/sig000005ff , +\blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , \blk00000003/sig00000604 , +\blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , \blk00000003/sig00000609 , +\blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , \blk00000003/sig0000060e , +\blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 , \blk00000003/sig00000613 , +\blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , \blk00000003/sig00000618 , +\blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , \blk00000003/sig0000061d , +\blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 }), + .C({\NLW_blk00000003/blk00000113_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000113_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000621 , \blk00000003/sig00000622 , \blk00000003/sig00000623 , +\blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , \blk00000003/sig00000627 , \blk00000003/sig00000628 , +\blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , \blk00000003/sig0000062c , \blk00000003/sig0000062d , +\blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 }), + .PCOUT({\blk00000003/sig000001ca , \blk00000003/sig000001cb , \blk00000003/sig000001cc , \blk00000003/sig000001cd , \blk00000003/sig000001ce , +\blk00000003/sig000001cf , \blk00000003/sig000001d0 , \blk00000003/sig000001d1 , \blk00000003/sig000001d2 , \blk00000003/sig000001d3 , +\blk00000003/sig000001d4 , \blk00000003/sig000001d5 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 , \blk00000003/sig000001e6 , \blk00000003/sig000001e7 , +\blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , \blk00000003/sig000001eb , \blk00000003/sig000001ec , +\blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , \blk00000003/sig000001f0 , \blk00000003/sig000001f1 , +\blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , \blk00000003/sig000001f5 , \blk00000003/sig000001f6 , +\blk00000003/sig000001f7 , \blk00000003/sig000001f8 , \blk00000003/sig000001f9 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000113_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000113_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000113_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000112 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000112_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000112_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .BCOUT({\NLW_blk00000003/blk00000112_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000112_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000112_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , 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\blk00000003/sig000005d0 }), + .C({\NLW_blk00000003/blk00000112_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000112_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 }), + .PCOUT({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , \blk00000003/sig0000026c , \blk00000003/sig0000026d , \blk00000003/sig0000026e , \blk00000003/sig0000026f , +\blk00000003/sig00000270 , \blk00000003/sig00000271 , \blk00000003/sig00000272 , \blk00000003/sig00000273 , \blk00000003/sig00000274 , +\blk00000003/sig00000275 , \blk00000003/sig00000276 , \blk00000003/sig00000277 , \blk00000003/sig00000278 , \blk00000003/sig00000279 , +\blk00000003/sig0000027a , \blk00000003/sig0000027b , \blk00000003/sig0000027c , \blk00000003/sig0000027d , \blk00000003/sig0000027e , +\blk00000003/sig0000027f , \blk00000003/sig00000280 , \blk00000003/sig00000281 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk00000112_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000112_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000112_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000111 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000111_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000111_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , \blk00000003/sig00000581 , +\blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , \blk00000003/sig00000585 , +\blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 }), + .BCOUT({\NLW_blk00000003/blk00000111_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000111_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000111_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , +\blk00000003/sig00000402 , \blk00000003/sig00000403 , \blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , +\blk00000003/sig00000407 , \blk00000003/sig00000408 , \blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , +\blk00000003/sig0000040c , \blk00000003/sig0000040d , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , +\blk00000003/sig00000411 , \blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , +\blk00000003/sig00000416 , \blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , +\blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , +\blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , +\blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , +\blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c }), + .C({\NLW_blk00000003/blk00000111_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<46>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<43>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<40>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<37>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<34>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<31>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<28>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<25>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<22>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<19>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<13>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<7>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000111_C<1>_UNCONNECTED , +\NLW_blk00000003/blk00000111_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk00000111_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000111_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000111_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , \blk00000003/sig00000589 , +\blk00000003/sig00000589 , \blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , +\blk00000003/sig0000058e , \blk00000003/sig0000058f , \blk00000003/sig00000590 }), + .PCOUT({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , \blk00000003/sig00000530 , +\blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , \blk00000003/sig00000535 , +\blk00000003/sig00000536 , \blk00000003/sig00000537 , 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, \NLW_blk00000003/blk00000111_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000111_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000111_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000110 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000110_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000110_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , \blk00000003/sig0000055f , +\blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , \blk00000003/sig00000562 , \blk00000003/sig00000563 , +\blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 }), + .BCOUT({\NLW_blk00000003/blk00000110_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000110_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_BCOUT<10>_UNCONNECTED , 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\NLW_blk00000003/blk00000110_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000110_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000110_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010f ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010f_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010f_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000051f , \blk00000003/sig0000051f , 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+\NLW_blk00000003/blk0000010f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010f_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e , \blk00000003/sig0000052f , \blk00000003/sig00000530 , +\blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , \blk00000003/sig00000534 , \blk00000003/sig00000535 , +\blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , \blk00000003/sig00000539 , \blk00000003/sig0000053a , +\blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , \blk00000003/sig0000053e , \blk00000003/sig0000053f , +\blk00000003/sig00000540 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , \blk00000003/sig0000054d , \blk00000003/sig0000054e , +\blk00000003/sig0000054f , \blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , +\blk00000003/sig00000554 , \blk00000003/sig00000555 , \blk00000003/sig00000556 }), + .C({\NLW_blk00000003/blk0000010f_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<43>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_C<3>_UNCONNECTED , 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\NLW_blk00000003/blk0000010f_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010f_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , +\blk00000003/sig00000557 , \blk00000003/sig00000557 , \blk00000003/sig00000557 , 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\blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010f_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010f_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010f_M<19>_UNCONNECTED , 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\NLW_blk00000003/blk0000010e_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010e_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , \blk00000003/sig00000505 , +\blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , \blk00000003/sig00000509 , +\blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c }), + .PCOUT({\blk00000003/sig00000212 , \blk00000003/sig00000213 , \blk00000003/sig00000214 , \blk00000003/sig00000215 , \blk00000003/sig00000216 , +\blk00000003/sig00000217 , \blk00000003/sig00000218 , \blk00000003/sig00000219 , \blk00000003/sig0000021a , \blk00000003/sig0000021b , +\blk00000003/sig0000021c , \blk00000003/sig0000021d , \blk00000003/sig0000021e , \blk00000003/sig0000021f , \blk00000003/sig00000220 , +\blk00000003/sig00000221 , \blk00000003/sig00000222 , \blk00000003/sig00000223 , \blk00000003/sig00000224 , \blk00000003/sig00000225 , +\blk00000003/sig00000226 , \blk00000003/sig00000227 , \blk00000003/sig00000228 , \blk00000003/sig00000229 , \blk00000003/sig0000022a , +\blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , \blk00000003/sig0000022e , \blk00000003/sig0000022f , +\blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , \blk00000003/sig00000233 , \blk00000003/sig00000234 , +\blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , \blk00000003/sig00000238 , \blk00000003/sig00000239 , +\blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , \blk00000003/sig0000023d , \blk00000003/sig0000023e , +\blk00000003/sig0000023f , \blk00000003/sig00000240 , \blk00000003/sig00000241 }), + .A({\blk00000003/sig0000050d , \blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , +\blk00000003/sig00000512 , \blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , +\blk00000003/sig00000517 , \blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , +\blk00000003/sig0000051c , \blk00000003/sig0000051d , \blk00000003/sig0000051e }), + .M({\NLW_blk00000003/blk0000010e_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010e_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010e_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010d ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010d_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010d_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000047d , \blk00000003/sig0000047e , \blk00000003/sig0000047f , +\blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , \blk00000003/sig00000484 , +\blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , \blk00000003/sig00000489 , +\blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .BCOUT({\NLW_blk00000003/blk0000010d_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010d_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010d_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010d_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , +\blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , +\blk00000003/sig00000495 , \blk00000003/sig00000496 , \blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , +\blk00000003/sig0000049a , \blk00000003/sig0000049b , \blk00000003/sig0000049c }), + .PCOUT({\blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , \blk00000003/sig000004a1 , +\blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , \blk00000003/sig000004a6 , +\blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , \blk00000003/sig000004ab , +\blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , \blk00000003/sig000004b0 , +\blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , \blk00000003/sig000004b5 , +\blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , \blk00000003/sig000004ba , +\blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , +\blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , +\blk00000003/sig000004c5 , \blk00000003/sig000004c6 , \blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , +\blk00000003/sig000004ca , \blk00000003/sig000004cb , \blk00000003/sig000004cc }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010d_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010d_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010d_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010c ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010c_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010c_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , +\blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , +\blk00000003/sig00000435 , \blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , +\blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c }), + .BCOUT({\NLW_blk00000003/blk0000010c_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010c_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010c_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010c_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<45>_UNCONNECTED , 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+\NLW_blk00000003/blk0000010c_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , +\blk00000003/sig00000440 , \blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , +\blk00000003/sig00000445 , \blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , +\blk00000003/sig0000044a , \blk00000003/sig0000044b , \blk00000003/sig0000044c }), + .PCOUT({\blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 , \blk00000003/sig00000451 , +\blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , \blk00000003/sig00000455 , \blk00000003/sig00000456 , +\blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , \blk00000003/sig0000045a , \blk00000003/sig0000045b , +\blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 , +\blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , \blk00000003/sig00000479 , +\blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010c_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010c_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010c_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk0000010b ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk0000010b_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010b_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , +\blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , \blk00000003/sig000003ed , +\blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 }), + .BCOUT({\NLW_blk00000003/blk0000010b_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000010b_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\NLW_blk00000003/blk0000010b_C<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<42>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<41>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<39>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<38>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<36>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<35>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<33>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<32>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<30>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<29>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<27>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<26>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<24>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<23>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010b_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<43>_UNCONNECTED , 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\NLW_blk00000003/blk0000010b_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010b_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010b_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , \blk00000003/sig000003f5 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc }), + .PCOUT({\blk00000003/sig000003fd , \blk00000003/sig000003fe , \blk00000003/sig000003ff , \blk00000003/sig00000400 , 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.CARRYOUTF(\NLW_blk00000003/blk0000010a_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk0000010a_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , \blk00000003/sig0000039b , +\blk00000003/sig0000039b , \blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , +\blk00000003/sig000003a0 , \blk00000003/sig000003a1 , \blk00000003/sig000003a2 }), + .BCOUT({\NLW_blk00000003/blk0000010a_BCOUT<17>_UNCONNECTED , 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+\NLW_blk00000003/blk0000010a_C<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_C<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_C<0>_UNCONNECTED }), + .P({\NLW_blk00000003/blk0000010a_P<47>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<46>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<45>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<44>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<43>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<42>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<41>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<40>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<39>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<38>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<37>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<36>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_P<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .D({\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , \blk00000003/sig000003a3 , +\blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , \blk00000003/sig000003a7 , +\blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa }), + .PCOUT({\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , +\blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da }), + .A({\blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , +\blk00000003/sig000003e0 , \blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , +\blk00000003/sig000003e5 , \blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , +\blk00000003/sig000003ea , \blk00000003/sig000003eb , \blk00000003/sig000003ec }), + .M({\NLW_blk00000003/blk0000010a_M<35>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<34>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<33>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<32>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<31>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<30>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<29>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<28>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<27>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<26>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<25>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<24>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<23>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<22>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<21>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<20>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<19>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<18>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<17>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<16>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<15>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<14>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<13>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<12>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<11>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<10>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<9>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<8>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<7>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<6>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<5>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<4>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<3>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<2>_UNCONNECTED , \NLW_blk00000003/blk0000010a_M<1>_UNCONNECTED , +\NLW_blk00000003/blk0000010a_M<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000039a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000398 ), + .Q(\blk00000003/sig00000399 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000397 ), + .Q(\blk00000003/sig0000038f ) + ); + XORCY \blk00000003/blk00000106 ( + .CI(\blk00000003/sig00000392 ), + .LI(\blk00000003/sig00000395 ), + .O(\blk00000003/sig00000396 ) + ); + MUXCY_D \blk00000003/blk00000105 ( + .CI(\blk00000003/sig00000392 ), + .DI(\blk00000003/sig00000394 ), + .S(\blk00000003/sig00000395 ), + .O(\NLW_blk00000003/blk00000105_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000105_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000104 ( + .CI(\blk00000003/sig0000038f ), + .LI(\blk00000003/sig00000391 ), + .O(\blk00000003/sig00000393 ) + ); + MUXCY_L \blk00000003/blk00000103 ( + .CI(\blk00000003/sig0000038f ), + .DI(\blk00000003/sig00000390 ), + .S(\blk00000003/sig00000391 ), + .LO(\blk00000003/sig00000392 ) + ); + MUXCY_L \blk00000003/blk00000102 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000038e ), + .S(\blk00000003/sig00000388 ), + .LO(\blk00000003/sig0000038a ) + ); + MUXCY_D \blk00000003/blk00000101 ( + .CI(\blk00000003/sig0000038a ), + .DI(\blk00000003/sig0000038d ), + .S(\blk00000003/sig0000038b ), + .O(\NLW_blk00000003/blk00000101_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000101_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig0000038a ), + .LI(\blk00000003/sig0000038b ), + .O(\blk00000003/sig0000038c ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000388 ), + .O(\blk00000003/sig00000389 ) + ); + MUXCY_L \blk00000003/blk000000fe ( + .CI(\blk00000003/sig0000037f ), + .DI(\blk00000003/sig00000387 ), + .S(\blk00000003/sig00000380 ), + .LO(\blk00000003/sig00000382 ) + ); + MUXCY_D \blk00000003/blk000000fd ( + .CI(\blk00000003/sig00000382 ), + .DI(\blk00000003/sig00000386 ), + .S(\blk00000003/sig00000383 ), + .O(\NLW_blk00000003/blk000000fd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000385 ), + .O(\blk00000003/sig0000037f ) + ); + XORCY \blk00000003/blk000000fb ( + .CI(\blk00000003/sig00000382 ), + .LI(\blk00000003/sig00000383 ), + .O(\blk00000003/sig00000384 ) + ); + XORCY \blk00000003/blk000000fa ( + .CI(\blk00000003/sig0000037f ), + .LI(\blk00000003/sig00000380 ), + .O(\blk00000003/sig00000381 ) + ); + FDE \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000037d ), + .Q(\blk00000003/sig0000037e ) + ); + MUXCY_L \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000037c ), + .S(\blk00000003/sig00000376 ), + .LO(\blk00000003/sig00000378 ) + ); + MUXCY_D \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig00000378 ), + .DI(\blk00000003/sig0000037b ), + .S(\blk00000003/sig00000379 ), + .O(\NLW_blk00000003/blk000000f7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig00000378 ), + .LI(\blk00000003/sig00000379 ), + .O(\blk00000003/sig0000037a ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000376 ), + .O(\blk00000003/sig00000377 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig0000036f ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig00000370 ), + .LO(\blk00000003/sig00000372 ) + ); + MUXCY_D \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000372 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig00000373 ), + .O(\NLW_blk00000003/blk000000f3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f3_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000375 ), + .O(\blk00000003/sig0000036f ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000372 ), + .LI(\blk00000003/sig00000373 ), + .O(\blk00000003/sig00000374 ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig0000036f ), + .LI(\blk00000003/sig00000370 ), + .O(\blk00000003/sig00000371 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000036d ), + .R(sclr), + .Q(\blk00000003/sig0000036e ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig0000036a ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036c ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\blk00000003/sig0000036d ) + ); + MUXCY_D \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000036b ), + .O(\blk00000003/sig00000367 ), + .LO(\NLW_blk00000003/blk000000ed_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000369 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000365 ) + ); + MUXCY \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000369 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000036a ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig00000367 ), + .DI(\blk00000003/sig00000366 ), + .S(\blk00000003/sig00000368 ), + .O(\blk00000003/sig00000369 ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000365 ), + .R(sclr), + .Q(\blk00000003/sig00000366 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000356 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000355 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ed ) + ); + MUXCY_D \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig000002ed ), + .DI(\blk00000003/sig00000363 ), + .S(\blk00000003/sig00000364 ), + .O(\blk00000003/sig00000360 ), + .LO(\NLW_blk00000003/blk000000e6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000360 ), + .DI(\blk00000003/sig00000361 ), + .S(\blk00000003/sig00000362 ), + .O(\blk00000003/sig0000035e ), + .LO(\NLW_blk00000003/blk000000e5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000035e ), + .DI(\blk00000003/sig00000354 ), + .S(\blk00000003/sig0000035f ), + .O(\blk00000003/sig0000035b ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000035b ), + .DI(\blk00000003/sig0000035c ), + .S(\blk00000003/sig0000035d ), + .O(\blk00000003/sig00000359 ), + .LO(\NLW_blk00000003/blk000000e3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000359 ), + .DI(\blk00000003/sig00000319 ), + .S(\blk00000003/sig0000035a ), + .O(\blk00000003/sig00000357 ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000357 ), + .DI(\blk00000003/sig000002ea ), + .S(\blk00000003/sig00000358 ), + .O(\NLW_blk00000003/blk000000e1_O_UNCONNECTED ), + .LO(\blk00000003/sig00000355 ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000355 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000356 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000344 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000354 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000343 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000029e ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029e ), + .DI(\blk00000003/sig00000352 ), + .S(\blk00000003/sig00000353 ), + .O(\blk00000003/sig00000350 ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000350 ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig00000351 ), + .O(\blk00000003/sig0000034e ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig0000034e ), + .DI(\blk00000003/sig0000029e ), + .S(\blk00000003/sig0000034f ), + .O(\blk00000003/sig0000034b ), + .LO(\NLW_blk00000003/blk000000db_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig0000034b ), + .DI(\blk00000003/sig0000034c ), + .S(\blk00000003/sig0000034d ), + .O(\blk00000003/sig00000349 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000349 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig0000034a ), + .O(\blk00000003/sig00000345 ), + .LO(\NLW_blk00000003/blk000000d9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000347 ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig00000348 ), + .O(\NLW_blk00000003/blk000000d8_O_UNCONNECTED ), + .LO(\blk00000003/sig00000343 ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000345 ), + .DI(\blk00000003/sig0000030e ), + .S(\blk00000003/sig00000346 ), + .O(\blk00000003/sig00000347 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000343 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000344 ) + ); + FDE \blk00000003/blk000000d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/sig00000342 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000340 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000338 ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000033b ), + .LI(\blk00000003/sig0000033e ), + .O(\blk00000003/sig0000033f ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig0000033b ), + .DI(\blk00000003/sig0000033d ), + .S(\blk00000003/sig0000033e ), + .O(\NLW_blk00000003/blk000000d1_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000338 ), + .LI(\blk00000003/sig0000033a ), + .O(\blk00000003/sig0000033c ) + ); + MUXCY_L \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000338 ), + .DI(\blk00000003/sig00000339 ), + .S(\blk00000003/sig0000033a ), + .LO(\blk00000003/sig0000033b ) + ); + MUXCY_L \blk00000003/blk000000ce ( + .CI(\blk00000003/sig0000032f ), + .DI(\blk00000003/sig00000337 ), + .S(\blk00000003/sig00000330 ), + .LO(\blk00000003/sig00000332 ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000332 ), + .DI(\blk00000003/sig00000336 ), + .S(\blk00000003/sig00000333 ), + .O(\NLW_blk00000003/blk000000cd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000335 ), + .O(\blk00000003/sig0000032f ) + ); + XORCY \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000332 ), + .LI(\blk00000003/sig00000333 ), + .O(\blk00000003/sig00000334 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000032f ), + .LI(\blk00000003/sig00000330 ), + .O(\blk00000003/sig00000331 ) + ); + MUXCY_L \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig0000032e ), + .S(\blk00000003/sig0000032c ), + .LO(\blk00000003/sig00000328 ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000032c ), + .O(\blk00000003/sig0000032d ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000328 ), + .DI(\blk00000003/sig0000032b ), + .S(\blk00000003/sig00000329 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000328 ), + .LI(\blk00000003/sig00000329 ), + .O(\blk00000003/sig0000032a ) + ); + MUXCY_L \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000327 ), + .S(\blk00000003/sig00000325 ), + .LO(\blk00000003/sig00000321 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000325 ), + .O(\blk00000003/sig00000326 ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig00000321 ), + .DI(\blk00000003/sig00000324 ), + .S(\blk00000003/sig00000322 ), + .O(\NLW_blk00000003/blk000000c3_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000321 ), + .LI(\blk00000003/sig00000322 ), + .O(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c1 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c0 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000318 ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000316 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000314 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000313 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000311 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030f ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/sig0000030d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000303 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000300 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000b1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002fb ), + .R(coef_ld), + .Q(\blk00000003/sig000002f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002f6 ), + .R(coef_ld), + .Q(\blk00000003/sig000002f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ed ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000030a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000030b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000308 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000309 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000306 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000307 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000304 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000305 ) + ); + XORCY \blk00000003/blk000000a9 ( + .CI(\blk00000003/sig00000302 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000303 ) + ); + MUXCY \blk00000003/blk000000a8 ( + .CI(\blk00000003/sig00000302 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a8_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a7 ( + .CI(\blk00000003/sig000002ff ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000301 ), + .O(\blk00000003/sig00000302 ), + .LO(\NLW_blk00000003/blk000000a7_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a6 ( + .CI(\blk00000003/sig000002fe ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000300 ) + ); + MUXCY \blk00000003/blk000000a5 ( + .CI(\blk00000003/sig000002fe ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002ff ) + ); + MUXCY_D \blk00000003/blk000000a4 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fd ), + .O(\blk00000003/sig000002fe ), + .LO(\NLW_blk00000003/blk000000a4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a3 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002fc ), + .O(\blk00000003/sig000002f8 ), + .LO(\NLW_blk00000003/blk000000a3_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000a2 ( + .CI(\blk00000003/sig000002fa ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002fb ) + ); + MUXCY \blk00000003/blk000000a1 ( + .CI(\blk00000003/sig000002fa ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk000000a1_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000a0 ( + .CI(\blk00000003/sig000002f8 ), + .DI(\blk00000003/sig000002f9 ), + .S(coef_we), + .O(\blk00000003/sig000002fa ), + .LO(\NLW_blk00000003/blk000000a0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002f7 ), + .O(\blk00000003/sig000002f2 ), + .LO(\NLW_blk00000003/blk0000009f_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009e ( + .CI(\blk00000003/sig000002f5 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig000002f6 ) + ); + MUXCY \blk00000003/blk0000009d ( + .CI(\blk00000003/sig000002f5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk0000009d_O_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000009c ( + .CI(\blk00000003/sig000002f2 ), + .DI(\blk00000003/sig000002f3 ), + .S(\blk00000003/sig000002f4 ), + .O(\blk00000003/sig000002f5 ), + .LO(\NLW_blk00000003/blk0000009c_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000009b ( + .CI(\blk00000003/sig000002eb ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000002e9 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(\blk00000003/sig000002ef ), + .DI(\blk00000003/sig000002f0 ), + .S(\blk00000003/sig000002f1 ), + .O(\NLW_blk00000003/blk0000009a_O_UNCONNECTED ), + .LO(\blk00000003/sig000002eb ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig000002ec ), + .DI(\blk00000003/sig000002ed ), + .S(\blk00000003/sig000002ee ), + .O(\blk00000003/sig000002ef ), + .LO(\NLW_blk00000003/blk00000099_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002eb ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ec ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000097 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e9 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .R(sclr), + .Q(\blk00000003/sig000002b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b4 ), + .R(\blk00000003/sig000002af ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .R(sclr), + .Q(\blk00000003/sig000002b3 ) + ); + FDRE \blk00000003/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002af ), + .Q(rdy) + ); + FDSE \blk00000003/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .S(sclr), + .Q(\blk00000003/sig000002ad ) + ); + FDRE \blk00000003/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002aa ), + .R(sclr), + .Q(\blk00000003/sig000002ab ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig00000296 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000293 ), + .R(sclr), + .Q(\blk00000003/sig000002a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(sclr), + .Q(\blk00000003/sig000002a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000024_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig000002a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig0000029f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000016e ), + .R(sclr), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000168 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000020_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000169 ), + .S(sclr), + .Q(\blk00000003/sig0000029d ) + ); + MUXCY \blk00000003/blk0000001e ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + XORCY \blk00000003/blk0000001d ( + .CI(\blk00000003/sig00000298 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig0000029a ) + ); + MUXCY \blk00000003/blk0000001c ( + .CI(\blk00000003/sig00000298 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000299 ) + ); + MUXCY_D \blk00000003/blk0000001b ( + .CI(\blk00000003/sig00000296 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000298 ), + .LO(\NLW_blk00000003/blk0000001b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000001a ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk0000001a_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk00000019 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000ac ), + .O(\NLW_blk00000003/blk00000019_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000018 ( + .CI(\blk00000003/sig00000292 ), + .LI(\blk00000003/sig00000049 ), + .O(\blk00000003/sig00000293 ) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000017 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000017_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000017_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000242 , \blk00000003/sig00000243 , \blk00000003/sig00000244 , +\blk00000003/sig00000245 , \blk00000003/sig00000246 , \blk00000003/sig00000247 , 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\NLW_blk00000003/blk00000017_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000017_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000017_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000252 , \blk00000003/sig00000253 , \blk00000003/sig00000254 , \blk00000003/sig00000255 , \blk00000003/sig00000256 , +\blk00000003/sig00000257 , \blk00000003/sig00000258 , \blk00000003/sig00000259 , \blk00000003/sig0000025a , \blk00000003/sig0000025b , +\blk00000003/sig0000025c , \blk00000003/sig0000025d , \blk00000003/sig0000025e , \blk00000003/sig0000025f , \blk00000003/sig00000260 , +\blk00000003/sig00000261 , \blk00000003/sig00000262 , \blk00000003/sig00000263 , \blk00000003/sig00000264 , \blk00000003/sig00000265 , +\blk00000003/sig00000266 , \blk00000003/sig00000267 , \blk00000003/sig00000268 , \blk00000003/sig00000269 , \blk00000003/sig0000026a , +\blk00000003/sig0000026b , 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\NLW_blk00000003/blk00000017_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000017_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000017_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , 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.B({\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , \blk00000003/sig0000020a , +\blk00000003/sig0000020a , \blk00000003/sig0000020b , \blk00000003/sig0000020c , \blk00000003/sig0000020d , \blk00000003/sig0000020e , +\blk00000003/sig0000020f , \blk00000003/sig00000210 , \blk00000003/sig00000211 }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , 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\NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + .M({\NLW_blk00000003/blk00000016_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000016_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000016_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000016_M<32>_UNCONNECTED , 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.RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000015_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000015_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , +\blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , +\blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , \blk00000003/sig000001c5 , \blk00000003/sig000001c6 , +\blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 }), + .BCOUT({\NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig000001ca , 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\blk00000003/sig000001b9 }), + .M({\NLW_blk00000003/blk00000015_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000015_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000015_M<0>_UNCONNECTED }) + ); + DSP48A1 #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000014 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000014_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000014_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , \blk00000003/sig00000170 , +\blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , +\blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 }), + .BCOUT({\NLW_blk00000003/blk00000014_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_BCOUT<0>_UNCONNECTED }), + .PCIN({\blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , +\blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , +\blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , +\blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , +\blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , +\blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , +\blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , +\blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , +\blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , +\blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000014_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000014_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000014_P<31>_UNCONNECTED , +\blk00000003/sig000000bf , \blk00000003/sig000000c0 , \blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , +\blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , \blk00000003/sig000000c8 , +\blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , +\blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , +\blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , +\blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , +\blk00000003/sig000000dd }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig0000015d , \blk00000003/sig0000015f , \blk00000003/sig00000161 }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .PCOUT({\NLW_blk00000003/blk00000014_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000014_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000014_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , +\blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , +\blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 }), + .M({\NLW_blk00000003/blk00000014_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000014_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000014_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000014_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000014_M<26>_UNCONNECTED , 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.O(\blk00000003/sig0000016d ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000000f ( + .CI(\blk00000003/sig00000168 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000169 ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig00000165 ), + .DI(\blk00000003/sig00000166 ), + .S(\blk00000003/sig00000167 ), + .O(\NLW_blk00000003/blk0000000e_O_UNCONNECTED ), + .LO(\blk00000003/sig00000168 ) + ); + MUXCY_D \blk00000003/blk0000000d ( + .CI(\blk00000003/sig00000162 ), + .DI(\blk00000003/sig00000163 ), + .S(\blk00000003/sig00000164 ), + .O(\blk00000003/sig00000165 ), + .LO(\NLW_blk00000003/blk0000000d_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000c ( + .C(clk), + .D(\blk00000003/sig00000160 ), + .Q(\blk00000003/sig00000161 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000b ( + .C(clk), + .D(\blk00000003/sig0000015e ), + .Q(\blk00000003/sig0000015f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000a ( + .C(clk), + .D(\blk00000003/sig0000015c ), + .Q(\blk00000003/sig0000015d ) + ); + XORCY \blk00000003/blk00000009 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000015a ), + .O(\blk00000003/sig0000015b ) + ); + MUXCY_D \blk00000003/blk00000008 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000159 ), + .S(\blk00000003/sig0000015a ), + .O(\NLW_blk00000003/blk00000008_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000008_LO_UNCONNECTED ) + ); + DSP48A1 #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CARRYOUTREG ( 0 ), + .CREG ( 1 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000007 ( + .CECARRYIN(ce), + .RSTC(\blk00000003/sig00000049 ), + .RSTCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEOPMODE(ce), + .CEC(ce), + .CARRYOUTF(\NLW_blk00000003/blk00000007_CARRYOUTF_UNCONNECTED ), + .RSTOPMODE(\blk00000003/sig00000049 ), + .RSTM(\blk00000003/sig00000049 ), + .CLK(clk), + .RSTB(\blk00000003/sig00000049 ), + .CEM(ce), + .CEB(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CEP(ce), + .CEA(ce), + .CARRYOUT(\NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .RSTP(\blk00000003/sig00000049 ), + .B({\blk00000003/sig00000103 , \blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , +\blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , +\blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , +\blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 }), + .BCOUT({\NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED , 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+\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .A({\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , +\blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , +\blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 }), + .M({\NLW_blk00000003/blk00000006_M<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<31>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<25>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<19>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<13>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<7>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_M<1>_UNCONNECTED , +\NLW_blk00000003/blk00000006_M<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000034/blk00000096 ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk00000034/sig000009d5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000095 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000095_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000094 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000094_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000093 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000093_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000092 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000092_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000091 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000091_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000090 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000090_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009d1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ce ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ca ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000008a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009cb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000089 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000088 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000087 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000086 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000085 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000084 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000083 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000082 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000081 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009c2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000080 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009be ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bd ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bf ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bb ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ba ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009bc ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000007a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000079 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b7 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000078 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000077 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000076 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000075 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000074 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000073 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b1 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000072 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000071 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009af ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000070 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ae ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009b0 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ac ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ab ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009ad ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a9 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk0000006a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a8 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000069 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009aa ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000068 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000067 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000034/blk00000066 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000034/sig000009a4 ), + .A3(\blk00000003/blk00000034/sig000009a4 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000002ad ), + .DPRA1(\blk00000003/sig000002ab ), + .DPRA2(\blk00000003/blk00000034/sig000009a4 ), + .DPRA3(\blk00000003/blk00000034/sig000009a4 ), + .WCLK(clk), + .WE(\blk00000003/blk00000034/sig000009d5 ), + .SPO(\NLW_blk00000003/blk00000034/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000034/sig000009a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d4 ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d2 ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d1 ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009d0 ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cf ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ce ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cd ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cc ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009cb ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ca ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c9 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c8 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c7 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c6 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c5 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c4 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c3 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c2 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c1 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009c0 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bf ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009be ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bd ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009bb ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ba ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009b0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009af ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ae ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ad ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ac ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009ab ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009aa ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000034/sig000009a5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk00000034/blk00000035 ( + .G(\blk00000003/blk00000034/sig000009a4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000130/blk00000152 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000130/sig00000a0c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000151 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/blk00000130/sig00000a0b ), + .Q15(\NLW_blk00000003/blk00000130/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000150 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/blk00000130/sig00000a0a ), + .Q15(\NLW_blk00000003/blk00000130/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk00000130/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk00000130/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk00000130/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk00000130/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk00000130/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk0000014a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk00000130/sig00000a04 ), + .Q15(\NLW_blk00000003/blk00000130/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000149 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk00000130/sig00000a03 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000148 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk00000130/sig00000a02 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000147 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk00000130/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000146 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk00000130/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000130/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000145 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk00000130/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000130/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000144 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk00000130/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000130/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000143 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk00000130/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000130/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000130/blk00000142 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000130/sig000009fb ), + .A3(\blk00000003/blk00000130/sig000009fb ), + .CE(\blk00000003/blk00000130/sig00000a0c ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk00000130/sig000009fc ), + .Q15(\NLW_blk00000003/blk00000130/blk00000142_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000141 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0b ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000140 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a0a ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a09 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a08 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a07 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a06 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a05 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a04 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a03 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a02 ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a01 ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig00000a00 ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009ff ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fe ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fd ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000130/sig000009fc ), + .Q(\blk00000003/sig000005e0 ) + ); + GND \blk00000003/blk00000130/blk00000131 ( + .G(\blk00000003/blk00000130/sig000009fb ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000175 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000153/sig00000a43 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/blk00000153/sig00000a42 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/blk00000153/sig00000a41 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/blk00000153/sig00000a40 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/blk00000153/sig00000a3f ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/blk00000153/sig00000a3e ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/blk00000153/sig00000a3d ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/blk00000153/sig00000a3c ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/blk00000153/sig00000a3b ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016c ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/blk00000153/sig00000a3a ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016b ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/blk00000153/sig00000a39 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016a ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/blk00000153/sig00000a38 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000169 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/blk00000153/sig00000a37 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000168 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/blk00000153/sig00000a36 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000167 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/blk00000153/sig00000a35 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000166 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/blk00000153/sig00000a34 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000165 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000153/sig00000a32 ), + .A3(\blk00000003/blk00000153/sig00000a32 ), + .CE(\blk00000003/blk00000153/sig00000a43 ), + .CLK(clk), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/blk00000153/sig00000a33 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000165_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a42 ), + .Q(\blk00000003/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a41 ), + .Q(\blk00000003/sig00000592 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a40 ), + .Q(\blk00000003/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3f ), + .Q(\blk00000003/sig00000594 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3e ), + .Q(\blk00000003/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3d ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3c ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3b ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a3a ), + .Q(\blk00000003/sig00000599 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a39 ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a38 ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a37 ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a36 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a35 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a34 ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000a33 ), + .Q(\blk00000003/sig000005a0 ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000a32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000176/blk00000198 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk00000176/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000197 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/blk00000176/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000197_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000196 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/blk00000176/sig00000a78 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000196_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000195 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/blk00000176/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000195_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000194 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/blk00000176/sig00000a76 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000194_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000193 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000665 ), + .Q(\blk00000003/blk00000176/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000193_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000192 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000666 ), + .Q(\blk00000003/blk00000176/sig00000a74 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000192_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000191 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000667 ), + .Q(\blk00000003/blk00000176/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000191_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000190 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000668 ), + .Q(\blk00000003/blk00000176/sig00000a72 ), + .Q15(\NLW_blk00000003/blk00000176/blk00000190_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018f ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000669 ), + .Q(\blk00000003/blk00000176/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018e ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066a ), + .Q(\blk00000003/blk00000176/sig00000a70 ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018d ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066b ), + .Q(\blk00000003/blk00000176/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018c ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066c ), + .Q(\blk00000003/blk00000176/sig00000a6e ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018b ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066d ), + .Q(\blk00000003/blk00000176/sig00000a6d ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk0000018a ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066e ), + .Q(\blk00000003/blk00000176/sig00000a6c ), + .Q15(\NLW_blk00000003/blk00000176/blk0000018a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000189 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig0000066f ), + .Q(\blk00000003/blk00000176/sig00000a6b ), + .Q15(\NLW_blk00000003/blk00000176/blk00000189_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000176/blk00000188 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk00000176/sig00000a69 ), + .A3(\blk00000003/blk00000176/sig00000a69 ), + .CE(\blk00000003/blk00000176/sig00000a7a ), + .CLK(clk), + .D(\blk00000003/sig00000670 ), + .Q(\blk00000003/blk00000176/sig00000a6a ), + .Q15(\NLW_blk00000003/blk00000176/blk00000188_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a79 ), + .Q(\blk00000003/sig00000621 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a78 ), + .Q(\blk00000003/sig00000622 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a77 ), + .Q(\blk00000003/sig00000623 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a76 ), + .Q(\blk00000003/sig00000624 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a75 ), + .Q(\blk00000003/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a74 ), + .Q(\blk00000003/sig00000626 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a73 ), + .Q(\blk00000003/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a72 ), + .Q(\blk00000003/sig00000628 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a71 ), + .Q(\blk00000003/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a70 ), + .Q(\blk00000003/sig0000062a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6f ), + .Q(\blk00000003/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6e ), + .Q(\blk00000003/sig0000062c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6d ), + .Q(\blk00000003/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk0000017a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6c ), + .Q(\blk00000003/sig0000062e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000179 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6b ), + .Q(\blk00000003/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176/blk00000178 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000176/sig00000a6a ), + .Q(\blk00000003/sig00000630 ) + ); + GND \blk00000003/blk00000176/blk00000177 ( + .G(\blk00000003/blk00000176/sig00000a69 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000199/blk000001bb ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk00000199/sig00000ab1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ba ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/blk00000199/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b9 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/blk00000199/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b8 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/blk00000199/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/blk00000199/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/blk00000199/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/blk00000199/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000199/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000199/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000199/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000199/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001b0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000199/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001af ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000199/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ae ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000199/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ad ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000199/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ac ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000199/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000199/blk000001ab ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk00000199/sig00000aa0 ), + .A3(\blk00000003/blk00000199/sig00000aa0 ), + .CE(\blk00000003/blk00000199/sig00000ab1 ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000199/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000199/blk000001ab_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000ab0 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaf ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aae ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aad ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aac ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aab ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aaa ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa9 ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa8 ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa7 ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk000001a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa6 ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa5 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa4 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa3 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa2 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000199/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000199/sig00000aa1 ), + .Q(\blk00000003/sig000005f0 ) + ); + GND \blk00000003/blk00000199/blk0000019a ( + .G(\blk00000003/blk00000199/sig00000aa0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001bc/blk000001de ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000001bc/sig00000ae8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dd ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk000001bc/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001dc ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk000001bc/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001db ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk000001bc/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001da ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk000001bc/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d9 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk000001bc/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d8 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk000001bc/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d7 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk000001bc/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d6 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk000001bc/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d5 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk000001bc/sig00000adf ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d4 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk000001bc/sig00000ade ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d3 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk000001bc/sig00000add ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d2 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk000001bc/sig00000adc ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d1 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk000001bc/sig00000adb ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001d0 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk000001bc/sig00000ada ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001cf ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk000001bc/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001bc/blk000001ce ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000001bc/sig00000ad7 ), + .A3(\blk00000003/blk000001bc/sig00000ad7 ), + .CE(\blk00000003/blk000001bc/sig00000ae8 ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk000001bc/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk000001bc/blk000001ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae7 ), + .Q(\blk00000003/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae6 ), + .Q(\blk00000003/sig00000642 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae5 ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae4 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae3 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae2 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae1 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ae0 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adf ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ade ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000add ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adc ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000adb ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ada ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad9 ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001bc/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001bc/sig00000ad8 ), + .Q(\blk00000003/sig00000650 ) + ); + GND \blk00000003/blk000001bc/blk000001bd ( + .G(\blk00000003/blk000001bc/sig00000ad7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001df/blk00000201 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk000001df/sig00000b1f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk00000200 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk000001df/sig00000b1e ), + .Q15(\NLW_blk00000003/blk000001df/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001ff ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk000001df/sig00000b1d ), + .Q15(\NLW_blk00000003/blk000001df/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fe ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk000001df/sig00000b1c ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fd ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk000001df/sig00000b1b ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fc ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk000001df/sig00000b1a ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fb ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk000001df/sig00000b19 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001fa ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk000001df/sig00000b18 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001fa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f9 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk000001df/sig00000b17 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f8 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk000001df/sig00000b16 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f7 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk000001df/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f6 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk000001df/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f5 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk000001df/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f4 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk000001df/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f3 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk000001df/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f2 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/blk000001df/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001df/blk000001f1 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk000001df/sig00000b0e ), + .A3(\blk00000003/blk000001df/sig00000b0e ), + .CE(\blk00000003/blk000001df/sig00000b1f ), + .CLK(clk), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/blk000001df/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000001df/blk000001f1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1e ), + .Q(\blk00000003/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1d ), + .Q(\blk00000003/sig00000632 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1c ), + .Q(\blk00000003/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1b ), + .Q(\blk00000003/sig00000634 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b1a ), + .Q(\blk00000003/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b19 ), + .Q(\blk00000003/sig00000636 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b18 ), + .Q(\blk00000003/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b17 ), + .Q(\blk00000003/sig00000638 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b16 ), + .Q(\blk00000003/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b15 ), + .Q(\blk00000003/sig0000063a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b14 ), + .Q(\blk00000003/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b13 ), + .Q(\blk00000003/sig0000063c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b12 ), + .Q(\blk00000003/sig0000063d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b11 ), + .Q(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b10 ), + .Q(\blk00000003/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001df/blk000001e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001df/sig00000b0f ), + .Q(\blk00000003/sig00000640 ) + ); + GND \blk00000003/blk000001df/blk000001e0 ( + .G(\blk00000003/blk000001df/sig00000b0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000202/blk00000224 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk00000202/sig00000b56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000223 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000202/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000223_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000222 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000202/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000222_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000221 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000202/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000221_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000220 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000202/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000220_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000202/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000202/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000202/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000202/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000202/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk0000021a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000202/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000202/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000219 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000202/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000202/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000218 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000202/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000202/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000217 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk00000202/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000216 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk00000202/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000215 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk00000202/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202/blk00000214 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk00000202/sig00000b45 ), + .A3(\blk00000003/blk00000202/sig00000b45 ), + .CE(\blk00000003/blk00000202/sig00000b56 ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk00000202/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000202/blk00000214_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b55 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b54 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b53 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000210 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b52 ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b51 ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b50 ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4f ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4e ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4d ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk0000020a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4c ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000209 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4b ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000208 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b4a ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000207 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b49 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000206 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b48 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b47 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000202/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000202/sig00000b46 ), + .Q(\blk00000003/sig00000670 ) + ); + GND \blk00000003/blk00000202/blk00000203 ( + .G(\blk00000003/blk00000202/sig00000b45 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000225/blk00000247 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000225/sig00000b8d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000246 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/blk00000225/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000225/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000245 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/blk00000225/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000225/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000244 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/blk00000225/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000225/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000243 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/blk00000225/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000242 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/blk00000225/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000241 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/blk00000225/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000240 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/blk00000225/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000225/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/blk00000225/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/blk00000225/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/blk00000225/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/blk00000225/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/blk00000225/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk0000023a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/blk00000225/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000225/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000239 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/blk00000225/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000225/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000238 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/blk00000225/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000225/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000225/blk00000237 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000225/sig00000b7c ), + .A3(\blk00000003/blk00000225/sig00000b7c ), + .CE(\blk00000003/blk00000225/sig00000b8d ), + .CLK(clk), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/blk00000225/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000225/blk00000237_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8c ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8b ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b8a ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b89 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b88 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b87 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b86 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b85 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b84 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b83 ), + .Q(\blk00000003/sig0000065a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b82 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b81 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b80 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7f ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7e ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000225/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000225/sig00000b7d ), + .Q(\blk00000003/sig00000660 ) + ); + GND \blk00000003/blk00000225/blk00000226 ( + .G(\blk00000003/blk00000225/sig00000b7c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000248/blk0000026a ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000248/sig00000bc4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000269 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/blk00000248/sig00000bc3 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000268 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/blk00000248/sig00000bc2 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000267 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/blk00000248/sig00000bc1 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000266 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/blk00000248/sig00000bc0 ), + .Q15(\NLW_blk00000003/blk00000248/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000265 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/blk00000248/sig00000bbf ), + .Q15(\NLW_blk00000003/blk00000248/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000264 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/blk00000248/sig00000bbe ), + .Q15(\NLW_blk00000003/blk00000248/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000263 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/blk00000248/sig00000bbd ), + .Q15(\NLW_blk00000003/blk00000248/blk00000263_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000262 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/blk00000248/sig00000bbc ), + .Q15(\NLW_blk00000003/blk00000248/blk00000262_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000261 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/blk00000248/sig00000bbb ), + .Q15(\NLW_blk00000003/blk00000248/blk00000261_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk00000260 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/blk00000248/sig00000bba ), + .Q15(\NLW_blk00000003/blk00000248/blk00000260_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/blk00000248/sig00000bb9 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025e ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/blk00000248/sig00000bb8 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025d ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/blk00000248/sig00000bb7 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/blk00000248/sig00000bb6 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/blk00000248/sig00000bb5 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000248/blk0000025a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000248/sig00000bb3 ), + .A3(\blk00000003/blk00000248/sig00000bb3 ), + .CE(\blk00000003/blk00000248/sig00000bc4 ), + .CLK(clk), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/blk00000248/sig00000bb4 ), + .Q15(\NLW_blk00000003/blk00000248/blk0000025a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc3 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc2 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc1 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bc0 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbf ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbe ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbd ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbc ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bbb ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bba ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb9 ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb8 ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb7 ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb6 ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb5 ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000248/blk0000024a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000248/sig00000bb4 ), + .Q(\blk00000003/sig0000044c ) + ); + GND \blk00000003/blk00000248/blk00000249 ( + .G(\blk00000003/blk00000248/sig00000bb3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000026b/blk0000028d ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000026b/sig00000bfb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/blk0000026b/sig00000bfa ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/blk0000026b/sig00000bf9 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000028a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/blk0000026b/sig00000bf8 ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000028a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000289 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/blk0000026b/sig00000bf7 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000289_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000288 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/blk0000026b/sig00000bf6 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000288_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000287 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/blk0000026b/sig00000bf5 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000287_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000286 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/blk0000026b/sig00000bf4 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000286_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000285 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk0000026b/sig00000bf3 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000285_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000284 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk0000026b/sig00000bf2 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000284_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000283 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/blk0000026b/sig00000bf1 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000282 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/blk0000026b/sig00000bf0 ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000281 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/blk0000026b/sig00000bef ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk00000280 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/blk0000026b/sig00000bee ), + .Q15(\NLW_blk00000003/blk0000026b/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/blk0000026b/sig00000bed ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/blk0000026b/sig00000bec ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000026b/blk0000027d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000026b/sig00000bea ), + .A3(\blk00000003/blk0000026b/sig00000bea ), + .CE(\blk00000003/blk0000026b/sig00000bfb ), + .CLK(clk), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/blk0000026b/sig00000beb ), + .Q15(\NLW_blk00000003/blk0000026b/blk0000027d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bfa ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf9 ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf8 ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000279 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf7 ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000278 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf6 ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000277 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf5 ), + .Q(\blk00000003/sig00000432 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000276 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf4 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000275 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf3 ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000274 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf2 ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000273 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf1 ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000272 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bf0 ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000271 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bef ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk00000270 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bee ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bed ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000bec ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000026b/blk0000026d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000026b/sig00000beb ), + .Q(\blk00000003/sig0000043c ) + ); + GND \blk00000003/blk0000026b/blk0000026c ( + .G(\blk00000003/blk0000026b/sig00000bea ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000028e/blk000002b0 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000028e/sig00000c32 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002af ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/blk0000028e/sig00000c31 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ae ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/blk0000028e/sig00000c30 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ad ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/blk0000028e/sig00000c2f ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ac ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/blk0000028e/sig00000c2e ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002ab ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/blk0000028e/sig00000c2d ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002aa ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/blk0000028e/sig00000c2c ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a9 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/blk0000028e/sig00000c2b ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a8 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/blk0000028e/sig00000c2a ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a7 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/blk0000028e/sig00000c29 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a6 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/blk0000028e/sig00000c28 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a5 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/blk0000028e/sig00000c27 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a4 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/blk0000028e/sig00000c26 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a3 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/blk0000028e/sig00000c25 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a2 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/blk0000028e/sig00000c24 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a1 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/blk0000028e/sig00000c23 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000028e/blk000002a0 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000028e/sig00000c21 ), + .A3(\blk00000003/blk0000028e/sig00000c21 ), + .CE(\blk00000003/blk0000028e/sig00000c32 ), + .CLK(clk), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/blk0000028e/sig00000c22 ), + .Q15(\NLW_blk00000003/blk0000028e/blk000002a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c31 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c30 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2f ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2e ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2d ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2c ), + .Q(\blk00000003/sig00000492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2b ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c2a ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c29 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c28 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c27 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c26 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c25 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c24 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c23 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000028e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000028e/sig00000c22 ), + .Q(\blk00000003/sig0000049c ) + ); + GND \blk00000003/blk0000028e/blk0000028f ( + .G(\blk00000003/blk0000028e/sig00000c21 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002d3 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk000002b1/sig00000c69 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d2 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/blk000002b1/sig00000c68 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d1 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/blk000002b1/sig00000c67 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002d0 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/blk000002b1/sig00000c66 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cf ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/blk000002b1/sig00000c65 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ce ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/blk000002b1/sig00000c64 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cd ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/blk000002b1/sig00000c63 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cc ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk000002b1/sig00000c62 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002cb ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk000002b1/sig00000c61 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002ca ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk000002b1/sig00000c60 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c9 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk000002b1/sig00000c5f ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c8 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk000002b1/sig00000c5e ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c7 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk000002b1/sig00000c5d ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c6 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk000002b1/sig00000c5c ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c5 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk000002b1/sig00000c5b ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c4 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk000002b1/sig00000c5a ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b1/blk000002c3 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk000002b1/sig00000c58 ), + .A3(\blk00000003/blk000002b1/sig00000c58 ), + .CE(\blk00000003/blk000002b1/sig00000c69 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk000002b1/sig00000c59 ), + .Q15(\NLW_blk00000003/blk000002b1/blk000002c3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c68 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c67 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c66 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c65 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c64 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c63 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c62 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c61 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c60 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c5a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig00000c59 ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig00000c58 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002d4/blk0000030c ( + .I0(\blk00000003/sig00000307 ), + .I1(ce), + .O(\blk00000003/blk000002d4/sig00000cce ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030b ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cbb ), + .DPO(\blk00000003/blk000002d4/sig00000ccd ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk0000030a ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cba ), + .DPO(\blk00000003/blk000002d4/sig00000ccc ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000309 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb9 ), + .DPO(\blk00000003/blk000002d4/sig00000ccb ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000308 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb8 ), + .DPO(\blk00000003/blk000002d4/sig00000cca ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000307 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb7 ), + .DPO(\blk00000003/blk000002d4/sig00000cc9 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000306 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb6 ), + .DPO(\blk00000003/blk000002d4/sig00000cc8 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000305 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb4 ), + .DPO(\blk00000003/blk000002d4/sig00000cc6 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk000002d4/blk00000304 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb3 ), + .DPO(\blk00000003/blk000002d4/sig00000cc5 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk000002d4/blk00000303 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb5 ), + .DPO(\blk00000003/blk000002d4/sig00000cc7 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk000002d4/blk00000302 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb2 ), + .DPO(\blk00000003/blk000002d4/sig00000cc4 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk000002d4/blk00000301 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb1 ), + .DPO(\blk00000003/blk000002d4/sig00000cc3 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk000002d4/blk00000300 ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cb0 ), + .DPO(\blk00000003/blk000002d4/sig00000cc2 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002d4/blk000002ff ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caf ), + .DPO(\blk00000003/blk000002d4/sig00000cc1 ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fe ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cae ), + .DPO(\blk00000003/blk000002d4/sig00000cc0 ) + ); + RAM16X1D #( + .INIT ( 16'h0004 )) + \blk00000003/blk000002d4/blk000002fd ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cad ), + .DPO(\blk00000003/blk000002d4/sig00000cbf ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk000002d4/blk000002fc ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cab ), + .DPO(\blk00000003/blk000002d4/sig00000cbd ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fb ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000caa ), + .DPO(\blk00000003/blk000002d4/sig00000cbc ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk000002d4/blk000002fa ( + .A0(\blk00000003/sig00000339 ), + .A1(\blk00000003/sig0000033d ), + .A2(\blk00000003/sig00000340 ), + .A3(\blk00000003/blk000002d4/sig00000ca9 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000390 ), + .DPRA1(\blk00000003/sig00000394 ), + .DPRA2(\blk00000003/sig0000039a ), + .DPRA3(\blk00000003/blk000002d4/sig00000ca9 ), + .WCLK(clk), + .WE(\blk00000003/blk000002d4/sig00000cce ), + .SPO(\blk00000003/blk000002d4/sig00000cac ), + .DPO(\blk00000003/blk000002d4/sig00000cbe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccd ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccc ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000ccb ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cca ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc9 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc8 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc7 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc6 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc5 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc4 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc3 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc2 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc1 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cc0 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbf ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbe ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbd ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbc ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cbb ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cba ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb9 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb8 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb7 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb6 ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb5 ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb4 ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb3 ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb2 ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb1 ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cb0 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caf ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cae ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cad ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cac ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000cab ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002d4/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002d4/sig00000caa ), + .Q(\blk00000003/sig00000730 ) + ); + GND \blk00000003/blk000002d4/blk000002d5 ( + .G(\blk00000003/blk000002d4/sig00000ca9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000030d/blk00000345 ( + .I0(\blk00000003/sig00000677 ), + .I1(ce), + .O(\blk00000003/blk0000030d/sig00000d33 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000344 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000071f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d20 ), + .DPO(\blk00000003/blk0000030d/sig00000d32 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000343 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000720 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1f ), + .DPO(\blk00000003/blk0000030d/sig00000d31 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000342 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000721 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1e ), + .DPO(\blk00000003/blk0000030d/sig00000d30 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000341 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000722 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1d ), + .DPO(\blk00000003/blk0000030d/sig00000d2f ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk0000030d/blk00000340 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000723 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1c ), + .DPO(\blk00000003/blk0000030d/sig00000d2e ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk0000030d/blk0000033f ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000724 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1b ), + .DPO(\blk00000003/blk0000030d/sig00000d2d ) + ); + RAM16X1D #( + .INIT ( 16'h0008 )) + \blk00000003/blk0000030d/blk0000033e ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000726 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d19 ), + .DPO(\blk00000003/blk0000030d/sig00000d2b ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk0000030d/blk0000033d ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000727 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d18 ), + .DPO(\blk00000003/blk0000030d/sig00000d2a ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk0000033c ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000725 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d1a ), + .DPO(\blk00000003/blk0000030d/sig00000d2c ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk0000033b ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000728 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d17 ), + .DPO(\blk00000003/blk0000030d/sig00000d29 ) + ); + RAM16X1D #( + .INIT ( 16'h0006 )) + \blk00000003/blk0000030d/blk0000033a ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000729 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d16 ), + .DPO(\blk00000003/blk0000030d/sig00000d28 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk0000030d/blk00000339 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072a ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d15 ), + .DPO(\blk00000003/blk0000030d/sig00000d27 ) + ); + RAM16X1D #( + .INIT ( 16'h000A )) + \blk00000003/blk0000030d/blk00000338 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072b ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d14 ), + .DPO(\blk00000003/blk0000030d/sig00000d26 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000337 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072c ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d13 ), + .DPO(\blk00000003/blk0000030d/sig00000d25 ) + ); + RAM16X1D #( + .INIT ( 16'h0003 )) + \blk00000003/blk0000030d/blk00000336 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072d ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d12 ), + .DPO(\blk00000003/blk0000030d/sig00000d24 ) + ); + RAM16X1D #( + .INIT ( 16'h000B )) + \blk00000003/blk0000030d/blk00000335 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072f ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d10 ), + .DPO(\blk00000003/blk0000030d/sig00000d22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk0000030d/blk00000334 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig00000730 ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d0f ), + .DPO(\blk00000003/blk0000030d/sig00000d21 ) + ); + RAM16X1D #( + .INIT ( 16'h000F )) + \blk00000003/blk0000030d/blk00000333 ( + .A0(\blk00000003/sig00000671 ), + .A1(\blk00000003/sig00000672 ), + .A2(\blk00000003/sig00000673 ), + .A3(\blk00000003/blk0000030d/sig00000d0e ), + .D(\blk00000003/sig0000072e ), + .DPRA0(\blk00000003/sig00000681 ), + .DPRA1(\blk00000003/sig0000067f ), + .DPRA2(\blk00000003/sig0000067d ), + .DPRA3(\blk00000003/blk0000030d/sig00000d0e ), + .WCLK(clk), + .WE(\blk00000003/blk0000030d/sig00000d33 ), + .SPO(\blk00000003/blk0000030d/sig00000d11 ), + .DPO(\blk00000003/blk0000030d/sig00000d23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d32 ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d31 ), + .Q(\blk00000003/sig00000570 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d30 ), + .Q(\blk00000003/sig00000571 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2f ), + .Q(\blk00000003/sig00000572 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2e ), + .Q(\blk00000003/sig00000573 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2d ), + .Q(\blk00000003/sig00000574 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2c ), + .Q(\blk00000003/sig00000575 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2b ), + .Q(\blk00000003/sig00000576 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d2a ), + .Q(\blk00000003/sig00000577 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d29 ), + .Q(\blk00000003/sig00000578 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d28 ), + .Q(\blk00000003/sig00000579 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d27 ), + .Q(\blk00000003/sig0000057a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d26 ), + .Q(\blk00000003/sig0000057b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d25 ), + .Q(\blk00000003/sig0000057c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d24 ), + .Q(\blk00000003/sig0000057d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d23 ), + .Q(\blk00000003/sig0000057e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d22 ), + .Q(\blk00000003/sig0000057f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d21 ), + .Q(\blk00000003/sig00000580 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d20 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1f ), + .Q(\blk00000003/sig00000732 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1e ), + .Q(\blk00000003/sig00000733 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1d ), + .Q(\blk00000003/sig00000734 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1c ), + .Q(\blk00000003/sig00000735 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1b ), + .Q(\blk00000003/sig00000736 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d1a ), + .Q(\blk00000003/sig00000737 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d19 ), + .Q(\blk00000003/sig00000738 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d18 ), + .Q(\blk00000003/sig00000739 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d17 ), + .Q(\blk00000003/sig0000073a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000316 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d16 ), + .Q(\blk00000003/sig0000073b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d15 ), + .Q(\blk00000003/sig0000073c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d14 ), + .Q(\blk00000003/sig0000073d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d13 ), + .Q(\blk00000003/sig0000073e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d12 ), + .Q(\blk00000003/sig0000073f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d11 ), + .Q(\blk00000003/sig00000740 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d10 ), + .Q(\blk00000003/sig00000741 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000030d/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000030d/sig00000d0f ), + .Q(\blk00000003/sig00000742 ) + ); + GND \blk00000003/blk0000030d/blk0000030e ( + .G(\blk00000003/blk0000030d/sig00000d0e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000386/blk000003ac ( + .I0(\blk00000003/sig00000678 ), + .I1(ce), + .O(\blk00000003/blk00000386/sig00000d74 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003ab ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000731 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003ab_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d73 ) + ); + RAM16X1D #( + .INIT ( 16'h000D )) + \blk00000003/blk00000386/blk000003aa ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000732 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003aa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d72 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk000003a9 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000733 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d71 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a8 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000734 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d70 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a7 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000735 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6f ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a6 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000736 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6e ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk000003a5 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000738 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6c ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a4 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000739 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6b ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk000003a3 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000737 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6d ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk000003a2 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073a ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d6a ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk000003a1 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073b ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d69 ) + ); + RAM16X1D #( + .INIT ( 16'h000C )) + \blk00000003/blk00000386/blk000003a0 ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073c ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk000003a0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d68 ) + ); + RAM16X1D #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000386/blk0000039f ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073d ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d67 ) + ); + RAM16X1D #( + .INIT ( 16'h0005 )) + \blk00000003/blk00000386/blk0000039e ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073e ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d66 ) + ); + RAM16X1D #( + .INIT ( 16'h0007 )) + \blk00000003/blk00000386/blk0000039d ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig0000073f ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d65 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000386/blk0000039c ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000741 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d63 ) + ); + RAM16X1D #( + .INIT ( 16'h0009 )) + \blk00000003/blk00000386/blk0000039b ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000742 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d62 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk00000386/blk0000039a ( + .A0(\blk00000003/sig00000674 ), + .A1(\blk00000003/sig00000675 ), + .A2(\blk00000003/sig00000676 ), + .A3(\blk00000003/blk00000386/sig00000d61 ), + .D(\blk00000003/sig00000740 ), + .DPRA0(\blk00000003/sig00000682 ), + .DPRA1(\blk00000003/sig00000680 ), + .DPRA2(\blk00000003/sig0000067e ), + .DPRA3(\blk00000003/blk00000386/sig00000d61 ), + .WCLK(clk), + .WE(\blk00000003/blk00000386/sig00000d74 ), + .SPO(\NLW_blk00000003/blk00000386/blk0000039a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000386/sig00000d64 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d73 ), + .Q(\blk00000003/sig0000050d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d72 ), + .Q(\blk00000003/sig0000050e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d71 ), + .Q(\blk00000003/sig0000050f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d70 ), + .Q(\blk00000003/sig00000510 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6f ), + .Q(\blk00000003/sig00000511 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6e ), + .Q(\blk00000003/sig00000512 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6d ), + .Q(\blk00000003/sig00000513 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6c ), + .Q(\blk00000003/sig00000514 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6b ), + .Q(\blk00000003/sig00000515 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d6a ), + .Q(\blk00000003/sig00000516 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d69 ), + .Q(\blk00000003/sig00000517 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d68 ), + .Q(\blk00000003/sig00000518 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d67 ), + .Q(\blk00000003/sig00000519 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d66 ), + .Q(\blk00000003/sig0000051a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d65 ), + .Q(\blk00000003/sig0000051b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d64 ), + .Q(\blk00000003/sig0000051c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d63 ), + .Q(\blk00000003/sig0000051d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000386/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000386/sig00000d62 ), + .Q(\blk00000003/sig0000051e ) + ); + GND \blk00000003/blk00000386/blk00000387 ( + .G(\blk00000003/blk00000386/sig00000d61 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ad/blk000003bf ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003ad/sig00000d93 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003be ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000003ad/sig00000d92 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003be_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000003ad/sig00000d91 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bc ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000003ad/sig00000d90 ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003bb ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000003ad/sig00000d8f ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003bb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003ba ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000003ad/sig00000d8e ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003ba_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b9 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000003ad/sig00000d8d ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b8 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000003ad/sig00000d8c ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ad/blk000003b7 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003ad/sig00000d8a ), + .A3(\blk00000003/blk000003ad/sig00000d8a ), + .CE(\blk00000003/blk000003ad/sig00000d93 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000003ad/sig00000d8b ), + .Q15(\NLW_blk00000003/blk000003ad/blk000003b7_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d92 ), + .Q(\blk00000003/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d91 ), + .Q(\blk00000003/sig00000506 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d90 ), + .Q(\blk00000003/sig00000507 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8f ), + .Q(\blk00000003/sig00000508 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8e ), + .Q(\blk00000003/sig00000509 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8d ), + .Q(\blk00000003/sig0000050a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8c ), + .Q(\blk00000003/sig0000050b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ad/sig00000d8b ), + .Q(\blk00000003/sig0000050c ) + ); + GND \blk00000003/blk000003ad/blk000003ae ( + .G(\blk00000003/blk000003ad/sig00000d8a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003c0/blk000003d2 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003c0/sig00000db2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/blk000003c0/sig00000db1 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003d0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/blk000003c0/sig00000db0 ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cf ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/blk000003c0/sig00000daf ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ce ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/blk000003c0/sig00000dae ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cd ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/blk000003c0/sig00000dad ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cc ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/blk000003c0/sig00000dac ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003cb ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/blk000003c0/sig00000dab ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003c0/blk000003ca ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003c0/sig00000da9 ), + .A3(\blk00000003/blk000003c0/sig00000da9 ), + .CE(\blk00000003/blk000003c0/sig00000db2 ), + .CLK(clk), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/blk000003c0/sig00000daa ), + .Q15(\NLW_blk00000003/blk000003c0/blk000003ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db1 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000db0 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daf ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dae ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dad ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dac ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000dab ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003c0/sig00000daa ), + .Q(\blk00000003/sig000004d4 ) + ); + GND \blk00000003/blk000003c0/blk000003c1 ( + .G(\blk00000003/blk000003c0/sig00000da9 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003d3/blk000003e5 ( + .I0(\blk00000003/sig0000067c ), + .I1(ce), + .O(\blk00000003/blk000003d3/sig00000dd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e4 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk000003d3/sig00000dd0 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e3 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk000003d3/sig00000dcf ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e2 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk000003d3/sig00000dce ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e1 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk000003d3/sig00000dcd ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003e0 ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk000003d3/sig00000dcc ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003df ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk000003d3/sig00000dcb ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003de ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk000003d3/sig00000dca ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003d3/blk000003dd ( + .A0(\blk00000003/sig0000068a ), + .A1(\blk00000003/sig00000688 ), + .A2(\blk00000003/blk000003d3/sig00000dc8 ), + .A3(\blk00000003/blk000003d3/sig00000dc8 ), + .CE(\blk00000003/blk000003d3/sig00000dd1 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk000003d3/sig00000dc9 ), + .Q15(\NLW_blk00000003/blk000003d3/blk000003dd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dd0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcf ), + .Q(\blk00000003/sig00000558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dce ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcd ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcc ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dcb ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dca ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003d3/sig00000dc9 ), + .Q(\blk00000003/sig0000055e ) + ); + GND \blk00000003/blk000003d3/blk000003d4 ( + .G(\blk00000003/blk000003d3/sig00000dc8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003e6/blk000003f8 ( + .I0(\blk00000003/sig0000067a ), + .I1(ce), + .O(\blk00000003/blk000003e6/sig00000df0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f7 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/blk000003e6/sig00000def ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f6 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/blk000003e6/sig00000dee ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f5 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/blk000003e6/sig00000ded ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f4 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/blk000003e6/sig00000dec ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f3 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/blk000003e6/sig00000deb ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f2 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/blk000003e6/sig00000dea ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f1 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/blk000003e6/sig00000de9 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003e6/blk000003f0 ( + .A0(\blk00000003/sig00000686 ), + .A1(\blk00000003/sig00000684 ), + .A2(\blk00000003/blk000003e6/sig00000de7 ), + .A3(\blk00000003/blk000003e6/sig00000de7 ), + .CE(\blk00000003/blk000003e6/sig00000df0 ), + .CLK(clk), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/blk000003e6/sig00000de8 ), + .Q15(\NLW_blk00000003/blk000003e6/blk000003f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000def ), + .Q(\blk00000003/sig0000051f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dee ), + .Q(\blk00000003/sig00000520 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000ded ), + .Q(\blk00000003/sig00000521 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dec ), + .Q(\blk00000003/sig00000522 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000deb ), + .Q(\blk00000003/sig00000523 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000dea ), + .Q(\blk00000003/sig00000524 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de9 ), + .Q(\blk00000003/sig00000525 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003e6/sig00000de8 ), + .Q(\blk00000003/sig00000526 ) + ); + GND \blk00000003/blk000003e6/blk000003e7 ( + .G(\blk00000003/blk000003e6/sig00000de7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003f9/blk0000040b ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk000003f9/sig00000e0f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk0000040a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a3 ), + .Q(\blk00000003/blk000003f9/sig00000e0e ), + .Q15(\NLW_blk00000003/blk000003f9/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000409 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a4 ), + .Q(\blk00000003/blk000003f9/sig00000e0d ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000408 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a5 ), + .Q(\blk00000003/blk000003f9/sig00000e0c ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000407 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a6 ), + .Q(\blk00000003/blk000003f9/sig00000e0b ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000406 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a7 ), + .Q(\blk00000003/blk000003f9/sig00000e0a ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000405 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a8 ), + .Q(\blk00000003/blk000003f9/sig00000e09 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000404 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003a9 ), + .Q(\blk00000003/blk000003f9/sig00000e08 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000404_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003f9/blk00000403 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk000003f9/sig00000e06 ), + .A3(\blk00000003/blk000003f9/sig00000e06 ), + .CE(\blk00000003/blk000003f9/sig00000e0f ), + .CLK(clk), + .D(\blk00000003/sig000003aa ), + .Q(\blk00000003/blk000003f9/sig00000e07 ), + .Q15(\NLW_blk00000003/blk000003f9/blk00000403_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0e ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0d ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0c ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0b ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e0a ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e09 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e08 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003f9/sig00000e07 ), + .Q(\blk00000003/sig0000056e ) + ); + GND \blk00000003/blk000003f9/blk000003fa ( + .G(\blk00000003/blk000003f9/sig00000e06 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000040c/blk0000041e ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk0000040c/sig00000e2e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/blk0000040c/sig00000e2d ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/blk0000040c/sig00000e2c ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041b ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/blk0000040c/sig00000e2b ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk0000041a ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/blk0000040c/sig00000e2a ), + .Q15(\NLW_blk00000003/blk0000040c/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000419 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/blk0000040c/sig00000e29 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000418 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/blk0000040c/sig00000e28 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000417 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/blk0000040c/sig00000e27 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000040c/blk00000416 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk0000040c/sig00000e25 ), + .A3(\blk00000003/blk0000040c/sig00000e25 ), + .CE(\blk00000003/blk0000040c/sig00000e2e ), + .CLK(clk), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/blk0000040c/sig00000e26 ), + .Q15(\NLW_blk00000003/blk0000040c/blk00000416_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000415 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2d ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000414 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2c ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000413 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2b ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000412 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e2a ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000411 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e29 ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk00000410 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e28 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e27 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c/blk0000040e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000040c/sig00000e26 ), + .Q(\blk00000003/sig00000566 ) + ); + GND \blk00000003/blk0000040c/blk0000040d ( + .G(\blk00000003/blk0000040c/sig00000e25 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f/blk00000431 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .O(\blk00000003/blk0000041f/sig00000e4d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000430 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f5 ), + .Q(\blk00000003/blk0000041f/sig00000e4c ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000430_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042f ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f6 ), + .Q(\blk00000003/blk0000041f/sig00000e4b ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042e ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f7 ), + .Q(\blk00000003/blk0000041f/sig00000e4a ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042d ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f8 ), + .Q(\blk00000003/blk0000041f/sig00000e49 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042c ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003f9 ), + .Q(\blk00000003/blk0000041f/sig00000e48 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042b ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fa ), + .Q(\blk00000003/blk0000041f/sig00000e47 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk0000042a ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fb ), + .Q(\blk00000003/blk0000041f/sig00000e46 ), + .Q15(\NLW_blk00000003/blk0000041f/blk0000042a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041f/blk00000429 ( + .A0(\blk00000003/sig00000689 ), + .A1(\blk00000003/sig00000687 ), + .A2(\blk00000003/blk0000041f/sig00000e44 ), + .A3(\blk00000003/blk0000041f/sig00000e44 ), + .CE(\blk00000003/blk0000041f/sig00000e4d ), + .CLK(clk), + .D(\blk00000003/sig000003fc ), + .Q(\blk00000003/blk0000041f/sig00000e45 ), + .Q15(\NLW_blk00000003/blk0000041f/blk00000429_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4c ), + .Q(\blk00000003/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4b ), + .Q(\blk00000003/sig0000058a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e4a ), + .Q(\blk00000003/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e49 ), + .Q(\blk00000003/sig0000058c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e48 ), + .Q(\blk00000003/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e47 ), + .Q(\blk00000003/sig0000058e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e46 ), + .Q(\blk00000003/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041f/sig00000e45 ), + .Q(\blk00000003/sig00000590 ) + ); + GND \blk00000003/blk0000041f/blk00000420 ( + .G(\blk00000003/blk0000041f/sig00000e44 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000432/blk00000444 ( + .I0(\blk00000003/sig00000679 ), + .I1(ce), + .O(\blk00000003/blk00000432/sig00000e6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000443 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/blk00000432/sig00000e6b ), + .Q15(\NLW_blk00000003/blk00000432/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000442 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/blk00000432/sig00000e6a ), + .Q15(\NLW_blk00000003/blk00000432/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000441 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/blk00000432/sig00000e69 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk00000440 ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/blk00000432/sig00000e68 ), + .Q15(\NLW_blk00000003/blk00000432/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043f ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/blk00000432/sig00000e67 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043e ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000432/sig00000e66 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043d ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000432/sig00000e65 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000432/blk0000043c ( + .A0(\blk00000003/sig00000685 ), + .A1(\blk00000003/sig00000683 ), + .A2(\blk00000003/blk00000432/sig00000e63 ), + .A3(\blk00000003/blk00000432/sig00000e63 ), + .CE(\blk00000003/blk00000432/sig00000e6c ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000432/sig00000e64 ), + .Q15(\NLW_blk00000003/blk00000432/blk0000043c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6b ), + .Q(\blk00000003/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk0000043a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e6a ), + .Q(\blk00000003/sig00000582 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000439 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e69 ), + .Q(\blk00000003/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000438 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e68 ), + .Q(\blk00000003/sig00000584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000437 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e67 ), + .Q(\blk00000003/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e66 ), + .Q(\blk00000003/sig00000586 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e65 ), + .Q(\blk00000003/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000432/sig00000e64 ), + .Q(\blk00000003/sig00000588 ) + ); + GND \blk00000003/blk00000432/blk00000433 ( + .G(\blk00000003/blk00000432/sig00000e63 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000445/blk00000457 ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk00000445/sig00000e8b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000456 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000445/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000445/blk00000456_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000455 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000445/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000455_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000454 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000445/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000454_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000453 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000445/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000453_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000452 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000445/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000452_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000451 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000445/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000451_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk00000450 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000445/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000445/blk00000450_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000445/blk0000044f ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk00000445/sig00000e82 ), + .A3(\blk00000003/blk00000445/sig00000e82 ), + .CE(\blk00000003/blk00000445/sig00000e8b ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000445/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000445/blk0000044f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e8a ), + .Q(\blk00000003/sig000003a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e89 ), + .Q(\blk00000003/sig000003a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e88 ), + .Q(\blk00000003/sig000003a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e87 ), + .Q(\blk00000003/sig000003a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk0000044a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e86 ), + .Q(\blk00000003/sig000003a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000449 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e85 ), + .Q(\blk00000003/sig000003a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000448 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e84 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445/blk00000447 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000445/sig00000e83 ), + .Q(\blk00000003/sig000003aa ) + ); + GND \blk00000003/blk00000445/blk00000446 ( + .G(\blk00000003/blk00000445/sig00000e82 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000458/blk0000046a ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk00000458/sig00000eaa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000469 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000458/sig00000ea9 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000469_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000468 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000458/sig00000ea8 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000468_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000467 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000458/sig00000ea7 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000467_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000466 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000458/sig00000ea6 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000466_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000465 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000458/sig00000ea5 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000465_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000464 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000458/sig00000ea4 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000464_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000463 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000458/sig00000ea3 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000463_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000458/blk00000462 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk00000458/sig00000ea1 ), + .A3(\blk00000003/blk00000458/sig00000ea1 ), + .CE(\blk00000003/blk00000458/sig00000eaa ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000458/sig00000ea2 ), + .Q15(\NLW_blk00000003/blk00000458/blk00000462_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea9 ), + .Q(\blk00000003/sig0000039b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea8 ), + .Q(\blk00000003/sig0000039c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea7 ), + .Q(\blk00000003/sig0000039d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea6 ), + .Q(\blk00000003/sig0000039e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea5 ), + .Q(\blk00000003/sig0000039f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea4 ), + .Q(\blk00000003/sig000003a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea3 ), + .Q(\blk00000003/sig000003a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000458/sig00000ea2 ), + .Q(\blk00000003/sig000003a2 ) + ); + GND \blk00000003/blk00000458/blk00000459 ( + .G(\blk00000003/blk00000458/sig00000ea1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000046b/blk0000047d ( + .I0(\blk00000003/sig0000068c ), + .I1(ce), + .O(\blk00000003/blk0000046b/sig00000ec9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047c ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk0000046b/sig00000ec8 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047b ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk0000046b/sig00000ec7 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk0000047a ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk0000046b/sig00000ec6 ), + .Q15(\NLW_blk00000003/blk0000046b/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000479 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk0000046b/sig00000ec5 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000478 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk0000046b/sig00000ec4 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000477 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk0000046b/sig00000ec3 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000476 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk0000046b/sig00000ec2 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000046b/blk00000475 ( + .A0(\blk00000003/sig00000387 ), + .A1(\blk00000003/sig00000386 ), + .A2(\blk00000003/blk0000046b/sig00000ec0 ), + .A3(\blk00000003/blk0000046b/sig00000ec0 ), + .CE(\blk00000003/blk0000046b/sig00000ec9 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk0000046b/sig00000ec1 ), + .Q15(\NLW_blk00000003/blk0000046b/blk00000475_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000474 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec8 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000473 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec7 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000472 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec6 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000471 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec5 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk00000470 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec4 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec3 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec2 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b/blk0000046d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000046b/sig00000ec1 ), + .Q(\blk00000003/sig000003fc ) + ); + GND \blk00000003/blk0000046b/blk0000046c ( + .G(\blk00000003/blk0000046b/sig00000ec0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000047e/blk00000490 ( + .I0(\blk00000003/sig0000068b ), + .I1(ce), + .O(\blk00000003/blk0000047e/sig00000ee8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048f ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk0000047e/sig00000ee7 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048e ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk0000047e/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048d ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk0000047e/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048c ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk0000047e/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048b ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk0000047e/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk0000048a ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk0000047e/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk0000047e/blk0000048a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000489 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk0000047e/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000489_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000488 ( + .A0(\blk00000003/sig0000038e ), + .A1(\blk00000003/sig0000038d ), + .A2(\blk00000003/blk0000047e/sig00000edf ), + .A3(\blk00000003/blk0000047e/sig00000edf ), + .CE(\blk00000003/blk0000047e/sig00000ee8 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk0000047e/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk0000047e/blk00000488_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee7 ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee6 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee5 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000484 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee4 ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000483 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee3 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000482 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee2 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000481 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee1 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000480 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000047e/sig00000ee0 ), + .Q(\blk00000003/sig000003f4 ) + ); + GND \blk00000003/blk0000047e/blk0000047f ( + .G(\blk00000003/blk0000047e/sig00000edf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e1/blk00000507 ( + .I0(\blk00000003/sig00000305 ), + .I1(ce), + .O(\blk00000003/blk000004e1/sig00000f25 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000506 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000506_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f24 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000505 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000505_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f23 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000504 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000070f ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000504_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f22 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000503 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000710 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000503_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f21 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000502 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000711 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000502_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f20 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000501 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000712 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000501_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1f ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk00000500 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000714 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk00000500_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1d ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004ff ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000715 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1c ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fe ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000713 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1e ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fd ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000716 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1b ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fc ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000717 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f1a ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fb ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000718 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f19 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004fa ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig00000719 ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004fa_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f18 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f9 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071a ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f17 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f8 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071b ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f16 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f7 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071d ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f14 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f6 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071e ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f13 ) + ); + RAM16X1D #( + .INIT ( 16'h0001 )) + \blk00000003/blk000004e1/blk000004f5 ( + .A0(\blk00000003/sig0000030c ), + .A1(\blk00000003/blk000004e1/sig00000f12 ), + .A2(\blk00000003/blk000004e1/sig00000f12 ), + .A3(\blk00000003/blk000004e1/sig00000f12 ), + .D(\blk00000003/sig0000071c ), + .DPRA0(\blk00000003/sig00000786 ), + .DPRA1(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA2(\blk00000003/blk000004e1/sig00000f12 ), + .DPRA3(\blk00000003/blk000004e1/sig00000f12 ), + .WCLK(clk), + .WE(\blk00000003/blk000004e1/sig00000f25 ), + .SPO(\NLW_blk00000003/blk000004e1/blk000004f5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004e1/sig00000f15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f24 ), + .Q(\blk00000003/sig000001a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f23 ), + .Q(\blk00000003/sig000001a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f22 ), + .Q(\blk00000003/sig000001aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f21 ), + .Q(\blk00000003/sig000001ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f20 ), + .Q(\blk00000003/sig000001ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1f ), + .Q(\blk00000003/sig000001ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1e ), + .Q(\blk00000003/sig000001ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1d ), + .Q(\blk00000003/sig000001af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1c ), + .Q(\blk00000003/sig000001b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1b ), + .Q(\blk00000003/sig000001b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f1a ), + .Q(\blk00000003/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f19 ), + .Q(\blk00000003/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f18 ), + .Q(\blk00000003/sig000001b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f17 ), + .Q(\blk00000003/sig000001b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f16 ), + .Q(\blk00000003/sig000001b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f15 ), + .Q(\blk00000003/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f14 ), + .Q(\blk00000003/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e1/sig00000f13 ), + .Q(\blk00000003/sig000001b9 ) + ); + GND \blk00000003/blk000004e1/blk000004e2 ( + .G(\blk00000003/blk000004e1/sig00000f12 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.veo b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.veo new file mode 100644 index 000000000..ce561daa2 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec2 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec2.v when simulating +// the core, hbdec2. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.xco b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.xco new file mode 100644 index 000000000..52eba9c26 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Tue Jun 9 23:48:14 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = fgg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=64 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=4 +CSET component_name=hbdec2 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=32 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-10-13T18:46:09Z +# END Extra information +GENERATE +# CRC: 7b386b7e diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_0.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_0.mif new file mode 100644 index 000000000..079623297 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_0.mif @@ -0,0 +1,9 @@ +111111111111000010 +000000000011000010 +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_1.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_1.mif new file mode 100644 index 000000000..d4a0b357e --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_1.mif @@ -0,0 +1,9 @@ +111111101000011111 +000000100110101110 +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_2.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_2.mif new file mode 100644 index 000000000..6d9d6044f --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto0_2.mif @@ -0,0 +1,9 @@ +111101110000011101 +000011100100101000 +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_flist.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_flist.txt new file mode 100644 index 000000000..d0a6a5443 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_flist.txt @@ -0,0 +1,19 @@ +# Output products list for +hbdec2.asy +hbdec2.gise +hbdec2.mif +hbdec2.ngc +hbdec2.v +hbdec2.veo +hbdec2.xco +hbdec2.xise +hbdec2COEFF_auto0_0.mif +hbdec2COEFF_auto0_1.mif +hbdec2COEFF_auto0_2.mif +hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +hbdec2_flist.txt +hbdec2_readme.txt +hbdec2_reload_addrfilt_decode_rom.mif +hbdec2_reload_order.txt +hbdec2_xmdf.tcl +hbdec2filt_decode_rom.mif diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_readme.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_readme.txt new file mode 100644 index 000000000..0b9324f9b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_readme.txt @@ -0,0 +1,73 @@ +The following files were generated for 'hbdec2' in directory +/home/mwest/git/fpgadev/usrp3/top/b205/coregen_dsp/ + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +ISE file generator: + Add description here... + + * hbdec2_flist.txt + +Model Parameter Resolution: + Resolves generated model parameter values on the component instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec2.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec2.ngc + * hbdec2.v + * hbdec2.veo + * hbdec2COEFF_auto0_0.mif + * hbdec2COEFF_auto0_1.mif + * hbdec2COEFF_auto0_2.mif + * hbdec2COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec2_reload_addrfilt_decode_rom.mif + * hbdec2filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec2.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec2.asy + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec2_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec2.gise + * hbdec2.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec2_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec2_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_order.txt b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_order.txt new file mode 100644 index 000000000..071b84e5b --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 16 +Reload index 1 = Index 18 +Reload index 2 = Index 20 +Reload index 3 = Index 22 +Reload index 4 = Index 8 +Reload index 5 = Index 10 +Reload index 6 = Index 12 +Reload index 7 = Index 14 +Reload index 8 = Index 0 +Reload index 9 = Index 2 +Reload index 10 = Index 4 +Reload index 11 = Index 6 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_xmdf.tcl b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_xmdf.tcl new file mode 100644 index 000000000..efebbe070 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2_xmdf.tcl @@ -0,0 +1,99 @@ +# The package naming convention is _xmdf +package provide hbdec2_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec2_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec2_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2 +} +# ::hbdec2_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec2_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2filt_decode_rom.mif b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2filt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/coregen_dsp/hbdec2filt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/b2xxmini/timing.ucf b/fpga/usrp3/top/b2xxmini/timing.ucf new file mode 100644 index 000000000..b10e37a14 --- /dev/null +++ b/fpga/usrp3/top/b2xxmini/timing.ucf @@ -0,0 +1,38 @@ +# 40 MHz main tcxo clock +NET "CLK_40MHz_FPGA*" TNM_NET = "CLK_40MHz_FPGA"; +TIMESPEC "TS_CLK_40MHz_FPGA" = PERIOD "CLK_40MHz_FPGA" 25000 ps HIGH 50 %; + +# 100 MHz GPIF clock +NET "FX3_PCLK" TNM_NET = "FX3_PCLK"; +TIMESPEC "TS_FX3_PCLK" = PERIOD "FX3_PCLK" 10000 ps HIGH 50 %; + +# data clock from catalina, sample rate dependent +# this clock equals sample rate in CMOS DDR 1R1T mode +# this clock is double the sample rate in CMOS DDR 2R2T mode +# Max clock rate is 61.44 MHz +NET "CAT_DCLK_P" TNM_NET = "CAT_DCLK_P"; +TIMESPEC "TS_CAT_DCLK_P" = PERIOD "CAT_DCLK_P" 16276 ps HIGH 50 %; + +#always use IOB for GPIF pins for awesome timing +INST "FX3_DQ*" IOB = TRUE; +INST "FX3_CTL*" IOB = TRUE; + +#low speed misc output group +INST "cFE_SEL_*" TNM = radio_misc_out; # Radio Clk domain +INST "cLED_*" TNM = radio_misc_out; # Radio Clk domain +INST "cTXDRV_PWEN*" TNM = radio_misc_out; # Radio Clk domain +INST "CAT_EN" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "CAT_SPI_EN" TNM = ls_misc_out; # Bus clk domain +INST "CAT_SPI_CLK" TNM = ls_misc_out; # Bus clk domain +INST "CAT_SPI_DO" TNM = ls_misc_out; # Bus clk domain (I) +INST "CAT_SPI_DI" TNM = ls_misc_out; # Bus clk domain + combinatorial +INST "CLK_40M_DAC_nSYNC" TNM = ls_misc_out; # Bus clk domain +INST "CLK_40M_DAC_SCLK" TNM = ls_misc_out; # Bus clk domain +INST "CLK_40M_DAC_DIN" TNM = ls_misc_out; # Bus clk domain + +#constrain the misc IOs to the clocks +NET "bus_clk" TNM_NET = "bus_clk"; +TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %; +TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING; +TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING; + diff --git a/fpga/usrp3/top/e31x/Makefile b/fpga/usrp3/top/e31x/Makefile new file mode 100644 index 000000000..a2ab64f1d --- /dev/null +++ b/fpga/usrp3/top/e31x/Makefile @@ -0,0 +1,101 @@ +# +# Copyright 2018 Ettus Research LLC +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP E3XX FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga_.bit: Configuration bitstream with header +## build/usrp__fpga_.dts: Device tree source file +## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= e31x + +DEFAULT_IMAGE_CORE_FILE_E31X=e31x_rfnoc_image_core.v +DEFAULT_EDGE_FILE_E31X=$(abspath e310_static_router.hex) + +# vivado_build($1=Device, $2=Definitions) +vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_E31X) + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream file..."; \ + cp build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \ + echo "Exporting build report..."; \ + cp build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \ + echo "Build DONE ... $(1)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- + +all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 E310_SG1_RFNOC E310_SG3_RFNOC ##(Default target) + +##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1). +E310_SG1_IDLE E3XX_idle: build/usrp_e310_sg1_idle_fpga.dts + $(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1) + $(call post_build,$@,E310_SG1_IDLE) + +##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3). +E310_SG3_IDLE E3XX_idle_sg3: build/usrp_e310_sg3_idle_fpga.dts + $(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1) + $(call post_build,$@,E310_SG3_IDLE) + +##E310_SG1: Build USRP E3XX (Speed Grade 1). +E310_SG1 E310: build/usrp_e310_sg1_fpga.dts + $(call vivado_build,E310_SG1, E310_SG1=1) + $(call post_build,$@,E310_SG1) + +##E310_SG3: Build USRP E3XX (Speed Grade 3). +E310_SG3 E310_sg3: build/usrp_e310_sg3_fpga.dts + $(call vivado_build,E310_SG3, E310_SG3=1) + $(call post_build,$@,E310_SG3) + + +build/%.dts: dts/%.dts dts/*.dtsi + -mkdir -p build + ${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $< + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-E3* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-E3* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc new file mode 100644 index 000000000..e4fc3538b --- /dev/null +++ b/fpga/usrp3/top/e31x/Makefile.e31x.inc @@ -0,0 +1,111 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include ../n3xx/coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/io_cap_gen/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## + +TOP_SRCS = \ +ppsloop.v \ +axi_pmu.v \ +spi_slave.v + +ifneq (IDLE,$(findstring IDLE, $(EXTRA_DEFS))) +TOP_SRCS += e31x.v +TOP_SRCS += e31x_core.v +TOP_SRCS += e310_io.v +TOP_SRCS += $(EDGE_FILE) $(IMAGE_CORE) +MB_XDC = \ +e31x_pins.xdc \ +e31x_timing.xdc +else +TOP_SRCS += e31x_idle.v +MB_XDC = \ +e31x_idle_pins.xdc +endif + +# The XDC files must be read in a specific order, motherboard first and then daughterboard. +# Outside of that, all the other sources can be read in any order desired. +DESIGN_SRCS = \ +$(abspath $(TOP_SRCS)) \ +$(CONTROL_LIB_SRCS) \ +$(IP_XCI_SRCS) \ +$(PACKET_PROC_SRCS) \ +$(AXI_SRCS) \ +$(FIFO_SRCS) \ +$(AURORA_PHY_SRCS) \ +$(BD_SRCS) \ +$(RADIO_SRCS) \ +$(RFNOC_SRCS) \ +$(TIMING_SRCS) \ +$(VITA_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(DRAM_SRCS) \ +$(COREGEN_DSP_SRCS) \ +$(DSP_SRCS) \ +$(LIB_IP_XCI_SRCS) \ +$(LIB_HLS_IP_SRCS) \ +$(EXTRAM_SRCS) \ +$(CAP_GEN_GENERIC_SRCS) \ +$(RFNOC_OOT_SRCS)\ +$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \ +$(RFNOC_BLOCK_EXAMPLE_SRCS) \ +$(abspath $(MB_XDC)) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_e31x.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/e31x/axi_pmu.v b/fpga/usrp3/top/e31x/axi_pmu.v new file mode 100644 index 000000000..97607c272 --- /dev/null +++ b/fpga/usrp3/top/e31x/axi_pmu.v @@ -0,0 +1,250 @@ +// +// Copyright 2015 Ettus Research, A National Instruments Company +// SPDX-License-Identifier: LGPL-3.0 +// +// Description: AXI PMU +// + +module axi_pmu +#( + parameter DEPTH = 64 +) +( + // sys connect + input s_axi_aclk, + input s_axi_areset, + + // spi slave port + input ss, + input mosi, + input sck, + output miso, + + // axi4 lite slave port + input [31:0] s_axi_awaddr, + input s_axi_awvalid, + output s_axi_awready, + + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_wvalid, + output s_axi_wready, + + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + input [31:0] s_axi_araddr, + input s_axi_arvalid, + output s_axi_arready, + + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input s_axi_rready, + + output s_axi_irq +); + + wire spi_stb; + wire [DEPTH-1:0] spi_rx; + wire [DEPTH-1:0] spi_tx; + + spi_slave inst_spi_slave0 + ( + .clk(s_axi_aclk), + .rst(s_axi_areset), + + .ss(ss), + .mosi(mosi), + .miso(miso), + .sck(sck), + + .parallel_stb(spi_stb), + .parallel_din(spi_tx), + .parallel_dout(spi_rx) + ); + + wire [7:0] rx_type = spi_rx[7:0]; + + reg [DEPTH-1:0] spi_rx_r0, spi_rx_r1, spi_rx_r2; + always @ (posedge s_axi_aclk) + if (s_axi_areset) begin + spi_rx_r0 <= 64'h0000_0000_0000_0000; + spi_rx_r1 <= 64'h0000_0000_0000_0000; + spi_rx_r2 <= 64'h0000_0000_0000_0000; + end else begin + spi_rx_r0 <= spi_stb && (rx_type == 0) ? spi_rx : spi_rx_r0; + spi_rx_r1 <= spi_stb && (rx_type == 1) ? spi_rx : spi_rx_r1; + spi_rx_r2 <= spi_stb && (rx_type == 2) ? spi_rx : spi_rx_r2; + end + + localparam IDLE = 3'b001; + localparam READ_IN_PROGRESS = 3'b010; + localparam WRITE_IN_PROGRESS = 3'b100; + + reg [2:0] state; + reg [7:0] addr; + + always @ (posedge s_axi_aclk) begin + if (s_axi_areset) begin + state <= IDLE; + end + else case (state) + + IDLE: begin + if (s_axi_arvalid) begin + state <= READ_IN_PROGRESS; + addr <= s_axi_araddr[7:0]; + end + else if (s_axi_awvalid) begin + state <= WRITE_IN_PROGRESS; + addr <= s_axi_awaddr[7:0]; + end + end + + READ_IN_PROGRESS: begin + if (s_axi_rready) + state <= IDLE; + end + + WRITE_IN_PROGRESS: begin + if (s_axi_bready) + state <= IDLE; + end + + default: begin + state <= IDLE; + end + + endcase + end + + // write mux + reg write_shutdown; + reg write_irq_mask; + + always @(*) begin + write_shutdown = 1'b0; + write_irq_mask = 1'b0; + + if (state == WRITE_IN_PROGRESS) + case (addr) + 8'h00: write_shutdown = 1'b1; + 8'h04: write_irq_mask = 1'b1; + endcase + end + + reg [31:0] shutdown = 32'h0000_0000; + always @ (posedge s_axi_aclk) begin + if (s_axi_areset) + shutdown <= 32'h0000_0000; + else if (write_shutdown) + shutdown <= s_axi_wdata; + end + + wire [31:0] spi_tx_tdata; + wire spi_tx_tvalid; + wire [5:0] spi_tx_occupied; + wire [5:0] spi_tx_space; + + wire [31:0] tmux = write_shutdown ? {s_axi_wdata[23:0], 8'h00} + : {s_axi_wdata[7:0], s_axi_wdata[15:8], addr[7:0], 8'h01}; + + wire is_spi_cmd = (addr[7:0] == 8'h00) || (addr[7:0] > 8'h04); + + axi_fifo_bram #(.WIDTH(32), .SIZE(5)) axi_fifo_short_inst + ( + .clk(s_axi_aclk), + .reset(s_axi_areset), + .clear(1'b0), + .i_tdata(tmux), + .i_tvalid(state == WRITE_IN_PROGRESS && is_spi_cmd), + .i_tready(), + .o_tdata(spi_tx_tdata), + .o_tvalid(spi_tx_tvalid), + .o_tready(spi_stb), + .occupied(spi_tx_occupied), + .space(spi_tx_space) + ); + + reg [63:0] spi_tx_reg; + + always @ (posedge s_axi_aclk) + if(s_axi_areset) + spi_tx_reg <= 64'h0000_0000_0000_0000; + else if (spi_stb) + spi_tx_reg <= {spi_tx_tvalid, 31'h00, spi_tx_tdata}; + + assign spi_tx = spi_tx_reg; + + /* battery stuff */ + wire [15:0] battery_voltage = {spi_rx_r0[55:48], spi_rx_r0[63:56]}; + wire [1:0] battery_temp_alert = spi_rx_r0[47:46]; + wire battery_online = spi_rx_r0[45]; + wire [2:0] battery_health = spi_rx_r0[44:42]; + wire [1:0] battery_status = spi_rx_r0[41:40]; + + /* charger stuff */ + /* unused [39:38] */ + wire [1:0] charger_health = spi_rx_r0[37:36]; + wire charger_online = spi_rx_r0[35]; + /* unused bit 34 */ + wire [1:0] charger_charge_type = spi_rx_r0[33:32]; + + /* gauge stuff */ + wire [7:0] gauge_status = spi_rx_r1[63:56]; + wire [15:0] voltage = {spi_rx_r1[47:40], spi_rx_r1[55:48]}; + wire [15:0] temp = {spi_rx_r1[31:24], spi_rx_r1[39:32]}; + wire [15:0] charge_acc = {spi_rx_r1[15:8] , spi_rx_r1[23:16]}; + + /* charge last full */ + wire [15:0] charge_last_full = {spi_rx_r2[15:8], spi_rx_r2[23:16]}; + + /* settings flags */ + wire [7:0] settings = spi_rx_r2[31:24]; + + reg [7:0] irq_enable; + always @ (posedge s_axi_aclk) begin + if (s_axi_areset) + irq_enable <= 8'h00; + else if (write_irq_mask) + irq_enable <= s_axi_wdata[15:8]; + end + + wire [7:0] irq_status = gauge_status; + assign s_axi_irq = |(irq_status & irq_enable); + + wire [3:0] version_maj = spi_rx_r0[15:12]; + wire [3:0] version_min = spi_rx_r0[11:8]; + + reg [31:0] rdata; + // read mux + always @(*) begin + rdata = 32'hdead_beef; + + if (state == READ_IN_PROGRESS) + case (addr) + 8'h00: rdata = shutdown; + 8'h04: rdata = {16'h0000, irq_enable, version_maj, version_min}; + 8'h08: rdata = {8'h0, battery_voltage, battery_temp_alert, battery_online, battery_health, battery_status}; + 8'h0c: rdata = {27'd0, charger_charge_type, charger_online, charger_health}; + 8'h10: rdata = {temp, charge_acc}; + 8'h14: rdata = {8'h00, gauge_status, voltage}; + 8'h18: rdata = {16'h0000, charge_last_full}; + 8'h1c: rdata = {24'd0, settings}; + endcase + end + + assign s_axi_arready = (state == IDLE); + assign s_axi_rvalid = (state == READ_IN_PROGRESS); + assign s_axi_rresp = 2'b00; + + assign s_axi_rdata = rdata; + + assign s_axi_awready = (state == IDLE); + assign s_axi_wready = (state == WRITE_IN_PROGRESS); + assign s_axi_bresp = 2'b00; + assign s_axi_bvalid = (state == WRITE_IN_PROGRESS); + +endmodule diff --git a/fpga/usrp3/top/e31x/build_e31x.tcl b/fpga/usrp3/top/e31x/build_e31x.tcl new file mode 100644 index 000000000..e07b124c2 --- /dev/null +++ b/fpga/usrp3/top/e31x/build_e31x.tcl @@ -0,0 +1,39 @@ +# +# Copyright 2016 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set e31x_strategy [dict create] +dict set e31x_strategy "opt_design.is_enabled" 1 +dict set e31x_strategy "opt_design.directive" "Default" +dict set e31x_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set e31x_strategy "place_design.directive" "Default" +dict set e31x_strategy "post_place_power_opt_design.is_enabled" 0 +dict set e31x_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set e31x_strategy "post_place_phys_opt_design.directive" "Default" +dict set e31x_strategy "route_design.directive" "Default" +dict set e31x_strategy "route_design.more_options" "-tns_cleanup" +dict set e31x_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set e31x_strategy "post_route_phys_opt_design.directive" "Default" +vivado_strategies::implement_design $e31x_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *] +set byte_swap_bin 1 +vivado_utils::write_implementation_outputs $byte_swap_bin + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/e31x/dts/dma-common.dtsi b/fpga/usrp3/top/e31x/dts/dma-common.dtsi new file mode 100644 index 000000000..ab6096f08 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/dma-common.dtsi @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-common.dtsi b/fpga/usrp3/top/e31x/dts/e31x-common.dtsi new file mode 100644 index 000000000..63cae413f --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-common.dtsi @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-pmu.dtsi b/fpga/usrp3/top/e31x/dts/e31x-pmu.dtsi new file mode 100644 index 000000000..f85c09816 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-pmu.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + devctrl: devctrl@40000000 { + compatible = "syscon"; + reg = <0x40000000 0x24>; + }; + poweroff { + compatible = "syscon-poweroff"; + regmap = <&devctrl>; + offset = <0x0>; + mask = <0x7a>; + }; + pmu { + compatible = "ni,e31x-pmu"; + regmap = <&devctrl>; + status = "okay"; + charger: charger@0{ + compatible = "ni,e31x-charger"; + }; + battery: battery@1{ + compatible = "ni,e31x-battery"; + }; + }; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-sg1-fpga.dtsi b/fpga/usrp3/top/e31x/dts/e31x-sg1-fpga.dtsi new file mode 100644 index 000000000..38d6b081b --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-sg1-fpga.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + firmware-name = "e310_sg1.bin"; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-sg1-idle-fpga.dtsi b/fpga/usrp3/top/e31x/dts/e31x-sg1-idle-fpga.dtsi new file mode 100644 index 000000000..c673a95d4 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-sg1-idle-fpga.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + firmware-name = "e310_sg1_idle.bin"; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-sg3-fpga.dtsi b/fpga/usrp3/top/e31x/dts/e31x-sg3-fpga.dtsi new file mode 100644 index 000000000..676983bfd --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-sg3-fpga.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + firmware-name = "e310_sg3.bin"; +}; diff --git a/fpga/usrp3/top/e31x/dts/e31x-sg3-idle-fpga.dtsi b/fpga/usrp3/top/e31x/dts/e31x-sg3-idle-fpga.dtsi new file mode 100644 index 000000000..0d65bb146 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/e31x-sg3-idle-fpga.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + firmware-name = "e310_sg3_idle.bin"; +}; diff --git a/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_fpga.dts b/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_fpga.dts new file mode 100644 index 000000000..48a677835 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_fpga.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +/dts-v1/; +/plugin/; + +#include "e31x-sg1-fpga.dtsi" +#include "e31x-common.dtsi" +#include "e31x-pmu.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_idle_fpga.dts b/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_idle_fpga.dts new file mode 100644 index 000000000..d406d2fd6 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/usrp_e310_sg1_idle_fpga.dts @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +/dts-v1/; +/plugin/; + +#include "e31x-sg1-idle-fpga.dtsi" +#include "e31x-pmu.dtsi" diff --git a/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_fpga.dts b/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_fpga.dts new file mode 100644 index 000000000..da29b5dc4 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_fpga.dts @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +/dts-v1/; +/plugin/; + +#include "e31x-sg3-fpga.dtsi" +#include "e31x-common.dtsi" +#include "e31x-pmu.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_idle_fpga.dts b/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_idle_fpga.dts new file mode 100644 index 000000000..58a9712e6 --- /dev/null +++ b/fpga/usrp3/top/e31x/dts/usrp_e310_sg3_idle_fpga.dts @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +/dts-v1/; +/plugin/; + +#include "e31x-sg3-idle-fpga.dtsi" +#include "e31x-pmu.dtsi" diff --git a/fpga/usrp3/top/e31x/e310_io.v b/fpga/usrp3/top/e31x/e310_io.v new file mode 100644 index 000000000..fe8968435 --- /dev/null +++ b/fpga/usrp3/top/e31x/e310_io.v @@ -0,0 +1,139 @@ +// +// Copyright 2015 Ettus Research, A National Instruments Company +// SPDX-License-Identifier: LGPL-3.0 +// +// Description: E31X IO for CMOS interface +// + +module e310_io ( + input areset, + input mimo, + // Baseband sample interface + output radio_clk, + output radio_rst, + output reg [11:0] rx_i0, + output reg [11:0] rx_q0, + output reg [11:0] rx_i1, + output reg [11:0] rx_q1, + output reg rx_stb, + input [11:0] tx_i0, + input [11:0] tx_q0, + input [11:0] tx_i1, + input [11:0] tx_q1, + output reg tx_stb, + // AD9361 interface + input rx_clk, + input rx_frame, + input [11:0] rx_data, + output tx_clk, + output tx_frame, + output [11:0] tx_data +); + + // Synchronize asynchronous reset and MIMO + synchronizer #(.STAGES(3), .INITIAL_VAL(1'b1)) sychronizer_radio_rst ( + .clk(radio_clk), .rst(areset), .in(1'b0), .out(radio_rst)); + + wire mimo_sync; + synchronizer synchronizer_mimo (.clk(radio_clk), .rst(radio_rst), .in(mimo), .out(mimo_sync)); + + /**************************************************************************** + ** RX Capture Interface + ****************************************************************************/ + wire rx_clk_bufr; // Capture clock + BUFR bufr_rx_clk (.I(rx_clk), .O(rx_clk_bufr)); + BUFG bufg_radio_clk (.I(rx_clk_bufr), .O(radio_clk)); + + wire [11:0] rx_i, rx_q; + genvar n; + generate + for (n = 0; n < 12; n = n + 1) begin + IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D(rx_data[n]), .Q1(rx_q[n]), .Q2(rx_i[n])); + end + endgenerate + + wire rx_frame_rising, rx_frame_falling; + IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr_frame ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D(rx_frame), .Q1(rx_frame_rising), .Q2(rx_frame_falling)); + + always @(posedge radio_clk or posedge radio_rst) begin + if (radio_rst) begin + rx_stb <= 1'b0; + end else begin + if (mimo_sync) begin + if (rx_frame_rising) begin + rx_i0 <= rx_i; + rx_q0 <= rx_q; + end else begin + rx_i1 <= rx_i; + rx_q1 <= rx_q; + end + rx_stb <= ~rx_frame_rising; + end else begin + rx_i0 <= rx_i; + rx_q0 <= rx_q; + rx_i1 <= rx_i; + rx_q1 <= rx_q; + rx_stb <= 1'b1; + end + end + end + + /**************************************************************************** + ** TX Output Interface + ****************************************************************************/ + reg [11:0] tx_i, tx_q; + reg tx_frame_int = 1'b1; + generate + for (n = 0; n < 12; n = n + 1) begin + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr ( + .C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0), + .D1(tx_i[n]), .D2(tx_q[n]), .Q(tx_data[n])); + end + endgenerate + + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame ( + .C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0), + // In SISO mode, TX frame is asserted only on the falling edge + .D1(tx_frame_int), .D2(tx_frame_int & mimo_sync), .Q(tx_frame)); + + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk ( + .C(radio_clk), .CE(1'b1), .R(1'b0), .S(1'b0), + .D1(1'b1), .D2(1'b0), .Q(tx_clk)); + + reg [11:0] tx_i1_hold, tx_q1_hold; + always @(posedge radio_clk or posedge radio_rst) begin + if (radio_rst) begin + tx_stb <= 1'b0; + tx_frame_int <= 1'b1; + end else begin + if (mimo_sync) begin + tx_stb <= ~tx_stb; + tx_frame_int <= tx_stb; + if (tx_stb) begin + tx_i <= tx_i0; + tx_q <= tx_q0; + tx_i1_hold <= tx_i1; + tx_q1_hold <= tx_q1; + end else begin + tx_i <= tx_i1_hold; + tx_q <= tx_q1_hold; + end + end else begin + tx_stb <= 1'b1; + tx_frame_int <= 1'b1; + if ({tx_i0,tx_q0} != 24'd0) begin + tx_i <= tx_i0; + tx_q <= tx_q0; + end else begin + tx_i <= tx_i1; + tx_q <= tx_q1; + end + end + end + end + +endmodule diff --git a/fpga/usrp3/top/e31x/e310_static_router.hex b/fpga/usrp3/top/e31x/e310_static_router.hex new file mode 100644 index 000000000..3a9dfa282 --- /dev/null +++ b/fpga/usrp3/top/e31x/e310_static_router.hex @@ -0,0 +1,5 @@ +00000004 +004000c0 +008000c1 +00c00040 +00c10080 diff --git a/fpga/usrp3/top/e31x/e31x.v b/fpga/usrp3/top/e31x/e31x.v new file mode 100644 index 000000000..3902ed551 --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x.v @@ -0,0 +1,882 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e31x +// Description: +// E31x Top Level +// +///////////////////////////////////////////////////////////////////// + +module e31x ( + + // PS Connections + inout [53:0] MIO, + input PS_SRSTB, + input PS_CLK, + input PS_PORB, + inout DDR_CLK, + inout DDR_CLK_N, + inout DDR_CKE, + inout DDR_CS_N, + inout DDR_RAS_N, + inout DDR_CAS_N, + inout DDR_WEB, + inout [2:0] DDR_BANKADDR, + inout [14:0] DDR_ADDR, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_N, + inout DDR_VRP, + inout DDR_VRN, + + // PL DDR + //input PL_DDR3_SYSCLK, + //output PL_DDR3_RESET_N, + //inout [15:0] PL_DDR3_DQ, + //inout [1:0] PL_DDR3_DQS_N, + //inout [1:0] PL_DDR3_DQS_P, + //output [14:0] PL_DDR3_ADDR, + //output [2:0] PL_DDR3_BA, + //output PL_DDR3_RAS_N, + //output PL_DDR3_CAS_N, + //output PL_DDR3_WE_N, + //output [0:0] PL_DDR3_CK_P, + //output [0:0] PL_DDR3_CK_N, + //output [0:0] PL_DDR3_CKE, + //output [1:0] PL_DDR3_DM, + //output [0:0] PL_DDR3_ODT, + + //AVR SPI IO + input AVR_CS_R, + output AVR_IRQ, + output AVR_MISO_R, + input AVR_MOSI_R, + input AVR_SCK_R, + + input ONSWITCH_DB, + + // RF Board connections + // Change to inout/output as + // they are implemented/tested + input [34:0] DB_EXP_1_8V, + + // Front-end Band Selects + output [2:0] TX_BANDSEL, + output [2:0] RX1_BANDSEL, + output [2:0] RX2_BANDSEL, + output [1:0] RX2C_BANDSEL, + output [1:0] RX1B_BANDSEL, + output [1:0] RX1C_BANDSEL, + output [1:0] RX2B_BANDSEL, + + // Enables + output TX_ENABLE1A, + output TX_ENABLE2A, + output TX_ENABLE1B, + output TX_ENABLE2B, + + // Antenna Selects + output VCTXRX1_V1, + output VCTXRX1_V2, + output VCTXRX2_V1, + output VCTXRX2_V2, + output VCRX1_V1, + output VCRX1_V2, + output VCRX2_V1, + output VCRX2_V2, + + // Leds + output LED_TXRX1_TX, + output LED_TXRX1_RX, + output LED_RX1_RX, + output LED_TXRX2_TX, + output LED_TXRX2_RX, + output LED_RX2_RX, + + // AD9361 connections + input [7:0] CAT_CTRL_OUT, + output [3:0] CAT_CTRL_IN, + output CAT_RESET, // FIXME Fix in Pinout + output CAT_CS, + output CAT_SCLK, + output CAT_MOSI, + input CAT_MISO, + input CAT_BBCLK_OUT, //unused + output CAT_SYNC, + output CAT_TXNRX, + output CAT_ENABLE, + output CAT_ENAGC, + input CAT_RX_FRAME, + input CAT_DATA_CLK, + output CAT_TX_FRAME, + output CAT_FB_CLK, + input [11:0] CAT_P0_D, + output [11:0] CAT_P1_D, + + // pps connections + input GPS_PPS, + input PPS_EXT_IN, + + // VTCXO and the DAC that feeds it + output TCXO_DAC_SYNC_N, + output TCXO_DAC_SCLK, + output TCXO_DAC_SDIN, + input TCXO_CLK, + + // gpios, change to inout somehow + inout [5:0] PL_GPIO +); + + // Constants + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam REG_DWIDTH = 32; + localparam DB_GPIO_WIDTH = 32; + localparam FP_GPIO_OFFSET = 32; // Offset within ps_gpio_* + localparam FP_GPIO_WIDTH = 6; + + //If bus_clk freq ever changes, update this parameter accordingly. + localparam BUS_CLK_RATE = 32'd100000000; //100 MHz bus_clk rate. + localparam NUM_SFP_PORTS = 0; + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + + // Clocks + wire bus_clk; + wire radio_clk; + wire reg_clk; + wire clk40; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + + // Resets + wire global_rst; + wire bus_rst; + wire radio_rst; + wire reg_rstn; + wire clk40_rst; + wire clk40_rstn; + wire FCLK_RESET0_N; + + // Crossbar + wire m_axi_xbar_arvalid; + wire m_axi_xbar_awvalid; + wire m_axi_xbar_bready; + wire m_axi_xbar_rready; + wire m_axi_xbar_wvalid; + wire [11:0] m_axi_xbar_arid; + wire [11:0] m_axi_xbar_awid; + wire [11:0] m_axi_xbar_wid; + wire [31:0] m_axi_xbar_araddr; + wire [31:0] m_axi_xbar_awaddr; + wire [31:0] m_axi_xbar_wdata; + wire [3:0] m_axi_xbar_wstrb; + wire m_axi_xbar_arready; + wire m_axi_xbar_awready; + wire m_axi_xbar_bvalid; + wire m_axi_xbar_rlast; + wire m_axi_xbar_rvalid; + wire m_axi_xbar_wready; + wire [1:0] m_axi_xbar_bresp; + wire [1:0] m_axi_xbar_rresp; + wire [31:0] m_axi_xbar_rdata; + + // PMU + wire [31:0] m_axi_pmu_araddr; + wire [2:0] m_axi_pmu_arprot; + wire m_axi_pmu_arready; + wire m_axi_pmu_arvalid; + wire [31:0] m_axi_pmu_awaddr; + wire [2:0] m_axi_pmu_awprot; + wire m_axi_pmu_awready; + wire m_axi_pmu_awvalid; + wire m_axi_pmu_bready; + wire [1:0] m_axi_pmu_bresp; + wire m_axi_pmu_bvalid; + wire [31:0] m_axi_pmu_rdata; + wire m_axi_pmu_rready; + wire [1:0] m_axi_pmu_rresp; + wire m_axi_pmu_rvalid; + wire [31:0] m_axi_pmu_wdata; + wire m_axi_pmu_wready; + wire [3:0] m_axi_pmu_wstrb; + wire m_axi_pmu_wvalid; + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + ///////////////////////////////////////////////////////////////////// + // + // Resets: + // - PL - Global Reset --> Bus Reset + // --> Radio Reset + // - PS - FCLK_RESET0_N --> clk40_rst(n) + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen ( + .clk(bus_clk), + .reset_out(global_rst) + ); + + // Synchronous reset for the bus_clk domain + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(~FCLK_RESET0_N), + //.reset_in(~clocks_locked), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + assign reg_rstn = clk40_rstn; + + ///////////////////////////////////////////////////////////////////// + // + // Clocks and PPS + // + ///////////////////////////////////////////////////////////////////// + + wire [1:0] pps_select; + + assign clk40 = FCLK_CLK1; // 40 MHz + assign bus_clk = FCLK_CLK0; // 100 MHz + //assign bus_clk = FCLK_CLK3; // 200 MHz + assign reg_clk = clk40; + + wire pps; + wire clk_tcxo = TCXO_CLK; // 40 MHz + wire is_10meg, is_pps, reflck, plllck; // reference status bits + reg [3:0] tcxo_status, st_rsync; + reg [2:0] pps_reg; + + wire pps_ext = PPS_EXT_IN; + wire gps_pps = GPS_PPS; + + // A local pps signal is derived from the tcxo clock. If a reference + // at an appropriate rate (1 pps or 10 MHz) is present and selected + // a digital control loop will be invoked to tune the vcxo and lock + // the reference. + ppsloop ppslp ( + .reset(1'b0), + .xoclk(clk_tcxo), .ppsgps(gps_pps), .ppsext(pps_ext), + .refsel(pps_select), + .lpps(pps), + .is10meg(is_10meg), .ispps(is_pps), .reflck(reflck), .plllck(plllck), + .sclk(TCXO_DAC_SCLK), .mosi(TCXO_DAC_SDIN), .sync_n(TCXO_DAC_SYNC_N), + .dac_dflt(16'h7fff) + ); + + always @(posedge bus_clk) begin + // status signals originate from other than the bus_clk domain so re-sync + // before passing to e300_core + st_rsync <= {plllck, is_10meg, is_pps, reflck}; + tcxo_status <= st_rsync; + end + + // TODO: Check this logic + // connect PPS input to GPIO so ntpd can use it + always @ (posedge bus_clk) + pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS}; + assign ps_gpio_in[8] = pps_reg[2]; // 62 + + ///////////////////////////////////////////////////////////////////// + // + // Power Button + // + ////////////////////////////////////////////////////////////////////// + + // register the debounced onswitch signal to detect edges, + // Note: ONSWITCH_DB is low active + reg [1:0] onswitch_edge; + always @ (posedge bus_clk) + onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB}; + + wire button_press = ~ONSWITCH_DB & onswitch_edge[0] & onswitch_edge[1]; + wire button_release = ONSWITCH_DB & ~onswitch_edge[0] & ~onswitch_edge[1]; + + // stretch the pulse so IRQs don't get lost + reg [7:0] button_press_reg, button_release_reg; + always @ (posedge bus_clk) + if (bus_rst) begin + button_press_reg <= 8'h00; + button_release_reg <= 8'h00; + end else begin + button_press_reg <= {button_press_reg[6:0], button_press}; + button_release_reg <= {button_release_reg[6:0], button_release}; + end + + wire button_press_irq = |button_press_reg; + wire button_release_irq = |button_release_reg; + + ///////////////////////////////////////////////////////////////////// + // + // Interrupts Fabric to PS + // + ////////////////////////////////////////////////////////////////////// + + wire [15:0] IRQ_F2P; + wire pmu_irq; + assign IRQ_F2P = {12'b0, + pmu_irq, // Interrupt 32 + button_release_irq, // Interrupt 31 + button_press_irq, // Interrupt 30 + 1'b0}; + + ///////////////////////////////////////////////////////////////////// + // + // PS Connections + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_tri; + + e31x_ps_bd e31x_ps_bd_inst ( + + // DDR Interface + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_addr(DDR_ADDR), + .DDR_ba(DDR_BANKADDR), + .DDR_cas_n(DDR_CAS_N), + .DDR_ck_n(DDR_CLK_N), + .DDR_ck_p(DDR_CLK), + .DDR_cke(DDR_CKE), + .DDR_cs_n(DDR_CS_N), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_N), + .DDR_dqs_p(DDR_DQS), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_N), + .DDR_reset_n(DDR_RESET_N), + .DDR_we_n(DDR_WE_N), + + // Clocks + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + + // Resets + .FCLK_RESET0_N(FCLK_RESET0_N), + + // GPIO + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + // Interrupts + .IRQ_F2P(IRQ_F2P), + + // MIO + .MIO(MIO), + + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + + // SPI + .SPI0_MISO_I(CAT_MISO), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(CAT_MOSI), + .SPI0_MOSI_T(), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(CAT_SCLK), + .SPI0_SCLK_T(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(CAT_CS), + .SPI0_SS_T(), + + .SPI1_MISO_I(), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_MOSI_I(), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_SCLK_I(), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_I(), + .SPI1_SS_O(), + .SPI1_SS_T(), + + // USB + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + + // XBAR Regport + .m_axi_xbar_araddr(m_axi_xbar_araddr), + .m_axi_xbar_arprot(m_axi_xbar_arprot), + .m_axi_xbar_arready(m_axi_xbar_arready), + .m_axi_xbar_arvalid(m_axi_xbar_arvalid), + .m_axi_xbar_awaddr(m_axi_xbar_awaddr), + .m_axi_xbar_awprot(m_axi_xbar_awprot), + .m_axi_xbar_awready(m_axi_xbar_awready), + .m_axi_xbar_awvalid(m_axi_xbar_awvalid), + .m_axi_xbar_bready(m_axi_xbar_bready), + .m_axi_xbar_bresp(m_axi_xbar_bresp), + .m_axi_xbar_bvalid(m_axi_xbar_bvalid), + .m_axi_xbar_rdata(m_axi_xbar_rdata), + .m_axi_xbar_rready(m_axi_xbar_rready), + .m_axi_xbar_rresp(m_axi_xbar_rresp), + .m_axi_xbar_rvalid(m_axi_xbar_rvalid), + .m_axi_xbar_wdata(m_axi_xbar_wdata), + .m_axi_xbar_wready(m_axi_xbar_wready), + .m_axi_xbar_wstrb(m_axi_xbar_wstrb), + .m_axi_xbar_wvalid(m_axi_xbar_wvalid), + + // PMU + .m_axi_pmu_araddr(m_axi_pmu_araddr), + .m_axi_pmu_arprot(m_axi_pmu_arprot), + .m_axi_pmu_arready(m_axi_pmu_arready), + .m_axi_pmu_arvalid(m_axi_pmu_arvalid), + .m_axi_pmu_awaddr(m_axi_pmu_awaddr), + .m_axi_pmu_awprot(m_axi_pmu_awprot), + .m_axi_pmu_awready(m_axi_pmu_awready), + .m_axi_pmu_awvalid(m_axi_pmu_awvalid), + .m_axi_pmu_bready(m_axi_pmu_bready), + .m_axi_pmu_bresp(m_axi_pmu_bresp), + .m_axi_pmu_bvalid(m_axi_pmu_bvalid), + .m_axi_pmu_rdata(m_axi_pmu_rdata), + .m_axi_pmu_rready(m_axi_pmu_rready), + .m_axi_pmu_rresp(m_axi_pmu_rresp), + .m_axi_pmu_rvalid(m_axi_pmu_rvalid), + .m_axi_pmu_wdata(m_axi_pmu_wdata), + .m_axi_pmu_wready(m_axi_pmu_wready), + .m_axi_pmu_wstrb(m_axi_pmu_wstrb), + .m_axi_pmu_wvalid(m_axi_pmu_wvalid), + + // DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid) + ); + + ///////////////////////////////////////////////////////////////////// + // + // AD9361 Interface + // + ///////////////////////////////////////////////////////////////////// + + wire [REG_DWIDTH-1:0] dboard_ctrl; + wire [REG_DWIDTH-1:0] dboard_status; + wire mimo_busclk; + wire tx_pll_lock_busclk, rx_pll_lock_busclk; + + wire codec_arst; + wire [NUM_CHANNELS*32-1:0] rx_flat, tx_flat; + + wire [11:0] rx_i0, rx_q0, tx_i0, tx_q0; + wire [11:0] rx_i1, rx_q1, tx_i1, tx_q1; + + wire rx_stb, tx_stb; + wire [NUM_CHANNELS-1:0] rx_atr, tx_atr; + + assign rx_flat = {rx_i1, 4'd0, rx_q1, 4'd0, + rx_i0, 4'd0, rx_q0, 4'd0}; + + assign tx_q0 = tx_flat[15:4]; + assign tx_i0 = tx_flat[31:20]; + assign tx_q1 = tx_flat[47:36]; + assign tx_i1 = tx_flat[63:52]; + + assign mimo_busclk = dboard_ctrl[0]; + assign codec_arst = dboard_ctrl[1]; + + synchronizer synchronizer_tx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(CAT_CTRL_OUT[7]), .out(tx_pll_lock_busclk) + ); + + synchronizer synchronizer_rx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(CAT_CTRL_OUT[6]), .out(rx_pll_lock_busclk) + ); + + assign dboard_status = { + 20'b0, + tcxo_status, // TCXO satus {plllck, is_10meg, is_pps, refclk} + tx_pll_lock_busclk, // TX PLL Lock + rx_pll_lock_busclk, // RX PLL Lock + 6'b0 + }; + + + e310_io e310_io ( + //.areset(codec_arst), TODO + .areset(bus_rst), + .mimo(mimo_busclk), + // Baseband sample interface + .radio_clk(radio_clk), + .radio_rst(radio_rst), + .rx_i0(rx_i1), + .rx_q0(rx_q1), + .rx_i1(rx_i0), + .rx_q1(rx_q0), + .rx_stb(rx_stb), + .tx_i0(tx_i1), + .tx_q0(tx_q1), + .tx_i1(tx_i0), + .tx_q1(tx_q0), + .tx_stb(tx_stb), + // AD9361 interface + .rx_clk(CAT_DATA_CLK), + .rx_frame(CAT_RX_FRAME), + .rx_data(CAT_P0_D), + .tx_clk(CAT_FB_CLK), + .tx_frame(CAT_TX_FRAME), + .tx_data(CAT_P1_D) + ); + + assign CAT_CTRL_IN = 4'b1; + assign CAT_ENAGC = 1'b1; + assign CAT_TXNRX = 1'b1; + assign CAT_ENABLE = 1'b1; + assign CAT_RESET = ~bus_rst; // Operates active-low, really CAT_RESET_B + assign CAT_SYNC = 1'b0; + + ///////////////////////////////////////////////////////////////////// + // + // DB GPIO Interface + // - Control Filter Banks + // - LEDs + // + ///////////////////////////////////////////////////////////////////// + + // Flattened Radio GPIO control + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat; + wire [32*NUM_CHANNELS-1:0] leds_flat; + + // Radio GPIO control + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_pins[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + + assign db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_in[i]; + assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_ddr[i] = db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign leds[i] = leds_flat[32*i +: 32]; + + gpio_atr_io #( + .WIDTH(DB_GPIO_WIDTH) + ) gpio_atr_db_inst ( + .clk(radio_clk), + .gpio_pins(db_gpio_pins[i]), + .gpio_ddr(db_gpio_ddr[i]), + .gpio_out(db_gpio_out[i]), + .gpio_in(db_gpio_in[i]) + ); + end + endgenerate + + // DB_GPIO and LED pin assignments with software mapping + wire [2:0] TX1_BANDSEL; + wire [2:0] TX2_BANDSEL; + + // Channel 0 + assign {VCRX1_V1, // [15:15] + VCRX1_V2, // [14:14] + VCTXRX1_V1, // [13:13] + VCTXRX1_V2, // [12:12] + TX_ENABLE1B, // [11:11] + TX_ENABLE1A, // [10:10] + RX1C_BANDSEL, // [9:8] + RX1B_BANDSEL, // [7:6] + RX1_BANDSEL, // [5:3] + TX1_BANDSEL // [2:0] + } = db_gpio_pins[1]; + + assign {LED_RX1_RX, + LED_TXRX1_TX, + LED_TXRX1_RX + } = leds[1]; + + // Channel 1 + assign {VCRX2_V1, + VCRX2_V2, + VCTXRX2_V1, + VCTXRX2_V2, + TX_ENABLE2B, + TX_ENABLE2A, + RX2C_BANDSEL, + RX2B_BANDSEL, + RX2_BANDSEL, + TX2_BANDSEL + } = db_gpio_pins[0]; + + assign {LED_RX2_RX, + LED_TXRX2_TX, + LED_TXRX2_RX + } = leds[0]; + + // It is okay to OR here as the both channels must be set to the same freq. + // This is needed so software does not have to set properties of radio core 0 + // when only using radio core 1. + assign TX_BANDSEL = TX1_BANDSEL | TX2_BANDSEL; + + ///////////////////////////////////////////////////////////////////// + // + // Front-Panel GPIO + // + ///////////////////////////////////////////////////////////////////// + + wire [FP_GPIO_WIDTH-1:0] fp_gpio_in; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_out; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri; + + gpio_atr_io #(.WIDTH(FP_GPIO_WIDTH)) fp_gpio_atr_inst ( + .clk(radio_clk), .gpio_pins(PL_GPIO), + .gpio_ddr(fp_gpio_tri), .gpio_out(fp_gpio_out), .gpio_in(fp_gpio_in) + ); + + ///////////////////////////////////////////////////////////////////// + // + // E320 Core: + // - xbar + // - Radio + // - DMA + // - DRAM + // - CEs + // + ////////////////////////////////////////////////////////////////////// + + wire [31:0] build_datestamp; + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + e31x_core #( + .REG_AWIDTH(REG_AWIDTH), + .BUS_CLK_RATE(BUS_CLK_RATE), + .NUM_SFP_PORTS(NUM_SFP_PORTS), + .NUM_RADIOS(NUM_RADIOS), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .NUM_CHANNELS_PER_DBOARD(NUM_CHANNELS_PER_RADIO), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .DB_GPIO_WIDTH(DB_GPIO_WIDTH) + ) e31x_core_inst ( + + //Clocks and resets + .radio_clk(radio_clk), + .radio_rst(radio_rst), + .bus_clk(bus_clk), + .bus_rst(bus_rst), + + // Clocking and PPS Controls/Indicators + .pps_refclk(pps), + .refclk_locked(reflck), + .pps_select(pps_select), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_xbar_awaddr), + .s_axi_awvalid(m_axi_xbar_awvalid), + .s_axi_awready(m_axi_xbar_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_xbar_wdata), + .s_axi_wstrb(m_axi_xbar_wstrb), + .s_axi_wvalid(m_axi_xbar_wvalid), + .s_axi_wready(m_axi_xbar_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_xbar_bresp), + .s_axi_bvalid(m_axi_xbar_bvalid), + .s_axi_bready(m_axi_xbar_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_xbar_araddr), + .s_axi_arvalid(m_axi_xbar_arvalid), + .s_axi_arready(m_axi_xbar_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_xbar_rdata), + .s_axi_rresp(m_axi_xbar_rresp), + .s_axi_rvalid(m_axi_xbar_rvalid), + .s_axi_rready(m_axi_xbar_rready), + + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + + // Front-Panel GPIO + .fp_gpio_in(fp_gpio_in), + .fp_gpio_tri(fp_gpio_tri), + .fp_gpio_out(fp_gpio_out), + + // PS GPIO Connection + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + + // DB GPIO + .db_gpio_out_flat(db_gpio_out_flat), + .db_gpio_ddr_flat(db_gpio_ddr_flat), + .db_gpio_in_flat(db_gpio_in_flat), + .db_gpio_fab_flat(32'b0), + + // TX/RX LEDs + .leds_flat(leds_flat), + + // Radio Strobes + .rx_stb({NUM_CHANNELS{rx_stb}}), + .tx_stb({NUM_CHANNELS{tx_stb}}), + + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + .build_datestamp(build_datestamp), + .sfp_ports_info(), + .dboard_status(dboard_status), + .xadc_readback(32'h0), //Unused + .fp_gpio_ctrl(), //Unused + .dboard_ctrl(dboard_ctrl) + ); + + ///////////////////////////////////////////////////////////////////// + // + // PL DDR3 Memory Interface + // + ///////////////////////////////////////////////////////////////////// + + //wire pl_dram_clk = FCLK_CLK3; + //wire pl_dram_rst = ~FCLK_RESET0_N; + + //example_top inst_example_top + //( + // .ddr3_dq (PL_DDR3_DQ), + // .ddr3_dqs_n (PL_DDR3_DQS_N), + // .ddr3_dqs_p (PL_DDR3_DQS_P), + // .ddr3_addr (PL_DDR3_ADDR), + // .ddr3_ba (PL_DDR3_BA), + // .ddr3_ras_n (PL_DDR3_RAS_N), + // .ddr3_cas_n (PL_DDR3_CAS_N), + // .ddr3_we_n (PL_DDR3_WE_N), + // .ddr3_reset_n (PL_DDR3_RESET_N), + // .ddr3_ck_p (PL_DDR3_CK_P), + // .ddr3_ck_n (PL_DDR3_CK_N), + // .ddr3_cke (PL_DDR3_CKE), + // .ddr3_dm (PL_DDR3_DM), + // .ddr3_odt (PL_DDR3_ODT), + // .sys_clk_i (PL_DDR3_SYSCLK), + // .clk_ref_i (pl_dram_clk), + // .tg_compare_error (), + // .init_calib_complete (), + // .sys_rst (pl_dram_rst) + //); + + // PMU + axi_pmu inst_axi_pmu ( + .s_axi_aclk(clk40), // TODO: Original design used bus_clk + .s_axi_areset(clk40_rst), + + .ss(AVR_CS_R), + .mosi(AVR_MOSI_R), + .sck(AVR_SCK_R), + .miso(AVR_MISO_R), + + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_pmu_awaddr), + .s_axi_awvalid(m_axi_pmu_awvalid), + .s_axi_awready(m_axi_pmu_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_pmu_wdata), + .s_axi_wstrb(m_axi_pmu_wstrb), + .s_axi_wvalid(m_axi_pmu_wvalid), + .s_axi_wready(m_axi_pmu_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_pmu_bresp), + .s_axi_bvalid(m_axi_pmu_bvalid), + .s_axi_bready(m_axi_pmu_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_pmu_araddr), + .s_axi_arvalid(m_axi_pmu_arvalid), + .s_axi_arready(m_axi_pmu_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_pmu_rdata), + .s_axi_rresp(m_axi_pmu_rresp), + .s_axi_rvalid(m_axi_pmu_rvalid), + .s_axi_rready(m_axi_pmu_rready), + + .s_axi_irq(pmu_irq) + ); + + assign AVR_IRQ = 1'b0; + + +endmodule // e31x diff --git a/fpga/usrp3/top/e31x/e31x_core.v b/fpga/usrp3/top/e31x/e31x_core.v new file mode 100644 index 000000000..7cd2dddf4 --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_core.v @@ -0,0 +1,681 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: e31x_core +// Description: +// - Motherboard Registers +// - Crossbar +// - Noc Block Radio +// - Noc Block Dram Fifo +// - Radio Front End control +// +///////////////////////////////////////////////////////////////////// + +`default_nettype none +module e31x_core #( + parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) + parameter REG_AWIDTH = 32, // Width of the address bus + parameter BUS_CLK_RATE = 200000000, // bus_clk rate + parameter NUM_SFP_PORTS = 0, // Number of SFP Ports + parameter NUM_RADIOS = 1, + parameter NUM_CHANNELS_PER_RADIO = 2, + parameter NUM_CHANNELS = 2, + parameter NUM_DBOARDS = 1, + parameter NUM_CHANNELS_PER_DBOARD = 2, + parameter FP_GPIO_WIDTH = 8, // Front panel GPIO width + parameter DB_GPIO_WIDTH = 16, // Daughterboard GPIO width + parameter CHDR_WIDTH = 16'd64 , + parameter RFNOC_PROTOVER = {8'd1, 8'd0} +)( + // Clocks and resets + input wire radio_clk, + input wire radio_rst, + input wire bus_clk, + input wire bus_rst, + + // Motherboard Registers: AXI lite interface + input wire s_axi_aclk, + input wire s_axi_aresetn, + input wire [REG_AWIDTH-1:0] s_axi_awaddr, + input wire s_axi_awvalid, + output wire s_axi_awready, + + input wire [REG_DWIDTH-1:0] s_axi_wdata, + input wire [REG_DWIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wvalid, + output wire s_axi_wready, + + output wire [1:0] s_axi_bresp, + output wire s_axi_bvalid, + input wire s_axi_bready, + + input wire [REG_AWIDTH-1:0] s_axi_araddr, + input wire s_axi_arvalid, + output wire s_axi_arready, + + output wire [REG_DWIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // PPS and Clock Control + input wire pps_refclk, + input wire refclk_locked, + output reg [1:0] pps_select, + + // PS GPIO source + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_out, + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] ps_gpio_in, + + // Front Panel GPIO + input wire [FP_GPIO_WIDTH-1:0] fp_gpio_in, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_out, + + // Radio GPIO control + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat, + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_fab_flat, + + // TX/RX LEDs + output wire [32*NUM_CHANNELS-1:0] leds_flat, + + // Radio ATR + output wire [NUM_CHANNELS-1:0] rx_atr, + output wire [NUM_CHANNELS-1:0] tx_atr, + + // Radio Data + input wire [NUM_CHANNELS-1:0] rx_stb, + input wire [NUM_CHANNELS-1:0] tx_stb, + input wire [32*NUM_CHANNELS-1:0] rx, + output wire [32*NUM_CHANNELS-1:0] tx, + + // DMA xport adapter to PS + input wire [63:0] s_dma_tdata, + input wire [3:0] s_dma_tuser, + input wire s_dma_tlast, + output wire s_dma_tready, + input wire s_dma_tvalid, + + output wire [63:0] m_dma_tdata, + output wire [3:0] m_dma_tdest, + output wire m_dma_tlast, + input wire m_dma_tready, + output wire m_dma_tvalid, + + // Misc + input wire [31:0] build_datestamp, + input wire [31:0] sfp_ports_info, + input wire [31:0] dboard_status, + input wire [31:0] xadc_readback, + output reg [31:0] fp_gpio_ctrl, + output reg [31:0] dboard_ctrl, + output reg [15:0] device_id +); + + ///////////////////////////////////////////////////////////////////////////////// + // + // FPGA Compatibility Number + // Rules for modifying compat number: + // - Major is updated when the FPGA is changed and requires a software + // change as a result. + // - Minor is updated when a new feature is added to the FPGA that does not + // break software compatibility. + // + ///////////////////////////////////////////////////////////////////////////////// + + localparam [15:0] COMPAT_MAJOR = 16'd5; + localparam [15:0] COMPAT_MINOR = 16'd0; + + ///////////////////////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////////////////////// + // + // Motherboard Registers + // + ///////////////////////////////////////////////////////////////////////////////// + + // Register base + localparam REG_BASE_MISC = 14'h0; + localparam REG_BASE_TIMEKEEPER = 14'h1000; + + // Misc Registers + localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; + localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; + localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; + localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; + localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; + localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; + localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; + localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; + localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; + localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; + localparam REG_SFP_PORT_INFO = REG_BASE_MISC + 14'h28; + localparam REG_FP_GPIO_CTRL = REG_BASE_MISC + 14'h2C; + localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; + localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; + localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40; + localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44; + localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + + localparam NUM_TIMEKEEPERS = 16'd1; + + wire m_ctrlport_req_wr; + wire m_ctrlport_req_rd; + wire [19:0] m_ctrlport_req_addr; + wire [31:0] m_ctrlport_req_data; + wire m_ctrlport_req_has_time; + wire [63:0] m_ctrlport_req_time; + wire m_ctrlport_resp_ack; + wire [31:0] m_ctrlport_resp_data; + + reg [31:0] fp_gpio_master_reg = 32'h0; + reg [31:0] fp_gpio_src_reg = 32'h0; + + wire reg_wr_req; + wire [REG_AWIDTH-1:0] reg_wr_addr; + wire [REG_DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [REG_DWIDTH-1:0] reg_rd_data; + + reg reg_rd_resp_glob; + reg [REG_DWIDTH-1:0] reg_rd_data_glob; + wire reg_rd_resp_tk; + wire [REG_DWIDTH-1:0] reg_rd_data_tk; + + reg [31:0] scratch_reg = 32'h0; + reg [31:0] bus_counter = 32'h0; + + always @(posedge bus_clk) begin + if (bus_rst) + bus_counter <= 32'd0; + else + bus_counter <= bus_counter + 32'd1; + end + + // Regport Master to convert AXI4-Lite to regport + axil_regport_master #( + .DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (REG_AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) core_regport_master_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_wr_keep (/*unused*/), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + //-------------------------------------------------------------------- + // Global Registers + // ------------------------------------------------------------------- + + // Write Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + scratch_reg <= 32'h0; + pps_select <= 2'b01; // Default to internal + fp_gpio_ctrl <= 32'h9; // Default to OFF - 4'b1001 + dboard_ctrl <= 32'h1; // Default to mimo + device_id <= 16'h0; + end else if (reg_wr_req) begin + case (reg_wr_addr) + REG_DEVICE_ID: begin + device_id <= reg_wr_data[15:0]; + end + REG_FP_GPIO_MASTER: begin + fp_gpio_master_reg <= reg_wr_data; + end + REG_FP_GPIO_RADIO_SRC: begin + fp_gpio_src_reg <= reg_wr_data; + end + REG_SCRATCH: begin + scratch_reg <= reg_wr_data; + end + REG_CLOCK_CTRL: begin + pps_select <= reg_wr_data[1:0]; + end + REG_FP_GPIO_CTRL: begin + fp_gpio_ctrl <= reg_wr_data; + end + REG_DBOARD_CTRL: begin + dboard_ctrl <= reg_wr_data; + end + endcase + end + end + + // Read Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + reg_rd_resp_glob <= 1'b0; + end + else begin + + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + + case (reg_rd_addr) + REG_DEVICE_ID: + reg_rd_data_glob <= device_id; + + REG_RFNOC_INFO: + reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + + REG_COMPAT_NUM: + reg_rd_data_glob <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]}; + + REG_FP_GPIO_CTRL: + reg_rd_data_glob <= fp_gpio_ctrl; + + REG_FP_GPIO_MASTER: + reg_rd_data_glob <= fp_gpio_master_reg; + + REG_FP_GPIO_RADIO_SRC: + reg_rd_data_glob <= fp_gpio_src_reg; + + REG_DATESTAMP: + reg_rd_data_glob <= build_datestamp; + + REG_GIT_HASH: + reg_rd_data_glob <= `GIT_HASH; + + REG_SCRATCH: + reg_rd_data_glob <= scratch_reg; + + REG_CLOCK_CTRL: begin + reg_rd_data_glob <= 32'b0; + reg_rd_data_glob[1:0] <= pps_select; + reg_rd_data_glob[3] <= refclk_locked; + end + + REG_XADC_READBACK: + reg_rd_data_glob <= xadc_readback; + + REG_BUS_CLK_RATE: + reg_rd_data_glob <= BUS_CLK_RATE; + + REG_BUS_CLK_COUNT: + reg_rd_data_glob <= bus_counter; + + REG_SFP_PORT_INFO: + reg_rd_data_glob <= sfp_ports_info; + + REG_DBOARD_CTRL: + reg_rd_data_glob <= dboard_ctrl; + + REG_DBOARD_STATUS: + reg_rd_data_glob <= dboard_status; + + REG_NUM_TIMEKEEPERS: + reg_rd_data_glob <= NUM_TIMEKEEPERS; + + default: + reg_rd_resp_glob <= 1'b0; + endcase + end + else if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + end + + wire pps_radioclk; + + // Synchronize the PPS signal to the radio clock domain + synchronizer pps_radio_sync ( + .clk(radio_clk), .rst(1'b0), .in(pps_refclk), .out(pps_radioclk) + ); + + ///////////////////////////////////////////////////////////////////////////// + // + // DMA Transport Adapter + // + ///////////////////////////////////////////////////////////////////////////// + wire [63:0] dmao_tdata; + wire dmao_tlast; + wire dmao_tvalid; + wire dmao_tready; + + wire [63:0] dmai_tdata; + wire dmai_tlast; + wire dmai_tvalid; + wire dmai_tready; + + liberio_chdr64_adapter #( + .DMA_ID_WIDTH (4) + ) dma_xport_adapter ( + .clk (bus_clk), + .rst (bus_rst), + .device_id (device_id), + // From DMA engine to core + .s_dma_tdata (s_dma_tdata), + .s_dma_tuser (s_dma_tuser), + .s_dma_tlast (s_dma_tlast), + .s_dma_tvalid (s_dma_tvalid), + .s_dma_tready (s_dma_tready), + // From core to DMA engine + .m_dma_tdata (m_dma_tdata), + .m_dma_tuser (m_dma_tdest), + .m_dma_tlast (m_dma_tlast), + .m_dma_tvalid (m_dma_tvalid), + .m_dma_tready (m_dma_tready), + // CHDR buses + .s_chdr_tdata (dmao_tdata), + .s_chdr_tlast (dmao_tlast), + .s_chdr_tvalid (dmao_tvalid), + .s_chdr_tready (dmao_tready), + .m_chdr_tdata (dmai_tdata), + .m_chdr_tlast (dmai_tlast), + .m_chdr_tvalid (dmai_tvalid), + .m_chdr_tready (dmai_tready) + ); + + ///////////////////////////////////////////////////////////////////////////// + // + // Radio Daughter board and Front End Control + // + ///////////////////////////////////////////////////////////////////////////// + + // Radio Daughter board GPIO + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_fab[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + // Daughter board I/O + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + wire [31:0] rx_int[0:NUM_CHANNELS-1], rx_data[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; + //wire rx_stb[0:NUM_CHANNELS-1], tx_stb[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; + wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; + wire db_fe_rb_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; + wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; + + wire [NUM_RADIOS-1:0] sync_out; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + assign rx_atr[i] = rx_running[i]; + assign tx_atr[i] = tx_running[i]; + end + endgenerate + + + //------------------------------------ + // Daughterboard Control + // ----------------------------------- + + localparam [7:0] SR_DB_BASE = 8'd160; + localparam [7:0] RB_DB_BASE = 8'd16; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_db_control + db_control #( + .USE_SPI_CLK(0), + .SR_BASE(SR_DB_BASE), + .RB_BASE(RB_DB_BASE) + ) db_control_i ( + .clk(radio_clk), .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), .rb_addr(db_fe_rb_addr[i]), .rb_data(db_fe_rb_data[i]), + .run_rx(rx_running[i]), .run_tx(tx_running[i]), + .misc_ins(32'h0), .misc_outs(), + .fp_gpio_in(radio_gpio_in[i]), .fp_gpio_out(radio_gpio_out[i]), .fp_gpio_ddr(radio_gpio_ddr[i]), .fp_gpio_fab(32'h0), + .db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_fab(), + .leds(leds[i]), + .spi_clk(1'b0), .spi_rst(1'b0), .sen(), .sclk(), .mosi(), .miso(1'b0) + ); + end + endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control + // Radio Data + assign rx_data[i] = rx[32*i+31:32*i]; + assign tx[32*i+31:32*i] = tx_data[i]; + // GPIO + assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i]; + assign db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_ddr[i]; + assign db_gpio_in[i] = db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_fab[i] = db_gpio_fab_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + // LEDs + assign leds_flat[32*i+31:32*i] = leds[i]; + end + endgenerate + + ///////////////////////////////////////////////////////////////////////////// + // + // Front-panel GPIO + // + ///////////////////////////////////////////////////////////////////////////// + + wire [FP_GPIO_WIDTH-1:0] radio_gpio_in_sync; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg = ~0; + + // Double-synchronize the inputs to the PS + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) ps_gpio_in_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in), .out(ps_gpio_in) + ); + + // Double-synchronize the inputs to the radio + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) radio_gpio_in_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in), .out(radio_gpio_in_sync) + ); + + // Map the double-synchronized inputs to all radio channels + generate + for (i=0; i clk40_rst(n) + // + ////////////////////////////////////////////////////////////////////// + + // Synchronous reset for the bus_clk domain + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(~FCLK_RESET0_N), + //.reset_in(~clocks_locked), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + assign reg_rstn = clk40_rstn; + + ///////////////////////////////////////////////////////////////////// + // + // Clocks and PPS + // + ///////////////////////////////////////////////////////////////////// + + wire [1:0] pps_select; + + assign clk40 = FCLK_CLK1; // 40 MHz + assign bus_clk = FCLK_CLK0; // 100 MHz + assign reg_clk = clk40; + + reg [2:0] pps_reg; + + wire pps_ext = PPS_EXT_IN; + wire gps_pps = GPS_PPS; + + // connect PPS input to GPIO so ntpd can use it + always @ (posedge bus_clk) + pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS}; + assign ps_gpio_in[8] = pps_reg[2]; // 62 + + ///////////////////////////////////////////////////////////////////// + // + // Power Button + // + ////////////////////////////////////////////////////////////////////// + + // register the debounced onswitch signal to detect edges, + // Note: ONSWITCH_DB is low active + reg [1:0] onswitch_edge; + always @ (posedge bus_clk) + onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB}; + + wire button_press = ~ONSWITCH_DB & onswitch_edge[0] & onswitch_edge[1]; + wire button_release = ONSWITCH_DB & ~onswitch_edge[0] & ~onswitch_edge[1]; + + // stretch the pulse so IRQs don't get lost + reg [7:0] button_press_reg, button_release_reg; + always @ (posedge bus_clk) + if (bus_rst) begin + button_press_reg <= 8'h00; + button_release_reg <= 8'h00; + end else begin + button_press_reg <= {button_press_reg[6:0], button_press}; + button_release_reg <= {button_release_reg[6:0], button_release}; + end + + wire button_press_irq = |button_press_reg; + wire button_release_irq = |button_release_reg; + + ///////////////////////////////////////////////////////////////////// + // + // Interrupts Fabric to PS + // + ////////////////////////////////////////////////////////////////////// + + wire [15:0] IRQ_F2P; + wire pmu_irq; + assign IRQ_F2P = {12'b0, + pmu_irq, // Interrupt 32 + button_release_irq, // Interrupt 31 + button_press_irq, // Interrupt 30 + 1'b0}; + + ///////////////////////////////////////////////////////////////////// + // + // PS Connections + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_tri; + + e31x_ps_bd e31x_ps_bd_inst ( + + // DDR Interface + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_addr(DDR_ADDR), + .DDR_ba(DDR_BANKADDR), + .DDR_cas_n(DDR_CAS_N), + .DDR_ck_n(DDR_CLK_N), + .DDR_ck_p(DDR_CLK), + .DDR_cke(DDR_CKE), + .DDR_cs_n(DDR_CS_N), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_N), + .DDR_dqs_p(DDR_DQS), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_N), + .DDR_reset_n(DDR_RESET_N), + .DDR_we_n(DDR_WE_N), + + // Clocks + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(), + .FCLK_CLK3(), + + // Resets + .FCLK_RESET0_N(FCLK_RESET0_N), + + // GPIO + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + // Interrupts + .IRQ_F2P(IRQ_F2P), + + // MIO + .MIO(MIO), + + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + + // SPI + .SPI0_MISO_I(), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_MOSI_I(), + .SPI0_MOSI_O(), + .SPI0_MOSI_T(), + .SPI0_SCLK_I(), + .SPI0_SCLK_O(), + .SPI0_SCLK_T(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_I(), + .SPI0_SS_O(), + .SPI0_SS_T(), + + .SPI1_MISO_I(), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_MOSI_I(), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_SCLK_I(), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_I(), + .SPI1_SS_O(), + .SPI1_SS_T(), + + // USB + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + + // XBAR Regport + .m_axi_xbar_araddr(), + .m_axi_xbar_arprot(), + .m_axi_xbar_arready(), + .m_axi_xbar_arvalid(), + .m_axi_xbar_awaddr(), + .m_axi_xbar_awprot(), + .m_axi_xbar_awready(), + .m_axi_xbar_awvalid(), + .m_axi_xbar_bready(), + .m_axi_xbar_bresp(), + .m_axi_xbar_bvalid(), + .m_axi_xbar_rdata(), + .m_axi_xbar_rready(), + .m_axi_xbar_rresp(), + .m_axi_xbar_rvalid(), + .m_axi_xbar_wdata(), + .m_axi_xbar_wready(), + .m_axi_xbar_wstrb(), + .m_axi_xbar_wvalid(), + + // PMU + .m_axi_pmu_araddr(m_axi_pmu_araddr), + .m_axi_pmu_arprot(m_axi_pmu_arprot), + .m_axi_pmu_arready(m_axi_pmu_arready), + .m_axi_pmu_arvalid(m_axi_pmu_arvalid), + .m_axi_pmu_awaddr(m_axi_pmu_awaddr), + .m_axi_pmu_awprot(m_axi_pmu_awprot), + .m_axi_pmu_awready(m_axi_pmu_awready), + .m_axi_pmu_awvalid(m_axi_pmu_awvalid), + .m_axi_pmu_bready(m_axi_pmu_bready), + .m_axi_pmu_bresp(m_axi_pmu_bresp), + .m_axi_pmu_bvalid(m_axi_pmu_bvalid), + .m_axi_pmu_rdata(m_axi_pmu_rdata), + .m_axi_pmu_rready(m_axi_pmu_rready), + .m_axi_pmu_rresp(m_axi_pmu_rresp), + .m_axi_pmu_rvalid(m_axi_pmu_rvalid), + .m_axi_pmu_wdata(m_axi_pmu_wdata), + .m_axi_pmu_wready(m_axi_pmu_wready), + .m_axi_pmu_wstrb(m_axi_pmu_wstrb), + .m_axi_pmu_wvalid(m_axi_pmu_wvalid), + + // DMA + .s_axis_dma_tdata(), + .s_axis_dma_tdest(), + .s_axis_dma_tlast(), + .s_axis_dma_tready(), + .s_axis_dma_tvalid(1'b0), + .m_axis_dma_tdata(), + .m_axis_dma_tuser(), + .m_axis_dma_tlast(), + .m_axis_dma_tready(1'b1), + .m_axis_dma_tvalid() + ); + + ///////////////////////////////////////////////////////////////////// + // + // PMU + // + ////////////////////////////////////////////////////////////////////// + + axi_pmu inst_axi_pmu ( + .s_axi_aclk(clk40), // TODO: Original design used bus_clk + .s_axi_areset(clk40_rst), + + .ss(AVR_CS_R), + .mosi(AVR_MOSI_R), + .sck(AVR_SCK_R), + .miso(AVR_MISO_R), + + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_pmu_awaddr), + .s_axi_awvalid(m_axi_pmu_awvalid), + .s_axi_awready(m_axi_pmu_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_pmu_wdata), + .s_axi_wstrb(m_axi_pmu_wstrb), + .s_axi_wvalid(m_axi_pmu_wvalid), + .s_axi_wready(m_axi_pmu_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_pmu_bresp), + .s_axi_bvalid(m_axi_pmu_bvalid), + .s_axi_bready(m_axi_pmu_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_pmu_araddr), + .s_axi_arvalid(m_axi_pmu_arvalid), + .s_axi_arready(m_axi_pmu_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_pmu_rdata), + .s_axi_rresp(m_axi_pmu_rresp), + .s_axi_rvalid(m_axi_pmu_rvalid), + .s_axi_rready(m_axi_pmu_rready), + + .s_axi_irq(pmu_irq) + ); + + assign AVR_IRQ = 1'b0; + + localparam DB_E31X_IDLE_OUT = { + 1'b0, /* DB_EXP_18_24 (99) */ + 13'b0000000000000, /* leds & rx bandsels */ + 1'b0, /* CAT_FB_CLK (85) */ + 1'b0, /* CAT_TX_FRAME (84) */ + 1'b0, /* CAT_RX_DATA_CLK (83) */ + 25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58)*/ + 1'b0, /* CAT_SYNC(57) */ + 4'b0000, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */ + 3'b000, /* DB_EXP_1_8_V_{33,34,32} */ + 2'b00, /* CAT_CTRL_IN[1:0] (49,48) */ + 1'b0, /* CAT_MISO (47) */ + 4'b0000, /* CAT_{MOSI,SCLK,CS,RESETn) (46,45, 44, 43) */ + 1'b0, /* DB_1_8V_31 (42) */ + 8'h00, /* CAT_CTRL_OUT (41:34) */ + 1'b0, /* DB_1_8V_11 (33) */ + 1'b0, /* CAT_CTRL_IN3 (32) */ + 1'b0, /* DB_1_8V_10 (31) */ + 1'b0, /* CAT_CTRL_IN2 (30) */ + 1'b0, /* DB_1_8V_9 (29) */ + 1'b0, /* VCRX2_V2 (28) */ + 1'b0, /* DB_1_8V_8 (25) */ + 1'b0, /* VCRX2_V1 (26) */ + 1'b0, /* DB_1_8V_7 (25) */ + 1'b0, /* VCRX1_V2 (24) */ + 1'b0, /* DB_1_8V_6 (23) */ + 1'b0, /* VCRX1_V1 (22) */ + 1'b0, /* DB_1_8V_5 (21) */ + 1'b0, /* VCTXRX1_V2 (20) */ + 1'b0, /* DB_1_8V_4 (19) */ + 1'b0, /* VCTXRX1_V1 (18) */ + 1'b0, /* DB_1_8V_3 (17) */ + 1'b0, /* VCTXRX2_V1 (16) */ + 1'b1, /* DB_1_8V_2 (15) */ + 15'd0}; + + localparam DB_E31X_IDLE_DDR = { + 1'b0, /* DB_EXP_18_24 (99) */ + 13'b0101010101010, /* leds & rx bandsels */ + 1'b0, /* CAT_FB_CLK (85) */ + 1'b0, /* CAT_TX_FRAME (84) */ + 1'b0, /* CAT_RX_DATA_CLK (83) */ + 25'b0000_0000_0000_0000_0000_0000_0, /* CAT_RX_FRAME(81), CAT_P0 & CAT_P1 (58) */ + 1'b0, /* CAT_SYNC(57) */ + 4'b0001, /* CAT_ENAGC(56), CAT_BBCLK_OUT (55), CAT_ENABLE(54), CAT_TXNRX(53) */ + 3'b000, /* DB_EXP_1_8_V_{32,33,34,} (52, 51, 50) */ + 2'b00, /* CAT_CTRL_IN[1:0] (49,48) */ + 1'b0, /* CAT_MISO (47) */ + 4'b0111, /* CAT_{MOSI,SCLK,CS,RESETn) (46, 45, 44, 43) */ + 1'b0, /* DB_1_8V_31 (42) */ + 8'h00, /* CAT_CTRL_OUT (41:34) */ + 1'b0, /* DB_1_8V_11 (33) */ + 1'b0, /* CAT_CTRL_IN3 (32) */ + 1'b0, /* DB_1_8V_10 (31) */ + 1'b0, /* CAT_CTRL_IN2 (30) */ + 1'b0, /* DB_1_8V_9 (29) */ + 1'b0, /* VCRX2_V2 (28) */ + 1'b0, /* DB_1_8V_8 (25) */ + 1'b0, /* VCRX2_V1 (26) */ + 1'b0, /* DB_1_8V_7 (24) */ + 1'b0, /* VCRX1_V2 (24) */ + 1'b0, /* DB_1_8V_6 (23) */ + 1'b0, /* VCRX1_V1 (22) */ + 1'b0, /* DB_1_8V_5 (21) */ + 1'b0, /* VCTXRX1_V1 (20) */ + 1'b0, /* DB_1_8V_4 (19) */ + 1'b0, /* VCTXRX1_V2 (18) */ + 1'b1, /* DB_1_8V_3 (17) */ + 1'b0, /* VCTXRX2_V1 (16) */ + 1'b1, /* DB_1_8V_2 (15) */ + 15'd0}; + + localparam NUM_DB_IO_PINS = 100; + + wire [NUM_DB_IO_PINS-1:0] db_ddr = DB_E31X_IDLE_DDR; + wire [NUM_DB_IO_PINS-1:0] db_out = DB_E31X_IDLE_OUT; + wire [NUM_DB_IO_PINS-1:0] db_in; + + + genvar k; + generate + for (k = 0; k < NUM_DB_IO_PINS; k = k+1) begin + IOBUF db_io_i(.O(db_in[k]), .IO(DB_IO[k]), .I(db_out[k]), .T(~db_ddr[k])); + end + endgenerate + +endmodule // e31x diff --git a/fpga/usrp3/top/e31x/e31x_idle_pins.xdc b/fpga/usrp3/top/e31x/e31x_idle_pins.xdc new file mode 100644 index 000000000..28bd48d3e --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_idle_pins.xdc @@ -0,0 +1,507 @@ +############################################################################### +# Pin mapping +############################################################################### +## RF board connector pins + +# Pin 1 +set_property PACKAGE_PIN H19 [get_ports {DB_IO[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[0]}] + +# Pin 2 +# 3.3v DB + +# Pin 3 +set_property PACKAGE_PIN F19 [get_ports {DB_IO[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[1]}] + +#Pin 4 +# 3.3v DB + +#Pin 5 +set_property PACKAGE_PIN G19 [get_ports {DB_IO[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[2]}] + +#Pin 6 +set_property PACKAGE_PIN E19 [get_ports {DB_IO[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[3]}] + +#Pin 7 +set_property PACKAGE_PIN E20 [get_ports {DB_IO[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[4]}] + +#Pin 8 +set_property PACKAGE_PIN G21 [get_ports {DB_IO[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[5]}] + +#Pin 9 +set_property PACKAGE_PIN G22 [get_ports {DB_IO[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[6]}] + +#Pin 10 +set_property PACKAGE_PIN G20 [get_ports {DB_IO[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[7]}] + +#Pin 11 +set_property PACKAGE_PIN H22 [get_ports {DB_IO[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[8]}] + +#Pin 12 +set_property PACKAGE_PIN F22 [get_ports {DB_IO[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[9]}] + +#Pin 13 +set_property PACKAGE_PIN A17 [get_ports {DB_IO[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[10]}] + +#Pin 14 +set_property PACKAGE_PIN F21 [get_ports {DB_IO[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[11]}] + +#Pin 15 +set_property PACKAGE_PIN B16 [get_ports {DB_IO[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[12]}] + +#Pin 16 -- Not used +#set_property PACKAGE_PIN J21 [get_ports {}] +#set_property IOSTANDARD LVCMOS18 [get_ports {}] + +#Pin 17 +set_property PACKAGE_PIN A19 [get_ports {DB_IO[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[13]}] + +#Pin 18 -- Not used +#set_property PACKAGE_PIN J22 [get_ports {}] +#set_property IOSTANDARD LVCMOS18 [get_ports {}] + +#Pin 19 +set_property PACKAGE_PIN B15 [get_ports {DB_IO[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[14]}] + +#Pin 20 +set_property PACKAGE_PIN K21 [get_ports {DB_IO[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[15]}] + +#Pin 21 +set_property PACKAGE_PIN A16 [get_ports {DB_IO[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[16]}] + +#Pin 22 +set_property PACKAGE_PIN L22 [get_ports {DB_IO[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[17]}] + +#Pin 23 +set_property PACKAGE_PIN B17 [get_ports {DB_IO[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[18]}] + +#Pin 24 +set_property PACKAGE_PIN L21 [get_ports {DB_IO[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[19]}] + +#Pin 25 +set_property PACKAGE_PIN C15 [get_ports {DB_IO[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[20]}] + +#Pin 26 +set_property PACKAGE_PIN R18 [get_ports {DB_IO[21]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[21]}] + +#Pin 27 +set_property PACKAGE_PIN E18 [get_ports {DB_IO[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[22]}] + +#Pin 28 +set_property PACKAGE_PIN T18 [get_ports {DB_IO[23]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[23]}] + +#Pin 29 +set_property PACKAGE_PIN F18 [get_ports {DB_IO[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[24]}] + +#Pin 30 +set_property PACKAGE_PIN M20 [get_ports {DB_IO[25]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[25]}] + +#Pin 31 +set_property PACKAGE_PIN F17 [get_ports {DB_IO[26]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[26]}] + +#Pin 32 +set_property PACKAGE_PIN M15 [get_ports {DB_IO[27]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[27]}] + +#Pin 33 +set_property PACKAGE_PIN G17 [get_ports {DB_IO[28]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB_IO[28]}] + +#Pin 34 +set_property PACKAGE_PIN J18 [get_ports {DB_IO[29]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[29]}] + +#Pin 35 +set_property PACKAGE_PIN U5 [get_ports {DB_IO[30]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[30]}] + +#Pin 36 +set_property PACKAGE_PIN J20 [get_ports {DB_IO[31]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[31]}] + +#Pin 37 +set_property PACKAGE_PIN U6 [get_ports {DB_IO[32]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[32]}] + +#Pin 38 +set_property PACKAGE_PIN K19 [get_ports {DB_IO[33]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[33]}] + +#Pin 39 +set_property PACKAGE_PIN AB5 [get_ports {DB_IO[34]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[34]}] + +#Pin 40 +set_property PACKAGE_PIN K20 [get_ports {DB_IO[35]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[35]}] + +#Pin 41 +set_property PACKAGE_PIN AB6 [get_ports {DB_IO[36]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[36]}] + +#Pin 42 +set_property PACKAGE_PIN L19 [get_ports {DB_IO[37]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[37]}] + +#Pin 43 +set_property PACKAGE_PIN AB7 [get_ports {DB_IO[38]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[38]}] + +#Pin 44 +set_property PACKAGE_PIN V12 [get_ports {DB_IO[39]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[39]}] + +#Pin 45 +set_property PACKAGE_PIN AA4 [get_ports {DB_IO[40]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[40]}] + +#Pin 46 +set_property PACKAGE_PIN W12 [get_ports {DB_IO[41]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[41]}] + +#Pin 47 +set_property PACKAGE_PIN T6 [get_ports {DB_IO[42]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[42]}] + +#Pin 48 +set_property PACKAGE_PIN U11 [get_ports {DB_IO[43]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[43]}] + +#Pin 49 +# 1.8V + +#Pin 50 +set_property PACKAGE_PIN W6 [get_ports {DB_IO[44]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[44]}] + +#Pin 51 +# 1.8V + +#Pin 52 +set_property PACKAGE_PIN W5 [get_ports {DB_IO[45]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[45]}] + +#Pin 53 +# 5V + +#Pin 54 +set_property PACKAGE_PIN V7 [get_ports {DB_IO[46]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[46]}] + +#Pin 55 +# 5V + +#Pin 56 +set_property PACKAGE_PIN W7 [get_ports {DB_IO[47]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[47]}] + +#Pin 57 +# 5V + +#Pin 58 +set_property PACKAGE_PIN V4 [get_ports {DB_IO[48]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[48]}] + +#Pin 59 +# 5V + +#Pin 60 +set_property PACKAGE_PIN V5 [get_ports {DB_IO[49]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[49]}] + +#Pin 61 +# 1.8V + +#Pin 62 +set_property PACKAGE_PIN U4 [get_ports {DB_IO[50]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[50]}] + +#Pin 63 +# 1.8V + +#Pin 64 +set_property PACKAGE_PIN T4 [get_ports {DB_IO[51]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[51]}] + +#Pin 65 +# GND + +#Pin 66 +set_property PACKAGE_PIN R6 [get_ports {DB_IO[52]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[52]}] + +#Pin 67 +set_property PACKAGE_PIN AB1 [get_ports {DB_IO[53]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[53]}] + +#Pin 68 +# GND + +#Pin 69 +set_property PACKAGE_PIN AB4 [get_ports {DB_IO[54]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[54]}] + +#Pin 70 +set_property PACKAGE_PIN M19 [get_ports {DB_IO[55]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[55]}] + +#Pin 71 +set_property PACKAGE_PIN AB2 [get_ports {DB_IO[56]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[56]}] + +#Pin 72 +# GND + +#Pin 73 +# GND + +#Pin 74 +set_property PACKAGE_PIN T16 [get_ports {DB_IO[57]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[57]}] + +#Pin 75 +set_property PACKAGE_PIN J15 [get_ports {DB_IO[58]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[58]}] + +#Pin 76 +# GND + +#Pin 77 +set_property PACKAGE_PIN J16 [get_ports {DB_IO[59]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[59]}] + +#Pin 78 +set_property PACKAGE_PIN N15 [get_ports {DB_IO[60]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[60]}] + +#Pin 79 +set_property PACKAGE_PIN J17 [get_ports {DB_IO[61]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[61]}] + +#Pin 80 +set_property PACKAGE_PIN M21 [get_ports {DB_IO[62]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[62]}] + +#Pin 81 +set_property PACKAGE_PIN K15 [get_ports {DB_IO[63]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[63]}] + +#Pin 82 +set_property PACKAGE_PIN P15 [get_ports {DB_IO[64]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[64]}] + +#Pin 83 +set_property PACKAGE_PIN K18 [get_ports {DB_IO[65]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[65]}] + +#Pin 84 +set_property PACKAGE_PIN N19 [get_ports {DB_IO[66]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[66]}] + +#Pin 85 +set_property PACKAGE_PIN K16 [get_ports {DB_IO[67]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[67]}] + +#Pin 86 +set_property PACKAGE_PIN P18 [get_ports {DB_IO[68]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[68]}] + +#Pin 87 +set_property PACKAGE_PIN L16 [get_ports {DB_IO[69]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[69]}] + +#Pin 88 +set_property PACKAGE_PIN P20 [get_ports {DB_IO[70]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[70]}] + +#Pin 89 +set_property PACKAGE_PIN L17 [get_ports {DB_IO[71]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[71]}] + +#Pin 90 +set_property PACKAGE_PIN P17 [get_ports {DB_IO[72]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[72]}] + +#Pin 91 +set_property PACKAGE_PIN M16 [get_ports {DB_IO[73]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[73]}] + +#Pin 92 +set_property PACKAGE_PIN P21 [get_ports {DB_IO[74]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[74]}] + +#Pin 93 +set_property PACKAGE_PIN M17 [get_ports {DB_IO[75]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[75]}] + +#Pin 94 +set_property PACKAGE_PIN R20 [get_ports {DB_IO[76]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[76]}] + +#Pin 95 +set_property PACKAGE_PIN N17 [get_ports {DB_IO[77]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[77]}] + +#Pin 96 +set_property PACKAGE_PIN T17 [get_ports {DB_IO[78]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[78]}] + +#Pin 97 +set_property PACKAGE_PIN N20 [get_ports {DB_IO[79]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[79]}] + +#Pin 98 +set_property PACKAGE_PIN M22 [get_ports {DB_IO[80]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[80]}] + +#Pin 99 +set_property PACKAGE_PIN N18 [get_ports {DB_IO[81]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[81]}] + +#Pin 100 +set_property PACKAGE_PIN N22 [get_ports {DB_IO[82]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[82]}] + +#Pin 101 +set_property PACKAGE_PIN L18 [get_ports {DB_IO[83]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[83]}] + +#Pin 102 +set_property PACKAGE_PIN P22 [get_ports {DB_IO[84]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[84]}] + +#Pin 103 +# GND + +#Pin 104 +set_property PACKAGE_PIN R21 [get_ports {DB_IO[85]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[85]}] + +#Pin 105 +# 1.8V + +#Pin 106 +# GND + +#Pin 107 +set_property PACKAGE_PIN AA8 [get_ports {DB_IO[86]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[86]}] + +#Pin 108 +set_property PACKAGE_PIN Y11 [get_ports {DB_IO[87]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[87]}] + +#Pin 109 +set_property PACKAGE_PIN AA9 [get_ports {DB_IO[88]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[88]}] + +#Pin 110 +set_property PACKAGE_PIN AB10 [get_ports {DB_IO[89]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[89]}] + +#Pin 111 +set_property PACKAGE_PIN AB9 [get_ports {DB_IO[90]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[90]}] + +#Pin 112 +set_property PACKAGE_PIN AA12 [get_ports {DB_IO[91]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[91]}] + +#Pin 113 +set_property PACKAGE_PIN U10 [get_ports {DB_IO[92]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[92]}] + +#Pin 114 +set_property PACKAGE_PIN U12 [get_ports {DB_IO[93]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[93]}] + +#Pin 115 +set_property PACKAGE_PIN Y10 [get_ports {DB_IO[94]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[94]}] + +#Pin 116 +set_property PACKAGE_PIN AB11 [get_ports {DB_IO[95]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[95]}] + +#Pin 117 +set_property PACKAGE_PIN U9 [get_ports {DB_IO[96]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[96]}] + +#Pin 118 +set_property PACKAGE_PIN AA11 [get_ports {DB_IO[97]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[97]}] + +#Pin 119 +set_property PACKAGE_PIN Y4 [get_ports {DB_IO[98]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[98]}] + +#Pin 120 +set_property PACKAGE_PIN AB12 [get_ports {DB_IO[99]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_IO[99]}] + +### Other I/O +set_property PACKAGE_PIN A22 [get_ports AVR_CS_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_CS_R] +set_property PACKAGE_PIN B22 [get_ports AVR_IRQ] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_IRQ] +set_property PACKAGE_PIN C22 [get_ports AVR_MISO_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_MISO_R] +set_property PACKAGE_PIN A21 [get_ports AVR_MOSI_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_MOSI_R] +set_property PACKAGE_PIN D22 [get_ports AVR_SCK_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_SCK_R] + +set_property PACKAGE_PIN E21 [get_ports ONSWITCH_DB] +set_property IOSTANDARD LVCMOS33 [get_ports ONSWITCH_DB] + +set_property PACKAGE_PIN Y9 [get_ports GPS_PPS] +set_property IOSTANDARD LVCMOS18 [get_ports GPS_PPS] + +set_property PACKAGE_PIN D18 [get_ports PPS_EXT_IN] +set_property IOSTANDARD LVCMOS33 [get_ports PPS_EXT_IN] + +set_property PACKAGE_PIN E16 [get_ports {PL_GPIO[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[0]}] +set_property PACKAGE_PIN C18 [get_ports {PL_GPIO[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[1]}] +set_property PACKAGE_PIN D17 [get_ports {PL_GPIO[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[2]}] +set_property PACKAGE_PIN D16 [get_ports {PL_GPIO[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[3]}] +set_property PACKAGE_PIN D15 [get_ports {PL_GPIO[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[4]}] +set_property PACKAGE_PIN E15 [get_ports {PL_GPIO[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[5]}] +set_property PULLDOWN true [get_ports {PL_GPIO[0]}] +set_property PULLDOWN true [get_ports {PL_GPIO[1]}] +set_property PULLDOWN true [get_ports {PL_GPIO[2]}] +set_property PULLDOWN true [get_ports {PL_GPIO[3]}] +set_property PULLDOWN true [get_ports {PL_GPIO[4]}] +set_property PULLDOWN true [get_ports {PL_GPIO[5]}] + diff --git a/fpga/usrp3/top/e31x/e31x_pins.xdc b/fpga/usrp3/top/e31x/e31x_pins.xdc new file mode 100644 index 000000000..8fd52b429 --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_pins.xdc @@ -0,0 +1,507 @@ +############################################################################### +# Pin mapping +############################################################################### +## RF board connector pins + +# Pin 1 +set_property PACKAGE_PIN H19 [get_ports {TX_BANDSEL[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[2]}] + +# Pin 2 +# 3.3v DB + +# Pin 3 +set_property PACKAGE_PIN F19 [get_ports {RX1B_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1B_BANDSEL[0]}] + +#Pin 4 +# 3.3v DB + +#Pin 5 +set_property PACKAGE_PIN G19 [get_ports {RX1B_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1B_BANDSEL[1]}] + +#Pin 6 +set_property PACKAGE_PIN E19 [get_ports {RX1_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[0]}] + +#Pin 7 +set_property PACKAGE_PIN E20 [get_ports VCTXRX2_V2] +set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX2_V2] + +#Pin 8 +set_property PACKAGE_PIN G21 [get_ports {RX1_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[1]}] + +#Pin 9 +set_property PACKAGE_PIN G22 [get_ports TX_ENABLE1A] +set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE1A] + +#Pin 10 +set_property PACKAGE_PIN G20 [get_ports {RX1_BANDSEL[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1_BANDSEL[2]}] + +#Pin 11 +set_property PACKAGE_PIN H22 [get_ports TX_ENABLE2A] +set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE2A] + +#Pin 12 +set_property PACKAGE_PIN F22 [get_ports {TX_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[0]}] + +#Pin 13 +set_property PACKAGE_PIN A17 [get_ports TX_ENABLE1B] +set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE1B] + +#Pin 14 +set_property PACKAGE_PIN F21 [get_ports {TX_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {TX_BANDSEL[1]}] + +#Pin 15 +set_property PACKAGE_PIN B16 [get_ports TX_ENABLE2B] +set_property IOSTANDARD LVCMOS33 [get_ports TX_ENABLE2B] + +#Pin 16 -- Not used +#set_property PACKAGE_PIN J21 [get_ports DB_SCL] +#set_property IOSTANDARD LVCMOS18 [get_ports DB_SCL] + +#Pin 17 +set_property PACKAGE_PIN A19 [get_ports {RX1C_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1C_BANDSEL[0]}] + +#Pin 18 -- Not used +#set_property PACKAGE_PIN J22 [get_ports DB_SDA] +#set_property IOSTANDARD LVCMOS18 [get_ports DB_SDA] + +#Pin 19 +set_property PACKAGE_PIN B15 [get_ports {RX1C_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX1C_BANDSEL[1]}] + +#Pin 20 +set_property PACKAGE_PIN K21 [get_ports TCXO_DAC_SYNC_N] +set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SYNC_N] + +#Pin 21 +set_property PACKAGE_PIN A16 [get_ports VCTXRX2_V1] +set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX2_V1] + +#Pin 22 +set_property PACKAGE_PIN L22 [get_ports TCXO_DAC_SCLK] +set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SCLK] + +#Pin 23 +set_property PACKAGE_PIN B17 [get_ports VCTXRX1_V2] +set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX1_V2] + +#Pin 24 +set_property PACKAGE_PIN L21 [get_ports TCXO_DAC_SDIN] +set_property IOSTANDARD LVCMOS18 [get_ports TCXO_DAC_SDIN] + +#Pin 25 +set_property PACKAGE_PIN C15 [get_ports VCTXRX1_V1] +set_property IOSTANDARD LVCMOS33 [get_ports VCTXRX1_V1] + +#Pin 26 +set_property PACKAGE_PIN R18 [get_ports {DB_EXP_1_8V[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[5]}] + +#Pin 27 +set_property PACKAGE_PIN E18 [get_ports VCRX1_V1] +set_property IOSTANDARD LVCMOS33 [get_ports VCRX1_V1] + +#Pin 28 +set_property PACKAGE_PIN T18 [get_ports {DB_EXP_1_8V[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[6]}] + +#Pin 29 +set_property PACKAGE_PIN F18 [get_ports VCRX1_V2] +set_property IOSTANDARD LVCMOS33 [get_ports VCRX1_V2] + +#Pin 30 +set_property PACKAGE_PIN M20 [get_ports TCXO_CLK] +set_property IOSTANDARD LVCMOS18 [get_ports TCXO_CLK] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCXO_CLK] + +#Pin 31 +set_property PACKAGE_PIN F17 [get_ports VCRX2_V1] +set_property IOSTANDARD LVCMOS33 [get_ports VCRX2_V1] + +#Pin 32 +set_property PACKAGE_PIN M15 [get_ports {DB_EXP_1_8V[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[8]}] + +#Pin 33 +set_property PACKAGE_PIN G17 [get_ports VCRX2_V2] +set_property IOSTANDARD LVCMOS33 [get_ports VCRX2_V2] + +#Pin 34 +set_property PACKAGE_PIN J18 [get_ports {DB_EXP_1_8V[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[9]}] + +#Pin 35 +set_property PACKAGE_PIN U5 [get_ports {CAT_CTRL_IN[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[2]}] + +#Pin 36 +set_property PACKAGE_PIN J20 [get_ports {DB_EXP_1_8V[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[10]}] + +#Pin 37 +set_property PACKAGE_PIN U6 [get_ports {CAT_CTRL_IN[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[3]}] + +#Pin 38 +set_property PACKAGE_PIN K19 [get_ports {DB_EXP_1_8V[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[11]}] + +#Pin 39 +set_property PACKAGE_PIN AB5 [get_ports {CAT_CTRL_OUT[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[0]}] + +#Pin 40 +set_property PACKAGE_PIN K20 [get_ports {CAT_CTRL_OUT[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[4]}] + +#Pin 41 +set_property PACKAGE_PIN AB6 [get_ports {CAT_CTRL_OUT[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[1]}] + +#Pin 42 +set_property PACKAGE_PIN L19 [get_ports {CAT_CTRL_OUT[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[5]}] + +#Pin 43 +set_property PACKAGE_PIN AB7 [get_ports {CAT_CTRL_OUT[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[2]}] + +#Pin 44 +set_property PACKAGE_PIN V12 [get_ports {CAT_CTRL_OUT[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[6]}] + +#Pin 45 +set_property PACKAGE_PIN AA4 [get_ports {CAT_CTRL_OUT[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[3]}] + +#Pin 46 +set_property PACKAGE_PIN W12 [get_ports {CAT_CTRL_OUT[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_OUT[7]}] + +#Pin 47 +set_property PACKAGE_PIN T6 [get_ports {DB_EXP_1_8V[31]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[31]}] + +#Pin 48 +set_property PACKAGE_PIN U11 [get_ports CAT_RESET] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_RESET] + +#Pin 49 +# 1.8V + +#Pin 50 +set_property PACKAGE_PIN W6 [get_ports CAT_CS] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_CS] + +#Pin 51 +# 1.8V +#Pin 52 +set_property PACKAGE_PIN W5 [get_ports CAT_SCLK] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_SCLK] + +#Pin 53 +# 5V + +#Pin 54 +set_property PACKAGE_PIN V7 [get_ports CAT_MOSI] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_MOSI] + +#Pin 55 +# 5V + +#Pin 56 +set_property PACKAGE_PIN W7 [get_ports CAT_MISO] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_MISO] + +#Pin 57 +# 5V + +#Pin 58 +set_property PACKAGE_PIN V4 [get_ports {CAT_CTRL_IN[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[0]}] + +#Pin 59 +# 5V + +#Pin 60 +set_property PACKAGE_PIN V5 [get_ports {CAT_CTRL_IN[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_CTRL_IN[1]}] + +#Pin 61 +# 1.8V + +#Pin 62 +set_property PACKAGE_PIN U4 [get_ports {DB_EXP_1_8V[33]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[33]}] + +#Pin 63 +# 1.8V + +#Pin 64 +set_property PACKAGE_PIN T4 [get_ports {DB_EXP_1_8V[34]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[34]}] +#Pin 65 +# GND + +#Pin 66 +set_property PACKAGE_PIN R6 [get_ports {DB_EXP_1_8V[32]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[32]}] + +#Pin 67 +set_property PACKAGE_PIN AB1 [get_ports CAT_TXNRX] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_TXNRX] + +#Pin 68 +# GND + +#Pin 69 +set_property PACKAGE_PIN AB4 [get_ports CAT_ENABLE] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_ENABLE] + +#Pin 70 +set_property PACKAGE_PIN M19 [get_ports CAT_BBCLK_OUT] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_BBCLK_OUT] + +#Pin 71 +set_property PACKAGE_PIN AB2 [get_ports CAT_ENAGC] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_ENAGC] + +#Pin 72 +# GND + +#Pin 73 +# GND + +#Pin 74 +set_property PACKAGE_PIN T16 [get_ports CAT_SYNC] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_SYNC] + +#Pin 78 +set_property PACKAGE_PIN N15 [get_ports {CAT_P1_D[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[11]}] + +#Pin 76 +# GND + +#Pin 100 +set_property PACKAGE_PIN N22 [get_ports {CAT_P1_D[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[10]}] + +#Pin 93 +set_property PACKAGE_PIN M17 [get_ports {CAT_P0_D[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[11]}] + +#Pin 96 +set_property PACKAGE_PIN T17 [get_ports {CAT_P1_D[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[9]}] + +#Pin 95 +set_property PACKAGE_PIN N17 [get_ports {CAT_P0_D[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[10]}] + +#Pin 98 +set_property PACKAGE_PIN M22 [get_ports {CAT_P1_D[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[8]}] + +#Pin 81 +set_property PACKAGE_PIN K15 [get_ports {CAT_P0_D[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[9]}] + +#Pin 92 +set_property PACKAGE_PIN P21 [get_ports {CAT_P1_D[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[7]}] + +#Pin 97 +set_property PACKAGE_PIN N20 [get_ports {CAT_P0_D[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[8]}] + +#Pin 94 +set_property PACKAGE_PIN R20 [get_ports {CAT_P1_D[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[6]}] + +#Pin 77 +set_property PACKAGE_PIN J16 [get_ports {CAT_P0_D[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[7]}] + +#Pin 86 +set_property PACKAGE_PIN P18 [get_ports {CAT_P1_D[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[5]}] + +#Pin 85 +set_property PACKAGE_PIN K16 [get_ports {CAT_P0_D[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[6]}] + +#Pin 90 +set_property PACKAGE_PIN P17 [get_ports {CAT_P1_D[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[4]}] + +#Pin 75 +set_property PACKAGE_PIN J15 [get_ports {CAT_P0_D[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[5]}] + +#Pin 82 +set_property PACKAGE_PIN P15 [get_ports {CAT_P1_D[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[3]}] + +#Pin 91 +set_property PACKAGE_PIN M16 [get_ports {CAT_P0_D[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[4]}] + +#Pin 88 +set_property PACKAGE_PIN P20 [get_ports {CAT_P1_D[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[2]}] + +#Pin 79 +set_property PACKAGE_PIN J17 [get_ports {CAT_P0_D[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[3]}] + +#Pin 80 +set_property PACKAGE_PIN M21 [get_ports {CAT_P1_D[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[1]}] + +#Pin 89 +set_property PACKAGE_PIN L17 [get_ports {CAT_P0_D[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[2]}] + +#Pin 84 +set_property PACKAGE_PIN N19 [get_ports {CAT_P1_D[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P1_D[0]}] + +#Pin 83 +set_property PACKAGE_PIN K18 [get_ports {CAT_P0_D[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[1]}] + +#Pin 102 +set_property PACKAGE_PIN P22 [get_ports CAT_TX_FRAME] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_TX_FRAME] + +#Pin 87 +set_property PACKAGE_PIN L16 [get_ports {CAT_P0_D[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {CAT_P0_D[0]}] + +#Pin 104 +set_property PACKAGE_PIN R21 [get_ports CAT_FB_CLK] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_FB_CLK] + +#Pin 99 +set_property PACKAGE_PIN N18 [get_ports CAT_RX_FRAME] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_RX_FRAME] + +#Pin 103 +# GND + +#Pin 101 +set_property PACKAGE_PIN L18 [get_ports CAT_DATA_CLK] +set_property IOSTANDARD LVCMOS18 [get_ports CAT_DATA_CLK] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CAT_DATA_CLK] + +#Pin 105 +# 1.8V + +#Pin 106 +# GND + +#Pin 107 +set_property PACKAGE_PIN AA8 [get_ports {RX2_BANDSEL[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[2]}] + +#Pin 108 +set_property PACKAGE_PIN Y11 [get_ports LED_TXRX1_TX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX1_TX] + +#Pin 109 +set_property PACKAGE_PIN AA9 [get_ports {RX2_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[1]}] + +#Pin 110 +set_property PACKAGE_PIN AB10 [get_ports LED_TXRX1_RX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX1_RX] + +#Pin 111 +set_property PACKAGE_PIN AB9 [get_ports {RX2_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BANDSEL[0]}] + +#Pin 112 +set_property PACKAGE_PIN AA12 [get_ports LED_RX1_RX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_RX1_RX] + +#Pin 113 +set_property PACKAGE_PIN U10 [get_ports {RX2C_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2C_BANDSEL[1]}] + +#Pin 114 +set_property PACKAGE_PIN U12 [get_ports LED_TXRX2_TX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX2_TX] + +#Pin 115 +set_property PACKAGE_PIN Y10 [get_ports {RX2C_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2C_BANDSEL[0]}] + +#Pin 116 +set_property PACKAGE_PIN AB11 [get_ports LED_TXRX2_RX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_TXRX2_RX] + +#Pin 117 +set_property PACKAGE_PIN U9 [get_ports {RX2B_BANDSEL[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2B_BANDSEL[1]}] + +#Pin 118 +set_property PACKAGE_PIN AA11 [get_ports LED_RX2_RX] +set_property IOSTANDARD LVCMOS18 [get_ports LED_RX2_RX] + +#Pin 119 +set_property PACKAGE_PIN Y4 [get_ports {RX2B_BANDSEL[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2B_BANDSEL[0]}] + +#Pin 120 +set_property PACKAGE_PIN AB12 [get_ports {DB_EXP_1_8V[24]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB_EXP_1_8V[24]}] + +### Other I/O +set_property PACKAGE_PIN A22 [get_ports AVR_CS_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_CS_R] +set_property PACKAGE_PIN B22 [get_ports AVR_IRQ] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_IRQ] +set_property PACKAGE_PIN C22 [get_ports AVR_MISO_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_MISO_R] +set_property PACKAGE_PIN A21 [get_ports AVR_MOSI_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_MOSI_R] +set_property PACKAGE_PIN D22 [get_ports AVR_SCK_R] +set_property IOSTANDARD LVCMOS33 [get_ports AVR_SCK_R] + +set_property PACKAGE_PIN E21 [get_ports ONSWITCH_DB] +set_property IOSTANDARD LVCMOS33 [get_ports ONSWITCH_DB] + +set_property PACKAGE_PIN Y9 [get_ports GPS_PPS] +set_property IOSTANDARD LVCMOS18 [get_ports GPS_PPS] + +set_property PACKAGE_PIN D18 [get_ports PPS_EXT_IN] +set_property IOSTANDARD LVCMOS33 [get_ports PPS_EXT_IN] + +set_property PACKAGE_PIN E16 [get_ports {PL_GPIO[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[0]}] +set_property PACKAGE_PIN C18 [get_ports {PL_GPIO[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[1]}] +set_property PACKAGE_PIN D17 [get_ports {PL_GPIO[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[2]}] +set_property PACKAGE_PIN D16 [get_ports {PL_GPIO[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[3]}] +set_property PACKAGE_PIN D15 [get_ports {PL_GPIO[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[4]}] +set_property PACKAGE_PIN E15 [get_ports {PL_GPIO[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {PL_GPIO[5]}] +set_property PULLDOWN true [get_ports {PL_GPIO[0]}] +set_property PULLDOWN true [get_ports {PL_GPIO[1]}] +set_property PULLDOWN true [get_ports {PL_GPIO[2]}] +set_property PULLDOWN true [get_ports {PL_GPIO[3]}] +set_property PULLDOWN true [get_ports {PL_GPIO[4]}] +set_property PULLDOWN true [get_ports {PL_GPIO[5]}] + diff --git a/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.v b/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.v new file mode 100644 index 000000000..2f035d524 --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.v @@ -0,0 +1,461 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for e31x) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:15.219909 +// Source: ./e31x/e31x_rfnoc_image_core.yml +// Source SHA256: 48e2907163bf8462812f33b7cf995da37c44d9652ba3afa38c510910a2365c05 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio + output wire [ 1-1:0] m_ctrlport_req_wr, + output wire [ 1-1:0] m_ctrlport_req_rd, + output wire [ 20-1:0] m_ctrlport_req_addr, + output wire [ 32-1:0] m_ctrlport_req_data, + output wire [ 4-1:0] m_ctrlport_req_byte_en, + output wire [ 1-1:0] m_ctrlport_req_has_time, + output wire [ 64-1:0] m_ctrlport_req_time, + input wire [ 1-1:0] m_ctrlport_resp_ack, + input wire [ 2-1:0] m_ctrlport_resp_status, + input wire [ 32-1:0] m_ctrlport_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio + input wire [ 64-1:0] radio_rx_data, + input wire [ 2-1:0] radio_rx_stb, + output wire [ 2-1:0] radio_rx_running, + output wire [ 64-1:0] radio_tx_data, + input wire [ 2-1:0] radio_tx_stb, + output wire [ 2-1:0] radio_tx_running, + // Transport 0 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (3), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (1), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata}), + .s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast}), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}), + .m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata}), + .m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast}), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (3), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hE310), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (1), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (1), + .NUM_EDGES (4), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data; + + assign radio0_radio_rx_data = radio_rx_data; + assign radio0_radio_rx_stb = radio_rx_stb; + assign radio_rx_running = radio0_radio_rx_running; + assign radio_tx_data = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb; + assign radio_tx_running = radio0_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.yml b/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.yml new file mode 100644 index 000000000..066f7ab0e --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_rfnoc_image_core.yml @@ -0,0 +1,54 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'e31x' +default_target: 'E310_SG3' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: # NoC block name + block_desc: 'radio_2x64.yml' # Block device descriptor + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio } + - { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } diff --git a/fpga/usrp3/top/e31x/e31x_timing.xdc b/fpga/usrp3/top/e31x/e31x_timing.xdc new file mode 100644 index 000000000..f1e32e9a2 --- /dev/null +++ b/fpga/usrp3/top/e31x/e31x_timing.xdc @@ -0,0 +1,157 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Description: Timing constraints for the USRP E31X +# + + +############################################################################### +# Input Clocks +############################################################################### + +# 10MHz / PPS References +create_clock -period 100.000 -name pps_ext [get_nets PPS_EXT_IN] + +create_clock -period 100.000 -name gps_pps [get_nets GPS_PPS] + +# TCXO clock 40 MHz +create_clock -period 25.000 -name TCXO_CLK [get_nets TCXO_CLK] +set_input_jitter TCXO_CLK 0.100 + +############################################################################### +# Rename Clocks +############################################################################### + +create_clock -period 10.000 \ + -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]}] +set_input_jitter bus_clk 0.300 + +create_clock -period 25.000 \ + -name clk40 [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[1]}] +set_input_jitter clk40 0.750 + +#create_clock -period 5.000 \ +# -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[3]}] +#set_input_jitter bus_clk 0.150 + +############################################################################### +# Timing Constraints for E310 daughter board signals +############################################################################### +# CAT_DATA_CLK is the data clock from AD9361, sample rate dependent with a max rate of 61.44 MHz +set cat_data_clk_period 16.276; +set cat_data_clk_duty_cycle_var [expr $cat_data_clk_period * (0.55 - 0.45)]; +set tcxo_jitter 0.0005; # Calculated from datasheet phase noise +create_clock -period $cat_data_clk_period -name CAT_DATA_CLK [get_ports CAT_DATA_CLK] +# Model variable duty cycle as jitter. +set_input_jitter CAT_DATA_CLK [expr $cat_data_clk_duty_cycle_var + $tcxo_jitter] + +# Generate DAC output clock +create_generated_clock -name CAT_FB_CLK -multiply_by 1 -source [get_pins e310_io/oddr_clk/C] [get_ports CAT_FB_CLK] + +# Asynchronous clock domains +set_clock_groups -asynchronous \ + -group [get_clocks -include_generated_clocks CAT_DATA_CLK] \ + -group [get_clocks -include_generated_clocks bus_clk] \ + -group [get_clocks -include_generated_clocks TCXO_CLK] + +set_clock_groups -asynchronous \ + -group [get_clocks -include_generated_clocks *clk_200M_o] \ + -group [get_clocks -include_generated_clocks pps_ext] \ + -group [get_clocks -include_generated_clocks gps_pps] + + +#TODO: I don't think this was getting used on E310 +# Logically exclusive clocks in catcodec capture interface. These two clocks are the input to a BUFG mux that +# drives radio_clk, meaning only one of the two can drive radio_clk at a time. +#set_clock_groups -logically_exclusive # -group [get_clocks -include_generated_clocks {clk0}] # -group [get_clocks -include_generated_clocks {clkdv}] + +# Setup ADC (AD9361) interface constraints. +set cat_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay RX data by 4.5 ns +set cat_data_clk_to_data_out_min 0; +set cat_data_clk_to_data_out_max 1.2; + +set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}] +set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}] +set_input_delay -clock [get_clocks CAT_DATA_CLK] -max [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_max] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay +set_input_delay -clock [get_clocks CAT_DATA_CLK] -min [expr $cat_data_prog_dly + $cat_data_clk_to_data_out_min] [get_ports {CAT_P0_D* CAT_RX_FRAME}] -clock_fall -add_delay + +set cat_fb_data_prog_dly 4.5; # Programmable skew in AD9361 set to delay TX data by 4.5 ns +set cat_fb_data_setup 1.0; +set cat_fb_data_hold 0; + +set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}] +set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}] +set_output_delay -clock CAT_FB_CLK -max [expr $cat_fb_data_prog_dly + $cat_fb_data_setup] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay; +set_output_delay -clock CAT_FB_CLK -min [expr $cat_fb_data_prog_dly - $cat_fb_data_hold] [get_ports {CAT_P1_D* CAT_TX_FRAME}] -clock_fall -add_delay; + +# TODO: CAT SPI +# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI +# clock is not accessible. So delay constraints are used to limit the delays to +# compatible values. + +# Transceiver SPI +set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \ + -to [get_ports CAT_MOSI] 10.000 -datapath_only +set_min_delay -to [get_ports CAT_MOSI] 1.000 +# +set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \ + -to [get_ports CAT_SCLK] 10.000 -datapath_only +set_min_delay -to [get_ports CAT_SCLK] 1.000 +# +set_max_delay -from [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]}] \ + -to [get_ports CAT_CS] 10.000 -datapath_only +set_min_delay -to [get_ports CAT_CS] 1.000 +# +set_max_delay -from [get_ports CAT_MISO] \ + -to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 10.000 -datapath_only +set_min_delay -from [get_ports CAT_MISO] \ + -to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 1.000 + +############################################################################### +# PPS and Ref Clk Input Timing +############################################################################### + +# Asynchronous clock domains +set_clock_groups -asynchronous \ + -group [get_clocks -include_generated_clocks bus_clk] \ + -group [get_clocks -include_generated_clocks pps_ext] \ + -group [get_clocks -include_generated_clocks gps_pps] + +# TCXO DAC SPI +# 12 MHz SPI clock rate +set_max_delay -datapath_only -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 40.000 +set_min_delay -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 1.000 + +# User GPIO +set_max_delay -datapath_only -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] [expr 15.0] +set_min_delay -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] 5.0 +set_max_delay -datapath_only -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] [expr 15.0] +set_min_delay -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] 5.0 + +# GPIO muxing +set_max_delay -from [get_pins e31x_core_inst/fp_gpio_src_reg_reg[*]/C] -to [get_clocks CAT_DATA_CLK] $cat_data_clk_period -datapath_only + +############################################################################### +# False Paths +############################################################################### + +# Synchronizer core false paths +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}] + +# USR_ACCESS build date +set_false_path -through [get_pins {usr_access_i/DATA[*]}] + +############################################################################### +## Asynchronous paths +############################################################################### +set_false_path -from [get_ports CAT_CTRL_OUT] +set_false_path -to [get_ports CAT_RESET] +set_false_path -to [get_ports RX*_BANDSEL*] +set_false_path -to [get_ports TX_BANDSEL*] +set_false_path -to [get_ports TX_ENABLE*] +set_false_path -to [get_ports LED_*] +set_false_path -to [get_ports VCRX*] +set_false_path -to [get_ports VCTX*] +set_false_path -from [get_ports ONSWITCH_DB] diff --git a/fpga/usrp3/top/e31x/ip/.gitignore b/fpga/usrp3/top/e31x/ip/.gitignore new file mode 100644 index 000000000..a68476493 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/.gitignore @@ -0,0 +1,2 @@ +vivado* +managed_ip_project diff --git a/fpga/usrp3/top/e31x/ip/Makefile.inc b/fpga/usrp3/top/e31x/ip/Makefile.inc new file mode 100644 index 000000000..76bec9cdd --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/Makefile.inc @@ -0,0 +1,68 @@ +# +# Copyright 2014 Ettus Research +# + +#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +#include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +#include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +#include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +#include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +#include $(IP_DIR)/input_sample_fifo/Makefile.inc +#include $(IP_DIR)/misc_clock_gen/Makefile.inc +#include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc +#include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc +#include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc +#include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc +include $(IP_DIR)/e31x_ps_bd/Makefile.inc +include $(IP_DIR)/mig_7series_0/Makefile.inc + +BD_SRCS = \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_E31X_PS_BD_SRCS) + +IP_XCI_SRCS = \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_MIG_7SERIES_0_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +#$(IP_AXI4_BRAM_SRCS) \ +#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \ +#$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \ +#$(IP_MISC_CLOCK_GEN_SRCS) \ + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +## Currently unused +## $(IP_INPUT_SAMPLE_FIFO_SRCS) \ + +IP_SYNTH_OUTPUTS = \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_MIG_7SERIES_0_OUTS) \ +#$(IP_AXI4_BRAM_OUTS) \ +#$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \ +#$(IP_AXI_INTERCONNECT_OUTS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \ +#$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \ +#$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_E31X_PS_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc new file mode 100644 index 000000000..d70c96edd --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2018 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_E31X_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/e31x_ps_bd/, \ +e31x_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E31X_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \ +e31x_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E31X_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_E31X_PS_BD_SRCS = $(IP_BUILD_DIR)/e31x_ps_bd/e31x_ps_bd/e31x_ps_bd.bd + +BD_E31X_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/e31x_ps_bd/, \ +e31x_ps_bd.bd.out \ +e31x_ps_bd/e31x_ps_bd_ooc.xdc \ +) + +$(IP_E31X_PS_BD_SRCS) $(BD_E31X_PS_BD_OUTS) $(IP_E31X_PS_BDTCL_SRCS): $(IP_E31X_PS_ORIG_SRCS) $(IP_E31X_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,e31x_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E31X_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl new file mode 100644 index 000000000..b54ef7efc --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps.tcl @@ -0,0 +1,432 @@ +proc getPresetInfo {} { + return [dict create name {e31x_ps} description {e31x_ps} vlnv xilinx.com:ip:processing_system7:5.5 display_name {e31x_ps} ] +} + +proc validate_preset {IPINST} { return true } + + +proc apply_preset {IPINST} { + return [dict create \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {866.666687} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {144.444443} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {40000000} \ + CONFIG.PCW_CLK2_FREQ {166666672} \ + CONFIG.PCW_CLK3_FREQ {200000000} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {52} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1733.333} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {0} \ + CONFIG.PCW_USE_S_AXI_HP1 {1} \ + CONFIG.PCW_USE_S_AXI_HP2 {1} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {0} \ + CONFIG.PCW_EN_PJTAG {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI1 {1} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_CLK3_PORT {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_IRQ_F2P_INTR {1} \ + CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ + CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 3} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PJTAG_PJTAG_IO {} \ + CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C1_I2C1_IO {} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_DIRECTION {inout} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_DIRECTION {inout} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_DIRECTION {out} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_DIRECTION {out} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_DIRECTION {inout} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_DIRECTION {inout} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_DIRECTION {inout} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_DIRECTION {in} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_PULLUP {enabled} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_15_DIRECTION {out} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_16_PULLUP {disabled} \ + CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_16_DIRECTION {out} \ + CONFIG.PCW_MIO_16_SLEW {fast} \ + CONFIG.PCW_MIO_17_PULLUP {disabled} \ + CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_17_DIRECTION {out} \ + CONFIG.PCW_MIO_17_SLEW {fast} \ + CONFIG.PCW_MIO_18_PULLUP {disabled} \ + CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_18_DIRECTION {out} \ + CONFIG.PCW_MIO_18_SLEW {fast} \ + CONFIG.PCW_MIO_19_PULLUP {disabled} \ + CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_19_DIRECTION {out} \ + CONFIG.PCW_MIO_19_SLEW {fast} \ + CONFIG.PCW_MIO_20_PULLUP {disabled} \ + CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_20_DIRECTION {out} \ + CONFIG.PCW_MIO_20_SLEW {fast} \ + CONFIG.PCW_MIO_21_PULLUP {disabled} \ + CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_21_DIRECTION {out} \ + CONFIG.PCW_MIO_21_SLEW {fast} \ + CONFIG.PCW_MIO_22_PULLUP {disabled} \ + CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_22_DIRECTION {in} \ + CONFIG.PCW_MIO_22_SLEW {fast} \ + CONFIG.PCW_MIO_23_PULLUP {disabled} \ + CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_23_DIRECTION {in} \ + CONFIG.PCW_MIO_23_SLEW {fast} \ + CONFIG.PCW_MIO_24_PULLUP {disabled} \ + CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_24_DIRECTION {in} \ + CONFIG.PCW_MIO_24_SLEW {fast} \ + CONFIG.PCW_MIO_25_PULLUP {disabled} \ + CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_SLEW {fast} \ + CONFIG.PCW_MIO_26_PULLUP {disabled} \ + CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_26_DIRECTION {in} \ + CONFIG.PCW_MIO_26_SLEW {fast} \ + CONFIG.PCW_MIO_27_PULLUP {disabled} \ + CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_27_DIRECTION {in} \ + CONFIG.PCW_MIO_27_SLEW {fast} \ + CONFIG.PCW_MIO_28_PULLUP {enabled} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_PULLUP {enabled} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_29_DIRECTION {in} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_30_PULLUP {enabled} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_30_DIRECTION {out} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_PULLUP {enabled} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_31_DIRECTION {in} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_PULLUP {enabled} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_PULLUP {enabled} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_PULLUP {enabled} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_34_DIRECTION {inout} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_PULLUP {enabled} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_PULLUP {enabled} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_36_DIRECTION {in} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_PULLUP {enabled} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_PULLUP {enabled} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_PULLUP {enabled} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_40_PULLUP {enabled} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_PULLUP {enabled} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_PULLUP {enabled} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_PULLUP {enabled} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_PULLUP {enabled} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_PULLUP {enabled} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_46_PULLUP {enabled} \ + CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_46_DIRECTION {inout} \ + CONFIG.PCW_MIO_46_SLEW {slow} \ + CONFIG.PCW_MIO_47_PULLUP {enabled} \ + CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_47_DIRECTION {inout} \ + CONFIG.PCW_MIO_47_SLEW {slow} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_48_DIRECTION {out} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_49_DIRECTION {in} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_50_PULLUP {enabled} \ + CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_50_DIRECTION {inout} \ + CONFIG.PCW_MIO_50_SLEW {slow} \ + CONFIG.PCW_MIO_51_PULLUP {enabled} \ + CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_51_DIRECTION {inout} \ + CONFIG.PCW_MIO_51_SLEW {slow} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_52_DIRECTION {out} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#I2C 0#I2C 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#scl#sda#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ + ] +} + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl new file mode 100644 index 000000000..b6b3cb1e5 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/e31x_ps_bd.tcl @@ -0,0 +1,720 @@ +# CHANGE DESIGN NAME HERE +set design_name e31x_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set m_axi_pmu [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_pmu ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_pmu + set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_xbar + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ + CONFIG.PortWidth {16} \ + CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ + CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ + CONFIG.ASSOCIATED_RESET {bus_rstn} \ + CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_xbar:m_axi_pmu} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {5} \ + ] $axi_interconnect_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 5 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {40000000} \ + CONFIG.PCW_CLK2_FREQ {166666672} \ + CONFIG.PCW_CLK3_FREQ {200000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 11} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_CLK3_PORT {1} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {0} \ + CONFIG.PCW_EN_PJTAG {0} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI1 {1} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {3} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_IO {} \ + CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_I2C_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_RESET_SELECT {} \ + CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 9} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {0} \ + CONFIG.PCW_USE_S_AXI_HP1 {1} \ + CONFIG.PCW_USE_S_AXI_HP2 {1} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {16} \ + CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_pmu] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_0_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_0_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_0_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK] + connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + + # Create address segments + create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite1 + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite2 + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite3 + create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4 + create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite + create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_pmu/Reg] SEG_m_axi_pmu_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c new file mode 100644 index 000000000..1ad91d83a --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init.c @@ -0,0 +1,13335 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c new file mode 100644 index 000000000..89d3d6f04 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg1.c @@ -0,0 +1,1087 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_3_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + +unsigned long ps7_pll_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_2_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + +unsigned long ps7_pll_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500500U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00200300U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_1_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + + + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + } + + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c new file mode 100644 index 000000000..8a8a9f04b --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl-sg3.c @@ -0,0 +1,1087 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_3_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + +unsigned long ps7_pll_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_2_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_2_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + +unsigned long ps7_pll_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00034000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_clock_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), + +}; + +unsigned long ps7_mio_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000200U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001240U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000012E0U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000012E1U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), + +}; + +unsigned long ps7_post_config_1_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), + +}; + +unsigned long ps7_debug_1_0[] = { + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + EMIT_EXIT(), + +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + + + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + } + + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c new file mode 100644 index 000000000..dd9994e98 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/e31x_ps_bd/ps7_init_gpl.c @@ -0,0 +1,13326 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..45633b29c --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,575 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z020 + clg484 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..a07af7845 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,577 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z020 + clg484 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc b/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc new file mode 100644 index 000000000..0be73f919 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_MIG_7SERIES_0_SRCS = $(IP_BUILD_DIR)/mig_7series_0/mig_7series_0.xci + +IP_MIG_7SERIES_0_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ +mig_7series_0.xci.out \ +mig_7series_0/user_design/rtl/mig_7series_0.v \ +mig_7series_0/user_design/rtl/mig_7series_0_mig.v \ +) + +IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ +mig_7series_0/example_design/rtl/example_top.v \ +mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \ +mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \ +mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \ +mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \ +mig_7series_0/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \ +) + +IP_MIG_7SERIES_0_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/mig_7series_0/, \ +mig_7series_0/example_design/sim/ddr3_model.sv \ +mig_7series_0/example_design/sim/ddr3_model_parameters.vh \ +) + +$(IP_MIG_7SERIES_0_SRCS) $(IP_MIG_7SERIES_0_OUTS) : $(IP_DIR)/mig_7series_0/mig_7series_0.xci $(IP_DIR)/mig_7series_0/mig_*.prj + ln -fs mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/mig_7series_0/mig_a.prj # Hack: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,mig_7series_0,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/mig_7series_0/mig_a.prj diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci new file mode 100644 index 000000000..5b99fe23c --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_7series_0.xci @@ -0,0 +1,2648 @@ + + + xilinx.com + xci + unknown + 1.0 + + + mig_7series_0 + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 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INTERNAL + FALSE + 1 + Custom + mig_7series_0 + Custom + Custom + mig_a.prj + zynq + + + xc7z020 + clg484 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj new file mode 100644 index 000000000..f8c67329b --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-1.prj @@ -0,0 +1,140 @@ + + + + mig_7series_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7z020-clg484/-1 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 1 + 50 Ohms + 0 + + 7z/xc7z020i-clg484 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 2500 + 1.8V + 4:1 + 100 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Disable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 29 + 128 + 12 + 1 + + + + diff --git a/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj new file mode 100644 index 000000000..635ea1471 --- /dev/null +++ b/fpga/usrp3/top/e31x/ip/mig_7series_0/mig_xc7z020clg484-3.prj @@ -0,0 +1,140 @@ + + + + mig_7series_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7z020-clg484/-3 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 1 + 50 Ohms + 0 + + 7z/xc7z020i-clg484 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 2500 + 1.8V + 4:1 + 100 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Disable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 29 + 128 + 12 + 1 + + + + diff --git a/fpga/usrp3/top/e31x/ppsloop.v b/fpga/usrp3/top/e31x/ppsloop.v new file mode 100644 index 000000000..ea720a373 --- /dev/null +++ b/fpga/usrp3/top/e31x/ppsloop.v @@ -0,0 +1,415 @@ +// +// Copyright 2015 Ettus Research +// + +`timescale 1ns / 1ps + + +module ppsloop( + input reset, + input xoclk, // 40 MHz from VCTCXO + input ppsgps, + input ppsext, + input [1:0] refsel, + output reg lpps, + output reg is10meg, + output reg ispps, + output reg reflck, + output plllck,// status of things + output sclk, + output mosi, + output sync_n, + input [15:0] dac_dflt + ); + wire ppsref = (refsel==2'b00)?ppsgps: + (refsel==2'b11)?ppsext: + 1'b0; + // reference pps to discilpline the VCTX|CXO to, from GPS or EXT in + + wire clk_200M_o, clk; + BUFG x_clk_gen ( .I(clk_200M_o), .O(clk)); + wire clk_40M; + + wire n_pps = (refsel==2'b01) | (refsel==2'b10); + reg _npps, no_pps; + always @(posedge clk) { no_pps, _npps } <= { _npps, n_pps }; + + PLLE2_ADV #(.BANDWIDTH("OPTIMIZED"), .COMPENSATION("INTERNAL"), + .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(30), + .CLKOUT0_DIVIDE(6), + .CLKOUT1_DIVIDE(30), + .CLKIN1_PERIOD(25.0) + ) + clkgen ( + .PWRDWN(1'b0), .RST(1'b0), + .CLKIN1(xoclk), + .CLKOUT0(clk_200M_o), + .CLKOUT1(clk_40M), + .LOCKED(plllck) + ); + + // state machine to manage reference detection and xo adjustment steps + reg [2:0] sstate, nxt_sstate; + localparam REFDET=3'b000; + localparam CFADJ=3'b001; + localparam SLEDGEA=3'b010; + localparam SLEDGEB=3'b011; + localparam FINEADJ=3'b100; + + // state machine to manage lead-lag count + reg [1:0] llstate, nxt_llstate; + localparam READY=2'b00; + localparam COUNT=2'b01; + localparam DONE=2'b11; + localparam WAIT=2'b10; + + /* Counter generating a local pps for the xo derived clock domains. + nxt_lcnt is manipulated by a state machine (sstate) to allow + quick re-alignment of the local pps rising edge with that of + the reference. + */ + reg [27:0] lcnt, nxt_lcnt; + wire recycle = (28'd199_999_999==lcnt); // sets the period, 1 sec + + always @(posedge clk) begin + sstate <= nxt_sstate; + lcnt <= nxt_lcnt; + lpps <= lcnt > 28'd150_000_000; // ~25% duty cycle + end + + /* Reference signal detection: + * Count the time interval between rising edges on the reference + * signal. The interval counter "rcnt" is restarted at rising edges + * of ppsref. "ppsref" could be either a pps signal, or a 10 MHz clock. + * Register "rlst" captures the value of rcnt at each rising edge. + * From this count value, we know the reference frequency. + */ + reg [27:0] rcnt, rlst; + reg signed [28:0] rdiff; + wire signed [28:0] srlst = { 1'b0, rlst }; // sign extended version of rlst + wire [27:0] nxt_rcnt; + reg rcnt_ovfl; + reg [3:0] ple; // pipeline from reference rising edge det. + wire valid_ref = is10meg | ispps; + + + /* If the reference is at 10 MHz, derive a reference pps using a counter + * to feed the frequency control logic. To detect a 0.5 ppm deviation + * on a 10 MHz signal using counters requires the better part of a second + * anyway, so samples at a 1 Hz rate are appropriate. This allows much of + * the same logic to be used for pps or 10 Mhz references. + */ + reg [23:0] tcnt; + reg tpps; + wire [23:0] nxt_tcnt = (~is10meg | tcnt==24'd9999999) ? 24'b0 : tcnt+1'b1; + always @(posedge ppsref) begin + /* note this is clocked by the reference signal and is not useful when + * the reference is a pps. + */ + tcnt <= nxt_tcnt; + tpps <= (tcnt>24'd7499999); + end + + /* The reference needs to be synchronized into the local clock domain, + * and while the local 'pps' is generated synchronously within this + * domain, it gets passed through identical stages to maintain + * the time relationship between detected rising edges. + */ + reg [2:0] refsmp; + reg [2:0] tsmp; + reg [2:0] xosmp; + always @(posedge clk) begin + // apply same sync delay to all pps flavors + refsmp <= { refsmp[1:0], ppsref}; + tsmp <= { tsmp[1:0], tpps}; + xosmp <= { xosmp[1:0], lpps }; + end + + + wire rising_r = (refsmp[2:1]==2'b01); + wire rising_t = (tsmp[2:1]==2'b01); + wire rising_ref = is10meg ? rising_t : rising_r; + wire rising_xo = (xosmp[2:1]==2'b01); + wire lead = rising_xo & ~rising_ref; + wire lag = ~rising_xo & rising_ref; + wire trig = rising_xo ^ rising_ref; + wire dtrig = rising_xo & rising_ref; + wire untrig = rising_xo | rising_ref; + wire llrdy = (is10meg ? ~tsmp[2] : ~refsmp[2]) & ~xosmp[2]; + wire rhigh = is10meg ? tsmp[1] : refsmp[1]; + + + reg [5:0] pcnt; + reg pcnt_ovfl; + wire [5:0] nxt_pcnt = (rising_r | pcnt_ovfl) ? 6'b0 : pcnt+1'b1; + always @(posedge clk) begin + pcnt <= nxt_pcnt; + if (rcnt_ovfl) + is10meg <= 1'b0; + else if (pcnt == 6'b111111) begin + pcnt_ovfl <= 1'b1; + is10meg <= 1'b0; + end + else if (rising_r) begin + is10meg <= (pcnt > 6'd16) & (pcnt < 6'd24); + pcnt_ovfl <= 1'b0; + end + end + + reg rr; + assign nxt_rcnt = rr ? 28'b0 : rcnt+1'b1; + always @(posedge clk) begin + rr <= rising_ref; + ple[3:0] <= {ple[2:0],rising_ref & valid_ref}; + + rcnt <= nxt_rcnt; + + // set the overflow flag if no reference edge is detected and + // hold it asserted until an edge does arrive. This allows clearing of + // the other flags, even if there is no reference. + if (rcnt==28'b1111111111111111111111111111) + rcnt_ovfl <= 1'b1; + else if (rr) + rcnt_ovfl <= 1'b0; + + if (rr) begin + // a rising edge arrived, grab the count and compare to bounds + rlst <= rcnt; + end + if (rr | rcnt_ovfl) begin + ispps <= ~is10meg & ~rcnt_ovfl & (rcnt > 28'd199997000) & (rcnt < 200003000); + /* reference frequency detect limits: + * 10M sampled with 200M should be 20 cycles, 16-24 provides xtra margin + * to allow for tolerances and possibly sampling at jittery edges + * allow +- 15 ppm on a pps signal + */ + + end + end + + + reg signed [27:0] coarse; + reg [15:0] dacv = 16'd32767; // power-on default mid-scale + wire signed [16:0] sdacv = { 1'b0, dacv}; + /* to exit coarse adjustment, the frequency error shall be small for + * several cycles + */ + reg esmall; + reg [2:0] es; + + reg pr; + + + /* The xo can be on-frequency while the rising edges are still + * out-of-phase, so a phase detector is also required. The + * counter "llcnt" accumulates how many ticks local pps leads + * or lags the reference pps . The range of this counter + * need not be as large as "rcnt". The count increments + * or decrements based upon which signal has a rising edge first, + * and the count is halted when the other rising edge occurs. + * Both signals are required to transition back to the low state + * to re-arm the detection state machine. + */ + reg llcntena; + reg lead_lagn; + reg signed [11:0] llcnt, nxt_llcnt; + wire signed [11:0] incr = lead_lagn ? -12'sd1 : 12'sd1; // -1 lead, +1 lag + reg [3:0] llsmall; + reg llovfl; + + reg [2:0] refs1, refs0; + reg refchanged; + reg refinternal; + always @(posedge clk) begin + refs1 <= { refs1[1:0], refsel[1] }; + refs0 <= { refs0[1:0], refsel[0] }; + refchanged <= { refs1[2], refs0[2] } != { refs1[1], refs0[1] }; + refinternal <= refs1[2] ^ refs0[2]; // not gps or external + + // compute how far off the expected period we are + if (ple[1]) begin + rdiff <= srlst-29'd199999999; + end + + // compute an adjustment for the dac + if (ple[2]) begin + // if rdiff is (+), the xo is fast + // include a bit of gain for quick adjustment + // an approximate gain was initially determined by 'theory' using + // the xo tuning sensitivity, and was find-tuned 'by hand' + // by observing the loop behaviour (with rdiff instrumented and + // pps signals connected out to an oscilloscope). + coarse <= sdacv - (rdiff <<< 3); + end + + // determine when the period error is small + if (ple[2] | rcnt_ovfl) begin + es <= { es[1:0], (rdiff<29'sd8 && rdiff>-29'sd8) }; + esmall <= valid_ref & ~rcnt_ovfl & (es[2:0] == 3'b111); + end + else if (sstate==REFDET) begin + es <= 3'b0; + esmall <= 1'b0; + end + + // assign the dac value when doing coarse-adjustment + // in the fine-adjust phaase, the PI control filtering takes over + if (ple[3] & (sstate==CFADJ)) begin + dacv <= coarse[15:0]; + end + else if (sstate==REFDET) begin + dacv <= 16'd32767; // center the DAC + end + end + + + always @(*) begin + nxt_sstate=sstate; + pr = 1'b0; + nxt_lcnt = recycle ? 26'd0 : lcnt + 1'b1; + case (sstate) + REFDET: begin // determine reference type + pr = 1'b0; + if (valid_ref) nxt_sstate = CFADJ; + end + CFADJ: begin // coarse freqency adjustment + pr = 1'b1; + if (esmall) nxt_sstate = SLEDGEA; + end + SLEDGEA: begin // ensure local pps is low and wait for a ref edge + pr = 1'b1; // preload the integrator + if (rhigh) nxt_sstate = SLEDGEB; + end + SLEDGEB: begin // force local pps rising edge to match reference + nxt_lcnt = 26'd0; + pr = 1'b1; // preload the integrator + if(rhigh) begin + nxt_lcnt = 28'd149_999_998; // force rising edge in a couple cycles + nxt_sstate = FINEADJ; + end + end + FINEADJ: begin // wide-ish bandwidth PI control + if (~valid_ref | llovfl) nxt_sstate = REFDET; + end + default: begin + nxt_sstate = REFDET; + end + endcase + // overriding conditions: + if (refinternal | refchanged | rcnt_ovfl ) nxt_sstate = REFDET; + end + + reg llsena; + always @(posedge clk) begin + llstate <= nxt_llstate; + if (llcntena) llcnt <= nxt_llcnt; + if (llstate==READY) lead_lagn <= lead; + if (llsena) llsmall <= { (llsmall[2:0] == 3'b111), llsmall[1:0], + (llcnt < 12'sd3)&(llcnt > -12'sd3)}; + if (llcntena) llovfl <= (llcnt>12'sd1800) | (llcnt< -12'sd1800); + end + + reg ppsfltena; + always @(*) begin + // values to hold by default: + nxt_llstate = llstate; + llcntena=1'b0; + nxt_llcnt=llcnt; + ppsfltena = 1'b0; + llsena = 1'b0; + + case (llstate) + READY: begin + nxt_llcnt=12'b0; + if (trig | dtrig) begin + nxt_llstate = trig ? COUNT : DONE; + llcntena=1'b1; + // even if dtrig, set llcnt to 0 to feed the filter pipe + end + end + COUNT: begin + if (untrig) begin // the second edge arrived + nxt_llstate = DONE; + end + else begin + llcntena=1'b1; + nxt_llcnt=llcnt+incr; + end + end + DONE: begin + nxt_llstate = WAIT; + ppsfltena = 1'b1; + end + WAIT: begin + if (llrdy) begin + nxt_llstate = READY; + llsena = 1'b1; + end + end + endcase + if (sstate==REFDET) begin + nxt_llstate = READY; + llcntena=1'b0; + ppsfltena = 1'b0; + llsena = 1'b0; + end + end + + + reg[15:0] daco; + + reg [1:0] enchain=2'b00; + always @(posedge clk) enchain <= { enchain[1:0], ppsfltena & (enchain==2'b00) }; + + reg signed [23:0] integ; + reg signed [23:0] prop; + wire signed [23:0] nxt_integ = integ + (llcnt <<< 6); + wire signed [23:0] nxt_prop = (llcnt <<< 7); + wire signed [23:0] eff = integ + prop; + wire urng = eff[23], orng = eff[23:22]==2'b01; + reg erng; + /* The values for proportional and integral gain terms were originally + * estimated using a model that accounted for the xo tuning sensitivity. + * When implemented, the loop dynamics observed differed significantly + * from model results, probably as a result of the Xilinx PLL + * (which was not modelled) being present in the loop. The gain values + * were find-tuned 'by hand' by observing the loop behaviour (with llcnt + * instrumented) and pps signals connected out to an oscilloscope). + */ + + always @(posedge clk) begin + if (no_pps) begin + daco <= dac_dflt; + end + else if (pr) begin + integ <= { 2'b00, dacv, 6'b0 }; // precharge the accumulator + daco <= dacv; + end + else begin + if (enchain[0]) begin + integ <= nxt_integ; + prop <= nxt_prop; + end + if (enchain[1]) begin + daco <= eff[21:6]; + erng <= urng | orng; + end + end + end + + wire fadj= (sstate==FINEADJ); + always @(posedge clk) begin + reflck <= refinternal | fadj; + end + + ad5662_auto_spi dac + ( + .clk(clk), + .dat(daco), + .sclk(sclk), + .mosi(mosi), + .sync_n(sync_n) + ); + +endmodule diff --git a/fpga/usrp3/top/e31x/setupenv.sh b/fpga/usrp3/top/e31x/setupenv.sh new file mode 100644 index 000000000..940ccede2 --- /dev/null +++ b/fpga/usrp3/top/e31x/setupenv.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-E31x" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["E310_SG1"]="zynq/xc7z020/clg484/-1" +PRODUCT_ID_MAP["E310_SG3"]="zynq/xc7z020/clg484/-3" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh diff --git a/fpga/usrp3/top/e31x/sim/dram_test/Makefile b/fpga/usrp3/top/e31x/sim/dram_test/Makefile new file mode 100644 index 000000000..164f956f3 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/dram_test/Makefile @@ -0,0 +1,65 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID= xc7z020/clg484/-1 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/mig_7series_0/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_MIG_7SERIES_0_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_test_tb + +SIM_SRCS = \ +$(abspath dram_test_tb.sv) \ +$(IP_MIG_7SERIES_0_SIM_OUTS) \ +$(IP_MIG_7SERIES_TG_SRCS) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv b/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv new file mode 100644 index 000000000..e447c80a6 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv @@ -0,0 +1,121 @@ +// +// Copyright 2016 Ettus Research +// + + +`timescale 1ns/1ps +`define SIM_TIMEOUT_US 10000 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 3 + +`define SIM_RUNTIME_US 100 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" + +module dram_test_tb(); + `TEST_BENCH_INIT("dram_test_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(sys_clk, 10, 50) //100MHz sys_clk to generate DDR3 clocking + `DEFINE_CLK(ref_clk, 5, 50) //200MHz ref_clk to generate DDR3 clocking + `DEFINE_RESET(sys_rst, 0, 250000) //100ns for GSR to deassert + + // Initialize DUT + wire calib_complete; + + wire [15:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes. + wire [1:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes. + wire [1:0] ddr3_dqs_p; + wire [14:0] ddr3_addr; // Address + wire [2:0] ddr3_ba; // Bank Address + wire ddr3_ras_n; // Row Address Strobe. + wire ddr3_cas_n; // Column address select + wire ddr3_we_n; // Write Enable + wire ddr3_reset_n; // SDRAM reset pin. + wire [0:0] ddr3_ck_p; // Differential clock + wire [0:0] ddr3_ck_n; + wire [0:0] ddr3_cke; // Clock Enable + wire [0:0] ddr3_cs_n; // Chip Select + wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; + wire [0:0] ddr3_odt; // On-Die termination enable. + + ddr3_model #( + .DEBUG(1) //Disable verbose prints + ) sdram_i0 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (1'b0), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[1:0]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[15:0]), + .dqs (ddr3_dqs_p[1:0]), + .dqs_n (ddr3_dqs_n[1:0]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + + example_top inst_example_top + ( + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_cke (ddr3_cke), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + .sys_clk_i (sys_clk), + .clk_ref_i (ref_clk), + .tg_compare_error (tg_compare_error), + .init_calib_complete (calib_complete), + .sys_rst (sys_rst) + ); + + // + //Make sure we catch the error condition + // + reg tg_compare_error_reg; + always @ (posedge sys_clk) + if (sys_rst) + tg_compare_error_reg = 1'b0; + else + tg_compare_error_reg = tg_compare_error | tg_compare_error_reg; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + + initial begin : tb_main + + `TEST_CASE_START("Wait for reset"); + while (sys_rst) @(posedge sys_clk); + `TEST_CASE_DONE((~sys_rst)); + + repeat (200) @(posedge sys_clk); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge sys_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Run for a while, then check for error"); + repeat (2_000_000) @(posedge sys_clk); + `ASSERT_ERROR(tg_compare_error_reg == 1'b0, "Test generator reported error"); + `TEST_CASE_DONE(1'b1); + `TEST_BENCH_DONE; + + end + +endmodule diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile new file mode 100644 index 000000000..bf4922c21 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile @@ -0,0 +1,40 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID= xc7z020/clg484/-1 + +DESIGN_SRCS = $(abspath ../../e310_io.v) \ + $(abspath $(addprefix $(BASE_DIR)/../lib/control/, \ + synchronizer.v \ + synchronizer_impl.v)) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = e310_io_tb + +SIM_SRCS = \ +$(abspath e310_io_tb.sv) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv b/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv new file mode 100644 index 000000000..66e086644 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/e310_io_tb.sv @@ -0,0 +1,230 @@ +// +// Copyright 2015 Ettus Research +// +// Test bench for E310 I/O interface to AD9361. + +`timescale 1ns/1ps +`define SIM_TIMEOUT_US 20 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 6 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" + +module e310_io_tb(); + `TEST_BENCH_INIT("e310_io_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(rx_clk, 16.27, 50) // ~61.44 MHz clock from AD9361 + `DEFINE_RESET(areset, 0, 100) // 100ns reset + + reg mimo; + wire radio_clk, radio_rst; + wire [11:0] rx_i0, rx_i1, rx_q0, rx_q1; + wire rx_stb; + reg [11:0] tx_i0, tx_i1, tx_q0, tx_q1; + wire tx_stb; + reg rx_frame; + reg [11:0] rx_data; + wire tx_clk; + wire tx_frame; + wire [11:0] tx_data; + e310_io e310_io ( + .areset(areset), + .mimo(mimo), + .radio_clk(radio_clk), + .radio_rst(radio_rst), + .rx_i0(rx_i0), + .rx_q0(rx_q0), + .rx_i1(rx_i1), + .rx_q1(rx_q1), + .rx_stb(rx_stb), + .tx_i0(tx_i0), + .tx_q0(tx_q0), + .tx_i1(tx_i1), + .tx_q1(tx_q1), + .tx_stb(tx_stb), + .rx_clk(rx_clk), + .rx_frame(rx_frame), + .rx_data(rx_data), + .tx_clk(tx_clk), + .tx_frame(tx_frame), + .tx_data(tx_data)); + + /******************************************************** + ** Test Bench + ********************************************************/ + initial begin : tb_main + mimo <= 1'b0; + tx_i0 <= 'd0; + tx_q0 <= 'd0; + tx_i1 <= 'd0; + tx_q1 <= 'd0; + rx_data <= 'd0; + rx_frame <= 1'b0; + `TEST_CASE_START("Wait for reset"); + while (areset) @(posedge radio_clk); + `TEST_CASE_DONE((~areset)); + + repeat (10) @(posedge radio_clk); + + `TEST_CASE_START("Test RX channel 0,1"); + mimo <= 1'b0; + rx_data <= 'd0; + repeat (10) @(posedge radio_clk); + fork + begin + for (int i = 1; i < 64; i = i + 2) begin + @(posedge radio_clk); + rx_frame <= 1'b1; + rx_data <= i; + @(negedge radio_clk); + rx_frame <= 1'b0; + rx_data <= i+1; + end + end + begin + while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk); + for (int i = 1; i < 64; i = i + 2) begin + // RX should be replicated across both ports + `ASSERT_ERROR(rx_i0 == i, "RX0 I incorrect!"); + `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!"); + `ASSERT_ERROR(rx_i1 == i, "RX1 I incorrect!"); + `ASSERT_ERROR(rx_q1 == i+1, "RX1 Q incorrect!"); + @(posedge radio_clk); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Test RX channels 0 & 1 (MIMO mode)"); + mimo <= 1'b1; + rx_frame <= 1'b0; + rx_data <= 'd0; + repeat (10) @(posedge radio_clk); + fork + begin + for (int i = 1; i < 64; i = i + 2) begin + @(posedge radio_clk); + rx_frame <= ~rx_frame; + rx_data <= i; + @(negedge radio_clk); + rx_data <= i+1; + end + end + begin + while ({rx_i0, rx_q0} == 24'd0) @(posedge radio_clk); + for (int i = 1; i < 32; i = i + 4) begin + // RX should be replicated across both ports + `ASSERT_ERROR(rx_i0 == i, "RX0 I incorrect!"); + `ASSERT_ERROR(rx_q0 == i+1, "RX0 Q incorrect!"); + @(posedge radio_clk); + `ASSERT_ERROR(rx_i1 == i+2, "RX1 I incorrect!"); + `ASSERT_ERROR(rx_q1 == i+3, "RX1 Q incorrect!"); + @(posedge radio_clk); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Test TX channel 0"); + mimo <= 1'b0; + tx_i0 <= 'd0; + tx_q0 <= 'd0; + tx_i1 <= 'd0; + tx_q1 <= 'd0; + repeat (10) @(posedge radio_clk); + // TX0 + fork + begin + for (int i = 1; i < 64; i = i + 2) begin + tx_i0 <= i; + tx_q0 <= i+1; + @(posedge radio_clk); + end + end + begin + while (tx_data == 12'd0) @(posedge tx_clk); + for (int i = 1; i < 64; i = i + 2) begin + // RX should be replicated across both ports + `ASSERT_ERROR(tx_data == i, "TX0 I data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect"); + @(negedge tx_clk); + `ASSERT_ERROR(tx_data == i+1, "TX0 Q data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect"); + @(posedge tx_clk); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Test TX channel 1"); + mimo <= 1'b0; + tx_i0 <= 'd0; + tx_q0 <= 'd0; + tx_i1 <= 'd0; + tx_q1 <= 'd0; + repeat (10) @(posedge radio_clk); + fork + begin + for (int i = 1; i < 64; i = i + 2) begin + tx_i1 <= i; + tx_q1 <= i+1; + @(posedge radio_clk); + end + end + begin + while (tx_data == 12'd0) @(posedge tx_clk); + for (int i = 1; i < 64; i = i + 2) begin + `ASSERT_ERROR(tx_data == i, "TX1 I data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect"); + @(negedge tx_clk); + `ASSERT_ERROR(tx_data == i+1, "TX1 Q data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect"); + @(posedge tx_clk); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Test TX channel 0 & 1 (MIMO)"); + mimo <= 1'b1; + tx_i0 <= 'd0; + tx_q0 <= 'd0; + tx_i1 <= 'd0; + tx_q1 <= 'd0; + repeat (10) @(posedge radio_clk); + fork + begin + for (int i = 1; i < 32; i = i + 4) begin + tx_i0 <= i; + tx_q0 <= i+1; + tx_i1 <= i+2; + tx_q1 <= i+3; + @(posedge radio_clk); + while (tx_stb) @(posedge radio_clk); + end + end + begin + while (tx_data == 12'd0) @(posedge tx_clk); + for (int i = 1; i < 32; i = i + 4) begin + `ASSERT_ERROR(tx_data == i, "TX0 I data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect"); + @(negedge tx_clk); + `ASSERT_ERROR(tx_data == i+1, "TX0 Q data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b1, "TX frame incorrect"); + @(posedge tx_clk); + `ASSERT_ERROR(tx_data == i+2, "TX1 I data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect"); + @(negedge tx_clk); + `ASSERT_ERROR(tx_data == i+3, "TX1 Q data incorrect!"); + `ASSERT_ERROR(tx_frame == 1'b0, "TX frame incorrect"); + @(posedge tx_clk); + end + end + join + `TEST_CASE_DONE(1); + `TEST_BENCH_DONE; + end + +endmodule diff --git a/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.build b/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.build new file mode 100755 index 000000000..759549e4b --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf catcap_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../../top/e300/coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir ../../../top/e300/ \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + catcap_tb.v + + +fuse -o catcap_tb catcap_tb diff --git a/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.v b/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.v new file mode 100644 index 000000000..4e05e6ed4 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e3x0/catcap_ddr_cmos/catcap_tb.v @@ -0,0 +1,114 @@ +// +// Copyright 2014 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +`timescale 1ns/1ps + +module catcap_tb(); + + wire GSR, GTS; + glbl glbl( ); + + reg clk = 0; + reg ddrclk = 0; + reg reset = 1; + + always #100 clk = ~clk; + always @(negedge clk) ddrclk <= ~ddrclk; + + initial $dumpfile("catcap_tb.vcd"); + initial $dumpvars(0,catcap_tb); + + wire [11:0] i0 = {4'hA,count}; + wire [11:0] q0 = {4'hB,count}; + wire [11:0] i1 = {4'hC,count}; + wire [11:0] q1 = {4'hD,count}; + + reg mimo; + reg [11:0] pins; + reg frame; + reg [7:0] count; + + initial + begin + #1000 reset = 0; + MIMO_BURST(4); + MIMO_BURST(5); + BURST(4); + BURST(5); + #2000; + $finish; + end + + task BURST; + input [7:0] len; + begin + frame <= 0; + @(posedge clk); + @(posedge clk); + mimo <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge ddrclk); + count <= 0; + repeat(len) + begin + @(posedge clk); + pins <= i0; + frame <= 1; + @(posedge clk); + pins <= q0; + frame <= 0; + count <= count + 1; + end + end + endtask // BURST + + task MIMO_BURST; + input [7:0] len; + begin + frame <= 0; + @(posedge clk); + @(posedge clk); + mimo <= 1; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge ddrclk); + count <= 0; + repeat(len) + begin + @(posedge clk); + pins <= i0; + frame <= 1; + @(posedge clk); + pins <= q0; + @(posedge clk); + pins <= i1; + frame <= 0; + @(posedge clk); + pins <= q1; + count <= count + 1; + end + @(posedge clk); + @(posedge clk); + end + endtask // MIMO_BURST + + wire rx_clk, rx_strobe; + wire [11:0] i0o,i1o,q0o,q1o; + + catcap_ddr_cmos catcap + (.data_clk(ddrclk), + .reset(reset), + .mimo(mimo), + .rx_frame(frame), + .rx_d(pins), + .rx_clk(rx_clk), + .rx_strobe(rx_strobe), + .i0(i0o),.q0(q0o), + .i1(i1o),.q1(q1o)); + +endmodule // hb_chain_tb diff --git a/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.build b/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.build new file mode 100755 index 000000000..6512340f1 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.build @@ -0,0 +1,21 @@ + +#!/bin/sh + +rm -rf isim* +rm -rf catgen_tb +rm -rf fuse* +\ +# --sourcelibdir ../../models \ + +vlogcomp \ + --sourcelibext .v \ + --sourcelibdir ../../../top/e300/coregen \ + --sourcelibdir ../../control_lib \ + --sourcelibdir ../../../top/e300 \ + --sourcelibdir $XILINX/verilog/src \ + --sourcelibdir $XILINX/verilog/src/unisims \ + --work work \ + catgen_tb.v + + +fuse -o catgen_tb catgen_tb diff --git a/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.v b/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.v new file mode 100644 index 000000000..070364b41 --- /dev/null +++ b/fpga/usrp3/top/e31x/sim/e3x0/catgen_ddr_cmos/catgen_tb.v @@ -0,0 +1,102 @@ +// +// Copyright 2014 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +`timescale 1ns/1ps + +module catgen_tb(); + + wire GSR, GTS; + glbl glbl( ); + + reg clk = 0; + reg reset = 1; + wire ddrclk; + + always #100 clk = ~clk; + + initial $dumpfile("catgen_tb.vcd"); + initial $dumpvars(0,catgen_tb); + + wire [11:0] pins; + wire frame; + + reg mimo; + reg [7:0] count; + reg tx_strobe; + + wire [11:0] i0 = {4'hA,count}; + wire [11:0] q0 = {4'hB,count}; + wire [11:0] i1 = {4'hC,count}; + wire [11:0] q1 = {4'hD,count}; + + initial + begin + #1000 reset = 0; + BURST(4); + BURST(5); + MIMO_BURST(4); + MIMO_BURST(5); + #2000; + $finish; + end + + task BURST; + input [7:0] len; + + begin + tx_strobe <= 0; + mimo <= 0; + count <= 0; + @(posedge clk); + @(posedge clk); + repeat(len) + begin + tx_strobe <= 1; + @(posedge clk); + count <= count + 1; + end + tx_strobe <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + endtask // BURST + + task MIMO_BURST; + input [7:0] len; + + begin + tx_strobe <= 0; + mimo <= 1; + count <= 0; + @(posedge clk); + @(posedge clk); + repeat(len) + begin + tx_strobe <= 1; + @(posedge clk); + tx_strobe <= 0; + @(posedge clk); + count <= count + 1; + end + tx_strobe <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + end + endtask // BURST + + catgen_ddr_cmos catgen + (.data_clk(ddrclk), + .reset(reset), + .mimo(mimo), + .tx_frame(frame), + .tx_d(pins), + .tx_clk(clk), + .tx_strobe(tx_strobe), + .i0(i0),.q0(q0), + .i1(i1),.q1(q1)); + +endmodule // hb_chain_tb diff --git a/fpga/usrp3/top/e31x/spi_slave.v b/fpga/usrp3/top/e31x/spi_slave.v new file mode 100644 index 000000000..d8d48115d --- /dev/null +++ b/fpga/usrp3/top/e31x/spi_slave.v @@ -0,0 +1,107 @@ +// +// Copyright 2015 Ettus Research LLC +// + +`ifndef LOG2 +`define LOG2(N) (\ + N < 2 ? 0 : \ + N < 4 ? 1 : \ + N < 8 ? 2 : \ + N < 16 ? 3 : \ + N < 32 ? 4 : \ + N < 64 ? 5 : \ + N < 128 ? 6 : \ + N < 256 ? 7 : \ + N < 512 ? 8 : \ + N < 1024 ? 9 : \ + 10) +`endif + +module spi_slave +#( + parameter DEPTH = 64 +) +( + // sys connect + input clk, + input rst, + + // spi slave port + input ss, + input mosi, + output miso, + input sck, + + // parallel data io port + output parallel_stb, + input [DEPTH-1:0] parallel_din, + output [DEPTH-1:0] parallel_dout +); + reg mosi_d, mosi_q; + reg ss_d, ss_q; + reg sck_d, sck_q; + reg sck_old_d, sck_old_q; + reg miso_d, miso_q; + + reg [DEPTH-1:0] data_d, data_q; + reg parallel_stb_d, parallel_stb_q; + reg [`LOG2(DEPTH)-1:0] bit_ct_d, bit_ct_q; + reg [DEPTH-1:0] parallel_dout_d, parallel_dout_q; + + assign miso = miso_q; + assign parallel_stb = parallel_stb_q; + assign parallel_dout = parallel_dout_q; + + always @(*) begin + ss_d = ss; + mosi_d = mosi; + miso_d = miso_q; + sck_d = sck; + sck_old_d = sck_q; + data_d = data_q; + parallel_stb_d = 1'b0; + bit_ct_d = bit_ct_q; + parallel_dout_d = parallel_dout_q; + + if (ss_q) begin + bit_ct_d = 'h0; + data_d = parallel_din; + miso_d = data_q[DEPTH-1]; + end + else begin + if (!sck_old_q && sck_q) begin // rising edge + data_d = {data_q[DEPTH-1-1:0], mosi_q}; + bit_ct_d = bit_ct_q + 1'b1; + if (bit_ct_q == (DEPTH - 1)) begin + parallel_dout_d = {data_q[DEPTH-1-1:0], mosi_q}; + parallel_stb_d = 1'b1; + data_d = parallel_din; + end + end + else if (sck_old_q && !sck_q) begin // falling edge + miso_d = data_q[DEPTH-1]; + end + end + end + + always @(posedge clk) begin + if (rst) begin + parallel_stb_q <= 1'b0; + bit_ct_q <= 'h0; + parallel_dout_q <= 'h0; + miso_q <= 1'b1; + end else begin + parallel_stb_q <= parallel_stb_d; + bit_ct_q <= bit_ct_d; + parallel_dout_q <= parallel_dout_d; + miso_q <= miso_d; + end + + sck_q <= sck_d; + mosi_q <= mosi_d; + ss_q <= ss_d; + data_q <= data_d; + sck_old_q <= sck_old_d; + end + +endmodule diff --git a/fpga/usrp3/top/e320/.gitignore b/fpga/usrp3/top/e320/.gitignore new file mode 100644 index 000000000..1b0a8a728 --- /dev/null +++ b/fpga/usrp3/top/e320/.gitignore @@ -0,0 +1,8 @@ +build +build-* +isim* +fuse* +tmp* +*.log +*.jou +*impact* diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile new file mode 100644 index 000000000..b15d4317c --- /dev/null +++ b/fpga/usrp3/top/e320/Makefile @@ -0,0 +1,100 @@ +# +# Copyright 2018-2019 Ettus Research, a National Instruments Brand +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP E3XX FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga_.bit: Configuration bitstream with header +## build/usrp__fpga_.dts: Device tree source file +## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) + +1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) +XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) +AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= e320 + +DEFAULT_IMAGE_CORE_FILE_E320=e320_rfnoc_image_core.v +DEFAULT_EDGE_FILE_E320=$(abspath e320_static_router.hex) + +# vivado_build($1=Device, $2=Definitions) +vivado_build = make -f Makefile.e320.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream file..."; \ + cp build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \ + echo "Exporting build report..."; \ + cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \ + echo "Build DONE ... $(1)_$(2)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- + +all: E320_1G E320_XG ##(Default target) + +##E320_1G: 1GigE on SFP+ Port. +E320_1G: build/usrp_e320_fpga_1G.dts + $(call vivado_build,E320,$(1G_DEFS) E320=1) + $(call post_build,E320,1G) + +##E320_XG: 10GigE on SFP+ Port. +E320_XG: build/usrp_e320_fpga_XG.dts + $(call vivado_build,E320,$(XG_DEFS) E320=1) + $(call post_build,E320,XG) + +##E320_AA: Aurora on SFP+ Port. +E320_AA: build/usrp_e320_fpga_AA.dts + $(call vivado_build,E320,$(AA_DEFS) E320=1) + $(call post_build,E320,AA) + + +build/%.dts: dts/%.dts dts/*.dtsi + -mkdir -p build + ${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $< + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-E3*_* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-E3*_* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc new file mode 100644 index 000000000..a20e6c0ff --- /dev/null +++ b/fpga/usrp3/top/e320/Makefile.e320.inc @@ -0,0 +1,141 @@ +# +# Copyright 2018-2019 Ettus Research, a National Instruments Brand +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include ../n3xx/coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/simple_gemac/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/xge/Makefile.srcs +include $(LIB_DIR)/xge_interface/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/io_cap_gen/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and +# DUC, and of course the radio. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +# If out-of-tree modules want to be compiled into this image, then they need to +# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. +# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual +# source files. +include $(RFNOC_OOT_MAKEFILE_SRCS) + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## +TOP_SRCS = \ +e320.v \ +e320_core.v \ +e320_clocking.v \ +n3xx_sfp_wrapper.v \ +n3xx_mgt_io_core.v \ +$(IMAGE_CORE) + +MB_XDC = \ +mb_pins.xdc \ +mb_timing.xdc + +ifdef BUILD_10G +MB_XDC += $(abspath e320_10ge.xdc) +endif + +ifdef BUILD_1G +MB_XDC += $(abspath e320_1ge.xdc) +endif + +ifdef BUILD_AURORA +MB_XDC += $(abspath e320_aurora.xdc) +endif + +ifdef SFP_10GBE +MB_XDC += $(abspath e320_10ge_port0.xdc) +endif + +ifndef NO_DRAM_FIFOS +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath e320_dram.xdc) +else +DRAM_SRCS = +endif + +# The XDC files must be read in a specific order, motherboard first and then daughterboard. +# Outside of that, all the other sources can be read in any order desired. +DESIGN_SRCS = \ +$(abspath $(TOP_SRCS)) \ +$(CONTROL_LIB_SRCS) \ +$(IP_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(PACKET_PROC_SRCS) \ +$(AXI_SRCS) \ +$(FIFO_SRCS) \ +$(ONE_GIGE_PHY_SRCS) \ +$(SIMPLE_GEMAC_SRCS) \ +$(AURORA_PHY_SRCS) \ +$(BD_SRCS) \ +$(TIMING_SRCS) \ +$(CAT_CAP_GEN_SRCS) \ +$(DRAM_SRCS) \ +$(COREGEN_DSP_SRCS) \ +$(DSP_SRCS) \ +$(LIB_IP_XCI_SRCS) \ +$(LIB_HLS_IP_SRCS) \ +$(EXTRAM_SRCS) \ +$(CAP_GEN_GENERIC_SRCS) \ +$(RFNOC_SRCS) \ +$(RFNOC_OOT_SRCS) \ +$(RFNOC_FRAMEWORK_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ +$(RFNOC_BLOCK_RADIO_SRCS) \ +$(abspath $(MB_XDC)) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/e320/build_e320.tcl b/fpga/usrp3/top/e320/build_e320.tcl new file mode 100644 index 000000000..757195865 --- /dev/null +++ b/fpga/usrp3/top/e320/build_e320.tcl @@ -0,0 +1,39 @@ +# +# Copyright 2016 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set e3xx_strategy [dict create] +dict set e3xx_strategy "opt_design.is_enabled" 1 +dict set e3xx_strategy "opt_design.directive" "Default" +dict set e3xx_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set e3xx_strategy "place_design.directive" "Default" +dict set e3xx_strategy "post_place_power_opt_design.is_enabled" 0 +dict set e3xx_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set e3xx_strategy "post_place_phys_opt_design.directive" "Default" +dict set e3xx_strategy "route_design.directive" "Default" +dict set e3xx_strategy "route_design.more_options" "-tns_cleanup" +dict set e3xx_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set e3xx_strategy "post_route_phys_opt_design.directive" "Default" +vivado_strategies::implement_design $e3xx_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *] +set byte_swap_bin 1 +vivado_utils::write_implementation_outputs $byte_swap_bin + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/e320/dev_config.json b/fpga/usrp3/top/e320/dev_config.json new file mode 100644 index 000000000..eb6ce9dc0 --- /dev/null +++ b/fpga/usrp3/top/e320/dev_config.json @@ -0,0 +1,3 @@ +{ + "warning": { "ignore": ["."]} +} diff --git a/fpga/usrp3/top/e320/dts/dma-common.dtsi b/fpga/usrp3/top/e320/dts/dma-common.dtsi new file mode 100644 index 000000000..0f3dde41d --- /dev/null +++ b/fpga/usrp3/top/e320/dts/dma-common.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma5: dma@43CF0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CF0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma5: dma@43C50000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C50000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + + usrp_rx_dma5: usrp-rx-dma@43c50000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + + regmap = <&dma_conf0>; + offset = <0x14>; + }; + + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + usrp_tx_dma5: usrp-tx-dma@43cf0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-common.dtsi b/fpga/usrp3/top/e320/dts/e320-common.dtsi new file mode 100644 index 000000000..470596f33 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-common.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>; + + spidev1: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/e320/dts/e320-fpga.dtsi b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi new file mode 100644 index 000000000..3f245d0a2 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/e320-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + firmware-name = "e320.bin"; +}; diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts new file mode 100644 index 000000000..c1d76ae4f --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_1G.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; // FIXME: Addresses + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts new file mode 100644 index 000000000..04f67d002 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_AA.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; //FIXME + reg-names = "misc-auro-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts new file mode 100644 index 000000000..3c64cfbf7 --- /dev/null +++ b/fpga/usrp3/top/e320/dts/usrp_e320_fpga_XG.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "e320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; //FIXME + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; //FIXME + reg-names = "misc-enet-regs"; + status = "okay"; + }; +}; + +#include "e320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v new file mode 100644 index 000000000..8d766e325 --- /dev/null +++ b/fpga/usrp3/top/e320/e320.v @@ -0,0 +1,1739 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e320 +// Description: +// E320 Top Level +// +///////////////////////////////////////////////////////////////////// + +`default_nettype none +module e320 ( + + // 5V Power Enable + output wire ENA_PAPWR, + + // GPIO + output wire EN_GPIO_2V5, + output wire EN_GPIO_3V3, + output wire EN_GPIO_VAR_SUPPLY, + inout wire [7:0] GPIO_PREBUFF, + inout wire [7:0] GPIO_DIR, + output wire GPIO_OE_N, + + // GPS + output wire CLK_GPS_PWR_EN, + output wire GPS_INITSURV_N, + output wire GPS_RST_N, + input wire GPS_ALARM, + input wire GPS_LOCK, + input wire GPS_PHASELOCK, + input wire GPS_SURVEY, + input wire GPS_WARMUP, + + // SFP + input wire SFP1_RX_P, + input wire SFP1_RX_N, + output wire SFP1_TX_P, + output wire SFP1_TX_N, + input wire SFP1_RXLOS, + input wire SFP1_TXFAULT, + input wire SFP1_MOD_ABS, // Unused + output wire SFP1_RS0, + output wire SFP1_RS1, + output wire SFP1_TXDISABLE, + + // MGT Clocks + + output wire CLK_PLL_SCLK, + output wire CLK_PLL_SDATA, + output wire CLK_PLL_SLE, + + input wire CLK_MGT_125M_P, + input wire CLK_MGT_125M_N, + input wire CLK_MGT_156_25M_P, + input wire CLK_MGT_156_25M_N, + + // PS Connections + inout wire [53:0] PS_MIO, + inout wire PS_CLK, + inout wire PS_SRST_B, + inout wire PS_POR_B, + inout wire DDR_MODCLK_P, + inout wire DDR_MODCLK_N, + inout wire PS_DDR3_CKE, + inout wire PS_DDR3_RESET_N, + inout wire [31:0] PS_DDR3_DQ, + inout wire [14:0] PS_DDR3_ADDR, + inout wire [3:0] PS_DDR3_DM, + inout wire [2:0] PS_DDR3_BA, + inout wire [3:0] PS_DDR3_DQS_P, + inout wire [3:0] PS_DDR3_DQS_N, + inout wire PS_DDR3_ODT, + inout wire PS_DDR3_VRN, + inout wire PS_DDR3_VRP, + inout wire PS_DDR3_WE_N, + inout wire PS_DDR3_CS_N, + inout wire PS_DDR3_CAS_N, + inout wire PS_DDR3_RAS_N, + + // PL DRAM Interface + input wire sys_clk_p, + input wire sys_clk_n, + // + inout wire [31:0] ddr3_dq, + inout wire [3:0] ddr3_dqs_n, + inout wire [3:0] ddr3_dqs_p, + output wire [3:0] ddr3_dm, + // + output wire [2:0] ddr3_ba, + output wire [15:0] ddr3_addr, + output wire ddr3_ras_n, + output wire ddr3_cas_n, + output wire ddr3_we_n, + // + output wire [0:0] ddr3_cs_n, + output wire [0:0] ddr3_cke, + output wire [0:0] ddr3_odt, + // + output wire [0:0] ddr3_ck_p, + output wire [0:0] ddr3_ck_n, + // + output wire ddr3_reset_n, + + // LEDs + output wire LED_LINK1, + output wire LED_ACT1, + + // PPS, REFCLK + input wire CLK_SYNC_INT, // PPS from GPS + input wire CLK_SYNC_INT_RAW, // PPS_RAW from GPS (Unused) + input wire CLK_SYNC_EXT, // PPS from external connector + input wire CLK_REF_RAW, // FPGA reference clock (GPS or external) + output wire CLK_REF_SEL, // Select for GPS or external reference clock + input wire CLK_MUX_OUT, // RF clock locked status + + // RF LVDS Data Interface + // + // Receive + input wire RX_CLK_P, + input wire RX_CLK_N, + input wire RX_FRAME_P, + input wire RX_FRAME_N, + input wire [5:0] RX_DATA_P, + input wire [5:0] RX_DATA_N, + // + // TraNSMIT + output wire TX_CLK_P, + output wire TX_CLK_N, + output wire TX_FRAME_P, + output wire TX_FRAME_N, + output wire [5:0] TX_DATA_P, + output wire [5:0] TX_DATA_N, + + // Switches + output wire [2:0] FE1_SEL, + output wire [2:0] FE2_SEL, + output wire [1:0] RX1_SEL, + output wire [1:0] RX2_SEL, + output wire [5:0] RX1_BSEL, + output wire [5:0] RX2_BSEL, + output wire [5:0] TX1_BSEL, + output wire [5:0] TX2_BSEL, + + // SPI + input wire XCVR_SPI_MISO, + output wire XCVR_SPI_MOSI, + output wire XCVR_SPI_CLK, + output wire XCVR_SPI_CS_N, + + // AD9361 + output wire XCVR_ENABLE, + output wire XCVR_SYNC, + output wire XCVR_TXNRX, + output wire XCVR_ENA_AGC, + output wire XCVR_RESET_N, + input wire [7:0] XCVR_CTRL_OUT, + + // Amplifiers + output wire TX_HFAMP1_ENA, + output wire TX_HFAMP2_ENA, + output wire TX_LFAMP1_ENA, + output wire TX_LFAMP2_ENA, + + // LEDs + output wire RX1_GRN_ENA, + output wire RX2_GRN_ENA, + output wire TX1_RED_ENA, + output wire TX2_RED_ENA, + output wire TXRX1_GRN_ENA, + output wire TXRX2_GRN_ENA + +); + + `ifdef SFP_1GBE + parameter PROTOCOL = "1GbE"; + parameter MDIO_EN = 1'b1; + parameter MDIO_PHYADDR = 5'd4; + `elsif SFP_10GBE + parameter PROTOCOL = "10GbE"; + parameter MDIO_EN = 1'b1; + parameter MDIO_PHYADDR = 5'd4; + `elsif SFP_AURORA + parameter PROTOCOL = "Aurora"; + parameter MDIO_EN = 1'b0; + parameter MDIO_PHYADDR = 5'd0; + `else + parameter PROTOCOL = "Disabled"; + parameter MDIO_EN = 1'b0; + parameter MDIO_PHYADDR = 5'd0; + `endif + + // Constants + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam REG_DWIDTH = 32; + localparam DB_GPIO_WIDTH = 32; + localparam FP_GPIO_OFFSET = 32; // Offset within ps_gpio_* + localparam FP_GPIO_WIDTH = 8; + + //If bus_clk freq ever changes, update this parameter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + localparam SFP_PORTNUM = 8'b0; // Only one SFP port + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + // Clocks + wire xgige_clk156; + wire bus_clk; + wire radio_clk; + wire reg_clk; + wire clk40; + wire ddr3_dma_clk; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + + // Resets + wire global_rst; + wire bus_rst; + wire radio_rst; + wire reg_rstn; + wire clk40_rst; + wire clk40_rstn; + wire FCLK_RESET0_N; + + // Regport for SFP + wire m_axi_net_arvalid; + wire m_axi_net_awvalid; + wire m_axi_net_bready; + wire m_axi_net_rready; + wire m_axi_net_wvalid; + wire [11:0] m_axi_net_arid; + wire [11:0] m_axi_net_awid; + wire [11:0] m_axi_net_wid; + wire [31:0] m_axi_net_araddr; + wire [31:0] m_axi_net_awaddr; + wire [31:0] m_axi_net_wdata; + wire [3:0] m_axi_net_wstrb; + wire m_axi_net_arready; + wire m_axi_net_awready; + wire m_axi_net_bvalid; + wire m_axi_net_rlast; + wire m_axi_net_rvalid; + wire m_axi_net_wready; + wire [1:0] m_axi_net_bresp; + wire [1:0] m_axi_net_rresp; + wire [31:0] m_axi_net_rdata; + + // Crossbar + wire m_axi_xbar_arvalid; + wire m_axi_xbar_awvalid; + wire m_axi_xbar_bready; + wire m_axi_xbar_rready; + wire m_axi_xbar_wvalid; + wire [11:0] m_axi_xbar_arid; + wire [11:0] m_axi_xbar_awid; + wire [11:0] m_axi_xbar_wid; + wire [31:0] m_axi_xbar_araddr; + wire [31:0] m_axi_xbar_awaddr; + wire [31:0] m_axi_xbar_wdata; + wire [3:0] m_axi_xbar_wstrb; + wire m_axi_xbar_arready; + wire m_axi_xbar_awready; + wire m_axi_xbar_bvalid; + wire m_axi_xbar_rlast; + wire m_axi_xbar_rvalid; + wire m_axi_xbar_wready; + wire [1:0] m_axi_xbar_bresp; + wire [1:0] m_axi_xbar_rresp; + wire [31:0] m_axi_xbar_rdata; + + // ETH DMA + wire m_axi_eth_dma_arvalid; + wire m_axi_eth_dma_awvalid; + wire m_axi_eth_dma_bready; + wire m_axi_eth_dma_rready; + wire m_axi_eth_dma_wvalid; + wire [11:0] m_axi_eth_dma_arid; + wire [11:0] m_axi_eth_dma_awid; + wire [11:0] m_axi_eth_dma_wid; + wire [31:0] m_axi_eth_dma_araddr; + wire [31:0] m_axi_eth_dma_awaddr; + wire [31:0] m_axi_eth_dma_wdata; + wire [3:0] m_axi_eth_dma_wstrb; + wire m_axi_eth_dma_arready; + wire m_axi_eth_dma_awready; + wire m_axi_eth_dma_bvalid; + wire m_axi_eth_dma_rlast; + wire m_axi_eth_dma_rvalid; + wire m_axi_eth_dma_wready; + wire [1:0] m_axi_eth_dma_bresp; + wire [1:0] m_axi_eth_dma_rresp; + wire [31:0] m_axi_eth_dma_rdata; + + // Processing System + wire [15:0] IRQ_F2P; + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // HP0 -- High Performance port 0 + wire [5:0] s_axi_hp0_awid; + wire [31:0] s_axi_hp0_awaddr; + wire [2:0] s_axi_hp0_awprot; + wire s_axi_hp0_awvalid; + wire s_axi_hp0_awready; + wire [63:0] s_axi_hp0_wdata; + wire [7:0] s_axi_hp0_wstrb; + wire s_axi_hp0_wvalid; + wire s_axi_hp0_wready; + wire [1:0] s_axi_hp0_bresp; + wire s_axi_hp0_bvalid; + wire s_axi_hp0_bready; + wire [5:0] s_axi_hp0_arid; + wire [31:0] s_axi_hp0_araddr; + wire [2:0] s_axi_hp0_arprot; + wire s_axi_hp0_arvalid; + wire s_axi_hp0_arready; + wire [63:0] s_axi_hp0_rdata; + wire [1:0] s_axi_hp0_rresp; + wire s_axi_hp0_rvalid; + wire s_axi_hp0_rready; + wire s_axi_hp0_rlast; + wire [3:0] s_axi_hp0_arcache; + wire [7:0] s_axi_hp0_awlen; + wire [2:0] s_axi_hp0_awsize; + wire [1:0] s_axi_hp0_awburst; + wire [3:0] s_axi_hp0_awcache; + wire s_axi_hp0_wlast; + wire [7:0] s_axi_hp0_arlen; + wire [1:0] s_axi_hp0_arburst; + wire [2:0] s_axi_hp0_arsize; + + wire [4:0] s_axi_eth_descriptor_awid; + wire [31:0] s_axi_eth_descriptor_awaddr; + wire [2:0] s_axi_eth_descriptor_awprot; + wire s_axi_eth_descriptor_awvalid; + wire s_axi_eth_descriptor_awready; + wire [31:0] s_axi_eth_descriptor_wdata; + wire [3:0] s_axi_eth_descriptor_wstrb; + wire s_axi_eth_descriptor_wvalid; + wire s_axi_eth_descriptor_wready; + wire [1:0] s_axi_eth_descriptor_bresp; + wire s_axi_eth_descriptor_bvalid; + wire s_axi_eth_descriptor_bready; + wire [4:0] s_axi_eth_descriptor_arid; + wire [31:0] s_axi_eth_descriptor_araddr; + wire [2:0] s_axi_eth_descriptor_arprot; + wire s_axi_eth_descriptor_arvalid; + wire s_axi_eth_descriptor_arready; + wire [31:0] s_axi_eth_descriptor_rdata; + wire [1:0] s_axi_eth_descriptor_rresp; + wire s_axi_eth_descriptor_rvalid; + wire s_axi_eth_descriptor_rready; + wire s_axi_eth_descriptor_rlast; + wire [3:0] s_axi_eth_descriptor_arcache; + wire [7:0] s_axi_eth_descriptor_awlen; + wire [2:0] s_axi_eth_descriptor_awsize; + wire [1:0] s_axi_eth_descriptor_awburst; + wire [3:0] s_axi_eth_descriptor_awcache; + wire s_axi_eth_descriptor_wlast; + wire [7:0] s_axi_eth_descriptor_arlen; + wire [1:0] s_axi_eth_descriptor_arburst; + wire [2:0] s_axi_eth_descriptor_arsize; + + // ARM ethernet dma clock crossing + wire [63:0] arm_eth_tx_tdata; + wire arm_eth_tx_tvalid; + wire arm_eth_tx_tlast; + wire arm_eth_tx_tready; + wire [3:0] arm_eth_tx_tuser; + wire [7:0] arm_eth_tx_tkeep; + + wire [63:0] arm_eth_tx_tdata_b; + wire arm_eth_tx_tvalid_b; + wire arm_eth_tx_tlast_b; + wire arm_eth_tx_tready_b; + wire [3:0] arm_eth_tx_tuser_b; + wire [7:0] arm_eth_tx_tkeep_b; + + wire [63:0] arm_eth_rx_tdata; + wire arm_eth_rx_tvalid; + wire arm_eth_rx_tlast; + wire arm_eth_rx_tready; + wire [3:0] arm_eth_rx_tuser; + wire [7:0] arm_eth_rx_tkeep; + + wire [63:0] arm_eth_rx_tdata_b; + wire arm_eth_rx_tvalid_b; + wire arm_eth_rx_tlast_b; + wire arm_eth_rx_tready_b; + wire [3:0] arm_eth_rx_tuser_b; + wire [7:0] arm_eth_rx_tkeep_b; + + wire arm_eth_rx_irq; + wire arm_eth_tx_irq; + + // Vita to Ethernet + wire [63:0] v2e_tdata; + wire v2e_tlast; + wire v2e_tvalid; + wire v2e_tready; + + // Ethernet to Vita + wire [63:0] e2v_tdata; + wire e2v_tlast; + wire e2v_tvalid; + wire e2v_tready; + + // Misc + wire [31:0] sfp_port_info; + wire sfp_link_up; + wire [15:0] device_id; + wire clocks_locked; + + ///////////////////////////////////////////////////////////////////// + // + // Resets: + // - PL - Global Reset --> Bus Reset + // --> Radio Reset + // - PS - FCLK_RESET0_N --> clk40_rst(n) + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen ( + .clk(bus_clk), + .reset_out(global_rst) + ); + + // Synchronous reset for the radio_clk domain + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(~clocks_locked), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(~clocks_locked), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + assign reg_rstn = clk40_rstn; + + ///////////////////////////////////////////////////////////////////// + // + // Clocks and PPS + // + ///////////////////////////////////////////////////////////////////// + + wire pps_refclk; + wire [1:0] pps_select; + wire ref_select; + wire refclk_locked_busclk; + + assign clk40 = FCLK_CLK1; // 40 MHz + assign bus_clk = FCLK_CLK3; // 200 MHz + assign reg_clk = clk40; + + e320_clocking e320_clocking_i ( + .global_rst(global_rst), + .ref_clk_from_pin(CLK_REF_RAW), + .ref_clk(), + .clk156(xgige_clk156), + .ddr3_dma_clk(ddr3_dma_clk), + .clocks_locked(clocks_locked), + .ext_pps_from_pin(CLK_SYNC_EXT), + .gps_pps_from_pin(CLK_SYNC_INT), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + assign CLK_REF_SEL = ref_select; + + synchronizer synchronize_rf_clk_lock ( + .clk(bus_clk), .rst(1'b0), .in(CLK_MUX_OUT), .out(refclk_locked_busclk) + ); + + ///////////////////////////////////////////////////////////////////// + // + // PL DDR3 Memory Interface + // + ///////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), + .ui_clk_sync_rst (ddr3_axi_rst), + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr[30:0]), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr[30:0]), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + .sys_rst (bus_rst) + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL ("INTERNAL"), + .XADC_CLK_PERIOD (5000) // In ps, should match xadc_clk period + ) tempmon_i ( + .clk (bus_clk), + .xadc_clk (bus_clk), + .rst (bus_rst), + .device_temp_i (12'd0), // Not used for "INTERNAL" + .device_temp (device_temp) + ); + + + ///////////////////////////////////////////////////////////////////// + // + // Front-Panel GPIO + // + ///////////////////////////////////////////////////////////////////// + + wire [31:0] fp_gpio_ctrl; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_in; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_out; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri; + + // Turn on GPIO buffers + assign GPIO_OE_N = fp_gpio_ctrl[0]; + + // Enable GPIO supply + assign EN_GPIO_VAR_SUPPLY = fp_gpio_ctrl[1]; + + // GPIO Voltage (1.8V, 2.5V, or 3.3V) + // + // 3V3 2V5 | Voltage + // ----------------- + // 0 0 | 1.8 V + // 0 1 | 2.5 V + // 1 0 | 3.3 V + assign EN_GPIO_2V5 = fp_gpio_ctrl[2]; + assign EN_GPIO_3V3 = fp_gpio_ctrl[3]; + + genvar i; + generate + for (i = 0; i < FP_GPIO_WIDTH; i = i+1) begin : gen_gpio_iobuf + assign fp_gpio_in[i] = GPIO_PREBUFF[i]; + assign GPIO_PREBUFF[i] = fp_gpio_tri[i] ? 1'bZ : fp_gpio_out[i]; + assign GPIO_DIR[i] = ~fp_gpio_tri[i]; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////// + // + // GPIO Interface + // - Control Filter Banks + // - LEDs + // + ///////////////////////////////////////////////////////////////////// + + // Flattened Radio GPIO control + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat; + wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat; + wire [32*NUM_CHANNELS-1:0] leds_flat; + + // Radio GPIO control + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_pins[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + + assign db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_in[i]; + assign db_gpio_out[i] = db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_ddr[i] = db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign leds[i] = leds_flat[32*i +: 32]; + + gpio_atr_io #( + .WIDTH(DB_GPIO_WIDTH) + ) gpio_atr_db_inst ( + .clk(radio_clk), + .gpio_pins(db_gpio_pins[i]), + .gpio_ddr(db_gpio_ddr[i]), + .gpio_out(db_gpio_out[i]), + .gpio_in(db_gpio_in[i]) + ); + end + endgenerate + + // DB_GPIO and LED pin assignments with software mapping + + // Channel 1 + assign {TX_HFAMP1_ENA, // HF TX AMP + TX_LFAMP1_ENA, // LF TX AMP + FE1_SEL[2:0], // TRX Switch + TX1_BSEL[5:3], // TX_SW2 + TX1_BSEL[2:0], // TX_SW1 + RX1_SEL[1:0], // RX_SW3 + RX1_BSEL[5:3], // RX_SW2 + RX1_BSEL[2:0] // RX_SW1 + } = db_gpio_pins[0]; + + assign {RX1_GRN_ENA, //TX/RX led + TX1_RED_ENA, //TX/RX led + TXRX1_GRN_ENA //RX2 led + } = leds[0]; + + // Channel 2 + assign {TX_HFAMP2_ENA, // HF TX AMP + TX_LFAMP2_ENA, // LF TX AMP + FE2_SEL[2:0], // TRX Switch + TX2_BSEL[5:3], // TX_SW2 + TX2_BSEL[2:0], // TX_SW1 + RX2_SEL[1:0], // RX_SW3 + RX2_BSEL[5:3], // RX_SW2 + RX2_BSEL[2:0] // RX_SW1 + } = db_gpio_pins[1]; + + assign {RX2_GRN_ENA, + TX2_RED_ENA, + TXRX2_GRN_ENA + } = leds[1]; + + ///////////////////////////////////////////////////////////////////// + // + // 5V Power Supply (TX Amplifier) + // + ///////////////////////////////////////////////////////////////////// + + assign ENA_PAPWR = 1'b1; + + ///////////////////////////////////////////////////////////////////// + // + // AD9361 Interface + // + ///////////////////////////////////////////////////////////////////// + + wire [NUM_CHANNELS*32-1:0] rx_flat, tx_flat; + + wire [11:0] rx_i0, rx_q0, tx_i0, tx_q0; + wire [11:0] rx_i1, rx_q1, tx_i1, tx_q1; + + wire [NUM_CHANNELS-1:0] rx_stb, tx_stb; + wire [NUM_CHANNELS-1:0] rx_atr, tx_atr; + + wire [REG_DWIDTH-1:0] dboard_ctrl; + wire [REG_DWIDTH-1:0] dboard_status; + wire mimo_busclk, mimo_radioclk; + wire tx_chan_sel_busclk, tx_chan_sel_radioclk; + wire rx_aligned; + + wire tx_pll_lock_busclk, rx_pll_lock_busclk; + + synchronizer synchronizer_tx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(XCVR_CTRL_OUT[7]), .out(tx_pll_lock_busclk) + ); + + synchronizer synchronizer_rx_pll_lock ( + .clk(bus_clk), .rst(1'b0), .in(XCVR_CTRL_OUT[6]), .out(rx_pll_lock_busclk) + ); + + assign dboard_status = { + 24'b0, + tx_pll_lock_busclk, // TX PLL Lock + rx_pll_lock_busclk, // RX PLL Lock + 6'b0 + }; + + assign mimo_busclk = dboard_ctrl[0]; + assign tx_chan_sel_busclk = dboard_ctrl[1]; + + synchronizer synchronizer_mimo_radioclk ( + .clk(radio_clk), .rst(1'b0), .in(mimo_busclk), .out(mimo_radioclk) + ); + + synchronizer synchronizer_tx_chan_sel_radioclk ( + .clk(radio_clk), .rst(1'b0), .in(tx_chan_sel_busclk), .out(tx_chan_sel_radioclk) + ); + + assign rx_flat = {rx_i1, 4'b0, rx_q1, 4'b0, + rx_i0, 4'b0, rx_q0, 4'b0}; + + assign tx_q0 = tx_flat[15:4]; + assign tx_i0 = tx_flat[31:20]; + assign tx_q1 = tx_flat[47:36]; + assign tx_i1 = tx_flat[63:52]; + + // Tx and Rx have samples on every clock, so keep stb asserted + assign rx_stb = { 1'b1, 1'b1 }; + assign tx_stb = { 1'b1, 1'b1 }; + + // These delays depend on the internal clock routing delays of the FPGA. + // Valid timing constraints are required to confirm that setup/hold are met + // at both the input and output interfaces. + localparam INPUT_DATA_DELAY = 27; + localparam OUTPUT_DATA_DELAY = 19; + + assign XCVR_ENABLE = 1'b1; + assign XCVR_SYNC = 1'b0; + assign XCVR_TXNRX = 1'b1; + assign XCVR_ENA_AGC = 1'b1; + assign XCVR_RESET_N = ~bus_rst; + + cat_io_lvds_dual_mode #( + .INVERT_FRAME_RX (0), + .INVERT_DATA_RX (6'b00_0000), + .INVERT_FRAME_TX (0), + .INVERT_DATA_TX (6'b00_0000), + .USE_CLOCK_IDELAY (0), + .USE_DATA_IDELAY (1), + .DATA_IDELAY_MODE ("FIXED"), + .CLOCK_IDELAY_MODE ("FIXED"), + .INPUT_CLOCK_DELAY (0), + .INPUT_DATA_DELAY (INPUT_DATA_DELAY), + .USE_CLOCK_ODELAY (1), + .USE_DATA_ODELAY (1), + .DATA_ODELAY_MODE ("FIXED"), + .CLOCK_ODELAY_MODE ("FIXED"), + .OUTPUT_CLOCK_DELAY (0), + .OUTPUT_DATA_DELAY (OUTPUT_DATA_DELAY) + ) cat_io_lvds_dual_mode_i0 ( + .rst (radio_rst), + .clk200 (bus_clk), // 200 MHz clock + + // Data and frame timing + .a_mimo (mimo_busclk), + .a_tx_ch (tx_chan_sel_busclk), + + // Delay control interface (not used) + .ctrl_clk (bus_clk), + // + .ctrl_in_data_delay (5'b00000), + .ctrl_in_clk_delay (5'b00000), + .ctrl_ld_in_data_delay (1'b0), + .ctrl_ld_in_clk_delay (1'b0), + // + .ctrl_out_data_delay (5'b00000), + .ctrl_out_clk_delay (5'b00000), + .ctrl_ld_out_data_delay (1'b0), + .ctrl_ld_out_clk_delay (1'b0), + + // Sample interface + .radio_clk (radio_clk), + .rx_aligned (rx_aligned), + // + .rx_i0 (rx_i0), + .rx_q0 (rx_q0), + .rx_i1 (rx_i1), + .rx_q1 (rx_q1), + // + .tx_i0 (tx_i0), + .tx_q0 (tx_q0), + .tx_i1 (tx_i1), + .tx_q1 (tx_q1), + + // AD9361 interface + .rx_clk_p (RX_CLK_P), + .rx_clk_n (RX_CLK_N), + .rx_frame_p (RX_FRAME_P), + .rx_frame_n (RX_FRAME_N), + .rx_d_p (RX_DATA_P), + .rx_d_n (RX_DATA_N), + // + .tx_clk_p (TX_CLK_P), + .tx_clk_n (TX_CLK_N), + .tx_frame_p (TX_FRAME_P), + .tx_frame_n (TX_FRAME_N), + .tx_d_p (TX_DATA_P), + .tx_d_n (TX_DATA_N) + ); + + ///////////////////////////////////////////////////////////////////// + // + // SFP Connections: + // - 1G + // - 10G + // - Aurora + // + ////////////////////////////////////////////////////////////////////// + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // 1G requires 125 MHz reference clock + //-------------------------------------------------------------- + + wire gige_refclk; + wire gige_refclk_bufg; + + // dont_touch required for good SI on clock + (* dont_touch = "true" *) IBUFDS_GTE2 gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (CLK_MGT_125M_P), + .IB(CLK_MGT_125M_N), + .O (gige_refclk) + ); + + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // XG requires 156.25 MHz reference clock + //-------------------------------------------------------------- + + wire xgige_refclk; + wire xgige_dclk; + + // dont_touch required for good SI on clock + (* dont_touch = "true" *) IBUFDS_GTE2 ten_gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (CLK_MGT_156_25M_P), + .IB(CLK_MGT_156_25M_N), + .O (xgige_refclk) + ); + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + //-------------------------------------------------------------- + // SFP Reference Clocks: + // XG requires 156.25 MHz reference clock + //-------------------------------------------------------------- + + wire aurora_refclk; + wire aurora_clk156; + wire aurora_init_clk; + + // Use the 156.25MHz reference clock for Aurora + assign aurora_refclk = xgige_refclk; + assign aurora_clk156 = xgige_clk156; + assign aurora_init_clk = xgige_dclk; + + wire sfp_gt_refclk; + wire sfp_gb_refclk; + wire sfp_misc_clk; + + // Make SFP1_RS1 open drain to avoid a short circuit when it is connected to + // ground by the SFP module (per the SFP+ specification). + wire SFP1_RS1_t; + assign SFP1_RS1 = SFP1_RS1_t ? 1'bZ : 1'b0; + + // Select Reference Clock according to Protocol + generate + if (PROTOCOL == "10GbE") begin + + assign sfp_gt_refclk = xgige_refclk; + assign sfp_gb_refclk = xgige_clk156; + assign sfp_misc_clk = xgige_dclk; + assign SFP1_RS0 = 1'b1; + assign SFP1_RS1_t = 1'b1; + + end else if (PROTOCOL == "1GbE") begin + + assign sfp_gt_refclk = gige_refclk; + assign sfp_gb_refclk = gige_refclk_bufg; + assign sfp_misc_clk = gige_refclk_bufg; + assign SFP1_RS0 = 1'b0; + assign SFP1_RS1_t = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + assign sfp_gt_refclk = aurora_refclk; + assign sfp_gb_refclk = aurora_clk156; + assign sfp_misc_clk = aurora_init_clk; + assign SFP1_RS0 = 1'b1; + assign SFP1_RS1_t = 1'b1; + + end else begin + + assign sfp_gt_refclk = 1'b0; + assign sfp_gb_refclk = 1'b0; + assign sfp_misc_clk = 1'b0; + assign SFP1_RS0 = 1'b0; + assign SFP1_RS1_t = 1'b0; + + end + endgenerate + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper: All protocols (1G/XG/AA) + eth_switch + // + ///////////////////////////////////////////////////////////////////// + + n3xx_sfp_wrapper #( + .PROTOCOL(PROTOCOL), + .MDIO_EN(MDIO_EN), + .MDIO_PHYADDR(MDIO_PHYADDR), + .DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM(SFP_PORTNUM) + ) sfp_wrapper_i ( + .areset(bus_rst), + .gt_refclk(sfp_gt_refclk), + .gb_refclk(sfp_gb_refclk), + .misc_clk(sfp_misc_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + .user_clk(), + .sync_clk(), + + // GT_COMMON + .qpllreset(), + .qplllock(1'b0), + .qplloutclk(1'b0), + .qplloutrefclk(1'b0), + .qpllrefclklost(), + + .mmcm_locked(1'b0), + .gt_pll_lock(), + + .txp(SFP1_TX_P), + .txn(SFP1_TX_N), + .rxp(SFP1_RX_P), + .rxn(SFP1_RX_N), + + .sfpp_rxlos(SFP1_RXLOS), + .sfpp_tx_fault(SFP1_TXFAULT), + .sfpp_tx_disable(SFP1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(reg_clk), + .s_axi_aresetn(reg_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_net_awaddr[REG_AWIDTH-1:0]), + .s_axi_awvalid(m_axi_net_awvalid), + .s_axi_awready(m_axi_net_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_net_wdata), + .s_axi_wstrb(m_axi_net_wstrb), + .s_axi_wvalid(m_axi_net_wvalid), + .s_axi_wready(m_axi_net_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_net_bresp), + .s_axi_bvalid(m_axi_net_bvalid), + .s_axi_bready(m_axi_net_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_net_araddr[REG_AWIDTH-1:0]), + .s_axi_arvalid(m_axi_net_arvalid), + .s_axi_arready(m_axi_net_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_net_rdata), + .s_axi_rresp(m_axi_net_rresp), + .s_axi_rvalid(m_axi_net_rvalid), + .s_axi_rready(m_axi_net_rready), + + // Ethernet to Vita + .e2v_tdata(e2v_tdata), + .e2v_tlast(e2v_tlast), + .e2v_tvalid(e2v_tvalid), + .e2v_tready(e2v_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_tdata), + .v2e_tlast(v2e_tlast), + .v2e_tvalid(v2e_tvalid), + .v2e_tready(v2e_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_rx_tdata_b), + .e2c_tkeep(arm_eth_rx_tkeep_b), + .e2c_tlast(arm_eth_rx_tlast_b), + .e2c_tvalid(arm_eth_rx_tvalid_b), + .e2c_tready(arm_eth_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_tx_tdata_b), + .c2e_tkeep(arm_eth_tx_tkeep_b), + .c2e_tlast(arm_eth_tx_tlast_b), + .c2e_tvalid(arm_eth_tx_tvalid_b), + .c2e_tready(arm_eth_tx_tready_b), + + // Misc + .port_info(sfp_port_info), + .device_id(device_id), + + // LED + .link_up(sfp_link_up), + .activity(LED_ACT1) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp_link_up : ps_gpio_out[60]; + assign LED_LINK1 = sfp_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA (SFP to ARM) + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth_rx_irq; + assign IRQ_F2P[1] = arm_eth_tx_irq; + + assign {s_axi_hp0_awid, s_axi_hp0_arid} = 12'd0; + assign {s_axi_eth_descriptor_awid, s_axi_eth_descriptor_arid} = 10'd0; + + axi_eth_dma inst_axi_eth_dma ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(m_axi_eth_dma_awaddr), //FIXME: Synthesis Warning: port width(10) doesn't match 32 + .s_axi_lite_awvalid(m_axi_eth_dma_awvalid), + .s_axi_lite_awready(m_axi_eth_dma_awready), + + .s_axi_lite_wdata(m_axi_eth_dma_wdata), + .s_axi_lite_wvalid(m_axi_eth_dma_wvalid), + .s_axi_lite_wready(m_axi_eth_dma_wready), + + .s_axi_lite_bresp(m_axi_eth_dma_bresp), + .s_axi_lite_bvalid(m_axi_eth_dma_bvalid), + .s_axi_lite_bready(m_axi_eth_dma_bready), + + .s_axi_lite_araddr(m_axi_eth_dma_araddr), //FIXME: Synthesis Warning: port width(10) doesn't match 32 + .s_axi_lite_arvalid(m_axi_eth_dma_arvalid), + .s_axi_lite_arready(m_axi_eth_dma_arready), + + .s_axi_lite_rdata(m_axi_eth_dma_rdata), + .s_axi_lite_rresp(m_axi_eth_dma_rresp), + .s_axi_lite_rvalid(m_axi_eth_dma_rvalid), + .s_axi_lite_rready(m_axi_eth_dma_rready), + + .m_axi_sg_awaddr(s_axi_eth_descriptor_awaddr), + .m_axi_sg_awlen(s_axi_eth_descriptor_awlen), + .m_axi_sg_awsize(s_axi_eth_descriptor_awsize), + .m_axi_sg_awburst(s_axi_eth_descriptor_awburst), + .m_axi_sg_awprot(s_axi_eth_descriptor_awprot), + .m_axi_sg_awcache(s_axi_eth_descriptor_awcache), + .m_axi_sg_awvalid(s_axi_eth_descriptor_awvalid), + .m_axi_sg_awready(s_axi_eth_descriptor_awready), + .m_axi_sg_wdata(s_axi_eth_descriptor_wdata), + .m_axi_sg_wstrb(s_axi_eth_descriptor_wstrb), + .m_axi_sg_wlast(s_axi_eth_descriptor_wlast), + .m_axi_sg_wvalid(s_axi_eth_descriptor_wvalid), + .m_axi_sg_wready(s_axi_eth_descriptor_wready), + .m_axi_sg_bresp(s_axi_eth_descriptor_bresp), + .m_axi_sg_bvalid(s_axi_eth_descriptor_bvalid), + .m_axi_sg_bready(s_axi_eth_descriptor_bready), + .m_axi_sg_araddr(s_axi_eth_descriptor_araddr), + .m_axi_sg_arlen(s_axi_eth_descriptor_arlen), + .m_axi_sg_arsize(s_axi_eth_descriptor_arsize), + .m_axi_sg_arburst(s_axi_eth_descriptor_arburst), + .m_axi_sg_arprot(s_axi_eth_descriptor_arprot), + .m_axi_sg_arcache(s_axi_eth_descriptor_arcache), + .m_axi_sg_arvalid(s_axi_eth_descriptor_arvalid), + .m_axi_sg_arready(s_axi_eth_descriptor_arready), + .m_axi_sg_rdata(s_axi_eth_descriptor_rdata), + .m_axi_sg_rresp(s_axi_eth_descriptor_rresp), + .m_axi_sg_rlast(s_axi_eth_descriptor_rlast), + .m_axi_sg_rvalid(s_axi_eth_descriptor_rvalid), + .m_axi_sg_rready(s_axi_eth_descriptor_rready), + + .m_axi_mm2s_araddr(s_axi_hp0_araddr), + .m_axi_mm2s_arlen(s_axi_hp0_arlen), + .m_axi_mm2s_arsize(s_axi_hp0_arsize), + .m_axi_mm2s_arburst(s_axi_hp0_arburst), + .m_axi_mm2s_arprot(s_axi_hp0_arprot), + .m_axi_mm2s_arcache(s_axi_hp0_arcache), + .m_axi_mm2s_arvalid(s_axi_hp0_arvalid), + .m_axi_mm2s_arready(s_axi_hp0_arready), + .m_axi_mm2s_rdata(s_axi_hp0_rdata), + .m_axi_mm2s_rresp(s_axi_hp0_rresp), + .m_axi_mm2s_rlast(s_axi_hp0_rlast), + .m_axi_mm2s_rvalid(s_axi_hp0_rvalid), + .m_axi_mm2s_rready(s_axi_hp0_rready), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth_tx_tvalid), + .m_axis_mm2s_tready(arm_eth_tx_tready), + .m_axis_mm2s_tlast(arm_eth_tx_tlast), + + .m_axi_s2mm_awaddr(s_axi_hp0_awaddr), + .m_axi_s2mm_awlen(s_axi_hp0_awlen), + .m_axi_s2mm_awsize(s_axi_hp0_awsize), + .m_axi_s2mm_awburst(s_axi_hp0_awburst), + .m_axi_s2mm_awprot(s_axi_hp0_awprot), + .m_axi_s2mm_awcache(s_axi_hp0_awcache), + .m_axi_s2mm_awvalid(s_axi_hp0_awvalid), + .m_axi_s2mm_awready(s_axi_hp0_awready), + .m_axi_s2mm_wdata(s_axi_hp0_wdata), + .m_axi_s2mm_wstrb(s_axi_hp0_wstrb), + .m_axi_s2mm_wlast(s_axi_hp0_wlast), + .m_axi_s2mm_wvalid(s_axi_hp0_wvalid), + .m_axi_s2mm_wready(s_axi_hp0_wready), + .m_axi_s2mm_bresp(s_axi_hp0_bresp), + .m_axi_s2mm_bvalid(s_axi_hp0_bvalid), + .m_axi_s2mm_bready(s_axi_hp0_bready), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth_rx_tvalid), + .s_axis_s2mm_tready(arm_eth_rx_tready), + .s_axis_s2mm_tlast(arm_eth_rx_tlast), + + .mm2s_introut(arm_eth_tx_irq), + .s2mm_introut(arm_eth_rx_irq), + .axi_dma_tstvec() + ); + + // Clock crossing fifo from dma(clk40) to sfp(bus_clk) + axi_fifo_2clk #(.WIDTH(1+8+64), .SIZE(5)) eth_tx_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth_tx_tlast, arm_eth_tx_tkeep, arm_eth_tx_tdata}), + .i_tvalid(arm_eth_tx_tvalid), + .i_tready(arm_eth_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth_tx_tlast_b, arm_eth_tx_tkeep_b, arm_eth_tx_tdata_b}), + .o_tvalid(arm_eth_tx_tvalid_b), + .o_tready(arm_eth_tx_tready_b) + ); + + // Clock crossing fifo from sfp(bus_clk) to dma(clk40) + axi_fifo_2clk #(.WIDTH(1+8+64), .SIZE(5)) eth_rx_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth_rx_tlast_b, arm_eth_rx_tkeep_b, arm_eth_rx_tdata_b}), + .i_tvalid(arm_eth_rx_tvalid_b), + .i_tready(arm_eth_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth_rx_tlast, arm_eth_rx_tkeep, arm_eth_rx_tdata}), + .o_tvalid(arm_eth_rx_tvalid), + .o_tready(arm_eth_rx_tready) + ); + + ///////////////////////////////////////////////////////////////////// + // + // PS Connections + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_tri; + + e320_ps_bd e320_ps_bd_i ( + // DDR Interface + .DDR_VRN(PS_DDR3_VRN), + .DDR_VRP(PS_DDR3_VRP), + .DDR_addr(PS_DDR3_ADDR), + .DDR_ba(PS_DDR3_BA), + .DDR_cas_n(PS_DDR3_CAS_N), + .DDR_ck_n(DDR_MODCLK_N), + .DDR_ck_p(DDR_MODCLK_P), + .DDR_cke(PS_DDR3_CKE), + .DDR_cs_n(PS_DDR3_CS_N), + .DDR_dm(PS_DDR3_DM), + .DDR_dq(PS_DDR3_DQ), + .DDR_dqs_n(PS_DDR3_DQS_N), + .DDR_dqs_p(PS_DDR3_DQS_P), + .DDR_odt(PS_DDR3_ODT), + .DDR_ras_n(PS_DDR3_RAS_N), + .DDR_reset_n(PS_DDR3_RESET_N), + .DDR_we_n(PS_DDR3_WE_N), + + // Clocks + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_CLK3(FCLK_CLK3), + + // Resets + .FCLK_RESET0_N(FCLK_RESET0_N), + + // GPIO + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + // Interrupts + .IRQ_F2P(IRQ_F2P), + + // MIO + .MIO(PS_MIO), + + .PS_CLK(PS_CLK), + .PS_PORB(PS_POR_B), + .PS_SRSTB(PS_SRST_B), + + // SPI + .SPI0_MISO_I(XCVR_SPI_MISO), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(XCVR_SPI_MOSI), + .SPI0_MOSI_T(), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(XCVR_SPI_CLK), + .SPI0_SCLK_T(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(XCVR_SPI_CS_N), + .SPI0_SS_T(), + + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(CLK_PLL_SDATA), + .SPI1_MOSI_T(), + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(CLK_PLL_SCLK), + .SPI1_SCLK_T(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(CLK_PLL_SLE), + .SPI1_SS_T(), + + // Eth DMA Descriptor + .s_axi_eth_descriptor_araddr(s_axi_eth_descriptor_araddr), + .s_axi_eth_descriptor_arburst(s_axi_eth_descriptor_arburst), + .s_axi_eth_descriptor_arcache(s_axi_eth_descriptor_arcache), + .s_axi_eth_descriptor_arid(s_axi_eth_descriptor_arid), + .s_axi_eth_descriptor_arlen(s_axi_eth_descriptor_arlen), + .s_axi_eth_descriptor_arlock(1'b0), + .s_axi_eth_descriptor_arprot(s_axi_eth_descriptor_arprot), + .s_axi_eth_descriptor_arqos(4'b0), + .s_axi_eth_descriptor_arready(s_axi_eth_descriptor_arready), + .s_axi_eth_descriptor_arsize(s_axi_eth_descriptor_arsize), + .s_axi_eth_descriptor_arvalid(s_axi_eth_descriptor_arvalid), + .s_axi_eth_descriptor_awaddr(s_axi_eth_descriptor_awaddr), + .s_axi_eth_descriptor_awburst(s_axi_eth_descriptor_awburst), + .s_axi_eth_descriptor_awcache(s_axi_eth_descriptor_awcache), + .s_axi_eth_descriptor_awid(s_axi_eth_descriptor_awid), + .s_axi_eth_descriptor_awlen(s_axi_eth_descriptor_awlen), + .s_axi_eth_descriptor_awlock(1'b0), + .s_axi_eth_descriptor_awprot(s_axi_eth_descriptor_awprot), + .s_axi_eth_descriptor_awqos(4'b0), + .s_axi_eth_descriptor_awready(s_axi_eth_descriptor_awready), + .s_axi_eth_descriptor_awsize(s_axi_eth_descriptor_awsize), + .s_axi_eth_descriptor_awvalid(s_axi_eth_descriptor_awvalid), + .s_axi_eth_descriptor_bid(), + .s_axi_eth_descriptor_bready(s_axi_eth_descriptor_bready), + .s_axi_eth_descriptor_bresp(s_axi_eth_descriptor_bresp), + .s_axi_eth_descriptor_bvalid(s_axi_eth_descriptor_bvalid), + .s_axi_eth_descriptor_rdata(s_axi_eth_descriptor_rdata), + .s_axi_eth_descriptor_rid(), + .s_axi_eth_descriptor_rlast(s_axi_eth_descriptor_rlast), + .s_axi_eth_descriptor_rready(s_axi_eth_descriptor_rready), + .s_axi_eth_descriptor_rresp(s_axi_eth_descriptor_rresp), + .s_axi_eth_descriptor_rvalid(s_axi_eth_descriptor_rvalid), + .s_axi_eth_descriptor_wdata(s_axi_eth_descriptor_wdata), + .s_axi_eth_descriptor_wlast(s_axi_eth_descriptor_wlast), + .s_axi_eth_descriptor_wready(s_axi_eth_descriptor_wready), + .s_axi_eth_descriptor_wstrb(s_axi_eth_descriptor_wstrb), + .s_axi_eth_descriptor_wvalid(s_axi_eth_descriptor_wvalid), + + // HP0 - Eth DMA + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(s_axi_hp0_araddr), + .S_AXI_HP0_arburst(s_axi_hp0_arburst), + .S_AXI_HP0_arcache(s_axi_hp0_arcache), + .S_AXI_HP0_arid(s_axi_hp0_arid), + .S_AXI_HP0_arlen(s_axi_hp0_arlen), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(s_axi_hp0_arprot), + .S_AXI_HP0_arqos(4'b0), + .S_AXI_HP0_arready(s_axi_hp0_arready), + .S_AXI_HP0_arsize(s_axi_hp0_arsize), + .S_AXI_HP0_arvalid(s_axi_hp0_arvalid), + .S_AXI_HP0_awaddr(s_axi_hp0_awaddr), + .S_AXI_HP0_awburst(s_axi_hp0_awburst), + .S_AXI_HP0_awcache(s_axi_hp0_awcache), + .S_AXI_HP0_awid(s_axi_hp0_awid), + .S_AXI_HP0_awlen(s_axi_hp0_awlen), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(s_axi_hp0_awprot), + .S_AXI_HP0_awqos(4'b0), + .S_AXI_HP0_awready(s_axi_hp0_awready), + .S_AXI_HP0_awsize(s_axi_hp0_awsize), + .S_AXI_HP0_awvalid(s_axi_hp0_awvalid), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(s_axi_hp0_bready), + .S_AXI_HP0_bresp(s_axi_hp0_bresp), + .S_AXI_HP0_bvalid(s_axi_hp0_bvalid), + .S_AXI_HP0_rdata(s_axi_hp0_rdata), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(s_axi_hp0_rlast), + .S_AXI_HP0_rready(s_axi_hp0_rready), + .S_AXI_HP0_rresp(s_axi_hp0_rresp), + .S_AXI_HP0_rvalid(s_axi_hp0_rvalid), + .S_AXI_HP0_wdata(s_axi_hp0_wdata), + .S_AXI_HP0_wlast(s_axi_hp0_wlast), + .S_AXI_HP0_wready(s_axi_hp0_wready), + .S_AXI_HP0_wstrb(s_axi_hp0_wstrb), + .S_AXI_HP0_wvalid(s_axi_hp0_wvalid), + .m_axi_eth_dma_araddr(m_axi_eth_dma_araddr), + .m_axi_eth_dma_arprot(), + .m_axi_eth_dma_arready(m_axi_eth_dma_arready), + .m_axi_eth_dma_arvalid(m_axi_eth_dma_arvalid), + .m_axi_eth_dma_awaddr(m_axi_eth_dma_awaddr), + .m_axi_eth_dma_awprot(), + .m_axi_eth_dma_awready(m_axi_eth_dma_awready), + .m_axi_eth_dma_awvalid(m_axi_eth_dma_awvalid), + .m_axi_eth_dma_bready(m_axi_eth_dma_bready), + .m_axi_eth_dma_bresp(m_axi_eth_dma_bresp), + .m_axi_eth_dma_bvalid(m_axi_eth_dma_bvalid), + .m_axi_eth_dma_rdata(m_axi_eth_dma_rdata), + .m_axi_eth_dma_rready(m_axi_eth_dma_rready), + .m_axi_eth_dma_rresp(m_axi_eth_dma_rresp), + .m_axi_eth_dma_rvalid(m_axi_eth_dma_rvalid), + .m_axi_eth_dma_wdata(m_axi_eth_dma_wdata), + .m_axi_eth_dma_wready(m_axi_eth_dma_wready), + .m_axi_eth_dma_wstrb(m_axi_eth_dma_wstrb), + .m_axi_eth_dma_wvalid(m_axi_eth_dma_wvalid), + + // MGT IO Regport + .m_axi_net_araddr(m_axi_net_araddr), + .m_axi_net_arprot(), + .m_axi_net_arready(m_axi_net_arready), + .m_axi_net_arvalid(m_axi_net_arvalid), + .m_axi_net_awaddr(m_axi_net_awaddr), + .m_axi_net_awprot(), + .m_axi_net_awready(m_axi_net_awready), + .m_axi_net_awvalid(m_axi_net_awvalid), + .m_axi_net_bready(m_axi_net_bready), + .m_axi_net_bresp(m_axi_net_bresp), + .m_axi_net_bvalid(m_axi_net_bvalid), + .m_axi_net_rdata(m_axi_net_rdata), + .m_axi_net_rready(m_axi_net_rready), + .m_axi_net_rresp(m_axi_net_rresp), + .m_axi_net_rvalid(m_axi_net_rvalid), + .m_axi_net_wdata(m_axi_net_wdata), + .m_axi_net_wready(m_axi_net_wready), + .m_axi_net_wstrb(m_axi_net_wstrb), + .m_axi_net_wvalid(m_axi_net_wvalid), + + // XBAR Regport + .m_axi_xbar_araddr(m_axi_xbar_araddr), + .m_axi_xbar_arprot(), + .m_axi_xbar_arready(m_axi_xbar_arready), + .m_axi_xbar_arvalid(m_axi_xbar_arvalid), + .m_axi_xbar_awaddr(m_axi_xbar_awaddr), + .m_axi_xbar_awprot(), + .m_axi_xbar_awready(m_axi_xbar_awready), + .m_axi_xbar_awvalid(m_axi_xbar_awvalid), + .m_axi_xbar_bready(m_axi_xbar_bready), + .m_axi_xbar_bresp(m_axi_xbar_bresp), + .m_axi_xbar_bvalid(m_axi_xbar_bvalid), + .m_axi_xbar_rdata(m_axi_xbar_rdata), + .m_axi_xbar_rready(m_axi_xbar_rready), + .m_axi_xbar_rresp(m_axi_xbar_rresp), + .m_axi_xbar_rvalid(m_axi_xbar_rvalid), + .m_axi_xbar_wdata(m_axi_xbar_wdata), + .m_axi_xbar_wready(m_axi_xbar_wready), + .m_axi_xbar_wstrb(m_axi_xbar_wstrb), + .m_axi_xbar_wvalid(m_axi_xbar_wvalid), + + // USB + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + + // DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid) + ); + + ///////////////////////////////////////////////////////////////////// + // + // GPSDO Control and Status + // + ///////////////////////////////////////////////////////////////////// + + wire [31:0] gps_ctrl; + wire [31:0] gps_status; + + assign CLK_GPS_PWR_EN = gps_ctrl[0]; + assign GPS_RST_N = gps_ctrl[1]; + assign GPS_INITSURV_N = gps_ctrl[2]; + assign gps_status[0] = GPS_LOCK; + assign gps_status[1] = GPS_ALARM; + assign gps_status[2] = GPS_PHASELOCK; + assign gps_status[3] = GPS_SURVEY; + assign gps_status[4] = GPS_WARMUP; + assign gps_status[31:5] = 'd0; + + ///////////////////////////////////////////////////////////////////// + // + // E320 Core: + // - xbar + // - Radio + // - DMA + // - DRAM + // - CEs + // + ////////////////////////////////////////////////////////////////////// + + wire [31:0] build_datestamp; + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + e320_core #( + .REG_AWIDTH(REG_AWIDTH), + .BUS_CLK_RATE(BUS_CLK_RATE), + .NUM_RADIOS(NUM_RADIOS), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .DB_GPIO_WIDTH(DB_GPIO_WIDTH) + ) e320_core_i ( + + //Clocks and resets + .radio_clk(radio_clk), + .radio_rst(radio_rst), + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps_refclk(pps_refclk), + .refclk_locked(refclk_locked_busclk), + .pps_select(pps_select), + .ref_select(ref_select), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(m_axi_xbar_awaddr), + .s_axi_awvalid(m_axi_xbar_awvalid), + .s_axi_awready(m_axi_xbar_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(m_axi_xbar_wdata), + .s_axi_wstrb(m_axi_xbar_wstrb), + .s_axi_wvalid(m_axi_xbar_wvalid), + .s_axi_wready(m_axi_xbar_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(m_axi_xbar_bresp), + .s_axi_bvalid(m_axi_xbar_bvalid), + .s_axi_bready(m_axi_xbar_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(m_axi_xbar_araddr), + .s_axi_arvalid(m_axi_xbar_arvalid), + .s_axi_arready(m_axi_xbar_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(m_axi_xbar_rdata), + .s_axi_rresp(m_axi_xbar_rresp), + .s_axi_rvalid(m_axi_xbar_rvalid), + .s_axi_rready(m_axi_xbar_rready), + + // DRAM signals + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + + // Front-Panel GPIO + .fp_gpio_in(fp_gpio_in), + .fp_gpio_tri(fp_gpio_tri), + .fp_gpio_out(fp_gpio_out), + + // PS GPIO Connection + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1: FP_GPIO_OFFSET]), + + // DB GPIO + .db_gpio_out_flat(db_gpio_out_flat), + .db_gpio_ddr_flat(db_gpio_ddr_flat), + .db_gpio_in_flat(db_gpio_in_flat), + .db_gpio_fab_flat(32'b0), // FIXME: Incorrect width + + // TX/RX LEDs + .leds_flat(leds_flat), + + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e_tdata(v2e_tdata), + .v2e_tvalid(v2e_tvalid), + .v2e_tlast(v2e_tlast), + .v2e_tready(v2e_tready), + + // Ethernet to VITA + .e2v_tdata(e2v_tdata), + .e2v_tlast(e2v_tlast), + .e2v_tvalid(e2v_tvalid), + .e2v_tready(e2v_tready), + + .build_datestamp(build_datestamp), + .sfp_ports_info(sfp_port_info), + .gps_status(gps_status), + .gps_ctrl(gps_ctrl), + .dboard_status(dboard_status), + .xadc_readback({20'h0, device_temp}), + .fp_gpio_ctrl(fp_gpio_ctrl), + .dboard_ctrl(dboard_ctrl), + .device_id(device_id) + ); + +endmodule // e320 +`default_nettype wire diff --git a/fpga/usrp3/top/e320/e320_10ge.xdc b/fpga/usrp3/top/e320/e320_10ge.xdc new file mode 100644 index 000000000..ad84a1b7f --- /dev/null +++ b/fpga/usrp3/top/e320/e320_10ge.xdc @@ -0,0 +1,16 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0-or-later +# + + +# No need for any asynchronous clock groups between bus_clk and the recovered clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. + +# Remove analysis between the xge_clk and the recovered clocks from the MGT PHYs, +# since they cannot be related to one another with any known phase or period. +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] diff --git a/fpga/usrp3/top/e320/e320_10ge_port0.xdc b/fpga/usrp3/top/e320/e320_10ge_port0.xdc new file mode 100644 index 000000000..3cb98091b --- /dev/null +++ b/fpga/usrp3/top/e320/e320_10ge_port0.xdc @@ -0,0 +1,7 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ "*sfp_wrapper_0/mgt_io_i/ten_gige_phy_i/*gtxe2_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_CHANNEL}] +set_property LOC GTXE2_COMMON_X0Y12 [get_cells -hierarchical -filter {NAME =~ "*gtxe2_common_0_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_COMMON}] diff --git a/fpga/usrp3/top/e320/e320_1ge.xdc b/fpga/usrp3/top/e320/e320_1ge.xdc new file mode 100644 index 000000000..7d5f51641 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_1ge.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between clk100 and the recovered clocks, +# because clk100 already has a blanket asynchronous constraint from the top level XDC. +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks ge_clk] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT1]] + +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*reset_sync*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/e320/e320_aurora.xdc b/fpga/usrp3/top/e320/e320_aurora.xdc new file mode 100644 index 000000000..3f6860de3 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_aurora.xdc @@ -0,0 +1,13 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] diff --git a/fpga/usrp3/top/e320/e320_clocking.v b/fpga/usrp3/top/e320/e320_clocking.v new file mode 100644 index 000000000..fff99180e --- /dev/null +++ b/fpga/usrp3/top/e320/e320_clocking.v @@ -0,0 +1,220 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: e320_clocking.v +// +// Purpose: +// +// TODO: First, instantiate clock input buffers on all clocks to provide termination +// for the PCB traces. +// +// Second, PPS inputs from the back panel (called external) and the GPSDO are captured by +// the Reference Clock. Selection is performed amongst these and the internally-generated +// options. +// +////////////////////////////////////////////////////////////////////// + +module e320_clocking ( + input global_rst, + + // Reference Clk + input ref_clk_from_pin, + output ref_clk, + + // Input clocks + input clk156, // 156.25 MHz + + // Output clocks + output ddr3_dma_clk, + output reg clocks_locked = 1'b0, + + // PPS Capture & Selection + input ext_pps_from_pin, + input gps_pps_from_pin, + input [1:0] pps_select, + output reg pps_refclk +); + + //TODO: Code is same as n3xx, try reusing it. + + // Clock Buffering and Generation : /////////////////////////////////////////////////// + // + // Manually instantiate input buffers on all clocks, and a global buffer on the + // Reference Clock for use in the rest of the design. All other clocks must have + // global buffers other places, since the declarations here are for SI purposes. + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire ref_clk_buf; + + // FPGA Reference Clock Buffering + // + // Only require an IBUF and BUFG here, since an MMCM is (thankfully) not needed + // to meet timing with the PPS signal. + IBUFG ref_clk_ibuf ( + .O(ref_clk_buf), + .I(ref_clk_from_pin) + ); + + BUFG ref_clk_bufg ( + .I(ref_clk_buf), + .O(ref_clk) + ); + + wire pps_ext_refclk; + wire pps_gps_refclk; + wire [1:0] pps_select_refclk; + + // Capture the external PPSs with a FF before sending them to the mux. To be safe, + // we double-synchronize the external signals. If we meet timing (which we should) + // then this is a two-cycle delay. If we don't meet timing, then it's 1-2 cycles + // and our system timing is thrown off--but at least our downstream logic doesn't + // go metastable! + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) ext_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk) + ); + // Same deal with the GPSDO PPS input. Double-sync, then use it. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) gps_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk) + ); + + // Synchronize the select bits over to the reference clock as well. Note that this is + // a vector, so we could have some non-one-hot values creep through when changing. + // See the note below as to why this is safe. + synchronizer #( + .FALSE_PATH_TO_IN(1), + .WIDTH(2) + ) pps_select_dsync ( + .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk) + ); + + // Bit locations for the pps_select vector. + localparam BIT_PPS_SEL_INT = 0; + localparam BIT_PPS_SEL_EXT = 1; + + // PPS MUX - selects internal/gpsdo or external PPS. + always @(posedge ref_clk) begin + + // Encoding is one-hot on these bits. It is possible when the vector is being double- + // synchronized to the reference clock domain that there could be multiple bits + // asserted simultaneously. This is not problematic because the order of operations + // in the following selection mux should take over and only one PPS should win. + // This could result in glitches, but that is expected during ANY PPS switchover + // since the switch is performed asynchronously to the PPS signal. + if (pps_select_refclk[BIT_PPS_SEL_INT]) begin + pps_refclk <= pps_gps_refclk; + end else if (pps_select_refclk[BIT_PPS_SEL_EXT]) begin + pps_refclk <= pps_ext_refclk; + end else begin + pps_refclk <= pps_gps_refclk; + end + end + + //--------------------------------------------------------------------------- + // Clock Generation + //--------------------------------------------------------------------------- + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (6.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (3.125), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (6.400)) + mmcm_adv_inst ( + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (ddr3_dma_clk_raw), + .CLKOUT0B (), + .CLKOUT1 (), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (clk156), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (locked_raw), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (global_rst)); + + BUFG clk300_bufg + (.O (ddr3_dma_clk), + .I (ddr3_dma_clk_raw)); + + + //--------------------------------------------------------------------------- + // Lock Signal + //--------------------------------------------------------------------------- + // + // We assume that the LOCKED signal from the MMCM is not necessarily a clean + // asynchronous signal, so we want to make sure that the MMCM is really + // locked before we assert our clocks_locked output. + // + //--------------------------------------------------------------------------- + + reg [9:0] locked_count = ~0; + + synchronizer lock_sync_i ( + .clk(clk156), .rst(1'b0), .in(locked_raw), .out(locked_sync) + ); + + // Filter the locked signal + always @(posedge clk156 or posedge global_rst) + begin + if (global_rst) begin + locked_count <= ~0; + clocks_locked <= 0; + end else begin + if (~locked_sync) begin + locked_count <= ~0; + clocks_locked <= 1'b0; + end else begin + if (locked_count == 0) begin + clocks_locked <= 1'b1; + end else begin + clocks_locked <= 1'b0; + locked_count <= locked_count - 1; + end + end + end + end + +endmodule diff --git a/fpga/usrp3/top/e320/e320_core.v b/fpga/usrp3/top/e320/e320_core.v new file mode 100644 index 000000000..f8fccecc0 --- /dev/null +++ b/fpga/usrp3/top/e320/e320_core.v @@ -0,0 +1,1103 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: e320_core +// Description: +// - Motherboard Registers +// - DRAM Interconnect +// - Radio Front End control +// - Timekeeper +// - RFNoC Image Core +// +///////////////////////////////////////////////////////////////////// + +`default_nettype none +module e320_core #( + parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) + parameter REG_AWIDTH = 32, // Width of the address bus + parameter BUS_CLK_RATE = 200000000, // bus_clk rate + parameter NUM_RADIOS = 1, + parameter NUM_CHANNELS = 2, + parameter NUM_DBOARDS = 1, + parameter NUM_CHANNELS_PER_DBOARD = 2, + parameter FP_GPIO_WIDTH = 8, // Front panel GPIO width + parameter DB_GPIO_WIDTH = 16, // Daughterboard GPIO width + parameter CHDR_WIDTH = 16'd64 , + parameter RFNOC_PROTOVER = {8'd1, 8'd0} +)( + // Clocks and resets + input wire radio_clk, + input wire radio_rst, + input wire bus_clk, + input wire bus_rst, + input wire ddr3_dma_clk, + input wire clk40, + + // Motherboard Registers: AXI lite interface + input wire s_axi_aclk, + input wire s_axi_aresetn, + input wire [REG_AWIDTH-1:0] s_axi_awaddr, + input wire s_axi_awvalid, + output wire s_axi_awready, + + input wire [REG_DWIDTH-1:0] s_axi_wdata, + input wire [REG_DWIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wvalid, + output wire s_axi_wready, + + output wire [1:0] s_axi_bresp, + output wire s_axi_bvalid, + input wire s_axi_bready, + + input wire [REG_AWIDTH-1:0] s_axi_araddr, + input wire s_axi_arvalid, + output wire s_axi_arready, + + output wire [REG_DWIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + output wire s_axi_rvalid, + input wire s_axi_rready, + + // PPS and Clock Control + input wire pps_refclk, + input wire refclk_locked, + output reg [1:0] pps_select, + output reg ref_select, + + // PS GPIO source + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_out, + input wire [FP_GPIO_WIDTH-1:0] ps_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] ps_gpio_in, + + // Front Panel GPIO + input wire [FP_GPIO_WIDTH-1:0] fp_gpio_in, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_tri, + output wire [FP_GPIO_WIDTH-1:0] fp_gpio_out, + + // Radio GPIO control + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_out_flat, + output wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_ddr_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_in_flat, + input wire [DB_GPIO_WIDTH*NUM_CHANNELS-1:0] db_gpio_fab_flat, + + // TX/RX LEDs + output wire [32*NUM_CHANNELS-1:0] leds_flat, + + // Radio ATR + output wire [NUM_CHANNELS-1:0] rx_atr, + output wire [NUM_CHANNELS-1:0] tx_atr, + + // Radio Data + input wire [NUM_CHANNELS-1:0] rx_stb, + input wire [NUM_CHANNELS-1:0] tx_stb, + input wire [32*NUM_CHANNELS-1:0] rx, + output wire [32*NUM_CHANNELS-1:0] tx, + + // AXI4 DDR3 Interface + input wire ddr3_axi_clk, + input wire ddr3_axi_rst, + input wire ddr3_running, + // Write Address Ports + output wire [3:0] ddr3_axi_awid, + output wire [31:0] ddr3_axi_awaddr, + output wire [7:0] ddr3_axi_awlen, + output wire [2:0] ddr3_axi_awsize, + output wire [1:0] ddr3_axi_awburst, + output wire [0:0] ddr3_axi_awlock, + output wire [3:0] ddr3_axi_awcache, + output wire [2:0] ddr3_axi_awprot, + output wire [3:0] ddr3_axi_awqos, + output wire ddr3_axi_awvalid, + input wire ddr3_axi_awready, + // Write Data Ports + output wire [255:0] ddr3_axi_wdata, + output wire [31:0] ddr3_axi_wstrb, + output wire ddr3_axi_wlast, + output wire ddr3_axi_wvalid, + input wire ddr3_axi_wready, + // Write Response Ports + output wire ddr3_axi_bready, + input wire [3:0] ddr3_axi_bid, + input wire [1:0] ddr3_axi_bresp, + input wire ddr3_axi_bvalid, + // Read Address Ports + output wire [3:0] ddr3_axi_arid, + output wire [31:0] ddr3_axi_araddr, + output wire [7:0] ddr3_axi_arlen, + output wire [2:0] ddr3_axi_arsize, + output wire [1:0] ddr3_axi_arburst, + output wire [0:0] ddr3_axi_arlock, + output wire [3:0] ddr3_axi_arcache, + output wire [2:0] ddr3_axi_arprot, + output wire [3:0] ddr3_axi_arqos, + output wire ddr3_axi_arvalid, + input wire ddr3_axi_arready, + // Read Data Ports + output wire ddr3_axi_rready, + input wire [3:0] ddr3_axi_rid, + input wire [255:0] ddr3_axi_rdata, + input wire [1:0] ddr3_axi_rresp, + input wire ddr3_axi_rlast, + input wire ddr3_axi_rvalid, + + + + // DMA xport adapter to PS + input wire [63:0] s_dma_tdata, + input wire [3:0] s_dma_tuser, + input wire s_dma_tlast, + output wire s_dma_tready, + input wire s_dma_tvalid, + + output wire [63:0] m_dma_tdata, + output wire [3:0] m_dma_tdest, + output wire m_dma_tlast, + input wire m_dma_tready, + output wire m_dma_tvalid, + + // e2v (Ethernet to Vita) and v2e (Vita to Ethernet) + output wire [63:0] v2e_tdata, + output wire v2e_tvalid, + output wire v2e_tlast, + input wire v2e_tready, + + input wire [63:0] e2v_tdata, + input wire e2v_tlast, + input wire e2v_tvalid, + output wire e2v_tready, + + // Misc + input wire [31:0] build_datestamp, + input wire [31:0] sfp_ports_info, + input wire [31:0] gps_status, + output reg [31:0] gps_ctrl, + input wire [31:0] dboard_status, + input wire [31:0] xadc_readback, + output reg [31:0] fp_gpio_ctrl, + output reg [31:0] dboard_ctrl, + output reg [15:0] device_id +); + + ///////////////////////////////////////////////////////////////////////////////// + // + // FPGA Compatibility Number + // Rules for modifying compat number: + // - Major is updated when the FPGA is changed and requires a software + // change as a result. + // - Minor is updated when a new feature is added to the FPGA that does not + // break software compatibility. + // + ///////////////////////////////////////////////////////////////////////////////// + + localparam [15:0] COMPAT_MAJOR = 16'd5; + localparam [15:0] COMPAT_MINOR = 16'd0; + + ///////////////////////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////////////////////// + // + // Motherboard Registers + // + ///////////////////////////////////////////////////////////////////////////////// + + // Register base + localparam REG_BASE_MISC = 14'h0; + localparam REG_BASE_TIMEKEEPER = 14'h1000; + + // Misc Registers + localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; + localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; + localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; + localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; + localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; + localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; + localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; + localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; + localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; + localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; + localparam REG_SFP_PORT_INFO = REG_BASE_MISC + 14'h28; + localparam REG_FP_GPIO_CTRL = REG_BASE_MISC + 14'h2C; + localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; + localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; + localparam REG_GPS_CTRL = REG_BASE_MISC + 14'h38; + localparam REG_GPS_STATUS = REG_BASE_MISC + 14'h3C; + localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40; + localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44; + localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + + localparam NUM_TIMEKEEPERS = 16'd1; + + wire m_ctrlport_req_wr; + wire m_ctrlport_req_rd; + wire [19:0] m_ctrlport_req_addr; + wire [31:0] m_ctrlport_req_data; + wire m_ctrlport_req_has_time; + wire [63:0] m_ctrlport_req_time; + wire m_ctrlport_resp_ack; + wire [31:0] m_ctrlport_resp_data; + + reg [31:0] fp_gpio_master_reg = 32'h0; + reg [31:0] fp_gpio_src_reg = 32'h0; + + wire reg_wr_req; + wire [REG_AWIDTH-1:0] reg_wr_addr; + wire [REG_DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [REG_DWIDTH-1:0] reg_rd_data; + + reg reg_rd_resp_glob; + reg [REG_DWIDTH-1:0] reg_rd_data_glob; + wire reg_rd_resp_tk; + wire [REG_DWIDTH-1:0] reg_rd_data_tk; + + reg [31:0] scratch_reg = 32'h0; + reg [31:0] bus_counter = 32'h0; + + always @(posedge bus_clk) begin + if (bus_rst) + bus_counter <= 32'd0; + else + bus_counter <= bus_counter + 32'd1; + end + + // Regport Master to convert AXI4-Lite to regport + axil_regport_master #( + .DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (REG_AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) core_regport_master_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_wr_keep (/*unused*/), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + //-------------------------------------------------------------------- + // Global Registers + // ------------------------------------------------------------------- + + // Write Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + scratch_reg <= 32'h0; + pps_select <= 2'b01; // Default to internal + ref_select <= 1'b0; // Default to internal + fp_gpio_ctrl <= 32'h9; // Default to OFF - 4'b1001 + gps_ctrl <= 32'h3; // Default to gps_en, out of reset + dboard_ctrl <= 32'h1; // Default to mimo + device_id <= 16'h0; + end else if (reg_wr_req) begin + case (reg_wr_addr) + REG_DEVICE_ID: begin + device_id <= reg_wr_data[15:0]; + end + REG_FP_GPIO_MASTER: begin + fp_gpio_master_reg <= reg_wr_data; + end + REG_FP_GPIO_RADIO_SRC: begin + fp_gpio_src_reg <= reg_wr_data; + end + REG_SCRATCH: begin + scratch_reg <= reg_wr_data; + end + REG_CLOCK_CTRL: begin + pps_select <= reg_wr_data[1:0]; + ref_select <= reg_wr_data[2]; + end + REG_FP_GPIO_CTRL: begin + fp_gpio_ctrl <= reg_wr_data; + end + REG_GPS_CTRL: begin + gps_ctrl <= reg_wr_data; + end + REG_DBOARD_CTRL: begin + dboard_ctrl <= reg_wr_data; + end + endcase + end + end + + // Read Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + reg_rd_resp_glob <= 1'b0; + end + else begin + + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + + case (reg_rd_addr) + REG_DEVICE_ID: + reg_rd_data_glob <= device_id; + + REG_RFNOC_INFO: + reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + + REG_COMPAT_NUM: + reg_rd_data_glob <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]}; + + REG_FP_GPIO_CTRL: + reg_rd_data_glob <= fp_gpio_ctrl; + + REG_FP_GPIO_MASTER: + reg_rd_data_glob <= fp_gpio_master_reg; + + REG_FP_GPIO_RADIO_SRC: + reg_rd_data_glob <= fp_gpio_src_reg; + + REG_DATESTAMP: + reg_rd_data_glob <= build_datestamp; + + REG_GIT_HASH: + `ifndef GIT_HASH + `define GIT_HASH 32'h0BADC0DE + `endif + reg_rd_data_glob <= `GIT_HASH; + + REG_SCRATCH: + reg_rd_data_glob <= scratch_reg; + + REG_CLOCK_CTRL: begin + reg_rd_data_glob <= 32'b0; + reg_rd_data_glob[1:0] <= pps_select; + reg_rd_data_glob[2] <= ref_select; + reg_rd_data_glob[3] <= refclk_locked; + end + + REG_XADC_READBACK: + reg_rd_data_glob <= xadc_readback; + + REG_BUS_CLK_RATE: + reg_rd_data_glob <= BUS_CLK_RATE; + + REG_BUS_CLK_COUNT: + reg_rd_data_glob <= bus_counter; + + REG_SFP_PORT_INFO: + reg_rd_data_glob <= sfp_ports_info; + + REG_GPS_CTRL: + reg_rd_data_glob <= gps_ctrl; + + REG_GPS_STATUS: + reg_rd_data_glob <= gps_status; + + REG_DBOARD_CTRL: + reg_rd_data_glob <= dboard_ctrl; + + REG_DBOARD_STATUS: + reg_rd_data_glob <= dboard_status; + + REG_NUM_TIMEKEEPERS: + reg_rd_data_glob <= NUM_TIMEKEEPERS; + + default: + reg_rd_resp_glob <= 1'b0; + endcase + end + else if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + end + + wire pps_radioclk; + + // Synchronize the PPS signal to the radio clock domain + synchronizer pps_radio_sync ( + .clk(radio_clk), .rst(1'b0), .in(pps_refclk), .out(pps_radioclk) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // DRAM + // + ///////////////////////////////////////////////////////////////////////////// + + localparam NUM_DRAM_FIFOS = 2; + + wire ddr3_dma_rst; + + synchronizer #( + .INITIAL_VAL(1'b1) + ) ddr3_dma_rst_sync_i ( + .clk(ddr3_dma_clk), .rst(1'b0), .in(ddr3_axi_rst), .out(ddr3_dma_rst) + ); + + // AXI4 MM buses + wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awready [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_wdata [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_wstrb [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_wuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_bid [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_bresp [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_buser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_aruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_rid [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_rdata [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_rresp [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_ruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rready [0:NUM_DRAM_FIFOS-1]; + + axi_intercon_4x64_256_bd_wrapper axi_intercon_2x64_256_bd_i ( + .S00_AXI_ACLK (ddr3_dma_clk ), + .S00_AXI_ARESETN (~ddr3_dma_rst ), + .S00_AXI_AWID (dram_axi_awid [0]), + .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWLEN (dram_axi_awlen [0]), + .S00_AXI_AWSIZE (dram_axi_awsize [0]), + .S00_AXI_AWBURST (dram_axi_awburst [0]), + .S00_AXI_AWLOCK (dram_axi_awlock [0]), + .S00_AXI_AWCACHE (dram_axi_awcache [0]), + .S00_AXI_AWPROT (dram_axi_awprot [0]), + .S00_AXI_AWQOS (dram_axi_awqos [0]), + .S00_AXI_AWREGION (dram_axi_awregion[0]), + .S00_AXI_AWVALID (dram_axi_awvalid [0]), + .S00_AXI_AWREADY (dram_axi_awready [0]), + .S00_AXI_WDATA (dram_axi_wdata [0]), + .S00_AXI_WSTRB (dram_axi_wstrb [0]), + .S00_AXI_WLAST (dram_axi_wlast [0]), + .S00_AXI_WVALID (dram_axi_wvalid [0]), + .S00_AXI_WREADY (dram_axi_wready [0]), + .S00_AXI_BID (dram_axi_bid [0]), + .S00_AXI_BRESP (dram_axi_bresp [0]), + .S00_AXI_BVALID (dram_axi_bvalid [0]), + .S00_AXI_BREADY (dram_axi_bready [0]), + .S00_AXI_ARID (dram_axi_arid [0]), + .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARLEN (dram_axi_arlen [0]), + .S00_AXI_ARSIZE (dram_axi_arsize [0]), + .S00_AXI_ARBURST (dram_axi_arburst [0]), + .S00_AXI_ARLOCK (dram_axi_arlock [0]), + .S00_AXI_ARCACHE (dram_axi_arcache [0]), + .S00_AXI_ARPROT (dram_axi_arprot [0]), + .S00_AXI_ARQOS (dram_axi_arqos [0]), + .S00_AXI_ARREGION (dram_axi_arregion[0]), + .S00_AXI_ARVALID (dram_axi_arvalid [0]), + .S00_AXI_ARREADY (dram_axi_arready [0]), + .S00_AXI_RID (dram_axi_rid [0]), + .S00_AXI_RDATA (dram_axi_rdata [0]), + .S00_AXI_RRESP (dram_axi_rresp [0]), + .S00_AXI_RLAST (dram_axi_rlast [0]), + .S00_AXI_RVALID (dram_axi_rvalid [0]), + .S00_AXI_RREADY (dram_axi_rready [0]), + // + .S01_AXI_ACLK (ddr3_dma_clk ), + .S01_AXI_ARESETN (~ddr3_dma_rst ), + .S01_AXI_AWID (dram_axi_awid [1]), + .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWLEN (dram_axi_awlen [1]), + .S01_AXI_AWSIZE (dram_axi_awsize [1]), + .S01_AXI_AWBURST (dram_axi_awburst [1]), + .S01_AXI_AWLOCK (dram_axi_awlock [1]), + .S01_AXI_AWCACHE (dram_axi_awcache [1]), + .S01_AXI_AWPROT (dram_axi_awprot [1]), + .S01_AXI_AWQOS (dram_axi_awqos [1]), + .S01_AXI_AWREGION (dram_axi_awregion[1]), + .S01_AXI_AWVALID (dram_axi_awvalid [1]), + .S01_AXI_AWREADY (dram_axi_awready [1]), + .S01_AXI_WDATA (dram_axi_wdata [1]), + .S01_AXI_WSTRB (dram_axi_wstrb [1]), + .S01_AXI_WLAST (dram_axi_wlast [1]), + .S01_AXI_WVALID (dram_axi_wvalid [1]), + .S01_AXI_WREADY (dram_axi_wready [1]), + .S01_AXI_BID (dram_axi_bid [1]), + .S01_AXI_BRESP (dram_axi_bresp [1]), + .S01_AXI_BVALID (dram_axi_bvalid [1]), + .S01_AXI_BREADY (dram_axi_bready [1]), + .S01_AXI_ARID (dram_axi_arid [1]), + .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARLEN (dram_axi_arlen [1]), + .S01_AXI_ARSIZE (dram_axi_arsize [1]), + .S01_AXI_ARBURST (dram_axi_arburst [1]), + .S01_AXI_ARLOCK (dram_axi_arlock [1]), + .S01_AXI_ARCACHE (dram_axi_arcache [1]), + .S01_AXI_ARPROT (dram_axi_arprot [1]), + .S01_AXI_ARQOS (dram_axi_arqos [1]), + .S01_AXI_ARREGION (dram_axi_arregion[1]), + .S01_AXI_ARVALID (dram_axi_arvalid [1]), + .S01_AXI_ARREADY (dram_axi_arready [1]), + .S01_AXI_RID (dram_axi_rid [1]), + .S01_AXI_RDATA (dram_axi_rdata [1]), + .S01_AXI_RRESP (dram_axi_rresp [1]), + .S01_AXI_RLAST (dram_axi_rlast [1]), + .S01_AXI_RVALID (dram_axi_rvalid [1]), + .S01_AXI_RREADY (dram_axi_rready [1]), + // + .S02_AXI_ACLK (ddr3_dma_clk ), + .S02_AXI_ARESETN (~ddr3_dma_rst ), + .S02_AXI_AWID (dram_axi_awid [2]), + .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWLEN (dram_axi_awlen [2]), + .S02_AXI_AWSIZE (dram_axi_awsize [2]), + .S02_AXI_AWBURST (dram_axi_awburst [2]), + .S02_AXI_AWLOCK (dram_axi_awlock [2]), + .S02_AXI_AWCACHE (dram_axi_awcache [2]), + .S02_AXI_AWPROT (dram_axi_awprot [2]), + .S02_AXI_AWQOS (dram_axi_awqos [2]), + .S02_AXI_AWREGION (dram_axi_awregion[2]), + .S02_AXI_AWVALID (dram_axi_awvalid [2]), + .S02_AXI_AWREADY (dram_axi_awready [2]), + .S02_AXI_WDATA (dram_axi_wdata [2]), + .S02_AXI_WSTRB (dram_axi_wstrb [2]), + .S02_AXI_WLAST (dram_axi_wlast [2]), + .S02_AXI_WVALID (dram_axi_wvalid [2]), + .S02_AXI_WREADY (dram_axi_wready [2]), + .S02_AXI_BID (dram_axi_bid [2]), + .S02_AXI_BRESP (dram_axi_bresp [2]), + .S02_AXI_BVALID (dram_axi_bvalid [2]), + .S02_AXI_BREADY (dram_axi_bready [2]), + .S02_AXI_ARID (dram_axi_arid [2]), + .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARLEN (dram_axi_arlen [2]), + .S02_AXI_ARSIZE (dram_axi_arsize [2]), + .S02_AXI_ARBURST (dram_axi_arburst [2]), + .S02_AXI_ARLOCK (dram_axi_arlock [2]), + .S02_AXI_ARCACHE (dram_axi_arcache [2]), + .S02_AXI_ARPROT (dram_axi_arprot [2]), + .S02_AXI_ARQOS (dram_axi_arqos [2]), + .S02_AXI_ARREGION (dram_axi_arregion[2]), + .S02_AXI_ARVALID (dram_axi_arvalid [2]), + .S02_AXI_ARREADY (dram_axi_arready [2]), + .S02_AXI_RID (dram_axi_rid [2]), + .S02_AXI_RDATA (dram_axi_rdata [2]), + .S02_AXI_RRESP (dram_axi_rresp [2]), + .S02_AXI_RLAST (dram_axi_rlast [2]), + .S02_AXI_RVALID (dram_axi_rvalid [2]), + .S02_AXI_RREADY (dram_axi_rready [2]), + // + .S03_AXI_ACLK (ddr3_dma_clk ), + .S03_AXI_ARESETN (~ddr3_dma_rst ), + .S03_AXI_AWID (dram_axi_awid [3]), + .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWLEN (dram_axi_awlen [3]), + .S03_AXI_AWSIZE (dram_axi_awsize [3]), + .S03_AXI_AWBURST (dram_axi_awburst [3]), + .S03_AXI_AWLOCK (dram_axi_awlock [3]), + .S03_AXI_AWCACHE (dram_axi_awcache [3]), + .S03_AXI_AWPROT (dram_axi_awprot [3]), + .S03_AXI_AWQOS (dram_axi_awqos [3]), + .S03_AXI_AWREGION (dram_axi_awregion[3]), + .S03_AXI_AWVALID (dram_axi_awvalid [3]), + .S03_AXI_AWREADY (dram_axi_awready [3]), + .S03_AXI_WDATA (dram_axi_wdata [3]), + .S03_AXI_WSTRB (dram_axi_wstrb [3]), + .S03_AXI_WLAST (dram_axi_wlast [3]), + .S03_AXI_WVALID (dram_axi_wvalid [3]), + .S03_AXI_WREADY (dram_axi_wready [3]), + .S03_AXI_BID (dram_axi_bid [3]), + .S03_AXI_BRESP (dram_axi_bresp [3]), + .S03_AXI_BVALID (dram_axi_bvalid [3]), + .S03_AXI_BREADY (dram_axi_bready [3]), + .S03_AXI_ARID (dram_axi_arid [3]), + .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARLEN (dram_axi_arlen [3]), + .S03_AXI_ARSIZE (dram_axi_arsize [3]), + .S03_AXI_ARBURST (dram_axi_arburst [3]), + .S03_AXI_ARLOCK (dram_axi_arlock [3]), + .S03_AXI_ARCACHE (dram_axi_arcache [3]), + .S03_AXI_ARPROT (dram_axi_arprot [3]), + .S03_AXI_ARQOS (dram_axi_arqos [3]), + .S03_AXI_ARREGION (dram_axi_arregion[3]), + .S03_AXI_ARVALID (dram_axi_arvalid [3]), + .S03_AXI_ARREADY (dram_axi_arready [3]), + .S03_AXI_RID (dram_axi_rid [3]), + .S03_AXI_RDATA (dram_axi_rdata [3]), + .S03_AXI_RRESP (dram_axi_rresp [3]), + .S03_AXI_RLAST (dram_axi_rlast [3]), + .S03_AXI_RVALID (dram_axi_rvalid [3]), + .S03_AXI_RREADY (dram_axi_rready [3]), + // + .M00_AXI_ACLK (ddr3_axi_clk ), + .M00_AXI_ARESETN (~ddr3_axi_rst ), + .M00_AXI_AWID (ddr3_axi_awid ), + .M00_AXI_AWADDR (ddr3_axi_awaddr ), + .M00_AXI_AWLEN (ddr3_axi_awlen ), + .M00_AXI_AWSIZE (ddr3_axi_awsize ), + .M00_AXI_AWBURST (ddr3_axi_awburst ), + .M00_AXI_AWLOCK (ddr3_axi_awlock ), + .M00_AXI_AWCACHE (ddr3_axi_awcache ), + .M00_AXI_AWPROT (ddr3_axi_awprot ), + .M00_AXI_AWQOS (ddr3_axi_awqos ), + .M00_AXI_AWREGION ( ), + .M00_AXI_AWVALID (ddr3_axi_awvalid ), + .M00_AXI_AWREADY (ddr3_axi_awready ), + .M00_AXI_WDATA (ddr3_axi_wdata ), + .M00_AXI_WSTRB (ddr3_axi_wstrb ), + .M00_AXI_WLAST (ddr3_axi_wlast ), + .M00_AXI_WVALID (ddr3_axi_wvalid ), + .M00_AXI_WREADY (ddr3_axi_wready ), + .M00_AXI_BID (ddr3_axi_bid ), + .M00_AXI_BRESP (ddr3_axi_bresp ), + .M00_AXI_BVALID (ddr3_axi_bvalid ), + .M00_AXI_BREADY (ddr3_axi_bready ), + .M00_AXI_ARID (ddr3_axi_arid ), + .M00_AXI_ARADDR (ddr3_axi_araddr ), + .M00_AXI_ARLEN (ddr3_axi_arlen ), + .M00_AXI_ARSIZE (ddr3_axi_arsize ), + .M00_AXI_ARBURST (ddr3_axi_arburst ), + .M00_AXI_ARLOCK (ddr3_axi_arlock ), + .M00_AXI_ARCACHE (ddr3_axi_arcache ), + .M00_AXI_ARPROT (ddr3_axi_arprot ), + .M00_AXI_ARQOS (ddr3_axi_arqos ), + .M00_AXI_ARREGION ( ), + .M00_AXI_ARVALID (ddr3_axi_arvalid ), + .M00_AXI_ARREADY (ddr3_axi_arready ), + .M00_AXI_RID (ddr3_axi_rid ), + .M00_AXI_RDATA (ddr3_axi_rdata ), + .M00_AXI_RRESP (ddr3_axi_rresp ), + .M00_AXI_RLAST (ddr3_axi_rlast ), + .M00_AXI_RVALID (ddr3_axi_rvalid ), + .M00_AXI_RREADY (ddr3_axi_rready ) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // DMA Transport Adapter + // + ///////////////////////////////////////////////////////////////////////////// + wire [63:0] dmao_tdata; + wire dmao_tlast; + wire dmao_tvalid; + wire dmao_tready; + + wire [63:0] dmai_tdata; + wire dmai_tlast; + wire dmai_tvalid; + wire dmai_tready; + + liberio_chdr64_adapter #( + .DMA_ID_WIDTH (4) + ) dma_xport_adapter ( + .clk (bus_clk), + .rst (bus_rst), + .device_id (device_id), + // From DMA engine to core + .s_dma_tdata (s_dma_tdata), + .s_dma_tuser (s_dma_tuser), + .s_dma_tlast (s_dma_tlast), + .s_dma_tvalid (s_dma_tvalid), + .s_dma_tready (s_dma_tready), + // From core to DMA engine + .m_dma_tdata (m_dma_tdata), + .m_dma_tuser (m_dma_tdest), + .m_dma_tlast (m_dma_tlast), + .m_dma_tvalid (m_dma_tvalid), + .m_dma_tready (m_dma_tready), + // CHDR buses + .s_chdr_tdata (dmao_tdata), + .s_chdr_tlast (dmao_tlast), + .s_chdr_tvalid (dmao_tvalid), + .s_chdr_tready (dmao_tready), + .m_chdr_tdata (dmai_tdata), + .m_chdr_tlast (dmai_tlast), + .m_chdr_tvalid (dmai_tvalid), + .m_chdr_tready (dmai_tready) + ); + + ///////////////////////////////////////////////////////////////////////////// + // + // Radio Daughter board and Front End Control + // + ///////////////////////////////////////////////////////////////////////////// + + // Radio Daughter board GPIO + wire [DB_GPIO_WIDTH-1:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [DB_GPIO_WIDTH-1:0] db_gpio_fab[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; + wire [31:0] leds[0:NUM_CHANNELS-1]; + + // Daughter board I/O + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + wire [31:0] rx_int[0:NUM_CHANNELS-1], rx_data[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; + //wire rx_stb[0:NUM_CHANNELS-1], tx_stb[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; + wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; + wire db_fe_rb_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; + wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; + + wire [NUM_RADIOS-1:0] sync_out; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + assign rx_atr[i] = rx_running[i]; + assign tx_atr[i] = tx_running[i]; + end + endgenerate + + + //------------------------------------ + // Daughterboard Control + // ----------------------------------- + + localparam [7:0] SR_DB_BASE = 8'd160; + localparam [7:0] RB_DB_BASE = 8'd16; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_db_control + db_control #( + .USE_SPI_CLK(0), + .SR_BASE(SR_DB_BASE), + .RB_BASE(RB_DB_BASE) + ) db_control_i ( + .clk(radio_clk), .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), .rb_addr(db_fe_rb_addr[i]), .rb_data(db_fe_rb_data[i]), + .run_rx(rx_running[i]), .run_tx(tx_running[i]), + .misc_ins(32'h0), .misc_outs(), + .fp_gpio_in(radio_gpio_in[i]), .fp_gpio_out(radio_gpio_out[i]), .fp_gpio_ddr(radio_gpio_ddr[i]), .fp_gpio_fab(32'h0), + .db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_fab(), + .leds(leds[i]), + .spi_clk(1'b0), .spi_rst(1'b0), .sen(), .sclk(), .mosi(), .miso(1'b0) + ); + end + endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control + // Radio Data + assign rx_data[i] = rx[32*i+31:32*i]; + assign tx[32*i+31:32*i] = tx_data[i]; + // GPIO + assign db_gpio_out_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_out[i]; + assign db_gpio_ddr_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH] = db_gpio_ddr[i]; + assign db_gpio_in[i] = db_gpio_in_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + assign db_gpio_fab[i] = db_gpio_fab_flat[DB_GPIO_WIDTH*i +: DB_GPIO_WIDTH]; + // LEDs + assign leds_flat[32*i+31:32*i] = leds[i]; + end + endgenerate + + ///////////////////////////////////////////////////////////////////////////// + // + // Front-panel GPIO + // + ///////////////////////////////////////////////////////////////////////////// + + wire [FP_GPIO_WIDTH-1:0] radio_gpio_in_sync; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg = ~0; + + // Double-synchronize the inputs to the PS + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) ps_gpio_in_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in), .out(ps_gpio_in) + ); + + // Double-synchronize the inputs to the radio + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) radio_gpio_in_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in), .out(radio_gpio_in_sync) + ); + + // Map the double-synchronized inputs to all radio channels + generate + for (i=0; i + + xilinx.com + xci + unknown + 1.0 + + + aurora_64b66b_pcs_pma + + + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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undef + undef + undef + undef + undef + undef + undef + undef + undef + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 156.25 + undef + + 100000000 + 0 + 0.000 + + 0 + 0.000 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + false + BL7 + BL8 + none + BL7 + BL8 + none + BL7 + BL8 + none + BL7 + BL8 + none + BL7 + BL8 + none + X0Y0 + X0Y0 + 1 + QPLL + none + false + false + none + 8 + 1 + left + 1 + 4 + 1 + false + GTXQ0 + None + None + None + None + 1 + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + gtx + false + 78.125 + 4 + 10312.5 + false + IMM + 1 + 0 + 0 + 0 + 0 + true + 66 + 1 + 156250.0 + 2 + 1 + false + TX + true + 1 + right + false + true + false + axi4_stream + false + xc7z045 + ffg900 + -3 + 156.250 + X0Y0 + aurora_64b66b_pcs_pma + NONE + Duplex + 7 + 78.125 + AXI4_LITE + None + 1 + 20 + Streaming + true + false + None + false + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + X0Y0 + 1 + left + false + false + false + GTXQ0 + None + None + None + None + 1 + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + gtx + 78.125 + 10.3125 + LCPLL + none + none + none + none + 156.250 + 156.250 + 156.250 + none + X0Y0 + X0Y0 + right + false + true + false + 1 + aurora_64b66b_pcs_pma + 78.125 + 20 + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + 0 + false + false + Duplex + AXI4_LITE + None + Streaming + zynq + + + xc7z045 + ffg900 + VERILOG + + MIXED + -3 + + + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..39ed52f8c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..c3fc89749 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,370 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input init_clk, + output user_clk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock, gt_pll_lock_iclk, mmcm_locked, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // Clocking + //-------------------------------------------------------------- + + wire tx_out_clk, tx_out_clk_bufg; + wire sync_clk_i; + wire user_clk_i; + wire mmcm_fb_clk; + wire sync_clk; + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (tx_out_clk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (!gt_pll_lock) + ); + + // BUFG for the feedback clock. The feedback signal is phase aligned to the input + // and must come from the CLK0 or CLK2X output of the PLL. In this case, we use + // the CLK0 output. + BUFG txout_clock_net_i ( + .I(tx_out_clk), + .O(tx_out_clk_bufg) + ); + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i; + wire qpll_drprdy_out_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_out (gt_qpllrefclk_quad1_i), + .GT0_GTREFCLK0_COMMON_IN (refclk), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt_qplllock_i), + .GT0_QPLLRESET_IN (gt_to_common_qpllreset_i), + .GT0_QPLLLOCKDETCLK_IN (init_clk), + .GT0_QPLLREFCLKLOST_OUT (gt_qpllrefclklost_i), + //---------------------- Common DRP Ports ---------------------- + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; + + aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); + + endmodule diff --git a/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_4k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 9 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_4k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..2f6ec0d88 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_8k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 1kx36 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_8k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc b/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc new file mode 100644 index 000000000..658891469 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_eth_dma/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_SRCS = $(IP_BUILD_DIR)/axi_eth_dma/axi_eth_dma.xci + +IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ +axi_eth_dma.xci.out \ +) + +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci + $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci b/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci new file mode 100644 index 000000000..ec1df69ec --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_eth_dma/axi_eth_dma.xci @@ -0,0 +1,412 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_eth_dma + + + 0 + 0 + 1 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 256 + 2 + 1 + 1 + 0.000 + AXI4 + WRITE_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 10 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 125 + 0 + zynq + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 16 + 32 + 64 + 32 + 64 + 32 + 64 + 32 + 1 + 1 + 0 + 16 + 0 + 23 + 0 + 32 + 64 + axi_eth_dma + 32 + 125 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 64 + 64 + 64 + 0 + 16 + 1 + 1 + 0 + 16 + 64 + 0 + 23 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 20 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc new file mode 100644 index 000000000..2f5ba57c6 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v + +BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \ +axi_intercon_4x64_256_bd.bd.out \ +axi_intercon_4x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd new file mode 100644 index 000000000..eb6c30100 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd @@ -0,0 +1,2191 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd + 1.00.a + + + isTop + true + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 200000000 + + + + + + + + ID_WIDTH + 4 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_M00_ACLK + + + + + + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 350000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + + + S01_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 350000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + 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SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + + + CLK.M00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + M00_AXI_ACLK + + + + + + FREQ_HZ + 200000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_M00_ACLK + + + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_AXI_ARESETN + + + + + + + + + + RST.M00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + M00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S00_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + + + + 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ACTIVE_LOW + + + + + + + + + + CLK.S03_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S03_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S02_AXI:S03_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN + + + + + + + + + + RST.S03_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S03_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + S02_AXI_ACLK + + in + + + + S02_AXI_ARESETN + + in + + + + S03_AXI_ACLK + + in + + + + S03_AXI_ARESETN + + in + + + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S02_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S03_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd_imp + 1.00.a + + + m00_rs + + + axi_intercon_4x64_256_bd_m00_rs_0 + 4 + 1 + 1 + 1 + + + + s00_rs + + + axi_intercon_4x64_256_bd_s00_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_width_conv + + + axi_intercon_4x64_256_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_rs + + + axi_intercon_4x64_256_bd_s01_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_width_conv + + + axi_intercon_4x64_256_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_4x64_256_bd_xbar_0 + 4 + 1 + 2 + 256 + SAMD + 4 + 0 + 0x00000004 + 0x00000008 + 0x0000000c + 0x00000010 + 0x00000014 + 0x00000018 + 0x0000001c + 0x00000020 + 0x00000024 + 0x00000028 + 0x0000002c + 0x00000030 + 0x00000034 + 0x00000038 + 0x0000003c + + + + s01_rs_256 + + + axi_intercon_4x64_256_bd_s01_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_256 + + + axi_intercon_4x64_256_bd_s00_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs + + + axi_intercon_4x64_256_bd_s02_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s03_rs + + + axi_intercon_4x64_256_bd_s03_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_width_conv + + + axi_intercon_4x64_256_bd_s02_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_width_conv + + + axi_intercon_4x64_256_bd_s03_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_rs_256 + + + axi_intercon_4x64_256_bd_s03_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs_256 + + + axi_intercon_4x64_256_bd_s02_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + + + s00_rs_M_AXI + + + + + s01_rs_M_AXI + + + + + xbar_M00_AXI + + + + + s00_rs_256_M_AXI + + + + + s01_rs_256_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + s02_rs_M_AXI + + + + + s03_rs_M_AXI + + + + + s02_width_conv_M_AXI + + + + + s03_width_conv_M_AXI + + + + + s02_rs_256_M_AXI + + + + + s03_rs_256_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + S02_AXI_ACLK_1 + + + + + + S02_AXI_ARESETN_1 + + + + + + S03_AXI_ACLK_1 + + + + + + S03_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml new file mode 100644 index 000000000..217597784 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml @@ -0,0 +1,123 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v new file mode 100644 index 000000000..71e446f92 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v @@ -0,0 +1,419 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_4x64_256_bd_wrapper ( + input M00_AXI_ACLK, + input M00_AXI_ARESETN, + output [31:0]M00_AXI_ARADDR, + output [1:0]M00_AXI_ARBURST, + output [3:0]M00_AXI_ARCACHE, + output [3:0]M00_AXI_ARID, + output [7:0]M00_AXI_ARLEN, + output [0:0]M00_AXI_ARLOCK, + output [2:0]M00_AXI_ARPROT, + output [3:0]M00_AXI_ARQOS, + input M00_AXI_ARREADY, + output [3:0]M00_AXI_ARREGION, + output [2:0]M00_AXI_ARSIZE, + output M00_AXI_ARVALID, + output [31:0]M00_AXI_AWADDR, + output [1:0]M00_AXI_AWBURST, + output [3:0]M00_AXI_AWCACHE, + output [3:0]M00_AXI_AWID, + output [7:0]M00_AXI_AWLEN, + output [0:0]M00_AXI_AWLOCK, + output [2:0]M00_AXI_AWPROT, + output [3:0]M00_AXI_AWQOS, + input M00_AXI_AWREADY, + output [3:0]M00_AXI_AWREGION, + output [2:0]M00_AXI_AWSIZE, + output M00_AXI_AWVALID, + input [3:0]M00_AXI_BID, + output M00_AXI_BREADY, + input [1:0]M00_AXI_BRESP, + input M00_AXI_BVALID, + input [255:0]M00_AXI_RDATA, + input [3:0]M00_AXI_RID, + input M00_AXI_RLAST, + output M00_AXI_RREADY, + input [1:0]M00_AXI_RRESP, + input M00_AXI_RVALID, + output [255:0]M00_AXI_WDATA, + output M00_AXI_WLAST, + input M00_AXI_WREADY, + output [31:0]M00_AXI_WSTRB, + output M00_AXI_WVALID, + input S00_AXI_ACLK, + input S00_AXI_ARESETN, + input [31:0]S00_AXI_ARADDR, + input [1:0]S00_AXI_ARBURST, + input [3:0]S00_AXI_ARCACHE, + input [0:0]S00_AXI_ARID, + input [7:0]S00_AXI_ARLEN, + input [0:0]S00_AXI_ARLOCK, + input [2:0]S00_AXI_ARPROT, + input [3:0]S00_AXI_ARQOS, + output S00_AXI_ARREADY, + input [3:0]S00_AXI_ARREGION, + input [2:0]S00_AXI_ARSIZE, + input S00_AXI_ARVALID, + input [31:0]S00_AXI_AWADDR, + input [1:0]S00_AXI_AWBURST, + input [3:0]S00_AXI_AWCACHE, + input [0:0]S00_AXI_AWID, + input [7:0]S00_AXI_AWLEN, + input [0:0]S00_AXI_AWLOCK, + input [2:0]S00_AXI_AWPROT, + input [3:0]S00_AXI_AWQOS, + output S00_AXI_AWREADY, + input [3:0]S00_AXI_AWREGION, + input [2:0]S00_AXI_AWSIZE, + input S00_AXI_AWVALID, + output [0:0]S00_AXI_BID, + input S00_AXI_BREADY, + output [1:0]S00_AXI_BRESP, + output S00_AXI_BVALID, + output [63:0]S00_AXI_RDATA, + output [0:0]S00_AXI_RID, + output S00_AXI_RLAST, + input S00_AXI_RREADY, + output [1:0]S00_AXI_RRESP, + output S00_AXI_RVALID, + input [63:0]S00_AXI_WDATA, + input S00_AXI_WLAST, + output S00_AXI_WREADY, + input [7:0]S00_AXI_WSTRB, + input S00_AXI_WVALID, + input S01_AXI_ACLK, + input S01_AXI_ARESETN, + input [31:0]S01_AXI_ARADDR, + input [1:0]S01_AXI_ARBURST, + input [3:0]S01_AXI_ARCACHE, + input [0:0]S01_AXI_ARID, + input [7:0]S01_AXI_ARLEN, + input [0:0]S01_AXI_ARLOCK, + input [2:0]S01_AXI_ARPROT, + input [3:0]S01_AXI_ARQOS, + output S01_AXI_ARREADY, + input [3:0]S01_AXI_ARREGION, + input [2:0]S01_AXI_ARSIZE, + input S01_AXI_ARVALID, + input [31:0]S01_AXI_AWADDR, + input [1:0]S01_AXI_AWBURST, + input [3:0]S01_AXI_AWCACHE, + input [0:0]S01_AXI_AWID, + input [7:0]S01_AXI_AWLEN, + input [0:0]S01_AXI_AWLOCK, + input [2:0]S01_AXI_AWPROT, + input [3:0]S01_AXI_AWQOS, + output S01_AXI_AWREADY, + input [3:0]S01_AXI_AWREGION, + input [2:0]S01_AXI_AWSIZE, + input S01_AXI_AWVALID, + output [0:0]S01_AXI_BID, + input S01_AXI_BREADY, + output [1:0]S01_AXI_BRESP, + output S01_AXI_BVALID, + output [63:0]S01_AXI_RDATA, + output [0:0]S01_AXI_RID, + output S01_AXI_RLAST, + input S01_AXI_RREADY, + output [1:0]S01_AXI_RRESP, + output S01_AXI_RVALID, + input [63:0]S01_AXI_WDATA, + input S01_AXI_WLAST, + output S01_AXI_WREADY, + input [7:0]S01_AXI_WSTRB, + input S01_AXI_WVALID, + input S02_AXI_ACLK, + input S02_AXI_ARESETN, + input [31:0]S02_AXI_ARADDR, + input [1:0]S02_AXI_ARBURST, + input [3:0]S02_AXI_ARCACHE, + input [0:0]S02_AXI_ARID, + input [7:0]S02_AXI_ARLEN, + input [0:0]S02_AXI_ARLOCK, + input [2:0]S02_AXI_ARPROT, + input [3:0]S02_AXI_ARQOS, + output S02_AXI_ARREADY, + input [3:0]S02_AXI_ARREGION, + input [2:0]S02_AXI_ARSIZE, + input S02_AXI_ARVALID, + input [31:0]S02_AXI_AWADDR, + input [1:0]S02_AXI_AWBURST, + input [3:0]S02_AXI_AWCACHE, + input [0:0]S02_AXI_AWID, + input [7:0]S02_AXI_AWLEN, + input [0:0]S02_AXI_AWLOCK, + input [2:0]S02_AXI_AWPROT, + input [3:0]S02_AXI_AWQOS, + output S02_AXI_AWREADY, + input [3:0]S02_AXI_AWREGION, + input [2:0]S02_AXI_AWSIZE, + input S02_AXI_AWVALID, + output [0:0]S02_AXI_BID, + input S02_AXI_BREADY, + output [1:0]S02_AXI_BRESP, + output S02_AXI_BVALID, + output [63:0]S02_AXI_RDATA, + output [0:0]S02_AXI_RID, + output S02_AXI_RLAST, + input S02_AXI_RREADY, + output [1:0]S02_AXI_RRESP, + output S02_AXI_RVALID, + input [63:0]S02_AXI_WDATA, + input S02_AXI_WLAST, + output S02_AXI_WREADY, + input [7:0]S02_AXI_WSTRB, + input S02_AXI_WVALID, + input S03_AXI_ACLK, + input S03_AXI_ARESETN, + input [31:0]S03_AXI_ARADDR, + input [1:0]S03_AXI_ARBURST, + input [3:0]S03_AXI_ARCACHE, + input [0:0]S03_AXI_ARID, + input [7:0]S03_AXI_ARLEN, + input [0:0]S03_AXI_ARLOCK, + input [2:0]S03_AXI_ARPROT, + input [3:0]S03_AXI_ARQOS, + output S03_AXI_ARREADY, + input [3:0]S03_AXI_ARREGION, + input [2:0]S03_AXI_ARSIZE, + input S03_AXI_ARVALID, + input [31:0]S03_AXI_AWADDR, + input [1:0]S03_AXI_AWBURST, + input [3:0]S03_AXI_AWCACHE, + input [0:0]S03_AXI_AWID, + input [7:0]S03_AXI_AWLEN, + input [0:0]S03_AXI_AWLOCK, + input [2:0]S03_AXI_AWPROT, + input [3:0]S03_AXI_AWQOS, + output S03_AXI_AWREADY, + input [3:0]S03_AXI_AWREGION, + input [2:0]S03_AXI_AWSIZE, + input S03_AXI_AWVALID, + output [0:0]S03_AXI_BID, + input S03_AXI_BREADY, + output [1:0]S03_AXI_BRESP, + output S03_AXI_BVALID, + output [63:0]S03_AXI_RDATA, + output [0:0]S03_AXI_RID, + output S03_AXI_RLAST, + input S03_AXI_RREADY, + output [1:0]S03_AXI_RRESP, + output S03_AXI_RVALID, + input [63:0]S03_AXI_WDATA, + input S03_AXI_WLAST, + output S03_AXI_WREADY, + input [7:0]S03_AXI_WSTRB, + input S03_AXI_WVALID +); + + axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID), + .S02_AXI_ACLK(S02_AXI_ACLK), + .S02_AXI_ARESETN(S02_AXI_ARESETN), + .S02_AXI_araddr(S02_AXI_ARADDR), + .S02_AXI_arburst(S02_AXI_ARBURST), + .S02_AXI_arcache(S02_AXI_ARCACHE), + .S02_AXI_arid(S02_AXI_ARID), + .S02_AXI_arlen(S02_AXI_ARLEN), + .S02_AXI_arlock(S02_AXI_ARLOCK), + .S02_AXI_arprot(S02_AXI_ARPROT), + .S02_AXI_arqos(S02_AXI_ARQOS), + .S02_AXI_arready(S02_AXI_ARREADY), + .S02_AXI_arregion(S02_AXI_ARREGION), + .S02_AXI_arsize(S02_AXI_ARSIZE), + .S02_AXI_arvalid(S02_AXI_ARVALID), + .S02_AXI_awaddr(S02_AXI_AWADDR), + .S02_AXI_awburst(S02_AXI_AWBURST), + .S02_AXI_awcache(S02_AXI_AWCACHE), + .S02_AXI_awid(S02_AXI_AWID), + .S02_AXI_awlen(S02_AXI_AWLEN), + .S02_AXI_awlock(S02_AXI_AWLOCK), + .S02_AXI_awprot(S02_AXI_AWPROT), + .S02_AXI_awqos(S02_AXI_AWQOS), + .S02_AXI_awready(S02_AXI_AWREADY), + .S02_AXI_awregion(S02_AXI_AWREGION), + .S02_AXI_awsize(S02_AXI_AWSIZE), + .S02_AXI_awvalid(S02_AXI_AWVALID), + .S02_AXI_bid(S02_AXI_BID), + .S02_AXI_bready(S02_AXI_BREADY), + .S02_AXI_bresp(S02_AXI_BRESP), + .S02_AXI_bvalid(S02_AXI_BVALID), + .S02_AXI_rdata(S02_AXI_RDATA), + .S02_AXI_rid(S02_AXI_RID), + .S02_AXI_rlast(S02_AXI_RLAST), + .S02_AXI_rready(S02_AXI_RREADY), + .S02_AXI_rresp(S02_AXI_RRESP), + .S02_AXI_rvalid(S02_AXI_RVALID), + .S02_AXI_wdata(S02_AXI_WDATA), + .S02_AXI_wlast(S02_AXI_WLAST), + .S02_AXI_wready(S02_AXI_WREADY), + .S02_AXI_wstrb(S02_AXI_WSTRB), + .S02_AXI_wvalid(S02_AXI_WVALID), + .S03_AXI_ACLK(S03_AXI_ACLK), + .S03_AXI_ARESETN(S03_AXI_ARESETN), + .S03_AXI_araddr(S03_AXI_ARADDR), + .S03_AXI_arburst(S03_AXI_ARBURST), + .S03_AXI_arcache(S03_AXI_ARCACHE), + .S03_AXI_arid(S03_AXI_ARID), + .S03_AXI_arlen(S03_AXI_ARLEN), + .S03_AXI_arlock(S03_AXI_ARLOCK), + .S03_AXI_arprot(S03_AXI_ARPROT), + .S03_AXI_arqos(S03_AXI_ARQOS), + .S03_AXI_arready(S03_AXI_ARREADY), + .S03_AXI_arregion(S03_AXI_ARREGION), + .S03_AXI_arsize(S03_AXI_ARSIZE), + .S03_AXI_arvalid(S03_AXI_ARVALID), + .S03_AXI_awaddr(S03_AXI_AWADDR), + .S03_AXI_awburst(S03_AXI_AWBURST), + .S03_AXI_awcache(S03_AXI_AWCACHE), + .S03_AXI_awid(S03_AXI_AWID), + .S03_AXI_awlen(S03_AXI_AWLEN), + .S03_AXI_awlock(S03_AXI_AWLOCK), + .S03_AXI_awprot(S03_AXI_AWPROT), + .S03_AXI_awqos(S03_AXI_AWQOS), + .S03_AXI_awready(S03_AXI_AWREADY), + .S03_AXI_awregion(S03_AXI_AWREGION), + .S03_AXI_awsize(S03_AXI_AWSIZE), + .S03_AXI_awvalid(S03_AXI_AWVALID), + .S03_AXI_bid(S03_AXI_BID), + .S03_AXI_bready(S03_AXI_BREADY), + .S03_AXI_bresp(S03_AXI_BRESP), + .S03_AXI_bvalid(S03_AXI_BVALID), + .S03_AXI_rdata(S03_AXI_RDATA), + .S03_AXI_rid(S03_AXI_RID), + .S03_AXI_rlast(S03_AXI_RLAST), + .S03_AXI_rready(S03_AXI_RREADY), + .S03_AXI_rresp(S03_AXI_RRESP), + .S03_AXI_rvalid(S03_AXI_RVALID), + .S03_AXI_wdata(S03_AXI_WDATA), + .S03_AXI_wlast(S03_AXI_WLAST), + .S03_AXI_wready(S03_AXI_WREADY), + .S03_AXI_wstrb(S03_AXI_WSTRB), + .S03_AXI_wvalid(S03_AXI_WVALID) + ); +endmodule diff --git a/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..90b0be153 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..70d1ff5f1 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2648 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_32bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 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+ 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + TRUE + MT41K512M16XX-125 + 16 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 31 + 256 + 4 + 1 + + + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc b/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc new file mode 100644 index 000000000..23db0e8e8 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2018 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_E320_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/e320_ps_bd/, \ +e320_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E320_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/e320_ps_bd/, \ +e320_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_E320_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_E320_PS_BD_SRCS = $(IP_BUILD_DIR)/e320_ps_bd/e320_ps_bd/e320_ps_bd.bd + +BD_E320_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/e320_ps_bd/, \ +e320_ps_bd.bd.out \ +e320_ps_bd/e320_ps_bd_ooc.xdc \ +) + +$(IP_E320_PS_BD_SRCS) $(BD_E320_PS_BD_OUTS) $(IP_E320_PS_BDTCL_SRCS): $(IP_E320_PS_ORIG_SRCS) $(IP_E320_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,e320_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_E320_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf new file mode 100644 index 000000000..158c6caac --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.pdf @@ -0,0 +1,7164 @@ +%PDF-1.4 +1 0 obj +<< + /Title (first) + /Author (sugandha) + /Producer (Concept Engineering GmbH) + /Creator (Nlview 6.6.11 2017-06-12 bk=1.3860 VDI=40 GEI=35) + /CreationDate (D:20180320170927) +>> +endobj +2 0 obj +<< + /Type /Catalog + /Pages 3 0 R + /Outlines 7 0 R + /PageMode /UseThumbs + /ViewerPreferences << /DisplayDocTitle true >> +>> +endobj +4 0 obj +<< + /Type /Font + /Subtype /Type1 + /Name /F1 + /BaseFont /Helvetica + /Encoding /MacRomanEncoding +>> +endobj +5 0 obj +<< + /ExtGState 6 0 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0.000 rg +/GSa0 gs +1 0 0 1 1605 440 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS1_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 460 m +1580 453 l +1594 453 l +1601 460 l +1594 467 l +1580 467 l +h f +Q +1580 460 m +1580 453 l +1594 453 l +1601 460 l +1594 467 l +1580 467 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 460 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI0_SS2_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 200 m +-47 207 l +-61 207 l +-61 193 l +-47 193 l +h f +Q +-40 200 m +-47 207 l +-61 207 l +-61 193 l +-47 193 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 200 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.368 -4.308 Td +(SPI1_MISO_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 220 m +1580 213 l +1594 213 l +1601 220 l +1594 227 l +1580 227 l +h f +Q +1580 220 m +1580 213 l +1594 213 l +1601 220 l +1594 227 l +1580 227 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 220 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 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180 m +1580 173 l +1594 173 l +1601 180 l +1594 187 l +1580 187 l +h f +Q +1580 180 m +1580 173 l +1594 173 l +1601 180 l +1594 187 l +1580 187 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 180 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_MOSI_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 80 m +-47 87 l +-61 87 l +-61 73 l +-47 73 l +h f +Q +-40 80 m +-47 87 l +-61 87 l +-61 73 l +-47 73 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 80 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-74.04 -4.308 Td +(SPI1_SCLK_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 100 m +1580 93 l +1594 93 l +1601 100 l +1594 107 l +1580 107 l +h f +Q +1580 100 m +1580 93 l +1594 93 l +1601 100 l +1594 107 l +1580 107 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 100 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SCLK_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 120 m +1580 113 l +1594 113 l +1601 120 l +1594 127 l +1580 127 l +h f +Q +1580 120 m +1580 113 l +1594 113 l +1601 120 l +1594 127 l +1580 127 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SCLK_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 260 m +-47 267 l +-61 267 l +-61 253 l +-47 253 l +h f +Q +-40 260 m +-47 267 l +-61 267 l +-61 253 l +-47 253 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 260 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-58.704 -4.308 Td +(SPI1_SS_I) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 280 m +1580 273 l +1594 273 l +1601 280 l +1594 287 l +1580 287 l +h f +Q +1580 280 m +1580 273 l +1594 273 l +1601 280 l +1594 287 l +1580 287 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 280 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 340 m +1580 333 l +1594 333 l +1601 340 l +1594 347 l +1580 347 l +h f +Q +1580 340 m +1580 333 l +1594 333 l +1601 340 l +1594 347 l +1580 347 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 340 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS_T) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 300 m +1580 293 l +1594 293 l +1601 300 l +1594 307 l +1580 307 l +h f +Q +1580 300 m +1580 293 l +1594 293 l +1601 300 l +1594 307 l +1580 307 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 300 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS1_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 320 m +1580 313 l +1594 313 l +1601 320 l +1594 327 l +1580 327 l +h f +Q +1580 320 m +1580 313 l +1594 313 l +1601 320 l +1594 327 l +1580 327 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 320 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(SPI1_SS2_O) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 120 m +-47 127 l +-61 127 l +-61 113 l +-47 113 l +h f +Q +-40 120 m +-47 127 l +-61 127 l +-61 113 l +-47 113 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 120 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-102.72 -4.308 Td +(S_AXI_GP0_ACLK) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 380 m +-47 387 l +-61 387 l +-61 373 l +-47 373 l +h f +Q +-40 380 m +-47 387 l +-61 387 l +-61 373 l +-47 373 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 380 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-128.052 -4.308 Td +(S_AXI_GP0_ARESETN) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 160 m +-47 167 l +-61 167 l +-61 153 l +-47 153 l +h f +Q +3 w +0.165 0.369 0.435 RG +-40 160 m +-47 167 l +-61 167 l +-61 153 l +-47 153 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 160 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-64.032 -4.308 Td +(S_AXI_HP0) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 180 m +-47 187 l +-61 187 l +-61 173 l +-47 173 l +h f +Q +1 w +0.063 0.133 0.208 RG +-40 180 m +-47 187 l +-61 187 l +-61 173 l +-47 173 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 180 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-102.048 -4.308 Td +(S_AXI_HP0_ACLK) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 60 m +-47 67 l +-61 67 l +-61 53 l +-47 53 l +h f +Q +-40 60 m +-47 67 l +-61 67 l +-61 53 l +-47 53 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 60 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-127.38 -4.308 Td +(S_AXI_HP0_ARESETN) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 480 m +1580 473 l +1594 473 l +1601 480 l +1594 487 l +1580 487 l +h f +Q +3 w +0.165 0.369 0.435 RG +1580 480 m +1580 473 l +1594 473 l +1601 480 l +1594 487 l +1580 487 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 480 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(USBIND_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +247 32 m +453 32 l +453 32 l +456 33 l +458 34 l +459 36 l +460 39 l +460 39 l +460 261 l +460 261 l +459 264 l +458 266 l +456 267 l +453 268 l +453 268 l +247 268 l +247 268 l +244 267 l +242 266 l +241 264 l +240 261 l +240 261 l +240 39 l +240 39 l +241 36 l +242 34 l +244 33 l +h f +Q +q +1 0 0 1 360 150 cm +1 0 0 1 -7 -7 cm +14 0 0 -14 0 14 cm /Im0 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 30 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-57.03 2.484 Td +(axi_interconnect_hp0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 350 270 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-44.358 -8.616 Td +(AXI Interconnect) Tj +ET +Q +q +1 0 0 1 251 43 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 51 10 18 re +f +Q +q +1 0 0 1 249.5 60.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 60 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 141 10 18 re +f +Q +q +1 0 0 1 450.5 150.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 150 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 150 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 71 10 18 re +f +Q +q +1 0 0 1 249.5 80.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 80 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_AXI) Tj +ET +Q +0.000 0.000 0.000 RG +230 100 m +240 100 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ACLK) Tj +ET +Q +230 120 m +240 120 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ARESETN) Tj +ET +Q +230 140 m +240 140 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ACLK) Tj +ET +Q +230 160 m +240 160 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ARESETN) Tj +ET +Q +230 180 m +240 180 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ACLK) Tj +ET +Q +230 200 m +240 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ARESETN) Tj +ET +Q +230 220 m +240 220 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_ACLK) Tj +ET +Q +230 240 m +240 240 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S01_ARESETN) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +247 32 m +453 32 l +S +460 39 m +460.003 38.8889 460.003 38.7778 460 38.6667 c +459.908 34.8927 456.774 31.908 453 32 c +S +460 39 m +460 261 l +S +453 268 m +453.111 268.003 453.222 268.003 453.333 268 c +457.107 267.908 460.092 264.774 460 261 c +S +453 268 m +247 268 l +S +240 261 m +239.997 261.111 239.997 261.222 240 261.333 c +240.092 265.107 243.226 268.092 247 268 c +S +240 261 m +240 39 l +S +247 32 m +246.889 31.9973 246.778 31.9973 246.667 32 c +242.893 32.092 239.908 35.2261 240 39 c +S +q +0.929 0.965 0.996 rg +/GSa0 gs +247 312 m +453 312 l +453 312 l +456 313 l +458 314 l +459 316 l +460 319 l +460 319 l +460 721 l +460 721 l +459 724 l +458 726 l +456 727 l +453 728 l +453 728 l +247 728 l +247 728 l +244 727 l +242 726 l +241 724 l +240 721 l +240 721 l +240 319 l +240 319 l +241 316 l +242 314 l +244 313 l +h f +Q +q +1 0 0 1 360 520 cm +1 0 0 1 -7 -7 cm +14 0 0 -14 0 14 cm /Im0 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 310 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-50.358 2.484 Td +(axi_interconnect_0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 350 730 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-44.358 -8.616 Td +(AXI Interconnect) Tj +ET +Q +q +1 0 0 1 251 323 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +230 331 10 18 re +f +Q +q +1 0 0 1 249.5 340.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 235 340 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 257 340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 451 10 18 re +f +Q +q +1 0 0 1 450.5 460.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 460 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M00_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 471 10 18 re +f +Q +q +1 0 0 1 450.5 480.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 480 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M01_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 491 10 18 re +f +Q +q +1 0 0 1 450.5 500.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 500 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M02_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 511 10 18 re +f +Q +q +1 0 0 1 450.5 520.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 520 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M03_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 531 10 18 re +f +Q +q +1 0 0 1 450.5 540.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 540 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 540 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M04_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 551 10 18 re +f +Q +q +1 0 0 1 450.5 560.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 560 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 560 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M05_AXI) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +460 571 10 18 re +f +Q +q +1 0 0 1 450.5 580.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 465 580 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 443 580 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-41.13 -3.59 Td +(M06_AXI) Tj +ET +Q +3 w +0.000 0.000 0.000 RG +230 360 m +240 360 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ACLK) Tj +ET +Q +230 380 m +240 380 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(ARESETN) Tj +ET +Q +230 400 m +240 400 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ACLK) Tj +ET +Q +230 420 m +240 420 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S00_ARESETN) Tj +ET +Q +230 440 m +240 440 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 440 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ACLK) Tj +ET +Q +230 460 m +240 460 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M00_ARESETN) Tj +ET +Q +230 480 m +240 480 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M01_ACLK) Tj +ET +Q +230 500 m +240 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M01_ARESETN) Tj +ET +Q +230 520 m +240 520 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M02_ACLK) Tj +ET +Q +230 540 m +240 540 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 540 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M02_ARESETN) Tj +ET +Q +230 560 m +240 560 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 560 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M03_ACLK) Tj +ET +Q +230 580 m +240 580 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 580 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M03_ARESETN) Tj +ET +Q +230 600 m +240 600 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 600 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M04_ACLK) Tj +ET +Q +230 620 m +240 620 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 620 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M04_ARESETN) Tj +ET +Q +230 640 m +240 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M05_ACLK) Tj +ET +Q +230 660 m +240 660 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 660 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M05_ARESETN) Tj +ET +Q +230 680 m +240 680 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 680 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M06_ACLK) Tj +ET +Q +230 700 m +240 700 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 700 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M06_ARESETN) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +247 312 m +453 312 l +S +460 319 m +460.003 318.889 460.003 318.778 460 318.667 c +459.908 314.893 456.774 311.908 453 312 c +S +460 319 m +460 721 l +S +453 728 m +453.111 728.003 453.222 728.003 453.333 728 c +457.107 727.908 460.092 724.774 460 721 c +S +453 728 m +247 728 l +S +240 721 m +239.997 721.111 239.997 721.222 240 721.333 c +240.092 725.107 243.226 728.092 247 728 c +S +240 721 m +240 319 l +S +247 312 m +246.889 311.997 246.778 311.997 246.667 312 c +242.893 312.092 239.908 315.226 240 319 c +S +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 220 m +-47 227 l +-61 227 l +-61 213 l +-47 213 l +h f +Q +0.063 0.133 0.208 RG +-40 220 m +-47 227 l +-61 227 l +-61 213 l +-47 213 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 220 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-40.68 -4.308 Td +(bus_clk) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 240 m +-47 247 l +-61 247 l +-61 233 l +-47 233 l +h f +Q +-40 240 m +-47 247 l +-61 247 l +-61 233 l +-47 233 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 240 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-46.02 -4.308 Td +(bus_rstn) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 -50 m +-47 -43 l +-61 -43 l +-61 -57 l +-47 -57 l +h f +Q +-40 -50 m +-47 -43 l +-61 -43 l +-61 -57 l +-47 -57 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 -50 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-28.008 -4.308 Td +(clk40) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 280 m +-47 287 l +-61 287 l +-61 273 l +-47 273 l +h f +Q +-40 280 m +-47 287 l +-61 287 l +-61 273 l +-47 273 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 280 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-54.684 -4.308 Td +(clk40_rstn) Tj +ET +Q +q +0.667 0.769 0.969 rg +/GSa0 gs +207 772 m +493 772 l +493 772 l +496 773 l +498 774 l +499 776 l +500 779 l +500 779 l +500 981 l +500 981 l +499 984 l +498 986 l +496 987 l +493 988 l +493 988 l +207 988 l +207 988 l +204 987 l +202 986 l +201 984 l +200 981 l +200 981 l +200 779 l +200 779 l +201 776 l +202 774 l +204 773 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 350 770 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-11.67 2.484 Td +(dma) Tj +ET +Q +q +1 0 0 1 211 783 cm +1 0 0 1 -8 -8 cm +16 0 0 -16 0 16 cm /Im1 Do +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 831 10 18 re +f +Q +q +1 0 0 1 490.5 840.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 840 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 840 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-56.69 -3.59 Td +(o_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 851 10 18 re +f +Q +q +1 0 0 1 490.5 860.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 860 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 860 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-77.24 -3.59 Td +(M_AXI_RX_DMA) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +500 871 10 18 re +f +Q +q +1 0 0 1 490.5 880.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 505 880 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 483 880 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-76.13 -3.59 Td +(M_AXI_TX_DMA) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 791 10 18 re +f +Q +q +1 0 0 1 209.5 800.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 800 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 800 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(i_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 811 10 18 re +f +Q +q +1 0 0 1 209.5 820.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 820 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 820 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_rx_dmac) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 831 10 18 re +f +Q +q +1 0 0 1 209.5 840.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 840 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 840 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_tx_dmac) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 851 10 18 re +f +Q +q +1 0 0 1 209.5 860.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 860 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 860 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_regfile) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +190 871 10 18 re +f +Q +q +1 0 0 1 209.5 880.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 195 880 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 217 880 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(s_axi_dma_rx_mapper) Tj +ET +Q +3 w +0.000 0.000 0.000 RG +190 900 m +200 900 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 900 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(bus_clk) Tj +ET +Q +190 920 m +200 920 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 920 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(bus_rstn) Tj +ET +Q +190 940 m +200 940 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 940 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(clk40) Tj +ET +Q +190 960 m +200 960 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 202 960 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(clk40_rstn) Tj +ET +Q +510 900 m +500 900 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 900 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-25 -3.59 Td +(rx_irq) Tj +ET +Q +510 920 m +500 920 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 920 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-24.45 -3.59 Td +(tx_irq) Tj +ET +Q +1 w +0.255 0.380 0.624 RG +207 772 m +493 772 l +S +500 779 m +500.003 778.889 500.003 778.778 500 778.667 c +499.908 774.893 496.774 771.908 493 772 c +S +500 779 m +500 981 l +S +493 988 m +493.111 988.003 493.222 988.003 493.333 988 c +497.107 987.908 500.092 984.774 500 981 c +S +493 988 m +207 988 l +S +200 981 m +199.997 981.111 199.997 981.222 200 981.333 c +200.092 985.107 203.226 988.092 207 988 c +S +200 981 m +200 779 l +S +207 772 m +206.889 771.997 206.778 771.997 206.667 772 c +202.893 772.092 199.908 775.226 200 779 c +S +q +0.867 0.831 0.816 rg +/GSa0 gs +-40 300 m +-47 307 l +-61 307 l +-61 293 l +-47 293 l +h f +Q +3 w +0.165 0.369 0.435 RG +-40 300 m +-47 307 l +-61 307 l +-61 293 l +-47 293 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -65 300 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-64.02 -4.308 Td +(i_cvita_dma) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 500 m +1580 493 l +1594 493 l +1601 500 l +1594 507 l +1580 507 l +h f +Q +1580 500 m +1580 493 l +1594 493 l +1601 500 l +1594 507 l +1580 507 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 500 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_eth_dma) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 520 m +1580 513 l +1594 513 l +1601 520 l +1594 527 l +1580 527 l +h f +Q +1580 520 m +1580 513 l +1594 513 l +1601 520 l +1594 527 l +1580 527 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 520 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_net) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 540 m +1580 533 l +1594 533 l +1601 540 l +1594 547 l +1580 547 l +h f +Q +1580 540 m +1580 533 l +1594 533 l +1601 540 l +1594 547 l +1580 547 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 540 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(m_axi_xbar) Tj +ET +Q +q +0.867 0.831 0.816 rg +/GSa0 gs +1580 560 m +1580 553 l +1594 553 l +1601 560 l +1594 567 l +1580 567 l +h f +Q +1580 560 m +1580 553 l +1594 553 l +1601 560 l +1594 567 l +1580 567 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1605 560 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -4.308 Td +(o_cvita_dma) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +767 -440 m +1133 -440 l +1133 -440 l +1136 -439 l +1138 -438 l +1139 -436 l +1140 -433 l +1140 -433 l +1140 493 l +1140 493 l +1139 496 l +1138 498 l +1136 499 l +1133 500 l +1133 500 l +767 500 l +767 500 l +764 499 l +762 498 l +761 496 l +760 493 l +760 493 l +760 -433 l +760 -433 l +761 -436 l +762 -438 l +764 -439 l +h f +Q +q +1 0 0 1 975 30 cm +1 0 0 1 -50 -15 cm +100 0 0 -30 0 30 cm /Im7 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 950 -442 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-61.356 2.484 Td +(processing_system7_0) Tj +ET +Q +q +0.255 0.380 0.624 rg +/GSa0 gs +1 0 0 1 950 502 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-73.02 -8.616 Td +(ZYNQ7 Processing System) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -429 10 18 re +f +Q +q +1 0 0 1 1130.5 -419.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 -420 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-36.13 -3.59 Td +(GPIO_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -409 10 18 re +f +Q +q +1 0 0 1 1130.5 -399.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 -400 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-21.66 -3.59 Td +(DDR) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -389 10 138 re +f +Q +q +1 0 0 1 1130.5 -379.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 -380 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-45.57 -3.59 Td +(FIXED_IO) Tj +ET +Q +0.000 0.000 0.000 RG +1150 -360 m +1140 -360 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -365 m +1118 -360 l +1123 -355 l +1128 -360 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-43.91 -3.59 Td +(MIO[53:0]) Tj +ET +Q +2 w +1150 -340 m +1140 -340 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -345 m +1118 -340 l +1123 -335 l +1128 -340 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.33 -3.59 Td +(DDR_VRN) Tj +ET +Q +1150 -320 m +1140 -320 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -325 m +1118 -320 l +1123 -315 l +1128 -320 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -320 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-47.78 -3.59 Td +(DDR_VRP) Tj +ET +Q +1150 -300 m +1140 -300 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -305 m +1118 -300 l +1123 -295 l +1128 -300 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -300 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.24 -3.59 Td +(PS_SRSTB) Tj +ET +Q +1150 -280 m +1140 -280 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -285 m +1118 -280 l +1123 -275 l +1128 -280 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -280 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-38.35 -3.59 Td +(PS_CLK) Tj +ET +Q +1150 -260 m +1140 -260 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1123 -265 m +1118 -260 l +1123 -255 l +1128 -260 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -260 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-47.24 -3.59 Td +(PS_PORB) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 -249 10 298 re +f +Q +q +1 0 0 1 1130.5 -239.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 -240 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 -240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(SPI_0) Tj +ET +Q +1150 -220 m +1140 -220 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -225 m +1119 -220 l +1127 -215 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.7 -3.59 Td +(SPI0_SCLK_I) Tj +ET +Q +1150 -200 m +1140 -200 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -205 m +1127 -200 l +1119 -195 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.7 -3.59 Td +(SPI0_SCLK_O) Tj +ET +Q +1150 -180 m +1140 -180 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -185 m +1127 -180 l +1119 -175 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-65.03 -3.59 Td +(SPI0_SCLK_T) Tj +ET +Q +1150 -160 m +1140 -160 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -165 m +1119 -160 l +1127 -155 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI0_MOSI_I) Tj +ET +Q +1150 -140 m +1140 -140 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -145 m +1127 -140 l +1119 -135 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI0_MOSI_O) Tj +ET +Q +1150 -120 m +1140 -120 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -125 m +1127 -120 l +1119 -115 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI0_MOSI_T) Tj +ET +Q +1150 -100 m +1140 -100 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -105 m +1119 -100 l +1127 -95 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI0_MISO_I) Tj +ET +Q +1150 -80 m +1140 -80 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -85 m +1127 -80 l +1119 -75 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI0_MISO_O) Tj +ET +Q +1150 -60 m +1140 -60 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -65 m +1127 -60 l +1119 -55 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI0_MISO_T) Tj +ET +Q +1150 -40 m +1140 -40 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 -45 m +1119 -40 l +1127 -35 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -40 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.92 -3.59 Td +(SPI0_SS_I) Tj +ET +Q +1150 -20 m +1140 -20 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -25 m +1127 -20 l +1119 -15 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 -20 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-53.92 -3.59 Td +(SPI0_SS_O) Tj +ET +Q +1150 0 m +1140 0 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 -5 m +1127 0 l +1119 5 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 0 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI0_SS1_O) Tj +ET +Q +1150 20 m +1140 20 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 15 m +1127 20 l +1119 25 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 20 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI0_SS2_O) Tj +ET +Q +1150 40 m +1140 40 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 35 m +1127 40 l +1119 45 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 40 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.25 -3.59 Td +(SPI0_SS_T) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 51 10 298 re +f +Q +q +1 0 0 1 1130.5 60.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im8 Do +Q +q +1 0 0 1 1145 60 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 60 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(SPI_1) Tj +ET +Q +1150 80 m +1140 80 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 75 m +1119 80 l +1127 85 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 80 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.7 -3.59 Td +(SPI1_SCLK_I) Tj +ET +Q +1150 100 m +1140 100 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 95 m +1127 100 l +1119 105 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 100 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.7 -3.59 Td +(SPI1_SCLK_O) Tj +ET +Q +1150 120 m +1140 120 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 115 m +1127 120 l +1119 125 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-65.03 -3.59 Td +(SPI1_SCLK_T) Tj +ET +Q +1150 140 m +1140 140 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 135 m +1119 140 l +1127 145 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI1_MOSI_I) Tj +ET +Q +1150 160 m +1140 160 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 155 m +1127 160 l +1119 165 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI1_MOSI_O) Tj +ET +Q +1150 180 m +1140 180 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 175 m +1127 180 l +1119 185 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI1_MOSI_T) Tj +ET +Q +1150 200 m +1140 200 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 195 m +1119 200 l +1127 205 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-61.14 -3.59 Td +(SPI1_MISO_I) Tj +ET +Q +1150 220 m +1140 220 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 215 m +1127 220 l +1119 225 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-66.14 -3.59 Td +(SPI1_MISO_O) Tj +ET +Q +1150 240 m +1140 240 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 235 m +1127 240 l +1119 245 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 240 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-64.47 -3.59 Td +(SPI1_MISO_T) Tj +ET +Q +1150 260 m +1140 260 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1127 255 m +1119 260 l +1127 265 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 260 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.92 -3.59 Td +(SPI1_SS_I) Tj +ET +Q +1150 280 m +1140 280 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 275 m +1127 280 l +1119 285 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 280 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-53.92 -3.59 Td +(SPI1_SS_O) Tj +ET +Q +1150 300 m +1140 300 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 295 m +1127 300 l +1119 305 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 300 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI1_SS1_O) Tj +ET +Q +1150 320 m +1140 320 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 315 m +1127 320 l +1119 325 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 320 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-59.48 -3.59 Td +(SPI1_SS2_O) Tj +ET +Q +1150 340 m +1140 340 l +S +q +0.255 0.380 0.624 rg +/GSa0 gs +1119 335 m +1127 340 l +1119 345 l +h f +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1118 340 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-52.25 -3.59 Td +(SPI1_SS_T) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 351 10 18 re +f +Q +q +1 0 0 1 1130.5 360.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 360 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im5 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 360 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-48.9 -3.59 Td +(USBIND_0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -79 10 18 re +f +Q +q +1 0 0 1 769.5 -69.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -70 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -70 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -59 10 18 re +f +Q +q +1 0 0 1 769.5 -49.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -50 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -50 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -39 10 18 re +f +Q +q +1 0 0 1 769.5 -29.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -30 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im6 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -30 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP2_FIFO_CTRL) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +1140 371 10 18 re +f +Q +q +1 0 0 1 1130.5 380.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 1145 380 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im4 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1123 380 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-55.58 -3.59 Td +(M_AXI_GP0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 -19 10 18 re +f +Q +q +1 0 0 1 769.5 -9.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 -10 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 -10 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 1 10 18 re +f +Q +q +1 0 0 1 769.5 10.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 10 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 10 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1) Tj +ET +Q +q +0.929 0.965 0.996 rg +/GSa0 gs +750 21 10 18 re +f +Q +q +1 0 0 1 769.5 30.5 cm +1 0 0 1 -7.5 -7.5 cm +15 0 0 -15 0 15 cm /Im2 Do +Q +q +1 0 0 1 755 30 cm +1 0 0 1 -5 -9 cm +10 0 0 -18 0 18 cm /Im3 Do +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 777 30 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP2) Tj +ET +Q +3 w +750 50 m +760 50 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 50 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(M_AXI_GP0_ACLK) Tj +ET +Q +750 70 m +760 70 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 70 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP0_ACLK) Tj +ET +Q +750 90 m +760 90 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 90 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S_AXI_HP1_ACLK) Tj +ET +Q +750 110 m +760 110 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 762 110 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td 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n +trailer +<< + /Size 170 + /Info 1 0 R + /Root 2 0 R +>> +startxref +118759 +%%EOF diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl new file mode 100644 index 000000000..04ba4accd --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/e320_ps_bd.tcl @@ -0,0 +1,823 @@ +# CHANGE DESIGN NAME HERE +set design_name e320_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set m_axi_eth_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_eth_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_eth_dma + set m_axi_net [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_net ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_net + set m_axi_xbar [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_xbar ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {0} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_WSTRB {0} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $m_axi_xbar + set s_axi_eth_descriptor [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth_descriptor ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_eth_descriptor + set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP0 + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ + CONFIG.PortWidth {16} \ + CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ + CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP0_ACLK + set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ + CONFIG.ASSOCIATED_RESET {bus_rstn} \ + CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_net:m_axi_xbar:m_axi_eth_dma} \ + CONFIG.ASSOCIATED_RESET {clk40_rstn} \ + CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + # Create instance: axi_interconnect_hp0, and set properties + set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp0 + + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ + CONFIG.NUM_MI {6} \ + ] $axi_interconnect_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 6 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {1000.000000} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {40.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {1000} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {40000000} \ + CONFIG.PCW_CLK2_FREQ {166666672} \ + CONFIG.PCW_CLK3_FREQ {200000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {2000.000} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {16} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {1} \ + CONFIG.PCW_ENET0_RESET_IO {MIO 3} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_CLK3_PORT {1} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {1} \ + CONFIG.PCW_EN_PJTAG {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI1 {1} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {3} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 14 .. 15} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C0_RESET_IO {} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {60} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {2000.000} \ + CONFIG.PCW_IRQ_F2P_INTR {1} \ + CONFIG.PCW_MIO_0_DIRECTION {inout} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {in} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {out} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {in} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {in} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {inout} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_DIRECTION {inout} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_15_PULLUP {enabled} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_16_DIRECTION {out} \ + CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_16_PULLUP {disabled} \ + CONFIG.PCW_MIO_16_SLEW {fast} \ + CONFIG.PCW_MIO_17_DIRECTION {out} \ + CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_17_PULLUP {disabled} \ + CONFIG.PCW_MIO_17_SLEW {fast} \ + CONFIG.PCW_MIO_18_DIRECTION {out} \ + CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_18_PULLUP {disabled} \ + CONFIG.PCW_MIO_18_SLEW {fast} \ + CONFIG.PCW_MIO_19_DIRECTION {out} \ + CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_19_PULLUP {disabled} \ + CONFIG.PCW_MIO_19_SLEW {fast} \ + CONFIG.PCW_MIO_1_DIRECTION {inout} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_20_DIRECTION {out} \ + CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_20_PULLUP {disabled} \ + CONFIG.PCW_MIO_20_SLEW {fast} \ + CONFIG.PCW_MIO_21_DIRECTION {out} \ + CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_21_PULLUP {disabled} \ + CONFIG.PCW_MIO_21_SLEW {fast} \ + CONFIG.PCW_MIO_22_DIRECTION {in} \ + CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_22_PULLUP {disabled} \ + CONFIG.PCW_MIO_22_SLEW {fast} \ + CONFIG.PCW_MIO_23_DIRECTION {in} \ + CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_23_PULLUP {disabled} \ + CONFIG.PCW_MIO_23_SLEW {fast} \ + CONFIG.PCW_MIO_24_DIRECTION {in} \ + CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_24_PULLUP {disabled} \ + CONFIG.PCW_MIO_24_SLEW {fast} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_25_PULLUP {disabled} \ + CONFIG.PCW_MIO_25_SLEW {fast} \ + CONFIG.PCW_MIO_26_DIRECTION {in} \ + CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_26_PULLUP {disabled} \ + CONFIG.PCW_MIO_26_SLEW {fast} \ + CONFIG.PCW_MIO_27_DIRECTION {in} \ + CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_27_PULLUP {disabled} \ + CONFIG.PCW_MIO_27_SLEW {fast} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_28_PULLUP {enabled} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_DIRECTION {in} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_29_PULLUP {enabled} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_30_DIRECTION {out} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_30_PULLUP {enabled} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_DIRECTION {in} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_31_PULLUP {enabled} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_32_PULLUP {enabled} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_33_PULLUP {enabled} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_DIRECTION {inout} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_34_PULLUP {enabled} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_35_PULLUP {enabled} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_DIRECTION {in} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_36_PULLUP {enabled} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_37_PULLUP {enabled} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_38_PULLUP {enabled} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_39_PULLUP {enabled} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {out} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_40_PULLUP {enabled} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_41_PULLUP {enabled} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_42_PULLUP {enabled} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_43_PULLUP {enabled} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_44_PULLUP {enabled} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_45_PULLUP {enabled} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_46_DIRECTION {in} \ + CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_46_PULLUP {enabled} \ + CONFIG.PCW_MIO_46_SLEW {slow} \ + CONFIG.PCW_MIO_47_DIRECTION {out} \ + CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_47_PULLUP {enabled} \ + CONFIG.PCW_MIO_47_SLEW {slow} \ + CONFIG.PCW_MIO_48_DIRECTION {inout} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_DIRECTION {inout} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {out} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_50_DIRECTION {inout} \ + CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_50_PULLUP {enabled} \ + CONFIG.PCW_MIO_50_SLEW {slow} \ + CONFIG.PCW_MIO_51_DIRECTION {inout} \ + CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_51_PULLUP {enabled} \ + CONFIG.PCW_MIO_51_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {out} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {in} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#GPIO#GPIO#ENET Reset#USB Reset#GPIO#GPIO#GPIO#UART 1#UART 1#PJTAG#PJTAG#PJTAG#PJTAG#I2C 0#I2C 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 0#UART 0#I2C 1#I2C 1#GPIO#GPIO#Enet 0#Enet 0} \ + CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#gpio[1]#gpio[2]#reset#reset#gpio[5]#gpio[6]#gpio[7]#tx#rx#tdi#tdo#tck#tms#scl#sda#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#rx#tx#scl#sda#gpio[50]#gpio[51]#mdc#mdio} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \ + CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ + CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {12} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {20} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 4} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_PS_SLCR_REGISTERS {1} \ + CONFIG.PCW_USE_S_AXI_GP0 {0} \ + CONFIG.PCW_USE_S_AXI_GP1 {0} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + CONFIG.PCW_USE_S_AXI_HP1 {1} \ + CONFIG.PCW_USE_S_AXI_HP2 {1} \ + CONFIG.PCW_USE_S_AXI_HP3 {0} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {16} \ + CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net s_axi_eth_descriptor_1 [get_bd_intf_ports s_axi_eth_descriptor] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_eth_dma] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_net] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_xbar] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net s_axi_regfile_1 [get_bd_intf_pins axi_interconnect_0/M03_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 [get_bd_intf_pins axi_interconnect_0/M04_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_0_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_0_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_0_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_0_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_GP0_ACLK_1 [get_bd_ports S_AXI_GP0_ACLK] [get_bd_pins axi_interconnect_0/ACLK] + connect_bd_net -net S_AXI_GP0_ARESETN_1 [get_bd_ports S_AXI_GP0_ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins axi_interconnect_hp0/S01_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/S01_ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + + # Create address segments + create_bd_addr_seg -range 0x00004000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_eth_dma/Reg] SEG_m_axi_eth_dma_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_net/Reg] SEG_m_axi_net_Reg + create_bd_addr_seg -range 0x00004000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_xbar/Reg] SEG_m_axi_xbar_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite4 + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite6 + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite8 + create_bd_addr_seg -range 0x00010000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite10 + create_bd_addr_seg -range 0x00010000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite12 + create_bd_addr_seg -range 0x00010000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_tx_dmac_0_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_tx_dmac_1_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_tx_dmac_2_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_tx_dmac_3_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_tx_dmac_4_axi_lite + create_bd_addr_seg -range 0x00010000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_tx_dmac_5_axi_lite + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth_descriptor] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c new file mode 100644 index 000000000..1ad91d83a --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init.c @@ -0,0 +1,13335 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c new file mode 100644 index 000000000..dd9994e98 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/e320_ps_bd/ps7_init_gpl.c @@ -0,0 +1,13326 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000110[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0x4 + // .. .. ==> 0XF8000118[7:4] = 0x00000004U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000118[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x3c + // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x10 + // .. ==> 0XF8000140[13:8] = 0x00000010U + // .. ==> MASK : 0x00003F00U VAL : 0x00001000U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000140[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001403U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xc + // .. ==> 0XF8000158[13:8] = 0x0000000CU + // .. ==> MASK : 0x00003F00U VAL : 0x00000C00U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000C03U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0xa + // .. .. ==> 0XF8000168[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0xa + // .. .. ==> 0XF8000180[13:8] = 0x0000000AU + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. .. DIVISOR1 = 0x5 + // .. .. ==> 0XF8000180[25:20] = 0x00000005U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00500A00U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000190[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x4 + // .. .. ==> 0XF8000190[13:8] = 0x00000004U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000400U + // .. .. DIVISOR1 = 0x3 + // .. .. ==> 0XF8000190[25:20] = 0x00000003U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00300400U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF80001A0[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF80001A0[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x017CC44DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1a + // .. .. ==> 0XF8006014[5:0] = 0x0000001AU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x7 + // .. .. ==> 0XF800612C[9:0] = 0x00000007U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U + // .. .. reg_phy_gatelvl_init_ratio = 0x7a + // .. .. ==> 0XF800612C[19:10] = 0x0000007AU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0001E807U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006130[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006130[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x5 + // .. .. ==> 0XF8006134[9:0] = 0x00000005U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000005U + // .. .. reg_phy_gatelvl_init_ratio = 0x7b + // .. .. ==> 0XF8006134[19:10] = 0x0000007BU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001EC00U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0001EC05U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1 + // .. .. ==> 0XF8006138[9:0] = 0x00000001U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000001U + // .. .. reg_phy_gatelvl_init_ratio = 0x78 + // .. .. ==> 0XF8006138[19:10] = 0x00000078U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0001E000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0001E001U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 + // .. .. ==> 0XF8006154[9:0] = 0x00000087U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000087U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF8006158[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x85 + // .. .. ==> 0XF800615C[9:0] = 0x00000085U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000085U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000085U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x81 + // .. .. ==> 0XF8006160[9:0] = 0x00000081U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000081U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000081U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcf + // .. .. ==> 0XF8006168[10:0] = 0x000000CFU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CFU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000CFU), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF800616C[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xd0 + // .. .. ==> 0XF8006170[10:0] = 0x000000D0U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000D0U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000D0U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xcd + // .. .. ==> 0XF8006174[10:0] = 0x000000CDU + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000CDU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000CDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xc7 + // .. .. ==> 0XF800617C[9:0] = 0x000000C7U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C7U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006180[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc5 + // .. .. ==> 0XF8006184[9:0] = 0x000000C5U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C5U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C5U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc1 + // .. .. ==> 0XF8006188[9:0] = 0x000000C1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x3 + // .. ==> 0XF8000B6C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000260U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000700[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000700[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000700[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000700[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000700[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000704[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000708[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800070C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000710[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000714[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000718[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000728[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000728[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF800072C[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001660U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000730[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000730[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000734[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 3 + // .. ==> 0XF8000734[7:5] = 0x00000003U + // .. ==> MASK : 0x000000E0U VAL : 0x00000060U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001661U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF8000738[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF800073C[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000740[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000740[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000740[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000744[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000744[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000744[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000748[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000748[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000748[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800074C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800074C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800074C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000750[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000750[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000750[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000754[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000754[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000754[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000758[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000758[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800075C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800075C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000760[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000760[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000764[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000764[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF8000768[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF8000768[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 1 + // .. ==> 0XF800076C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. IO_Type = 1 + // .. ==> 0XF800076C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007A8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007AC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007B8[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000012E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007BC[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000012E0U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007C8[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007CC[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001280U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xffef + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFEFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFEF0000U + // .. .. .. .. DATA_0_LSW = 0x10 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000010U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000010U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFEF0010U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x18 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x18 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000018U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000018U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000018U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xfff7 + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FFF7U + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFFF70000U + // .. .. .. .. DATA_0_LSW = 0x8 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000008U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFFF70008U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 0 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + true + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..413db0f83 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,49 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_clocking.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +one_gig_eth_pcs_pma_support.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..ae93c645d --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,352 @@ + + + xilinx.com + xci + unknown + 1.0 + + + one_gig_eth_pcs_pma + + + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + true + 0 + 0 + false + false + DIFF_PAIR_0 + DIFF_PAIR_1 + false + DIFF_PAIR_0 + DIFF_PAIR_1 + zynq + 0 + one_gig_eth_pcs_pma + 50.0 + false + . + false + false + false + false + zynq + 8 + 9 + X0Y0 + 7 + 4 + GTH + false + false + false + false + true + false + false + 1 + clk0 + 125 + TXOUTCLK + true + false + one_gig_eth_pcs_pma_gt + false + GTXE2 + false + 1 + false + false + true + xc7z045 + false + 1 + false + false + Sync + one_gig_eth_pcs_pma + Custom + 50.0 + TEMAC + Custom + 0 + false + false + false + false + X0Y0 + GTH + false + false + 125 + Custom + true + 1G + 1 + Transceiver + 125 + clk0 + TXOUTCLK + DIFF_PAIR_0 + DIFF_PAIR_1 + false + 10_100_1000 + false + 1000BASEX + Include_Shared_Logic_in_Example_Design + Time_of_day + false + DIFF_PAIR_0 + DIFF_PAIR_1 + 1 + false + zynq + + + xc7z045 + ffg900 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch new file mode 100644 index 000000000..41f963797 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch @@ -0,0 +1,25 @@ +65,66d64 +< input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality. +< input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality. +70,71d67 +< output gtrefclk, // gtrefclk routed through an IBUFG. +< output gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +88d83 +< wire gtrefclk_i; +93,108d87 +< // Clock circuitry for the Transceiver uses a differential input clock. +< // gtrefclk is routed to the tranceiver. +< IBUFDS_GTE2 ibufds_gtrefclk ( +< .I (gtrefclk_p), +< .IB (gtrefclk_n), +< .CEB (1'b0), +< .O (gtrefclk_i), +< .ODIV2 () +< ); +< +< assign gtrefclk = gtrefclk_i; +< +< BUFG bufg_gtrefclk ( +< .I (gtrefclk_i), +< .O (gtrefclk_bufg) +< ); diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch new file mode 100644 index 000000000..277c890f1 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch @@ -0,0 +1,17 @@ +70,73c70,71 +< input gtrefclk_p, // differential clock +< input gtrefclk_n, // differential clock +< output gtrefclk_out, // Very high quality clock for GT transceiver. +< output gtrefclk_bufg_out, +--- +> input gtrefclk, // gtrefclk routed through an IBUFG. +> input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +125,126d122 +< wire gtrefclk; // High quality clock +< wire gtrefclk_bufg; +205,206d200 +< .gtrefclk_p (gtrefclk_p), +< .gtrefclk_n (gtrefclk_n), +210,211d203 +< .gtrefclk (gtrefclk), +< .gtrefclk_bufg (gtrefclk_bufg), diff --git a/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..f30f98fc3 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,102 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO PHY Address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect // Input from PMD to indicate presence of optical input. +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_out (), + .gt0_qplloutrefclk_out () + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..899260fe0 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/, \ +imports/ten_gig_eth_pcs_pma_example_design.v \ +imports/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +imports/ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +imports/ten_gig_eth_pcs_pma_support.v \ +imports/ten_gig_eth_pcs_pma_gt_common.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..140a5049b --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,200 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma + + + 0 + 0 + 0 + 0 + 0 + + + 0 + 0.000 + + + + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 0 + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + false + 0 + 0 + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + + 0 + 0.000 + + + + 0 + 0.000 + 0 + ten_gig_eth_pcs_pma + 78.125 + zynq + X0Y0 + 32 + 0 + false + false + true + false + false + false + clk0 + 156 + 10 + ten_gig_eth_pcs_pma_gt + ten_gig_eth_pcs_pma + 78.125 + None + X0Y0 + true + clk0 + 156.25 + 0 + Time_of_day + false + false + false + BASE-R + 64bit + false + false + 10Gig + GTH + zynq + + + xc7z045 + ffg900 + VERILOG + + MIXED + -3 + + + TRUE + TRUE + IP_Flow + 15 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..aa4db148f --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,249 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + wire qplloutclk; + wire qplloutrefclk; + wire qplllock; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qpllreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..7c1d09fe6 --- /dev/null +++ b/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output dclk +); + + wire dclk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Dividing independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/e320/mb_pins.xdc b/fpga/usrp3/top/e320/mb_pins.xdc new file mode 100644 index 000000000..aa299133c --- /dev/null +++ b/fpga/usrp3/top/e320/mb_pins.xdc @@ -0,0 +1,473 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Motherboard Pin Definitions for the E320. +# + +## Power ################################################################### +## +############################################################################ + +# Power Enable, Bank 10 +set_property PACKAGE_PIN AK15 [get_ports {ENA_PAPWR}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENA_PAPWR}] + +## SFP + ################################################################### +## +############################################################################ + +## Power +#set_property PACKAGE_PIN AB9 [get_ports {+1V2_MGT_AVTT}] +#set_property IOSTANDARD [get_ports {+1V2_MGT_AVTT}] + +## Clocks, Bank 112 +set_property PACKAGE_PIN R7 [get_ports {CLK_MGT_156_25M_N}] +set_property PACKAGE_PIN R8 [get_ports {CLK_MGT_156_25M_P}] + +set_property PACKAGE_PIN N7 [get_ports {CLK_MGT_125M_N}] +set_property PACKAGE_PIN N8 [get_ports {CLK_MGT_125M_P}] + +## MGT, Bank 112 +set_property PACKAGE_PIN V5 [get_ports {SFP1_RX_N}] +set_property PACKAGE_PIN V6 [get_ports {SFP1_RX_P}] +set_property PACKAGE_PIN T1 [get_ports {SFP1_TX_N}] +set_property PACKAGE_PIN T2 [get_ports {SFP1_TX_P}] + +## SFP Sideband, Bank 10, 3.3V +set_property PACKAGE_PIN AJ16 [get_ports {SFP1_RXLOS}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_RXLOS}] + +set_property PACKAGE_PIN AK13 [get_ports {SFP1_TXFAULT}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_TXFAULT}] + +set_property PACKAGE_PIN AK12 [get_ports {SFP1_TXDISABLE}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_TXDISABLE}] + +set_property PACKAGE_PIN AE17 [get_ports {SFP1_MOD_ABS}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_MOD_ABS}] + +set_property PACKAGE_PIN AJ18 [get_ports {SFP1_RS0}] +set_property PACKAGE_PIN AK16 [get_ports {SFP1_RS1}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP1_RS*}] + +set_property PACKAGE_PIN AB17 [get_ports {LED_LINK1}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED_LINK1}] + +set_property PACKAGE_PIN AB16 [get_ports {LED_ACT1}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED_ACT1}] + +## Used with N310 hardware +#set_property PACKAGE_PIN U25 [get_ports PANEL_LED_GPS] +#set_property PACKAGE_PIN T25 [get_ports PANEL_LED_LINK] +#set_property PACKAGE_PIN W29 [get_ports PANEL_LED_PPS] +#set_property PACKAGE_PIN V24 [get_ports PANEL_LED_REF] +#set_property IOSTANDARD LVCMOS33 [get_ports PANEL_LED_*] +#set_property DRIVE 4 [get_ports PANEL_LED_*] +#set_property SLEW SLOW [get_ports PANEL_LED_*] + +## XCVR #################################################################### +## Catalina AD9361 Connections +## -- Data Buses +## -- Clocks +## -- SPI +## -- TX Amplifier +## -- LEDs +## +############################################################################ + +set_property PACKAGE_PIN P25 [get_ports {XCVR_ENABLE}] +set_property PACKAGE_PIN T25 [get_ports {XCVR_SYNC}] +set_property PACKAGE_PIN P23 [get_ports {XCVR_TXNRX}] +set_property PACKAGE_PIN N27 [get_ports {XCVR_ENA_AGC}] +set_property PACKAGE_PIN P26 [get_ports {XCVR_RESET_N}] + +## AD9361 SPI, Bank 13, 1.8V +set_property PACKAGE_PIN T27 [get_ports {XCVR_SPI_CS_N}] +set_property PACKAGE_PIN N26 [get_ports {XCVR_SPI_MISO}] +set_property PACKAGE_PIN P24 [get_ports {XCVR_SPI_MOSI}] +set_property PACKAGE_PIN T24 [get_ports {XCVR_SPI_CLK}] + +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_*}] + +## Catalina TX Data Bus +set_property PACKAGE_PIN F3 [get_ports {TX_CLK_N}] +set_property PACKAGE_PIN F4 [get_ports {TX_CLK_P}] +set_property IOSTANDARD LVDS [get_ports {TX_CLK_*}] +# +set_property PACKAGE_PIN B4 [get_ports {TX_FRAME_N}] +set_property PACKAGE_PIN B5 [get_ports {TX_FRAME_P}] +set_property IOSTANDARD LVDS [get_ports {TX_FRAME_*}] +# +set_property PACKAGE_PIN L2 [get_ports {TX_DATA_N[0]}] +set_property PACKAGE_PIN L3 [get_ports {TX_DATA_P[0]}] +set_property PACKAGE_PIN D5 [get_ports {TX_DATA_N[1]}] +set_property PACKAGE_PIN E6 [get_ports {TX_DATA_P[1]}] +set_property PACKAGE_PIN A4 [get_ports {TX_DATA_N[2]}] +set_property PACKAGE_PIN A5 [get_ports {TX_DATA_P[2]}] +set_property PACKAGE_PIN J3 [get_ports {TX_DATA_N[3]}] +set_property PACKAGE_PIN J4 [get_ports {TX_DATA_P[3]}] +set_property PACKAGE_PIN D1 [get_ports {TX_DATA_N[4]}] +set_property PACKAGE_PIN E1 [get_ports {TX_DATA_P[4]}] +set_property PACKAGE_PIN E2 [get_ports {TX_DATA_N[5]}] +set_property PACKAGE_PIN E3 [get_ports {TX_DATA_P[5]}] +set_property IOSTANDARD LVDS [get_ports {TX_DATA_*[*]}] + +## Catalina RX Data Bus +set_property PACKAGE_PIN G4 [get_ports {RX_CLK_N}] +set_property PACKAGE_PIN G5 [get_ports {RX_CLK_P}] +set_property IOSTANDARD LVDS [get_ports {RX_CLK_*}] +set_property DIFF_TERM TRUE [get_ports {RX_CLK_*}] +# +set_property PACKAGE_PIN J6 [get_ports {RX_FRAME_N}] +set_property PACKAGE_PIN K6 [get_ports {RX_FRAME_P}] +set_property IOSTANDARD LVDS [get_ports {RX_FRAME_*}] +set_property DIFF_TERM TRUE [get_ports {RX_FRAME_*}] +# +set_property PACKAGE_PIN C3 [get_ports {RX_DATA_N[0]}] +set_property PACKAGE_PIN C4 [get_ports {RX_DATA_P[0]}] +set_property PACKAGE_PIN G6 [get_ports {RX_DATA_N[1]}] +set_property PACKAGE_PIN H6 [get_ports {RX_DATA_P[1]}] +set_property PACKAGE_PIN D3 [get_ports {RX_DATA_N[2]}] +set_property PACKAGE_PIN D4 [get_ports {RX_DATA_P[2]}] +set_property PACKAGE_PIN K1 [get_ports {RX_DATA_N[3]}] +set_property PACKAGE_PIN L1 [get_ports {RX_DATA_P[3]}] +set_property PACKAGE_PIN J5 [get_ports {RX_DATA_N[4]}] +set_property PACKAGE_PIN K5 [get_ports {RX_DATA_P[4]}] +set_property PACKAGE_PIN F2 [get_ports {RX_DATA_N[5]}] +set_property PACKAGE_PIN G2 [get_ports {RX_DATA_P[5]}] +set_property IOSTANDARD LVDS [get_ports {RX_DATA_*[*]}] +set_property DIFF_TERM TRUE [get_ports {RX_DATA_*[*]}] + +## TX Amp, Bank 13, 1.8V +set_property PACKAGE_PIN P29 [get_ports {TX_HFAMP1_ENA}] +set_property PACKAGE_PIN U29 [get_ports {TX_HFAMP2_ENA}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX_HFAMP*_ENA}] + +set_property PACKAGE_PIN N29 [get_ports {TX_LFAMP1_ENA}] +set_property PACKAGE_PIN T29 [get_ports {TX_LFAMP2_ENA}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX_LFAMP*_ENA}] + +# CTRL_OUT, Bank 13, 1.8 V +set_property PACKAGE_PIN V28 [get_ports {XCVR_CTRL_OUT[0]}] +set_property PACKAGE_PIN V29 [get_ports {XCVR_CTRL_OUT[1]}] +set_property PACKAGE_PIN W29 [get_ports {XCVR_CTRL_OUT[2]}] +set_property PACKAGE_PIN W30 [get_ports {XCVR_CTRL_OUT[3]}] +set_property PACKAGE_PIN V27 [get_ports {XCVR_CTRL_OUT[4]}] +set_property PACKAGE_PIN W28 [get_ports {XCVR_CTRL_OUT[5]}] +set_property PACKAGE_PIN W25 [get_ports {XCVR_CTRL_OUT[6]}] +set_property PACKAGE_PIN W26 [get_ports {XCVR_CTRL_OUT[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {XCVR_CTRL_OUT[*]}] +# Set pull-up on bits 6 and 7 to make the bitstream compatible with Rev A, +# where the signals don't exist. +set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[6]}] +set_property PULLUP TRUE [get_ports {XCVR_CTRL_OUT[7]}] + +## RX/TX LEDs, Bank 10, 3.3 V +set_property PACKAGE_PIN AG14 [get_ports {RX1_GRN_ENA}] +set_property PACKAGE_PIN AG17 [get_ports {RX2_GRN_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX*_GRN_ENA}] + +set_property PACKAGE_PIN AG16 [get_ports {TX1_RED_ENA}] +set_property PACKAGE_PIN AF15 [get_ports {TX2_RED_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {TX*_RED_ENA}] + +set_property PACKAGE_PIN AG15 [get_ports {TXRX1_GRN_ENA}] +set_property PACKAGE_PIN AF18 [get_ports {TXRX2_GRN_ENA}] +set_property IOSTANDARD LVCMOS33 [get_ports {TXRX*_GRN_ENA}] + + +## PL DDR #################################################################### +## +############################################################################ + +## PL DDR, Bank 34,35 + +set_property PACKAGE_PIN G9 [get_ports {SYS_CLK_N}] +set_property PACKAGE_PIN H9 [get_ports {SYS_CLK_P}] +set_property PACKAGE_PIN D8 [get_ports {DDR3_ADDR[0]}] +set_property PACKAGE_PIN F9 [get_ports {DDR3_ADDR[1]}] +set_property PACKAGE_PIN A7 [get_ports {DDR3_ADDR[2]}] +set_property PACKAGE_PIN D9 [get_ports {DDR3_ADDR[3]}] +set_property PACKAGE_PIN H7 [get_ports {DDR3_ADDR[4]}] +set_property PACKAGE_PIN E8 [get_ports {DDR3_ADDR[5]}] +set_property PACKAGE_PIN F8 [get_ports {DDR3_ADDR[6]}] +set_property PACKAGE_PIN E7 [get_ports {DDR3_ADDR[7]}] +set_property PACKAGE_PIN C6 [get_ports {DDR3_ADDR[8]}] +set_property PACKAGE_PIN C7 [get_ports {DDR3_ADDR[9]}] +set_property PACKAGE_PIN B7 [get_ports {DDR3_ADDR[10]}] +set_property PACKAGE_PIN J9 [get_ports {DDR3_ADDR[11]}] +set_property PACKAGE_PIN D11 [get_ports {DDR3_ADDR[12]}] +set_property PACKAGE_PIN F7 [get_ports {DDR3_ADDR[13]}] +set_property PACKAGE_PIN D6 [get_ports {DDR3_ADDR[14]}] +set_property PACKAGE_PIN B6 [get_ports {DDR3_ADDR[15]}] +set_property PACKAGE_PIN C9 [get_ports {DDR3_BA[0]}] +set_property PACKAGE_PIN G7 [get_ports {DDR3_BA[1]}] +set_property PACKAGE_PIN B9 [get_ports {DDR3_BA[2]}] +set_property PACKAGE_PIN D10 [get_ports {DDR3_CAS_N}] +set_property PACKAGE_PIN E11 [get_ports {DDR3_CKE[0]}] +set_property PACKAGE_PIN H8 [get_ports {DDR3_CK_N[0]}] +set_property PACKAGE_PIN J8 [get_ports {DDR3_CK_P[0]}] +set_property PACKAGE_PIN E10 [get_ports {DDR3_CS_N[0]}] +set_property PACKAGE_PIN D16 [get_ports {DDR3_DM[0]}] +set_property PACKAGE_PIN C12 [get_ports {DDR3_DM[1]}] +set_property PACKAGE_PIN J13 [get_ports {DDR3_DM[2]}] +set_property PACKAGE_PIN F14 [get_ports {DDR3_DM[3]}] +set_property PACKAGE_PIN B16 [get_ports {DDR3_DQ[0]}] +set_property PACKAGE_PIN A17 [get_ports {DDR3_DQ[1]}] +set_property PACKAGE_PIN C16 [get_ports {DDR3_DQ[2]}] +set_property PACKAGE_PIN E15 [get_ports {DDR3_DQ[3]}] +set_property PACKAGE_PIN C17 [get_ports {DDR3_DQ[4]}] +set_property PACKAGE_PIN D14 [get_ports {DDR3_DQ[5]}] +set_property PACKAGE_PIN B17 [get_ports {DDR3_DQ[6]}] +set_property PACKAGE_PIN D15 [get_ports {DDR3_DQ[7]}] +set_property PACKAGE_PIN B12 [get_ports {DDR3_DQ[8]}] +set_property PACKAGE_PIN A13 [get_ports {DDR3_DQ[9]}] +set_property PACKAGE_PIN C11 [get_ports {DDR3_DQ[10]}] +set_property PACKAGE_PIN C14 [get_ports {DDR3_DQ[11]}] +set_property PACKAGE_PIN A12 [get_ports {DDR3_DQ[12]}] +set_property PACKAGE_PIN B14 [get_ports {DDR3_DQ[13]}] +set_property PACKAGE_PIN B11 [get_ports {DDR3_DQ[14]}] +set_property PACKAGE_PIN A14 [get_ports {DDR3_DQ[15]}] +set_property PACKAGE_PIN J16 [get_ports {DDR3_DQ[16]}] +set_property PACKAGE_PIN J14 [get_ports {DDR3_DQ[17]}] +set_property PACKAGE_PIN L15 [get_ports {DDR3_DQ[18]}] +set_property PACKAGE_PIN H14 [get_ports {DDR3_DQ[19]}] +set_property PACKAGE_PIN K15 [get_ports {DDR3_DQ[20]}] +set_property PACKAGE_PIN H13 [get_ports {DDR3_DQ[21]}] +set_property PACKAGE_PIN L14 [get_ports {DDR3_DQ[22]}] +set_property PACKAGE_PIN J15 [get_ports {DDR3_DQ[23]}] +set_property PACKAGE_PIN E13 [get_ports {DDR3_DQ[24]}] +set_property PACKAGE_PIN F15 [get_ports {DDR3_DQ[25]}] +set_property PACKAGE_PIN F13 [get_ports {DDR3_DQ[26]}] +set_property PACKAGE_PIN G16 [get_ports {DDR3_DQ[27]}] +set_property PACKAGE_PIN E12 [get_ports {DDR3_DQ[28]}] +set_property PACKAGE_PIN G15 [get_ports {DDR3_DQ[29]}] +set_property PACKAGE_PIN D13 [get_ports {DDR3_DQ[30]}] +set_property PACKAGE_PIN G14 [get_ports {DDR3_DQ[31]}] +set_property PACKAGE_PIN E17 [get_ports {DDR3_DQS_N[0]}] +set_property PACKAGE_PIN F17 [get_ports {DDR3_DQS_P[0]}] +set_property PACKAGE_PIN A15 [get_ports {DDR3_DQS_N[1]}] +set_property PACKAGE_PIN B15 [get_ports {DDR3_DQS_P[1]}] +set_property PACKAGE_PIN K13 [get_ports {DDR3_DQS_N[2]}] +set_property PACKAGE_PIN L13 [get_ports {DDR3_DQS_P[2]}] +set_property PACKAGE_PIN F12 [get_ports {DDR3_DQS_N[3]}] +set_property PACKAGE_PIN G12 [get_ports {DDR3_DQS_P[3]}] +set_property PACKAGE_PIN G11 [get_ports {DDR3_ODT[0]}] +set_property PACKAGE_PIN A10 [get_ports {DDR3_RAS_N}] +set_property PACKAGE_PIN B10 [get_ports {DDR3_RESET_N}] +set_property PACKAGE_PIN A9 [get_ports {DDR3_WE_N}] + +## Front Panel GPIO ######################################################## +## +############################################################################ + +# GPIO, Bank 12 +set_property PACKAGE_PIN AC26 [get_ports {EN_GPIO_2V5}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_2V5}] + +set_property PACKAGE_PIN AA29 [get_ports {EN_GPIO_3V3}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_3V3}] + +set_property PACKAGE_PIN AB30 [get_ports {EN_GPIO_VAR_SUPPLY}] +set_property IOSTANDARD LVCMOS18 [get_ports {EN_GPIO_VAR_SUPPLY}] + +set_property PACKAGE_PIN AF27 [get_ports {GPIO_PREBUFF[0]}] +set_property PACKAGE_PIN AF29 [get_ports {GPIO_PREBUFF[1]}] +set_property PACKAGE_PIN AE25 [get_ports {GPIO_PREBUFF[2]}] +set_property PACKAGE_PIN AF25 [get_ports {GPIO_PREBUFF[3]}] +set_property PACKAGE_PIN AJ30 [get_ports {GPIO_PREBUFF[4]}] +set_property PACKAGE_PIN AK30 [get_ports {GPIO_PREBUFF[5]}] +set_property PACKAGE_PIN AJ28 [get_ports {GPIO_PREBUFF[6]}] +set_property PACKAGE_PIN AJ29 [get_ports {GPIO_PREBUFF[7]}] + +set_property PACKAGE_PIN AA27 [get_ports {GPIO_DIR[0]}] +set_property PACKAGE_PIN AA28 [get_ports {GPIO_DIR[1]}] +set_property PACKAGE_PIN AB25 [get_ports {GPIO_DIR[2]}] +set_property PACKAGE_PIN AB26 [get_ports {GPIO_DIR[3]}] +set_property PACKAGE_PIN AE26 [get_ports {GPIO_DIR[4]}] +set_property PACKAGE_PIN AB27 [get_ports {GPIO_DIR[5]}] +set_property PACKAGE_PIN AC27 [get_ports {GPIO_DIR[6]}] +set_property PACKAGE_PIN Y25 [get_ports {GPIO_DIR[7]}] + +set_property PACKAGE_PIN AD26 [get_ports {GPIO_OE_N}] + +set_property IOSTANDARD LVCMOS18 [get_ports {GPIO_*}] + +## GPSDO ################################################################### +## +############################################################################ + +# GPSDO, Bank 13 +set_property PACKAGE_PIN R28 [get_ports {CLK_GPS_PWR_EN}] +set_property IOSTANDARD LVCMOS18 [get_ports {CLK_GPS_PWR_EN}] + +# GPSDO, Bank 10 +set_property PACKAGE_PIN AD14 [get_ports {GPS_ALARM}] +set_property PACKAGE_PIN AD13 [get_ports {GPS_INITSURV_N}] +set_property PACKAGE_PIN AH13 [get_ports {GPS_LOCK}] +set_property PACKAGE_PIN AE12 [get_ports {GPS_PHASELOCK}] +set_property PACKAGE_PIN AG12 [get_ports {GPS_RST_N}] +set_property PACKAGE_PIN AH14 [get_ports {GPS_SURVEY}] +set_property PACKAGE_PIN AF12 [get_ports {GPS_WARMUP}] + +set_property IOSTANDARD LVCMOS33 [get_ports {GPS_*}] + +## Daughterboard Connections ############################################### +## +############################################################################ + +# Switches, Bank 9 +set_property PACKAGE_PIN Y20 [get_ports {FE1_SEL[0]}] +set_property PACKAGE_PIN AA20 [get_ports {FE1_SEL[1]}] +set_property PACKAGE_PIN AC18 [get_ports {FE1_SEL[2]}] +set_property PACKAGE_PIN AA18 [get_ports {FE2_SEL[0]}] +set_property PACKAGE_PIN AA19 [get_ports {FE2_SEL[1]}] +set_property PACKAGE_PIN AB19 [get_ports {FE2_SEL[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FE*_SEL[*]}] + +set_property PACKAGE_PIN AC19 [get_ports {RX1_SEL[0]}] +set_property PACKAGE_PIN AD18 [get_ports {RX1_SEL[1]}] +set_property PACKAGE_PIN AB20 [get_ports {RX2_SEL[0]}] +set_property PACKAGE_PIN AD20 [get_ports {RX2_SEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {RX*_SEL[*]}] + +# Switches, Bank 11 +set_property PACKAGE_PIN AB21 [get_ports {RX1_BSEL[0]}] +set_property PACKAGE_PIN AB22 [get_ports {RX1_BSEL[1]}] +set_property PACKAGE_PIN W21 [get_ports {RX1_BSEL[2]}] +set_property PACKAGE_PIN Y21 [get_ports {RX1_BSEL[3]}] +set_property PACKAGE_PIN AA24 [get_ports {RX1_BSEL[4]}] +set_property PACKAGE_PIN AB24 [get_ports {RX1_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX1_BSEL[*]}] + +set_property PACKAGE_PIN AC24 [get_ports {RX2_BSEL[0]}] +set_property PACKAGE_PIN AD24 [get_ports {RX2_BSEL[1]}] +set_property PACKAGE_PIN AG24 [get_ports {RX2_BSEL[2]}] +set_property PACKAGE_PIN AG25 [get_ports {RX2_BSEL[3]}] +set_property PACKAGE_PIN AD21 [get_ports {RX2_BSEL[4]}] +set_property PACKAGE_PIN AE21 [get_ports {RX2_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {RX2_BSEL[*]}] + +set_property PACKAGE_PIN AK17 [get_ports {TX1_BSEL[0]}] +set_property PACKAGE_PIN AK18 [get_ports {TX1_BSEL[1]}] +set_property PACKAGE_PIN AH19 [get_ports {TX1_BSEL[2]}] +set_property PACKAGE_PIN AJ19 [get_ports {TX1_BSEL[3]}] +set_property PACKAGE_PIN AF19 [get_ports {TX1_BSEL[4]}] +set_property PACKAGE_PIN AG19 [get_ports {TX1_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX1_BSEL[*]}] + +set_property PACKAGE_PIN AK23 [get_ports {TX2_BSEL[0]}] +set_property PACKAGE_PIN AJ23 [get_ports {TX2_BSEL[1]}] +set_property PACKAGE_PIN AJ24 [get_ports {TX2_BSEL[2]}] +set_property PACKAGE_PIN AH23 [get_ports {TX2_BSEL[3]}] +set_property PACKAGE_PIN AH24 [get_ports {TX2_BSEL[4]}] +set_property PACKAGE_PIN AG22 [get_ports {TX2_BSEL[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {TX2_BSEL[*]}] + +## PPS, REFCLK ############################################################# +## +############################################################################ + +# RefClk, Bank 10 +set_property PACKAGE_PIN AF14 [get_ports {CLK_REF_RAW}] +set_property PACKAGE_PIN AH17 [get_ports {CLK_REF_SEL}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_REF_*}] + +# PPS, Bank 10 +set_property PACKAGE_PIN AD15 [get_ports {CLK_SYNC_EXT}] +set_property PACKAGE_PIN AC14 [get_ports {CLK_SYNC_INT}] +set_property PACKAGE_PIN AA15 [get_ports {CLK_SYNC_INT_RAW}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_SYNC_*}] + +## REF CLK PLL, Bank 10 +set_property PACKAGE_PIN AE15 [get_ports {CLK_PLL_SCLK}] +set_property PACKAGE_PIN AE16 [get_ports {CLK_PLL_SDATA}] +set_property PACKAGE_PIN AE18 [get_ports {CLK_PLL_SLE}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_PLL_*}] +# +# Set pull-up on CLK_MUX_OUT to make the bitstream compatible with Rev A, where +# the signal doesn't exist. +set_property PACKAGE_PIN AH18 [get_ports {CLK_MUX_OUT}] +set_property IOSTANDARD LVCMOS33 [get_ports {CLK_MUX_OUT}] +set_property PULLUP TRUE [get_ports {CLK_MUX_OUT}] + + +############################################################################ +##FIXME: Remove this? + +## PS DDR +#set_property PACKAGE_PIN K25 [get_ports DDR_MODCLK_P] +#set_property PACKAGE_PIN J25 [get_ports DDR_MODCLK_N] +#set_property PACKAGE_PIN M22 [get_ports PS_DDR3_CKE] +#set_property PACKAGE_PIN F25 [get_ports PS_DDR3_RESET_N] +#set_property PACKAGE_PIN J24 [get_ports PS_DDR3_ADDR[14]] +#set_property PACKAGE_PIN H23 [get_ports PS_DDR3_ADDR[13]] +#set_property PACKAGE_PIN K23 [get_ports PS_DDR3_ADDR[12]] +#set_property PACKAGE_PIN H24 [get_ports PS_DDR3_ADDR[11]] +#set_property PACKAGE_PIN G26 [get_ports PS_DDR3_ADDR[10]] +#set_property PACKAGE_PIN J23 [get_ports PS_DDR3_ADDR[9]] +#set_property PACKAGE_PIN F27 [get_ports PS_DDR3_ADDR[8]] +#set_property PACKAGE_PIN K22 [get_ports PS_DDR3_ADDR[7]] +#set_property PACKAGE_PIN H26 [get_ports PS_DDR3_ADDR[6]] +#set_property PACKAGE_PIN G24 [get_ports PS_DDR3_ADDR[5]] +#set_property PACKAGE_PIN J26 [get_ports PS_DDR3_ADDR[4]] +#set_property PACKAGE_PIN G25 [get_ports PS_DDR3_ADDR[3]] +#set_property PACKAGE_PIN L27 [get_ports PS_DDR3_ADDR[2]] +#set_property PACKAGE_PIN K26 [get_ports PS_DDR3_ADDR[1]] +#set_property PACKAGE_PIN L25 [get_ports PS_DDR3_ADDR[0]] +#set_property PACKAGE_PIN K28 [get_ports PS_DDR3_DM[3]] +#set_property PACKAGE_PIN H29 [get_ports PS_DDR3_DM[2]] +#set_property PACKAGE_PIN B30 [get_ports PS_DDR3_DM[1]] +#set_property PACKAGE_PIN C27 [get_ports PS_DDR3_DM[0]] +#set_property PACKAGE_PIN M25 [get_ports PS_DDR3_BA[2]] +#set_property PACKAGE_PIN M26 [get_ports PS_DDR3_BA[1]] +#set_property PACKAGE_PIN M27 [get_ports PS_DDR3_BA[0]] +#set_property PACKAGE_PIN L28 [get_ports PS_DDR3_DQS_P[3]] +#set_property PACKAGE_PIN G29 [get_ports PS_DDR3_DQS_P[2]] +#set_property PACKAGE_PIN C29 [get_ports PS_DDR3_DQS_P[1]] +#set_property PACKAGE_PIN C26 [get_ports PS_DDR3_DQS_P[0]] +#set_property PACKAGE_PIN L29 [get_ports PS_DDR3_DQS_N[3]] +#set_property PACKAGE_PIN F29 [get_ports PS_DDR3_DQS_N[2]] +#set_property PACKAGE_PIN B29 [get_ports PS_DDR3_DQS_N[1]] +#set_property PACKAGE_PIN B26 [get_ports PS_DDR3_DQS_N[0]] +#set_property PACKAGE_PIN M30 [get_ports PS_DDR3_DQ[31]] +#set_property PACKAGE_PIN L30 [get_ports PS_DDR3_DQ[30]] +#set_property PACKAGE_PIN M29 [get_ports PS_DDR3_DQ[29]] +#set_property PACKAGE_PIN K30 [get_ports PS_DDR3_DQ[28]] +#set_property PACKAGE_PIN J28 [get_ports PS_DDR3_DQ[27]] +#set_property PACKAGE_PIN J30 [get_ports PS_DDR3_DQ[26]] +#set_property PACKAGE_PIN K27 [get_ports PS_DDR3_DQ[25]] +#set_property PACKAGE_PIN J29 [get_ports PS_DDR3_DQ[24]] +#set_property PACKAGE_PIN F30 [get_ports PS_DDR3_DQ[23]] +#set_property PACKAGE_PIN G30 [get_ports PS_DDR3_DQ[22]] +#set_property PACKAGE_PIN F28 [get_ports PS_DDR3_DQ[21]] +#set_property PACKAGE_PIN E30 [get_ports PS_DDR3_DQ[20]] +#set_property PACKAGE_PIN E28 [get_ports PS_DDR3_DQ[19]] +#set_property PACKAGE_PIN H28 [get_ports PS_DDR3_DQ[18]] +#set_property PACKAGE_PIN G27 [get_ports PS_DDR3_DQ[17]] +#set_property PACKAGE_PIN H27 [get_ports PS_DDR3_DQ[16]] +#set_property PACKAGE_PIN D29 [get_ports PS_DDR3_DQ[15]] +#set_property PACKAGE_PIN D28 [get_ports PS_DDR3_DQ[14]] +#set_property PACKAGE_PIN D30 [get_ports PS_DDR3_DQ[13]] +#set_property PACKAGE_PIN C28 [get_ports PS_DDR3_DQ[12]] +#set_property PACKAGE_PIN A28 [get_ports PS_DDR3_DQ[11]] +#set_property PACKAGE_PIN A30 [get_ports PS_DDR3_DQ[10]] +#set_property PACKAGE_PIN A27 [get_ports PS_DDR3_DQ[9]] +#set_property PACKAGE_PIN A29 [get_ports PS_DDR3_DQ[8]] +#set_property PACKAGE_PIN E27 [get_ports PS_DDR3_DQ[7]] +#set_property PACKAGE_PIN D26 [get_ports PS_DDR3_DQ[6]] +#set_property PACKAGE_PIN E26 [get_ports PS_DDR3_DQ[5]] +#set_property PACKAGE_PIN B25 [get_ports PS_DDR3_DQ[4]] +#set_property PACKAGE_PIN D25 [get_ports PS_DDR3_DQ[3]] +#set_property PACKAGE_PIN B27 [get_ports PS_DDR3_DQ[2]] +#set_property PACKAGE_PIN E25 [get_ports PS_DDR3_DQ[1]] +#set_property PACKAGE_PIN A25 [get_ports PS_DDR3_DQ[0]] +#set_property PACKAGE_PIN L23 [get_ports PS_DDR3_ODT] +#set_property PACKAGE_PIN N21 [get_ports PS_DDR3_VRN] +#set_property PACKAGE_PIN M21 [get_ports PS_DDR3_VRP] +#set_property PACKAGE_PIN N23 [get_ports PS_DDR3_WE_N] +#set_property PACKAGE_PIN N22 [get_ports PS_DDR3_CS_N] +#set_property PACKAGE_PIN M24 [get_ports PS_DDR3_CAS_N] +#set_property PACKAGE_PIN N24 [get_ports PS_DDR3_RAS_N] + diff --git a/fpga/usrp3/top/e320/mb_timing.xdc b/fpga/usrp3/top/e320/mb_timing.xdc new file mode 100644 index 000000000..3b77cad2d --- /dev/null +++ b/fpga/usrp3/top/e320/mb_timing.xdc @@ -0,0 +1,360 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Description: Timing constraints for the USRP E320 +# + + +############################################################################### +# Input Clocks +############################################################################### + +# External Reference Clock +set REF_CLK_PERIOD 50.00 +create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports CLK_REF_RAW] + +# Radio clock from AD9361 +set rx_clk_period 8.138 +create_clock -name rx_clk -period $rx_clk_period [get_ports RX_CLK_P] + +# 1 Gigabit Ethernet Reference Clock +create_clock -name ge_clk -period 8.000 [get_ports CLK_MGT_125M_P] + +# 10 Gigabit and Aurora Reference Clock +create_clock -name xge_clk -period 6.400 [get_ports CLK_MGT_156_25M_P] + +# Derived radio clocks (two mutually-exclusive clocks using a BUFGMUX) +create_generated_clock -name radio_clk_1x \ + -divide_by 4 \ + -add \ + -master_clock rx_clk \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_2x_bufr/O] \ + [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] +create_generated_clock -name radio_clk_2x \ + -divide_by 2 \ + -add \ + -master_clock rx_clk \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_input_lvds_i0/sdr_clk_bufr/O] \ + [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O] +set_clock_groups -physically_exclusive -group radio_clk_1x -group radio_clk_2x + + + +############################################################################### +# Rename Clocks +############################################################################### + +create_clock -name clk100 \ + -period [get_property PERIOD [get_clocks clk_fpga_0]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]] +set_input_jitter clk100 0.3 + +create_clock -name clk40 \ + -period [get_property PERIOD [get_clocks clk_fpga_1]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]] +set_input_jitter clk40 0.75 + +create_clock -name meas_clk_ref \ + -period [get_property PERIOD [get_clocks clk_fpga_2]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]] +set_input_jitter meas_clk_ref 0.18 + +create_clock -name bus_clk \ + -period [get_property PERIOD [get_clocks clk_fpga_3]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]] +set_input_jitter bus_clk 0.15 + +# DMA Clock +create_generated_clock -name ddr3_dma_clk \ + [get_pins {e320_clocking_i/mmcm_adv_inst/CLKOUT0}] + + + +############################################################################### +# Clock Crossings +############################################################################### + +set DDR3_UI_CLK_PERIOD [get_property period [get_clocks ddr3_ui_clk]] +set RADIO_CLK_1X_PERIOD [get_property period [get_clocks radio_clk_1x]] +set RADIO_CLK_2X_PERIOD [get_property period [get_clocks radio_clk_2x]] +set XGE_CLK_PERIOD [get_property period [get_clocks xge_clk]] + +# XADC temperature +set_max_delay -from [get_pins tempmon_i/device_temp_r_reg[*]/C] -to [get_clocks ddr3_ui_clk] $DDR3_UI_CLK_PERIOD -datapath_only + +# GPIO muxing +set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_1x] $RADIO_CLK_1X_PERIOD -datapath_only +set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_2x] $RADIO_CLK_2X_PERIOD -datapath_only + +# Codec reset +set_max_delay -from [get_pins e320_core_i/dboard_ctrl_reg[2]/C] -to [get_clocks radio_clk_1x_1] $RADIO_CLK_1X_PERIOD -datapath_only + +# Power-on reset +set_max_delay -from [get_pins por_gen/por_rst_reg/C] -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only + +# SFP MDIO data and clock signal crossings. These are double synchronized in +# the Xilinx MDIO IP. +set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdio_out_reg/C] \ + -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only +set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdc_reg/C] \ + -to [get_clocks xge_clk] $XGE_CLK_PERIOD -datapath_only + + + +############################################################################### +# False Paths +############################################################################### + +# Synchronizer core false paths +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/S}] + + +# MIG core reset +# According to Xilinx AR 61112, it is safe to make sys_rst a false path. +set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ + -to [get_clocks ddr3_ui_clk] +set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \ + -to [get_clocks ddr3_ui_clk_2x] + +# USR_ACCESS build date +set_false_path -through [get_pins usr_access_i/DATA[*]] + + + +############################################################################### +# PPS Input Timing +############################################################################### + +# The external PPS is synchronous to the external reference clock. We want to +# allow for 5 ns of setup and 5 ns of hold at the external connectors of the +# device. +set t_ext_setup 5.0 +set t_ext_hold 5.0 + +# Board delays for external REF/PPS +set t_ext_pps_to_fpga(min) 1.673 ; # Delay from external pin of PPS to FPGA +set t_ext_pps_to_fpga(max) 5.011 +set t_ext_ref_to_fpga(min) 1.452 ; # Delay from external pin of reference clock to FPGA +set t_ext_ref_to_fpga(max) 4.000 + +# Calculate the needed setup and hold at FPGA for external PPS, taking into +# account worst-case clock and data path skew. +set t_ext_fpga_setup [expr $t_ext_setup + ($t_ext_ref_to_fpga(min) - $t_ext_pps_to_fpga(max))] +set t_ext_fpga_hold [expr $t_ext_hold + ($t_ext_pps_to_fpga(min) - $t_ext_ref_to_fpga(max))] + +set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_ext_fpga_setup] [get_ports CLK_SYNC_EXT] +set_input_delay -clock ref_clk -min $t_ext_fpga_hold [get_ports CLK_SYNC_EXT] + + +# The GPS provides 2 ns setup and 2 ns of hold around the rising clock edge +set t_int_setup 2.0 +set t_int_hold 2.0 + +# Board delays for internal REF/PPS +set t_int_pps_to_fpga(min) 0.359 ; # Delay from PPS output of GPS to FPGA +set t_int_pps_to_fpga(max) 0.438 +set t_int_ref_to_fpga(min) 1.699 ; # Delay from reference clock output of GPS to FPGA +set t_int_ref_to_fpga(max) 3.149 + +# Calculate the needed setup and hold at FPGA for internal PPS, taking into +# account worst-case clock and data path skew. +set t_int_fpga_setup [expr $t_int_setup + ($t_int_ref_to_fpga(min) - $t_int_pps_to_fpga(max))] +set t_int_fpga_hold [expr $t_int_hold + ($t_int_pps_to_fpga(min) - $t_int_ref_to_fpga(max))] + +set_input_delay -clock ref_clk -max [expr $REF_CLK_PERIOD - $t_int_fpga_setup] [get_ports CLK_SYNC_INT] +set_input_delay -clock ref_clk -min $t_int_fpga_hold [get_ports CLK_SYNC_INT] + + + +############################################################################### +# LVDS Interface +############################################################################### + +# LVDS interface is source synchronous DDR. tPCB numbers are taken from +# HyperLynx for the Rev B PCB. 10 ps was added to each PCB delay for additional +# margin. + +# From the AD9361 data sheet +set tDDRX(min) 0.25 +set tDDRX(max) 1.25 +set tSTX(min) 1.0 +set tHTX(min) 0.0 + +# Other timing parameters +set tCP2X(min) [expr 0.45 * $rx_clk_period] ; # Worst-case bit period +set tTrns(max) 0.220 ; # Amount of time it takes an input to transition + +# Input timing parameters +set tPCB_RX(max) 0.058 ; # Max delay by which the clock trace is longer than the data trace +set tPCB_RX(min) -0.059 ; # Min delay by which the clock trace is longer than the data trace +set tSetupIn [expr $tCP2X(min) - $tDDRX(max) + $tPCB_RX(min)] +set tHoldIn [expr $tDDRX(min) - $tTrns(max) - $tPCB_RX(max)] + +# Input Setup/Hold (Rising Clock Edge) +set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] +set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] + +# Input Setup/Hold (Falling Clock Edge) +set_input_delay -clock [get_clocks rx_clk] -max [expr $tCP2X(min) - $tSetupIn] [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay +set_input_delay -clock [get_clocks rx_clk] -min $tHoldIn [get_ports {RX_DATA_*[*] RX_FRAME_*}] -clock_fall -add_delay + + +# Output timing parameters +set tPCB_TX(max) 0.066 ; # Max delay by which the clock trace is longer than the data trace +set tPCB_TX(min) -0.049 ; # Min delay by which the clock trace is longer than the data trace +set tSetupOut [expr $tSTX(min) - $tPCB_TX(min)] +set tHoldOut [expr $tHTX(min) + $tPCB_TX(max)] + +# Create tx_clk (FB_CLK) +create_generated_clock \ + -name tx_clk \ + -multiply_by 1 \ + -source [get_pins cat_io_lvds_dual_mode_i0/cat_io_lvds_i0/cat_output_lvds_i0/ddr_clk_oserdese2/CLK] \ + [get_ports TX_CLK_P] + +# Output Setup +set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] +set_output_delay -clock [get_clocks tx_clk] -max $tSetupOut [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay + +# Output Hold +set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] +set_output_delay -clock [get_clocks tx_clk] -min [expr -$tHoldOut] [get_ports {TX_DATA_*[*] TX_FRAME_*}] -clock_fall -add_delay + + + +############################################################################### +# SPI +############################################################################### + +# Xilinx doesn't allow you to fully constrain EMIO because the internal SPI +# clock is not accessible. So delay constraints are used to limit the delays to +# compatible values. + +# Transceiver SPI +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \ + -to [get_ports XCVR_SPI_MOSI] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \ + -to [get_ports XCVR_SPI_CLK] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]] \ + -to [get_ports XCVR_SPI_CS_N] 6.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 +# +set_max_delay -from [get_ports XCVR_SPI_MISO] \ + -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 4.0 -datapath_only +set_min_delay -from [get_ports XCVR_SPI_MISO] -to [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 0.0 + +# Clock synthesizer SPI +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1MO] \ + -to [get_ports CLK_PLL_SDATA] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_MOSI] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SCLKO] \ + -to [get_ports CLK_PLL_SCLK] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CLK] 0.0 +# +set_max_delay -from [get_pins e320_ps_bd_i/processing_system7_0/inst/PS7_i/EMIOSPI1SSON[0]] \ + -to [get_ports CLK_PLL_SLE] 9.0 -datapath_only +set_min_delay -to [get_ports XCVR_SPI_CS_N] 0.0 + + + +############################################################################### +# Miscellaneous I/O Constraints +############################################################################### + +# Transceiver +set_max_delay -to [get_ports XCVR_RESET_N] 50.0 +set_min_delay -to [get_ports XCVR_RESET_N] 0.0 +# +set_max_delay -from [get_ports XCVR_CTRL_OUT[*]] 5.0 -datapath_only +set_min_delay -from [get_ports XCVR_CTRL_OUT[*]] 0.0 + +# GPIO +set_max_delay -from [get_ports GPIO_PREBUFF[*]] 5.0 -datapath_only +set_min_delay -from [get_ports GPIO_PREBUFF[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_DIR[*]]] \ + -to [get_ports GPIO_DIR[*]] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_DIR[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_PREBUFF[*]]] \ + -to [get_ports GPIO_PREBUFF[*]] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_PREBUFF[*]] 0.0 +# +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports GPIO_OE_N]] \ + -to [get_ports GPIO_OE_N] 8.0 -datapath_only +set_min_delay -to [get_ports GPIO_OE_N] 0.0 +# +set_max_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 50.0 +set_min_delay -to [get_ports {EN_GPIO_2V5 EN_GPIO_3V3 EN_GPIO_VAR_SUPPLY}] 0.0 + +# GPS +set_max_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 10.0 -datapath_only +set_min_delay -from [get_ports {GPS_ALARM GPS_LOCK GPS_PHASELOCK GPS_SURVEY GPS_WARMUP}] 0.0 +# +set_max_delay -to [get_ports GPS_INITSURV_N] 50.0 +set_min_delay -to [get_ports GPS_INITSURV_N] 0.0 +set_max_delay -to [get_ports GPS_RST_N] 50.0 +set_min_delay -to [get_ports GPS_RST_N] 0.0 +# +set_max_delay -to [get_ports CLK_GPS_PWR_EN] 50.0 +set_min_delay -to [get_ports CLK_GPS_PWR_EN] 0.0 + +# Clock Control +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports CLK_REF_SEL]] \ + -to [get_ports CLK_REF_SEL] 8.0 -datapath_only +set_min_delay -to [get_ports CLK_REF_SEL] 0.0 +# +set_max_delay -from [get_ports CLK_MUX_OUT] 5.0 -datapath_only +set_min_delay -from [get_ports CLK_MUX_OUT] 0.0 + +# DDR3 +set_max_delay -to [get_ports ddr3_reset_n] 50.0 +set_min_delay -to [get_ports ddr3_reset_n] 0.0 + +# LEDs +set_max_delay -to [get_ports RX1_GRN_ENA] 50.0 +set_min_delay -to [get_ports RX1_GRN_ENA] 0.0 +set_max_delay -to [get_ports TX1_RED_ENA] 50.0 +set_min_delay -to [get_ports TX1_RED_ENA] 0.0 +set_max_delay -to [get_ports TXRX1_GRN_ENA] 50.0 +set_min_delay -to [get_ports TXRX1_GRN_ENA] 0.0 +set_max_delay -to [get_ports RX2_GRN_ENA] 50.0 +set_min_delay -to [get_ports RX2_GRN_ENA] 0.0 +set_max_delay -to [get_ports TX2_RED_ENA] 50.0 +set_min_delay -to [get_ports TX2_RED_ENA] 0.0 +set_max_delay -to [get_ports TXRX2_GRN_ENA] 50.0 +set_min_delay -to [get_ports TXRX2_GRN_ENA] 0.0 +# +set_max_delay -to [get_ports LED_ACT1] 50.0 +set_min_delay -to [get_ports LED_ACT1] 0.0 +set_max_delay -to [get_ports LED_LINK1] 50.0 +set_min_delay -to [get_ports LED_LINK1] 0.0 + +# Control Filters +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports FE*_SEL[*]]] \ + -to [get_ports FE*_SEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_SEL[*]]] \ + -to [get_ports RX*_SEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports RX*_BSEL[*]]] \ + -to [get_ports RX*_BSEL[*]] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX*_BSEL[*]]] \ + -to [get_ports TX*_BSEL[*]] 10.0 -datapath_only + +# PA Control +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_HFAMP*_ENA]] \ + -to [get_ports TX_HFAMP*_ENA] 10.0 -datapath_only +set_max_delay -from [all_fanin -only_cells -startpoints_only -flat [get_ports TX_LFAMP*_ENA]] \ + -to [get_ports TX_LFAMP*_ENA] 10.0 -datapath_only + +# SFP +set_max_delay -from [get_ports SFP1_RXLOS] 50.0 +set_min_delay -from [get_ports SFP1_RXLOS] 0.0 +set_max_delay -to [get_ports SFP1_TXDISABLE] 50.0 +set_min_delay -to [get_ports SFP1_TXDISABLE] 0.0 diff --git a/fpga/usrp3/top/e320/n3xx_mgt_io_core.v b/fpga/usrp3/top/e320/n3xx_mgt_io_core.v new file mode 100644 index 000000000..aa702775e --- /dev/null +++ b/fpga/usrp3/top/e320/n3xx_mgt_io_core.v @@ -0,0 +1,654 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: e320_mgt_io_core +// Description: +// Encapsulates the PSC/PMA, the MAC layer and the control interface +// for 1GbE, 10GbE and Aurora +// +////////////////////////////////////////////////////////////////////// + +module n3xx_mgt_io_core #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora, Disabled} + parameter [13:0] REG_BASE = 14'h0, + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0 +)( + // Resets + input areset, + input bus_rst, + // Clocks + input gt_refclk, + input gb_refclk, + input misc_clk, + input bus_clk, + // SFP high-speed IO + output txp, + output txn, + input rxp, + input rxn, + // SFP low-speed IO + input sfpp_rxlos, + input sfpp_tx_fault, + output sfpp_tx_disable, + // Data port: Ethernet TX + input [63:0] s_axis_tdata, + input [3:0] s_axis_tuser, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // Data port: Ethernet RX + output [63:0] m_axis_tdata, + output [3:0] m_axis_tuser, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // Register port + input reg_wr_req, + input [REG_AWIDTH-1:0] reg_wr_addr, + input [REG_DWIDTH-1:0] reg_wr_data, + input reg_rd_req, + input [REG_AWIDTH-1:0] reg_rd_addr, + output reg_rd_resp, + output [REG_DWIDTH-1:0] reg_rd_data, + // Misc + output [31:0] port_info, + output link_up, + output reg activity +); + + //----------------------------------------------------------------- + // Registers + //----------------------------------------------------------------- + localparam [7:0] COMPAT_NUM = 8'd2; + + // Common registers + localparam REG_PORT_INFO = REG_BASE + 'h0; + localparam REG_MAC_CTRL_STATUS = REG_BASE + 'h4; + localparam REG_PHY_CTRL_STATUS = REG_BASE + 'h8; + localparam REG_MAC_LED_CTL = REG_BASE + 'hC; + + // Ethernet specific + localparam REG_ETH_MDIO_BASE = REG_BASE + 'h10; + // Aurora specific + localparam REG_AURORA_OVERRUNS = REG_BASE + 'h20; + localparam REG_CHECKSUM_ERRORS = REG_BASE + 'h24; + localparam REG_BIST_CHECKER_SAMPS = REG_BASE + 'h28; + localparam REG_BIST_CHECKER_ERRORS = REG_BASE + 'h2C; + + wire reg_rd_resp_mdio; + reg reg_rd_resp_glob = 1'b0; + wire [REG_DWIDTH-1:0] reg_rd_data_mdio; + reg [REG_DWIDTH-1:0] reg_rd_data_glob = 32'h0; + + // Protocol specific constants + wire [7:0] mgt_protocol; + wire [31:0] mac_ctrl_rst_val, phy_ctrl_rst_val; + wire [1:0] mac_led_ctl_rst_val = 2'h0; + + // Flush logic: If the link is not up, we will flush all packets coming from + // the device. This avoids the MAC backpressuring when the PHY is down. + // The device will always send discovery packets to the transports during + // initialization, and they have no way of knowing if it's safe to travel + // down this route. c2mac == "CHDR to MAC" + wire [63:0] c2mac_tdata; + wire [3:0] c2mac_tuser; + wire c2mac_tlast; + wire c2mac_tvalid; + wire c2mac_tready; + + axis_packet_flush #( + .WIDTH(64+3), // tdata + tuser + .TIMEOUT_W(1), // Not using timeout + .FLUSH_PARTIAL_PKTS(0), + .PIPELINE("NONE") + ) linkup_flush ( + .clk(bus_clk), + .reset(bus_rst), + .enable(~link_up), // enable flushing when link down + .timeout(1'b0), + .flushing(/* not required */), + .done(/* not required */), + // Input from device/crossbar + .s_axis_tdata ({s_axis_tuser, s_axis_tdata}), + .s_axis_tlast (s_axis_tlast), + .s_axis_tvalid (s_axis_tvalid), + .s_axis_tready (s_axis_tready), + // Output to MAC + .m_axis_tdata ({c2mac_tuser, c2mac_tdata}), + .m_axis_tlast (c2mac_tlast), + .m_axis_tvalid (c2mac_tvalid), + .m_axis_tready (c2mac_tready) + ); + + generate + if (PROTOCOL == "Aurora") begin + assign mgt_protocol = 8'd3; + assign mac_ctrl_rst_val = 32'h0; + assign phy_ctrl_rst_val = 32'h0; + end else if (PROTOCOL == "10GbE") begin + assign mgt_protocol = 8'd2; + assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset + assign phy_ctrl_rst_val = 32'h0; + end else if (PROTOCOL == "1GbE") begin + assign mgt_protocol = 8'd1; + assign mac_ctrl_rst_val = {31'h0, 1'b1}; // tx_enable on reset + assign phy_ctrl_rst_val = 32'h0; + end else begin + assign mgt_protocol = 8'd0; + assign mac_ctrl_rst_val = 32'h0; + assign phy_ctrl_rst_val = 32'h0; + end + endgenerate + + // Writable registers + reg [31:0] mac_ctrl_reg = 32'h0; + reg [31:0] phy_ctrl_reg = 32'h0; + reg [1:0] mac_led_ctl = 2'h0; + + always @(posedge bus_clk) begin + if (bus_rst) begin + mac_ctrl_reg <= mac_ctrl_rst_val; + phy_ctrl_reg <= phy_ctrl_rst_val; + mac_led_ctl <= mac_led_ctl_rst_val; + end else if (reg_wr_req) begin + case(reg_wr_addr) + REG_MAC_CTRL_STATUS: + mac_ctrl_reg <= reg_wr_data; + REG_PHY_CTRL_STATUS: + phy_ctrl_reg <= reg_wr_data; + REG_MAC_LED_CTL: + mac_led_ctl <= reg_wr_data[1:0]; + endcase + end + end + + // Readable registers + wire [31:0] overruns; + wire [31:0] checksum_errors; + wire [47:0] bist_checker_samps; + wire [47:0] bist_checker_errors; + wire [31:0] mac_status, phy_status; + wire [31:0] mac_status_bclk, phy_status_bclk; + + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, mgt_protocol, PORTNUM}; + + always @(posedge bus_clk) begin + // No reset handling needed for readback + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + case(reg_rd_addr) + REG_PORT_INFO: + reg_rd_data_glob <= port_info; + REG_MAC_CTRL_STATUS: + reg_rd_data_glob <= mac_status_bclk; + REG_PHY_CTRL_STATUS: + reg_rd_data_glob <= phy_status_bclk; + REG_MAC_LED_CTL: + reg_rd_data_glob <= {30'd0, mac_led_ctl}; + REG_AURORA_OVERRUNS: + reg_rd_data_glob <= overruns; + REG_CHECKSUM_ERRORS: + reg_rd_data_glob <= checksum_errors; + REG_BIST_CHECKER_SAMPS: + reg_rd_data_glob <= bist_checker_samps[47:16]; //Scale num samples by 2^16 + REG_BIST_CHECKER_ERRORS: + reg_rd_data_glob <= bist_checker_errors[31:0]; //Don't scale errors + default: + reg_rd_resp_glob <= 1'b0; + endcase + end if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + + synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) mac_status_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(mac_status), .out(mac_status_bclk) + ); + + synchronizer #( .STAGES(2), .WIDTH(32), .INITIAL_VAL(32'h0) ) phy_status_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(phy_status), .out(phy_status_bclk) + ); + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_mdio, reg_rd_resp_glob}), + .sla_rd_data({reg_rd_data_mdio, reg_rd_data_glob}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + //----------------------------------------------------------------- + // Ethernet Specific: MDIO + //----------------------------------------------------------------- + + wire mdc, mdio_m2s, mdio_s2m, mdio_s2m_sync; + generate + if ((PROTOCOL == "10GbE" || PROTOCOL == "1GbE") && (MDIO_EN == 1)) begin + mdio_master #( + .REG_BASE (REG_ETH_MDIO_BASE), + .REG_AWIDTH (REG_AWIDTH), + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (bus_clk), + .rst (bus_rst), + .mdc (mdc), + .mdio_in (mdio_s2m_sync), + .mdio_out (mdio_m2s), + .mdio_tri (), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_data (reg_rd_data_mdio), + .reg_rd_resp (reg_rd_resp_mdio) + ); + + // We can cross mdio_s2m into the bus_clk domain. A synchronizer is safe + // here because the bit is inherently async + synchronizer #(.INITIAL_VAL(1'b0)) mdio_s2m_sync_i ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mdio_s2m), .out(mdio_s2m_sync) + ); + end else begin + assign mdc = 1'b0; + assign mdio_m2s = 1'b0; + assign reg_rd_resp_mdio = 1'b0; + assign reg_rd_data_mdio = 32'h0; + end + endgenerate + + generate + if (PROTOCOL == "10GbE") begin + //----------------------------------------------------------------- + // 10 Gigabit Ethernet + //----------------------------------------------------------------- + wire [63:0] xgmii_txd; + wire [7:0] xgmii_txc; + wire [63:0] xgmii_rxd; + wire [7:0] xgmii_rxc; + wire xge_phy_resetdone; + + ten_gige_phy ten_gige_phy_i + ( + // Clocks and Reset + .areset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .refclk(gt_refclk), // Transciever reference clock: 156.25MHz + .clk156(gb_refclk), // Globally buffered core clock: 156.25MHz + .dclk(misc_clk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(1'b0), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable) + ); + + xge_mac_wrapper #( + .PORTNUM(PORTNUM), + .WISHBONE(0) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(gb_refclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(bus_clk), + .sys_rst(bus_rst), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // Other + .phy_ready(xge_phy_resetdone), + .ctrl_tx_enable(mac_ctrl_reg[0]), + .status_crc_error(mac_status[0]), + .status_fragment_error(mac_status[1]), + .status_txdfifo_ovflow(mac_status[2]), + .status_txdfifo_udflow(mac_status[3]), + .status_rxdfifo_ovflow(mac_status[4]), + .status_rxdfifo_udflow(mac_status[5]), + .status_pause_frame_rx(mac_status[6]), + .status_local_fault(mac_status[7]), + .status_remote_fault(mac_status[8]), + .wb_ack_o(), + .wb_dat_o(), + .wb_adr_i(1'b0), + .wb_clk_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_i(1'b0), + .wb_rst_i(1'b0), + .wb_stb_i(1'b0), + .wb_we_i (1'b0), + .wb_int_o() + ); + + assign phy_status[31:8] = 24'h0; + assign mac_status[31:9] = 23'h0; + assign link_up = phy_status_bclk[0]; + + end else if (PROTOCOL == "1GbE") begin + + //----------------------------------------------------------------- + // 1 Gigabit Ethernet + //----------------------------------------------------------------- + wire [7:0] gmii_txd, gmii_rxd; + wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; + wire gmii_clk; + wire gt0_qplloutclk, gt0_qplloutrefclk; //unused in 7-series Zynq + + assign gt0_qplloutclk = 1'b0; + assign gt0_qplloutrefclk = 1'b0; + assign sfpp_tx_disable = 1'b0; // Always on. + + one_gige_phy one_gige_phy_i + ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i + ( + .clk125(gmii_clk), + .reset(areset), + + .GMII_GTX_CLK(), + .GMII_TX_EN(gmii_tx_en), + .GMII_TX_ER(gmii_tx_er), + .GMII_TXD(gmii_txd), + .GMII_RX_CLK(gmii_clk), + .GMII_RX_DV(gmii_rx_dv), + .GMII_RX_ER(gmii_rx_er), + .GMII_RXD(gmii_rxd), + + .sys_clk(bus_clk), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + + .wb_clk_i(1'b0), + .wb_rst_i(1'b0), + .wb_adr_i(8'h0), + .wb_dat_i(32'h0), + .wb_we_i(1'b0), + .wb_stb_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_o(), + .wb_ack_o(), + .wb_int_o(), + .mdc(), + .mdio_out(1'b0), + .mdio_tri(), + .mdio_in(), + .debug_tx(), + .debug_rx() + ); + + assign phy_status[31:16] = 16'h0; + assign mac_status[31:0] = 32'h0; + assign link_up = phy_status_bclk[0]; + + assign gt_tx_out_clk_unbuf = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + //----------------------------------------------------------------- + // Aurora + //----------------------------------------------------------------- + wire user_clk, user_rst; + wire [63:0] m2p_tdata, p2m_tdata; + wire m2p_tvalid, m2p_tready, p2m_tvalid; + wire channel_up, hard_err, soft_err, mac_crit_err; + + wire bist_checker_en = mac_ctrl_reg[0]; + wire bist_gen_en = mac_ctrl_reg[1]; + wire bist_loopback_en = mac_ctrl_reg[2]; + wire [5:0] bist_gen_rate = mac_ctrl_reg[8:3]; + wire phy_areset = mac_ctrl_reg[9]; + wire mac_clear = mac_ctrl_reg[10]; + wire bist_checker_locked; + + assign sfpp_tx_disable = 1'b0; // Always on. + + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err) + ); + + aurora_axis_mac #( + .PHY_ENDIANNESS ("LITTLE"), + .PACKET_MODE (1), + .MAX_PACKET_SIZE(1024), + .BIST_ENABLED (1) + ) aurora_mac_i ( + // Clocks and resets + .phy_clk(user_clk), .phy_rst(user_rst), + .sys_clk(bus_clk), .sys_rst(bus_rst), + .clear(mac_clear), + // PHY Interface (Synchronous to phy_clk) + .phy_s_axis_tdata(p2m_tdata), + .phy_s_axis_tvalid(p2m_tvalid), + .phy_m_axis_tdata(m2p_tdata), + .phy_m_axis_tvalid(m2p_tvalid), + .phy_m_axis_tready(m2p_tready), + // User Interface (Synchronous to sys_clk) + .s_axis_tdata(c2mac_tdata), + .s_axis_tlast(c2mac_tlast), + .s_axis_tvalid(c2mac_tvalid), + .s_axis_tready(c2mac_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tlast(m_axis_tlast), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + // PHY Status Inputs (Synchronous to phy_clk) + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + // Status and Error Outputs (Synchronous to sys_clk) + .overruns(overruns), + .soft_errors(), + .checksum_errors(checksum_errors), + .critical_err(mac_crit_err), + // BIST Interface (Synchronous to sys_clk) + .bist_gen_en(bist_gen_en), + .bist_gen_rate(bist_gen_rate), + .bist_checker_en(bist_checker_en), + .bist_loopback_en(bist_loopback_en), + .bist_checker_locked(bist_checker_locked), + .bist_checker_samps(bist_checker_samps), + .bist_checker_errors(bist_checker_errors) + ); + + assign m_axis_tuser = 4'd0; + + wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk; + synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk)); + + reg [19:0] bist_lock_latency; + always @(posedge bus_clk) begin + if (!bist_checker_en && !bist_checker_locked) + bist_lock_latency <= 20'd0; + else if (bist_checker_en && !bist_checker_locked) + bist_lock_latency <= bist_lock_latency + 20'd1; + end + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + assign phy_status = {30'd0, hard_err, channel_up}; + assign mac_status = { + 6'h0, //[31:26] + mac_crit_err_latch, //[25] + 1'b1, //[24] + 1'b0, //[23] + 1'b0, //[22] + 1'b0, //[21] + 1'b0, //[20] + bist_lock_latency[19:4], //[19:4] + bist_checker_locked, //[3] + soft_err_bclk, //[2] + hard_err_bclk, //[1] + channel_up_bclk //[0] + }; + + assign link_up = channel_up_bclk; + + end else begin + + //----------------------------------------------------------------- + // Disabled + //----------------------------------------------------------------- + + assign phy_status = 'h0; + assign mac_status = 'h0; + assign link_up = 1'b0; + + assign sfpp_tx_disable = 1'b0; // Always on. + + assign c2mac_tready = 1'b1; + assign m_axis_tdata = 64'h0; + assign m_axis_tuser = 4'h0; + assign m_axis_tlast = 1'b0; + assign m_axis_tvalid = 1'b0; + + end + endgenerate + + wire identify_enable = mac_led_ctl[0]; + wire identify_value = mac_led_ctl[1]; + + //----------------------------------------------------------------- + // Activity detector + //----------------------------------------------------------------- + wire activity_int; + + pulse_stretch act_pulse_str_i ( + .clk(bus_clk), + .rst(bus_rst | ~link_up), + .pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)), + .pulse_stretched(activity_int) + ); + + always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int; + +endmodule diff --git a/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v b/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v new file mode 100644 index 000000000..5067b1727 --- /dev/null +++ b/fpga/usrp3/top/e320/n3xx_sfp_wrapper.v @@ -0,0 +1,484 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2017 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_sfp_wrapper +// Description: +// Reduces clutter at top level. +// - Aurora: wraps up sfpp_io, axil_regport and axi_dummy +// - 1/10G: wrapper around network interface +// +////////////////////////////////////////////////////////////////////// + +module n3xx_sfp_wrapper #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora, Disabled} + parameter DWIDTH = 32, + parameter AWIDTH = 14, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0, + parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0} +)( + // Resets + input areset, + input bus_rst, + + // Clocks + input gt_refclk, + input gb_refclk, + input misc_clk, + input bus_clk, + // FIXME: Merge E320 and N310 files + input user_clk, + input sync_clk, + + //Axi-lite + input s_axi_aclk, + input s_axi_aresetn, + input [AWIDTH-1:0] s_axi_awaddr, + input s_axi_awvalid, + output s_axi_awready, + + input [DWIDTH-1:0] s_axi_wdata, + input [DWIDTH/8-1:0] s_axi_wstrb, + input s_axi_wvalid, + output s_axi_wready, + + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + input [AWIDTH-1:0] s_axi_araddr, + input s_axi_arvalid, + output s_axi_arready, + + output [DWIDTH-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input s_axi_rready, + + // SFP high-speed IO + output txp, + output txn, + input rxp, + input rxn, + + // SFP low-speed IO + input sfpp_present_n, + input sfpp_rxlos, + input sfpp_tx_fault, + output sfpp_tx_disable, + + //GT Common + input qpllrefclklost, + input qplllock, + input qplloutclk, + input qplloutrefclk, + output qpllreset, + + //Aurora MMCM + input mmcm_locked, + output gt_pll_lock, + output gt_tx_out_clk_unbuf, + + // Vita router interface + output [63:0] e2v_tdata, + output e2v_tlast, + output e2v_tvalid, + input e2v_tready, + + input [63:0] v2e_tdata, + input v2e_tlast, + input v2e_tvalid, + output v2e_tready, + + // CPU + output [63:0] e2c_tdata, + output [7:0] e2c_tkeep, + output e2c_tlast, + output e2c_tvalid, + input e2c_tready, + + input [63:0] c2e_tdata, + input [7:0] c2e_tkeep, + input c2e_tlast, + input c2e_tvalid, + output c2e_tready, + + // MISC + output [31:0] port_info, + input [15:0] device_id, + + // Timebase Outputs + output sfp_pps, + output sfp_refclk, + + // Sideband White Rabbit Control + input wr_reset_n, + input wr_refclk, + + output wr_dac_sclk, + output wr_dac_din, + output wr_dac_clr_n, + output wr_dac_cs_n, + output wr_dac_ldac_n, + + output wr_eeprom_scl_o, + input wr_eeprom_scl_i, + output wr_eeprom_sda_o, + input wr_eeprom_sda_i, + + input wr_uart_rx, + output wr_uart_tx, + + // WR AXI Control + output wr_axi_aclk, + input wr_axi_aresetn, + input [31:0] wr_axi_awaddr, + input wr_axi_awvalid, + output wr_axi_awready, + input [DWIDTH-1:0] wr_axi_wdata, + input [DWIDTH/8-1:0] wr_axi_wstrb, + input wr_axi_wvalid, + output wr_axi_wready, + output [1:0] wr_axi_bresp, + output wr_axi_bvalid, + input wr_axi_bready, + input [31:0] wr_axi_araddr, + input wr_axi_arvalid, + output wr_axi_arready, + output [DWIDTH-1:0] wr_axi_rdata, + output [1:0] wr_axi_rresp, + output wr_axi_rvalid, + input wr_axi_rready, + output wr_axi_rlast, + + output link_up, + output activity + +); + + localparam REG_BASE_SFP_IO = 14'h0; + localparam REG_BASE_ETH_SWITCH = 14'h1000; + + // AXI4-Lite to RegPort (PS to PL Register Access) + wire reg_wr_req; + wire [AWIDTH-1:0] reg_wr_addr; + wire [DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp, reg_rd_resp_io, reg_rd_resp_eth_if; + wire [DWIDTH-1:0] reg_rd_data, reg_rd_data_io, reg_rd_data_eth_if; + + axil_regport_master #( + .DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) sfp_reg_mst_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}), + .sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + wire [63:0] sfpo_tdata, sfpi_tdata; + wire [3:0] sfpo_tuser, sfpi_tuser; + wire sfpo_tlast, sfpi_tlast, sfpo_tvalid, sfpi_tvalid, sfpo_tready, sfpi_tready; + + generate + if (PROTOCOL != "WhiteRabbit") begin + n3xx_mgt_io_core #( + .PROTOCOL (PROTOCOL), + .REG_BASE (REG_BASE_SFP_IO), + .REG_DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (AWIDTH), // Width of the address bus + .MDIO_EN (MDIO_EN), + .MDIO_PHYADDR (MDIO_PHYADDR), + .PORTNUM (PORTNUM) + ) mgt_io_i ( + //must reset all channels on quad when sfp1 gtx core is reset + .areset (areset), + .gt_refclk (gt_refclk), + .gb_refclk (gb_refclk), + .misc_clk (misc_clk), + + .bus_rst (bus_rst), + .bus_clk (bus_clk), + + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .sfpp_rxlos (sfpp_rxlos), + .sfpp_tx_fault (sfpp_tx_fault), + .sfpp_tx_disable(sfpp_tx_disable), + + //RegPort + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_io), + .reg_rd_data (reg_rd_data_io), + + // Vita to Ethernet + .s_axis_tdata (sfpi_tdata), + .s_axis_tuser (sfpi_tuser), + .s_axis_tlast (sfpi_tlast), + .s_axis_tvalid (sfpi_tvalid), + .s_axis_tready (sfpi_tready), + + // Ethernet to Vita + .m_axis_tdata (sfpo_tdata), + .m_axis_tuser (sfpo_tuser), + .m_axis_tlast (sfpo_tlast), + .m_axis_tvalid (sfpo_tvalid), + .m_axis_tready (sfpo_tready), + + .port_info (port_info), + .link_up (link_up), + .activity (activity) + ); + + end else begin + //--------------------------------------------------------------------------------- + // White Rabbit + //--------------------------------------------------------------------------------- + + wire wr_sfp_scl, wr_sfp_sda_o, wr_sfp_sda_i; + + n3xx_wr_top #( + .g_simulation(1'b0), // in std_logic + .g_dpram_size(131072/4), + .g_dpram_initf("../../../../bin/wrpc/wrc_phy16.bram") + ) wr_inst ( + .areset_n_i (wr_reset_n), // in std_logic; -- active low reset, optional + .wr_refclk_buf_i (wr_refclk), // in std_logic; -- 20MHz VCXO after IBUFGDS + .gige_refclk_buf_i (gt_refclk), // in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + .dac_sclk_o (wr_dac_sclk), // out std_logic; -- N3xx cWB-DAC-SCLK + .dac_din_o (wr_dac_din), // out std_logic; -- N3xx cWB-DAC-DIN + .dac_clr_n_o (wr_dac_clr_n), // out std_logic; -- N3xx cWB-DAC-nCLR + .dac_cs_n_o (wr_dac_cs_n), // out std_logic; -- N3xx cWB-DAC-nSYNC + .dac_ldac_n_o (wr_dac_ldac_n), // out std_logic; -- N3xx cWB-DAC-nLDAC + .LED_ACT (activity), // out std_logic; -- connect to SFP+ ACT + .LED_LINK (link_up), // out std_logic; -- connect to SFP+ LINK + .sfp_txp_o (txp), // out std_logic; + .sfp_txn_o (txn), // out std_logic; + .sfp_rxp_i (rxp), // in std_logic; + .sfp_rxn_i (rxn), // in std_logic; + .sfp_mod_def0_b (sfpp_present_n), // in std_logic; - sfp detect + .eeprom_scl_o (wr_eeprom_scl_o), + .eeprom_scl_i (wr_eeprom_scl_i), + .eeprom_sda_o (wr_eeprom_sda_o), + .eeprom_sda_i (wr_eeprom_sda_i), + .sfp_scl_o (wr_sfp_scl), + .sfp_scl_i (wr_sfp_scl), + .sfp_sda_o (wr_sfp_sda_o), + .sfp_sda_i (wr_sfp_sda_i), + .sfp_tx_fault_i (sfpp_tx_fault), // in std_logic; + .sfp_tx_disable_o (sfpp_tx_disable), // out std_logic; + .sfp_los_i (sfpp_rxlos), // in std_logic; + .wr_uart_rxd (wr_uart_rx), // in std_logic; + .wr_uart_txd (wr_uart_tx), // out std_logic; + + .s00_axi_aclk_o (wr_axi_aclk), + .s00_axi_aresetn (wr_axi_aresetn), + .s00_axi_awaddr (wr_axi_awaddr), + .s00_axi_awprot (3'b0), + .s00_axi_awvalid (wr_axi_awvalid), + .s00_axi_awready (wr_axi_awready), + .s00_axi_wdata (wr_axi_wdata), + .s00_axi_wstrb (wr_axi_wstrb), + .s00_axi_wvalid (wr_axi_wvalid), + .s00_axi_wready (wr_axi_wready), + .s00_axi_bresp (wr_axi_bresp), + .s00_axi_bvalid (wr_axi_bvalid), + .s00_axi_bready (wr_axi_bready), + .s00_axi_araddr (wr_axi_araddr), + .s00_axi_arprot (3'b0), + .s00_axi_arvalid (wr_axi_arvalid), + .s00_axi_arready (wr_axi_arready), + .s00_axi_rdata (wr_axi_rdata), + .s00_axi_rresp (wr_axi_rresp), + .s00_axi_rvalid (wr_axi_rvalid), + .s00_axi_rready (wr_axi_rready), + .s00_axi_rlast (wr_axi_rlast), + .axi_int_o (), + + .pps_o (sfp_pps), // out std_logic; + .clk_pps_o (sfp_refclk), // out std_logic; + .link_ok_o (), // out std_logic; + .clk_sys_locked_o (), // out std_logic; + .clk_dmtd_locked_o (), // out std_logic); + .wr_debug0_o (), + .wr_debug1_o () + ); + + // TEMPORARY mimic the AXGE SFP EEROM + sfp_eeprom sfp_eeprom_i ( + .clk_i(bus_clk), + .sfp_scl(wr_sfp_scl), + .sfp_sda_i(wr_sfp_sda_o), + .sfp_sda_o(wr_sfp_sda_i)); + + // Assign the port_info vector similarly to mgt_io_core + localparam [7:0] COMPAT_NUM = 8'd2; + localparam [7:0] MGT_PROTOCOL = 8'd4; + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM}; + + // Tie off unused outputs. + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + endgenerate + + generate + // Tie off the Ethernet switch for these protocols that do not use it. + if(PROTOCOL == "Aurora" || PROTOCOL == "Disabled" || PROTOCOL == "WhiteRabbit") begin + + //set unused wires to default value + assign e2c_tdata = 64'h0; + assign e2c_tkeep = 8'h0; + assign e2c_tlast = 1'b0; + assign e2c_tvalid = 1'b0; + assign c2e_tready = 1'b1; + + assign reg_rd_resp_eth_if = 1'b0; + assign reg_rd_data_eth_if = 'h0; + + end else begin + + wire [3:0] e2c_tuser; + wire [3:0] c2e_tuser; + + // In AXI Stream, tkeep is the byte qualifier that indicates + // whether the content of the associated byte + // of TDATA is processed as part of the data stream. + // tuser as used in eth_interface is the number of valid bytes + + // Converting tuser to tkeep for ingress packets + assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 + : (e2c_tuser == 4'd0) ? 8'b1111_1111 + : (e2c_tuser == 4'd1) ? 8'b0000_0001 + : (e2c_tuser == 4'd2) ? 8'b0000_0011 + : (e2c_tuser == 4'd3) ? 8'b0000_0111 + : (e2c_tuser == 4'd4) ? 8'b0000_1111 + : (e2c_tuser == 4'd5) ? 8'b0001_1111 + : (e2c_tuser == 4'd6) ? 8'b0011_1111 + : 8'b0111_1111; + + // Converting tkeep to tuser for egress packets + assign c2e_tuser = ~c2e_tlast ? 4'd0 + : (c2e_tkeep == 8'b1111_1111) ? 4'd0 + : (c2e_tkeep == 8'b0111_1111) ? 4'd7 + : (c2e_tkeep == 8'b0011_1111) ? 4'd6 + : (c2e_tkeep == 8'b0001_1111) ? 4'd5 + : (c2e_tkeep == 8'b0000_1111) ? 4'd4 + : (c2e_tkeep == 8'b0000_0111) ? 4'd3 + : (c2e_tkeep == 8'b0000_0011) ? 4'd2 + : (c2e_tkeep == 8'b0000_0001) ? 4'd1 + : 4'd0; + + + eth_interface #( + .PROTOVER (RFNOC_PROTOVER), + .MTU (10), + .NODE_INST (0), + .REG_AWIDTH (AWIDTH), + .BASE (REG_BASE_ETH_SWITCH) + ) eth_interface ( + .clk (bus_clk), + .reset (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_port (), + .eth_tx_tdata (sfpi_tdata), + .eth_tx_tuser (sfpi_tuser), + .eth_tx_tlast (sfpi_tlast), + .eth_tx_tvalid (sfpi_tvalid), + .eth_tx_tready (sfpi_tready), + .eth_rx_tdata (sfpo_tdata), + .eth_rx_tuser (sfpo_tuser), + .eth_rx_tlast (sfpo_tlast), + .eth_rx_tvalid (sfpo_tvalid), + .eth_rx_tready (sfpo_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + + end + endgenerate + +endmodule // n310_sfp_wrapper diff --git a/fpga/usrp3/top/e320/setupenv.sh b/fpga/usrp3/top/e320/setupenv.sh new file mode 100644 index 000000000..76bf520ed --- /dev/null +++ b/fpga/usrp3/top/e320/setupenv.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-E320" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["E320"]="zynq/xc7z045/ffg900/-3" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh diff --git a/fpga/usrp3/top/n3xx/.gitignore b/fpga/usrp3/top/n3xx/.gitignore new file mode 100644 index 000000000..1b0a8a728 --- /dev/null +++ b/fpga/usrp3/top/n3xx/.gitignore @@ -0,0 +1,8 @@ +build +build-* +isim* +fuse* +tmp* +*.log +*.jou +*impact* diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile new file mode 100644 index 000000000..5900b26d0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/Makefile @@ -0,0 +1,191 @@ +# +# Copyright 2016-2018 Ettus Research, a National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP N3XX FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga_.bit: Configuration bitstream with header +## build/usrp__fpga_.dts: Device tree source file +## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) + +# Debug Options +# Uncomment this line or add to make arg to omit radio_clk (sourced from db) and use bus_clk as radio_clk +# OPTIONS += NO_DB=1 +# Uncomment this line to add two example Aurora loopback lanes on the general NPIO bus. +# OPTIONS += NPIO_LANES=2 +# Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus. +# OPTIONS += QSFP_LANES=4 + +# Additional definitions specific to the various targets: +WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) +HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) +XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 USE_REPLAY=1 BUILD_10G=1 $(OPTIONS) +HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 USE_REPLAY=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) +XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 USE_REPLAY=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) +AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) +XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 USE_REPLAY=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) +AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 USE_REPLAY=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) + +# Defaults specific to the various targets: +N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex) +N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex) +N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n320_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex) +N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n300_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex) +N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=n310_bist_image_core.v DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= n3xx + +# vivado_build($1=Device, $2=Definitions, $3=Defaults) +# Device: N300, N310, or N320 +# Definitions: See above (*_DEFS) +# Defaults: See above (*_DEFAULTS) +vivado_build = make -f Makefile.n3xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream file..."; \ + cp build-$(1)_$(2)/n3xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \ + echo "Exporting build report..."; \ + cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \ + echo "Build DONE ... $(1)_$(2)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- + +all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target) + +##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N310_WX: build/usrp_n310_fpga_WX.dts + $(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,WX) + +##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N310_HG: build/usrp_n310_fpga_HG.dts + $(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,HG) + +##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N310_XG: build/usrp_n310_fpga_XG.dts + $(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,XG) + +##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +N310_HA: build/usrp_n310_fpga_HA.dts + $(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,HA) + +##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +N310_XA: build/usrp_n310_fpga_XA.dts + $(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS)) + $(call post_build,N310,XA) + +##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. +N310_AA: build/usrp_n310_fpga_AA.dts + $(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS)) + $(call post_build,N310,AA) + +##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N300_WX: build/usrp_n300_fpga_WX.dts + $(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,WX) + +##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N300_HG: build/usrp_n300_fpga_HG.dts + $(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,HG) + +##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N300_XG: build/usrp_n300_fpga_XG.dts + $(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,XG) + +##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +N300_HA: build/usrp_n300_fpga_HA.dts + $(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,HA) + +##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +N300_XA: build/usrp_n300_fpga_XA.dts + $(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS)) + $(call post_build,N300,XA) + +##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1. +N300_AA: build/usrp_n300_fpga_AA.dts + $(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS)) + $(call post_build,N300,AA) + +##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1. +N320_WX: build/usrp_n320_fpga_WX.dts + $(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,WX) + +##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N320_HG: build/usrp_n320_fpga_HG.dts + $(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,HG) + +##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1. +N320_XG: build/usrp_n320_fpga_XG.dts + $(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,XG) + +##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1. +N320_XQ: build/usrp_n320_fpga_XQ.dts + $(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,XQ) + +##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3. +N320_AQ: build/usrp_n320_fpga_AQ.dts + $(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS)) + $(call post_build,N320,AQ) + +build/%.dts: dts/%.dts dts/*.dtsi + -mkdir -p build + ${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $< + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-N3*_* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-N3*_* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc new file mode 100644 index 000000000..aea75a69a --- /dev/null +++ b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc @@ -0,0 +1,161 @@ +# +# Copyright 2008-2019 Ettus Research, a National Instruments Brand +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/simple_gemac/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/xge/Makefile.srcs +include $(LIB_DIR)/xge_interface/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/white_rabbit/wr_cores_v4_2/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/rh/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/mg/Makefile.srcs +include $(BASE_DIR)/n3xx/dboards/common/Makefile.srcs +# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and +# DUC, and of course the radio. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +# If out-of-tree modules want to be compiled into this image, then they need to +# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. +# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual +# source files. +include $(RFNOC_OOT_MAKEFILE_SRCS) + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## +TOP_SRCS = \ +n3xx_core.v \ +n3xx_mgt_channel_wrapper.v \ +n3xx_mgt_wrapper.v \ +n3xx_mgt_io_core.v \ +n3xx_clocking.v \ +n3xx_db_fe_core.v \ +WrapBufg.vhd \ +$(IMAGE_CORE) + +MB_CLOCKS_XDC = $(abspath mb_clocks.xdc) + +MB_XDC = \ +mb_timing.xdc \ +mb_pins.xdc + +ifdef BUILD_WR +MB_XDC += $(abspath n3xx_wr.xdc) +TOP_SRCS += \ +n3xx_wr_top.vhd \ +n3xx_serial_dac.vhd \ +n3xx_serial_dac_arb.vhd +endif + +ifdef BUILD_10G +MB_XDC += $(abspath n310_10ge.xdc) +endif + +ifdef BUILD_1G +MB_XDC += $(abspath n310_1ge.xdc) +endif + +ifdef BUILD_AURORA +MB_XDC += $(abspath n310_aurora.xdc) +endif + +ifndef NO_DRAM_FIFOS +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath n310_dram.xdc) +else +DRAM_SRCS = +endif + +ifdef N300 +DB_CLOCKS_XDC = +DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \ +$(MAGNESIUM_DB0_XDC) \ +$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS) +endif + +ifdef N310 +DB_CLOCKS_XDC = +DB_SRCS = $(MAGNESIUM_DB_TIMING_XDC) \ +$(MAGNESIUM_DB0_XDC) $(MAGNESIUM_DB1_XDC) \ +$(MAGNESIUM_TOP_SRCS) $(MAGNESIUM_DB_SRCS) +endif + +ifdef N320 +DB_CLOCKS_XDC = $(RHODIUM_DB_CLOCKS_XDC) +DB_SRCS = $(RHODIUM_DB_XDC) \ +$(RHODIUM_TOP_SRCS) $(RHODIUM_DB_SRCS) +endif + +DB_SRCS += $(DB_COMMON_SRCS) + +# The XDC files must be read in a specific order, motherboard first and then daughterboard, +# and the clocking XDC files must be before other XDC files. +# Outside of that, all the other sources can be read in any order desired. +DESIGN_SRCS = $(MB_CLOCKS_XDC) $(DB_CLOCKS_XDC) $(abspath $(MB_XDC)) $(DB_SRCS) \ +$(abspath $(TOP_SRCS)) $(AXI_SRCS) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \ +$(UDP_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \ +$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \ +$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \ +$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ +$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \ +$(WHITE_RABBIT_SRCS) \ +$(RFNOC_FRAMEWORK_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \ +$(RFNOC_BLOCK_RADIO_SRCS) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_n3xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/n3xx/WrapBufg.vhd b/fpga/usrp3/top/n3xx/WrapBufg.vhd new file mode 100644 index 000000000..1f3417658 --- /dev/null +++ b/fpga/usrp3/top/n3xx/WrapBufg.vhd @@ -0,0 +1,172 @@ +-------------------------------------------------------------------------------- +-- +-- File: WrapBufg.vhd +-- Author: Robert Atkinson +-- Original Project: RF-RIO +-- Date: 13 January 2012 +-- +-------------------------------------------------------------------------------- +-- Copyright 2012 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +-------------------------------------------------------------------------------- +-- +-- Purpose: This is a simple wrapper around a BUFG to make instantiating BUFGCTRLs +-- easier without a headache to relearn the port usage each time. This +-- wrapper only supports a single input clock. When disabled, the BUFG +-- output is zero. +-- +-------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library UNISIM; + use UNISIM.vcomponents.all; + + +entity WrapBufg is + generic( + -- ClkIn is selected by default if set to true, otherwise zero. + kEnableByDefault : boolean := false; + -- If kIgnore is set to true, then the BUFG will switch inputs whenever + -- the aCe signal changes as opposed to waiting for ClkIn to transition low. + kIgnore : boolean := false; + -- If aCe is asynchronous to ClkIn, set this generic to true and the select + -- lines of the BUFGCTRL will be used. If aCe is synchronous to ClkIn, then the CE pins + -- will be used - note that this requires that setup and hold times be met! If aCe is + -- synchronous to ClkIn but no timing relationship is really needed then set this to true. + kEnableIsAsync : boolean := false + ); + port( + -- Input clock + ClkIn : in std_logic; + -- Enable to the BUFG - this signal is treated either asynchronously + -- or synchronously based on the value of the kEnableIsAsync generic. + aCe : in std_logic; + -- Clock output + ClkOut : out std_logic + ); +end WrapBufg; + + +architecture rtl of WrapBufg is + + signal iCe0, + iCe1, + aSel0, + aSel1, + kIgnore0 : std_logic; + +begin + + -- From Data Sheet: + -- The BUFGCTRL is designed to switch between two clock inputs without the possibility of a + -- glitch. When the presently selected clock transitions from High to Low after S0 and S1 + -- changes, the output is kept Low until the other (to-be-selected) clock has transitioned from + -- High to Low. Then the new clock starts driving the output. The default configuration for + -- BUFGCTRL is falling edge sensitive and held at Low prior to the input switching. + -- BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching + -- by using the INIT_OUT attribute. + -- In some applications the conditions previously described are not desirable. Asserting the + -- IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching + -- between two clock inputs. In other words, asserting IGNORE causes the MUX to switch + -- the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away + -- from the I0 input immediately when the select pin changes, while IGNORE1 causes the + -- output to switch away from the I1 input immediately when the select pin changes. + -- Selection of an input clock requires a "select" pair (S0 and CE0, or S1 and CE1) to be + -- asserted High. If either S or CE is not asserted High, the desired input will not be selected. + -- In normal operation, both S and CE pairs (all four select lines) are not expected to be + -- asserted High simultaneously. Typically only one pin of a "select" pair is used as a select + -- line, while the other pin is tied High. + + -- If the aCe input is async to the I clock, then use the select pins + -- of the BUFGCTRL since setup and hold times at the S* pins do not have + -- to be met. Enable both Select pins if the aCe signal is synchronous to the I clock. + aSel0 <= aCe when kEnableIsAsync else + '1'; + aSel1 <= not aCe when kEnableIsAsync else + '1'; + + -- Only use the CE pins when the input aCe signal is synchronous to the I clock. + iCe0 <= '1' when kEnableIsAsync else + aCe; + iCe1 <= '1' when kEnableIsAsync else + not aCe; + + -- No PkgNiUtilities for me. + kIgnore0 <= '1' when kIgnore else + '0'; + + --vhook_i BUFGCTRL GlobalBuffer + --vhook_a {^IS_(.*)} '0' + --vhook_a INIT_OUT 0 + --vhook_a PRESELECT_I0 kEnableByDefault + --vhook_a PRESELECT_I1 not kEnableByDefault + --vhook_a O ClkOut + --vhook_a CE0 iCe0 + --vhook_a CE1 iCe1 + --vhook_a I0 ClkIn + --vhook_a I1 '0' + --vhook_a IGNORE0 kIgnore0 + --vhook_a IGNORE1 '1' + --vhook_a S0 aSel0 + --vhook_a S1 aSel1 + GlobalBuffer: BUFGCTRL + generic map ( + INIT_OUT => 0, --integer:=0 + IS_CE0_INVERTED => '0', --bit:='0' + IS_CE1_INVERTED => '0', --bit:='0' + IS_I0_INVERTED => '0', --bit:='0' + IS_I1_INVERTED => '0', --bit:='0' + IS_IGNORE0_INVERTED => '0', --bit:='0' + IS_IGNORE1_INVERTED => '0', --bit:='0' + IS_S0_INVERTED => '0', --bit:='0' + IS_S1_INVERTED => '0', --bit:='0' + PRESELECT_I0 => kEnableByDefault, --boolean:=false + PRESELECT_I1 => not kEnableByDefault) --boolean:=false + port map ( + O => ClkOut, --out std_ulogic + CE0 => iCe0, --in std_ulogic + CE1 => iCe1, --in std_ulogic + I0 => ClkIn, --in std_ulogic + I1 => '0', --in std_ulogic + IGNORE0 => kIgnore0, --in std_ulogic + IGNORE1 => '1', --in std_ulogic + S0 => aSel0, --in std_ulogic + S1 => aSel1); --in std_ulogic + + + --vscan Begin Add Explain Clock + --vscan # These are the outputs of the BUFGCTRLs in the WrapBufg module. VScan + --vscan # sees the output as glitchy but the clocks are guaranteed to switch + --vscan # in a glitchless fashion provided that either setup and hold times + --vscan # are met at the CE pins of the BUFGCTRL (these paths are analyzed by the + --vscan # tools for timing) or the CE pins are hardwired and the S pins are used + --vscan # which require no timing relationship to the input clocks. + --vscan *[WrapBufg]GlobalBuffer/[BUFGCTRL]O + --vscan End Add Explain Clock + + + -- Check that enable lines match up with the generics of the BUFGCTRL + --vscan vscan_off + --synthesis translate_off + SimProcess: process + begin + wait for 1 ns; + if kEnableIsAsync then + assert kEnableByDefault = (aSel0 = '1') + report "Initial condition on enable lines do not match between" & LF + & "the BUFGCTRL generic and the SEL line" + severity error; + else + assert kEnableByDefault = (iCe0 = '1') + report "Initial condition on enable lines do not match between" & LF + & "the BUFGCTRL generic and the CE line" + severity error; + end if; + wait; + end process SimProcess; + --synthesis translate_on + --vscan vscan_on + +end rtl; diff --git a/fpga/usrp3/top/n3xx/build_n3xx.tcl b/fpga/usrp3/top/n3xx/build_n3xx.tcl new file mode 100644 index 000000000..45ba102c3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/build_n3xx.tcl @@ -0,0 +1,39 @@ +# +# Copyright 2016 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set n3xx_strategy [dict create] +dict set n3xx_strategy "opt_design.is_enabled" 1 +dict set n3xx_strategy "opt_design.directive" "NoBramPowerOpt" +dict set n3xx_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set n3xx_strategy "place_design.directive" "ExtraNetDelay_high" +dict set n3xx_strategy "post_place_power_opt_design.is_enabled" 0 +dict set n3xx_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set n3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore" +dict set n3xx_strategy "route_design.directive" "Explore" +dict set n3xx_strategy "route_design.more_options" "-tns_cleanup" +dict set n3xx_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set n3xx_strategy "post_route_phys_opt_design.directive" "Explore" +vivado_strategies::implement_design $n3xx_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes +set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *] +set byte_swap_bin 1 +vivado_utils::write_implementation_outputs $byte_swap_bin + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore b/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore new file mode 100644 index 000000000..dbc4e5588 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/.gitignore @@ -0,0 +1,4 @@ +_xmsgs +*.log +*.ncf + diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/.lso b/fpga/usrp3/top/n3xx/coregen_dsp/.lso new file mode 100644 index 000000000..9d9a4a3aa --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/.lso @@ -0,0 +1 @@ +fir_compiler_v5_0 diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..6717ac611 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/Makefile.srcs @@ -0,0 +1,17 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/n3xx/coregen_dsp/, \ +hbdec1.v \ +hbdec1.ngc \ +hbdec2.v \ +hbdec2.ngc \ +hbdec3.v \ +hbdec3.ngc \ +)) + diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..5c09a6253 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$22g6~753-Xnzd}foo8#5+421).97 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174289io6`;138b?>i6;hk1<7*;12827geh39;0n76a>3`494?"39:0:?om4n531>c=5$530>45ek2d?=?4>0:9l56g4290/8<=512``?k26:3;:76a>3`094?"39:0:?om4n531>44<3f;8m<4?:%627?74jj1e8<<51298k45f83:1(9?<:01ag>h39;0:865`12;e>5<#<891=>ll;o626?7232e:?4k50;&756<6;ki0b9?=:048?j741m0;6):>3;30ff=i<881=:54o01:g?6=,=;86<=mc:l757<6021d=>7m:18'045=9:hh7c:>2;3:?>i6;0k1<7*;12827ge:?7?=h9:3=6=4+401956dd3g>:>7?k;:m27<3=83.?=>4>3ca8j17528o07b?<9583>!26;3;8nn5a40095c=5$530>45ek2d?=?4=0:9l56?5290/8<=512``?k26:38:76a>38394?"39:0:?om4n531>74<3f;85=4?:%627?74jj1e8<<52298k45?n3:1(9?<:01ag>h39;09865`12`a>5<#<891=>ll;o626?4232e:?oo50;&756<6;ki0b9?=:348?j74j00;6):>3;30ff=i<881>:54o01al8:18'045=9:hh7c:>2;0:?>i6;hl1<7*;12827ge:?7?=h9:2n6=4+401956dd3g>:>74>3ca8j1752;o07b?!26;3;8in5a40094>=h9:o>6=4+401956cd3g>:>7?4;n30a1<72->:?7?k<:18'045=9:oh7c:>2;18?j74m;0;6):>3;30af=i<881865`12g2>5<#<891=>kl;o626?3<3f;8i=4?:%627?74mj1e8<<56:9l56bb290/8<=512g`?k26:3=07b?!26;3;8in5a4009<>=h9:nh6=4+401956cd3g>:>774;n30`g<72->:?7?jn:18'045=9:oh7c:>2;`8?j74l00;6):>3;30af=i<881o65`12f;>5<#<891=>kl;o626?b<3f;8h:4?:%627?74mj1e8<<5e:9l56b1290/8<=512g`?k26:3l07b?!26;3;8in5a400955=5$530>45bk2d?=?4>1:9l56b5290/8<=512g`?k26:3;976a>3e394?"39:0:?hm4n531>45<3f;8h=4?:%627?74mj1e8<<51598k45dn3:1(9?<:01fg>h39;0:965`12af>5<#<891=>kl;o626?7132e:?nj50;&756<6;li0b9?=:058?j74kj0;6):>3;30af=i<881=554o01`f?6=,=;86<=jc:l757<6121d=>mn:18'045=9:oh7c:>2;3b?>i6;j21<7*;12827`e:?7?=h9:i>6=4+401956cd3g>:>7?j;:m27f2=83.?=>4>3da8j17528l07b?!26;3;8in5a400965=7>5$530>45bk2d?=?4=1:9l56e6290/8<=512g`?k26:38976a>3b294?"39:0:?hm4n531>75<3f;8nk4?:%627?74mj1e8<<52598k45bj3:1(9?<:01fg>h39;09965`12gb>5<#<891=>kl;o626?4132e:?h750;&756<6;li0b9?=:358?j74m10;6):>3;30af=i<881>554o01f3?6=,=;86<=jc:l757<5121d=>ji:18'045=9:oh7c:>2;0b?>i6;m>1<7*;12827`e:?7?=h9:ho6=4+401956cd3g>:>74>40a8j1752910c<:>5;29 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1742:n27c:>2;00?>o4j;0;6):>3;1g=>h39;09865f3c394?"39:08h45a400960=j6;o626?4032c8hh4?:%627?5c12d?=?4=8:9j7ab=83.?=>4jl:18'045=;m30b9?=:3c8?l5cj3:1(9?<:2f:?k26:38i76g!26;39o56`;1381g>=n;j<1<7*;1280`<=i<881>i54i2`a>5<#<891?i74n531>7c<3`9i<7>5$530>6b>3g>:>75=h39;0:76gic;29 1742oo0b9?=:398mcd=83.?=>4ie:l757<432c::n4?:%627?71j2d?=?4?;:k22d<72->:?7?9b:l757<632c::44?:%627?71j2d?=?4=;:k22=<72->:?7?9b:l757<432c:::4?:%627?71j2d?=?4;;:k223<72->:?7?9b:l757<232c::84?:%627?71j2d?=?49;:k221<72->:?7?9b:l757<032c::?4?:%627?71j2d?=?47;:k224<72->:?7?9b:l757<>32c::=4?:%627?71j2d?=?4n;:k21c<72->:?7?9b:l757:?7?9b:l757:?7?9b:l7570:9j50?=83.?=>4>6c9m044=9810e<;8:18'045=9?h0b9?=:008?l72>3:1(9?<:04a?k26:3;876g>5483>!26;3;=n6`;13820>=n9<>1<7*;12822g=i<881=854i070>5<#<891=;l4n531>40<3`;>>7>5$530>40e3g>:>7?8;:k214<72->:?7?9b:l757<6021b=8>50;&756<6>k1e8<<51898m42a290/8<=517`8j17528k07d?;e;29 174282;3a?>o63;35f>h39;0:o65f15`94?"39:0::o5a40095a=j6=4+401953d4>6c9m044=:810e<:9:18'045=9?h0b9?=:308?l73=3:1(9?<:04a?k26:38876g>4583>!26;3;=n6`;13810>=n9=91<7*;12822g=i<881>854i051>5<#<891=;l4n531>70<3`;<=7>5$530>40e3g>:>7<8;:k235<72->:?7?9b:l757<5021b=;h50;&756<6>k1e8<<52898m40b290/8<=517`8j1752;k07d?9d;29 174282;0a?>o6>:0;6):>3;35f>h39;09o65f14:94?"39:0::o5a40096a=o6=4+401953d:?7?8f:l757<632e:;i4?:%627?70n2d?=?4=;:m23f<72->:?7?8f:l757<432c9m:4?:%627?4f>2d?=?4?;:k1e0<72->:?72d?=?4=;:k1e6<72->:?72d?=?4;;:k264<72->:?7?=0:l757<732c:=k4?:%627?7582d?=?4>;:k25`<72->:?7?=0:l757<532c:=i4?:%627?7582d?=?4<;:k25f<72->:?7?=0:l757<332c:=o4?:%627?7582d?=?4:;:k25d<72->:?7?=0:l757<132c:=44?:%627?7582d?=?48;:k26d<72->:?7?=0:l75744?:%627?7582d?=?46;:k26=<72->:?7?=0:l757:4?:%627?7582d?=?4m;:k263<72->:?7?=0:l75784?:%627?7582d?=?4k;:k261<72->:?7?=0:l757>4?:%627?7582d?=?4i;:k267<72->:?7?=0:l757<6821b=<650;&756<6:91e8<<51098m46c290/8<=511a8j1752910e<>m:18'045=99i0b9?=:098m46f290/8<=511a8j1752;10e<>6:18'045=99i0b9?=:298m46?290/8<=511a8j1752=10e<>8:18'045=99i0b9?=:498m461290/8<=511a8j1752?10e<>::18'045=99i0b9?=:698m471290/8<=511a8j1752110e:18'045=99i0b9?=:e98m477290/8<=511a8j1752l10e<>i:18'045=99i0b9?=:g98m46b290/8<=511a8j17528:07d??4;29 17428:h7c:>2;32?>i6;=0;6):>3;307>h39;0;76a>3383>!26;3;8?6`;1382?>i6;80;6):>3;307>h39;0976a>3183>!26;3;8?6`;1380?>i6:o0;6):>3;307>h39;0?76a>2d83>!26;3;8?6`;1386?>i6:m0;6):>3;307>h39;0=76a>2b83>!26;3;8?6`;1384?>i6;m0;6):>3;307>h39;0376a>3b83>!26;3;8?6`;138:?>i6;k0;6):>3;307>h39;0j76a>3`83>!26;3;8?6`;138a?>i6;00;6):>3;307>h39;0h76a>3983>!26;3;8?6`;138g?>i6;>0;6):>3;307>h39;0n76a>3783>!26;3;8?6`;138e?>i6;<0;6):>3;307>h39;0:<65`13`94?"39:0:?>5a400954=5<#<891=l74n531>4=5<#<891=l74n531>6=6=4+40195d?5<#<891=l74n531>0=5<#<891=l74n531>2=5<#<891=l74n531><=5<#<891=l74n531>g=5<#<891=l74n531>a=5<#<891=l74n531>c=4;h3a4?6=,=;862:9j5dc=83.?=>4>a89m044=9:10e76g>ac83>!26;3;j56`;13822>=n9h>1<7*;1282e<=i<881=:54i0;:>5<#<891=l74n531>4><3f9j97>5$530>6g33g>:>7>4;n1b7?6=,=;86>o;;o626?7<3f9j>7>5$530>6g33g>:>7<4;n1b5?6=,=;86>o;;o626?5<3f9j<7>5$530>6g33g>:>7:4;n1:b?6=,=;86>o;;o626?3<3f92i7>5$530>6g33g>:>784;n1:`?6=,=;86>o;;o626?1<3f92n7>5$530>6g33g>:>764;n1:e?6=,=;86>o;;o626??<3f9257>5$530>6g33g>:>7o4;n1:o;;o626?d<3f92;7>5$530>6g33g>:>7m4;n1:2?6=,=;86>o;;o626?b<3f9297>5$530>6g33g>:>7k4;n1:0?6=,=;86>o;;o626?`<3f92?7>5$530>6g33g>:>7??;:m0=7<72->:?7=n4:l757<6921d?4>50;&756<4i=1e8<<51398k6>a290/8<=53`68j17528907b=7e;29 1742:k?7c:>2;37?>i40m0;6):>3;1b0>h39;0:965`39a94?"39:08m95a400953=o;;o626?7?32e8444?:%627?5f<2d?=?4>9:9l7=>=83.?=>468:18'045=;h>0b9?=:0`8?j5?=3:1(9?<:2c7?k26:3;h76a<8583>!26;39j86`;1382`>=h;191<7*;1280e1=i<881=h54o2:1>5<#<891?l:4n531>4`<3f93=7>5$530>6g33g>:>7:?7=n4:l757<5921d?:h50;&756<4i=1e8<<52398k61b290/8<=53`68j1752;907b=8d;29 1742:k?7c:>2;07?>i4?j0;6):>3;1b0>h39;09965`3``94?"39:08m95a400963=o;;o626?4?32e8m54?:%627?5f<2d?=?4=9:9l7d1=83.?=>4o9:18'045=;h>0b9?=:3`8?j5>k3:1(9?<:2c7?k26:38h76a<9083>!26;39j86`;1381`>=h;1<1<7*;1280e1=i<881>h54o25a>5<#<891?l:4n531>7`<3`k?6=4+4019e6=i<881<65fa383>!26;3k87c:>2;38?lg6290/8<=5a29m044=:21bm=4?:%627?g43g>:>7=4;h;e>5<#<891m>5a40090>=n1l0;6):>3;c0?k26:3?07d7k:18'045=i:1e8<<56:9j=f<72->:?7o<;o626?1<3`3i6=4+4019e6=i<881465f9`83>!26;3k87c:>2;;8?l??290/8<=5a29m044=i21b5:4?:%627?g43g>:>7l4;h;5>5<#<891m>5a4009g>=n1<0;6):>3;c0?k26:3n07d7;:18'045=i:1e8<<5e:9j=6<72->:?7o<;o626?`<3`396=4+4019e6=i<881==54i8394?"39:0j?6`;13825>=n190;6):>3;c0?k26:3;976g7f;29 1742h90b9?=:018?lgd290/8<=5a29m044=9=10ell50;&7565:9jed<72->:?7o<;o626?7132cj57>5$530>d55<#<891m>5a40095==h39;0:565fa783>!26;3k87c:>2;3b?>of=3:1(9?<:`18j17528h07d76:18'045=i:1e8<<51b98m=c=83.?=>4n3:l757<6l21d8=l50;&756<38h1e8<<50:9l05?=83.?=>4;0`9m044=921d8=650;&756<38h1e8<<52:9l051=83.?=>4;0`9m044=;21d8=850;&756<38h1e8<<54:9l053=83.?=>4;0`9m044==21d8=:50;&756<38h1e8<<56:9l055=83.?=>4;0`9m044=?21d8=?50;&756<38h1e8<<58:9l056=83.?=>4;0`9m044=121d?kh50;&756<38h1e8<<5a:9l7cc=83.?=>4;0`9m044=j21d?kj50;&756<38h1e8<<5c:9l7ce=83.?=>4;0`9m044=l21d?kl50;&756<38h1e8<<5e:9l7cg=83.?=>4;0`9m044=n21d?k750;&756<38h1e8<<51198k6`?290/8<=541c8j17528;07b=i6;29 1742=:j7c:>2;31?>i4n<0;6):>3;63e>h39;0:?65`3g694?"39:0?n;o626?7132e8j<4?:%627?27i2d?=?4>7:9l7c6=83.?=>4;0`9m044=9110c>ki:18'045=<9k0b9?=:0;8?j5bm3:1(9?<:52b?k26:3;j76a!26;3>;m6`;1382f>=h;lh1<7*;12874d=i<881=n54o2gb>5<#<8918=o4n531>4b<3f9n57>5$530>16f3g>:>7?j;:m0a=<72->:?7:?a:l757<6n21d?h950;&756<38h1e8<<52198k6c1290/8<=541c8j1752;;07b=j5;29 1742=:j7c:>2;01?>i4m=0;6):>3;63e>h39;09?65`3d194?"39:0?n;o626?4132e?==4?:%627?27i2d?=?4=7:9l05`=83.?=>4;0`9m044=:110c9>j:18'045=<9k0b9?=:3;8?j27l3:1(9?<:52b?k26:38j76a;0b83>!26;3>;m6`;1381f>=h<981<7*;12874d=i<881>n54o2d4>5<#<8918=o4n531>7b<3f9no7>5$530>16f3g>:>7:?7:?a:l757<5n21bo94?:%627?e43g>:>7>4;ha1>5<#<891o>5a40095>=nk80;6):>3;a0?k26:3807dm?:18'045=k:1e8<<53:9jfc<72->:?7m<;o626?2<3`hn6=4+4019g6=i<881965fbe83>!26;3i87c:>2;48?ldd290/8<=5c29m044=?21bno4?:%627?e43g>:>764;h`b>5<#<891o>5a4009=>=nj10;6):>3;a0?k26:3k07dl8:18'045=k:1e8<<5b:9jf3<72->:?7m<;o626?e<3`h>6=4+4019g6=i<881h65fb583>!26;3i87c:>2;g8?ld4290/8<=5c29m044=n21bn?4?:%627?e43g>:>7??;:ka5?6=,=;86n=4n531>47<3`h;6=4+4019g6=i<881=?54i`d94?"39:0h?6`;13827>=nkj0;6):>3;a0?k26:3;?76glb;29 1742j90b9?=:078?lef290/8<=5c29m044=9?10en750;&7567:9jg=<72->:?7m<;o626?7?32ch;7>5$530>f55<#<891o>5a40095d=h39;0:n65fb883>!26;3i87c:>2;3`?>ofm3:1(9?<:b18j17528n07d?8a;29 17428=27c:>2;28?l7003:1(9?<:05:?k26:3;07d?87;29 17428=27c:>2;08?xd3>10;684?:1y'07c=:k30D9=k;I605>"4?>0:mh94i0;2>5<5<5<=57>55;294~"3:l09585G42f8L1563-9<;7?ne69'6d7=k2c:8<4?::k2<4<722c:5:4?::k761<722e?=;4?::a03g=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:9b;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e6g>4083>>o6080;66g>9683>>i39?0;66sm47f94?3=83:p(95<5<5<=i7>55;294~"3:l09595G42f8L1563-9<;7?ne69'6d7=:2c:8<4?::k2<4<722c:5:4?::k75=<722e?=;4?::a03`=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:80;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e<>;1<7;50;2x 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1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=n:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 1742j90b9?=:058?le?290/8<=5c29m044=9110en950;&7569:9jg3<72->:?7m<;o626?7f32ch97>5$530>f55<#<891o>5a40095f=h39;0:h65f16c94?"39:0:;45a40094>=n9>21<7*;12823<=i<881=65f16594?"39:0:;45a40096>=zj<9i6=4>a083>5}#<;o1>594H51g?M2492P:?k4>0z6g>2>=?>03?79l:5c951<0>3=964n022>4=#9981?;o4$020>71a3g;:;7?4n01f>4=#9=:1>:h4n055>4=i9>h1=6`>9782?k4?>3;0b?o7:09'6g5=:020b?l;:09m720=82.8mi4:;o621?7<,=8=6?l<;%613?5fl2.???4;2e9'065=:k?0(9=;:24:?!24=39=h6a>o39l0;66g>8783>>o60=0;66a=b683>>o6010;66g;2383>>o5j?0;66g>8683>>o39o0;66g>8g83>>i6?=0;66g;1`83>>o6000;66a;2g83>>i4io0;66g;1b83>>o39k0;66g>8c83>>o3:90;66g>8483>>o60:0;66g>9383>>o60;0;66g;1e83>>i4?10;66g>8`83>>o60l0;66g>7483>>o6?:0;66g;2083>>o60m0;66g;2283>>ib;3:1(9?<:d08j1752910ch?50;&756;:mf4?6=,=;86h<4n531>7=h39;0876ake;29 1742l80b9?=:598kab=83.?=>4j2:l757<232eoo7>5$530>`46`;1384?>ici3:1(9?<:d08j1752110ci750;&756d=h39;0i76ak5;29 1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 1742h90b9?=:038?l?7290/8<=5a29m044=9;10e5h50;&7563:9jef<72->:?7o<;o626?7332cjn7>5$530>d55<#<891m>5a400953=h39;0:;65fa983>!26;3k87c:>2;3;?>of?3:1(9?<:`18j17528307do9:18'045=i:1e8<<51`98md3=83.?=>4n3:l757<6j21b544?:%627?g43g>:>7?l;:k;a?6=,=;86l=4n531>4b<3f>;n7>5$530>16f3g>:>7>4;n63=?6=,=;869>n;o626?7<3f>;47>5$530>16f3g>:>7<4;n633?6=,=;869>n;o626?5<3f>;:7>5$530>16f3g>:>7:4;n631?6=,=;869>n;o626?3<3f>;87>5$530>16f3g>:>784;n637?6=,=;869>n;o626?1<3f>;=7>5$530>16f3g>:>764;n634?6=,=;869>n;o626??<3f9mj7>5$530>16f3g>:>7o4;n1ea?6=,=;869>n;o626?d<3f9mh7>5$530>16f3g>:>7m4;n1eg?6=,=;869>n;o626?b<3f9mn7>5$530>16f3g>:>7k4;n1ee?6=,=;869>n;o626?`<3f9m57>5$530>16f3g>:>7??;:m0b=<72->:?7:?a:l757<6921d?k850;&756<38h1e8<<51398k6`2290/8<=541c8j17528907b=i4;29 1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 1742j90b9?=:018?led290/8<=5c29m044=9=10enl50;&7565:9jgd<72->:?7m<;o626?7132ch57>5$530>f55<#<891o>5a40095==h39;0:565fc783>!26;3i87c:>2;3b?>od=3:1(9?<:b18j17528h07dl6:18'045=k:1e8<<51b98mdc=83.?=>4l3:l757<6l21b=:o50;&756<6?01e8<<50:9j52>=83.?=>4>789m044=921b=:950;&756<6?01e8<<52:9~f05d290:m<4?:1y'07c=:1=0D9=k;I605>\6;o0:13=?<0?47s+36595dc03gko6<5af`82?k7783:0b<>>:09'554=;?k0(<><:35e?k76?3;0b<=j:09'516=:>l0b<99:09m52d=92d:5;4>;o0;2?7"4im0>7c:>5;38 1412;h87):=7;1b`>"3;;0?>i5+42196g3<,=9?6>86;%601?51l2e8mh4?::k75`<722c:4;4?::k2<1<722e9n:4?::k2<=<722c?>?4?::k1f3<722c:4:4?::k75c<722c:4k4?::m231<722c?=l4?::k2<<<722e?>k4?::m0ec<722c?=n4?::k75g<722c:4o4?::k765<722c:484?::k2<6<722c:5?4?::k2<7<722c?=i4?::m03=<722c:4l4?::k2<`<722c:;84?::k236<722c?><4?::k2>4?::mf7?6=,=;86h<4n531>5=h39;0:76aj0;29 1742l80b9?=:398ka`=83.?=>4j2:l757<432eoi7>5$530>`46`;1386?>ick3:1(9?<:d08j1752?10cil50;&756==h39;0276ak7;29 1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 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17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 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1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=j:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 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1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 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1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 17428k27c:>2;30?>o6im0;6):>3;3b=>h39;0:865f1`a94?"39:0:m45a400950=8:9l7d3=83.?=>444421d?4j50;&756<4i=1e8<<57:9l7444447=:18'045=;h>0b9?=:038?j5>83:1(9?<:2c7?k26:3;976a<8g83>!26;39j86`;13827>=h;1o1<7*;1280e1=i<881=954o2:g>5<#<891?l:4n531>43<3f93o7>5$530>6g33g>:>7?9;:m0:?7=n4:l757<6?21d?5o50;&756<4i=1e8<<51998k6>>290/8<=53`68j17528307b=78;29 1742:k?7c:>2;3b?>i40>0;6):>3;1b0>h39;0:n65`39794?"39:08m95a40095f=o;;o626?7b32e84?4?:%627?5f<2d?=?4>f:9l7=7=83.?=>46?:18'045=;h>0b9?=:338?j50n3:1(9?<:2c7?k26:38976a<7d83>!26;39j86`;13817>=h;>n1<7*;1280e1=i<881>954o25`>5<#<891?l:4n531>73<3f9jn7>5$530>6g33g>:>7<9;:m0ed<72->:?7=n4:l757<5?21d?l750;&756<4i=1e8<<52998k6g?290/8<=53`68j1752;307b=n7;29 1742:k?7c:>2;0b?>i4i?0;6):>3;1b0>h39;09n65`38a94?"39:08m95a40096f=o;;o626?4b32e8;o4?:%627?5f<2d?=?4=f:9je1<72->:?7o<;o626?6<3`k96=4+4019e6=i<881=65fa083>!26;3k87c:>2;08?lg7290/8<=5a29m044=;21b5k4?:%627?g43g>:>7:4;h;f>5<#<891m>5a40091>=n1m0;6):>3;c0?k26:3<07d7l:18'045=i:1e8<<57:9j=g<72->:?7o<;o626?><3`3j6=4+4019e6=i<881565f9983>!26;3k87c:>2;c8?l?0290/8<=5a29m044=j21b5;4?:%627?g43g>:>7m4;h;6>5<#<891m>5a4009`>=n1=0;6):>3;c0?k26:3o07d7<:18'045=i:1e8<<5f:9j=7<72->:?7o<;o626?7732c2=7>5$530>d55<#<891m>5a400957=h39;0:?65fab83>!26;3k87c:>2;37?>ofj3:1(9?<:`18j17528?07don:18'045=i:1e8<<51798md?=83.?=>4n3:l757<6?21bm54?:%627?g43g>:>7?7;:kb3?6=,=;86l=4n531>4?<3`k=6=4+4019e6=i<881=l54i`794?"39:0j?6`;1382f>=n100;6):>3;c0?k26:3;h76g7e;29 1742h90b9?=:0f8?j27j3:1(9?<:52b?k26:3:07b:?9;29 1742=:j7c:>2;38?j2703:1(9?<:52b?k26:3807b:?7;29 1742=:j7c:>2;18?j27>3:1(9?<:52b?k26:3>07b:?5;29 1742=:j7c:>2;78?j27<3:1(9?<:52b?k26:3<07b:?3;29 1742=:j7c:>2;58?j2793:1(9?<:52b?k26:3207b:?0;29 1742=:j7c:>2;;8?j5an3:1(9?<:52b?k26:3k07b=ie;29 1742=:j7c:>2;`8?j5al3:1(9?<:52b?k26:3i07b=ic;29 1742=:j7c:>2;f8?j5aj3:1(9?<:52b?k26:3o07b=ia;29 1742=:j7c:>2;d8?j5a13:1(9?<:52b?k26:3;;76a!26;3>;m6`;13825>=h;o<1<7*;12874d=i<881=?54o2d6>5<#<8918=o4n531>45<3f9m87>5$530>16f3g>:>7?;;:m0b6<72->:?7:?a:l757<6=21d?k<50;&756<38h1e8<<51798k6`6290/8<=541c8j17528=07b=i0;29 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1742:n27c:>2;3g?>o4j10;6):>3;1g=>h39;0:i65f3c594?"39:08h45a40095c=4;h1a1?6=,=;86>j6;o626?4632c8n94?:%627?5c12d?=?4=2:9j7g5=83.?=>4l=:18'045=;m30b9?=:368?l5e93:1(9?<:2f:?k26:38>76g!26;39o56`;13812>=n;ml1<7*;1280`<=i<881>:54i2ff>5<#<891?i74n531>7><3`9oh7>5$530>6b>3g>:>7<6;:k0`f<72->:?7=k9:l757<5i21b?il50;&756<4l01e8<<52c98m6b6290/8<=53e;8j1752;i07d=l6;29 1742:n27c:>2;0g?>o4jk0;6):>3;1g=>h39;09i65f3c294?"39:08h45a40096c=h39;0;76gid;29 1742oo0b9?=:098mce=83.?=>4ie:l757<532cmn7>5$530>cc54i04`>5<#<891=;l4n531>5=5<#<891=;l4n531>7=54i044>5<#<891=;l4n531>1=5<#<891=;l4n531>3=5<#<891=;l4n531>==5<#<891=;l4n531>d=5<#<891=;l4n531>f=5<#<891=;l4n531>`=5<#<891=;l4n531>46<3`;>57>5$530>40e3g>:>7?>;:k212<72->:?7?9b:l757<6:21b=8850;&756<6>k1e8<<51298m432290/8<=517`8j17528>07d?:4;29 174282;36?>o6=:0;6):>3;35f>h39;0::65f14094?"39:0::o5a400952=32c:8k4?:%627?71j2d?=?4>a:9j51c=83.?=>4>6c9m044=9k10e<:l:18'045=9?h0b9?=:0a8?l73j3:1(9?<:04a?k26:3;o76g>4`83>!26;3;=n6`;1382a>=n9=31<7*;12822g=i<881=k54i06;>5<#<891=;l4n531>76<3`;?;7>5$530>40e3g>:>7<>;:k203<72->:?7?9b:l757<5:21b=9;50;&756<6>k1e8<<52298m423290/8<=517`8j1752;>07d?;3;29 174282;06?>o6?;0;6):>3;35f>h39;09:65f16394?"39:0::o5a400962=32c::h4?:%627?71j2d?=?4=a:9j53b=83.?=>4>6c9m044=:k10e<8<:18'045=9?h0b9?=:3a8?l7203:1(9?<:04a?k26:38o76g>4e83>!26;3;=n6`;1381a>=n9=81<7*;12822g=i<881>k54o0:3>5<#<891=:h4n531>5=5<#<891=:h4n531>7=54i3c4>5<#<891>l84n531>5=6=4+40196d05<#<891>l84n531>7=54i3c1>5<#<891>l84n531>1=5<#<891=?>4n531>4=5<#<891=?>4n531>6=5<#<891=?>4n531>0=5<#<891=?>4n531>2=5<#<891=?>4n531><=5<#<891=?>4n531>g=5<#<891=?>4n531>a=5<#<891=?>4n531>c=4;h32:?7??c:l757<632c::?7??c:l757<432c:<54?:%627?77k2d?=?4;;:k242<72->:?7??c:l757<232c:<;4?:%627?77k2d?=?49;:k240<72->:?7??c:l757<032c:=;4?:%627?77k2d?=?47;:k250<72->:?7??c:l757<>32c:=94?:%627?77k2d?=?4n;:k256<72->:?7??c:l757:?7??c:l757:?7??c:l7570:9j552=83.?=>4>0b9m044=9810c<=;:18'045=9:90b9?=:198k455290/8<=51218j1752810c<=>:18'045=9:90b9?=:398k457290/8<=51218j1752:10c<10c<=k:18'045=9:90b9?=:998k45d290/8<=51218j1752010c<=m:18'045=9:90b9?=:`98k45f290/8<=51218j1752k10c<=6:18'045=9:90b9?=:b98k45?290/8<=51218j1752m10c<=8:18'045=9:90b9?=:d98k451290/8<=51218j1752o10c<=::18'045=9:90b9?=:028?j75j3:1(9?<:010?k26:3;:76g>a`83>!26;3;j56`;1383?>o6i10;6):>3;3b=>h39;0:76g>a683>!26;3;j56`;1381?>o6i?0;6):>3;3b=>h39;0876g>a483>!26;3;j56`;1387?>o6i:0;6):>3;3b=>h39;0>76g>a383>!26;3;j56`;1385?>o6i80;6):>3;3b=>h39;0<76g>a183>!26;3;j56`;138;?>o61o0;6):>3;3b=>h39;0276g>9d83>!26;3;j56`;138b?>o61m0;6):>3;3b=>h39;0i76g>9b83>!26;3;j56`;138`?>o61k0;6):>3;3b=>h39;0o76g>9`83>!26;3;j56`;138f?>o6j;0;6):>3;3b=>h39;0m76g>b083>!26;3;j56`;13824>=n9k:1<7*;1282e<=i<881=<54i0ce>5<#<891=l74n531>44<3`;ji7>5$530>4g>3g>:>7?<;:k2ea<72->:?7?n9:l757<6<21b=lm50;&756<6i01e8<<51498m4ge290/8<=51`;8j17528<07d?n4;29 17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 1742:k?7c:>2;3f?>i40;0;6):>3;1b0>h39;0:j65`39394?"39:08m95a400965=o;;o626?4532e8;h4?:%627?5f<2d?=?4=3:9l72b=83.?=>49l:18'045=;h>0b9?=:378?j5fj3:1(9?<:2c7?k26:38=76a!26;39j86`;13813>=h;h31<7*;1280e1=i<881>554o2c;>5<#<891?l:4n531>7?<3f9j;7>5$530>6g33g>:>7:?7=n4:l757<5j21d?4m50;&756<4i=1e8<<52b98k6?6290/8<=53`68j1752;n07b=76;29 1742:k?7c:>2;0f?>i4?k0;6):>3;1b0>h39;09j65fa583>!26;3k87c:>2;28?lg5290/8<=5a29m044=921bm<4?:%627?g43g>:>7<4;hc3>5<#<891m>5a40097>=n1o0;6):>3;c0?k26:3>07d7j:18'045=i:1e8<<55:9j=a<72->:?7o<;o626?0<3`3h6=4+4019e6=i<881;65f9c83>!26;3k87c:>2;:8?l?f290/8<=5a29m044=121b554?:%627?g43g>:>7o4;h;4>5<#<891m>5a4009f>=n1?0;6):>3;c0?k26:3i07d7::18'045=i:1e8<<5d:9j=1<72->:?7o<;o626?c<3`386=4+4019e6=i<881j65f9383>!26;3k87c:>2;33?>o>93:1(9?<:`18j17528;07d7?:18'045=i:1e8<<51398m=`=83.?=>4n3:l757<6;21bmn4?:%627?g43g>:>7?;;:kbf?6=,=;86l=4n531>43<3`kj6=4+4019e6=i<881=;54i`;94?"39:0j?6`;13823>=ni10;6):>3;c0?k26:3;376gn7;29 1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8:=:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 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1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 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78a;295~N3;81vb>78b;295~N3;81vb>78c;295~N3;81vb>78d;295~N3;81vb>78e;295~N3;81vb>78f;295~N3;81vb>770;295~N3;81vb>771;295~N3;81vb>772;295~N3;81vb>773;295~N3;81vb>774;295~N3;81vb>775;295~N3;81vb>776;295~N3;81vb>777;295~N3;81vb>778;295~N3;81vb>779;295~N3;81vb>77a;295~N3;81vb>77b;295~N3;81vb>77c;295~N3;81vb>77d;295~N3;81vb>77e;295~N3;81vb>77f;295~N3;81vb>760;295~N3;81vb>761;295~N3;81vb>762;295~N3;81vb>763;295~N3;81vb>l9c;295~N3;81vb>l9d;295~N3;81vb>l9e;295~N3;81vb>l9f;295~N3;81vb>l80;295~N3;81vb>l81;295~N3;81vb>l82;295~N3;81vb>l83;295~N3;81vb>l84;295~N3;81vb>l85;295~N3;81vb>l86;295~N3;81vb>l87;295~N3;81vb>l88;295~N3;81vb>l89;295~N3;81vb>l8a;295~N3;81vb>l8b;295~N3;81vb>l8c;295~N3;81vb>l8d;295~N3;81vb>l8e;295~N3;81vb>l8f;295~N3;81vb>l70;295~N3;81vb>l71;295~N3;81vb>l72;295~N3;81vb>l73;295~N3;81vb>l74;295~N3;81vb>l75;295~N3;81vb>j:e;295~N3;81vb>j:f;295~N3;81vb>j90;295~N3;81vb>j91;295~N3;81vb>j92;295~N3;81vb>j93;295~N3;81vb>j94;295~N3;81vb>j95;295~N3;81vb>j96;295~N3;81vb>j97;295~N3;81vb>j98;295~N3;81vb>j99;295~N3;81vb>j9a;295~N3;81vb>j9b;295~N3;81vb>j9c;295~N3;81vb>j9d;295~N3;81vb>j9e;295~N3;81vb>j9f;295~N3;81vb>j80;295~N3;81vb>j81;295~N3;81vb>j82;295~N3;81vb>j83;295~N3;81vb>j84;295~N3;81vb>j85;295~N3;81vb>j86;295~N3;81vb>j87;295~N3;81vb>h:0;295~N3;81vb>h:1;295~N3;81vb>h:2;295~N3;81vb>h:3;295~N3;81vb>h:4;295~N3;81vb>h:5;295~N3;81vb>h:6;295~N3;81vb>h:7;295~N3;81vb>h:8;295~N3;81vb>h:9;295~N3;81vb>h:a;295~N3;81vb>h:b;295~N3;81vb>h:c;295~N3;81vb>h:d;295~N3;81vb>h:e;295~N3;81vb>h:f;295~N3;81vb>h90;295~N3;81vb>h91;295~N3;81vb>h92;295~N3;81vb>h93;295~N3;81vb>h94;295~N3;81vb>h95;295~N3;81vb>h96;295~N3;81vb>h97;295~N3;81vb>h98;295~N3;81vb>h99;295~N3;81vb9?;2;295~N3;81vb9?;3;295~N3;81vb9?;4;295~N3;81vb9?;5;295~N3;81vb9?;6;295~N3;81vb9?;7;295~N3;81vb9?;8;295~N3;81vb9?;9;295~N3;81vb9?;a;295~N3;81vb9?;b;295~N3;81vb9?;c;295~N3;81vb9?;d;295~N3;81vb9?;e;295~N3;81vb9?;f;295~N3;81vb9?:0;295~N3;81vb9?:1;295~N3;81vb9?:2;295~N3;81vb9?:3;295~N3;81vb9?:4;295~N3;81vb9?:5;295~N3;81vb9?:6;295~N3;81vb9?:7;295~N3;81vb9?:8;295~N3;81vb9?:9;295~N3;81vb9?:a;295~N3;81vb9?:b;295~N3;81vb9=<4;295~N3;81vb9=<5;295~N3;81vb9=<6;295~N3;81vb9=<7;295~N3;81vb9=<8;295~N3;81vb9=<9;295~N3;81vb9=8;295~N3;81vb99>9;295~N3;81vb99>a;295~N3;81vb99>b;295~N3;81vb99>c;295~N3;81vb99>d;295~N3;81vb99>e;295~N3;81vb99>f;295~N3;81vb99=0;295~N3;81vb99=1;295~N3;81vb99=2;295~N3;81vb99=3;295~N3;81vb99=4;295~N3;81vb99=5;295~N3;81vb99=6;295~N3;81vb99=7;295~N3;81vb99=8;295~N3;81vb99=9;295~N3;81vb99=a;295~N3;81vb99=b;295~N3;81vb99=c;295~N3;81vb99=d;295~N3;81vb99=e;295~N3;81vb99=f;295~N3;81vb99<0;295~N3;81vb99<1;295~N3;81vb97?a;295~N3;81vb97?b;295~N3;81vb97?c;295~N3;81vb97?d;295~N3;81vb97?e;295~N3;81vb97?f;295~N3;81vb97>0;295~N3;81vb97>1;295~N3;81vb97>2;295~N3;81vb97>3;295~N3;81vb97>4;295~N3;81vb97>5;295~N3;81vb97>6;295~N3;81vb97>7;295~N3;81vb97>8;295~N3;81vb97>9;295~N3;81vb97>a;295~N3;81vb97>b;295~N3;81vb97>c;295~N3;81vb97>d;295~N3;81vb97>e;295~N3;81vb97>f;295~N3;81vb97=0;295~N3;81vb97=1;295~N3;81vb97=2;295~N3;81vb97=3;295~N3;81vb9oic;295~N3;81vb9oid;295~N3;81vb9oie;295~N3;81vb9oif;295~N3;81vb9l?0;295~N3;81vb9l?1;295~N3;81vb9l?2;295~N3;81vb9l?3;295~N3;81vb9l?4;295~N3;81vb9l?5;295~N3;81vb9l?6;295~N3;81vb9l?7;295~N3;81vb9l?8;295~N3;81vb9l?9;295~N3;81vb9l?a;295~N3;81vb9l?b;295~N3;81vb9l?c;295~N3;81vb9l?d;295~N3;81vb9l?e;295~N3;81vb9l?f;295~N3;81vb9l>0;295~N3;81vb9l>1;295~N3;81vb9l>2;295~N3;81vb9l>3;295~N3;81vb9l>4;295~N3;81vb9l>5;295~N3;81vb9mje;295~N3;81vb9mjf;295~N3;81vb9mi0;295~N3;81vb9mi1;295~N3;81vb9mi2;295~N3;81vb9mi3;295~N3;81vb9mi4;295~N3;81vb9mi5;295~N3;81vb9mi6;295~N3;81vb9mi7;295~N3;81vb9mi8;295~N3;81vb9mi9;295~N3;81vb9mia;295~N3;81vb9mib;295~N3;81vb9mic;295~N3;81vb9mid;295~N3;81vb9mie;295~N3;81vb9mif;295~N3;81vb9j?0;295~N3;81vb9j?1;295~N3;81vb9j?2;295~N3;81vb9j?3;295~N3;81vb9j?4;295~N3;81vb9j?5;295~N3;81vb9j?6;295~N3;81vb9j?7;295~N3;81vb9kj0;295~N3;81vb9kj1;295~N3;81vb9kj2;295~N3;81vb9kj3;295~N3;81vb9kj4;295~N3;81vb9kj5;295~N3;81vb9kj6;295~N3;81vb9kj7;295~N3;81vb9kj8;295~N3;81vb9kj9;295~N3;81vb9kja;295~N3;81vb9kjb;295~N3;81vb9kjc;295~N3;81vb9kjd;295~N3;81vb9kje;295~N3;81vb9kjf;295~N3;81vb9ki0;295~N3;81vb9ki1;295~N3;81vb9ki2;295~N3;81vb9ki3;295~N3;81vb9ki4;295~N3;81vb9ki5;295~N3;81vb9ki6;295~N3;81vb9ki7;295~N3;81vb9ki8;295~N3;81vb9ki9;295~N3;81vb8>k2;295~N3;81vb8>k3;295~N3;81vb8>k4;295~N3;81vb8>k5;295~N3;81vb8>k6;295~N3;81vb8>k7;295~N3;81vb8>k8;295~N3;81vb8>k9;295~N3;81vb8>ka;295~N3;81vb8>kb;295~N3;81vb8>kc;295~N3;81vb8>kd;295~N3;81vb8>ke;295~N3;81vb8>kf;295~N3;81vb8>j0;295~N3;81vb8>j1;295~N3;81vb8>j2;295~N3;81vb8>j3;295~N3;81vb8>j4;295~N3;81vb8>j5;295~N3;81vb8>j6;295~N3;81vb8>j7;295~N3;81vb8>j8;295~N3;81vb8>j9;295~N3;81vb8>ja;295~N3;81vb8>jb;295~N3;81vb80;295~N3;81vb8l>1;295~N3;81vb8l>2;295~N3;81vb8l>3;295~N3;81vb8l>4;295~N3;81vb8l>5;295~N3;81vb8l>6;295~N3;81vb8l>7;295~N3;81vb8l>8;295~N3;81vb8l>9;295~N3;81vb8l>a;295~N3;81vb8l>b;295~N3;81vb8l>c;295~N3;81vb8l>d;295~N3;81vb8l>e;295~N3;81vb8l>f;295~N3;81vb8l=0;295~N3;81vb8l=1;295~N3;81vb8l=2;295~N3;81vb8l=3;295~N3;81vb8l=4;295~N3;81vb8l=5;295~N3;81vb8l=6;295~N3;81vb8l=7;295~N3;81vb8l=8;295~N3;81vb8l=9;295~N3;81vb8l=a;295~N3;81vb8l=b;295~N3;81vb8l=c;295~N3;81vb8l=d;295~N3;81vb8l=e;295~N3;81vb8l=f;295~N3;81vb8j76;295~N3;81vb8j77;295~N3;81vb8j78;295~N3;81vb8j79;295~N3;81vb8j7a;295~N3;81vb8j7b;295~N3;81vb8j7c;295~N3;81vb8j7d;295~N3;81vb8j7e;295~N3;81vb8j7f;295~N3;81vb8j60;295~N3;81vb8j61;295~N3;81vb8j62;295~N3;81vb8j63;295~N3;81vb8j64;295~N3;81vb8j65;295~N3;81vb8j66;295~N3;81vb8j67;295~N3;81vb8j68;295~N3;81vb8j69;295~N3;81vb8j6a;295~N3;81vb8j6b;295~N3;81vb8j6c;295~N3;81vb8j6d;295~N3;81vb8j6e;295~N3;81vb8j6f;295~N3;81vb8jn0;295~N3;81vb8jn1;295~N3;81vb8jn2;295~N3;81vb8jn3;295~N3;81vb8jn4;295~N3;81vb8jn5;295~N3;81vb8jn6;295~N3;81vb8jn7;295~N3;81vb8jn8;295~N3;81vb8jn9;295~N3;81vb8jna;295~N3;81vb8jnb;295~N3;81vb;>?2;295~N3;81vb;>?3;295~N3;81vb;>?4;295~N3;81vb;>?5;295~N3;81vb;>?6;295~N3;81vb;>?7;295~N3;81vb;>?8;295~N3;81vb;>?9;295~N3;81vb;>?a;295~N3;81vb;>?b;295~N3;81vb;>?c;295~N3;81vb;>?d;295~N3;81vb;>?e;295~N3;81vb;>?f;295~N3;81vb;>>0;295~N3;81vb;>>1;295~N3;81vb;>>2;295~N3;81vb;>>3;295~N3;81vb;>>4;295~N3;81vb;>>5;295~N3;81vb;>>6;295~N3;81vb;>>7;295~N3;81vb;>>8;295~N3;81vb;>>9;295~N3;81vb;>>a;295~N3;81vb;>>b;295~N3;81vb;>>c;295~N3;81vb;>>d;295~N3;81vb;>>e;295~N3;81vb;>>f;295~N3;81vb;>=0;295~N3;81vb;>=1;295~N3;81vb;>=2;295~N3;81vb;>=3;295~N3;81vb;>=4;295~N3;81vb;>=5;295~N3;81vb;>=6;295~N3;81vb;>=7;295~N3;81vb;<8e;295~N3;81vb;<8f;295~N3;81vb;<70;295~N3;81vb;<71;295~N3;81vb;<72;295~N3;81vb;<73;295~N3;81vb;<74;295~N3;81vb;<75;295~N3;81vb;<76;295~N3;81vb;<77;295~N3;81vb;<78;295~N3;81vb;<79;295~N3;81vb;<7a;295~N3;81vb;<7b;295~N3;81vb;<7c;295~N3;81vb;<7d;295~N3;81vb;<7e;295~N3;81vb;<7f;295~N3;81vb;<60;295~N3;81vb;<61;295~N3;81vb;<62;295~N3;81vb;<63;295~N3;81vb;<64;295~N3;81vb;<65;295~N3;81vb;<66;295~N3;81vb;<67;295~N3;81vb;<68;295~N3;81vb;<69;295~N3;81vb;<6a;295~N3;81vb;<6b;295~N3;81vb;<6c;295~N3;81vb;<6d;295~N3;81vb;<6e;295~N3;81vb;<6f;295~N3;81vb;0;295~N3;81vb;;>1;295~N3;81vb;;>2;295~N3;81vb;;>3;295~N3;81vb;;>4;295~N3;81vb;;>5;295~N3;81vb;;>6;295~N3;81vb;;>7;295~N3;81vb;;>8;295~N3;81vb;;>9;295~N3;81vb;;>a;295~N3;81vb;;>b;295~N3;81vb;;>c;295~N3;81vb;;>d;295~N3;81vb;;>e;295~N3;81vb;;>f;295~N3;81vb;9?a;295~N3;81vb;9?b;295~N3;81vb;9?c;295~N3;81vb;9?d;295~N3;81vb;9?e;295~N3;81vb;9?f;295~N3;81vb;9>0;295~N3;81vb;9>1;295~N3;81vb;9>2;295~N3;81vb;9>3;295~N3;81vb;9>4;295~N3;81vb;9>5;295~N3;81vb;9>6;295~N3;81vb;9>7;295~N3;81vb;9>8;295~N3;81vb;9>9;295~N3;81vb;9>a;295~N3;81vb;9>b;295~N3;81vb;9>c;295~N3;81vb;9>d;295~N3;81vb;o=4;295~N3;81vb;o=5;295~N3;81vb;o=6;295~N3;81vb;o=7;295~N3;81vb;o=8;295~N3;81vb;o=9;295~N3;81vb;o=a;295~N3;81vb;o=b;295~N3;81vb;o=c;295~N3;81vb;o=d;295~N3;81vb;o=e;295~N3;81vb;o=f;295~N3;81vb;o<0;295~N3;81vb;o<1;295~N3;81vb;o<2;295~N3;81vb;o<3;295~N3;81vb;o<4;295~N3;81vb;o<5;295~N3;81vb;o<6;295~N3;81vb;o<7;295~N3;81vqpsO@Byb0cb===_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000097_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c13 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000881 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/sig00000b8e ), + .Q15(\NLW_blk00000003/blk00000c12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c11 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000880 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000b8d ), + .Q15(\NLW_blk00000003/blk00000c10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0f ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig0000087f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000c0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0d ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig0000087e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000c0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0b ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig0000087c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000c0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c09 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig0000087b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000c08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c07 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig0000087d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000c06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c05 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000879 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000c04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c03 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000878 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000c02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c01 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig0000087a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000c00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bff ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000876 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000bfe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000875 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000bfc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000877 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000bfa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000873 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000bf8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000872 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000bf6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000874 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000bf4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000870 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000bf2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig0000086f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000bf0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bef ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000871 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/sig00000b7c ), + .Q15(\NLW_blk00000003/blk00000bee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bed ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig0000086d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/sig00000b7b ), + .Q15(\NLW_blk00000003/blk00000bec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000beb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig0000086c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/sig00000b7a ), + .Q15(\NLW_blk00000003/blk00000bea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig0000086e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/sig00000b79 ), + .Q15(\NLW_blk00000003/blk00000be8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig0000086a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/sig00000b78 ), + .Q15(\NLW_blk00000003/blk00000be6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig0000086b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/sig00000b77 ), + .Q15(\NLW_blk00000003/blk00000be4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig000008b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig00000b76 ), + .Q15(\NLW_blk00000003/blk00000be2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig00000b75 ), + .Q15(\NLW_blk00000003/blk00000be0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bde ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000b74 ), + .Q15(\NLW_blk00000003/blk00000bde_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig000008ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000b73 ), + .Q15(\NLW_blk00000003/blk00000bdc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig000008af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bda ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig00000b72 ), + .Q15(\NLW_blk00000003/blk00000bda_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig000008ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000b71 ), + .Q15(\NLW_blk00000003/blk00000bd8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000b70 ), + .Q15(\NLW_blk00000003/blk00000bd6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000b6f ), + .Q15(\NLW_blk00000003/blk00000bd4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig000008a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000b6e ), + .Q15(\NLW_blk00000003/blk00000bd2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000b6d ), + .Q15(\NLW_blk00000003/blk00000bd0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig000008a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000b6c ), + .Q15(\NLW_blk00000003/blk00000bce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000b6b ), + .Q15(\NLW_blk00000003/blk00000bcc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig00000b6a ), + .Q15(\NLW_blk00000003/blk00000bca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig000008a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig00000b69 ), + .Q15(\NLW_blk00000003/blk00000bc8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig000008a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000b68 ), + .Q15(\NLW_blk00000003/blk00000bc6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig000008a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig00000b67 ), + .Q15(\NLW_blk00000003/blk00000bc4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig00000b66 ), + .Q15(\NLW_blk00000003/blk00000bc2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig00000b65 ), + .Q15(\NLW_blk00000003/blk00000bc0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000bbe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig0000089d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000bbc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b62 ), + .Q(\blk00000003/sig0000089f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000bba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b61 ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000bb8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b60 ), + .Q(\blk00000003/sig0000089b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000bb6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b5f ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000bb4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5e ), + .Q(\blk00000003/sig00000839 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000bb2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5d ), + .Q(\blk00000003/sig00000838 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000bb0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baf ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5c ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000bae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bad ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5b ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000bac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bab ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5a ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000baa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba9 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b59 ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000ba8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba7 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b58 ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000ba6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba5 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b57 ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000ba4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b56 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000ba2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b55 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000ba0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b54 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000b9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b53 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000b9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b52 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000b9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b99 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b51 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b98 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000b98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b97 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b50 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b96 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000b96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b95 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4f ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b94 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000b94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b93 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4e ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b92 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000b92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b91 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4d ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b90 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000b90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4c ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000b8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4b ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000b8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4a ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000b8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b89 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b49 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000b88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b87 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b48 ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000b86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b85 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b47 ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000b84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b83 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b46 ), + .Q(\blk00000003/sig00000851 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000b82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b81 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b45 ), + .Q(\blk00000003/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/sig00000b45 ), + .Q15(\NLW_blk00000003/blk00000b80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b44 ), + .Q(\blk00000003/sig0000084e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/sig00000b44 ), + .Q15(\NLW_blk00000003/blk00000b7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b43 ), + .Q(\blk00000003/sig00000850 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/sig00000b43 ), + .Q15(\NLW_blk00000003/blk00000b7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b42 ), + .Q(\blk00000003/sig0000084c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/sig00000b42 ), + .Q15(\NLW_blk00000003/blk00000b7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b79 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b41 ), + .Q(\blk00000003/sig0000084b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/sig00000b41 ), + .Q15(\NLW_blk00000003/blk00000b78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b77 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b40 ), + .Q(\blk00000003/sig0000084d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/sig00000b40 ), + .Q15(\NLW_blk00000003/blk00000b76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b75 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3f ), + .Q(\blk00000003/sig00000849 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/sig00000b3f ), + .Q15(\NLW_blk00000003/blk00000b74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b73 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3e ), + .Q(\blk00000003/sig00000848 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/sig00000b3e ), + .Q15(\NLW_blk00000003/blk00000b72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b71 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3d ), + .Q(\blk00000003/sig0000084a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/sig00000b3d ), + .Q15(\NLW_blk00000003/blk00000b70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3c ), + .Q(\blk00000003/sig00000847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/sig00000b3c ), + .Q15(\NLW_blk00000003/blk00000b6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3b ), + .Q(\blk00000003/sig00000846 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/sig00000b3b ), + .Q15(\NLW_blk00000003/blk00000b6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3a ), + .Q(\blk00000003/sig00000845 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/sig00000b3a ), + .Q15(\NLW_blk00000003/blk00000b6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b69 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b39 ), + .Q(\blk00000003/sig00000844 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/sig00000b39 ), + .Q15(\NLW_blk00000003/blk00000b68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b67 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b38 ), + .Q(\blk00000003/sig00000842 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/sig00000b38 ), + .Q15(\NLW_blk00000003/blk00000b66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b65 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b37 ), + .Q(\blk00000003/sig00000841 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/sig00000b37 ), + .Q15(\NLW_blk00000003/blk00000b64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b63 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b36 ), + .Q(\blk00000003/sig00000843 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/sig00000b36 ), + .Q15(\NLW_blk00000003/blk00000b62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b61 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b35 ), + .Q(\blk00000003/sig0000083f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/sig00000b35 ), + .Q15(\NLW_blk00000003/blk00000b60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b34 ), + .Q(\blk00000003/sig0000083e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/sig00000b34 ), + .Q15(\NLW_blk00000003/blk00000b5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b33 ), + .Q(\blk00000003/sig00000840 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/sig00000b33 ), + .Q15(\NLW_blk00000003/blk00000b5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b32 ), + .Q(\blk00000003/sig0000083c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/sig00000b32 ), + .Q15(\NLW_blk00000003/blk00000b5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b59 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b31 ), + .Q(\blk00000003/sig0000083b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/sig00000b31 ), + .Q15(\NLW_blk00000003/blk00000b58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b57 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b30 ), + .Q(\blk00000003/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/sig00000b30 ), + .Q15(\NLW_blk00000003/blk00000b56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b55 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b2f ), + .Q(\blk00000003/sig0000083a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/sig00000b2f ), + .Q15(\NLW_blk00000003/blk00000b54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b53 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000b2e ), + .Q(\blk00000003/sig000009ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b52 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig00000b2e ), + .Q15(\NLW_blk00000003/blk00000b52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b51 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2d ), + .Q(\blk00000003/sig00000808 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/sig00000b2d ), + .Q15(\NLW_blk00000003/blk00000b50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2c ), + .Q(\blk00000003/sig00000807 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/sig00000b2c ), + .Q15(\NLW_blk00000003/blk00000b4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2b ), + .Q(\blk00000003/sig00000809 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/sig00000b2b ), + .Q15(\NLW_blk00000003/blk00000b4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2a ), + .Q(\blk00000003/sig00000806 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/sig00000b2a ), + .Q15(\NLW_blk00000003/blk00000b4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b49 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b29 ), + .Q(\blk00000003/sig00000805 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/sig00000b29 ), + .Q15(\NLW_blk00000003/blk00000b48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b47 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b28 ), + .Q(\blk00000003/sig00000804 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/sig00000b28 ), + .Q15(\NLW_blk00000003/blk00000b46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b45 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b27 ), + .Q(\blk00000003/sig00000803 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/sig00000b27 ), + .Q15(\NLW_blk00000003/blk00000b44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b43 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b26 ), + .Q(\blk00000003/sig00000801 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/sig00000b26 ), + .Q15(\NLW_blk00000003/blk00000b42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b41 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b25 ), + .Q(\blk00000003/sig00000800 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/sig00000b25 ), + .Q15(\NLW_blk00000003/blk00000b40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b24 ), + .Q(\blk00000003/sig00000802 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/sig00000b24 ), + .Q15(\NLW_blk00000003/blk00000b3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b23 ), + .Q(\blk00000003/sig000007fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/sig00000b23 ), + .Q15(\NLW_blk00000003/blk00000b3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b22 ), + .Q(\blk00000003/sig000007fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/sig00000b22 ), + .Q15(\NLW_blk00000003/blk00000b3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b39 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b21 ), + .Q(\blk00000003/sig000007ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/sig00000b21 ), + .Q15(\NLW_blk00000003/blk00000b38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b37 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b20 ), + .Q(\blk00000003/sig000007fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/sig00000b20 ), + .Q15(\NLW_blk00000003/blk00000b36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b35 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1f ), + .Q(\blk00000003/sig000007fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/sig00000b1f ), + .Q15(\NLW_blk00000003/blk00000b34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b33 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1e ), + .Q(\blk00000003/sig000007fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/sig00000b1e ), + .Q15(\NLW_blk00000003/blk00000b32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b31 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1d ), + .Q(\blk00000003/sig000007f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/sig00000b1d ), + .Q15(\NLW_blk00000003/blk00000b30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1c ), + .Q(\blk00000003/sig000007f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/sig00000b1c ), + .Q15(\NLW_blk00000003/blk00000b2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1b ), + .Q(\blk00000003/sig000007f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/sig00000b1b ), + .Q15(\NLW_blk00000003/blk00000b2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1a ), + .Q(\blk00000003/sig000007f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/sig00000b1a ), + .Q15(\NLW_blk00000003/blk00000b2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b29 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b19 ), + .Q(\blk00000003/sig000007f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b28 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/sig00000b19 ), + .Q15(\NLW_blk00000003/blk00000b28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b27 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b18 ), + .Q(\blk00000003/sig000007f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b26 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/sig00000b18 ), + .Q15(\NLW_blk00000003/blk00000b26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b25 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b17 ), + .Q(\blk00000003/sig000007f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b24 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/sig00000b17 ), + .Q15(\NLW_blk00000003/blk00000b24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b23 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b16 ), + .Q(\blk00000003/sig000007f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b22 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/sig00000b16 ), + .Q15(\NLW_blk00000003/blk00000b22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b21 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b15 ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b20 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/sig00000b15 ), + .Q15(\NLW_blk00000003/blk00000b20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b14 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/sig00000b14 ), + .Q15(\NLW_blk00000003/blk00000b1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b13 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/sig00000b13 ), + .Q15(\NLW_blk00000003/blk00000b1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b12 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/sig00000b12 ), + .Q15(\NLW_blk00000003/blk00000b1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b19 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b11 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b18 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/sig00000b11 ), + .Q15(\NLW_blk00000003/blk00000b18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b17 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b10 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b16 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/sig00000b10 ), + .Q15(\NLW_blk00000003/blk00000b16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b15 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0f ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b14 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/sig00000b0f ), + .Q15(\NLW_blk00000003/blk00000b14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b13 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0e ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/sig00000b0e ), + .Q15(\NLW_blk00000003/blk00000b12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b11 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0d ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/sig00000b0d ), + .Q15(\NLW_blk00000003/blk00000b10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0c ), + .Q(\blk00000003/sig00000817 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/sig00000b0c ), + .Q15(\NLW_blk00000003/blk00000b0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0b ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/sig00000b0b ), + .Q15(\NLW_blk00000003/blk00000b0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0a ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/sig00000b0a ), + .Q15(\NLW_blk00000003/blk00000b0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b09 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b09 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/sig00000b09 ), + .Q15(\NLW_blk00000003/blk00000b08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b07 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b08 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/sig00000b08 ), + .Q15(\NLW_blk00000003/blk00000b06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b05 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b07 ), + .Q(\blk00000003/sig00000813 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/sig00000b07 ), + .Q15(\NLW_blk00000003/blk00000b04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b03 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b06 ), + .Q(\blk00000003/sig00000812 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/sig00000b06 ), + .Q15(\NLW_blk00000003/blk00000b02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b01 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b05 ), + .Q(\blk00000003/sig00000810 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/sig00000b05 ), + .Q15(\NLW_blk00000003/blk00000b00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aff ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b04 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/sig00000b04 ), + .Q15(\NLW_blk00000003/blk00000afe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afd ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b03 ), + .Q(\blk00000003/sig00000811 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/sig00000b03 ), + .Q15(\NLW_blk00000003/blk00000afc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afb ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b02 ), + .Q(\blk00000003/sig0000080d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/sig00000b02 ), + .Q15(\NLW_blk00000003/blk00000afa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af9 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b01 ), + .Q(\blk00000003/sig0000080c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/sig00000b01 ), + .Q15(\NLW_blk00000003/blk00000af8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af7 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b00 ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/sig00000b00 ), + .Q15(\NLW_blk00000003/blk00000af6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af5 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000aff ), + .Q(\blk00000003/sig0000080a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/sig00000aff ), + .Q15(\NLW_blk00000003/blk00000af4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af3 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000afe ), + .Q(\blk00000003/sig0000080b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/sig00000afe ), + .Q15(\NLW_blk00000003/blk00000af2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afd ), + .Q(\blk00000003/sig00000937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig00000afd ), + .Q15(\NLW_blk00000003/blk00000af0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aee ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000afc ), + .Q15(\NLW_blk00000003/blk00000aee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afb ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aec ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000afb ), + .Q15(\NLW_blk00000003/blk00000aec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aeb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afa ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aea ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000afa ), + .Q15(\NLW_blk00000003/blk00000aea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af9 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000af9 ), + .Q15(\NLW_blk00000003/blk00000ae8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af8 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000af8 ), + .Q15(\NLW_blk00000003/blk00000ae6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af7 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000af7 ), + .Q15(\NLW_blk00000003/blk00000ae4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000af6 ), + .Q15(\NLW_blk00000003/blk00000ae2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000af5 ), + .Q15(\NLW_blk00000003/blk00000ae0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ade ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000af4 ), + .Q15(\NLW_blk00000003/blk00000ade_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000add ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000af3 ), + .Q15(\NLW_blk00000003/blk00000adc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ada ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000af2 ), + .Q15(\NLW_blk00000003/blk00000ada_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000af1 ), + .Q15(\NLW_blk00000003/blk00000ad8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000af0 ), + .Q15(\NLW_blk00000003/blk00000ad6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000aef ), + .Q15(\NLW_blk00000003/blk00000ad4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000aee ), + .Q15(\NLW_blk00000003/blk00000ad2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000aed ), + .Q15(\NLW_blk00000003/blk00000ad0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ace ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000aec ), + .Q15(\NLW_blk00000003/blk00000ace_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000aeb ), + .Q15(\NLW_blk00000003/blk00000acc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aca ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000aea ), + .Q15(\NLW_blk00000003/blk00000aca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000ae9 ), + .Q15(\NLW_blk00000003/blk00000ac8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000ae8 ), + .Q15(\NLW_blk00000003/blk00000ac6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk00000ac4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk00000ac2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/sig00000152 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk00000ac0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abe ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk00000abe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/sig00000150 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk00000abc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/sig0000014f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aba ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk00000aba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/sig00000151 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk00000ab8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/sig0000014d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk00000ab6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/sig0000014c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000adf ), + .Q15(\NLW_blk00000003/blk00000ab4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/sig0000014e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000ade ), + .Q15(\NLW_blk00000003/blk00000ab2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000add ), + .Q15(\NLW_blk00000003/blk00000ab0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aae ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000adc ), + .Q15(\NLW_blk00000003/blk00000aae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aac ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000adb ), + .Q15(\NLW_blk00000003/blk00000aac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaa ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000ada ), + .Q15(\NLW_blk00000003/blk00000aaa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk00000aa8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk00000aa6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000ad7 ), + .Q15(\NLW_blk00000003/blk00000aa4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000ad6 ), + .Q15(\NLW_blk00000003/blk00000aa2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000ad5 ), + .Q15(\NLW_blk00000003/blk00000aa0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000ad4 ), + .Q15(\NLW_blk00000003/blk00000a9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000ad3 ), + .Q15(\NLW_blk00000003/blk00000a9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000ad2 ), + .Q15(\NLW_blk00000003/blk00000a9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a99 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a98 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000ad1 ), + .Q15(\NLW_blk00000003/blk00000a98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a97 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a96 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000ad0 ), + .Q15(\NLW_blk00000003/blk00000a96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a95 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a94 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000acf ), + .Q15(\NLW_blk00000003/blk00000a94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a93 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a92 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000ace ), + .Q15(\NLW_blk00000003/blk00000a92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a90 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000acd ), + .Q15(\NLW_blk00000003/blk00000a90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/sig000007d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/sig00000acc ), + .Q15(\NLW_blk00000003/blk00000a8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/sig000007d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/sig00000acb ), + .Q15(\NLW_blk00000003/blk00000a8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/sig000007d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/sig00000aca ), + .Q15(\NLW_blk00000003/blk00000a8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a89 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/sig000007d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/sig00000ac9 ), + .Q15(\NLW_blk00000003/blk00000a88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a87 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/sig000007d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/sig00000ac8 ), + .Q15(\NLW_blk00000003/blk00000a86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a85 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/sig000007d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/sig00000ac7 ), + .Q15(\NLW_blk00000003/blk00000a84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a83 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/sig000007d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk00000a82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a81 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/sig000007d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk00000a80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/sig000007d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk00000a7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/sig000007cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk00000a7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/sig000007ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk00000a7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a79 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/sig000007d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk00000a78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a77 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/sig000007cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk00000a76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a75 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/sig000007cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/sig00000abf ), + .Q15(\NLW_blk00000003/blk00000a74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a73 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/sig000007cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/sig00000abe ), + .Q15(\NLW_blk00000003/blk00000a72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a71 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/sig000007c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/sig00000abd ), + .Q15(\NLW_blk00000003/blk00000a70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/sig000007c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/sig00000abc ), + .Q15(\NLW_blk00000003/blk00000a6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/sig000007ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/sig00000abb ), + .Q15(\NLW_blk00000003/blk00000a6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/sig000007c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/sig00000aba ), + .Q15(\NLW_blk00000003/blk00000a6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a69 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/sig000007c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk00000a68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a67 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/sig000007c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk00000a66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a65 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/sig000007c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk00000a64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a63 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig000007c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk00000a62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a61 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig000007c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk00000a60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig000007f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk00000a5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig000007f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk00000a5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig000007ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk00000a5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a59 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig000007ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk00000a58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a57 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000a56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a55 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig000007eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000a54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a53 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig000007ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a52 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000a52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a51 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig000007ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000a50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig000007e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000a4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig000007e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000a4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig000007e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000a4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a49 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig000007e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000a48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a47 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig000007e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000a46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a45 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig000007e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000a44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a43 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig000007e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000a42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a41 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig000007e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000a40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig000007e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000a3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig000007e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000a3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig000007de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000a3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a39 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig000007dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000a38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a37 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig000007df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/sig00000aa0 ), + .Q15(\NLW_blk00000003/blk00000a36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a35 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig000007db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/sig00000a9f ), + .Q15(\NLW_blk00000003/blk00000a34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a33 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig000007da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/sig00000a9e ), + .Q15(\NLW_blk00000003/blk00000a32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a31 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig000007dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/sig00000a9d ), + .Q15(\NLW_blk00000003/blk00000a30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000761 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001de ), + .Q(\blk00000003/sig00000a9c ), + .Q15(\NLW_blk00000003/blk00000a2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig000009ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ca ), + .Q(\blk00000003/sig00000a9b ), + .Q15(\NLW_blk00000003/blk00000a2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a99 ), + .Q15(\NLW_blk00000003/blk00000a2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a29 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a28 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a97 ), + .Q15(\NLW_blk00000003/blk00000a28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a27 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a26 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a95 ), + .Q15(\NLW_blk00000003/blk00000a26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a25 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a24 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a93 ), + .Q15(\NLW_blk00000003/blk00000a24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a23 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a22 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a91 ), + .Q15(\NLW_blk00000003/blk00000a22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a21 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a20 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a8f ), + .Q15(\NLW_blk00000003/blk00000a20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a8d ), + .Q15(\NLW_blk00000003/blk00000a1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a8b ), + .Q15(\NLW_blk00000003/blk00000a1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a89 ), + .Q15(\NLW_blk00000003/blk00000a1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a19 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a18 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a87 ), + .Q15(\NLW_blk00000003/blk00000a18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a17 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a16 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a85 ), + .Q15(\NLW_blk00000003/blk00000a16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a15 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a14 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000a83 ), + .Q15(\NLW_blk00000003/blk00000a14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a13 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a12 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000a81 ), + .Q15(\NLW_blk00000003/blk00000a12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a11 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a10 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000a7f ), + .Q15(\NLW_blk00000003/blk00000a10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000a7d ), + .Q15(\NLW_blk00000003/blk00000a0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000a7b ), + .Q15(\NLW_blk00000003/blk00000a0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000a0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a09 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a08 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000a08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a07 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a06 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000a06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a05 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a04 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000a04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a03 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a02 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000a02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a01 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a00 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000a00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ff ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fe ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000a6d ), + .Q15(\NLW_blk00000003/blk000009fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000a6b ), + .Q15(\NLW_blk00000003/blk000009fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fa ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000a69 ), + .Q15(\NLW_blk00000003/blk000009fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000a67 ), + .Q15(\NLW_blk00000003/blk000009f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000a65 ), + .Q15(\NLW_blk00000003/blk000009f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig00000a63 ), + .Q15(\NLW_blk00000003/blk000009f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000a61 ), + .Q15(\NLW_blk00000003/blk000009f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig00000a5f ), + .Q15(\NLW_blk00000003/blk000009f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ef ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ee ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig00000a5d ), + .Q15(\NLW_blk00000003/blk000009ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ed ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ec ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig00000a5b ), + .Q15(\NLW_blk00000003/blk000009ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009eb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ea ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig00000a59 ), + .Q15(\NLW_blk00000003/blk000009ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig00000a57 ), + .Q15(\NLW_blk00000003/blk000009e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig00000a55 ), + .Q15(\NLW_blk00000003/blk000009e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig00000a53 ), + .Q15(\NLW_blk00000003/blk000009e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig00000a51 ), + .Q15(\NLW_blk00000003/blk000009e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig00000a4f ), + .Q15(\NLW_blk00000003/blk000009e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009df ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009de ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig00000a4d ), + .Q15(\NLW_blk00000003/blk000009de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig00000a4b ), + .Q15(\NLW_blk00000003/blk000009dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009db ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009da ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig00000a49 ), + .Q15(\NLW_blk00000003/blk000009da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig00000a47 ), + .Q15(\NLW_blk00000003/blk000009d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig00000a45 ), + .Q15(\NLW_blk00000003/blk000009d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig00000a43 ), + .Q15(\NLW_blk00000003/blk000009d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig00000a41 ), + .Q15(\NLW_blk00000003/blk000009d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig00000a3f ), + .Q15(\NLW_blk00000003/blk000009d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cf ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ce ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig00000a3d ), + .Q15(\NLW_blk00000003/blk000009ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig00000a3b ), + .Q15(\NLW_blk00000003/blk000009cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig000007a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/sig00000a3a ), + .Q15(\NLW_blk00000003/blk000009ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig000007a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/sig00000a39 ), + .Q15(\NLW_blk00000003/blk000009c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig000007a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/sig00000a38 ), + .Q15(\NLW_blk00000003/blk000009c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig000007a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/sig00000a37 ), + .Q15(\NLW_blk00000003/blk000009c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig000007a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/sig00000a36 ), + .Q15(\NLW_blk00000003/blk000009c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig000007a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/sig00000a35 ), + .Q15(\NLW_blk00000003/blk000009c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bf ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig000007a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/sig00000a34 ), + .Q15(\NLW_blk00000003/blk000009be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bd ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig000007a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/sig00000a33 ), + .Q15(\NLW_blk00000003/blk000009bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig000007a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/sig00000a32 ), + .Q15(\NLW_blk00000003/blk000009ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig000007a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/sig00000a31 ), + .Q15(\NLW_blk00000003/blk000009b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig0000079f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/sig00000a30 ), + .Q15(\NLW_blk00000003/blk000009b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/sig00000a2f ), + .Q15(\NLW_blk00000003/blk000009b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig0000079c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/sig00000a2e ), + .Q15(\NLW_blk00000003/blk000009b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig0000079e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/sig00000a2d ), + .Q15(\NLW_blk00000003/blk000009b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009af ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig0000079a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/sig00000a2c ), + .Q15(\NLW_blk00000003/blk000009ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ad ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000799 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/sig00000a2b ), + .Q15(\NLW_blk00000003/blk000009ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ab ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig0000079b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/sig00000a2a ), + .Q15(\NLW_blk00000003/blk000009aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000797 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000a29 ), + .Q15(\NLW_blk00000003/blk000009a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000796 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000a28 ), + .Q15(\NLW_blk00000003/blk000009a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000798 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/sig00000a27 ), + .Q15(\NLW_blk00000003/blk000009a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000794 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig00000a26 ), + .Q15(\NLW_blk00000003/blk000009a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig00000a25 ), + .Q15(\NLW_blk00000003/blk000009a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000795 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig00000a24 ), + .Q15(\NLW_blk00000003/blk0000099e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000792 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig00000a23 ), + .Q15(\NLW_blk00000003/blk0000099c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig000007c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/sig00000a22 ), + .Q15(\NLW_blk00000003/blk0000099a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000999 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig000007bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000998 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000998_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000997 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig000007c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000996 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000996_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000995 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig000007bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000994 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000994_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000993 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig000007bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000992 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000992_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000991 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig000007be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000990 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000990_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig000007ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/sig00000a1c ), + .Q15(\NLW_blk00000003/blk0000098e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig000007b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/sig00000a1b ), + .Q15(\NLW_blk00000003/blk0000098c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig000007bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/sig00000a1a ), + .Q15(\NLW_blk00000003/blk0000098a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000989 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig000007b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000988 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000988_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000987 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig000007b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000986 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000986_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000985 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig000007b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000984 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000984_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000983 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig000007b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000982 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000982_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000981 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig000007b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000980 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000980_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a14 ), + .Q(\blk00000003/sig000007b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/sig00000a14 ), + .Q15(\NLW_blk00000003/blk0000097e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a13 ), + .Q(\blk00000003/sig000007b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/sig00000a13 ), + .Q15(\NLW_blk00000003/blk0000097c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a12 ), + .Q(\blk00000003/sig000007b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/sig00000a12 ), + .Q15(\NLW_blk00000003/blk0000097a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000979 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a11 ), + .Q(\blk00000003/sig000007b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000978 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000978_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000977 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a10 ), + .Q(\blk00000003/sig000007af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000976 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/sig00000a10 ), + .Q15(\NLW_blk00000003/blk00000976_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000975 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0f ), + .Q(\blk00000003/sig000007ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000974 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/sig00000a0f ), + .Q15(\NLW_blk00000003/blk00000974_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000973 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0e ), + .Q(\blk00000003/sig000007ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000972 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/sig00000a0e ), + .Q15(\NLW_blk00000003/blk00000972_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000971 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0d ), + .Q(\blk00000003/sig000007ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000970 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/sig00000a0d ), + .Q15(\NLW_blk00000003/blk00000970_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0c ), + .Q(\blk00000003/sig000007aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/sig00000a0c ), + .Q15(\NLW_blk00000003/blk0000096e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .Q(\blk00000003/sig00000869 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a0b ), + .Q15(\NLW_blk00000003/blk0000096c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0a ), + .Q(\blk00000003/sig000007ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/sig00000a0a ), + .Q15(\NLW_blk00000003/blk0000096a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000969 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .Q(\blk00000003/sig00000867 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000968 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000968_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000967 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .Q(\blk00000003/sig00000866 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000966 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000966_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000965 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .Q(\blk00000003/sig00000868 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000964 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000964_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000963 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .Q(\blk00000003/sig00000865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000962 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000962_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .Q(\blk00000003/sig00000864 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000960 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000960_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .Q(\blk00000003/sig00000863 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a04 ), + .Q15(\NLW_blk00000003/blk0000095e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .Q(\blk00000003/sig00000862 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a03 ), + .Q15(\NLW_blk00000003/blk0000095c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a02 ), + .Q(\blk00000003/sig00000860 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a02 ), + .Q15(\NLW_blk00000003/blk0000095a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000959 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .Q(\blk00000003/sig0000085f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000958 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000958_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000957 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a00 ), + .Q(\blk00000003/sig00000861 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000956 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000956_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000955 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .Q(\blk00000003/sig0000085d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000954 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000954_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000953 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fe ), + .Q(\blk00000003/sig0000085c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000952 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000952_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000951 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .Q(\blk00000003/sig0000085e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000950 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000950_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fc ), + .Q(\blk00000003/sig0000085a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000009fc ), + .Q15(\NLW_blk00000003/blk0000094e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .Q(\blk00000003/sig00000859 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000009fb ), + .Q15(\NLW_blk00000003/blk0000094c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fa ), + .Q(\blk00000003/sig0000085b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000009fa ), + .Q15(\NLW_blk00000003/blk0000094a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000949 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .Q(\blk00000003/sig00000858 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000948 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000009f9 ), + .Q15(\NLW_blk00000003/blk00000948_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000947 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f8 ), + .Q(\blk00000003/sig00000857 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000946 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000009f8 ), + .Q15(\NLW_blk00000003/blk00000946_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000945 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .Q(\blk00000003/sig00000856 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000944 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000009f7 ), + .Q15(\NLW_blk00000003/blk00000944_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000943 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f6 ), + .Q(\blk00000003/sig00000855 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000942 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000009f6 ), + .Q15(\NLW_blk00000003/blk00000942_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000941 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .Q(\blk00000003/sig00000853 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000940 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000009f5 ), + .Q15(\NLW_blk00000003/blk00000940_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .Q(\blk00000003/sig00000852 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000009f4 ), + .Q15(\NLW_blk00000003/blk0000093e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .Q(\blk00000003/sig00000854 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000009f3 ), + .Q15(\NLW_blk00000003/blk0000093c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000009f2 ), + .Q15(\NLW_blk00000003/blk0000093a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000939 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f1 ), + .Q(\blk00000003/sig00000897 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000938 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000009f1 ), + .Q15(\NLW_blk00000003/blk00000938_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000937 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f0 ), + .Q(\blk00000003/sig00000899 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000936 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000009f0 ), + .Q15(\NLW_blk00000003/blk00000936_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000935 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .Q(\blk00000003/sig00000895 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000934 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000009ef ), + .Q15(\NLW_blk00000003/blk00000934_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000933 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000932 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000009ee ), + .Q15(\NLW_blk00000003/blk00000932_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000931 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000930 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000009ed ), + .Q15(\NLW_blk00000003/blk00000930_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .Q(\blk00000003/sig00000893 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000009ec ), + .Q15(\NLW_blk00000003/blk0000092e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000009eb ), + .Q15(\NLW_blk00000003/blk0000092c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .Q(\blk00000003/sig00000891 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000009ea ), + .Q15(\NLW_blk00000003/blk0000092a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000929 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000928 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000009e9 ), + .Q15(\NLW_blk00000003/blk00000928_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000927 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000926 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000009e8 ), + .Q15(\NLW_blk00000003/blk00000926_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000925 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000924 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000009e7 ), + .Q15(\NLW_blk00000003/blk00000924_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000923 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/sig0000088f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000922 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000009e6 ), + .Q15(\NLW_blk00000003/blk00000922_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/sig0000088b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000920 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000009e5 ), + .Q15(\NLW_blk00000003/blk00000920_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000009e4 ), + .Q15(\NLW_blk00000003/blk0000091e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000009e3 ), + .Q15(\NLW_blk00000003/blk0000091c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/sig00000888 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000009e2 ), + .Q15(\NLW_blk00000003/blk0000091a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000919 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/sig00000887 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000918 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000009e1 ), + .Q15(\NLW_blk00000003/blk00000918_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000917 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/sig00000889 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000916 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000009e0 ), + .Q15(\NLW_blk00000003/blk00000916_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000915 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/sig00000886 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000914 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000009df ), + .Q15(\NLW_blk00000003/blk00000914_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/sig00000885 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000912 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000009de ), + .Q15(\NLW_blk00000003/blk00000912_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/sig00000884 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000910 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000009dd ), + .Q15(\NLW_blk00000003/blk00000910_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/sig00000883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000009dc ), + .Q15(\NLW_blk00000003/blk0000090e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/sig000002a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d5 ), + .Q(\blk00000003/sig000009db ), + .Q15(\NLW_blk00000003/blk0000090c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/sig000002a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig000009da ), + .Q15(\NLW_blk00000003/blk0000090a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/sig00000882 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000908 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000908_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000907 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/sig000008c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000906 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000906_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d7 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000904 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000904_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d6 ), + .Q(\blk00000003/sig000009b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000902 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d1 ), + .Q(\blk00000003/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000902_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d5 ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000900 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000900_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d4 ), + .Q(\blk00000003/sig000008bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig000009d4 ), + .Q15(\NLW_blk00000003/blk000008fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d3 ), + .Q(\blk00000003/sig000008c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig000009d3 ), + .Q15(\NLW_blk00000003/blk000008fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d2 ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig000009d2 ), + .Q15(\NLW_blk00000003/blk000008fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d1 ), + .Q(\blk00000003/sig000008bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig000009d1 ), + .Q15(\NLW_blk00000003/blk000008f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d0 ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig000009d0 ), + .Q15(\NLW_blk00000003/blk000008f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cf ), + .Q(\blk00000003/sig000008bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig000009cf ), + .Q15(\NLW_blk00000003/blk000008f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ce ), + .Q(\blk00000003/sig000008b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig000009ce ), + .Q15(\NLW_blk00000003/blk000008f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cd ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig000009cd ), + .Q15(\NLW_blk00000003/blk000008f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cc ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig000009cc ), + .Q15(\NLW_blk00000003/blk000008ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cb ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig000009cb ), + .Q15(\NLW_blk00000003/blk000008ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ca ), + .Q(\blk00000003/sig000008b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig000009ca ), + .Q15(\NLW_blk00000003/blk000008ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c9 ), + .Q(\blk00000003/sig000008b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig000009c9 ), + .Q15(\NLW_blk00000003/blk000008e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c8 ), + .Q(\blk00000003/sig000008b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig000009c8 ), + .Q15(\NLW_blk00000003/blk000008e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c7 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig000009c7 ), + .Q15(\NLW_blk00000003/blk000008e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c6 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig000009c6 ), + .Q15(\NLW_blk00000003/blk000008e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c5 ), + .Q(\blk00000003/sig000001de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig000009c5 ), + .Q15(\NLW_blk00000003/blk000008e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c4 ), + .Q(\blk00000003/sig00000760 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d7 ), + .Q(\blk00000003/sig000009c4 ), + .Q15(\NLW_blk00000003/blk000008de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c3 ), + .Q(\blk00000003/sig0000091f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008dc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000009c3 ), + .Q15(\NLW_blk00000003/blk000008dc_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk000008db ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000275 ) + ); + INV \blk00000003/blk000008da ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000232 ) + ); + INV \blk00000003/blk000008d9 ( + .I(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000026e ) + ); + INV \blk00000003/blk000008d8 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000283 ) + ); + INV \blk00000003/blk000008d7 ( + .I(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000274 ) + ); + INV \blk00000003/blk000008d6 ( + .I(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009ab ) + ); + INV \blk00000003/blk000008d5 ( + .I(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000286 ) + ); + INV \blk00000003/blk000008d4 ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026f ) + ); + INV \blk00000003/blk000008d3 ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000248 ) + ); + INV \blk00000003/blk000008d2 ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000231 ) + ); + INV \blk00000003/blk000008d1 ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c1 ) + ); + INV \blk00000003/blk000008d0 ( + .I(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000001cb ) + ); + INV \blk00000003/blk000008cf ( + .I(\blk00000003/sig000000be ), + .O(\blk00000003/sig000000bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000009b0 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig00000250 ), + .I2(coef_ld), + .O(\blk00000003/sig0000024c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig00000241 ), + .I2(\blk00000003/sig00000250 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000244 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000008cb ( + .I0(coef_ld), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000024b ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig00000227 ), + .I2(coef_we), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000255 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000250 ), + .I4(coef_ld), + .O(\blk00000003/sig0000024a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c8 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig000009ba ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000027e ), + .I1(ce), + .I2(\blk00000003/sig00000241 ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig000009c2 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig00000285 ), + .I1(ce), + .I2(\blk00000003/sig0000023f ), + .I3(\blk00000003/sig00000276 ), + .O(\blk00000003/sig000009c1 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig000009af ), + .I1(ce), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig000009bc ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c4 ( + .I0(ce), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig000009b9 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig000001e7 ), + .I1(\blk00000003/sig000009ae ), + .I2(\blk00000003/sig000000ad ), + .I3(ce), + .I4(nd), + .O(\blk00000003/sig000009c0 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig000001e2 ), + .I1(\blk00000003/sig000001d7 ), + .I2(\blk00000003/sig000009be ), + .I3(ce), + .O(\blk00000003/sig000009bf ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000009be ), + .I2(ce), + .O(\blk00000003/sig000009bd ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000000ad ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig000009bb ) + ); + LUT4 #( + .INIT ( 16'hECCC )) + \blk00000003/blk000008bf ( + .I0(coef_we), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000258 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008be ( + .C(clk), + .D(\blk00000003/sig000009c2 ), + .Q(\blk00000003/sig0000027e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008bd ( + .C(clk), + .D(\blk00000003/sig000009c1 ), + .Q(\blk00000003/sig00000285 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bc ( + .C(clk), + .D(\blk00000003/sig000009c0 ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bb ( + .C(clk), + .D(\blk00000003/sig000009bf ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ba ( + .C(clk), + .D(\blk00000003/sig000009bd ), + .R(sclr), + .Q(\blk00000003/sig000009be ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b9 ( + .C(clk), + .D(\blk00000003/sig000009bc ), + .R(sclr), + .Q(\blk00000003/sig000009af ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b8 ( + .C(clk), + .D(\blk00000003/sig000009bb ), + .R(sclr), + .Q(\blk00000003/sig000009ae ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig00000935 ), + .O(\blk00000003/sig0000092f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig00000934 ), + .O(\blk00000003/sig0000092c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig00000933 ), + .O(\blk00000003/sig00000929 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig00000932 ), + .O(\blk00000003/sig00000926 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000923 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000028e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig00000260 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig000009ae ), + .O(\blk00000003/sig000000b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a5 ), + .R(sclr), + .Q(\blk00000003/sig000009aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a2 ), + .R(sclr), + .Q(\blk00000003/sig000009a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099f ), + .R(sclr), + .Q(\blk00000003/sig000009a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099c ), + .R(sclr), + .Q(\blk00000003/sig000009a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000999 ), + .R(sclr), + .Q(\blk00000003/sig000009a6 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .S(sclr), + .Q(\blk00000003/sig00000936 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .S(sclr), + .Q(\blk00000003/sig00000935 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .S(sclr), + .Q(\blk00000003/sig00000934 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .S(sclr), + .Q(\blk00000003/sig00000933 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .R(sclr), + .Q(\blk00000003/sig00000932 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .S(sclr), + .Q(\blk00000003/sig00000931 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig000002a0 ) + ); + FDR \blk00000003/blk000008a1 ( + .C(clk), + .D(\blk00000003/sig000009ba ), + .R(ce), + .Q(\blk00000003/sig000009b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .R(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig0000029a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .S(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig00000295 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028f ), + .S(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000292 ), + .R(sclr), + .Q(\blk00000003/sig00000293 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000289 ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028c ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDR \blk00000003/blk0000089a ( + .C(clk), + .D(\blk00000003/sig000009b9 ), + .R(ce), + .Q(\blk00000003/sig000009b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000899 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000261 ), + .R(\blk00000003/sig00000264 ), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000898 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000897 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000259 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000896 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000256 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000895 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000225 ), + .R(coef_ld), + .Q(\blk00000003/sig00000223 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000894 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b4 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000998 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000892 ( + .I0(\blk00000003/sig000009a7 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000891 ( + .I0(\blk00000003/sig000009a8 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000890 ( + .I0(\blk00000003/sig000009a9 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009a1 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk0000088f ( + .I0(\blk00000003/sig000009aa ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000009a4 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000088e ( + .I0(\blk00000003/sig000001dc ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000996 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000994 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000995 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000993 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000991 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000992 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000990 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000887 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000098e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000886 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000098f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000885 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000098d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig0000098b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig0000098c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig0000098a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000988 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000989 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000987 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000985 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000986 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000984 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000982 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000983 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000981 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000097f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000877 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000980 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000876 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000097e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000875 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig0000097c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000097d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig0000097b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000979 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig0000097a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000978 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000976 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000977 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000975 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000973 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000974 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000972 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000970 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000971 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000096f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000866 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000096d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000865 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000096e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig0000096c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig0000096a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig0000096b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000969 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000968 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000966 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000967 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000965 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000963 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000964 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000962 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000859 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000960 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000858 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000961 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000857 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000095f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000856 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000095d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000855 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000095e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000854 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig0000095c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000853 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig0000095a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000852 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig0000095b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000851 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000959 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000850 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000957 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000958 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000956 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000954 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000955 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000953 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000951 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000849 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000952 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000848 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000950 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000847 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000094e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000846 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000094f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000845 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000094d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000844 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig0000094b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000843 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig0000094c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000842 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig0000094a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000841 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000948 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000840 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000949 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000947 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000945 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000946 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000944 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000942 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000943 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000839 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000941 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000838 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000093f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000837 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000940 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000836 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000093e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000835 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ad ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000093c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000834 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ac ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000093d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000833 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ae ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000093b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000832 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b0 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000939 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000831 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001af ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000093a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000830 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b1 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000938 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000082f ( + .I0(\blk00000003/sig00000936 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000920 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082e ( + .I0(ce), + .I1(\blk00000003/sig000001de ), + .O(\blk00000003/sig000009b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082d ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/sig000009b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082c ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/sig000009b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082b ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/sig000009b5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082a ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/sig000009b4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000829 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/sig0000091e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000828 ( + .I0(sclr), + .I1(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig0000029d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000827 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .O(\blk00000003/sig00000298 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000826 ( + .I0(\blk00000003/sig00000295 ), + .I1(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig00000296 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000825 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .I2(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000824 ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig00000291 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000823 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000822 ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000821 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig00000288 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000820 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000284 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081f ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig0000023f ), + .O(\blk00000003/sig00000281 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081e ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000027f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081d ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081c ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081b ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081a ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000819 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000247 ), + .I2(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000818 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000268 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000817 ( + .I0(\blk00000003/sig00000241 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000026a ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000816 ( + .I0(\blk00000003/sig00000250 ), + .I1(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig00000263 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000815 ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .I2(\blk00000003/sig0000022f ), + .O(\blk00000003/sig0000025a ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk00000814 ( + .I0(coef_we), + .I1(\blk00000003/sig0000025d ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000252 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000813 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000246 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000812 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000811 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig0000023b ), + .O(\blk00000003/sig0000024e ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000810 ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022c ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000080f ( + .I0(\blk00000003/sig0000025c ), + .I1(\blk00000003/sig0000025b ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080e ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080d ( + .I0(coef_we), + .I1(\blk00000003/sig0000023b ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000021f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000080c ( + .I0(\blk00000003/sig00000223 ), + .I1(coef_we), + .O(\blk00000003/sig00000224 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000080b ( + .I0(\blk00000003/sig0000023b ), + .I1(coef_we), + .I2(\blk00000003/sig0000022f ), + .I3(\blk00000003/sig00000227 ), + .I4(coef_ld), + .O(\blk00000003/sig0000023a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000080a ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000238 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000809 ( + .I0(\blk00000003/sig000000ad ), + .I1(nd), + .O(\blk00000003/sig000001e6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000808 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000001e4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk00000807 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000009b0 ), + .O(\blk00000003/sig000000c7 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000806 ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000001dd ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000805 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig000009a7 ), + .I2(\blk00000003/sig000009a8 ), + .I3(\blk00000003/sig000009a9 ), + .I4(\blk00000003/sig000009aa ), + .O(\blk00000003/sig000000c9 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000804 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000001ca ), + .I2(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000803 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001d8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000802 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000bc ), + .O(\blk00000003/sig000000bb ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000801 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000ba ), + .O(\blk00000003/sig000000b9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000800 ( + .I0(\blk00000003/sig000000b4 ), + .I1(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000000b5 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk000007ff ( + .I0(\blk00000003/sig000001ca ), + .I1(\blk00000003/sig000001e5 ), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .I4(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk000007fe ( + .I0(\blk00000003/sig000001d5 ), + .I1(\blk00000003/sig000009af ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d0 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000007fd ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000000b0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk000007fc ( + .I0(\blk00000003/sig000001e5 ), + .I1(\blk00000003/sig000001d5 ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk000007fb ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001da ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk000007fa ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000009ad ), + .I3(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b7 ) + ); + MUXCY \blk00000003/blk000007f9 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig000009ab ), + .O(\blk00000003/sig000009a3 ) + ); + MUXCY_L \blk00000003/blk000007f8 ( + .CI(\blk00000003/sig000009a3 ), + .DI(\blk00000003/sig000009aa ), + .S(\blk00000003/sig000009a4 ), + .LO(\blk00000003/sig000009a0 ) + ); + MUXCY_L \blk00000003/blk000007f7 ( + .CI(\blk00000003/sig000009a0 ), + .DI(\blk00000003/sig000009a9 ), + .S(\blk00000003/sig000009a1 ), + .LO(\blk00000003/sig0000099d ) + ); + MUXCY_L \blk00000003/blk000007f6 ( + .CI(\blk00000003/sig0000099d ), + .DI(\blk00000003/sig000009a8 ), + .S(\blk00000003/sig0000099e ), + .LO(\blk00000003/sig0000099a ) + ); + MUXCY_L \blk00000003/blk000007f5 ( + .CI(\blk00000003/sig0000099a ), + .DI(\blk00000003/sig000009a7 ), + .S(\blk00000003/sig0000099b ), + .LO(\blk00000003/sig00000997 ) + ); + MUXCY_D \blk00000003/blk000007f4 ( + .CI(\blk00000003/sig00000997 ), + .DI(\blk00000003/sig000009a6 ), + .S(\blk00000003/sig00000998 ), + .O(\NLW_blk00000003/blk000007f4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007f4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig000009a3 ), + .LI(\blk00000003/sig000009a4 ), + .O(\blk00000003/sig000009a5 ) + ); + XORCY \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig000009a0 ), + .LI(\blk00000003/sig000009a1 ), + .O(\blk00000003/sig000009a2 ) + ); + XORCY \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig0000099d ), + .LI(\blk00000003/sig0000099e ), + .O(\blk00000003/sig0000099f ) + ); + XORCY \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig0000099a ), + .LI(\blk00000003/sig0000099b ), + .O(\blk00000003/sig0000099c ) + ); + XORCY \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000997 ), + .LI(\blk00000003/sig00000998 ), + .O(\blk00000003/sig00000999 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000996 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000995 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000994 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000993 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000992 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000991 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000990 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000989 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000988 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000987 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000986 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000985 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000984 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000983 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000982 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000981 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000980 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000979 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000978 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000977 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000976 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000975 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000974 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000973 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000972 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000971 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000970 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000969 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000968 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000967 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000966 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000965 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000964 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000963 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000962 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000961 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000960 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000959 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000958 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000957 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000956 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000955 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000954 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000953 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000952 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000951 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000950 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000949 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000948 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000947 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000946 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000945 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000944 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000943 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000942 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000941 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000940 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000001dc ) + ); + MUXCY_L \blk00000003/blk0000078e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000936 ), + .S(\blk00000003/sig00000920 ), + .LO(\blk00000003/sig0000092e ) + ); + MUXCY_L \blk00000003/blk0000078d ( + .CI(\blk00000003/sig0000092e ), + .DI(\blk00000003/sig00000935 ), + .S(\blk00000003/sig0000092f ), + .LO(\blk00000003/sig0000092b ) + ); + MUXCY_L \blk00000003/blk0000078c ( + .CI(\blk00000003/sig0000092b ), + .DI(\blk00000003/sig00000934 ), + .S(\blk00000003/sig0000092c ), + .LO(\blk00000003/sig00000928 ) + ); + MUXCY_L \blk00000003/blk0000078b ( + .CI(\blk00000003/sig00000928 ), + .DI(\blk00000003/sig00000933 ), + .S(\blk00000003/sig00000929 ), + .LO(\blk00000003/sig00000925 ) + ); + MUXCY_L \blk00000003/blk0000078a ( + .CI(\blk00000003/sig00000925 ), + .DI(\blk00000003/sig00000932 ), + .S(\blk00000003/sig00000926 ), + .LO(\blk00000003/sig00000922 ) + ); + MUXCY_D \blk00000003/blk00000789 ( + .CI(\blk00000003/sig00000922 ), + .DI(\blk00000003/sig00000931 ), + .S(\blk00000003/sig00000923 ), + .O(\NLW_blk00000003/blk00000789_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000789_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000788 ( + .CI(\blk00000003/sig0000092e ), + .LI(\blk00000003/sig0000092f ), + .O(\blk00000003/sig00000930 ) + ); + XORCY \blk00000003/blk00000787 ( + .CI(\blk00000003/sig0000092b ), + .LI(\blk00000003/sig0000092c ), + .O(\blk00000003/sig0000092d ) + ); + XORCY \blk00000003/blk00000786 ( + .CI(\blk00000003/sig00000928 ), + .LI(\blk00000003/sig00000929 ), + .O(\blk00000003/sig0000092a ) + ); + XORCY \blk00000003/blk00000785 ( + .CI(\blk00000003/sig00000925 ), + .LI(\blk00000003/sig00000926 ), + .O(\blk00000003/sig00000927 ) + ); + XORCY \blk00000003/blk00000784 ( + .CI(\blk00000003/sig00000922 ), + .LI(\blk00000003/sig00000923 ), + .O(\blk00000003/sig00000924 ) + ); + XORCY \blk00000003/blk00000783 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000920 ), + .O(\blk00000003/sig00000921 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000779 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000778 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000777 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000776 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000775 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c5 ), + .R(sclr), + .Q(\blk00000003/sig0000076c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c4 ), + .R(sclr), + .Q(\blk00000003/sig0000076b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c3 ), + .R(sclr), + .Q(\blk00000003/sig0000076a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c2 ), + .R(sclr), + .Q(\blk00000003/sig00000769 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c1 ), + .R(sclr), + .Q(\blk00000003/sig00000768 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c0 ), + .R(sclr), + .Q(\blk00000003/sig00000767 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bf ), + .R(sclr), + .Q(\blk00000003/sig00000766 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003be ), + .R(sclr), + .Q(\blk00000003/sig00000765 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bd ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bc ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bb ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000432 ), + .R(sclr), + .Q(\blk00000003/sig00000791 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000431 ), + .R(sclr), + .Q(\blk00000003/sig00000790 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000430 ), + .R(sclr), + .Q(\blk00000003/sig0000078f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042f ), + .R(sclr), + .Q(\blk00000003/sig0000078e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000078d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042d ), + .R(sclr), + .Q(\blk00000003/sig0000078c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042c ), + .R(sclr), + .Q(\blk00000003/sig0000078b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042b ), + .R(sclr), + .Q(\blk00000003/sig0000078a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042a ), + .R(sclr), + .Q(\blk00000003/sig00000789 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000429 ), + .R(sclr), + .Q(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000428 ), + .R(sclr), + .Q(\blk00000003/sig00000787 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000427 ), + .R(sclr), + .Q(\blk00000003/sig00000786 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000426 ), + .R(sclr), + .Q(\blk00000003/sig00000785 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig0000077c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig0000077b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig0000077a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000295 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .R(sclr), + .Q(\blk00000003/sig00000744 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .R(sclr), + .Q(\blk00000003/sig00000742 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .R(sclr), + .Q(\blk00000003/sig00000743 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000741 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000740 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000739 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000738 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000737 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000736 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000733 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000735 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000734 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000733 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f2 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f2_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f2_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f2_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f2_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f2_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f2_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f2_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000703 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , \blk00000003/sig00000706 , +\blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , \blk00000003/sig0000070b , +\blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , \blk00000003/sig00000710 , +\blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , \blk00000003/sig00000715 , +\blk00000003/sig00000716 , \blk00000003/sig00000717 , \blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a }), + .P({\NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , +\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071c , \blk00000003/sig0000071d , \blk00000003/sig0000071e , +\blk00000003/sig0000071f , \blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , +\blk00000003/sig00000724 , \blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 , \blk00000003/sig00000728 , +\blk00000003/sig00000729 , \blk00000003/sig0000072a , \blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , +\blk00000003/sig0000072e , \blk00000003/sig0000072f , \blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 }), + .PCOUT({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f1 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000006a3 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , \blk00000003/sig000006a5 , \blk00000003/sig000006a6 , +\blk00000003/sig000006a7 , \blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , +\blk00000003/sig000006ac , \blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , +\blk00000003/sig000006b1 , \blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , +\blk00000003/sig000006b6 , \blk00000003/sig000006b7 , \blk00000003/sig000006b8 , \blk00000003/sig000006b9 , \blk00000003/sig000006ba }), + .P({\NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , +\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bc , \blk00000003/sig000006bd , \blk00000003/sig000006be , +\blk00000003/sig000006bf , \blk00000003/sig000006c0 , \blk00000003/sig000006c1 , \blk00000003/sig000006c2 , \blk00000003/sig000006c3 , +\blk00000003/sig000006c4 , \blk00000003/sig000006c5 , \blk00000003/sig000006c6 , \blk00000003/sig000006c7 , \blk00000003/sig000006c8 , +\blk00000003/sig000006c9 , \blk00000003/sig000006ca , \blk00000003/sig000006cb , \blk00000003/sig000006cc , \blk00000003/sig000006cd , +\blk00000003/sig000006ce , \blk00000003/sig000006cf , \blk00000003/sig000006d0 , \blk00000003/sig000006d1 , \blk00000003/sig000006d2 }), + .PCOUT({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f0 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000643 , \blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 , \blk00000003/sig00000646 , +\blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , \blk00000003/sig0000064b , +\blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , \blk00000003/sig00000650 , +\blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , \blk00000003/sig00000655 , +\blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a }), + .P({\NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , +\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , \blk00000003/sig0000065e , +\blk00000003/sig0000065f , \blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , \blk00000003/sig00000672 }), + .PCOUT({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ef ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e4 , \blk00000003/sig000005e5 , \blk00000003/sig000005e6 , +\blk00000003/sig000005e7 , \blk00000003/sig000005e8 , \blk00000003/sig000005e9 , \blk00000003/sig000005ea , \blk00000003/sig000005eb , +\blk00000003/sig000005ec , \blk00000003/sig000005ed , \blk00000003/sig000005ee , \blk00000003/sig000005ef , \blk00000003/sig000005f0 , +\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa }), + .P({\NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , +\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , +\blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , +\blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , +\blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , +\blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 }), + .PCOUT({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ee ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005b3 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , \blk00000003/sig000005b6 , +\blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , \blk00000003/sig000005bb , +\blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , \blk00000003/sig000005c0 , +\blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , \blk00000003/sig000005c5 , +\blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , \blk00000003/sig000005ca }), + .P({\NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , +\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , \blk00000003/sig000005e1 , \blk00000003/sig000005e2 }), + .PCOUT({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ed ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000541 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , \blk00000003/sig0000054d , \blk00000003/sig0000054e , +\blk00000003/sig0000054f , \blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , +\blk00000003/sig00000554 , \blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 }), + .P({\NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , +\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , +\blk00000003/sig0000055d , \blk00000003/sig0000055e , \blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , +\blk00000003/sig00000562 , \blk00000003/sig00000563 , \blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , +\blk00000003/sig00000567 , \blk00000003/sig00000568 , \blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , +\blk00000003/sig0000056c , \blk00000003/sig0000056d , \blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 }), + .PCOUT({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ec ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004cf , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , \blk00000003/sig000004d1 , \blk00000003/sig000004d2 , +\blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , +\blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da , \blk00000003/sig000004db , \blk00000003/sig000004dc , +\blk00000003/sig000004dd , \blk00000003/sig000004de , \blk00000003/sig000004df , \blk00000003/sig000004e0 , \blk00000003/sig000004e1 , +\blk00000003/sig000004e2 , \blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 , \blk00000003/sig000004e6 }), + .P({\NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , +\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed , \blk00000003/sig000004ee , \blk00000003/sig000004ef , +\blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , \blk00000003/sig000004f3 , \blk00000003/sig000004f4 , +\blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , \blk00000003/sig000004f8 , \blk00000003/sig000004f9 , +\blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , \blk00000003/sig000004fd , \blk00000003/sig000004fe }), + .PCOUT({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000eb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000045d , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 }), + .P({\NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , +\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , +\blk00000003/sig00000479 , \blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , +\blk00000003/sig0000047e , \blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , +\blk00000003/sig00000483 , \blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , +\blk00000003/sig00000488 , \blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .PCOUT({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ea ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000041b , \blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , +\blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , +\blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , +\blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d , +\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 }), + .P({\NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , +\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , +\blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , +\blk00000003/sig0000043c , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , +\blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , +\blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a }), + .PCOUT({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003bb , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 }), + .P({\NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , +\blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , +\blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , +\blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea }), + .PCOUT({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000319 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , +\blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , +\blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , +\blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , +\blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 }), + .P({\NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , +\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , \blk00000003/sig00000334 , +\blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , +\blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , +\blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , +\blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 }), + .PCOUT({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002b9 , \blk00000003/sig000002b9 , \blk00000003/sig000002ba , \blk00000003/sig000002bb , \blk00000003/sig000002bc , +\blk00000003/sig000002bd , \blk00000003/sig000002be , \blk00000003/sig000002bf , \blk00000003/sig000002c0 , \blk00000003/sig000002c1 , +\blk00000003/sig000002c2 , \blk00000003/sig000002c3 , \blk00000003/sig000002c4 , \blk00000003/sig000002c5 , \blk00000003/sig000002c6 , +\blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , \blk00000003/sig000002ca , \blk00000003/sig000002cb , +\blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , \blk00000003/sig000002cf , \blk00000003/sig000002d0 }), + .P({\NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , +\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , \blk00000003/sig000002d4 , +\blk00000003/sig000002d5 , \blk00000003/sig000002d6 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , +\blk00000003/sig000002da , \blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , +\blk00000003/sig000002df , \blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , +\blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 }), + .PCOUT({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig000002a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .Q(\blk00000003/sig0000029f ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000029f ), + .LI(\blk00000003/sig000002a1 ), + .O(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig000002a1 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029d ), + .Q(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig0000029a ), + .S(\blk00000003/sig0000029b ), + .O(\NLW_blk00000003/blk000000df_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000296 ), + .O(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000295 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000294 ), + .S(\blk00000003/sig0000028e ), + .LO(\blk00000003/sig00000290 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000293 ), + .S(\blk00000003/sig00000291 ), + .O(\NLW_blk00000003/blk000000da_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000290 ), + .LI(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000292 ) + ); + XORCY \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000028f ) + ); + MUXCY_L \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000287 ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig00000288 ), + .LO(\blk00000003/sig0000028a ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig0000028a ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig0000028b ), + .O(\NLW_blk00000003/blk000000d6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000287 ) + ); + XORCY \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig0000028b ), + .O(\blk00000003/sig0000028c ) + ); + XORCY \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000287 ), + .LI(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000289 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000277 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000285 ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000283 ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000276 ), + .S(\blk00000003/sig00000281 ), + .O(\blk00000003/sig0000027d ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig0000027d ), + .DI(\blk00000003/sig0000027e ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig00000249 ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000027a ), + .O(\NLW_blk00000003/blk000000cb_O_UNCONNECTED ), + .LO(\blk00000003/sig00000277 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000277 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000278 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000276 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000265 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000274 ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000273 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig0000026d ), + .LO(\NLW_blk00000003/blk000000c5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig0000026d ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .O(\blk00000003/sig0000026b ), + .LO(\NLW_blk00000003/blk000000c4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026b ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026c ), + .O(\blk00000003/sig00000267 ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026a ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\blk00000003/sig00000265 ) + ); + MUXCY_D \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000267 ), + .DI(\blk00000003/sig0000023e ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ), + .LO(\NLW_blk00000003/blk000000c1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000265 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000266 ) + ); + FDE \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000263 ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025e ), + .LI(\blk00000003/sig00000260 ), + .O(\blk00000003/sig00000261 ) + ); + MUXCY_D \blk00000003/blk000000bb ( + .CI(\blk00000003/sig0000025e ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig00000260 ), + .O(\NLW_blk00000003/blk000000bb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bb_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig0000025d ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig00000257 ), + .DI(\blk00000003/sig0000025c ), + .S(\blk00000003/sig00000258 ), + .LO(\blk00000003/sig00000254 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000254 ), + .DI(\blk00000003/sig0000025b ), + .S(\blk00000003/sig00000255 ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000025a ), + .O(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000257 ), + .LI(\blk00000003/sig00000258 ), + .O(\blk00000003/sig00000259 ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000254 ), + .LI(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000256 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000243 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .Q(\blk00000003/sig00000236 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .Q(\blk00000003/sig00000241 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000249 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig00000247 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000244 ), + .Q(\blk00000003/sig00000245 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000239 ), + .Q(\blk00000003/sig0000023d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a4_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\blk00000003/sig0000022f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000229 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000238 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig00000237 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000235 ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000232 ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig00000233 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000231 ), + .O(\blk00000003/sig0000022e ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig0000022e ), + .DI(\blk00000003/sig0000022f ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000099_O_UNCONNECTED ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022c ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000097_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(\blk00000003/sig00000228 ), + .O(\NLW_blk00000003/blk00000096_O_UNCONNECTED ), + .LO(\blk00000003/sig00000229 ) + ); + XORCY \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000224 ), + .O(\blk00000003/sig00000225 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000223 ), + .S(\blk00000003/sig00000224 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000093 ( + .CI(\blk00000003/sig0000021c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk00000091_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000090 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .D(\blk00000003/sig000000be ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(\blk00000003/sig000001dd ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001de ), + .R(sclr), + .Q(\blk00000003/sig000001df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dc ), + .R(\blk00000003/sig000001dd ), + .Q(rdy) + ); + FDRE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001da ), + .R(sclr), + .Q(\blk00000003/sig000001db ) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d8 ), + .S(sclr), + .Q(\blk00000003/sig000001d9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .R(sclr), + .Q(\blk00000003/sig000001d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d6 ), + .R(sclr), + .Q(\blk00000003/sig000001ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d4 ), + .R(sclr), + .Q(\blk00000003/sig000001d5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d2 ), + .R(sclr), + .Q(\blk00000003/sig000001d3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001d_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\blk00000003/sig000001d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c8 ), + .R(sclr), + .Q(\blk00000003/sig000000c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c3 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c4 ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig000001ca ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001cb ), + .O(\NLW_blk00000003/blk00000017_O_UNCONNECTED ), + .LO(\blk00000003/sig000001cc ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000016 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000016_P<47>_UNCONNECTED , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , +\blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 }), + .A({\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , +\blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , \blk00000003/sig000001ba , +\blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , +\blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 }), + .PCOUT({\NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000015 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000015_P<47>_UNCONNECTED , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , +\blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , +\blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , \blk00000003/sig00000118 , +\blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , \blk00000003/sig0000011d , +\blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , \blk00000003/sig00000122 , +\blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , \blk00000003/sig00000127 , +\blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , \blk00000003/sig0000012c , +\blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , \blk00000003/sig00000131 , +\blk00000003/sig00000132 , \blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , +\blk00000003/sig00000137 , \blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a }), + .A({\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , +\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013c , \blk00000003/sig0000013d , \blk00000003/sig0000013e , +\blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , \blk00000003/sig00000142 , \blk00000003/sig00000143 , +\blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , \blk00000003/sig00000147 , \blk00000003/sig00000148 , +\blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , \blk00000003/sig0000014c , \blk00000003/sig0000014d , +\blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , \blk00000003/sig00000151 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c9 ), + .O(\blk00000003/sig000000c5 ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000000c5 ), + .DI(\blk00000003/sig000000c6 ), + .S(\blk00000003/sig000000c7 ), + .O(\blk00000003/sig000000bd ), + .LO(\blk00000003/sig000000c8 ) + ); + XORCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000000c3 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000000c4 ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000000c0 ), + .DI(\blk00000003/sig000000c1 ), + .S(\blk00000003/sig000000c2 ), + .O(\NLW_blk00000003/blk00000011_O_UNCONNECTED ), + .LO(\blk00000003/sig000000c3 ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000c0 ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000f ( + .C(clk), + .D(\blk00000003/sig000000bb ), + .Q(\blk00000003/sig000000bc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000e ( + .C(clk), + .D(\blk00000003/sig000000b9 ), + .Q(\blk00000003/sig000000ba ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .Q(\blk00000003/sig000000b8 ) + ); + XORCY \blk00000003/blk0000000c ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b6 ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000b4 ), + .S(\blk00000003/sig000000b5 ), + .O(\NLW_blk00000003/blk0000000b_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000af ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b3 ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b1 ), + .R(sclr), + .Q(\blk00000003/sig000000b2 ) + ); + MUXCY_D \blk00000003/blk00000008 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000ae ), + .LO(\NLW_blk00000003/blk00000008_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000007 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig000000ad ), + .S(nd), + .O(\blk00000003/sig000000af ), + .LO(\blk00000003/sig000000ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000ac ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002c/blk0000008e ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002c/sig00000c29 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c26 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c28 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c21 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c09 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c06 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c05 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c03 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c02 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c04 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c00 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c01 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c28 ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c27 ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c26 ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c25 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c24 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c23 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c22 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c21 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c20 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1f ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1e ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1d ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1c ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1b ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1a ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c19 ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c18 ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c17 ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c16 ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c15 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c14 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c13 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c12 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c11 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c10 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0f ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0e ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0d ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0c ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0b ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0a ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c09 ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c08 ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c07 ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c06 ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c05 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c04 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c03 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c02 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c01 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c00 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bff ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfe ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfd ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfc ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfb ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfa ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bf9 ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002c/blk0000002d ( + .G(\blk00000003/blk0000002c/sig00000bf8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000120/blk00000152 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000120/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000151 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000120/sig00000c75 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000150 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000120/sig00000c74 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000120/sig00000c76 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/blk00000120/sig00000c72 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/blk00000120/sig00000c71 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000120/sig00000c73 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/blk00000120/sig00000c6f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/blk00000120/sig00000c6e ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000149 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/blk00000120/sig00000c70 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000148 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/blk00000120/sig00000c6c ), + .Q15(\NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000147 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/blk00000120/sig00000c6b ), + .Q15(\NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000146 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/blk00000120/sig00000c6d ), + .Q15(\NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000145 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/blk00000120/sig00000c69 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000144 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/blk00000120/sig00000c68 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000143 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/blk00000120/sig00000c6a ), + .Q15(\NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000142 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/blk00000120/sig00000c66 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000141 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/blk00000120/sig00000c65 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000140 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/blk00000120/sig00000c67 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/blk00000120/sig00000c63 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/blk00000120/sig00000c62 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/blk00000120/sig00000c64 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/blk00000120/sig00000c60 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/blk00000120/sig00000c5f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/blk00000120/sig00000c61 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c76 ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c75 ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c74 ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c73 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c72 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c71 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c70 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6f ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6e ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6d ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6c ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6b ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6a ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c69 ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c68 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c67 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c66 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c65 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c64 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c63 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c62 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c61 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c60 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c5f ), + .Q(\blk00000003/sig000003d2 ) + ); + GND \blk00000003/blk00000120/blk00000121 ( + .G(\blk00000003/blk00000120/sig00000c5e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000185 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk00000153/sig00000cc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000184 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000153/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000183 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000153/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000182 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000153/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000181 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000153/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000180 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000153/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000153/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000153/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000153/sig00000cbc ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017c ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000153/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017b ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000153/sig00000cba ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017a ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000153/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000179 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000153/sig00000cbb ), + .Q15(\NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000178 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000153/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000177 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000153/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000176 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000153/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000175 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000153/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000153/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000153/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk00000153/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk00000153/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000153/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk00000153/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk00000153/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk00000153/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc4 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc3 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc2 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc1 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc0 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbf ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbe ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbd ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbc ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbb ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cba ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb9 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb8 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb7 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb6 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb5 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb4 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb3 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb2 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb1 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb0 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000caf ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cae ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cad ), + .Q(\blk00000003/sig000003ea ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000186/blk000001b8 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000186/sig00000d13 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk00000186/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk00000186/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk00000186/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk00000186/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk00000186/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk00000186/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk00000186/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk00000186/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001af ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk00000186/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ae ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/blk00000186/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ad ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/blk00000186/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ac ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk00000186/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ab ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/blk00000186/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001aa ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/blk00000186/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a9 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/blk00000186/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a8 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/blk00000186/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/blk00000186/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/blk00000186/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/blk00000186/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/blk00000186/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/blk00000186/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/blk00000186/sig00000cfc ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/blk00000186/sig00000cfb ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/blk00000186/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d12 ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d11 ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d10 ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0f ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0e ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0d ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000199 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0c ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0b ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0a ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d09 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d08 ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d07 ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d06 ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d05 ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d04 ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d03 ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d02 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d01 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d00 ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cff ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfe ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfd ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfc ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfb ), + .Q(\blk00000003/sig00000432 ) + ); + GND \blk00000003/blk00000186/blk00000187 ( + .G(\blk00000003/blk00000186/sig00000cfa ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b9/blk000001eb ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk000001b9/sig00000d61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001ea ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk000001b9/sig00000d5f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk000001b9/sig00000d5e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk000001b9/sig00000d60 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk000001b9/sig00000d5c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk000001b9/sig00000d5b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk000001b9/sig00000d5d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk000001b9/sig00000d59 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk000001b9/sig00000d58 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e2 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk000001b9/sig00000d5a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e1 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk000001b9/sig00000d56 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e0 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/blk000001b9/sig00000d55 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001df ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk000001b9/sig00000d57 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001de ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/blk000001b9/sig00000d53 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dd ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/blk000001b9/sig00000d52 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dc ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/blk000001b9/sig00000d54 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001db ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/blk000001b9/sig00000d50 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001da ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/blk000001b9/sig00000d4f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/blk000001b9/sig00000d51 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/blk000001b9/sig00000d4d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/blk000001b9/sig00000d4c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/blk000001b9/sig00000d4e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/blk000001b9/sig00000d4a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/blk000001b9/sig00000d49 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/blk000001b9/sig00000d4b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d60 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5f ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5e ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5d ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5c ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5b ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5a ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d59 ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d58 ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d57 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d56 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d55 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d54 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d53 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d52 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d51 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d50 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4f ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4e ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4d ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4c ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4b ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4a ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d49 ), + .Q(\blk00000003/sig0000044a ) + ); + GND \blk00000003/blk000001b9/blk000001ba ( + .G(\blk00000003/blk000001b9/sig00000d48 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000021e ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk000001ec/sig00000daf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk000001ec/sig00000dad ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk000001ec/sig00000dac ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk000001ec/sig00000dae ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk000001ec/sig00000daa ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000219 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk000001ec/sig00000da9 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000218 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk000001ec/sig00000dab ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000217 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000001ec/sig00000da7 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000216 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000001ec/sig00000da6 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000215 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk000001ec/sig00000da8 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000214 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000001ec/sig00000da4 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000213 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000001ec/sig00000da3 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000212 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000001ec/sig00000da5 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000211 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000001ec/sig00000da1 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000210 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000001ec/sig00000da0 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000001ec/sig00000da2 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk000001ec/sig00000d9e ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk000001ec/sig00000d9d ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk000001ec/sig00000d9f ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk000001ec/sig00000d9b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk000001ec/sig00000d9a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk000001ec/sig00000d9c ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000001ec/sig00000d98 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000001ec/sig00000d97 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk000001ec/sig00000d99 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dae ), + .Q(\blk00000003/sig000005b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dad ), + .Q(\blk00000003/sig000005b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000203 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dac ), + .Q(\blk00000003/sig000005b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000202 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dab ), + .Q(\blk00000003/sig000005b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000201 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000daa ), + .Q(\blk00000003/sig000005b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000200 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da9 ), + .Q(\blk00000003/sig000005b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da8 ), + .Q(\blk00000003/sig000005b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da7 ), + .Q(\blk00000003/sig000005ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da6 ), + .Q(\blk00000003/sig000005bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da5 ), + .Q(\blk00000003/sig000005bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da4 ), + .Q(\blk00000003/sig000005bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da3 ), + .Q(\blk00000003/sig000005be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da2 ), + .Q(\blk00000003/sig000005bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da1 ), + .Q(\blk00000003/sig000005c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da0 ), + .Q(\blk00000003/sig000005c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9f ), + .Q(\blk00000003/sig000005c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9e ), + .Q(\blk00000003/sig000005c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9d ), + .Q(\blk00000003/sig000005c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9c ), + .Q(\blk00000003/sig000005c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9b ), + .Q(\blk00000003/sig000005c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9a ), + .Q(\blk00000003/sig000005c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d99 ), + .Q(\blk00000003/sig000005c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d98 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d97 ), + .Q(\blk00000003/sig000005ca ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig00000d96 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000021f/blk00000251 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk0000021f/sig00000dfd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000250 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/blk0000021f/sig00000dfb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/blk0000021f/sig00000dfa ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/blk0000021f/sig00000dfc ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/blk0000021f/sig00000df8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/blk0000021f/sig00000df7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/blk0000021f/sig00000df9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/blk0000021f/sig00000df5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000249 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/blk0000021f/sig00000df4 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000248 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/blk0000021f/sig00000df6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000247 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/blk0000021f/sig00000df2 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000246 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/blk0000021f/sig00000df1 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000245 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/blk0000021f/sig00000df3 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000244 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/blk0000021f/sig00000def ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000243 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/blk0000021f/sig00000dee ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000242 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/blk0000021f/sig00000df0 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000241 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/blk0000021f/sig00000dec ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000240 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/blk0000021f/sig00000deb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/blk0000021f/sig00000ded ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/blk0000021f/sig00000de9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/blk0000021f/sig00000de8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/blk0000021f/sig00000dea ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/blk0000021f/sig00000de6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/blk0000021f/sig00000de5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000239 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/blk0000021f/sig00000de7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfc ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfb ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfa ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df9 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df8 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df7 ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df6 ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df5 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df4 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df3 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df2 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df1 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df0 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000def ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dee ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000ded ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dec ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000deb ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dea ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de9 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de8 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de7 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de6 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de5 ), + .Q(\blk00000003/sig000005e2 ) + ); + GND \blk00000003/blk0000021f/blk00000220 ( + .G(\blk00000003/blk0000021f/sig00000de4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000252/blk00000284 ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk00000252/sig00000e4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000283 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000252/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000282 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000252/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000281 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000252/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000280 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000252/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000252/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000252/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000252/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000252/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000252/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk00000252/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000279 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk00000252/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000278 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000252/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000277 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk00000252/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000276 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk00000252/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000275 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk00000252/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000274 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk00000252/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000273 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk00000252/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000272 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk00000252/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000271 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk00000252/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000270 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk00000252/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk00000252/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk00000252/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk00000252/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk00000252/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e4a ), + .Q(\blk00000003/sig00000703 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e49 ), + .Q(\blk00000003/sig00000704 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000269 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e48 ), + .Q(\blk00000003/sig00000705 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000268 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e47 ), + .Q(\blk00000003/sig00000706 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000267 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e46 ), + .Q(\blk00000003/sig00000707 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e45 ), + .Q(\blk00000003/sig00000708 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e44 ), + .Q(\blk00000003/sig00000709 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e43 ), + .Q(\blk00000003/sig0000070a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e42 ), + .Q(\blk00000003/sig0000070b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e41 ), + .Q(\blk00000003/sig0000070c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e40 ), + .Q(\blk00000003/sig0000070d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3f ), + .Q(\blk00000003/sig0000070e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3e ), + .Q(\blk00000003/sig0000070f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3d ), + .Q(\blk00000003/sig00000710 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3c ), + .Q(\blk00000003/sig00000711 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3b ), + .Q(\blk00000003/sig00000712 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3a ), + .Q(\blk00000003/sig00000713 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e39 ), + .Q(\blk00000003/sig00000714 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e38 ), + .Q(\blk00000003/sig00000715 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e37 ), + .Q(\blk00000003/sig00000716 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e36 ), + .Q(\blk00000003/sig00000717 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e35 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e34 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e33 ), + .Q(\blk00000003/sig0000071a ) + ); + GND \blk00000003/blk00000252/blk00000253 ( + .G(\blk00000003/blk00000252/sig00000e32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000285/blk000002b7 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk00000285/sig00000e99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/blk00000285/sig00000e97 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/blk00000285/sig00000e96 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/blk00000285/sig00000e98 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/blk00000285/sig00000e94 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/blk00000285/sig00000e93 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/blk00000285/sig00000e95 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/blk00000285/sig00000e91 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002af ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/blk00000285/sig00000e90 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ae ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/blk00000285/sig00000e92 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ad ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/blk00000285/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ac ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/blk00000285/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ab ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/blk00000285/sig00000e8f ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002aa ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/blk00000285/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a9 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/blk00000285/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a8 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/blk00000285/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a7 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/blk00000285/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/blk00000285/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/blk00000285/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/blk00000285/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/blk00000285/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/blk00000285/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/blk00000285/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/blk00000285/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk0000029f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/blk00000285/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e98 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e97 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e96 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e95 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e94 ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e93 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e92 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e91 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e90 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8f ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8e ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8d ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8c ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8b ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8a ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e89 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e88 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e87 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e86 ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e85 ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e84 ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e83 ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e82 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e81 ), + .Q(\blk00000003/sig00000732 ) + ); + GND \blk00000003/blk00000285/blk00000286 ( + .G(\blk00000003/blk00000285/sig00000e80 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b8/blk000002ea ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk000002b8/sig00000ee7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d0 ), + .Q(\blk00000003/blk000002b8/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d1 ), + .Q(\blk00000003/blk000002b8/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004cf ), + .Q(\blk00000003/blk000002b8/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d3 ), + .Q(\blk00000003/blk000002b8/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d4 ), + .Q(\blk00000003/blk000002b8/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d2 ), + .Q(\blk00000003/blk000002b8/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d6 ), + .Q(\blk00000003/blk000002b8/sig00000edf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d7 ), + .Q(\blk00000003/blk000002b8/sig00000ede ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e1 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d5 ), + .Q(\blk00000003/blk000002b8/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e0 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d9 ), + .Q(\blk00000003/blk000002b8/sig00000edc ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002df ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004da ), + .Q(\blk00000003/blk000002b8/sig00000edb ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002de ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d8 ), + .Q(\blk00000003/blk000002b8/sig00000edd ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dd ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dc ), + .Q(\blk00000003/blk000002b8/sig00000ed9 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dc ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dd ), + .Q(\blk00000003/blk000002b8/sig00000ed8 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002db ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004db ), + .Q(\blk00000003/blk000002b8/sig00000eda ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002da ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004df ), + .Q(\blk00000003/blk000002b8/sig00000ed6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e0 ), + .Q(\blk00000003/blk000002b8/sig00000ed5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004de ), + .Q(\blk00000003/blk000002b8/sig00000ed7 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e2 ), + .Q(\blk00000003/blk000002b8/sig00000ed3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e3 ), + .Q(\blk00000003/blk000002b8/sig00000ed2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e1 ), + .Q(\blk00000003/blk000002b8/sig00000ed4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/blk000002b8/sig00000ed0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/blk000002b8/sig00000ecf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e4 ), + .Q(\blk00000003/blk000002b8/sig00000ed1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee6 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee5 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee4 ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee3 ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee2 ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee1 ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee0 ), + .Q(\blk00000003/sig00000547 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edf ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ede ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edd ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edc ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edb ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000eda ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed9 ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed8 ), + .Q(\blk00000003/sig0000054f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed7 ), + .Q(\blk00000003/sig00000550 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed6 ), + .Q(\blk00000003/sig00000551 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed5 ), + .Q(\blk00000003/sig00000552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed4 ), + .Q(\blk00000003/sig00000553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed3 ), + .Q(\blk00000003/sig00000554 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed2 ), + .Q(\blk00000003/sig00000555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed1 ), + .Q(\blk00000003/sig00000556 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ecf ), + .Q(\blk00000003/sig00000558 ) + ); + GND \blk00000003/blk000002b8/blk000002b9 ( + .G(\blk00000003/blk000002b8/sig00000ece ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002eb/blk0000031d ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk000002eb/sig00000f35 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/blk000002eb/sig00000f33 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/blk000002eb/sig00000f32 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/blk000002eb/sig00000f34 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000319 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/blk000002eb/sig00000f30 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000318 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/blk000002eb/sig00000f2f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000317 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/blk000002eb/sig00000f31 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000316 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/blk000002eb/sig00000f2d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000315 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/blk000002eb/sig00000f2c ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000314 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/blk000002eb/sig00000f2e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000313 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/blk000002eb/sig00000f2a ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000312 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/blk000002eb/sig00000f29 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000311 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/blk000002eb/sig00000f2b ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000310 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/blk000002eb/sig00000f27 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/blk000002eb/sig00000f26 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/blk000002eb/sig00000f28 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/blk000002eb/sig00000f24 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/blk000002eb/sig00000f23 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/blk000002eb/sig00000f25 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/blk000002eb/sig00000f21 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000309 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/blk000002eb/sig00000f20 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000308 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/blk000002eb/sig00000f22 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000307 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002eb/sig00000f1e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000306 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002eb/sig00000f1d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000305 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/blk000002eb/sig00000f1f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000304 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f34 ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000303 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f33 ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000302 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f32 ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000301 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f31 ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000300 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f30 ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2f ), + .Q(\blk00000003/sig0000055e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2e ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2d ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2c ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2b ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2a ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f29 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f28 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f27 ), + .Q(\blk00000003/sig00000566 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f26 ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f25 ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f24 ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f23 ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f22 ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f21 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f20 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1f ), + .Q(\blk00000003/sig0000056e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1e ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1d ), + .Q(\blk00000003/sig00000570 ) + ); + GND \blk00000003/blk000002eb/blk000002ec ( + .G(\blk00000003/blk000002eb/sig00000f1c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000031e/blk00000350 ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk0000031e/sig00000f83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk0000031e/sig00000f81 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk0000031e/sig00000f80 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk0000031e/sig00000f82 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk0000031e/sig00000f7e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk0000031e/sig00000f7d ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk0000031e/sig00000f7f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000349 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk0000031e/sig00000f7b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000348 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk0000031e/sig00000f7a ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000347 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk0000031e/sig00000f7c ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000346 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk0000031e/sig00000f78 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000345 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk0000031e/sig00000f77 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000344 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk0000031e/sig00000f79 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000343 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk0000031e/sig00000f75 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000342 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/blk0000031e/sig00000f74 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000341 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk0000031e/sig00000f76 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000340 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/blk0000031e/sig00000f72 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/blk0000031e/sig00000f71 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/blk0000031e/sig00000f73 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/blk0000031e/sig00000f6f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/blk0000031e/sig00000f6e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/blk0000031e/sig00000f70 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/blk0000031e/sig00000f6c ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000339 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/blk0000031e/sig00000f6b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000338 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/blk0000031e/sig00000f6d ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f82 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f81 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f80 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7f ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7e ), + .Q(\blk00000003/sig000006a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7d ), + .Q(\blk00000003/sig000006a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7c ), + .Q(\blk00000003/sig000006a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7b ), + .Q(\blk00000003/sig000006aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7a ), + .Q(\blk00000003/sig000006ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f79 ), + .Q(\blk00000003/sig000006ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f78 ), + .Q(\blk00000003/sig000006ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f77 ), + .Q(\blk00000003/sig000006ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f76 ), + .Q(\blk00000003/sig000006af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f75 ), + .Q(\blk00000003/sig000006b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f74 ), + .Q(\blk00000003/sig000006b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f73 ), + .Q(\blk00000003/sig000006b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f72 ), + .Q(\blk00000003/sig000006b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f71 ), + .Q(\blk00000003/sig000006b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f70 ), + .Q(\blk00000003/sig000006b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6f ), + .Q(\blk00000003/sig000006b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6e ), + .Q(\blk00000003/sig000006b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6d ), + .Q(\blk00000003/sig000006b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6c ), + .Q(\blk00000003/sig000006b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6b ), + .Q(\blk00000003/sig000006ba ) + ); + GND \blk00000003/blk0000031e/blk0000031f ( + .G(\blk00000003/blk0000031e/sig00000f6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000351/blk00000383 ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk00000351/sig00000fd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000382 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk00000351/sig00000fcf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000381 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk00000351/sig00000fce ), + .Q15(\NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000380 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk00000351/sig00000fd0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk00000351/sig00000fcc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk00000351/sig00000fcb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk00000351/sig00000fcd ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk00000351/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk00000351/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk00000351/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000379 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk00000351/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000378 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk00000351/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000377 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk00000351/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000376 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk00000351/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000375 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/blk00000351/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000374 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk00000351/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000373 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/blk00000351/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000372 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/blk00000351/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000371 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/blk00000351/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000370 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/blk00000351/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/blk00000351/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/blk00000351/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/blk00000351/sig00000fba ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/blk00000351/sig00000fb9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/blk00000351/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000036a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fd0 ), + .Q(\blk00000003/sig000006bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000369 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcf ), + .Q(\blk00000003/sig000006bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000368 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fce ), + .Q(\blk00000003/sig000006bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000367 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcd ), + .Q(\blk00000003/sig000006be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000366 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcc ), + .Q(\blk00000003/sig000006bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000365 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcb ), + .Q(\blk00000003/sig000006c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000364 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fca ), + .Q(\blk00000003/sig000006c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000363 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc9 ), + .Q(\blk00000003/sig000006c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000362 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc8 ), + .Q(\blk00000003/sig000006c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc7 ), + .Q(\blk00000003/sig000006c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc6 ), + .Q(\blk00000003/sig000006c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc5 ), + .Q(\blk00000003/sig000006c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc4 ), + .Q(\blk00000003/sig000006c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc3 ), + .Q(\blk00000003/sig000006c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc2 ), + .Q(\blk00000003/sig000006c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc1 ), + .Q(\blk00000003/sig000006ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc0 ), + .Q(\blk00000003/sig000006cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbf ), + .Q(\blk00000003/sig000006cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbe ), + .Q(\blk00000003/sig000006cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbd ), + .Q(\blk00000003/sig000006ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbc ), + .Q(\blk00000003/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbb ), + .Q(\blk00000003/sig000006d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fba ), + .Q(\blk00000003/sig000006d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fb9 ), + .Q(\blk00000003/sig000006d2 ) + ); + GND \blk00000003/blk00000351/blk00000352 ( + .G(\blk00000003/blk00000351/sig00000fb8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000384/blk000003b6 ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk00000384/sig0000101f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk00000384/sig0000101d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk00000384/sig0000101c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk00000384/sig0000101e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk00000384/sig0000101a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk00000384/sig00001019 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk00000384/sig0000101b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003af ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk00000384/sig00001017 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ae ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk00000384/sig00001016 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ad ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk00000384/sig00001018 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ac ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk00000384/sig00001014 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ab ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk00000384/sig00001013 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003aa ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk00000384/sig00001015 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a9 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk00000384/sig00001011 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a8 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk00000384/sig00001010 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a7 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk00000384/sig00001012 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a6 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk00000384/sig0000100e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk00000384/sig0000100d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk00000384/sig0000100f ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk00000384/sig0000100b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk00000384/sig0000100a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk00000384/sig0000100c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk00000384/sig00001008 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk00000384/sig00001007 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk00000384/sig00001009 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101e ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101d ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101c ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101b ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101a ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001019 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001018 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001017 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001016 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001015 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001014 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001013 ), + .Q(\blk00000003/sig000004da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001012 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001011 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001010 ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100f ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100e ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100d ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100c ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100b ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100a ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001009 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001008 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001007 ), + .Q(\blk00000003/sig000004e6 ) + ); + GND \blk00000003/blk00000384/blk00000385 ( + .G(\blk00000003/blk00000384/sig00001006 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b7/blk000003e9 ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk000003b7/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/blk000003b7/sig0000106b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/blk000003b7/sig0000106a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/blk000003b7/sig0000106c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/blk000003b7/sig00001068 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/blk000003b7/sig00001067 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/blk000003b7/sig00001069 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/blk000003b7/sig00001065 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/blk000003b7/sig00001064 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e0 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/blk000003b7/sig00001066 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003df ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/blk000003b7/sig00001062 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003de ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/blk000003b7/sig00001061 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dd ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/blk000003b7/sig00001063 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dc ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/blk000003b7/sig0000105f ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003db ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/blk000003b7/sig0000105e ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003da ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/blk000003b7/sig00001060 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d9 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/blk000003b7/sig0000105c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/blk000003b7/sig0000105b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/blk000003b7/sig0000105d ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/blk000003b7/sig00001059 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/blk000003b7/sig00001058 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/blk000003b7/sig0000105a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/blk000003b7/sig00001056 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/blk000003b7/sig00001055 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/blk000003b7/sig00001057 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106c ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106b ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106a ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001069 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001068 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001067 ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001066 ), + .Q(\blk00000003/sig000004ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001065 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001064 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001063 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001062 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001061 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001060 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105f ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105e ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105d ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105c ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105b ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105a ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001059 ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001058 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001057 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001056 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001055 ), + .Q(\blk00000003/sig000004fe ) + ); + GND \blk00000003/blk000003b7/blk000003b8 ( + .G(\blk00000003/blk000003b7/sig00001054 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ea/blk0000041c ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk000003ea/sig000010bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/blk000003ea/sig000010b9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/blk000003ea/sig000010b8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000419 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/blk000003ea/sig000010ba ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000418 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/blk000003ea/sig000010b6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000417 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/blk000003ea/sig000010b5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000416 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/blk000003ea/sig000010b7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000415 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/blk000003ea/sig000010b3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000414 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/blk000003ea/sig000010b2 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000413 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/blk000003ea/sig000010b4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000412 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk000003ea/sig000010b0 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000411 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk000003ea/sig000010af ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000410 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk000003ea/sig000010b1 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk000003ea/sig000010ad ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk000003ea/sig000010ac ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040d ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk000003ea/sig000010ae ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040c ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk000003ea/sig000010aa ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/blk000003ea/sig000010a9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk000003ea/sig000010ab ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000409 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/blk000003ea/sig000010a7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000408 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/blk000003ea/sig000010a6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000407 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/blk000003ea/sig000010a8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000406 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/blk000003ea/sig000010a4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000405 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/blk000003ea/sig000010a3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000404 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/blk000003ea/sig000010a5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ba ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b9 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b8 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b7 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b6 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b5 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b4 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b3 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b2 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b1 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b0 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010af ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ae ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ad ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ac ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ab ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010aa ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a9 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a8 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a7 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a6 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a5 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a4 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a3 ), + .Q(\blk00000003/sig0000065a ) + ); + GND \blk00000003/blk000003ea/blk000003eb ( + .G(\blk00000003/blk000003ea/sig000010a2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041d/blk0000044f ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk0000041d/sig00001109 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/blk0000041d/sig00001107 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/blk0000041d/sig00001106 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/blk0000041d/sig00001108 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/blk0000041d/sig00001104 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/blk0000041d/sig00001103 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000449 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/blk0000041d/sig00001105 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000448 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/blk0000041d/sig00001101 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000447 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/blk0000041d/sig00001100 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000446 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/blk0000041d/sig00001102 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000445 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/blk0000041d/sig000010fe ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000444 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/blk0000041d/sig000010fd ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000443 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/blk0000041d/sig000010ff ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000442 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/blk0000041d/sig000010fb ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000441 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/blk0000041d/sig000010fa ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000440 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/blk0000041d/sig000010fc ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043f ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/blk0000041d/sig000010f8 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/blk0000041d/sig000010f7 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/blk0000041d/sig000010f9 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/blk0000041d/sig000010f5 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/blk0000041d/sig000010f4 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/blk0000041d/sig000010f6 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000439 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/blk0000041d/sig000010f2 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000438 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/blk0000041d/sig000010f1 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000437 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/blk0000041d/sig000010f3 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001108 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001107 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001106 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000433 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001105 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000432 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001104 ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000431 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001103 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000430 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001102 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001101 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001100 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010ff ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fe ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fd ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fc ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fb ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fa ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f9 ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f8 ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f7 ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f6 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f5 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f4 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f3 ), + .Q(\blk00000003/sig00000670 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f2 ), + .Q(\blk00000003/sig00000671 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f1 ), + .Q(\blk00000003/sig00000672 ) + ); + GND \blk00000003/blk0000041d/blk0000041e ( + .G(\blk00000003/blk0000041d/sig000010f0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000450/blk00000482 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk00000450/sig00001157 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000481 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/blk00000450/sig00001155 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000480 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/blk00000450/sig00001154 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/blk00000450/sig00001156 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/blk00000450/sig00001152 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/blk00000450/sig00001151 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/blk00000450/sig00001153 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/blk00000450/sig0000114f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/blk00000450/sig0000114e ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000479 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/blk00000450/sig00001150 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000478 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/blk00000450/sig0000114c ), + .Q15(\NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000477 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/blk00000450/sig0000114b ), + .Q15(\NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000476 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/blk00000450/sig0000114d ), + .Q15(\NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000475 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/blk00000450/sig00001149 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000474 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/blk00000450/sig00001148 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000473 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/blk00000450/sig0000114a ), + .Q15(\NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000472 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/blk00000450/sig00001146 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000471 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/blk00000450/sig00001145 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000470 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/blk00000450/sig00001147 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/blk00000450/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/blk00000450/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/blk00000450/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/blk00000450/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/blk00000450/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/blk00000450/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001156 ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001155 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001154 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001153 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001152 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001151 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000463 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001150 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000462 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114f ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114e ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114d ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114c ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114b ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114a ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001149 ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001148 ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001147 ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001146 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001145 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001144 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001143 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001142 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001141 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001140 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000113f ), + .Q(\blk00000003/sig00000474 ) + ); + GND \blk00000003/blk00000450/blk00000451 ( + .G(\blk00000003/blk00000450/sig0000113e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000483/blk000004b5 ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk00000483/sig000011a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/blk00000483/sig000011a3 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/blk00000483/sig000011a2 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/blk00000483/sig000011a4 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/blk00000483/sig000011a0 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/blk00000483/sig0000119f ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004af ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/blk00000483/sig000011a1 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ae ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000483/sig0000119d ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ad ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000483/sig0000119c ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ac ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000483/sig0000119e ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ab ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000483/sig0000119a ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004aa ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000483/sig00001199 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a9 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000483/sig0000119b ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a8 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000483/sig00001197 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a7 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000483/sig00001196 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a6 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000483/sig00001198 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a5 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000483/sig00001194 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000483/sig00001193 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000483/sig00001195 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000483/sig00001191 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000483/sig00001190 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000483/sig00001192 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/blk00000483/sig0000118e ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/blk00000483/sig0000118d ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000483/sig0000118f ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a4 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a3 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a2 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a1 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a0 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119f ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119e ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119d ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119c ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119b ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119a ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001199 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001198 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001197 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001196 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001195 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001194 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001193 ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001192 ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001191 ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001190 ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118f ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118e ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118d ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk00000483/blk00000484 ( + .G(\blk00000003/blk00000483/sig0000118c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004b6/blk000004e8 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk000004b6/sig000011f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/blk000004b6/sig000011f1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/blk000004b6/sig000011f0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/blk000004b6/sig000011f2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/blk000004b6/sig000011ee ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/blk000004b6/sig000011ed ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/blk000004b6/sig000011ef ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/blk000004b6/sig000011eb ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/blk000004b6/sig000011ea ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004df ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/blk000004b6/sig000011ec ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004de ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/blk000004b6/sig000011e8 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dd ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000324 ), + .Q(\blk00000003/blk000004b6/sig000011e7 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dc ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000322 ), + .Q(\blk00000003/blk000004b6/sig000011e9 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004db ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000326 ), + .Q(\blk00000003/blk000004b6/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004da ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000327 ), + .Q(\blk00000003/blk000004b6/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d9 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000325 ), + .Q(\blk00000003/blk000004b6/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d8 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000329 ), + .Q(\blk00000003/blk000004b6/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032a ), + .Q(\blk00000003/blk000004b6/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000328 ), + .Q(\blk00000003/blk000004b6/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032c ), + .Q(\blk00000003/blk000004b6/sig000011df ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032d ), + .Q(\blk00000003/blk000004b6/sig000011de ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032b ), + .Q(\blk00000003/blk000004b6/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032f ), + .Q(\blk00000003/blk000004b6/sig000011dc ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000330 ), + .Q(\blk00000003/blk000004b6/sig000011db ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032e ), + .Q(\blk00000003/blk000004b6/sig000011dd ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f2 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f1 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f0 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ef ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ee ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ed ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ec ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011eb ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ea ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e9 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e8 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e7 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e6 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e5 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e4 ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e3 ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e2 ), + .Q(\blk00000003/sig000005f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e1 ), + .Q(\blk00000003/sig000005f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e0 ), + .Q(\blk00000003/sig000005f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011df ), + .Q(\blk00000003/sig000005f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011de ), + .Q(\blk00000003/sig000005f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dd ), + .Q(\blk00000003/sig000005f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dc ), + .Q(\blk00000003/sig000005f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011db ), + .Q(\blk00000003/sig000005fa ) + ); + GND \blk00000003/blk000004b6/blk000004b7 ( + .G(\blk00000003/blk000004b6/sig000011da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e9/blk0000051b ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk000004e9/sig00001241 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000051a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/blk000004e9/sig0000123f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000519 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/blk000004e9/sig0000123e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000518 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/blk000004e9/sig00001240 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000517 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/blk000004e9/sig0000123c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000516 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/blk000004e9/sig0000123b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000515 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/blk000004e9/sig0000123d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000514 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/blk000004e9/sig00001239 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000513 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/blk000004e9/sig00001238 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000512 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/blk000004e9/sig0000123a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000511 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/blk000004e9/sig00001236 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000510 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/blk000004e9/sig00001235 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/blk000004e9/sig00001237 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/blk000004e9/sig00001233 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/blk000004e9/sig00001232 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050c ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/blk000004e9/sig00001234 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050b ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/blk000004e9/sig00001230 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/blk000004e9/sig0000122f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000509 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/blk000004e9/sig00001231 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000508 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/blk000004e9/sig0000122d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000507 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/blk000004e9/sig0000122c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000506 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/blk000004e9/sig0000122e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000505 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/blk000004e9/sig0000122a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000504 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/blk000004e9/sig00001229 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000503 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/blk000004e9/sig0000122b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001240 ), + .Q(\blk00000003/sig000005fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123f ), + .Q(\blk00000003/sig000005fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123e ), + .Q(\blk00000003/sig000005fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123d ), + .Q(\blk00000003/sig000005fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123c ), + .Q(\blk00000003/sig000005ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123b ), + .Q(\blk00000003/sig00000600 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123a ), + .Q(\blk00000003/sig00000601 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001239 ), + .Q(\blk00000003/sig00000602 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001238 ), + .Q(\blk00000003/sig00000603 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001237 ), + .Q(\blk00000003/sig00000604 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001236 ), + .Q(\blk00000003/sig00000605 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001235 ), + .Q(\blk00000003/sig00000606 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001234 ), + .Q(\blk00000003/sig00000607 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001233 ), + .Q(\blk00000003/sig00000608 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001232 ), + .Q(\blk00000003/sig00000609 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001231 ), + .Q(\blk00000003/sig0000060a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001230 ), + .Q(\blk00000003/sig0000060b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122f ), + .Q(\blk00000003/sig0000060c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122e ), + .Q(\blk00000003/sig0000060d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122d ), + .Q(\blk00000003/sig0000060e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122c ), + .Q(\blk00000003/sig0000060f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122b ), + .Q(\blk00000003/sig00000610 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122a ), + .Q(\blk00000003/sig00000611 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001229 ), + .Q(\blk00000003/sig00000612 ) + ); + GND \blk00000003/blk000004e9/blk000004ea ( + .G(\blk00000003/blk000004e9/sig00001228 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000051c/blk0000054e ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk0000051c/sig0000128f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/blk0000051c/sig0000128d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/blk0000051c/sig0000128c ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/blk0000051c/sig0000128e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/blk0000051c/sig0000128a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000549 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/blk0000051c/sig00001289 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000548 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/blk0000051c/sig0000128b ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000547 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/blk0000051c/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000546 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/blk0000051c/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000545 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/blk0000051c/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000544 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/blk0000051c/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000543 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/blk0000051c/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000542 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/blk0000051c/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000541 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/blk0000051c/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000540 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/blk0000051c/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/blk0000051c/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/blk0000051c/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/blk0000051c/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/blk0000051c/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/blk0000051c/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/blk0000051c/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000539 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/blk0000051c/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000538 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/blk0000051c/sig00001278 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000537 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/blk0000051c/sig00001277 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000536 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/blk0000051c/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128e ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128d ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128c ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128b ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128a ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001289 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001288 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001287 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001286 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001285 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001284 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001283 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001282 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001281 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001280 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127f ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127e ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127d ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127c ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127b ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127a ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001279 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001278 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001277 ), + .Q(\blk00000003/sig000002d0 ) + ); + GND \blk00000003/blk0000051c/blk0000051d ( + .G(\blk00000003/blk0000051c/sig00001276 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000054f/blk00000581 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk0000054f/sig000012dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000580 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/blk0000054f/sig000012db ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/blk0000054f/sig000012da ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/blk0000054f/sig000012dc ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/blk0000054f/sig000012d8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/blk0000054f/sig000012d7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/blk0000054f/sig000012d9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/blk0000054f/sig000012d5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000579 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/blk0000054f/sig000012d4 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000578 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/blk0000054f/sig000012d6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000577 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/blk0000054f/sig000012d2 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000576 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/blk0000054f/sig000012d1 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000575 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/blk0000054f/sig000012d3 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000574 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/blk0000054f/sig000012cf ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000573 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk0000054f/sig000012ce ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000572 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/blk0000054f/sig000012d0 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000571 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk0000054f/sig000012cc ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000570 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk0000054f/sig000012cb ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk0000054f/sig000012cd ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk0000054f/sig000012c9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk0000054f/sig000012c8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk0000054f/sig000012ca ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk0000054f/sig000012c6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk0000054f/sig000012c5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000569 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk0000054f/sig000012c7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012dc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012db ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012da ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ce ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ca ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk0000054f/blk00000550 ( + .G(\blk00000003/blk0000054f/sig000012c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000582/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk00000582/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk00000582/sig00001329 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk00000582/sig00001328 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk00000582/sig0000132a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk00000582/sig00001326 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005af ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk00000582/sig00001325 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ae ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk00000582/sig00001327 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ad ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/blk00000582/sig00001323 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ac ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/blk00000582/sig00001322 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ab ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/blk00000582/sig00001324 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005aa ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/blk00000582/sig00001320 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a9 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/blk00000582/sig0000131f ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a8 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/blk00000582/sig00001321 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a7 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/blk00000582/sig0000131d ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a6 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/blk00000582/sig0000131c ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a5 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/blk00000582/sig0000131e ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a4 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/blk00000582/sig0000131a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/blk00000582/sig00001319 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/blk00000582/sig0000131b ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/blk00000582/sig00001317 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/blk00000582/sig00001316 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/blk00000582/sig00001318 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/blk00000582/sig00001314 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/blk00000582/sig00001313 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/blk00000582/sig00001315 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000132a ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001329 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000599 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001328 ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000598 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001327 ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000597 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001326 ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000596 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001325 ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001324 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000594 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001323 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001322 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000592 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000591 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001320 ), + .Q(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000590 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131f ), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131e ), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131d ), + .Q(\blk00000003/sig00000326 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131c ), + .Q(\blk00000003/sig00000327 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131b ), + .Q(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131a ), + .Q(\blk00000003/sig00000329 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001319 ), + .Q(\blk00000003/sig0000032a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001318 ), + .Q(\blk00000003/sig0000032b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001317 ), + .Q(\blk00000003/sig0000032c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001316 ), + .Q(\blk00000003/sig0000032d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001315 ), + .Q(\blk00000003/sig0000032e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001314 ), + .Q(\blk00000003/sig0000032f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001313 ), + .Q(\blk00000003/sig00000330 ) + ); + GND \blk00000003/blk00000582/blk00000583 ( + .G(\blk00000003/blk00000582/sig00001312 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5/blk000005e7 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk000005b5/sig00001379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/blk000005b5/sig00001377 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/blk000005b5/sig00001376 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/blk000005b5/sig00001378 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/blk000005b5/sig00001374 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/blk000005b5/sig00001373 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/blk000005b5/sig00001375 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/blk000005b5/sig00001371 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005df ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/blk000005b5/sig00001370 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005de ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/blk000005b5/sig00001372 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dd ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/blk000005b5/sig0000136e ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dc ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/blk000005b5/sig0000136d ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005db ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/blk000005b5/sig0000136f ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005da ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/blk000005b5/sig0000136b ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d9 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/blk000005b5/sig0000136a ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d8 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/blk000005b5/sig0000136c ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d7 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/blk000005b5/sig00001368 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/blk000005b5/sig00001367 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/blk000005b5/sig00001369 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/blk000005b5/sig00001365 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/blk000005b5/sig00001364 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/blk000005b5/sig00001366 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/blk000005b5/sig00001362 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/blk000005b5/sig00001361 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005cf ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/blk000005b5/sig00001363 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001378 ), + .Q(\blk00000003/sig00000331 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001377 ), + .Q(\blk00000003/sig00000332 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001376 ), + .Q(\blk00000003/sig00000333 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001375 ), + .Q(\blk00000003/sig00000334 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001374 ), + .Q(\blk00000003/sig00000335 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001373 ), + .Q(\blk00000003/sig00000336 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001372 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001371 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001370 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136f ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136e ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136d ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136c ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136b ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136a ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001369 ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001368 ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001367 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001366 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001365 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001364 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001363 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001362 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001361 ), + .Q(\blk00000003/sig00000348 ) + ); + GND \blk00000003/blk000005b5/blk000005b6 ( + .G(\blk00000003/blk000005b5/sig00001360 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005e8/blk00000620 ( + .I0(ce), + .I1(\blk00000003/sig00000237 ), + .O(\blk00000003/blk000005e8/sig000013dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c9 ), + .DPO(\blk00000003/blk000005e8/sig000013db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c8 ), + .DPO(\blk00000003/blk000005e8/sig000013da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061d ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c7 ), + .DPO(\blk00000003/blk000005e8/sig000013d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061c ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c6 ), + .DPO(\blk00000003/blk000005e8/sig000013d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061b ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c5 ), + .DPO(\blk00000003/blk000005e8/sig000013d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061a ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c4 ), + .DPO(\blk00000003/blk000005e8/sig000013d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000619 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c2 ), + .DPO(\blk00000003/blk000005e8/sig000013d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000618 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c1 ), + .DPO(\blk00000003/blk000005e8/sig000013d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000617 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c3 ), + .DPO(\blk00000003/blk000005e8/sig000013d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000616 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c0 ), + .DPO(\blk00000003/blk000005e8/sig000013d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000615 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bf ), + .DPO(\blk00000003/blk000005e8/sig000013d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000614 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013be ), + .DPO(\blk00000003/blk000005e8/sig000013d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000613 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bd ), + .DPO(\blk00000003/blk000005e8/sig000013cf ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000612 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bc ), + .DPO(\blk00000003/blk000005e8/sig000013ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000611 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bb ), + .DPO(\blk00000003/blk000005e8/sig000013cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000610 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b9 ), + .DPO(\blk00000003/blk000005e8/sig000013cb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b8 ), + .DPO(\blk00000003/blk000005e8/sig000013ca ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013ba ), + .DPO(\blk00000003/blk000005e8/sig000013cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013db ), + .Q(\blk00000003/sig000002a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013da ), + .Q(\blk00000003/sig000002a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d9 ), + .Q(\blk00000003/sig000002a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d8 ), + .Q(\blk00000003/sig000002aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d7 ), + .Q(\blk00000003/sig000002ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d6 ), + .Q(\blk00000003/sig000002ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d5 ), + .Q(\blk00000003/sig000002ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d4 ), + .Q(\blk00000003/sig000002ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d3 ), + .Q(\blk00000003/sig000002af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d1 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000602 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d0 ), + .Q(\blk00000003/sig000002b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cf ), + .Q(\blk00000003/sig000002b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000600 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ce ), + .Q(\blk00000003/sig000002b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cd ), + .Q(\blk00000003/sig000002b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cc ), + .Q(\blk00000003/sig000002b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cb ), + .Q(\blk00000003/sig000002b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ca ), + .Q(\blk00000003/sig000002b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c9 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c8 ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c7 ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c6 ), + .Q(\blk00000003/sig000008c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c5 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c4 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c3 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c2 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c1 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c0 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bf ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013be ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bd ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bc ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bb ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ba ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b9 ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b8 ), + .Q(\blk00000003/sig000008d5 ) + ); + GND \blk00000003/blk000005e8/blk000005e9 ( + .G(\blk00000003/blk000005e8/sig000013b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000621/blk00000659 ( + .I0(ce), + .I1(\blk00000003/sig0000073d ), + .O(\blk00000003/blk00000621/sig0000143f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000658 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142c ), + .DPO(\blk00000003/blk00000621/sig0000143e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000657 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142b ), + .DPO(\blk00000003/blk00000621/sig0000143d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000656 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c6 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142a ), + .DPO(\blk00000003/blk00000621/sig0000143c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000655 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c7 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001429 ), + .DPO(\blk00000003/blk00000621/sig0000143b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000654 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c8 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001428 ), + .DPO(\blk00000003/blk00000621/sig0000143a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000653 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c9 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001427 ), + .DPO(\blk00000003/blk00000621/sig00001439 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000652 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cb ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001425 ), + .DPO(\blk00000003/blk00000621/sig00001437 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk00000651 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cc ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001424 ), + .DPO(\blk00000003/blk00000621/sig00001436 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000650 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ca ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001426 ), + .DPO(\blk00000003/blk00000621/sig00001438 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064f ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cd ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001423 ), + .DPO(\blk00000003/blk00000621/sig00001435 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064e ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ce ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001422 ), + .DPO(\blk00000003/blk00000621/sig00001434 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk0000064d ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cf ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001421 ), + .DPO(\blk00000003/blk00000621/sig00001433 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064c ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d0 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001420 ), + .DPO(\blk00000003/blk00000621/sig00001432 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064b ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d1 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141f ), + .DPO(\blk00000003/blk00000621/sig00001431 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk0000064a ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d2 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141e ), + .DPO(\blk00000003/blk00000621/sig00001430 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000649 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141c ), + .DPO(\blk00000003/blk00000621/sig0000142e ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000648 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141b ), + .DPO(\blk00000003/blk00000621/sig0000142d ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000647 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d3 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141d ), + .DPO(\blk00000003/blk00000621/sig0000142f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000646 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143e ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143d ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143c ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143b ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143a ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001439 ), + .Q(\blk00000003/sig00000450 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001438 ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001437 ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001436 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001435 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001434 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001433 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001432 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001431 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001430 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142f ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142e ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142d ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142c ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142b ), + .Q(\blk00000003/sig000008d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142a ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001429 ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001428 ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001427 ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001426 ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001425 ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001424 ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001423 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001422 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001421 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000628 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001420 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141f ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141e ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141d ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141c ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141b ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk00000621/blk00000622 ( + .G(\blk00000003/blk00000621/sig0000141a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000065a/blk00000692 ( + .I0(ce), + .I1(\blk00000003/sig0000073e ), + .O(\blk00000003/blk0000065a/sig000014a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000691 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148f ), + .DPO(\blk00000003/blk0000065a/sig000014a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000690 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148e ), + .DPO(\blk00000003/blk0000065a/sig000014a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068f ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d8 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148d ), + .DPO(\blk00000003/blk0000065a/sig0000149f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068e ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d9 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148c ), + .DPO(\blk00000003/blk0000065a/sig0000149e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068d ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008da ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148b ), + .DPO(\blk00000003/blk0000065a/sig0000149d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068c ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008db ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148a ), + .DPO(\blk00000003/blk0000065a/sig0000149c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk0000068b ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dd ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001488 ), + .DPO(\blk00000003/blk0000065a/sig0000149a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068a ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008de ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001487 ), + .DPO(\blk00000003/blk0000065a/sig00001499 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000689 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dc ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001489 ), + .DPO(\blk00000003/blk0000065a/sig0000149b ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000688 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008df ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001486 ), + .DPO(\blk00000003/blk0000065a/sig00001498 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000687 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e0 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001485 ), + .DPO(\blk00000003/blk0000065a/sig00001497 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk00000686 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e1 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001484 ), + .DPO(\blk00000003/blk0000065a/sig00001496 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000685 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e2 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001483 ), + .DPO(\blk00000003/blk0000065a/sig00001495 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000684 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e3 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001482 ), + .DPO(\blk00000003/blk0000065a/sig00001494 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000683 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e4 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001481 ), + .DPO(\blk00000003/blk0000065a/sig00001493 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000682 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147f ), + .DPO(\blk00000003/blk0000065a/sig00001491 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000681 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147e ), + .DPO(\blk00000003/blk0000065a/sig00001490 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000680 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e5 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001480 ), + .DPO(\blk00000003/blk0000065a/sig00001492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a1 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a0 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149f ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149e ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149d ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149c ), + .Q(\blk00000003/sig000004c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149b ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149a ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001499 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001498 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001497 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001496 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001495 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001494 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001493 ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001492 ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001491 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001490 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148f ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148e ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148d ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148c ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148b ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148a ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001489 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001488 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001487 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001486 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001485 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000662 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001484 ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001483 ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000660 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001482 ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001481 ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001480 ), + .Q(\blk00000003/sig000008f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147f ), + .Q(\blk00000003/sig000008f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147e ), + .Q(\blk00000003/sig000008f9 ) + ); + GND \blk00000003/blk0000065a/blk0000065b ( + .G(\blk00000003/blk0000065a/sig0000147d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000693/blk000006cb ( + .I0(ce), + .I1(\blk00000003/sig0000073f ), + .O(\blk00000003/blk00000693/sig00001505 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006ca ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f2 ), + .DPO(\blk00000003/blk00000693/sig00001504 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f1 ), + .DPO(\blk00000003/blk00000693/sig00001503 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c8 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ea ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f0 ), + .DPO(\blk00000003/blk00000693/sig00001502 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c7 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008eb ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ef ), + .DPO(\blk00000003/blk00000693/sig00001501 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c6 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ec ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ee ), + .DPO(\blk00000003/blk00000693/sig00001500 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006c5 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ed ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ed ), + .DPO(\blk00000003/blk00000693/sig000014ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c4 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ef ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014eb ), + .DPO(\blk00000003/blk00000693/sig000014fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c3 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f0 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ea ), + .DPO(\blk00000003/blk00000693/sig000014fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006c2 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ee ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ec ), + .DPO(\blk00000003/blk00000693/sig000014fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c1 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f1 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e9 ), + .DPO(\blk00000003/blk00000693/sig000014fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c0 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f2 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e8 ), + .DPO(\blk00000003/blk00000693/sig000014fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006bf ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f3 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e7 ), + .DPO(\blk00000003/blk00000693/sig000014f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006be ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f4 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e6 ), + .DPO(\blk00000003/blk00000693/sig000014f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bd ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f5 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e5 ), + .DPO(\blk00000003/blk00000693/sig000014f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bc ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f6 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e4 ), + .DPO(\blk00000003/blk00000693/sig000014f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006bb ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e2 ), + .DPO(\blk00000003/blk00000693/sig000014f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006ba ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e1 ), + .DPO(\blk00000003/blk00000693/sig000014f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006b9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f7 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e3 ), + .DPO(\blk00000003/blk00000693/sig000014f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001504 ), + .Q(\blk00000003/sig0000052f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001503 ), + .Q(\blk00000003/sig00000530 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001502 ), + .Q(\blk00000003/sig00000531 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001501 ), + .Q(\blk00000003/sig00000532 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001500 ), + .Q(\blk00000003/sig00000533 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ff ), + .Q(\blk00000003/sig00000534 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fe ), + .Q(\blk00000003/sig00000535 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fd ), + .Q(\blk00000003/sig00000536 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fc ), + .Q(\blk00000003/sig00000537 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fb ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fa ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f9 ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f8 ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f7 ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f6 ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f5 ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f4 ), + .Q(\blk00000003/sig0000053f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f3 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f2 ), + .Q(\blk00000003/sig000008fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f1 ), + .Q(\blk00000003/sig000008fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f0 ), + .Q(\blk00000003/sig000008fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ef ), + .Q(\blk00000003/sig000008fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ee ), + .Q(\blk00000003/sig000008fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ed ), + .Q(\blk00000003/sig000008ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ec ), + .Q(\blk00000003/sig00000900 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014eb ), + .Q(\blk00000003/sig00000901 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ea ), + .Q(\blk00000003/sig00000902 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e9 ), + .Q(\blk00000003/sig00000903 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e8 ), + .Q(\blk00000003/sig00000904 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e7 ), + .Q(\blk00000003/sig00000905 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e6 ), + .Q(\blk00000003/sig00000906 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e5 ), + .Q(\blk00000003/sig00000907 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e4 ), + .Q(\blk00000003/sig00000908 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e3 ), + .Q(\blk00000003/sig00000909 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e2 ), + .Q(\blk00000003/sig0000090a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e1 ), + .Q(\blk00000003/sig0000090b ) + ); + GND \blk00000003/blk00000693/blk00000694 ( + .G(\blk00000003/blk00000693/sig000014e0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006cc/blk00000704 ( + .I0(ce), + .I1(\blk00000003/sig00000740 ), + .O(\blk00000003/blk000006cc/sig00001568 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000703 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fa ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001555 ), + .DPO(\blk00000003/blk000006cc/sig00001567 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000702 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fb ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001554 ), + .DPO(\blk00000003/blk000006cc/sig00001566 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000701 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fc ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001553 ), + .DPO(\blk00000003/blk000006cc/sig00001565 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000700 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fd ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001552 ), + .DPO(\blk00000003/blk000006cc/sig00001564 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006ff ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fe ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001551 ), + .DPO(\blk00000003/blk000006cc/sig00001563 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fe ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008ff ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001550 ), + .DPO(\blk00000003/blk000006cc/sig00001562 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006fd ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000901 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154e ), + .DPO(\blk00000003/blk000006cc/sig00001560 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006fc ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000902 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154d ), + .DPO(\blk00000003/blk000006cc/sig0000155f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fb ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000900 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154f ), + .DPO(\blk00000003/blk000006cc/sig00001561 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006fa ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000903 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154c ), + .DPO(\blk00000003/blk000006cc/sig0000155e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f9 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000904 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154b ), + .DPO(\blk00000003/blk000006cc/sig0000155d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f8 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000905 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154a ), + .DPO(\blk00000003/blk000006cc/sig0000155c ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006f7 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000906 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001549 ), + .DPO(\blk00000003/blk000006cc/sig0000155b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f6 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000907 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001548 ), + .DPO(\blk00000003/blk000006cc/sig0000155a ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006f5 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000908 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001547 ), + .DPO(\blk00000003/blk000006cc/sig00001559 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f4 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090a ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001545 ), + .DPO(\blk00000003/blk000006cc/sig00001557 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f3 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090b ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001544 ), + .DPO(\blk00000003/blk000006cc/sig00001556 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f2 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000909 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001546 ), + .DPO(\blk00000003/blk000006cc/sig00001558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001567 ), + .Q(\blk00000003/sig000005a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001566 ), + .Q(\blk00000003/sig000005a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001565 ), + .Q(\blk00000003/sig000005a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001564 ), + .Q(\blk00000003/sig000005a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001563 ), + .Q(\blk00000003/sig000005a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001562 ), + .Q(\blk00000003/sig000005a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001561 ), + .Q(\blk00000003/sig000005a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001560 ), + .Q(\blk00000003/sig000005a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155f ), + .Q(\blk00000003/sig000005a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155e ), + .Q(\blk00000003/sig000005aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155d ), + .Q(\blk00000003/sig000005ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155c ), + .Q(\blk00000003/sig000005ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155b ), + .Q(\blk00000003/sig000005ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155a ), + .Q(\blk00000003/sig000005ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001559 ), + .Q(\blk00000003/sig000005af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001558 ), + .Q(\blk00000003/sig000005b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001557 ), + .Q(\blk00000003/sig000005b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001556 ), + .Q(\blk00000003/sig000005b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001555 ), + .Q(\blk00000003/sig0000090c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001554 ), + .Q(\blk00000003/sig0000090d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001553 ), + .Q(\blk00000003/sig0000090e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001552 ), + .Q(\blk00000003/sig0000090f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001551 ), + .Q(\blk00000003/sig00000910 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001550 ), + .Q(\blk00000003/sig00000911 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154f ), + .Q(\blk00000003/sig00000912 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154e ), + .Q(\blk00000003/sig00000913 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154d ), + .Q(\blk00000003/sig00000914 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154c ), + .Q(\blk00000003/sig00000915 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154b ), + .Q(\blk00000003/sig00000916 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154a ), + .Q(\blk00000003/sig00000917 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001549 ), + .Q(\blk00000003/sig00000918 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001548 ), + .Q(\blk00000003/sig00000919 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001547 ), + .Q(\blk00000003/sig0000091a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001546 ), + .Q(\blk00000003/sig0000091b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001545 ), + .Q(\blk00000003/sig0000091c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001544 ), + .Q(\blk00000003/sig0000091d ) + ); + GND \blk00000003/blk000006cc/blk000006cd ( + .G(\blk00000003/blk000006cc/sig00001543 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000705/blk0000072b ( + .I0(ce), + .I1(\blk00000003/sig00000741 ), + .O(\blk00000003/blk00000705/sig000015a7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000072a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk00000729 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000728 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090e ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000727 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090f ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000726 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000910 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000725 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000911 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000724 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000913 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000723 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000914 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000722 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000912 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000721 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000915 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000720 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000916 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159c ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk0000071f ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000917 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071e ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000918 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071d ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000919 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001599 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071c ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091a ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001598 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071b ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001596 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk0000071a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001595 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000719 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091b ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000718 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a6 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000717 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a5 ), + .Q(\blk00000003/sig000003aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000716 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a4 ), + .Q(\blk00000003/sig000003ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a3 ), + .Q(\blk00000003/sig000003ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a2 ), + .Q(\blk00000003/sig000003ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a1 ), + .Q(\blk00000003/sig000003ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a0 ), + .Q(\blk00000003/sig000003af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159f ), + .Q(\blk00000003/sig000003b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159e ), + .Q(\blk00000003/sig000003b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159d ), + .Q(\blk00000003/sig000003b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159c ), + .Q(\blk00000003/sig000003b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159b ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159a ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001599 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001598 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000709 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001597 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000708 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001596 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000707 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001595 ), + .Q(\blk00000003/sig000003ba ) + ); + GND \blk00000003/blk00000705/blk00000706 ( + .G(\blk00000003/blk00000705/sig00001594 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000075c/blk00000782 ( + .I0(ce), + .I1(\blk00000003/sig00000235 ), + .O(\blk00000003/blk0000075c/sig000015e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000075c/blk00000781 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000780 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077f ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077e ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077d ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015df ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077c ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015de ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077b ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077a ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000779 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000778 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000777 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000776 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000775 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000774 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000773 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000772 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000771 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000770 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e3 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e2 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e1 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e0 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015df ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015de ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dd ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dc ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015db ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015da ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d9 ), + .Q(\blk00000003/sig00000104 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d8 ), + .Q(\blk00000003/sig00000105 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d7 ), + .Q(\blk00000003/sig00000106 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d6 ), + .Q(\blk00000003/sig00000107 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d5 ), + .Q(\blk00000003/sig00000108 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d4 ), + .Q(\blk00000003/sig00000109 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d3 ), + .Q(\blk00000003/sig0000010a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d2 ), + .Q(\blk00000003/sig0000010b ) + ); + GND \blk00000003/blk0000075c/blk0000075d ( + .G(\blk00000003/blk0000075c/sig000015d1 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..e01cbfd43 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$3155~753-Xnzd}foo8#5+421).97 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17a2;2;7c:>e;d8?j41n3:1(9?i:3:3?k26m3;;76a=6d83>!26n383<6`;1d825>=h:?i1<7*;1g81<5=i<8o1=?54o34a>5<#<8l1>5>4n53f>45<3f8=m7>5$53e>7>73g>:i7?;;:m12<<72->:j7<70:l75`<6=21d>;650;&75c<5091e8e;3;?>i5><0;6):>f;0;4>h39l0:565`27694?"39o094=5a40g95d=d:9l60`=83.?=k4=819m04c=9l10c?;k:18'04`=:1:0b9?j:0d8?j42k3:1(9?i:3:3?k26m38;76a=5c83>!26n383<6`;1d815>=h:?54o37:>5<#<8l1>5>4n53f>75<3f8>47>5$53e>7>73g>:i7<;;:m112<72->:j7<70:l75`<5=21d>5950;&75c<5091e81290/8e;0;?>i50=0;6):>f;0;4>h39l09565`29194?"39o094=5a40g96d=50z&77d<5i?1C8974H51g?j4f=3:17pl;8983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3000;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3180;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3100;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i00;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3ik0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ab83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3im0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ad83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3io0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b983>c<729q/8>o54378L12>3A>8h6*=ae87?l?32900e4;50;9j=3<722c2;7>5;h;;>5<5<5<5<?6=44i566>5<5<i57>5f;294~"3;h0?>85G45;8L15c3-8jh7:4i8694?=n1<0;66g66;29?l?02900e4650;9j5d2=831b>5k50;9j6=`=831b>4>50;9j6<7=831b>4<50;9j012=831b89;50;9l061=831d>5j50;9~f1df290m6=4?{%60e?25=2B?845G42f8 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17a28o37c:>e;33?>i6ml0;6):>f;3f<>h39l0:=65`1df94?"39o0:i55a40g957=5:9l5`2=83.?=k4>e99m04c=9?10c50z&77d<5i?1C8974H51g?j4f=3:17pl83g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84c83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84e83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0==0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85683><<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<954?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<9n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41`<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:=4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>80;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`427<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:94?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0><0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`423<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:54?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42`<7200;6=u+42c906><@=>27E:6<729q/8>o52c`8L12>3A>8h6*=ae8;b>o5i10;66g=a883>>i4?>0;66s|200:>5<61rTm5638568:1>;0=1029638588:1>;0=h0296385c8:1>;0=j0296385e8:1>;0=l0296385g8:1>;0>9029638608:1>;0>;029638628:1>;0>=029638648:1>;0>?029638668:1>;0>1029638688:1>;0>h0296386c8:1>;0>j0296386e8:1>;0>l0296s|200b>5<61rTm;638568:0>;0=1028638588:0>;0=h0286385c8:0>;0=j0286385e8:0>;0=l0286385g8:0>;0>9028638608:0>;0>;028638628:0>;0>=028638648:0>;0>?028638668:0>;0>1028638688:0>;0>h0286386c8:0>;0>j0286386e8:0>;0>l0286s|200a>5<5sW;o<6386b82e1=z{;;9o7>52z\2g`=:??o1=l:4}r026a<72;qU=nj4=64g>4g33ty9=?k50;0xZ4ed34==57?n4:p644a2909wS?la:?42g<6i=1v??<0;296~X6k016;;o51`68yv46;80;6?uQ1b:8920128k?7p}=12094?4|V8i<70998;3b0>{t:8986=4={_3`2>;0>>0:m95rs3300?6=:rT:o85277195d2<>6<=8:181[7d:27<:=4>a59~w77403:1>vP>c09>334=9h>0q~<>3883>7}Y9m201:8>:0c7?xu59:k1<75<5sW;o:6385g82e1=z{;;8o7>52z\2`0=:?4g33ty9=>k50;0xZ4b434=>o7?n4:p645a2909wS?k2:?41g<6i=1v??;0;296~X6l816;8951`68yv46<80;6?uQ1b`8923>28k?7p}=15094?4|V8i;709:8;3b0>{t:8>86=4={_671>;0>o09m45rs3370?6=9hqU=5k4=61e>4>b34=?<7?7e:?404<60l16;9<519g89224282n709;4;3;a>;0<<0:4h5275495=c<5>><6<6j;<578d9>31g=91o01::m:0:f?813k3;3i6384e82<`=:?=o1=5k4=66e>4>b34=><7?7e:?414<60l16;8<519g89234282n709:4;3;a>;0=<0:4h5274495=c<5>515g8922628>n709;2;37a>;0<:0:8h52756951c<5>>>6<:j;<57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15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0??1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0><1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0181<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0191<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0121<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0131<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0081<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0091<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0021<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0031<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h21<7:?:34904}O<:n0(9=n:0466>\6w8;51e862?472;;1qdhi:18'04`=nl1e8:j7hj;o62a?7<3`li6=4+40d9b`=i<8o1>65f1g`94?"39o0:jl5a40g94>=n9o31<7*;1g82bd=i<8o1=65f1g:94?"39o0:jl5a40g96>=n9o=1<7*;1g82bd=i<8o1?65f1g494?"39o0:jl5a40g90>=n9o?1<7*;1g82bd=i<8o1965f1g694?"39o0:jl5a40g92>=n9o91<7*;1g82bd=i<8o1;65f23194?"39o0:jl5a40g9<>=n:;81<7*;1g82bd=i<8o1565f23394?"39o0:jl5a40g9e>=n:;:1<7*;1g82bd=i<8o1n65f20d94?"39o0:jl5a40g9g>=n:8o1<7*;1g82bd=i<8o1h65f20694?"39o0:jl5a40g9a>=n:931<7*;1g82bd=i<8o1j65f1gg94?"39o0:jl5a40g955=;;o62a?6<3`;;?7>5$53e>4633g>:i7?4;h335?6=,=;m6<>;;o62a?4<3`>?:7>5;h3;a?6=3`>8=7>5;h3:b?6=3f89h7>5$53e>74d3g>:i7>4;n01f?6=,=;m6?5$53e>74d3g>:i7<4;n01=?6=,=;m6?5$53e>74d3g>:i7:4;n013?6=,=;m6?5$53e>74d3g>:i784;n011?6=,=;m6?97>5$53e>74d3g>:i764;n060?6=,=;m6??7>5$53e>74d3g>:i7o4;n066?6=,=;m6?=7>5$53e>74d3g>:i7m4;n064?6=,=;m6?5$53e>74d3g>:i7k4;n00f?6=,=;m6?5$53e>74d3g>:i7??;:m161<72->:j7<=c:l75`<6921d>8h50;&75c<5=l1e88m50;&75c<5=l1e88o50;&75c<5=l1e88650;&75c<5=l1e85950;&75c<5=l1e85;50;&75c<5=l1e85=50;&75c<5=l1e8:650;&75c<5=l1e8;<50;&75c<5=l1e8"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ac83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?ij0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ae83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?il0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ag83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jh0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7bc83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jj0;6k4?:1y'06g=<;?0D9:6;I60`>"5im0=7d7;:188m<3=831b5;4?::k:3?6=3`336=44i0c7>5<5<5<5<>6=44o514>5<1<75f9483>>o>>3:17d78:188m<>=831b=l:50;9j6=c=831b>5h50;9j6<6=831b>4?50;9j6<4=831b89:50;9j013=831d8>950;9l6=b=831vn5lj:18e>5<7s->8m7:=5:J70<=O<:n0(?ok:59j=1<722c297>5;h;5>5<>o6i=0;66g=8d83>>o50o0;66g=9183>>o5180;66g=9383>>o3<=0;66g;4483>>i3;>0;66a=8e83>>{e0kl1<7h50;2x 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7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc37>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg71290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno?n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg7e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc3`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg7b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno<=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc07>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg41290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno<8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc0`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg4b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno==:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc17>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg51290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno=n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc1`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg5b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<;6=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc62>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc67>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg21290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<36=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc6:>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc6`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg2b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc77>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg31290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc7`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg3b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc47>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk<>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg01290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno88:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc4`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg0b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno8i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno9=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg1429026=4?{%60e?2402B?845G42f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v new file mode 100644 index 000000000..e5423434c --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec2.v @@ -0,0 +1,24109 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec2.v +// /___/ /\ Timestamp: Wed Dec 4 13:33:47 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec2.ngc ./tmp/_cg/hbdec2.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec2.ngc +// Output file : ./tmp/_cg/hbdec2.v +// # of Modules : 1 +// Design Name : hbdec2 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec2 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000767 ; + wire \blk00000003/sig00000766 ; + wire \blk00000003/sig00000765 ; + wire \blk00000003/sig00000764 ; + wire \blk00000003/sig00000763 ; + wire \blk00000003/sig00000762 ; + wire \blk00000003/sig00000761 ; + wire \blk00000003/sig00000760 ; + wire \blk00000003/sig0000075f ; + wire \blk00000003/sig0000075e ; + wire \blk00000003/sig0000075d ; + wire \blk00000003/sig0000075c ; + wire \blk00000003/sig0000075b ; + wire \blk00000003/sig0000075a ; + wire \blk00000003/sig00000759 ; + wire \blk00000003/sig00000758 ; + wire \blk00000003/sig00000757 ; + wire \blk00000003/sig00000756 ; + wire \blk00000003/sig00000755 ; + wire \blk00000003/sig00000754 ; + wire \blk00000003/sig00000753 ; + wire \blk00000003/sig00000752 ; + wire \blk00000003/sig00000751 ; + wire \blk00000003/sig00000750 ; + wire \blk00000003/sig0000074f ; + wire \blk00000003/sig0000074e ; + wire \blk00000003/sig0000074d ; + wire \blk00000003/sig0000074c ; + wire \blk00000003/sig0000074b ; + wire \blk00000003/sig0000074a ; + wire \blk00000003/sig00000749 ; + wire \blk00000003/sig00000748 ; + wire \blk00000003/sig00000747 ; + wire \blk00000003/sig00000746 ; + wire \blk00000003/sig00000745 ; + wire \blk00000003/sig00000744 ; + wire \blk00000003/sig00000743 ; + wire \blk00000003/sig00000742 ; + wire \blk00000003/sig00000741 ; + wire \blk00000003/sig00000740 ; + wire \blk00000003/sig0000073f ; + wire \blk00000003/sig0000073e ; + wire \blk00000003/sig0000073d ; + wire \blk00000003/sig0000073c ; + wire \blk00000003/sig0000073b ; + wire \blk00000003/sig0000073a ; + wire \blk00000003/sig00000739 ; + wire \blk00000003/sig00000738 ; + wire \blk00000003/sig00000737 ; + wire \blk00000003/sig00000736 ; + wire \blk00000003/sig00000735 ; + wire \blk00000003/sig00000734 ; + wire \blk00000003/sig00000733 ; + wire \blk00000003/sig00000732 ; + wire \blk00000003/sig00000731 ; + wire \blk00000003/sig00000730 ; + wire \blk00000003/sig0000072f ; + wire \blk00000003/sig0000072e ; + wire \blk00000003/sig0000072d ; + wire \blk00000003/sig0000072c ; + wire \blk00000003/sig0000072b ; + wire \blk00000003/sig0000072a ; + wire \blk00000003/sig00000729 ; + wire \blk00000003/sig00000728 ; + wire \blk00000003/sig00000727 ; + wire \blk00000003/sig00000726 ; + wire \blk00000003/sig00000725 ; + wire \blk00000003/sig00000724 ; + wire \blk00000003/sig00000723 ; + wire \blk00000003/sig00000722 ; + wire \blk00000003/sig00000721 ; + wire \blk00000003/sig00000720 ; + wire \blk00000003/sig0000071f ; + wire \blk00000003/sig0000071e ; + wire \blk00000003/sig0000071d ; + wire \blk00000003/sig0000071c ; + wire \blk00000003/sig0000071b ; + wire \blk00000003/sig0000071a ; + wire \blk00000003/sig00000719 ; + wire \blk00000003/sig00000718 ; + wire \blk00000003/sig00000717 ; + wire \blk00000003/sig00000716 ; + wire \blk00000003/sig00000715 ; + wire \blk00000003/sig00000714 ; + wire \blk00000003/sig00000713 ; + wire \blk00000003/sig00000712 ; + wire \blk00000003/sig00000711 ; + wire \blk00000003/sig00000710 ; + wire \blk00000003/sig0000070f ; + wire \blk00000003/sig0000070e ; + wire \blk00000003/sig0000070d ; + wire \blk00000003/sig0000070c ; + wire \blk00000003/sig0000070b ; + wire \blk00000003/sig0000070a ; + wire \blk00000003/sig00000709 ; + wire \blk00000003/sig00000708 ; + wire \blk00000003/sig00000707 ; + wire \blk00000003/sig00000706 ; + wire \blk00000003/sig00000705 ; + wire \blk00000003/sig00000704 ; + wire \blk00000003/sig00000703 ; + wire \blk00000003/sig00000702 ; + wire \blk00000003/sig00000701 ; + wire \blk00000003/sig00000700 ; + wire \blk00000003/sig000006ff ; + wire \blk00000003/sig000006fe ; + wire \blk00000003/sig000006fd ; + wire \blk00000003/sig000006fc ; + wire \blk00000003/sig000006fb ; + wire \blk00000003/sig000006fa ; + wire \blk00000003/sig000006f9 ; + wire \blk00000003/sig000006f8 ; + wire \blk00000003/sig000006f7 ; + wire \blk00000003/sig000006f6 ; + wire \blk00000003/sig000006f5 ; + wire \blk00000003/sig000006f4 ; + wire \blk00000003/sig000006f3 ; + wire \blk00000003/sig000006f2 ; + wire \blk00000003/sig000006f1 ; + wire \blk00000003/sig000006f0 ; + wire \blk00000003/sig000006ef ; + wire \blk00000003/sig000006ee ; + wire \blk00000003/sig000006ed ; + wire \blk00000003/sig000006ec ; + wire \blk00000003/sig000006eb ; + wire \blk00000003/sig000006ea ; + wire \blk00000003/sig000006e9 ; + wire \blk00000003/sig000006e8 ; + wire \blk00000003/sig000006e7 ; + wire \blk00000003/sig000006e6 ; + wire \blk00000003/sig000006e5 ; + wire \blk00000003/sig000006e4 ; + wire \blk00000003/sig000006e3 ; + wire \blk00000003/sig000006e2 ; + wire \blk00000003/sig000006e1 ; + wire \blk00000003/sig000006e0 ; + wire \blk00000003/sig000006df ; + wire \blk00000003/sig000006de ; + wire \blk00000003/sig000006dd ; + wire \blk00000003/sig000006dc ; + wire \blk00000003/sig000006db ; + wire \blk00000003/sig000006da ; + wire \blk00000003/sig000006d9 ; + wire \blk00000003/sig000006d8 ; + wire \blk00000003/sig000006d7 ; + wire \blk00000003/sig000006d6 ; + wire \blk00000003/sig000006d5 ; + wire \blk00000003/sig000006d4 ; + wire \blk00000003/sig000006d3 ; + wire \blk00000003/sig000006d2 ; + wire \blk00000003/sig000006d1 ; + wire \blk00000003/sig000006d0 ; + wire \blk00000003/sig000006cf ; + wire \blk00000003/sig000006ce ; + wire \blk00000003/sig000006cd ; + wire \blk00000003/sig000006cc ; + wire \blk00000003/sig000006cb ; + wire \blk00000003/sig000006ca ; + wire \blk00000003/sig000006c9 ; + wire \blk00000003/sig000006c8 ; + wire \blk00000003/sig000006c7 ; + wire \blk00000003/sig000006c6 ; + wire \blk00000003/sig000006c5 ; + wire \blk00000003/sig000006c4 ; + wire \blk00000003/sig000006c3 ; + wire \blk00000003/sig000006c2 ; + wire \blk00000003/sig000006c1 ; + wire \blk00000003/sig000006c0 ; + wire \blk00000003/sig000006bf ; + wire \blk00000003/sig000006be ; + wire \blk00000003/sig000006bd ; + wire \blk00000003/sig000006bc ; + wire \blk00000003/sig000006bb ; + wire \blk00000003/sig000006ba ; + wire \blk00000003/sig000006b9 ; + wire \blk00000003/sig000006b8 ; + wire \blk00000003/sig000006b7 ; + wire \blk00000003/sig000006b6 ; + wire \blk00000003/sig000006b5 ; + wire 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\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000690_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000688_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000686_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000678_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000676_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000668_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000666_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000664_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000662_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000660_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000012_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000679 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000782 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f6 ), + .Q(\blk00000003/sig00000767 ), + .Q15(\NLW_blk00000003/blk00000782_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000780 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f5 ), + .Q(\blk00000003/sig00000766 ), + .Q15(\NLW_blk00000003/blk00000780_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072f ), + .Q(\blk00000003/sig00000765 ), + .Q15(\NLW_blk00000003/blk0000077e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000733 ), + .Q(\blk00000003/sig00000764 ), + .Q15(\NLW_blk00000003/blk0000077c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000731 ), + .Q(\blk00000003/sig00000763 ), + .Q15(\NLW_blk00000003/blk0000077a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000779 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000778 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072d ), + .Q(\blk00000003/sig00000762 ), + .Q15(\NLW_blk00000003/blk00000778_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000777 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000776 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/sig00000761 ), + .Q15(\NLW_blk00000003/blk00000776_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000775 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000774 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000729 ), + .Q(\blk00000003/sig00000760 ), + .Q15(\NLW_blk00000003/blk00000774_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000772 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072b ), + .Q(\blk00000003/sig0000075f ), + .Q15(\NLW_blk00000003/blk00000772_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000770 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/sig0000075e ), + .Q15(\NLW_blk00000003/blk00000770_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071f ), + .Q(\blk00000003/sig0000075d ), + .Q15(\NLW_blk00000003/blk0000076e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/sig0000075c ), + .Q15(\NLW_blk00000003/blk0000076c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/sig0000075b ), + .Q15(\NLW_blk00000003/blk0000076a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000768 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/sig0000075a ), + .Q15(\NLW_blk00000003/blk00000768_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000766 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071b ), + .Q(\blk00000003/sig00000759 ), + .Q15(\NLW_blk00000003/blk00000766_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000764 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/sig00000758 ), + .Q15(\NLW_blk00000003/blk00000764_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000762 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071d ), + .Q(\blk00000003/sig00000757 ), + .Q15(\NLW_blk00000003/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000760 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/sig00000756 ), + .Q15(\NLW_blk00000003/blk00000760_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/sig00000755 ), + .Q15(\NLW_blk00000003/blk0000075e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/sig00000754 ), + .Q15(\NLW_blk00000003/blk0000075c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/sig00000753 ), + .Q15(\NLW_blk00000003/blk0000075a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/sig00000752 ), + .Q15(\NLW_blk00000003/blk00000758_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000756 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/sig00000751 ), + .Q15(\NLW_blk00000003/blk00000756_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000754 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/sig00000750 ), + .Q15(\NLW_blk00000003/blk00000754_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000752 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/sig0000074f ), + .Q15(\NLW_blk00000003/blk00000752_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000750 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/sig0000074e ), + .Q15(\NLW_blk00000003/blk00000750_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/sig0000074d ), + .Q15(\NLW_blk00000003/blk0000074e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/sig000001ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/sig0000074c ), + .Q15(\NLW_blk00000003/blk0000074c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/sig0000074b ), + .Q15(\NLW_blk00000003/blk0000074a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000748 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000748_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000746 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000746_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000744 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000744_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000742 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000742_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000740 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000740_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/sig00000745 ), + .Q15(\NLW_blk00000003/blk0000073e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/sig00000744 ), + .Q15(\NLW_blk00000003/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000743 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/sig00000743 ), + .Q15(\NLW_blk00000003/blk0000073a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000738_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000741 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000736 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000736_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000734 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000734_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000732_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000730 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000730_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/sig0000073d ), + .Q15(\NLW_blk00000003/blk0000072e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073c ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/sig0000073c ), + .Q15(\NLW_blk00000003/blk0000072c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073b ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/sig0000073b ), + .Q15(\NLW_blk00000003/blk0000072a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000729 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000728 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000728_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000726 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000726_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000724 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000724_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000722 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000722_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000720 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000720_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .Q(\blk00000003/sig000004f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000735 ), + .Q15(\NLW_blk00000003/blk0000071e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .Q(\blk00000003/sig0000067a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c3 ), + .Q(\blk00000003/sig00000734 ), + .Q15(\NLW_blk00000003/blk0000071c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000732 ), + .Q(\blk00000003/sig00000733 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000732 ), + .Q15(\NLW_blk00000003/blk0000071a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000719 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000730 ), + .Q(\blk00000003/sig00000731 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000718 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000730 ), + .Q15(\NLW_blk00000003/blk00000718_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000717 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072e ), + .Q(\blk00000003/sig0000072f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000716 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000072e ), + .Q15(\NLW_blk00000003/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000715 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072c ), + .Q(\blk00000003/sig0000072d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000714 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig0000072c ), + .Q15(\NLW_blk00000003/blk00000714_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000713 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072a ), + .Q(\blk00000003/sig0000072b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000712 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig0000072a ), + .Q15(\NLW_blk00000003/blk00000712_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000711 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000728 ), + .Q(\blk00000003/sig00000729 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000710 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000728 ), + .Q15(\NLW_blk00000003/blk00000710_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/sig00000727 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000726 ), + .Q15(\NLW_blk00000003/blk0000070e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070d ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/sig00000725 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000724 ), + .Q15(\NLW_blk00000003/blk0000070c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/sig00000723 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000722 ), + .Q15(\NLW_blk00000003/blk0000070a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000709 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/sig00000721 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000708 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000720 ), + .Q15(\NLW_blk00000003/blk00000708_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000707 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071e ), + .Q(\blk00000003/sig0000071f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000706 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig0000071e ), + .Q15(\NLW_blk00000003/blk00000706_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071c ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000704 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig0000071c ), + .Q15(\NLW_blk00000003/blk00000704_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000703 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000702 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000071a ), + .Q15(\NLW_blk00000003/blk00000702_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000701 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000700 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000718 ), + .Q15(\NLW_blk00000003/blk00000700_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ff ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000716 ), + .Q15(\NLW_blk00000003/blk000006fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000714 ), + .Q15(\NLW_blk00000003/blk000006fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000712 ), + .Q15(\NLW_blk00000003/blk000006fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000710 ), + .Q15(\NLW_blk00000003/blk000006f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig0000070e ), + .Q15(\NLW_blk00000003/blk000006f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig0000070c ), + .Q15(\NLW_blk00000003/blk000006f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/sig0000070b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig0000070a ), + .Q15(\NLW_blk00000003/blk000006f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/sig00000709 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000708 ), + .Q15(\NLW_blk00000003/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ef ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/sig00000707 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000706 ), + .Q15(\NLW_blk00000003/blk000006ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ed ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/sig00000705 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000704 ), + .Q15(\NLW_blk00000003/blk000006ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006eb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/sig00000703 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000702 ), + .Q15(\NLW_blk00000003/blk000006ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/sig00000701 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000700 ), + .Q15(\NLW_blk00000003/blk000006e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/sig000006ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006fe ), + .Q15(\NLW_blk00000003/blk000006e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/sig000006fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006fc ), + .Q15(\NLW_blk00000003/blk000006e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006fa ), + .Q15(\NLW_blk00000003/blk000006e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006f8 ), + .Q15(\NLW_blk00000003/blk000006e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006df ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006f6 ), + .Q15(\NLW_blk00000003/blk000006de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006f4 ), + .Q15(\NLW_blk00000003/blk000006dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006db ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006f2 ), + .Q15(\NLW_blk00000003/blk000006da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006f0 ), + .Q15(\NLW_blk00000003/blk000006d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006ee ), + .Q15(\NLW_blk00000003/blk000006d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006ec ), + .Q15(\NLW_blk00000003/blk000006d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/sig000006eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ea ), + .Q15(\NLW_blk00000003/blk000006d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/sig000006e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006e8 ), + .Q15(\NLW_blk00000003/blk000006d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/sig000006e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006e6 ), + .Q15(\NLW_blk00000003/blk000006ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/sig000006e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006e4 ), + .Q15(\NLW_blk00000003/blk000006cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/sig000006e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006e2 ), + .Q15(\NLW_blk00000003/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/sig000006e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006e0 ), + .Q15(\NLW_blk00000003/blk000006c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/sig000006df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006de ), + .Q15(\NLW_blk00000003/blk000006c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/sig000006dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006dc ), + .Q15(\NLW_blk00000003/blk000006c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006da ), + .Q15(\NLW_blk00000003/blk000006c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006d8 ), + .Q15(\NLW_blk00000003/blk000006c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006d6 ), + .Q15(\NLW_blk00000003/blk000006be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006d4 ), + .Q15(\NLW_blk00000003/blk000006bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/sig00000682 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/sig000006d3 ), + .Q15(\NLW_blk00000003/blk000006ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/sig0000056e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000006d2 ), + .Q15(\NLW_blk00000003/blk000006b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/sig00000681 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/sig000006d1 ), + .Q15(\NLW_blk00000003/blk000006b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/sig0000056c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000006d0 ), + .Q15(\NLW_blk00000003/blk000006b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/sig0000056b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000006cf ), + .Q15(\NLW_blk00000003/blk000006b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/sig0000056d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000006ce ), + .Q15(\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/sig00000569 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ae ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000006cd ), + .Q15(\NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/sig00000568 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ac ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000006cc ), + .Q15(\NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/sig0000056a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006aa ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000006cb ), + .Q15(\NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/sig00000567 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000006ca ), + .Q15(\NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/sig00000566 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a6 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000006c9 ), + .Q15(\NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/sig00000564 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000006c8 ), + .Q15(\NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/sig00000563 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000006c7 ), + .Q15(\NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/sig00000565 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000006c6 ), + .Q15(\NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/sig00000561 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000006c5 ), + .Q15(\NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/sig00000560 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000006c4 ), + .Q15(\NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/sig00000562 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000006c3 ), + .Q15(\NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/sig0000055e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000698 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000006c2 ), + .Q15(\NLW_blk00000003/blk00000698_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/sig0000055d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000696 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000006c1 ), + .Q15(\NLW_blk00000003/blk00000696_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/sig0000055f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000694 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000006c0 ), + .Q15(\NLW_blk00000003/blk00000694_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/sig0000055c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000692 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000006bf ), + .Q15(\NLW_blk00000003/blk00000692_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000691 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/sig0000055b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000690 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000006be ), + .Q15(\NLW_blk00000003/blk00000690_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/sig00000559 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000006bd ), + .Q15(\NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/sig00000558 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000006bc ), + .Q15(\NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/sig0000055a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000006bb ), + .Q15(\NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/sig0000059e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000688 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000006ba ), + .Q15(\NLW_blk00000003/blk00000688_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/sig0000059d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000686 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000006b9 ), + .Q15(\NLW_blk00000003/blk00000686_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000685 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/sig00000557 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000684 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000006b8 ), + .Q15(\NLW_blk00000003/blk00000684_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000683 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/sig0000059b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000682 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006b7 ), + .Q15(\NLW_blk00000003/blk00000682_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000681 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/sig0000059a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000680 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006b6 ), + .Q15(\NLW_blk00000003/blk00000680_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/sig0000059c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006b5 ), + .Q15(\NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/sig00000599 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006b4 ), + .Q15(\NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/sig00000598 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006b3 ), + .Q15(\NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/sig00000596 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000678 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006b2 ), + .Q15(\NLW_blk00000003/blk00000678_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/sig00000595 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000676 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006b1 ), + .Q15(\NLW_blk00000003/blk00000676_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/sig00000597 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006b0 ), + .Q15(\NLW_blk00000003/blk00000674_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/sig00000593 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000672 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006af ), + .Q15(\NLW_blk00000003/blk00000672_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/sig00000592 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000670 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ae ), + .Q15(\NLW_blk00000003/blk00000670_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/sig00000594 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006ad ), + .Q15(\NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/sig00000590 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006ac ), + .Q15(\NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/sig0000058f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006ab ), + .Q15(\NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/sig00000591 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000668 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006aa ), + .Q15(\NLW_blk00000003/blk00000668_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/sig0000058e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000666 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006a9 ), + .Q15(\NLW_blk00000003/blk00000666_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/sig0000058d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000664 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006a8 ), + .Q15(\NLW_blk00000003/blk00000664_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/sig0000058b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000662 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006a7 ), + .Q15(\NLW_blk00000003/blk00000662_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/sig0000058a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000660 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006a6 ), + .Q15(\NLW_blk00000003/blk00000660_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/sig0000058c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006a5 ), + .Q15(\NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/sig00000588 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006a4 ), + .Q15(\NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/sig00000587 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006a3 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/sig00000589 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006a2 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/sig000002c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig000006a1 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/sig00000680 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d0 ), + .Q(\blk00000003/sig000006a0 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/sig000002c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d4 ), + .Q(\blk00000003/sig0000069f ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/sig000005c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000069e ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/sig000005c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig0000069d ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/sig000005c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000069c ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/sig000005c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig0000069b ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/sig000005c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000069a ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/sig000005c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000699 ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/sig000005c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000698 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/sig000005c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000697 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/sig000005bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000696 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/sig000005be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000695 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/sig000005c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000694 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/sig000005bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000693 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/sig000005bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000692 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/sig000005ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000691 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/sig000005b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000690 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/sig000005bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig0000068f ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/sig000005b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000068e ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/sig000005b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000068d ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig000004f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig0000068c ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig0000068b ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068a ), + .Q(\blk00000003/sig000001df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig0000068a ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000627 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027e ) + ); + INV \blk00000003/blk00000626 ( + .I(\blk00000003/sig00000287 ), + .O(\blk00000003/sig00000277 ) + ); + INV \blk00000003/blk00000625 ( + .I(\blk00000003/sig000001ce ), + .O(\blk00000003/sig0000028c ) + ); + INV \blk00000003/blk00000624 ( + .I(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000027d ) + ); + INV \blk00000003/blk00000623 ( + .I(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000678 ) + ); + INV \blk00000003/blk00000622 ( + .I(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028f ) + ); + INV \blk00000003/blk00000621 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000278 ) + ); + INV \blk00000003/blk00000620 ( + .I(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000243 ) + ); + INV \blk00000003/blk0000061f ( + .I(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000ba ) + ); + INV \blk00000003/blk0000061e ( + .I(\blk00000003/sig000000ad ), + .O(\blk00000003/sig000001c7 ) + ); + INV \blk00000003/blk0000061d ( + .I(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig0000067c ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig00000234 ), + .I2(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig00000248 ), + .I1(\blk00000003/sig0000023c ), + .I2(\blk00000003/sig0000024b ), + .I3(coef_ld), + .I4(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000023f ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000619 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000246 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024b ), + .I4(coef_ld), + .O(\blk00000003/sig00000245 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig00000287 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000219 ), + .O(\blk00000003/sig00000689 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000028e ), + .I1(ce), + .I2(\blk00000003/sig0000023a ), + .I3(\blk00000003/sig0000027f ), + .O(\blk00000003/sig00000688 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig00000686 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000614 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000067f ), + .O(\blk00000003/sig00000685 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000613 ( + .I0(ce), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig0000067d ), + .O(\blk00000003/sig00000684 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig00000291 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000687 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000611 ( + .C(clk), + .D(\blk00000003/sig00000689 ), + .Q(\blk00000003/sig00000287 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000610 ( + .C(clk), + .D(\blk00000003/sig00000688 ), + .Q(\blk00000003/sig0000028e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060e ( + .C(clk), + .D(\blk00000003/sig00000686 ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig00000602 ), + .O(\blk00000003/sig000005fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig00000601 ), + .O(\blk00000003/sig000005fa ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig00000600 ), + .O(\blk00000003/sig000005f7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig000002ba ), + .O(\blk00000003/sig000002bb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000067e ), + .O(\blk00000003/sig00000296 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig00000264 ), + .O(\blk00000003/sig00000265 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000254 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000024f ), + .O(\blk00000003/sig0000024d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig0000022a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(sclr), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066f ), + .R(sclr), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066c ), + .R(sclr), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000669 ), + .R(sclr), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000666 ), + .R(sclr), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f2 ), + .R(sclr), + .Q(\blk00000003/sig00000603 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fe ), + .S(sclr), + .Q(\blk00000003/sig00000602 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fb ), + .R(sclr), + .Q(\blk00000003/sig00000601 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f8 ), + .R(sclr), + .Q(\blk00000003/sig00000600 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f5 ), + .S(sclr), + .Q(\blk00000003/sig000005ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c0 ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bd ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDR \blk00000003/blk000005ef ( + .C(clk), + .D(\blk00000003/sig00000685 ), + .R(ce), + .Q(\blk00000003/sig0000067f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .S(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR \blk00000003/blk000005ea ( + .C(clk), + .D(\blk00000003/sig00000684 ), + .R(ce), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000268 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000267 ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025c ), + .R(coef_ld), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(coef_ld), + .Q(\blk00000003/sig00000261 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000258 ), + .R(sclr), + .Q(\blk00000003/sig00000259 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000255 ), + .R(sclr), + .Q(\blk00000003/sig00000256 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000251 ), + .R(coef_ld), + .Q(\blk00000003/sig00000252 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .R(coef_ld), + .Q(\blk00000003/sig0000024f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000af ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000665 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig00000674 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000668 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig00000675 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig00000676 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig00000677 ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig000001dd ), + .O(\blk00000003/sig00000671 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig000001dd ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000663 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000661 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000662 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000660 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000065e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000065f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000065d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000065b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000065c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000065a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000658 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000659 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000657 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000655 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000656 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000654 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000652 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000653 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000651 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000064f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000650 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000064e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000064c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000064d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000064b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000649 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000064a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000648 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000646 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000647 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000645 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000643 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000644 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000642 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000640 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000641 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000063f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000063d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000063e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000063c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000063a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000063b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000639 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000637 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000638 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ae ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000636 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000635 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000633 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ab ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000634 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005aa ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000632 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000630 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000631 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000062f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000062d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000062e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000062c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000062a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000062b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000629 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000627 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000628 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000626 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000624 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000625 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000623 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000621 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000622 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000620 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000597 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000061e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000596 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000061f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000595 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000061d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000061b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000061c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000061a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000618 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000619 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000617 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000615 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000616 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000614 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000612 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000613 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000589 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000611 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000060f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000610 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000060e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000060c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000584 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000060d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000583 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000060b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000582 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000609 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000060a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000608 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000606 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000607 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000605 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000057c ( + .I0(\blk00000003/sig00000603 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057b ( + .I0(ce), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000683 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057a ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/sig000005ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000579 ( + .I0(ce), + .I1(\blk00000003/sig00000682 ), + .O(\blk00000003/sig000005ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000578 ( + .I0(ce), + .I1(\blk00000003/sig00000681 ), + .O(\blk00000003/sig000005ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000577 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002b5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000576 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig000002b2 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000575 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002af ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000574 ( + .I0(\blk00000003/sig000002b0 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002ad ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000573 ( + .I0(\blk00000003/sig00000680 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002aa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000572 ( + .I0(sclr), + .I1(\blk00000003/sig0000067f ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000571 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000570 ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000029f ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000056f ( + .I0(\blk00000003/sig000001e6 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig00000298 ), + .O(\blk00000003/sig0000029d ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000056e ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000056d ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000293 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk0000056c ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig00000295 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056b ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056a ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023a ), + .O(\blk00000003/sig0000028a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000569 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000288 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000568 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000248 ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000283 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000567 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000285 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000566 ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000565 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000564 ( + .I0(\blk00000003/sig00000238 ), + .I1(\blk00000003/sig00000242 ), + .I2(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000275 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000563 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000562 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000248 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000561 ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig0000067d ), + .O(\blk00000003/sig0000026c ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000560 ( + .I0(coef_we), + .I1(\blk00000003/sig00000222 ), + .I2(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000260 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000055f ( + .I0(\blk00000003/sig00000261 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .O(\blk00000003/sig0000025e ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk0000055e ( + .I0(coef_we), + .I1(\blk00000003/sig00000262 ), + .I2(\blk00000003/sig00000222 ), + .I3(\blk00000003/sig00000227 ), + .O(\blk00000003/sig0000025b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055d ( + .I0(\blk00000003/sig00000259 ), + .I1(\blk00000003/sig000001c3 ), + .O(\blk00000003/sig00000257 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055c ( + .I0(\blk00000003/sig00000252 ), + .I1(coef_we), + .O(\blk00000003/sig00000250 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000055b ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .O(\blk00000003/sig00000241 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000055a ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000559 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000249 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000558 ( + .I0(\blk00000003/sig00000261 ), + .I1(\blk00000003/sig00000262 ), + .O(\blk00000003/sig0000022d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000557 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000229 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000556 ( + .I0(\blk00000003/sig00000262 ), + .I1(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000555 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000220 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000554 ( + .I0(coef_we), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000021d ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000553 ( + .I0(\blk00000003/sig00000236 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .I4(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000552 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000233 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000551 ( + .I0(nd), + .I1(\blk00000003/sig00000291 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000550 ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000001dd ), + .O(\blk00000003/sig000001e3 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000054f ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig0000067c ), + .O(\blk00000003/sig000000c0 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000054e ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000001de ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000054d ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001ca ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000054c ( + .I0(\blk00000003/sig00000256 ), + .I1(\blk00000003/sig00000259 ), + .O(\blk00000003/sig000001c4 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk0000054b ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig00000674 ), + .I2(\blk00000003/sig00000675 ), + .I3(\blk00000003/sig00000676 ), + .I4(\blk00000003/sig00000677 ), + .O(\blk00000003/sig000000c2 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000054a ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig000001c3 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000549 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001db ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000548 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b4 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000547 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b3 ), + .O(\blk00000003/sig000000b2 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000546 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000545 ( + .I0(\blk00000003/sig000000ad ), + .I1(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000000ae ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000544 ( + .I0(\blk00000003/sig000001c3 ), + .I1(\blk00000003/sig000001e4 ), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .I4(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000543 ( + .I0(\blk00000003/sig000001d4 ), + .I1(\blk00000003/sig0000067b ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001cf ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000542 ( + .I0(\blk00000003/sig000001e4 ), + .I1(\blk00000003/sig000001d4 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000541 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk00000540 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig0000067a ), + .I3(\blk00000003/sig000000b1 ), + .O(\blk00000003/sig000000b0 ) + ); + MUXCY \blk00000003/blk0000053f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000678 ), + .O(\blk00000003/sig00000670 ) + ); + MUXCY_L \blk00000003/blk0000053e ( + .CI(\blk00000003/sig00000670 ), + .DI(\blk00000003/sig00000677 ), + .S(\blk00000003/sig00000671 ), + .LO(\blk00000003/sig0000066d ) + ); + MUXCY_L \blk00000003/blk0000053d ( + .CI(\blk00000003/sig0000066d ), + .DI(\blk00000003/sig00000676 ), + .S(\blk00000003/sig0000066e ), + .LO(\blk00000003/sig0000066a ) + ); + MUXCY_L \blk00000003/blk0000053c ( + .CI(\blk00000003/sig0000066a ), + .DI(\blk00000003/sig00000675 ), + .S(\blk00000003/sig0000066b ), + .LO(\blk00000003/sig00000667 ) + ); + MUXCY_L \blk00000003/blk0000053b ( + .CI(\blk00000003/sig00000667 ), + .DI(\blk00000003/sig00000674 ), + .S(\blk00000003/sig00000668 ), + .LO(\blk00000003/sig00000664 ) + ); + MUXCY_D \blk00000003/blk0000053a ( + .CI(\blk00000003/sig00000664 ), + .DI(\blk00000003/sig00000673 ), + .S(\blk00000003/sig00000665 ), + .O(\NLW_blk00000003/blk0000053a_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000053a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000539 ( + .CI(\blk00000003/sig00000670 ), + .LI(\blk00000003/sig00000671 ), + .O(\blk00000003/sig00000672 ) + ); + XORCY \blk00000003/blk00000538 ( + .CI(\blk00000003/sig0000066d ), + .LI(\blk00000003/sig0000066e ), + .O(\blk00000003/sig0000066f ) + ); + XORCY \blk00000003/blk00000537 ( + .CI(\blk00000003/sig0000066a ), + .LI(\blk00000003/sig0000066b ), + .O(\blk00000003/sig0000066c ) + ); + XORCY \blk00000003/blk00000536 ( + .CI(\blk00000003/sig00000667 ), + .LI(\blk00000003/sig00000668 ), + .O(\blk00000003/sig00000669 ) + ); + XORCY \blk00000003/blk00000535 ( + .CI(\blk00000003/sig00000664 ), + .LI(\blk00000003/sig00000665 ), + .O(\blk00000003/sig00000666 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000620 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000619 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000618 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000617 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000616 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000615 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000614 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000613 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000612 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000611 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000610 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000609 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000608 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000607 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000606 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000605 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig000001dd ) + ); + MUXCY_L \blk00000003/blk000004d4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000603 ), + .S(\blk00000003/sig000005f1 ), + .LO(\blk00000003/sig000005fc ) + ); + MUXCY_L \blk00000003/blk000004d3 ( + .CI(\blk00000003/sig000005fc ), + .DI(\blk00000003/sig00000602 ), + .S(\blk00000003/sig000005fd ), + .LO(\blk00000003/sig000005f9 ) + ); + MUXCY_L \blk00000003/blk000004d2 ( + .CI(\blk00000003/sig000005f9 ), + .DI(\blk00000003/sig00000601 ), + .S(\blk00000003/sig000005fa ), + .LO(\blk00000003/sig000005f6 ) + ); + MUXCY_L \blk00000003/blk000004d1 ( + .CI(\blk00000003/sig000005f6 ), + .DI(\blk00000003/sig00000600 ), + .S(\blk00000003/sig000005f7 ), + .LO(\blk00000003/sig000005f3 ) + ); + MUXCY_D \blk00000003/blk000004d0 ( + .CI(\blk00000003/sig000005f3 ), + .DI(\blk00000003/sig000005ff ), + .S(\blk00000003/sig000005f4 ), + .O(\NLW_blk00000003/blk000004d0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000004d0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000004cf ( + .CI(\blk00000003/sig000005fc ), + .LI(\blk00000003/sig000005fd ), + .O(\blk00000003/sig000005fe ) + ); + XORCY \blk00000003/blk000004ce ( + .CI(\blk00000003/sig000005f9 ), + .LI(\blk00000003/sig000005fa ), + .O(\blk00000003/sig000005fb ) + ); + XORCY \blk00000003/blk000004cd ( + .CI(\blk00000003/sig000005f6 ), + .LI(\blk00000003/sig000005f7 ), + .O(\blk00000003/sig000005f8 ) + ); + XORCY \blk00000003/blk000004cc ( + .CI(\blk00000003/sig000005f3 ), + .LI(\blk00000003/sig000005f4 ), + .O(\blk00000003/sig000005f5 ) + ); + XORCY \blk00000003/blk000004cb ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000005f1 ), + .O(\blk00000003/sig000005f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig0000050e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig0000050d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig0000050c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig0000050b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000050a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig00000509 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig00000508 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig00000507 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig00000506 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig00000505 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000504 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000503 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000502 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig000004fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000490 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig000004fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig000004fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig000004f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig000004f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig000004f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000450 ), + .R(sclr), + .Q(\blk00000003/sig00000526 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044f ), + .R(sclr), + .Q(\blk00000003/sig00000525 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000489 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044e ), + .R(sclr), + .Q(\blk00000003/sig00000524 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000488 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044d ), + .R(sclr), + .Q(\blk00000003/sig00000523 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000487 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044c ), + .R(sclr), + .Q(\blk00000003/sig00000522 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000486 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044b ), + .R(sclr), + .Q(\blk00000003/sig00000521 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044a ), + .R(sclr), + .Q(\blk00000003/sig00000520 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000484 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000449 ), + .R(sclr), + .Q(\blk00000003/sig0000051f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000448 ), + .R(sclr), + .Q(\blk00000003/sig0000051e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000482 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000447 ), + .R(sclr), + .Q(\blk00000003/sig0000051d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000481 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000446 ), + .R(sclr), + .Q(\blk00000003/sig0000051c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000480 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000445 ), + .R(sclr), + .Q(\blk00000003/sig0000051b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000444 ), + .R(sclr), + .Q(\blk00000003/sig0000051a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000443 ), + .R(sclr), + .Q(\blk00000003/sig00000519 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000442 ), + .R(sclr), + .Q(\blk00000003/sig00000518 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000441 ), + .R(sclr), + .Q(\blk00000003/sig00000517 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000440 ), + .R(sclr), + .Q(\blk00000003/sig00000516 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043f ), + .R(sclr), + .Q(\blk00000003/sig00000515 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000479 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043e ), + .R(sclr), + .Q(\blk00000003/sig00000514 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000478 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043d ), + .R(sclr), + .Q(\blk00000003/sig00000513 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000477 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043c ), + .R(sclr), + .Q(\blk00000003/sig00000512 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000476 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043b ), + .R(sclr), + .Q(\blk00000003/sig00000511 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000475 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043a ), + .R(sclr), + .Q(\blk00000003/sig00000510 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000474 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000439 ), + .R(sclr), + .Q(\blk00000003/sig0000050f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004aa ), + .R(sclr), + .Q(\blk00000003/sig00000586 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a9 ), + .R(sclr), + .Q(\blk00000003/sig00000585 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a8 ), + .R(sclr), + .Q(\blk00000003/sig00000584 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000449 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a7 ), + .R(sclr), + .Q(\blk00000003/sig00000583 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000448 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a6 ), + .R(sclr), + .Q(\blk00000003/sig00000582 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000447 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a5 ), + .R(sclr), + .Q(\blk00000003/sig00000581 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000446 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a4 ), + .R(sclr), + .Q(\blk00000003/sig00000580 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a3 ), + .R(sclr), + .Q(\blk00000003/sig0000057f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000444 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a2 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000443 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a1 ), + .R(sclr), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000442 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a0 ), + .R(sclr), + .Q(\blk00000003/sig0000057c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000441 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049f ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000440 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049e ), + .R(sclr), + .Q(\blk00000003/sig0000057a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049d ), + .R(sclr), + .Q(\blk00000003/sig00000579 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049c ), + .R(sclr), + .Q(\blk00000003/sig00000578 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049b ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049a ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000499 ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000498 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000439 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000497 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000438 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000496 ), + .R(sclr), + .Q(\blk00000003/sig00000572 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000437 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000495 ), + .R(sclr), + .Q(\blk00000003/sig00000571 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000436 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000494 ), + .R(sclr), + .Q(\blk00000003/sig00000570 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000435 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000493 ), + .R(sclr), + .Q(\blk00000003/sig0000056f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000434 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig0000053e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000433 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig0000053d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig0000053c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000431 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig0000053b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000430 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000053a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig00000539 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig00000538 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig00000537 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042c ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig00000536 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042b ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig00000535 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042a ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000534 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000429 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000533 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000428 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000532 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000427 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000531 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000426 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000530 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000425 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig0000052f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000424 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig0000052e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000423 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig0000052d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000422 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig0000052c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000421 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig0000052b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000420 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig0000052a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000529 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000528 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000527 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004da ), + .R(sclr), + .Q(\blk00000003/sig000005b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d9 ), + .R(sclr), + .Q(\blk00000003/sig000005b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d8 ), + .R(sclr), + .Q(\blk00000003/sig000005b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000419 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d7 ), + .R(sclr), + .Q(\blk00000003/sig000005b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000418 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d6 ), + .R(sclr), + .Q(\blk00000003/sig000005b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000417 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d5 ), + .R(sclr), + .Q(\blk00000003/sig000005b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000416 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig000005b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000415 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig000005af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000414 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig000005ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000413 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig000005ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000412 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig000005ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000411 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig000005ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000410 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig000005aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig000005a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cc ), + .R(sclr), + .Q(\blk00000003/sig000005a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cb ), + .R(sclr), + .Q(\blk00000003/sig000005a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ca ), + .R(sclr), + .Q(\blk00000003/sig000005a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c9 ), + .R(sclr), + .Q(\blk00000003/sig000005a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c8 ), + .R(sclr), + .Q(\blk00000003/sig000005a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000409 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c7 ), + .R(sclr), + .Q(\blk00000003/sig000005a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000408 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c6 ), + .R(sclr), + .Q(\blk00000003/sig000005a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000407 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c5 ), + .R(sclr), + .Q(\blk00000003/sig000005a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000406 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c4 ), + .R(sclr), + .Q(\blk00000003/sig000005a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000405 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c3 ), + .R(sclr), + .Q(\blk00000003/sig0000059f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000404 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000468 ), + .R(sclr), + .Q(\blk00000003/sig00000556 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000467 ), + .R(sclr), + .Q(\blk00000003/sig00000555 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000466 ), + .R(sclr), + .Q(\blk00000003/sig00000554 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000465 ), + .R(sclr), + .Q(\blk00000003/sig00000553 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000464 ), + .R(sclr), + .Q(\blk00000003/sig00000552 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000463 ), + .R(sclr), + .Q(\blk00000003/sig00000551 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000462 ), + .R(sclr), + .Q(\blk00000003/sig00000550 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000461 ), + .R(sclr), + .Q(\blk00000003/sig0000054f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000460 ), + .R(sclr), + .Q(\blk00000003/sig0000054e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045f ), + .R(sclr), + .Q(\blk00000003/sig0000054d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045e ), + .R(sclr), + .Q(\blk00000003/sig0000054c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045d ), + .R(sclr), + .Q(\blk00000003/sig0000054b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045c ), + .R(sclr), + .Q(\blk00000003/sig0000054a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045b ), + .R(sclr), + .Q(\blk00000003/sig00000549 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045a ), + .R(sclr), + .Q(\blk00000003/sig00000548 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000459 ), + .R(sclr), + .Q(\blk00000003/sig00000547 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000458 ), + .R(sclr), + .Q(\blk00000003/sig00000546 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000457 ), + .R(sclr), + .Q(\blk00000003/sig00000545 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000456 ), + .R(sclr), + .Q(\blk00000003/sig00000544 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000455 ), + .R(sclr), + .Q(\blk00000003/sig00000543 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000454 ), + .R(sclr), + .Q(\blk00000003/sig00000542 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000453 ), + .R(sclr), + .Q(\blk00000003/sig00000541 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000452 ), + .R(sclr), + .Q(\blk00000003/sig00000540 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000451 ), + .R(sclr), + .Q(\blk00000003/sig0000053f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .R(sclr), + .Q(\blk00000003/sig000004ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000004ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ba ), + .R(sclr), + .Q(\blk00000003/sig000004eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002be ), + .R(sclr), + .Q(\blk00000003/sig000004e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig000004e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f5 ), + .R(sclr), + .Q(\blk00000003/sig000004e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000004f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000004f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .R(sclr), + .Q(\blk00000003/sig000004f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f1 ), + .R(sclr), + .Q(\blk00000003/sig000004f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ef ), + .R(sclr), + .Q(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig000004ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig000004ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig000004ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig000004e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e5 ), + .R(sclr), + .Q(\blk00000003/sig000004e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e3 ), + .R(sclr), + .Q(\blk00000003/sig000004e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e1 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000232 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dc ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004db ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000268 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000264 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004db ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fc ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004ab , \blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , +\blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , +\blk00000003/sig000004b4 , \blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , +\blk00000003/sig000004b9 , \blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , +\blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , +\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , +\blk00000003/sig000004d1 , \blk00000003/sig000004d2 , \blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , +\blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da }), + .PCOUT({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000047b , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , \blk00000003/sig0000047e , +\blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , +\blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , +\blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c , \blk00000003/sig0000048d , +\blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 }), + .P({\NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , +\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa }), + .PCOUT({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fa ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000439 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 }), + .P({\NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , +\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , +\blk00000003/sig0000045f , \blk00000003/sig00000460 , \blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , +\blk00000003/sig00000464 , \blk00000003/sig00000465 , \blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 }), + .PCOUT({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003d9 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , +\blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000337 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , +\blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , +\blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , +\blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , +\blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , +\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 }), + .PCOUT({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002d7 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , \blk00000003/sig000002da , +\blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , \blk00000003/sig000002df , +\blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , +\blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , +\blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee }), + .P({\NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , +\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 }), + .PCOUT({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig000002b9 ) + ); + XORCY \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002bc ), + .LI(\blk00000003/sig000002bf ), + .O(\blk00000003/sig000002c0 ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bc ), + .DI(\blk00000003/sig000002be ), + .S(\blk00000003/sig000002bf ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig000002b9 ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bd ) + ); + MUXCY_L \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002b9 ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002bc ) + ); + MUXCY_L \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig000002b2 ), + .LO(\blk00000003/sig000002b4 ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002b4 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b5 ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000002b4 ), + .LI(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002b6 ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002b3 ) + ); + MUXCY_L \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002a9 ), + .DI(\blk00000003/sig000002b1 ), + .S(\blk00000003/sig000002aa ), + .LO(\blk00000003/sig000002ac ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002ac ), + .DI(\blk00000003/sig000002b0 ), + .S(\blk00000003/sig000002ad ), + .O(\NLW_blk00000003/blk000000ea_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000002af ), + .O(\blk00000003/sig000002a9 ) + ); + XORCY \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002ac ), + .LI(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002ae ) + ); + XORCY \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002a9 ), + .LI(\blk00000003/sig000002aa ), + .O(\blk00000003/sig000002ab ) + ); + FDE \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig000002a8 ) + ); + MUXCY_L \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a6 ), + .S(\blk00000003/sig000002a0 ), + .LO(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002a2 ), + .DI(\blk00000003/sig000002a5 ), + .S(\blk00000003/sig000002a3 ), + .O(\NLW_blk00000003/blk000000e4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig000002a2 ), + .LI(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + XORCY \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + MUXCY_L \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000001e7 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig000001e6 ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000e0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .R(sclr), + .Q(\blk00000003/sig00000298 ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000db_O_UNCONNECTED ), + .LO(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000293 ), + .O(\blk00000003/sig00000294 ), + .LO(\blk00000003/sig00000290 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000290 ), + .R(sclr), + .Q(\blk00000003/sig00000291 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000280 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig0000021c ), + .DI(\blk00000003/sig0000028e ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028b ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028b ), + .DI(\blk00000003/sig0000028c ), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000289 ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000289 ), + .DI(\blk00000003/sig0000027f ), + .S(\blk00000003/sig0000028a ), + .O(\blk00000003/sig00000286 ), + .LO(\NLW_blk00000003/blk000000d3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig00000286 ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000284 ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig00000284 ), + .DI(\blk00000003/sig00000244 ), + .S(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000219 ), + .S(\blk00000003/sig00000283 ), + .O(\NLW_blk00000003/blk000000d0_O_UNCONNECTED ), + .LO(\blk00000003/sig00000280 ) + ); + XORCY \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000280 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000281 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026f ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000027f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig000001cd ), + .DI(\blk00000003/sig0000027d ), + .S(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig000001cd ), + .S(\blk00000003/sig0000027a ), + .O(\blk00000003/sig00000276 ), + .LO(\NLW_blk00000003/blk000000ca_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000276 ), + .DI(\blk00000003/sig00000277 ), + .S(\blk00000003/sig00000278 ), + .O(\blk00000003/sig00000274 ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000274 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000273 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\blk00000003/sig0000026e ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000239 ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig0000026e ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000026f ) + ); + FDE \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026c ), + .Q(\blk00000003/sig0000026d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000026b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000263 ) + ); + XORCY \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000266 ), + .LI(\blk00000003/sig00000269 ), + .O(\blk00000003/sig0000026a ) + ); + MUXCY_D \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000266 ), + .DI(\blk00000003/sig00000268 ), + .S(\blk00000003/sig00000269 ), + .O(\NLW_blk00000003/blk000000c0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000263 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000267 ) + ); + MUXCY_L \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000263 ), + .DI(\blk00000003/sig00000264 ), + .S(\blk00000003/sig00000265 ), + .LO(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bd ( + .CI(\blk00000003/sig0000025a ), + .DI(\blk00000003/sig00000262 ), + .S(\blk00000003/sig0000025b ), + .LO(\blk00000003/sig0000025d ) + ); + MUXCY_D \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025d ), + .DI(\blk00000003/sig00000261 ), + .S(\blk00000003/sig0000025e ), + .O(\NLW_blk00000003/blk000000bc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bc_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025a ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig0000025d ), + .LI(\blk00000003/sig0000025e ), + .O(\blk00000003/sig0000025f ) + ); + XORCY \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025a ), + .LI(\blk00000003/sig0000025b ), + .O(\blk00000003/sig0000025c ) + ); + MUXCY_L \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000259 ), + .S(\blk00000003/sig00000257 ), + .LO(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000257 ), + .O(\blk00000003/sig00000258 ) + ); + MUXCY_D \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000253 ), + .DI(\blk00000003/sig00000256 ), + .S(\blk00000003/sig00000254 ), + .O(\NLW_blk00000003/blk000000b6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000253 ), + .LI(\blk00000003/sig00000254 ), + .O(\blk00000003/sig00000255 ) + ); + MUXCY_L \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000252 ), + .S(\blk00000003/sig00000250 ), + .LO(\blk00000003/sig0000024c ) + ); + XORCY \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000251 ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024c ), + .DI(\blk00000003/sig0000024f ), + .S(\blk00000003/sig0000024d ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig0000024c ), + .LI(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000024e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig00000248 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig0000022f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021b ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022e ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022c ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000228 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000224 ), + .R(coef_ld), + .Q(\blk00000003/sig00000222 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000237 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .Q(\blk00000003/sig00000232 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022f ), + .Q(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022d ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022e ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig0000022c ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig00000228 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000225 ), + .O(\blk00000003/sig00000221 ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig00000221 ), + .DI(\blk00000003/sig00000222 ), + .S(\blk00000003/sig00000223 ), + .O(\NLW_blk00000003/blk00000093_O_UNCONNECTED ), + .LO(\blk00000003/sig00000224 ) + ); + XORCY \blk00000003/blk00000092 ( + .CI(\blk00000003/sig0000021a ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000218 ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000220 ), + .O(\NLW_blk00000003/blk00000091_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig0000021b ), + .DI(\blk00000003/sig0000021c ), + .S(\blk00000003/sig0000021d ), + .O(\blk00000003/sig0000021e ), + .LO(\NLW_blk00000003/blk00000090_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000218 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000219 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000029 ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .R(sclr), + .Q(\blk00000003/sig000000b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(\blk00000003/sig000001de ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .R(\blk00000003/sig000001de ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .S(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDRE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cb ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c9 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001a_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .Q(\blk00000003/sig000001ce ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c1 ), + .R(sclr), + .Q(\blk00000003/sig000000bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000016_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bd ), + .S(sclr), + .Q(\blk00000003/sig000001cc ) + ); + MUXCY \blk00000003/blk00000014 ( + .CI(\blk00000003/sig000001c8 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000001cb ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000001c6 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001c8 ), + .LO(\blk00000003/sig000001c9 ) + ); + MUXCY_D \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c3 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c4 ), + .O(\NLW_blk00000003/blk00000012_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c5 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000011 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000011_P<47>_UNCONNECTED , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , +\blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , +\blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , +\blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , +\blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , +\blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , +\blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , +\blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , +\blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , +\blk00000003/sig000001a7 , \blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa }), + .A({\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , +\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , +\blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , +\blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , +\blk00000003/sig000001b9 , \blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , +\blk00000003/sig000001be , \blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 }), + .PCOUT({\NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000010 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000010_P<47>_UNCONNECTED , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , +\blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , +\blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , +\blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c2 ), + .O(\blk00000003/sig000000be ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig000000be ), + .DI(\blk00000003/sig000000bf ), + .S(\blk00000003/sig000000c0 ), + .O(\blk00000003/sig000000b6 ), + .LO(\blk00000003/sig000000c1 ) + ); + XORCY \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000bc ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000000bd ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000b9 ), + .DI(\blk00000003/sig000000ba ), + .S(\blk00000003/sig000000bb ), + .O(\NLW_blk00000003/blk0000000c_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000b6 ), + .DI(\blk00000003/sig000000b7 ), + .S(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b9 ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000a ( + .C(clk), + .D(\blk00000003/sig000000b4 ), + .Q(\blk00000003/sig000000b5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .D(\blk00000003/sig000000b2 ), + .Q(\blk00000003/sig000000b3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b0 ), + .Q(\blk00000003/sig000000b1 ) + ); + XORCY \blk00000003/blk00000007 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000af ) + ); + MUXCY_D \blk00000003/blk00000006 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ad ), + .S(\blk00000003/sig000000ae ), + .O(\NLW_blk00000003/blk00000006_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000006_LO_UNCONNECTED ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002b/blk0000008d ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002b/sig00000800 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000089 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000088 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000087 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000086 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000085 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000084 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000083 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000082 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000081 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000080 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000079 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000078 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000077 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000076 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000075 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000074 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000073 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000072 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000071 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000070 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000069 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000068 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000067 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000066 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000065 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000064 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000063 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000062 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000061 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000060 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ff ), + .Q(\blk00000003/sig000001e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fe ), + .Q(\blk00000003/sig000001e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fd ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fc ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fb ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fa ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f9 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f8 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f7 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f6 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f5 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f4 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f3 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f2 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f1 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f0 ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ef ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ee ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ed ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ec ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007eb ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ea ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e9 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e8 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e7 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e6 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e5 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e4 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e3 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e2 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e1 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e0 ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007df ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007de ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dd ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dc ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007db ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007da ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d9 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d8 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d7 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d6 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d5 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d4 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d3 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d2 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d1 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d0 ), + .Q(\blk00000003/sig00000217 ) + ); + GND \blk00000003/blk0000002b/blk0000002c ( + .G(\blk00000003/blk0000002b/sig000007cf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000117/blk00000149 ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk00000117/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000148 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk00000117/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000147 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk00000117/sig0000084c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000146 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk00000117/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000145 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk00000117/sig0000084a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000144 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk00000117/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000143 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk00000117/sig0000084b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000142 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000117/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000141 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000117/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000140 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000117/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000117/sig00000844 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000117/sig00000843 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000117/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000117/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000117/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000117/sig00000842 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000139 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000117/sig0000083e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000138 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000117/sig0000083d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000137 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000117/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000136 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000117/sig0000083b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000135 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000117/sig0000083a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000134 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000117/sig0000083c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000133 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000117/sig00000838 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000132 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000117/sig00000837 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000131 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000117/sig00000839 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084e ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084d ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084c ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084b ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084a ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000849 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000848 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000847 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000846 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000845 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000844 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000843 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000842 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000841 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000840 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083f ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083e ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083d ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083c ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083b ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083a ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000839 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000838 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000837 ), + .Q(\blk00000003/sig000003f0 ) + ); + GND \blk00000003/blk00000117/blk00000118 ( + .G(\blk00000003/blk00000117/sig00000836 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014a/blk0000017c ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk0000014a/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f8 ), + .Q(\blk00000003/blk0000014a/sig0000089c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f9 ), + .Q(\blk00000003/blk0000014a/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000179 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f7 ), + .Q(\blk00000003/blk0000014a/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000178 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fb ), + .Q(\blk00000003/blk0000014a/sig00000899 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000177 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fc ), + .Q(\blk00000003/blk0000014a/sig00000898 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000176 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fa ), + .Q(\blk00000003/blk0000014a/sig0000089a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000175 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fe ), + .Q(\blk00000003/blk0000014a/sig00000896 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000174 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004ff ), + .Q(\blk00000003/blk0000014a/sig00000895 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000173 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fd ), + .Q(\blk00000003/blk0000014a/sig00000897 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000172 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000501 ), + .Q(\blk00000003/blk0000014a/sig00000893 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000171 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/blk0000014a/sig00000892 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000170 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000500 ), + .Q(\blk00000003/blk0000014a/sig00000894 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016f ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000504 ), + .Q(\blk00000003/blk0000014a/sig00000890 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016e ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000505 ), + .Q(\blk00000003/blk0000014a/sig0000088f ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016d ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000503 ), + .Q(\blk00000003/blk0000014a/sig00000891 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016c ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000507 ), + .Q(\blk00000003/blk0000014a/sig0000088d ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000508 ), + .Q(\blk00000003/blk0000014a/sig0000088c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000506 ), + .Q(\blk00000003/blk0000014a/sig0000088e ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000169 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050a ), + .Q(\blk00000003/blk0000014a/sig0000088a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000168 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050b ), + .Q(\blk00000003/blk0000014a/sig00000889 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000167 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000509 ), + .Q(\blk00000003/blk0000014a/sig0000088b ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000166 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050d ), + .Q(\blk00000003/blk0000014a/sig00000887 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000165 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050e ), + .Q(\blk00000003/blk0000014a/sig00000886 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000164 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050c ), + .Q(\blk00000003/blk0000014a/sig00000888 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089d ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089c ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089b ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089a ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000899 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000898 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000897 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000896 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000895 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000894 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000893 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000892 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000891 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000890 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088f ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088e ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088d ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088c ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088b ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088a ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000889 ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000888 ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000887 ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000886 ), + .Q(\blk00000003/sig00000408 ) + ); + GND \blk00000003/blk0000014a/blk0000014b ( + .G(\blk00000003/blk0000014a/sig00000885 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017d/blk000001af ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk0000017d/sig000008ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ae ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000017d/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ad ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000017d/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ac ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000017d/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ab ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000017d/sig000008e8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001aa ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000017d/sig000008e7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a9 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000017d/sig000008e9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a8 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000017d/sig000008e5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a7 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000017d/sig000008e4 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a6 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000017d/sig000008e6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a5 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000017d/sig000008e2 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a4 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000017d/sig000008e1 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a3 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000017d/sig000008e3 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a2 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000017d/sig000008df ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a1 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000017d/sig000008de ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a0 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000017d/sig000008e0 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000017d/sig000008dc ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000017d/sig000008db ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000017d/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000017d/sig000008d9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000017d/sig000008d8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000017d/sig000008da ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000199 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000017d/sig000008d6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000198 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000017d/sig000008d5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000197 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000017d/sig000008d7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ec ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008eb ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ea ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e9 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e8 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e7 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e6 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e5 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e4 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e3 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e2 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e1 ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e0 ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008df ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008de ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dd ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dc ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008db ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008da ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d9 ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d8 ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d7 ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d6 ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d5 ), + .Q(\blk00000003/sig00000450 ) + ); + GND \blk00000003/blk0000017d/blk0000017e ( + .G(\blk00000003/blk0000017d/sig000008d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b0/blk000001e2 ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk000001b0/sig0000093c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000510 ), + .Q(\blk00000003/blk000001b0/sig0000093a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000511 ), + .Q(\blk00000003/blk000001b0/sig00000939 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001df ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000050f ), + .Q(\blk00000003/blk000001b0/sig0000093b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001de ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000513 ), + .Q(\blk00000003/blk000001b0/sig00000937 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000514 ), + .Q(\blk00000003/blk000001b0/sig00000936 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000512 ), + .Q(\blk00000003/blk000001b0/sig00000938 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001db ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000516 ), + .Q(\blk00000003/blk000001b0/sig00000934 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001da ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000517 ), + .Q(\blk00000003/blk000001b0/sig00000933 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d9 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000515 ), + .Q(\blk00000003/blk000001b0/sig00000935 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d8 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000519 ), + .Q(\blk00000003/blk000001b0/sig00000931 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d7 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051a ), + .Q(\blk00000003/blk000001b0/sig00000930 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d6 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000518 ), + .Q(\blk00000003/blk000001b0/sig00000932 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d5 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051c ), + .Q(\blk00000003/blk000001b0/sig0000092e ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d4 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051d ), + .Q(\blk00000003/blk000001b0/sig0000092d ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d3 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051b ), + .Q(\blk00000003/blk000001b0/sig0000092f ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d2 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051f ), + .Q(\blk00000003/blk000001b0/sig0000092b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000520 ), + .Q(\blk00000003/blk000001b0/sig0000092a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051e ), + .Q(\blk00000003/blk000001b0/sig0000092c ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cf ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000522 ), + .Q(\blk00000003/blk000001b0/sig00000928 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ce ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000523 ), + .Q(\blk00000003/blk000001b0/sig00000927 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000521 ), + .Q(\blk00000003/blk000001b0/sig00000929 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000525 ), + .Q(\blk00000003/blk000001b0/sig00000925 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cb ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000526 ), + .Q(\blk00000003/blk000001b0/sig00000924 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ca ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000524 ), + .Q(\blk00000003/blk000001b0/sig00000926 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093b ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093a ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000939 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000938 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000937 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000936 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000935 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000934 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000933 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000932 ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000931 ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000930 ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092f ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092e ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092d ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092c ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092b ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092a ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000929 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000928 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000927 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000926 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000925 ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000924 ), + .Q(\blk00000003/sig00000468 ) + ); + GND \blk00000003/blk000001b0/blk000001b1 ( + .G(\blk00000003/blk000001b0/sig00000923 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e3/blk00000215 ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk000001e3/sig0000098b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000214 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/blk000001e3/sig00000989 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000213 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/blk000001e3/sig00000988 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000212 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/blk000001e3/sig0000098a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000211 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/blk000001e3/sig00000986 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000210 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/blk000001e3/sig00000985 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/blk000001e3/sig00000987 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/blk000001e3/sig00000983 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/blk000001e3/sig00000982 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/blk000001e3/sig00000984 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/blk000001e3/sig00000980 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/blk000001e3/sig0000097f ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000209 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/blk000001e3/sig00000981 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000208 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/blk000001e3/sig0000097d ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000207 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/blk000001e3/sig0000097c ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000206 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/blk000001e3/sig0000097e ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000205 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/blk000001e3/sig0000097a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000204 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/blk000001e3/sig00000979 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000203 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/blk000001e3/sig0000097b ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000202 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/blk000001e3/sig00000977 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000201 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002eb ), + .Q(\blk00000003/blk000001e3/sig00000976 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000200 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/blk000001e3/sig00000978 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001ff ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ed ), + .Q(\blk00000003/blk000001e3/sig00000974 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fe ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/blk000001e3/sig00000973 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fd ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/blk000001e3/sig00000975 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000098a ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000989 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000988 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000987 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000986 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000985 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000984 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000983 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000982 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000981 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000980 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000979 ), + .Q(\blk00000003/sig0000048c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000978 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000977 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000976 ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000975 ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000974 ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000973 ), + .Q(\blk00000003/sig00000492 ) + ); + GND \blk00000003/blk000001e3/blk000001e4 ( + .G(\blk00000003/blk000001e3/sig00000972 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000216/blk00000248 ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk00000216/sig000009da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000247 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000528 ), + .Q(\blk00000003/blk00000216/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000246 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000529 ), + .Q(\blk00000003/blk00000216/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000245 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000527 ), + .Q(\blk00000003/blk00000216/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000244 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052b ), + .Q(\blk00000003/blk00000216/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000243 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052c ), + .Q(\blk00000003/blk00000216/sig000009d4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000242 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052a ), + .Q(\blk00000003/blk00000216/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000241 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052e ), + .Q(\blk00000003/blk00000216/sig000009d2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000240 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052f ), + .Q(\blk00000003/blk00000216/sig000009d1 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052d ), + .Q(\blk00000003/blk00000216/sig000009d3 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000531 ), + .Q(\blk00000003/blk00000216/sig000009cf ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000532 ), + .Q(\blk00000003/blk00000216/sig000009ce ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000530 ), + .Q(\blk00000003/blk00000216/sig000009d0 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000534 ), + .Q(\blk00000003/blk00000216/sig000009cc ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000535 ), + .Q(\blk00000003/blk00000216/sig000009cb ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000239 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000533 ), + .Q(\blk00000003/blk00000216/sig000009cd ), + .Q15(\NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000238 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000537 ), + .Q(\blk00000003/blk00000216/sig000009c9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000237 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000538 ), + .Q(\blk00000003/blk00000216/sig000009c8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000236 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000536 ), + .Q(\blk00000003/blk00000216/sig000009ca ), + .Q15(\NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000235 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053a ), + .Q(\blk00000003/blk00000216/sig000009c6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000234 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053b ), + .Q(\blk00000003/blk00000216/sig000009c5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000233 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000539 ), + .Q(\blk00000003/blk00000216/sig000009c7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000232 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053d ), + .Q(\blk00000003/blk00000216/sig000009c3 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000231 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053e ), + .Q(\blk00000003/blk00000216/sig000009c2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000230 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053c ), + .Q(\blk00000003/blk00000216/sig000009c4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d9 ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d8 ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d7 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d6 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d5 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d4 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d3 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d2 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d1 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d0 ), + .Q(\blk00000003/sig0000049c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cf ), + .Q(\blk00000003/sig0000049d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ce ), + .Q(\blk00000003/sig0000049e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cd ), + .Q(\blk00000003/sig0000049f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cc ), + .Q(\blk00000003/sig000004a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cb ), + .Q(\blk00000003/sig000004a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ca ), + .Q(\blk00000003/sig000004a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c9 ), + .Q(\blk00000003/sig000004a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c8 ), + .Q(\blk00000003/sig000004a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c7 ), + .Q(\blk00000003/sig000004a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c6 ), + .Q(\blk00000003/sig000004a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c5 ), + .Q(\blk00000003/sig000004a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c4 ), + .Q(\blk00000003/sig000004a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c3 ), + .Q(\blk00000003/sig000004a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c2 ), + .Q(\blk00000003/sig000004aa ) + ); + GND \blk00000003/blk00000216/blk00000217 ( + .G(\blk00000003/blk00000216/sig000009c1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000249/blk0000027b ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk00000249/sig00000a29 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000027a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/blk00000249/sig00000a27 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000279 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000339 ), + .Q(\blk00000003/blk00000249/sig00000a26 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000278 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000337 ), + .Q(\blk00000003/blk00000249/sig00000a28 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000277 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033b ), + .Q(\blk00000003/blk00000249/sig00000a24 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000276 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033c ), + .Q(\blk00000003/blk00000249/sig00000a23 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000275 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033a ), + .Q(\blk00000003/blk00000249/sig00000a25 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000274 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033e ), + .Q(\blk00000003/blk00000249/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000273 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033f ), + .Q(\blk00000003/blk00000249/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000272 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033d ), + .Q(\blk00000003/blk00000249/sig00000a22 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000271 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/blk00000249/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000270 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000342 ), + .Q(\blk00000003/blk00000249/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000340 ), + .Q(\blk00000003/blk00000249/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000344 ), + .Q(\blk00000003/blk00000249/sig00000a1b ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000345 ), + .Q(\blk00000003/blk00000249/sig00000a1a ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000343 ), + .Q(\blk00000003/blk00000249/sig00000a1c ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000347 ), + .Q(\blk00000003/blk00000249/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000348 ), + .Q(\blk00000003/blk00000249/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000269 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000346 ), + .Q(\blk00000003/blk00000249/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000268 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034a ), + .Q(\blk00000003/blk00000249/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000267 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034b ), + .Q(\blk00000003/blk00000249/sig00000a14 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000266 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000349 ), + .Q(\blk00000003/blk00000249/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000265 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034d ), + .Q(\blk00000003/blk00000249/sig00000a12 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000264 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034e ), + .Q(\blk00000003/blk00000249/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000263 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034c ), + .Q(\blk00000003/blk00000249/sig00000a13 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a28 ), + .Q(\blk00000003/sig000004ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a27 ), + .Q(\blk00000003/sig000004ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a26 ), + .Q(\blk00000003/sig000004ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a25 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a24 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a23 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a22 ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a21 ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a20 ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1f ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1e ), + .Q(\blk00000003/sig000004b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1d ), + .Q(\blk00000003/sig000004b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1c ), + .Q(\blk00000003/sig000004b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1b ), + .Q(\blk00000003/sig000004b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1a ), + .Q(\blk00000003/sig000004b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a19 ), + .Q(\blk00000003/sig000004ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a18 ), + .Q(\blk00000003/sig000004bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a17 ), + .Q(\blk00000003/sig000004bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a16 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a15 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a14 ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a13 ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a12 ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a11 ), + .Q(\blk00000003/sig000004c2 ) + ); + GND \blk00000003/blk00000249/blk0000024a ( + .G(\blk00000003/blk00000249/sig00000a10 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027c/blk000002ae ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk0000027c/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ad ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000540 ), + .Q(\blk00000003/blk0000027c/sig00000a76 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ac ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk0000027c/sig00000a75 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ab ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000053f ), + .Q(\blk00000003/blk0000027c/sig00000a77 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002aa ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk0000027c/sig00000a73 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a9 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk0000027c/sig00000a72 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a8 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk0000027c/sig00000a74 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a7 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk0000027c/sig00000a70 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a6 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk0000027c/sig00000a6f ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a5 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk0000027c/sig00000a71 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a4 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk0000027c/sig00000a6d ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a3 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk0000027c/sig00000a6c ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a2 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk0000027c/sig00000a6e ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a1 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk0000027c/sig00000a6a ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a0 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk0000027c/sig00000a69 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk0000027c/sig00000a6b ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk0000027c/sig00000a67 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk0000027c/sig00000a66 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk0000027c/sig00000a68 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk0000027c/sig00000a64 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk0000027c/sig00000a63 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000299 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk0000027c/sig00000a65 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000298 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk0000027c/sig00000a61 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000297 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk0000027c/sig00000a60 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000296 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk0000027c/sig00000a62 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a77 ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a76 ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a75 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a74 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a73 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a72 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a71 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a70 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6f ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6e ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6d ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6c ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6b ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6a ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a69 ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a68 ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a67 ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a66 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a65 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a64 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a63 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a62 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a61 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a60 ), + .Q(\blk00000003/sig000004da ) + ); + GND \blk00000003/blk0000027c/blk0000027d ( + .G(\blk00000003/blk0000027c/sig00000a5f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002af/blk000002e1 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk000002af/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002e0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000002af/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002df ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000559 ), + .Q(\blk00000003/blk000002af/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002de ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000002af/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055b ), + .Q(\blk00000003/blk000002af/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055c ), + .Q(\blk00000003/blk000002af/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002db ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055a ), + .Q(\blk00000003/blk000002af/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002da ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055e ), + .Q(\blk00000003/blk000002af/sig00000abf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055f ), + .Q(\blk00000003/blk000002af/sig00000abe ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d8 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055d ), + .Q(\blk00000003/blk000002af/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d7 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000561 ), + .Q(\blk00000003/blk000002af/sig00000abc ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d6 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000562 ), + .Q(\blk00000003/blk000002af/sig00000abb ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d5 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000560 ), + .Q(\blk00000003/blk000002af/sig00000abd ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d4 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000564 ), + .Q(\blk00000003/blk000002af/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d3 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000565 ), + .Q(\blk00000003/blk000002af/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d2 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000563 ), + .Q(\blk00000003/blk000002af/sig00000aba ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d1 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000002af/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000002af/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cf ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000566 ), + .Q(\blk00000003/blk000002af/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ce ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000002af/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000002af/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000002af/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cb ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000002af/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ca ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000002af/sig00000aaf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002c9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000002af/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abe ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aba ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab5 ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab4 ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab3 ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab2 ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab1 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab0 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aaf ), + .Q(\blk00000003/sig000002ee ) + ); + GND \blk00000003/blk000002af/blk000002b0 ( + .G(\blk00000003/blk000002af/sig00000aae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e2/blk00000314 ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk000002e2/sig00000b16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000313 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000570 ), + .Q(\blk00000003/blk000002e2/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000312 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000571 ), + .Q(\blk00000003/blk000002e2/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000311 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000056f ), + .Q(\blk00000003/blk000002e2/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000310 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000573 ), + .Q(\blk00000003/blk000002e2/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000574 ), + .Q(\blk00000003/blk000002e2/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000572 ), + .Q(\blk00000003/blk000002e2/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000576 ), + .Q(\blk00000003/blk000002e2/sig00000b0e ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000577 ), + .Q(\blk00000003/blk000002e2/sig00000b0d ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000575 ), + .Q(\blk00000003/blk000002e2/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000579 ), + .Q(\blk00000003/blk000002e2/sig00000b0b ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000309 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057a ), + .Q(\blk00000003/blk000002e2/sig00000b0a ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000308 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000578 ), + .Q(\blk00000003/blk000002e2/sig00000b0c ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000307 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057c ), + .Q(\blk00000003/blk000002e2/sig00000b08 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000306 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057d ), + .Q(\blk00000003/blk000002e2/sig00000b07 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000305 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057b ), + .Q(\blk00000003/blk000002e2/sig00000b09 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000304 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057f ), + .Q(\blk00000003/blk000002e2/sig00000b05 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000303 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000580 ), + .Q(\blk00000003/blk000002e2/sig00000b04 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000302 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057e ), + .Q(\blk00000003/blk000002e2/sig00000b06 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000301 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000582 ), + .Q(\blk00000003/blk000002e2/sig00000b02 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000300 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000583 ), + .Q(\blk00000003/blk000002e2/sig00000b01 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002ff ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000581 ), + .Q(\blk00000003/blk000002e2/sig00000b03 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fe ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000585 ), + .Q(\blk00000003/blk000002e2/sig00000aff ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fd ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000586 ), + .Q(\blk00000003/blk000002e2/sig00000afe ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fc ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000584 ), + .Q(\blk00000003/blk000002e2/sig00000b00 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b15 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b14 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b13 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b12 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b11 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b10 ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0f ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0e ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0d ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0c ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0b ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0a ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b09 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b08 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b07 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b06 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b05 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b04 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b03 ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b02 ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b01 ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b00 ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000aff ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000afe ), + .Q(\blk00000003/sig00000306 ) + ); + GND \blk00000003/blk000002e2/blk000002e3 ( + .G(\blk00000003/blk000002e2/sig00000afd ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000315/blk00000347 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk00000315/sig00000b65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000346 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/blk00000315/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000345 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk00000315/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000344 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/blk00000315/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000343 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk00000315/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000342 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk00000315/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000341 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk00000315/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000340 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk00000315/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk00000315/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033e ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk00000315/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033d ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/blk00000315/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033c ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/blk00000315/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033b ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk00000315/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033a ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/blk00000315/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000339 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/blk00000315/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000338 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/blk00000315/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000337 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/blk00000315/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000336 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/blk00000315/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000335 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/blk00000315/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000334 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000315/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000333 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000315/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000332 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/blk00000315/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000331 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000315/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000330 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000315/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000032f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000315/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b64 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b63 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b62 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b61 ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b60 ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5f ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5e ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5d ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5c ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5b ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5a ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b59 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b58 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b57 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b56 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b55 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b54 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b53 ), + .Q(\blk00000003/sig00000348 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b52 ), + .Q(\blk00000003/sig00000349 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b51 ), + .Q(\blk00000003/sig0000034a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b50 ), + .Q(\blk00000003/sig0000034b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4f ), + .Q(\blk00000003/sig0000034c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4e ), + .Q(\blk00000003/sig0000034d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4d ), + .Q(\blk00000003/sig0000034e ) + ); + GND \blk00000003/blk00000315/blk00000316 ( + .G(\blk00000003/blk00000315/sig00000b4c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000348/blk0000037a ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk00000348/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000379 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000348/sig00000bb2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000378 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000348/sig00000bb1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000377 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000348/sig00000bb3 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000376 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/blk00000348/sig00000baf ), + .Q15(\NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000375 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/blk00000348/sig00000bae ), + .Q15(\NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000374 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/blk00000348/sig00000bb0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000373 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/blk00000348/sig00000bac ), + .Q15(\NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000372 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/blk00000348/sig00000bab ), + .Q15(\NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000371 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/blk00000348/sig00000bad ), + .Q15(\NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000370 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/blk00000348/sig00000ba9 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/blk00000348/sig00000ba8 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/blk00000348/sig00000baa ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/blk00000348/sig00000ba6 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/blk00000348/sig00000ba5 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/blk00000348/sig00000ba7 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/blk00000348/sig00000ba3 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000369 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/blk00000348/sig00000ba2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000368 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/blk00000348/sig00000ba4 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000367 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/blk00000348/sig00000ba0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000366 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000348/sig00000b9f ), + .Q15(\NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000365 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/blk00000348/sig00000ba1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000364 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000348/sig00000b9d ), + .Q15(\NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000363 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000348/sig00000b9c ), + .Q15(\NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000362 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000348/sig00000b9e ), + .Q15(\NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb3 ), + .Q(\blk00000003/sig0000034f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb2 ), + .Q(\blk00000003/sig00000350 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb1 ), + .Q(\blk00000003/sig00000351 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb0 ), + .Q(\blk00000003/sig00000352 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baf ), + .Q(\blk00000003/sig00000353 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bae ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bad ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bac ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bab ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baa ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba9 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba8 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba7 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba6 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba5 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba4 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba3 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba2 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba1 ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba0 ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9f ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9e ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9d ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9c ), + .Q(\blk00000003/sig00000366 ) + ); + GND \blk00000003/blk00000348/blk00000349 ( + .G(\blk00000003/blk00000348/sig00000b9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000037b/blk000003b3 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk0000037b/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c06 ), + .DPO(\blk00000003/blk0000037b/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c05 ), + .DPO(\blk00000003/blk0000037b/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b0 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c04 ), + .DPO(\blk00000003/blk0000037b/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003af ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c03 ), + .DPO(\blk00000003/blk0000037b/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ae ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c02 ), + .DPO(\blk00000003/blk0000037b/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ad ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c01 ), + .DPO(\blk00000003/blk0000037b/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ac ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bff ), + .DPO(\blk00000003/blk0000037b/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000037b/blk000003ab ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfe ), + .DPO(\blk00000003/blk0000037b/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003aa ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c00 ), + .DPO(\blk00000003/blk0000037b/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000037b/blk000003a9 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfd ), + .DPO(\blk00000003/blk0000037b/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000037b/blk000003a8 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfc ), + .DPO(\blk00000003/blk0000037b/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk0000037b/blk000003a7 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfb ), + .DPO(\blk00000003/blk0000037b/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000037b/blk000003a6 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfa ), + .DPO(\blk00000003/blk0000037b/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a5 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf9 ), + .DPO(\blk00000003/blk0000037b/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000004 )) + \blk00000003/blk0000037b/blk000003a4 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf8 ), + .DPO(\blk00000003/blk0000037b/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk0000037b/blk000003a3 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf6 ), + .DPO(\blk00000003/blk0000037b/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf5 ), + .DPO(\blk00000003/blk0000037b/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf7 ), + .DPO(\blk00000003/blk0000037b/sig00000c09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c18 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c17 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c16 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c15 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c14 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c13 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c12 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c11 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c10 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0f ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0e ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0d ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0c ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0b ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0a ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c09 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c08 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c07 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c06 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c05 ), + .Q(\blk00000003/sig000005ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c04 ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c03 ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c02 ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c01 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c00 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bff ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfe ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000385 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfd ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfc ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfb ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfa ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf9 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf8 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf7 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf6 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf5 ), + .Q(\blk00000003/sig000005da ) + ); + GND \blk00000003/blk0000037b/blk0000037c ( + .G(\blk00000003/blk0000037b/sig00000bf4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b4/blk000003ec ( + .I0(ce), + .I1(\blk00000003/sig000004e1 ), + .O(\blk00000003/blk000003b4/sig00000c7e ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003eb ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005c9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6b ), + .DPO(\blk00000003/blk000003b4/sig00000c7d ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003ea ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ca ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6a ), + .DPO(\blk00000003/blk000003b4/sig00000c7c ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e9 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cb ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c69 ), + .DPO(\blk00000003/blk000003b4/sig00000c7b ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e8 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cc ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c68 ), + .DPO(\blk00000003/blk000003b4/sig00000c7a ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e7 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cd ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c67 ), + .DPO(\blk00000003/blk000003b4/sig00000c79 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk000003b4/blk000003e6 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ce ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c66 ), + .DPO(\blk00000003/blk000003b4/sig00000c78 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk000003b4/blk000003e5 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d0 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c64 ), + .DPO(\blk00000003/blk000003b4/sig00000c76 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk000003b4/blk000003e4 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d1 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c63 ), + .DPO(\blk00000003/blk000003b4/sig00000c75 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003e3 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cf ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c65 ), + .DPO(\blk00000003/blk000003b4/sig00000c77 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003e2 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d2 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c62 ), + .DPO(\blk00000003/blk000003b4/sig00000c74 ) + ); + RAM32X1D #( + .INIT ( 32'h00000006 )) + \blk00000003/blk000003b4/blk000003e1 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d3 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c61 ), + .DPO(\blk00000003/blk000003b4/sig00000c73 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk000003b4/blk000003e0 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d4 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c60 ), + .DPO(\blk00000003/blk000003b4/sig00000c72 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003df ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d5 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5f ), + .DPO(\blk00000003/blk000003b4/sig00000c71 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003de ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d6 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5e ), + .DPO(\blk00000003/blk000003b4/sig00000c70 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003dd ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d7 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5d ), + .DPO(\blk00000003/blk000003b4/sig00000c6f ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000003b4/blk000003dc ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5b ), + .DPO(\blk00000003/blk000003b4/sig00000c6d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003db ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005da ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5a ), + .DPO(\blk00000003/blk000003b4/sig00000c6c ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk000003b4/blk000003da ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d8 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5c ), + .DPO(\blk00000003/blk000003b4/sig00000c6e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c79 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c78 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c77 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c76 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c75 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c74 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c73 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c72 ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c71 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c70 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6f ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6e ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6d ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6c ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6b ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6a ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c69 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c68 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c67 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c66 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c65 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c64 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c63 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c62 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c61 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c60 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5b ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5a ), + .Q(\blk00000003/sig000005ec ) + ); + GND \blk00000003/blk000003b4/blk000003b5 ( + .G(\blk00000003/blk000003b4/sig00000c59 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000044d/blk00000473 ( + .I0(ce), + .I1(\blk00000003/sig000004e2 ), + .O(\blk00000003/blk0000044d/sig00000cbf ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000472 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005db ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbe ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000044d/blk00000471 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dc ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbd ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000470 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dd ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbc ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046f ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005de ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbb ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk0000046e ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005df ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cba ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046d ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e0 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046c ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e2 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk0000046b ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e3 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046a ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e1 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000469 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e4 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000468 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e5 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb4 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk0000044d/blk00000467 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e6 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000466 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e7 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000465 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e8 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk00000464 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e9 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000463 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005eb ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cae ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk00000462 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ec ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cad ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000044d/blk00000461 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ea ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000caf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbe ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbd ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbc ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbb ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cba ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb9 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb8 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb7 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb6 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb5 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb4 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb3 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb2 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb1 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb0 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000451 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000caf ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cae ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cad ), + .Q(\blk00000003/sig000003d8 ) + ); + GND \blk00000003/blk0000044d/blk0000044e ( + .G(\blk00000003/blk0000044d/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004a4/blk000004ca ( + .I0(ce), + .I1(\blk00000003/sig00000230 ), + .O(\blk00000003/blk000004a4/sig00000cfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000004a4/blk000004c9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c7 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c6 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c5 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c4 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c3 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c2 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c1 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c0 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bf ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004be ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bd ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cef ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bc ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cee ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bb ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ced ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004ba ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ceb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cea ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfb ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfa ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf9 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf8 ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf7 ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf6 ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf5 ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf4 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf3 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf2 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf1 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf0 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cef ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cee ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ced ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cec ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ceb ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cea ), + .Q(\blk00000003/sig00000104 ) + ); + GND \blk00000003/blk000004a4/blk000004a5 ( + .G(\blk00000003/blk000004a4/sig00000ce9 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc new file mode 100644 index 000000000..5eaff1030 --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0dg2~753-Xnzd}foo8#5+421).97 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155289;j6`;3081<>=h9::i6=4+4209566a3g>8=7<6;:m275g=83.???4>31d8j1562;k07b?<0083>!24:3;85$511>457n2d??<4=c:9l57ce290/8><5122e?k24938o76a>2d294?"3;;0:?=h4n512>7c<3f;9hk4?:%606?748o1e8>?52g98k454i3:1(9==:0174>h3;80;76a>32;94?"3;;0:?9>4n512>4=5$511>45382d??<4=;:m2761=83.???4>3528j1562:10c<=<6;29 155289?<6`;3087?>i6;:?1<7*;3382716=50;&777<6;=:0b9=>:698k45493:1(9==:0174>h3;80376a>32294?"3;;0:?9>4n512><=5$511>45382d??<4n;:m277c=83.???4>3528j1562k10c<==d;29 155289?<6`;308`?>i6;;i1<7*;3382716:g98k45513:1(9==:0174>h3;80:<65`120;>5<#<:81=>:?;o605?7632e:??850;&777<6;=:0b9=>:008?j74:<0;6):<2;3005=i<:;1=>54o0110?6=,=996<=;0:l774<6<21d=><<:18'064=9:>;7c:<1;36?>i6;;81<7*;33827168>7?<419m067=9>10c<==0;29 155289?<6`;3082<>=h9:;m6=4+420956273g>8=7?6;:m274c=83.???4>3528j15628k07b?<1e83>!24:3;88=5a42395g=5$511>45382d??<4>c:9l567f290/8><51263?k2493;o76a>30;94?"3;;0:?9>4n512>4c<3f;8=54?:%606?74<91e8>?51g98k456?3:1(9==:0174>h3;809<65`1235>5<#<:81=>:?;o605?4632e:?<;50;&777<6;=:0b9=>:308?j749=0;6):<2;3005=i<:;1>>54o0127?6=,=996<=;0:l774<5<21d=>?=:18'064=9:>;7c:<1;06?>i6;:l1<7*;33827168>7?<419m067=:>10c<==h9:9h6=4+420956273g>8=7<6;:m276d=83.???4>3528j1562;k07b?<3383>!24:3;88=5a42396g=5$511>45382d??<4=c:9l567d290/8><51263?k24938o76a>30394?"3;;0:?9>4n512>7c<3f;8==4?:%606?74<91e8>?52g98k451j3:1(9==:0145>h3;80;76a>37c94?"3;;0:?:?4n512>4=5$511>45092d??<4=;:m273>=83.???4>3638j1562:10c<=97;29 155289<=6`;3087?>i6;?<1<7*;3382727;0b9=>:698k451:3:1(9==:0145>h3;80376a>37394?"3;;0:?:?4n512><=5$511>45092d??<4n;:m270`=83.???4>3638j1562k10c<=:e;29 155289<=6`;308`?>i6;;0b9=>:g98k452i3:1(9==:0145>h3;80:<65`127:>5<#<:81=>9>;o605?7632e:?8950;&777<6;>;0b9=>:008?j74=?0;6):<2;3034=i<:;1=>54o0161?6=,=996<=81:l774<6<21d=>;;:18'064=9:=:7c:<1;36?>i6;<91<7*;33827278>7?<709m067=9>10c<=:1;29 155289<=6`;3082<>=h9:?;6=4+420956163g>8=7?6;:m271`=83.???4>3638j15628k07b?<4d83>!24:3;8;<5a42395g=5$511>45092d??<4>c:9l562e290/8><51252?k2493;o76a>35c94?"3;;0:?:?4n512>4c<3f;8844?:%606?74?81e8>?51g98k45303:1(9==:0145>h3;809<65`1264>5<#<:81=>9>;o605?4632e:?9850;&777<6;>;0b9=>:308?j74<<0;6):<2;3034=i<:;1>>54o0170?6=,=996<=81:l774<5<21d=>:<:18'064=9:=:7c:<1;06?>i6;>:1<7*;33827278>7?<709m067=:>10c<=9e;29 155289<=6`;3081<>=h9:8=7<6;:m273e=83.???4>3638j1562;k07b?<6283>!24:3;8;<5a42396g=47>5$511>45092d??<4=c:9l562c290/8><51252?k24938o76a>35094?"3;;0:?:?4n512>7c<3f;88<4?:%606?74?81e8>?52g98md`02900c<=6c;29 155289j>6`;3083?>i6;0h1<7*;33827d4:298k45>03:1(9==:01b6>h3;80?76a>38594?"3;;0:?l<4n512>0=5$511>45f:2d??<49;:m27<3=83.???4>3`08j1562>10c<=63;29 155289j>6`;308;?>i6;081<7*;33827d450;&777<6;h80b9=>:c98k45?n3:1(9==:01b6>h3;80h76a>39g94?"3;;0:?l<4n512>a=5$511>45f:2d??<4j;:m27=e=83.???4>3`08j1562o10c<=7b;29 155289j>6`;30824>=h9:2j6=4+420956g53g>8=7?>;:m27=>=83.???4>3`08j15628807b?<8683>!24:3;8m?5a423956=5$511>45f:2d??<4>4:9l56>2290/8><512c1?k2493;>76a>39694?"3;;0:?l<4n512>40<3f;84>4?:%606?74i;1e8>?51698k45?:3:1(9==:01b6>h3;80:465`12:2>5<#<:81=>o=;o605?7>32e:?5>50;&777<6;h80b9=>:0c8?j74?o0;6):<2;30e7=i<:;1=o54o014`?6=,=996<=n2:l774<6k21d=>9l:18'064=9:k97c:<1;3g?>i6;>h1<7*;33827d48>7?6`;30814>=h9:=36=4+420956g53g>8=7<>;:m2721=83.???4>3`08j1562;807b?<7783>!24:3;8m?5a423966=5$511>45f:2d??<4=4:9l5613290/8><512c1?k24938>76a>3`394?"3;;0:?l<4n512>70<3f;8m=4?:%606?74i;1e8>?52698k45>n3:1(9==:01b6>h3;809465`12;f>5<#<:81=>o=;o605?4>32e:?4j50;&777<6;h80b9=>:3c8?j741=0;6):<2;30e7=i<:;1>o54o01;=?6=,=996<=n2:l774<5k21d=>9j:18'064=9:k97c:<1;0g?>i6;>91<7*;33827d48>7?i6;ji1<7*;33827a5:298k45d13:1(9==:01g7>h3;80?76a>3b:94?"3;;0:?i=4n512>0=5$511>45c;2d??<49;:m27f0=83.???4>3e18j1562>10c<=l4;29 155289o?6`;308;?>i6;j91<7*;33827a5:c98k45d83:1(9==:01g7>h3;80h76a>3cd94?"3;;0:?i=4n512>a=5$511>45c;2d??<4j;:m27gb=83.???4>3e18j1562o10c<=mc;29 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h<5>4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<594?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<584?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5;4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5:4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<554?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<544?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5l4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5o4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5n4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5i4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5h4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5k4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3tho7;t3181f?562;o1>k4ri02:>5<#<:81==64n512>5=5<#<:81>=l4n512>4=5<#<:81>=l4n512>6=5<#<:81>=l4n512>0=6=4+420965d5<#<:81>=l4n512>2=5<#<:81>=l4n512><=5<#<:81>=l4n512>g=5<#<:81>=l4n512>a=6=4+420965d5<#<:81>=l4n512>c=4;h037?6=,=996?>m;o605?7632c:==4?:%606?77n2d??<4?;:k71<<722c:5h4?::k701<722c:mk4?::m17`<72->8>7<;:m17g<72->8>7<8>7<8>7<8>7<8>7<4?:%606?44l2d??<4m;:m127<72->8>7<8>7<8>7<>;50;&777<5;m1e8>?51098k717290/8><527d8j1562910c?8j:18'064=:?l0b9=>:098k70c290/8><527d8j1562;10c?8l:18'064=:?l0b9=>:298k70e290/8><527d8j1562=10c?8n:18'064=:?l0b9=>:498k70>290/8><527d8j1562?10c?87:18'064=:?l0b9=>:698k7??290/8><527d8j1562110c?78:18'064=:?l0b9=>:898k7?1290/8><527d8j1562h10c?7::18'064=:?l0b9=>:c98k7?3290/8><527d8j1562j10c?7<:18'064=:?l0b9=>:e98k7>>290/8><527d8j1562l10c?9j:18'064=:?l0b9=>:g98k714290/8><527d8j15628:07b<97;29 1552;d0lo0;6<4?:1y'01b=:k=0D9;l;I664>i5j?0;66sm7d294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l;1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d094?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l91<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d694?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l?1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d494?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l=1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d:94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l31<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dc94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?lh1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7da94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ln1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dg94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ll1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7g294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?o;1<7:50;2x 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\ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v new file mode 100644 index 000000000..cd6e39d9f --- /dev/null +++ b/fpga/usrp3/top/n3xx/coregen_dsp/hbdec3.v @@ -0,0 +1,20014 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec3.v +// /___/ /\ Timestamp: Wed Dec 4 13:32:32 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec3.ngc ./tmp/_cg/hbdec3.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec3.ngc +// Output file : ./tmp/_cg/hbdec3.v +// # of Modules : 1 +// Design Name : hbdec3 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec3 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [47 : 0] dout_1; + output [47 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000664 ; + wire \blk00000003/sig00000663 ; + wire \blk00000003/sig00000662 ; + wire \blk00000003/sig00000661 ; + wire \blk00000003/sig00000660 ; + wire \blk00000003/sig0000065f ; + wire \blk00000003/sig0000065e ; + wire \blk00000003/sig0000065d ; + wire \blk00000003/sig0000065c ; + wire \blk00000003/sig0000065b ; + wire \blk00000003/sig0000065a ; + wire \blk00000003/sig00000659 ; + wire \blk00000003/sig00000658 ; + wire \blk00000003/sig00000657 ; + wire \blk00000003/sig00000656 ; + wire \blk00000003/sig00000655 ; + wire \blk00000003/sig00000654 ; + wire \blk00000003/sig00000653 ; + wire \blk00000003/sig00000652 ; + wire \blk00000003/sig00000651 ; + wire \blk00000003/sig00000650 ; + wire \blk00000003/sig0000064f ; + wire \blk00000003/sig0000064e ; + wire \blk00000003/sig0000064d ; + wire \blk00000003/sig0000064c ; + wire \blk00000003/sig0000064b ; + wire \blk00000003/sig0000064a ; + wire \blk00000003/sig00000649 ; + wire \blk00000003/sig00000648 ; + wire \blk00000003/sig00000647 ; + wire \blk00000003/sig00000646 ; + wire \blk00000003/sig00000645 ; + wire \blk00000003/sig00000644 ; + wire \blk00000003/sig00000643 ; + wire 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\blk00000003/blk000002b1/sig000009c7 ; + wire \blk00000003/blk000002b1/sig000009c6 ; + wire \blk00000003/blk000002b1/sig000009c5 ; + wire \blk00000003/blk000002b1/sig000009c4 ; + wire \blk00000003/blk000002b1/sig000009c3 ; + wire \blk00000003/blk000002b1/sig000009c2 ; + wire \blk00000003/blk000002b1/sig000009c1 ; + wire \blk00000003/blk000002b1/sig000009c0 ; + wire \blk00000003/blk000002b1/sig000009bf ; + wire \blk00000003/blk000002ea/sig00000a27 ; + wire \blk00000003/blk000002ea/sig00000a26 ; + wire \blk00000003/blk000002ea/sig00000a25 ; + wire \blk00000003/blk000002ea/sig00000a24 ; + wire \blk00000003/blk000002ea/sig00000a23 ; + wire \blk00000003/blk000002ea/sig00000a22 ; + wire \blk00000003/blk000002ea/sig00000a21 ; + wire \blk00000003/blk000002ea/sig00000a20 ; + wire \blk00000003/blk000002ea/sig00000a1f ; + wire \blk00000003/blk000002ea/sig00000a1e ; + wire \blk00000003/blk000002ea/sig00000a1d ; + wire \blk00000003/blk000002ea/sig00000a1c ; + wire \blk00000003/blk000002ea/sig00000a1b ; + wire \blk00000003/blk000002ea/sig00000a1a ; + wire \blk00000003/blk000002ea/sig00000a19 ; + wire \blk00000003/blk000002ea/sig00000a18 ; + wire \blk00000003/blk000002ea/sig00000a17 ; + wire \blk00000003/blk000002ea/sig00000a16 ; + wire \blk00000003/blk000002ea/sig00000a15 ; + wire \blk00000003/blk000002ea/sig00000a14 ; + wire \blk00000003/blk00000371/sig00000a64 ; + wire \blk00000003/blk00000371/sig00000a63 ; + wire \blk00000003/blk00000371/sig00000a62 ; + wire \blk00000003/blk00000371/sig00000a61 ; + wire \blk00000003/blk00000371/sig00000a60 ; + wire \blk00000003/blk00000371/sig00000a5f ; + wire \blk00000003/blk00000371/sig00000a5e ; + wire \blk00000003/blk00000371/sig00000a5d ; + wire \blk00000003/blk00000371/sig00000a5c ; + wire \blk00000003/blk00000371/sig00000a5b ; + wire \blk00000003/blk00000371/sig00000a5a ; + wire \blk00000003/blk00000371/sig00000a59 ; + wire \blk00000003/blk00000371/sig00000a58 ; + wire \blk00000003/blk00000371/sig00000a57 ; + wire \blk00000003/blk00000371/sig00000a56 ; + wire \blk00000003/blk00000371/sig00000a55 ; + wire \blk00000003/blk00000371/sig00000a54 ; + wire \blk00000003/blk00000371/sig00000a53 ; + wire \blk00000003/blk00000371/sig00000a52 ; + wire \blk00000003/blk00000371/sig00000a51 ; + wire NLW_blk00000001_P_UNCONNECTED; + wire NLW_blk00000002_G_UNCONNECTED; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000618_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000616_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000614_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000608_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000606_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000604_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000598_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000596_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000594_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000592_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000590_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000588_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000586_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000584_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000568_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000566_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000564_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000562_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000560_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000558_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000556_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000554_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000552_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000550_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000534_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000532_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000530_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000528_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000526_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000524_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000522_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000520_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000008f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [47 : 0] NlwRenamedSig_OI_dout_1; + wire [47 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[47] = NlwRenamedSig_OI_dout_1[47], + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[47] = NlwRenamedSig_OI_dout_2[47], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/sig00000579 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000434 ), + .Q(\blk00000003/sig00000664 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/sig00000502 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000042e ), + .Q(\blk00000003/sig00000663 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000630 ), + .Q(\blk00000003/sig00000662 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062e ), + .Q(\blk00000003/sig00000661 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062c ), + .Q(\blk00000003/sig00000660 ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062a ), + .Q(\blk00000003/sig0000065f ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000628 ), + .Q(\blk00000003/sig0000065e ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000626 ), + .Q(\blk00000003/sig0000065d ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000624 ), + .Q(\blk00000003/sig0000065c ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061e ), + .Q(\blk00000003/sig0000065b ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000622 ), + .Q(\blk00000003/sig0000065a ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000618 ), + .Q(\blk00000003/sig00000659 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061c ), + .Q(\blk00000003/sig00000658 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000620 ), + .Q(\blk00000003/sig00000657 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000616 ), + .Q(\blk00000003/sig00000656 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000614 ), + .Q(\blk00000003/sig00000655 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061a ), + .Q(\blk00000003/sig00000654 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000612 ), + .Q(\blk00000003/sig00000653 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000610 ), + .Q(\blk00000003/sig00000652 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060e ), + .Q(\blk00000003/sig00000651 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000608 ), + .Q(\blk00000003/sig00000650 ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060c ), + .Q(\blk00000003/sig0000064f ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000602 ), + .Q(\blk00000003/sig0000064e ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000606 ), + .Q(\blk00000003/sig0000064d ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060a ), + .Q(\blk00000003/sig0000064c ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000600 ), + .Q(\blk00000003/sig0000064b ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000626 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fe ), + .Q(\blk00000003/sig0000064a ), + .Q15(\NLW_blk00000003/blk00000626_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000624 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig00000649 ), + .Q15(\NLW_blk00000003/blk00000624_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000622 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fc ), + .Q(\blk00000003/sig00000648 ), + .Q15(\NLW_blk00000003/blk00000622_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000620 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/sig00000647 ), + .Q15(\NLW_blk00000003/blk00000620_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/sig00000646 ), + .Q15(\NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/sig00000645 ), + .Q15(\NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/sig00000644 ), + .Q15(\NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000618 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/sig00000643 ), + .Q15(\NLW_blk00000003/blk00000618_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000616 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/sig00000642 ), + .Q15(\NLW_blk00000003/blk00000616_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000614 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/sig00000641 ), + .Q15(\NLW_blk00000003/blk00000614_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000613 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000612 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/sig00000640 ), + .Q15(\NLW_blk00000003/blk00000612_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000611 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000610 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/sig0000063f ), + .Q15(\NLW_blk00000003/blk00000610_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/sig0000063e ), + .Q15(\NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/sig0000063d ), + .Q15(\NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/sig0000063c ), + .Q15(\NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000608 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e2 ), + .Q(\blk00000003/sig0000063b ), + .Q15(\NLW_blk00000003/blk00000608_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000606 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e0 ), + .Q(\blk00000003/sig0000063a ), + .Q15(\NLW_blk00000003/blk00000606_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000604 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005de ), + .Q(\blk00000003/sig00000639 ), + .Q15(\NLW_blk00000003/blk00000604_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005dc ), + .Q(\blk00000003/sig00000638 ), + .Q15(\NLW_blk00000003/blk00000602_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000600 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005da ), + .Q(\blk00000003/sig00000637 ), + .Q15(\NLW_blk00000003/blk00000600_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fe ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d8 ), + .Q(\blk00000003/sig00000636 ), + .Q15(\NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fc ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d6 ), + .Q(\blk00000003/sig00000635 ), + .Q15(\NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fa ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d4 ), + .Q(\blk00000003/sig00000634 ), + .Q15(\NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f8 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d0 ), + .Q(\blk00000003/sig00000633 ), + .Q15(\NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .Q(\blk00000003/sig00000434 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig00000632 ), + .Q15(\NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .Q(\blk00000003/sig0000057a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ae ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c4 ), + .Q(\blk00000003/sig00000631 ), + .Q15(\NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062f ), + .Q(\blk00000003/sig00000630 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig0000062f ), + .Q15(\NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062d ), + .Q(\blk00000003/sig0000062e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig0000062d ), + .Q15(\NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062b ), + .Q(\blk00000003/sig0000062c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000062b ), + .Q15(\NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000629 ), + .Q(\blk00000003/sig0000062a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000629 ), + .Q15(\NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000627 ), + .Q(\blk00000003/sig00000628 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000627 ), + .Q15(\NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000625 ), + .Q(\blk00000003/sig00000626 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000625 ), + .Q15(\NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000623 ), + .Q(\blk00000003/sig00000624 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000623 ), + .Q15(\NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000621 ), + .Q(\blk00000003/sig00000622 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000621 ), + .Q15(\NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061f ), + .Q(\blk00000003/sig00000620 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig0000061f ), + .Q15(\NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061d ), + .Q(\blk00000003/sig0000061e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig0000061d ), + .Q15(\NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005df ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061b ), + .Q(\blk00000003/sig0000061c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig0000061b ), + .Q15(\NLW_blk00000003/blk000005de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000619 ), + .Q(\blk00000003/sig0000061a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000619 ), + .Q15(\NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005db ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000617 ), + .Q(\blk00000003/sig00000618 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000617 ), + .Q15(\NLW_blk00000003/blk000005da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000615 ), + .Q(\blk00000003/sig00000616 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000615 ), + .Q15(\NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000613 ), + .Q(\blk00000003/sig00000614 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000613 ), + .Q15(\NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000611 ), + .Q(\blk00000003/sig00000612 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000611 ), + .Q15(\NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060f ), + .Q(\blk00000003/sig00000610 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig0000060f ), + .Q15(\NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060d ), + .Q(\blk00000003/sig0000060e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000060d ), + .Q15(\NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060b ), + .Q(\blk00000003/sig0000060c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig0000060b ), + .Q15(\NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000609 ), + .Q(\blk00000003/sig0000060a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000609 ), + .Q15(\NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000607 ), + .Q(\blk00000003/sig00000608 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000607 ), + .Q15(\NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000605 ), + .Q(\blk00000003/sig00000606 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000605 ), + .Q15(\NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000603 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000603 ), + .Q15(\NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000601 ), + .Q(\blk00000003/sig00000602 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000601 ), + .Q15(\NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ff ), + .Q(\blk00000003/sig00000600 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005ff ), + .Q15(\NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fd ), + .Q(\blk00000003/sig000005fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005fd ), + .Q15(\NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fb ), + .Q(\blk00000003/sig000005fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005fb ), + .Q15(\NLW_blk00000003/blk000005be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/sig000005fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005f9 ), + .Q15(\NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/sig000005f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005f7 ), + .Q15(\NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/sig000005f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005f5 ), + .Q15(\NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/sig000005f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005f3 ), + .Q15(\NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/sig000005f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005f1 ), + .Q15(\NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005ef ), + .Q15(\NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/sig000005ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ed ), + .Q15(\NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005af ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/sig000005ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005eb ), + .Q15(\NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ad ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/sig000005ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005e9 ), + .Q15(\NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ab ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/sig000005e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005e7 ), + .Q15(\NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/sig000005e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005e5 ), + .Q15(\NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/sig000005e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005e3 ), + .Q15(\NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e1 ), + .Q(\blk00000003/sig000005e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005e1 ), + .Q15(\NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005df ), + .Q(\blk00000003/sig000005e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005df ), + .Q15(\NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005dd ), + .Q(\blk00000003/sig000005de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005dd ), + .Q15(\NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059f ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005db ), + .Q(\blk00000003/sig000005dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005db ), + .Q15(\NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059d ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d9 ), + .Q(\blk00000003/sig000005da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005d9 ), + .Q15(\NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059b ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d7 ), + .Q(\blk00000003/sig000005d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005d7 ), + .Q15(\NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d5 ), + .Q(\blk00000003/sig000005d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000598 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005d5 ), + .Q15(\NLW_blk00000003/blk00000598_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000597 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d3 ), + .Q(\blk00000003/sig000005d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000596 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005d3 ), + .Q15(\NLW_blk00000003/blk00000596_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d2 ), + .Q(\blk00000003/sig00000581 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000594 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000435 ), + .Q(\blk00000003/sig000005d2 ), + .Q15(\NLW_blk00000003/blk00000594_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d1 ), + .Q(\blk00000003/sig00000480 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000592 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig000005d1 ), + .Q15(\NLW_blk00000003/blk00000592_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000591 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005cf ), + .Q(\blk00000003/sig000005d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000590 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000005cf ), + .Q15(\NLW_blk00000003/blk00000590_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ce ), + .Q(\blk00000003/sig0000047e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000005ce ), + .Q15(\NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cd ), + .Q(\blk00000003/sig0000047d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000005cd ), + .Q15(\NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cc ), + .Q(\blk00000003/sig0000047f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig000005cc ), + .Q15(\NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cb ), + .Q(\blk00000003/sig0000047b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000588 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000005cb ), + .Q15(\NLW_blk00000003/blk00000588_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/sig0000047a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000586 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000005ca ), + .Q15(\NLW_blk00000003/blk00000586_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/sig0000047c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000584 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000005c9 ), + .Q15(\NLW_blk00000003/blk00000584_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/sig00000479 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000005c8 ), + .Q15(\NLW_blk00000003/blk00000582_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/sig00000478 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000580 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000005c7 ), + .Q15(\NLW_blk00000003/blk00000580_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/sig00000476 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000005c6 ), + .Q15(\NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/sig00000475 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000005c5 ), + .Q15(\NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/sig00000477 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000005c4 ), + .Q15(\NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/sig00000473 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000578 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000005c3 ), + .Q15(\NLW_blk00000003/blk00000578_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/sig00000472 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000576 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000005c2 ), + .Q15(\NLW_blk00000003/blk00000576_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/sig00000474 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000574 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000005c1 ), + .Q15(\NLW_blk00000003/blk00000574_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/sig00000470 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000572 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000005c0 ), + .Q15(\NLW_blk00000003/blk00000572_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/sig0000046f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000570 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000005bf ), + .Q15(\NLW_blk00000003/blk00000570_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/sig00000471 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000005be ), + .Q15(\NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/sig0000046e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000005bd ), + .Q15(\NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/sig0000046d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000005bc ), + .Q15(\NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/sig0000046b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000568 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000005bb ), + .Q15(\NLW_blk00000003/blk00000568_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/sig0000046a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000566 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000005ba ), + .Q15(\NLW_blk00000003/blk00000566_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/sig0000046c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000564 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000005b9 ), + .Q15(\NLW_blk00000003/blk00000564_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/sig000004b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000562 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005b8 ), + .Q15(\NLW_blk00000003/blk00000562_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/sig000004af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000560 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005b7 ), + .Q15(\NLW_blk00000003/blk00000560_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/sig00000469 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000005b6 ), + .Q15(\NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/sig000004ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005b5 ), + .Q15(\NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/sig000004ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005b4 ), + .Q15(\NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/sig000004ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000558 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005b3 ), + .Q15(\NLW_blk00000003/blk00000558_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/sig000004ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000556 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005b2 ), + .Q15(\NLW_blk00000003/blk00000556_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/sig000004aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000554 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005b1 ), + .Q15(\NLW_blk00000003/blk00000554_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/sig000004a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000552 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005b0 ), + .Q15(\NLW_blk00000003/blk00000552_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/sig000004a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000550 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005af ), + .Q15(\NLW_blk00000003/blk00000550_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/sig000004a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005ae ), + .Q15(\NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/sig000004a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ad ), + .Q15(\NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/sig000004a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005ac ), + .Q15(\NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/sig000004a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000548 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005ab ), + .Q15(\NLW_blk00000003/blk00000548_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/sig000004a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000546 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005aa ), + .Q15(\NLW_blk00000003/blk00000546_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/sig000004a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000544 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005a9 ), + .Q15(\NLW_blk00000003/blk00000544_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/sig000004a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000542 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005a8 ), + .Q15(\NLW_blk00000003/blk00000542_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/sig000004a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000540 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005a7 ), + .Q15(\NLW_blk00000003/blk00000540_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/sig0000049e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005a6 ), + .Q15(\NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/sig0000049d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005a5 ), + .Q15(\NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/sig0000049f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005a4 ), + .Q15(\NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/sig0000049b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000538 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005a3 ), + .Q15(\NLW_blk00000003/blk00000538_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/sig0000049a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000536 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005a2 ), + .Q15(\NLW_blk00000003/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/sig0000049c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000534 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005a1 ), + .Q15(\NLW_blk00000003/blk00000534_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/sig000002de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000532 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig000005a0 ), + .Q15(\NLW_blk00000003/blk00000532_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/sig000002df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000059f ), + .Q15(\NLW_blk00000003/blk00000530_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/sig00000499 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig0000059e ), + .Q15(\NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/sig00000580 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d2 ), + .Q(\blk00000003/sig0000059d ), + .Q15(\NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/sig000004da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000059c ), + .Q15(\NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/sig000004d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000528 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000059b ), + .Q15(\NLW_blk00000003/blk00000528_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/sig000004d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000526 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000059a ), + .Q15(\NLW_blk00000003/blk00000526_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/sig000004d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000524 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000599 ), + .Q15(\NLW_blk00000003/blk00000524_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/sig000004d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000522 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000598 ), + .Q15(\NLW_blk00000003/blk00000522_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/sig000004d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000520 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000597 ), + .Q15(\NLW_blk00000003/blk00000520_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/sig000004d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000596 ), + .Q15(\NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/sig000004d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000595 ), + .Q15(\NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/sig000004d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000594 ), + .Q15(\NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/sig000004d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000518 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000593 ), + .Q15(\NLW_blk00000003/blk00000518_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/sig000004d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000516 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000592 ), + .Q15(\NLW_blk00000003/blk00000516_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/sig000004cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000514 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000591 ), + .Q15(\NLW_blk00000003/blk00000514_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/sig000004cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000512 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000590 ), + .Q15(\NLW_blk00000003/blk00000512_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/sig000004cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000510 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig0000058f ), + .Q15(\NLW_blk00000003/blk00000510_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/sig000004ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig0000058e ), + .Q15(\NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/sig000004ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000058d ), + .Q15(\NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/sig000004c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000058c ), + .Q15(\NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/sig000004cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig0000058b ), + .Q15(\NLW_blk00000003/blk00000508_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/sig000001e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000506 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e3 ), + .Q(\blk00000003/sig0000058a ), + .Q15(\NLW_blk00000003/blk00000506_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/sig0000042e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000504 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d8 ), + .Q(\blk00000003/sig00000589 ), + .Q15(\NLW_blk00000003/blk00000504_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000503 ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000288 ) + ); + INV \blk00000003/blk00000502 ( + .I(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000281 ) + ); + INV \blk00000003/blk00000501 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000296 ) + ); + INV \blk00000003/blk00000500 ( + .I(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000287 ) + ); + INV \blk00000003/blk000004ff ( + .I(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000578 ) + ); + INV \blk00000003/blk000004fe ( + .I(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000299 ) + ); + INV \blk00000003/blk000004fd ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000282 ) + ); + INV \blk00000003/blk000004fc ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000245 ) + ); + INV \blk00000003/blk000004fb ( + .I(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000227 ) + ); + INV \blk00000003/blk000004fa ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000b9 ) + ); + INV \blk00000003/blk000004f9 ( + .I(\blk00000003/sig000000b6 ), + .O(\blk00000003/sig000000b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig0000057c ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004f7 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000249 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000004f6 ( + .I0(\blk00000003/sig0000024a ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig0000024d ), + .I3(coef_ld), + .I4(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000241 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000004f5 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000248 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000004f4 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024d ), + .I4(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f3 ( + .I0(\blk00000003/sig00000291 ), + .I1(ce), + .I2(\blk00000003/sig0000023e ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000588 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f2 ( + .I0(\blk00000003/sig00000298 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000289 ), + .O(\blk00000003/sig00000587 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f1 ( + .I0(\blk00000003/sig0000057b ), + .I1(ce), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig00000585 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004f0 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000057f ), + .O(\blk00000003/sig00000584 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004ef ( + .I0(ce), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000583 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000004ee ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000002a2 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000586 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ed ( + .C(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/sig00000291 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ec ( + .C(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/sig00000298 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e9 ( + .I0(\blk00000003/sig00000500 ), + .O(\blk00000003/sig000004fb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e8 ( + .I0(\blk00000003/sig000004ff ), + .O(\blk00000003/sig000004f8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e7 ( + .I0(\blk00000003/sig000004fe ), + .O(\blk00000003/sig000004f5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e6 ( + .I0(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004f2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e5 ( + .I0(\blk00000003/sig000002da ), + .O(\blk00000003/sig000002db ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e4 ( + .I0(\blk00000003/sig000002d7 ), + .O(\blk00000003/sig000002d8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e3 ( + .I0(\blk00000003/sig000002d3 ), + .O(\blk00000003/sig000002d4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e2 ( + .I0(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig000002b1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e1 ( + .I0(\blk00000003/sig0000057e ), + .O(\blk00000003/sig000002a7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e0 ( + .I0(\blk00000003/sig0000029f ), + .O(\blk00000003/sig0000029d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004df ( + .I0(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004de ( + .I0(\blk00000003/sig0000026e ), + .O(\blk00000003/sig0000026f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dd ( + .I0(\blk00000003/sig0000026a ), + .O(\blk00000003/sig0000026b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dc ( + .I0(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004db ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig0000025a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004da ( + .I0(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000252 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d9 ( + .I0(\blk00000003/sig00000254 ), + .O(\blk00000003/sig0000024f ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004d8 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d7 ( + .I0(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000229 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d6 ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000572 ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056f ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056c ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000569 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f0 ), + .S(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004fc ), + .S(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f9 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .S(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dd ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dc ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d6 ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c8 ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d1 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ce ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d0 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cb ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bc ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bf ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c4 ) + ); + FDR \blk00000003/blk000004c2 ( + .C(clk), + .D(\blk00000003/sig00000584 ), + .R(ce), + .Q(\blk00000003/sig0000057f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .S(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig0000029f ) + ); + FDR \blk00000003/blk000004bb ( + .C(clk), + .D(\blk00000003/sig00000583 ), + .R(ce), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000274 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig00000271 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000273 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026d ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .R(coef_ld), + .Q(\blk00000003/sig00000267 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(sclr), + .Q(\blk00000003/sig00000263 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025e ), + .R(sclr), + .Q(\blk00000003/sig00000260 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025b ), + .R(sclr), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000257 ), + .R(coef_ld), + .Q(\blk00000003/sig00000258 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig00000255 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000250 ), + .R(coef_ld), + .Q(\blk00000003/sig00000254 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004b0 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000565 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004af ( + .I0(\blk00000003/sig00000574 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000568 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ae ( + .I0(\blk00000003/sig00000575 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ad ( + .I0(\blk00000003/sig00000576 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000004ac ( + .I0(\blk00000003/sig00000577 ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000571 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000004ab ( + .I0(\blk00000003/sig000001df ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000563 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004aa ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000104 ), + .I3(NlwRenamedSig_OI_dout_2[47]), + .O(\blk00000003/sig00000562 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a9 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000561 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a8 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig0000055f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a7 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000560 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a6 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000055e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a5 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000055c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a4 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000055d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a3 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000055b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a2 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000559 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a1 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000055a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a0 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000558 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000556 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000557 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000555 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000553 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000554 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000552 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000499 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000550 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000498 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000551 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000497 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig0000054f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000496 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000054d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000495 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000054e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000494 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000054c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000493 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000054a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000492 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000054b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000491 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000549 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000490 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000547 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000548 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000546 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000544 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000545 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000543 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000541 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000489 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000542 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000488 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000540 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000487 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000053e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000486 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig0000053f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000485 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000053d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000484 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000053b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000483 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000053c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000482 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000053a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000481 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000538 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000480 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000539 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000537 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000535 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000536 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000534 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000533 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[47]), + .O(\blk00000003/sig00000532 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000479 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000530 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000478 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000531 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000477 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig0000052f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000476 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000052d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000475 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig0000052e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000474 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000052c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000473 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000052a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000472 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000052b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000471 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000529 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000470 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000527 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000528 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000526 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000524 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000525 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000523 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000521 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000469 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000522 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000468 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000520 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000467 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig0000051e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000466 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig0000051f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000465 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000051d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000464 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000051b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000463 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000051c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000462 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000051a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000461 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000518 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000460 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000519 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000517 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000515 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000516 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000514 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000512 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000513 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000459 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000511 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000458 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig0000050f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000457 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000510 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000456 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig0000050e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000455 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000050c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000454 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000050d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000453 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000050b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000452 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000509 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000451 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000050a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000450 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000508 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000506 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000507 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000505 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000503 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000504 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000044a ( + .I0(\blk00000003/sig00000501 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000449 ( + .I0(ce), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig00000582 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000448 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/sig000004ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000447 ( + .I0(ce), + .I1(\blk00000003/sig00000581 ), + .O(\blk00000003/sig000004ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000446 ( + .I0(\blk00000003/sig000002cf ), + .I1(\blk00000003/sig000002de ), + .O(\blk00000003/sig000002ca ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000445 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d1 ), + .O(\blk00000003/sig000002c7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000444 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d0 ), + .O(\blk00000003/sig000002cd ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000443 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002c3 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000442 ( + .I0(\blk00000003/sig000002c4 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002be ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000441 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c5 ), + .O(\blk00000003/sig000002c1 ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000440 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c6 ), + .O(\blk00000003/sig000002bb ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000043f ( + .I0(sclr), + .I1(\blk00000003/sig0000057f ), + .O(\blk00000003/sig000002b8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000043e ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000043d ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b0 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000043c ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002a9 ), + .O(\blk00000003/sig000002ae ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000043b ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002ab ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043a ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002a4 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000439 ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000438 ( + .I0(\blk00000003/sig000002a0 ), + .I1(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000437 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000297 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000436 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig0000023c ), + .O(\blk00000003/sig00000294 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000435 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000292 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000434 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000024a ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000433 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000432 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000286 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000431 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000284 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000430 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig00000244 ), + .I2(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000042f ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027b ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042e ( + .I0(\blk00000003/sig0000023e ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig0000024a ), + .O(\blk00000003/sig0000027d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000042d ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000276 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042c ( + .I0(coef_we), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000268 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000042b ( + .I0(\blk00000003/sig00000267 ), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .I3(coef_we), + .O(\blk00000003/sig00000265 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000042a ( + .I0(\blk00000003/sig00000263 ), + .I1(\blk00000003/sig000001c4 ), + .O(\blk00000003/sig00000261 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000429 ( + .I0(\blk00000003/sig00000258 ), + .I1(coef_we), + .O(\blk00000003/sig00000256 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000428 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000243 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000427 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000426 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(coef_ld), + .O(\blk00000003/sig0000024b ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000425 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022e ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000424 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000423 ( + .I0(coef_we), + .I1(\blk00000003/sig00000238 ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig0000021f ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000422 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(\blk00000003/sig0000022c ), + .I3(\blk00000003/sig00000224 ), + .I4(coef_ld), + .O(\blk00000003/sig00000237 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000421 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000420 ( + .I0(nd), + .I1(\blk00000003/sig000002a2 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig000001e5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000041e ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig0000057c ), + .O(\blk00000003/sig000000bf ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000041d ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000001e0 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000041c ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001cb ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000041b ( + .I0(\blk00000003/sig0000029f ), + .I1(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000001c8 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk0000041a ( + .I0(\blk00000003/sig0000025f ), + .I1(\blk00000003/sig00000260 ), + .I2(\blk00000003/sig00000263 ), + .O(\blk00000003/sig000001c5 ) + ); + LUT5 #( + .INIT ( 32'h00008000 )) + \blk00000003/blk00000419 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig00000574 ), + .I2(\blk00000003/sig00000575 ), + .I3(\blk00000003/sig00000576 ), + .I4(\blk00000003/sig00000577 ), + .O(\blk00000003/sig000000c1 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000418 ( + .I0(\blk00000003/sig000001d8 ), + .I1(\blk00000003/sig000001c4 ), + .I2(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000417 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001dd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000416 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000000b3 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000415 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig000000b1 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000414 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001da ), + .I3(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000413 ( + .I0(\blk00000003/sig000001c4 ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .I4(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000412 ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig0000057b ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000411 ( + .I0(\blk00000003/sig000001e6 ), + .I1(\blk00000003/sig000001d6 ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000410 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001db ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000040f ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig0000057a ), + .I3(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000af ) + ); + MUXCY \blk00000003/blk0000040e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000578 ), + .O(\blk00000003/sig00000570 ) + ); + MUXCY_L \blk00000003/blk0000040d ( + .CI(\blk00000003/sig00000570 ), + .DI(\blk00000003/sig00000577 ), + .S(\blk00000003/sig00000571 ), + .LO(\blk00000003/sig0000056d ) + ); + MUXCY_L \blk00000003/blk0000040c ( + .CI(\blk00000003/sig0000056d ), + .DI(\blk00000003/sig00000576 ), + .S(\blk00000003/sig0000056e ), + .LO(\blk00000003/sig0000056a ) + ); + MUXCY_L \blk00000003/blk0000040b ( + .CI(\blk00000003/sig0000056a ), + .DI(\blk00000003/sig00000575 ), + .S(\blk00000003/sig0000056b ), + .LO(\blk00000003/sig00000567 ) + ); + MUXCY_L \blk00000003/blk0000040a ( + .CI(\blk00000003/sig00000567 ), + .DI(\blk00000003/sig00000574 ), + .S(\blk00000003/sig00000568 ), + .LO(\blk00000003/sig00000564 ) + ); + MUXCY_D \blk00000003/blk00000409 ( + .CI(\blk00000003/sig00000564 ), + .DI(\blk00000003/sig00000573 ), + .S(\blk00000003/sig00000565 ), + .O(\NLW_blk00000003/blk00000409_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000409_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000408 ( + .CI(\blk00000003/sig00000570 ), + .LI(\blk00000003/sig00000571 ), + .O(\blk00000003/sig00000572 ) + ); + XORCY \blk00000003/blk00000407 ( + .CI(\blk00000003/sig0000056d ), + .LI(\blk00000003/sig0000056e ), + .O(\blk00000003/sig0000056f ) + ); + XORCY \blk00000003/blk00000406 ( + .CI(\blk00000003/sig0000056a ), + .LI(\blk00000003/sig0000056b ), + .O(\blk00000003/sig0000056c ) + ); + XORCY \blk00000003/blk00000405 ( + .CI(\blk00000003/sig00000567 ), + .LI(\blk00000003/sig00000568 ), + .O(\blk00000003/sig00000569 ) + ); + XORCY \blk00000003/blk00000404 ( + .CI(\blk00000003/sig00000564 ), + .LI(\blk00000003/sig00000565 ), + .O(\blk00000003/sig00000566 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000556 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000555 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000554 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000553 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000552 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000551 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000550 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000549 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000548 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000547 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000546 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000545 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000544 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000543 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000542 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000541 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000540 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000537 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000536 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000535 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000534 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000533 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000532 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000531 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000530 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000529 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000528 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000527 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000519 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000518 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000517 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000516 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000515 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000514 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000513 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000512 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000511 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000510 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000504 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000503 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig000001df ) + ); + MUXCY_L \blk00000003/blk000003a1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000501 ), + .S(\blk00000003/sig000004ef ), + .LO(\blk00000003/sig000004fa ) + ); + MUXCY_L \blk00000003/blk000003a0 ( + .CI(\blk00000003/sig000004fa ), + .DI(\blk00000003/sig00000500 ), + .S(\blk00000003/sig000004fb ), + .LO(\blk00000003/sig000004f7 ) + ); + MUXCY_L \blk00000003/blk0000039f ( + .CI(\blk00000003/sig000004f7 ), + .DI(\blk00000003/sig000004ff ), + .S(\blk00000003/sig000004f8 ), + .LO(\blk00000003/sig000004f4 ) + ); + MUXCY_L \blk00000003/blk0000039e ( + .CI(\blk00000003/sig000004f4 ), + .DI(\blk00000003/sig000004fe ), + .S(\blk00000003/sig000004f5 ), + .LO(\blk00000003/sig000004f1 ) + ); + MUXCY_D \blk00000003/blk0000039d ( + .CI(\blk00000003/sig000004f1 ), + .DI(\blk00000003/sig000004fd ), + .S(\blk00000003/sig000004f2 ), + .O(\NLW_blk00000003/blk0000039d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000039d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000039c ( + .CI(\blk00000003/sig000004fa ), + .LI(\blk00000003/sig000004fb ), + .O(\blk00000003/sig000004fc ) + ); + XORCY \blk00000003/blk0000039b ( + .CI(\blk00000003/sig000004f7 ), + .LI(\blk00000003/sig000004f8 ), + .O(\blk00000003/sig000004f9 ) + ); + XORCY \blk00000003/blk0000039a ( + .CI(\blk00000003/sig000004f4 ), + .LI(\blk00000003/sig000004f5 ), + .O(\blk00000003/sig000004f6 ) + ); + XORCY \blk00000003/blk00000399 ( + .CI(\blk00000003/sig000004f1 ), + .LI(\blk00000003/sig000004f2 ), + .O(\blk00000003/sig000004f3 ) + ); + XORCY \blk00000003/blk00000398 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000004ef ), + .O(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig00000450 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig0000044f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig0000044e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig0000044d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig0000044c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d8 ), + .R(sclr), + .Q(\blk00000003/sig0000044b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d7 ), + .R(sclr), + .Q(\blk00000003/sig0000044a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d6 ), + .R(sclr), + .Q(\blk00000003/sig00000449 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d5 ), + .R(sclr), + .Q(\blk00000003/sig00000448 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d4 ), + .R(sclr), + .Q(\blk00000003/sig00000447 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d3 ), + .R(sclr), + .Q(\blk00000003/sig00000446 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000445 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000444 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000443 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000442 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000441 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000440 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig0000043f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig0000043e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig0000043d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig0000043c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000043b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000043a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig00000439 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040d ), + .R(sclr), + .Q(\blk00000003/sig00000468 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040c ), + .R(sclr), + .Q(\blk00000003/sig00000467 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040b ), + .R(sclr), + .Q(\blk00000003/sig00000466 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040a ), + .R(sclr), + .Q(\blk00000003/sig00000465 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000409 ), + .R(sclr), + .Q(\blk00000003/sig00000464 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig00000463 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig00000462 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig00000461 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig00000460 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000045f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig0000045e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig0000045d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig0000045c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig0000045b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig0000045a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000459 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000458 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000457 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000456 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000345 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000455 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000344 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig00000454 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000343 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig00000453 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000342 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig00000452 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000341 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig00000451 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000340 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig00000498 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig00000497 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000496 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000495 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000494 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig00000493 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig00000492 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000339 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig00000491 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000338 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig00000490 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000337 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000048f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000336 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig0000048e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000335 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig0000048d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000334 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig0000048c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000333 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig0000048b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000332 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig0000048a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000331 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000489 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000330 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000488 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000487 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000486 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000485 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig00000484 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig00000483 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig00000482 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000329 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig00000481 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000328 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig000004c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig000004c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000326 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig000004c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000325 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig000004c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000324 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig000004c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000323 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig000004c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000322 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig000004c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000321 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig000004c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000320 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig000004c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig000004bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig000004be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041a ), + .R(sclr), + .Q(\blk00000003/sig000004bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000419 ), + .R(sclr), + .Q(\blk00000003/sig000004bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000418 ), + .R(sclr), + .Q(\blk00000003/sig000004bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000417 ), + .R(sclr), + .Q(\blk00000003/sig000004ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000319 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000416 ), + .R(sclr), + .Q(\blk00000003/sig000004b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000318 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000415 ), + .R(sclr), + .Q(\blk00000003/sig000004b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000317 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000414 ), + .R(sclr), + .Q(\blk00000003/sig000004b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000316 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000413 ), + .R(sclr), + .Q(\blk00000003/sig000004b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000412 ), + .R(sclr), + .Q(\blk00000003/sig000004b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000314 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000411 ), + .R(sclr), + .Q(\blk00000003/sig000004b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000313 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000410 ), + .R(sclr), + .Q(\blk00000003/sig000004b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000312 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040f ), + .R(sclr), + .Q(\blk00000003/sig000004b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000311 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040e ), + .R(sclr), + .Q(\blk00000003/sig000004b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d1 ), + .R(sclr), + .Q(\blk00000003/sig00000438 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d0 ), + .R(sclr), + .Q(\blk00000003/sig00000437 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cf ), + .R(sclr), + .Q(\blk00000003/sig00000436 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000434 ), + .R(sclr), + .Q(\blk00000003/sig00000435 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d3 ), + .R(sclr), + .Q(\blk00000003/sig00000433 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d7 ), + .R(sclr), + .Q(\blk00000003/sig00000432 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002da ), + .R(sclr), + .Q(\blk00000003/sig00000431 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e1 ), + .R(sclr), + .Q(\blk00000003/sig00000430 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000042f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c6 ), + .R(sclr), + .Q(\blk00000003/sig0000042d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c5 ), + .R(sclr), + .Q(\blk00000003/sig0000042c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig0000042b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000042a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000275 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000429 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000271 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000428 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000427 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000426 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000107 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003f6 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , +\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , +\blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , +\blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , +\blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 }), + .PCOUT({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000106 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003c6 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , +\blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , +\blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , +\blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , +\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000105 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000354 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , +\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , +\blk00000003/sig00000370 , \blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , +\blk00000003/sig00000375 , \blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , +\blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , +\blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .PCOUT({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000104 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002f4 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , +\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , +\blk00000003/sig00000310 , \blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , +\blk00000003/sig00000315 , \blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , +\blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , +\blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 }), + .PCOUT({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000002d2 ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig000002d9 ), + .LI(\blk00000003/sig000002db ), + .O(\blk00000003/sig000002dd ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig000002d5 ), + .LI(\blk00000003/sig000002d8 ), + .O(\blk00000003/sig000002dc ) + ); + MUXCY_D \blk00000003/blk000000fe ( + .CI(\blk00000003/sig000002d9 ), + .DI(\blk00000003/sig000002da ), + .S(\blk00000003/sig000002db ), + .O(\NLW_blk00000003/blk000000fe_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fe_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000fd ( + .CI(\blk00000003/sig000002d5 ), + .DI(\blk00000003/sig000002d7 ), + .S(\blk00000003/sig000002d8 ), + .LO(\blk00000003/sig000002d9 ) + ); + XORCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig000002d2 ), + .LI(\blk00000003/sig000002d4 ), + .O(\blk00000003/sig000002d6 ) + ); + MUXCY_L \blk00000003/blk000000fb ( + .CI(\blk00000003/sig000002d2 ), + .DI(\blk00000003/sig000002d3 ), + .S(\blk00000003/sig000002d4 ), + .LO(\blk00000003/sig000002d5 ) + ); + MUXCY_L \blk00000003/blk000000fa ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002d1 ), + .S(\blk00000003/sig000002c7 ), + .LO(\blk00000003/sig000002cc ) + ); + MUXCY_L \blk00000003/blk000000f9 ( + .CI(\blk00000003/sig000002cc ), + .DI(\blk00000003/sig000002d0 ), + .S(\blk00000003/sig000002cd ), + .LO(\blk00000003/sig000002c9 ) + ); + MUXCY_D \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig000002c9 ), + .DI(\blk00000003/sig000002cf ), + .S(\blk00000003/sig000002ca ), + .O(\NLW_blk00000003/blk000000f8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig000002cc ), + .LI(\blk00000003/sig000002cd ), + .O(\blk00000003/sig000002ce ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig000002c9 ), + .LI(\blk00000003/sig000002ca ), + .O(\blk00000003/sig000002cb ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002c7 ), + .O(\blk00000003/sig000002c8 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig000002ba ), + .DI(\blk00000003/sig000002c6 ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002c0 ) + ); + MUXCY_L \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002c0 ), + .DI(\blk00000003/sig000002c5 ), + .S(\blk00000003/sig000002c1 ), + .LO(\blk00000003/sig000002bd ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bd ), + .DI(\blk00000003/sig000002c4 ), + .S(\blk00000003/sig000002be ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002c3 ), + .O(\blk00000003/sig000002ba ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002c0 ), + .LI(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002c2 ) + ); + XORCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig000002bd ), + .LI(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002ba ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bc ) + ); + FDE \blk00000003/blk000000ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .Q(\blk00000003/sig000002b9 ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b1 ), + .LO(\blk00000003/sig000002b3 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002b3 ), + .DI(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002b4 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002b3 ), + .LI(\blk00000003/sig000002b4 ), + .O(\blk00000003/sig000002b5 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002b2 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002aa ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig000002ab ), + .LO(\blk00000003/sig000002ad ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002ad ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig000002ae ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig000002aa ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig000002ad ), + .LI(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002af ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002aa ), + .LI(\blk00000003/sig000002ab ), + .O(\blk00000003/sig000002ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig000002a5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a7 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\blk00000003/sig000002a8 ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a3 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig000002a3 ), + .DI(\blk00000003/sig000002a2 ), + .S(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ), + .LO(\blk00000003/sig000002a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + MUXCY_L \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000dd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000298 ), + .S(\blk00000003/sig00000299 ), + .O(\blk00000003/sig00000295 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000295 ), + .DI(\blk00000003/sig00000296 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000293 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000293 ), + .DI(\blk00000003/sig00000289 ), + .S(\blk00000003/sig00000294 ), + .O(\blk00000003/sig00000290 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000292 ), + .O(\blk00000003/sig0000028e ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028e ), + .DI(\blk00000003/sig00000246 ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000028c ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000028d ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000028a ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000028b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000279 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000289 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000285 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000285 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000283 ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000283 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000282 ), + .O(\blk00000003/sig0000027e ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027e ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027a ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000027c ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027d ), + .O(\NLW_blk00000003/blk000000ca_O_UNCONNECTED ), + .LO(\blk00000003/sig00000278 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig0000027a ), + .DI(\blk00000003/sig0000023b ), + .S(\blk00000003/sig0000027b ), + .O(\blk00000003/sig0000027c ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000278 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig00000279 ) + ); + FDE \blk00000003/blk000000c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000276 ), + .Q(\blk00000003/sig00000277 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000275 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000269 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000270 ), + .LI(\blk00000003/sig00000272 ), + .O(\blk00000003/sig00000274 ) + ); + XORCY \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026c ), + .LI(\blk00000003/sig0000026f ), + .O(\blk00000003/sig00000273 ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000271 ), + .S(\blk00000003/sig00000272 ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c2_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig0000026c ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .LO(\blk00000003/sig00000270 ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000269 ), + .LI(\blk00000003/sig0000026b ), + .O(\blk00000003/sig0000026d ) + ); + MUXCY_L \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig0000026a ), + .S(\blk00000003/sig0000026b ), + .LO(\blk00000003/sig0000026c ) + ); + MUXCY \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000264 ) + ); + MUXCY_D \blk00000003/blk000000bd ( + .CI(\blk00000003/sig00000264 ), + .DI(\blk00000003/sig00000267 ), + .S(\blk00000003/sig00000265 ), + .O(\NLW_blk00000003/blk000000bd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig00000264 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000263 ), + .S(\blk00000003/sig00000261 ), + .LO(\blk00000003/sig0000025c ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000262 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025c ), + .DI(\blk00000003/sig00000260 ), + .S(\blk00000003/sig0000025d ), + .LO(\blk00000003/sig00000259 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000259 ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig0000025a ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig0000025c ), + .LI(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000259 ), + .LI(\blk00000003/sig0000025a ), + .O(\blk00000003/sig0000025b ) + ); + MUXCY_L \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000258 ), + .S(\blk00000003/sig00000256 ), + .LO(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig00000255 ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig0000024e ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024e ), + .DI(\blk00000003/sig00000254 ), + .S(\blk00000003/sig0000024f ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b0 ( + .CI(\blk00000003/sig0000024e ), + .LI(\blk00000003/sig0000024f ), + .O(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000233 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig00000246 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000240 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig0000023a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\blk00000003/sig0000022c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022a ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk0000009e_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000226 ), + .R(coef_ld), + .Q(\blk00000003/sig00000224 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000232 ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022e ), + .O(\blk00000003/sig0000022b ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig0000022c ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000228 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022a ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ), + .LO(\NLW_blk00000003/blk00000093_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000223 ), + .DI(\blk00000003/sig00000224 ), + .S(\blk00000003/sig00000225 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig00000226 ) + ); + XORCY \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021c ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000090_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk0000008f ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk0000008f_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e7 ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000028 ( + .C(clk), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(\blk00000003/sig000001e0 ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDRE \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(\blk00000003/sig000001e0 ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .S(sclr), + .Q(\blk00000003/sig000001de ) + ); + FDRE \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .R(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ca ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c6 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c0 ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000014 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bb ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000014_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000013 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c9 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000001cb ), + .O(\blk00000003/sig000001cc ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000001c7 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c8 ), + .O(\blk00000003/sig000001c9 ), + .LO(\blk00000003/sig000001ca ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000001c4 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c5 ), + .O(\NLW_blk00000003/blk00000010_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c6 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000f ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , +\blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab }), + .A({\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , +\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , +\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 }), + .PCOUT({\NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000e ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , +\blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , +\blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , +\blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , +\blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , +\blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , +\blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , +\blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , +\blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c1 ), + .O(\blk00000003/sig000000bd ), + .LO(\NLW_blk00000003/blk0000000d_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000b5 ), + .LO(\blk00000003/sig000000c0 ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000bb ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000b8 ), + .DI(\blk00000003/sig000000b9 ), + .S(\blk00000003/sig000000ba ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bb ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig000000b5 ), + .DI(\blk00000003/sig000000b6 ), + .S(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b3 ), + .Q(\blk00000003/sig000000b4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000007 ( + .C(clk), + .D(\blk00000003/sig000000b1 ), + .Q(\blk00000003/sig000000b2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .D(\blk00000003/sig000000af ), + .Q(\blk00000003/sig000000b0 ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ae ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002a/blk0000008c ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002a/sig000006fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fc ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fb ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fa ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f9 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f8 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f7 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f6 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f5 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f4 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f3 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f2 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f1 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f0 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ef ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ee ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ed ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ec ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006eb ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ea ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e9 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e8 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e7 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e6 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e5 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e4 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e3 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e2 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e1 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e0 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006df ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006de ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dd ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dc ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006db ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006da ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d9 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d8 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d7 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d6 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d5 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d4 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d3 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d2 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d1 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d0 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cf ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ce ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cd ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002a/blk0000002b ( + .G(\blk00000003/blk0000002a/sig000006cc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000119/blk0000014b ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk00000119/sig0000074d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000014a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f5 ), + .Q(\blk00000003/blk00000119/sig0000074b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000149 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f6 ), + .Q(\blk00000003/blk00000119/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000148 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f4 ), + .Q(\blk00000003/blk00000119/sig0000074c ), + .Q15(\NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000147 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f8 ), + .Q(\blk00000003/blk00000119/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000146 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f9 ), + .Q(\blk00000003/blk00000119/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000145 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f7 ), + .Q(\blk00000003/blk00000119/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000144 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fb ), + .Q(\blk00000003/blk00000119/sig00000745 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000143 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fc ), + .Q(\blk00000003/blk00000119/sig00000744 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000142 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fa ), + .Q(\blk00000003/blk00000119/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000141 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fe ), + .Q(\blk00000003/blk00000119/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000140 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002ff ), + .Q(\blk00000003/blk00000119/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fd ), + .Q(\blk00000003/blk00000119/sig00000743 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000301 ), + .Q(\blk00000003/blk00000119/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000302 ), + .Q(\blk00000003/blk00000119/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000300 ), + .Q(\blk00000003/blk00000119/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000304 ), + .Q(\blk00000003/blk00000119/sig0000073c ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000305 ), + .Q(\blk00000003/blk00000119/sig0000073b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000139 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000303 ), + .Q(\blk00000003/blk00000119/sig0000073d ), + .Q15(\NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000138 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000307 ), + .Q(\blk00000003/blk00000119/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000137 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000308 ), + .Q(\blk00000003/blk00000119/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000136 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000306 ), + .Q(\blk00000003/blk00000119/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000135 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030a ), + .Q(\blk00000003/blk00000119/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000134 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030b ), + .Q(\blk00000003/blk00000119/sig00000735 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000133 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/blk00000119/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074c ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074b ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074a ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000749 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000748 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000747 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000746 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000745 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000744 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000743 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000742 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000741 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000740 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073f ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073e ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073d ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073c ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073b ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073a ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000739 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000738 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000737 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000736 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000735 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk00000119/blk0000011a ( + .G(\blk00000003/blk00000119/sig00000734 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014c/blk0000017e ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk0000014c/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043a ), + .Q(\blk00000003/blk0000014c/sig0000079b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043b ), + .Q(\blk00000003/blk0000014c/sig0000079a ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000439 ), + .Q(\blk00000003/blk0000014c/sig0000079c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk0000014c/sig00000798 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000179 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk0000014c/sig00000797 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000178 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043c ), + .Q(\blk00000003/blk0000014c/sig00000799 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000177 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk0000014c/sig00000795 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000176 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk0000014c/sig00000794 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000175 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk0000014c/sig00000796 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000174 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk0000014c/sig00000792 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000173 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk0000014c/sig00000791 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000172 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk0000014c/sig00000793 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000171 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk0000014c/sig0000078f ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000170 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk0000014c/sig0000078e ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016f ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk0000014c/sig00000790 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016e ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk0000014c/sig0000078c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk0000014c/sig0000078b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk0000014c/sig0000078d ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk0000014c/sig00000789 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044d ), + .Q(\blk00000003/blk0000014c/sig00000788 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000169 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk0000014c/sig0000078a ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000168 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044f ), + .Q(\blk00000003/blk0000014c/sig00000786 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000167 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000450 ), + .Q(\blk00000003/blk0000014c/sig00000785 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000166 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044e ), + .Q(\blk00000003/blk0000014c/sig00000787 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079c ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079b ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079a ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000799 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000798 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000797 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000796 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000795 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000794 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000793 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000792 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000791 ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000790 ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078f ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078e ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078d ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078c ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078b ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078a ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000789 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000788 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000787 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000786 ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000785 ), + .Q(\blk00000003/sig000003f5 ) + ); + GND \blk00000003/blk0000014c/blk0000014d ( + .G(\blk00000003/blk0000014c/sig00000784 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017f/blk000001b1 ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk0000017f/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001b0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000355 ), + .Q(\blk00000003/blk0000017f/sig000007eb ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001af ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000356 ), + .Q(\blk00000003/blk0000017f/sig000007ea ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ae ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000354 ), + .Q(\blk00000003/blk0000017f/sig000007ec ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ad ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000358 ), + .Q(\blk00000003/blk0000017f/sig000007e8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ac ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000359 ), + .Q(\blk00000003/blk0000017f/sig000007e7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ab ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000357 ), + .Q(\blk00000003/blk0000017f/sig000007e9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001aa ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035b ), + .Q(\blk00000003/blk0000017f/sig000007e5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a9 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035c ), + .Q(\blk00000003/blk0000017f/sig000007e4 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a8 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035a ), + .Q(\blk00000003/blk0000017f/sig000007e6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a7 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035e ), + .Q(\blk00000003/blk0000017f/sig000007e2 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a6 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035f ), + .Q(\blk00000003/blk0000017f/sig000007e1 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a5 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035d ), + .Q(\blk00000003/blk0000017f/sig000007e3 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a4 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000361 ), + .Q(\blk00000003/blk0000017f/sig000007df ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a3 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000362 ), + .Q(\blk00000003/blk0000017f/sig000007de ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a2 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000360 ), + .Q(\blk00000003/blk0000017f/sig000007e0 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a1 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000364 ), + .Q(\blk00000003/blk0000017f/sig000007dc ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000365 ), + .Q(\blk00000003/blk0000017f/sig000007db ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000363 ), + .Q(\blk00000003/blk0000017f/sig000007dd ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000367 ), + .Q(\blk00000003/blk0000017f/sig000007d9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000368 ), + .Q(\blk00000003/blk0000017f/sig000007d8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000366 ), + .Q(\blk00000003/blk0000017f/sig000007da ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036a ), + .Q(\blk00000003/blk0000017f/sig000007d6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036b ), + .Q(\blk00000003/blk0000017f/sig000007d5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk00000199 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000369 ), + .Q(\blk00000003/blk0000017f/sig000007d7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ec ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007eb ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ea ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e9 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e8 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e7 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e6 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e5 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e4 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e3 ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e2 ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e1 ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e0 ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007df ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007de ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dd ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dc ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007db ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007da ), + .Q(\blk00000003/sig00000408 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d9 ), + .Q(\blk00000003/sig00000409 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d8 ), + .Q(\blk00000003/sig0000040a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d7 ), + .Q(\blk00000003/sig0000040b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d6 ), + .Q(\blk00000003/sig0000040c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d5 ), + .Q(\blk00000003/sig0000040d ) + ); + GND \blk00000003/blk0000017f/blk00000180 ( + .G(\blk00000003/blk0000017f/sig000007d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b2/blk000001e4 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk000001b2/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000452 ), + .Q(\blk00000003/blk000001b2/sig0000083b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000453 ), + .Q(\blk00000003/blk000001b2/sig0000083a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000451 ), + .Q(\blk00000003/blk000001b2/sig0000083c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000455 ), + .Q(\blk00000003/blk000001b2/sig00000838 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001df ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000456 ), + .Q(\blk00000003/blk000001b2/sig00000837 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001de ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000454 ), + .Q(\blk00000003/blk000001b2/sig00000839 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000458 ), + .Q(\blk00000003/blk000001b2/sig00000835 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000459 ), + .Q(\blk00000003/blk000001b2/sig00000834 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001db ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000457 ), + .Q(\blk00000003/blk000001b2/sig00000836 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001da ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045b ), + .Q(\blk00000003/blk000001b2/sig00000832 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d9 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045c ), + .Q(\blk00000003/blk000001b2/sig00000831 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d8 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045a ), + .Q(\blk00000003/blk000001b2/sig00000833 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d7 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk000001b2/sig0000082f ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d6 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk000001b2/sig0000082e ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d5 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk000001b2/sig00000830 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d4 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk000001b2/sig0000082c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk000001b2/sig0000082b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk000001b2/sig0000082d ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk000001b2/sig00000829 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk000001b2/sig00000828 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cf ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk000001b2/sig0000082a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001ce ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk000001b2/sig00000826 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk000001b2/sig00000825 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk000001b2/sig00000827 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083c ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083b ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083a ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000839 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000838 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000837 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000836 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000835 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000834 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000833 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000832 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000831 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000830 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082f ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082e ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082d ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082c ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082b ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082a ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000829 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000828 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000827 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000826 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000825 ), + .Q(\blk00000003/sig00000425 ) + ); + GND \blk00000003/blk000001b2/blk000001b3 ( + .G(\blk00000003/blk000001b2/sig00000824 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e5/blk00000217 ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk000001e5/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000216 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk000001e5/sig0000088b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000215 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk000001e5/sig0000088a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000214 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk000001e5/sig0000088c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000213 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk000001e5/sig00000888 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000212 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000001e5/sig00000887 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000211 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk000001e5/sig00000889 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000210 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000001e5/sig00000885 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000001e5/sig00000884 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000001e5/sig00000886 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000001e5/sig00000882 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000001e5/sig00000881 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000001e5/sig00000883 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000001e5/sig0000087f ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000209 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000001e5/sig0000087e ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000208 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000001e5/sig00000880 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000207 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000001e5/sig0000087c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000206 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000001e5/sig0000087b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000205 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000001e5/sig0000087d ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000204 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000001e5/sig00000879 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000203 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000001e5/sig00000878 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000202 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000001e5/sig0000087a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000201 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk000001e5/sig00000876 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000200 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk000001e5/sig00000875 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk000001ff ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk000001e5/sig00000877 ), + .Q15(\NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088c ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088b ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088a ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000889 ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000888 ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000887 ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000886 ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000885 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000884 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000883 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000882 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000881 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000880 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087f ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087e ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087d ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087c ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087b ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087a ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000879 ), + .Q(\blk00000003/sig00000307 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000878 ), + .Q(\blk00000003/sig00000308 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000877 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000876 ), + .Q(\blk00000003/sig0000030a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000875 ), + .Q(\blk00000003/sig0000030b ) + ); + GND \blk00000003/blk000001e5/blk000001e6 ( + .G(\blk00000003/blk000001e5/sig00000874 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000218/blk0000024a ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk00000218/sig000008dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000249 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000218/sig000008db ), + .Q15(\NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000248 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000218/sig000008da ), + .Q15(\NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000247 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000218/sig000008dc ), + .Q15(\NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000246 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000218/sig000008d8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000245 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000218/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000244 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000218/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000243 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000218/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000242 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000218/sig000008d4 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000241 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000218/sig000008d6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000240 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000218/sig000008d2 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000218/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000218/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000218/sig000008cf ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000218/sig000008ce ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000218/sig000008d0 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000218/sig000008cc ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000239 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000218/sig000008cb ), + .Q15(\NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000238 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000218/sig000008cd ), + .Q15(\NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000237 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000218/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000236 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000218/sig000008c8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000235 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000218/sig000008ca ), + .Q15(\NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000234 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000218/sig000008c6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000233 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000218/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000232 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000218/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008dc ), + .Q(\blk00000003/sig0000030c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008db ), + .Q(\blk00000003/sig0000030d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008da ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d9 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d8 ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d7 ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d6 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d5 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d4 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d3 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d2 ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d1 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cf ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ce ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cd ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cc ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cb ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ca ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c9 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c8 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c7 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c6 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c5 ), + .Q(\blk00000003/sig00000323 ) + ); + GND \blk00000003/blk00000218/blk00000219 ( + .G(\blk00000003/blk00000218/sig000008c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000024b/blk0000027d ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk0000024b/sig0000092d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk0000024b/sig0000092b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk0000024b/sig0000092a ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk0000024b/sig0000092c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000279 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049d ), + .Q(\blk00000003/blk0000024b/sig00000928 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000278 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049e ), + .Q(\blk00000003/blk0000024b/sig00000927 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000277 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk0000024b/sig00000929 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000276 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a0 ), + .Q(\blk00000003/blk0000024b/sig00000925 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000275 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a1 ), + .Q(\blk00000003/blk0000024b/sig00000924 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000274 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049f ), + .Q(\blk00000003/blk0000024b/sig00000926 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000273 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a3 ), + .Q(\blk00000003/blk0000024b/sig00000922 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000272 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a4 ), + .Q(\blk00000003/blk0000024b/sig00000921 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000271 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a2 ), + .Q(\blk00000003/blk0000024b/sig00000923 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000270 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a6 ), + .Q(\blk00000003/blk0000024b/sig0000091f ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a7 ), + .Q(\blk00000003/blk0000024b/sig0000091e ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a5 ), + .Q(\blk00000003/blk0000024b/sig00000920 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a9 ), + .Q(\blk00000003/blk0000024b/sig0000091c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004aa ), + .Q(\blk00000003/blk0000024b/sig0000091b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a8 ), + .Q(\blk00000003/blk0000024b/sig0000091d ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000024b/sig00000919 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000269 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000024b/sig00000918 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000268 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000024b/sig0000091a ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000267 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000024b/sig00000916 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000266 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000024b/sig00000915 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000265 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000024b/sig00000917 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092c ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092b ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092a ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000929 ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000928 ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000927 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000926 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000925 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000924 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000923 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000922 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000921 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000920 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091f ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091e ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091d ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091c ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091b ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091a ), + .Q(\blk00000003/sig00000366 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000919 ), + .Q(\blk00000003/sig00000367 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000918 ), + .Q(\blk00000003/sig00000368 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000917 ), + .Q(\blk00000003/sig00000369 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000916 ), + .Q(\blk00000003/sig0000036a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000915 ), + .Q(\blk00000003/sig0000036b ) + ); + GND \blk00000003/blk0000024b/blk0000024c ( + .G(\blk00000003/blk0000024b/sig00000914 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027e/blk000002b0 ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk0000027e/sig0000097d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002af ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000027e/sig0000097b ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ae ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000027e/sig0000097a ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ad ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000027e/sig0000097c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ac ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000027e/sig00000978 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ab ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000027e/sig00000977 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002aa ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000027e/sig00000979 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a9 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000027e/sig00000975 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a8 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000027e/sig00000974 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a7 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000027e/sig00000976 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a6 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000027e/sig00000972 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a5 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000027e/sig00000971 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a4 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000027e/sig00000973 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a3 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000027e/sig0000096f ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a2 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000027e/sig0000096e ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a1 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000027e/sig00000970 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a0 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000027e/sig0000096c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000027e/sig0000096b ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000027e/sig0000096d ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c4 ), + .Q(\blk00000003/blk0000027e/sig00000969 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c5 ), + .Q(\blk00000003/blk0000027e/sig00000968 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c3 ), + .Q(\blk00000003/blk0000027e/sig0000096a ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c7 ), + .Q(\blk00000003/blk0000027e/sig00000966 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000299 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c8 ), + .Q(\blk00000003/blk0000027e/sig00000965 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000298 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c6 ), + .Q(\blk00000003/blk0000027e/sig00000967 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097c ), + .Q(\blk00000003/sig0000036c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097b ), + .Q(\blk00000003/sig0000036d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097a ), + .Q(\blk00000003/sig0000036e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000979 ), + .Q(\blk00000003/sig0000036f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000978 ), + .Q(\blk00000003/sig00000370 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000977 ), + .Q(\blk00000003/sig00000371 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000976 ), + .Q(\blk00000003/sig00000372 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000975 ), + .Q(\blk00000003/sig00000373 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000974 ), + .Q(\blk00000003/sig00000374 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000973 ), + .Q(\blk00000003/sig00000375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000972 ), + .Q(\blk00000003/sig00000376 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000971 ), + .Q(\blk00000003/sig00000377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000970 ), + .Q(\blk00000003/sig00000378 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096f ), + .Q(\blk00000003/sig00000379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096e ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096d ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096c ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096b ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096a ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000969 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000968 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000967 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000966 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000965 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk0000027e/blk0000027f ( + .G(\blk00000003/blk0000027e/sig00000964 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002e9 ( + .I0(ce), + .I1(\blk00000003/sig00000234 ), + .O(\blk00000003/blk000002b1/sig000009e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d1 ), + .DPO(\blk00000003/blk000002b1/sig000009e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d0 ), + .DPO(\blk00000003/blk000002b1/sig000009e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e6 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cf ), + .DPO(\blk00000003/blk000002b1/sig000009e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e5 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ce ), + .DPO(\blk00000003/blk000002b1/sig000009e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e4 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cd ), + .DPO(\blk00000003/blk000002b1/sig000009df ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e3 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cc ), + .DPO(\blk00000003/blk000002b1/sig000009de ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002b1/blk000002e2 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ca ), + .DPO(\blk00000003/blk000002b1/sig000009dc ) + ); + RAM32X1D #( + .INIT ( 32'h000000E5 )) + \blk00000003/blk000002b1/blk000002e1 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c9 ), + .DPO(\blk00000003/blk000002b1/sig000009db ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e0 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cb ), + .DPO(\blk00000003/blk000002b1/sig000009dd ) + ); + RAM32X1D #( + .INIT ( 32'h000000BD )) + \blk00000003/blk000002b1/blk000002df ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c8 ), + .DPO(\blk00000003/blk000002b1/sig000009da ) + ); + RAM32X1D #( + .INIT ( 32'h000000F1 )) + \blk00000003/blk000002b1/blk000002de ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c7 ), + .DPO(\blk00000003/blk000002b1/sig000009d9 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000002b1/blk000002dd ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c6 ), + .DPO(\blk00000003/blk000002b1/sig000009d8 ) + ); + RAM32X1D #( + .INIT ( 32'h000000DC )) + \blk00000003/blk000002b1/blk000002dc ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c5 ), + .DPO(\blk00000003/blk000002b1/sig000009d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000057 )) + \blk00000003/blk000002b1/blk000002db ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c4 ), + .DPO(\blk00000003/blk000002b1/sig000009d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000037 )) + \blk00000003/blk000002b1/blk000002da ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c3 ), + .DPO(\blk00000003/blk000002b1/sig000009d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000072 )) + \blk00000003/blk000002b1/blk000002d9 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c1 ), + .DPO(\blk00000003/blk000002b1/sig000009d3 ) + ); + RAM32X1D #( + .INIT ( 32'h000000A7 )) + \blk00000003/blk000002b1/blk000002d8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c0 ), + .DPO(\blk00000003/blk000002b1/sig000009d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002b1/blk000002d7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c2 ), + .DPO(\blk00000003/blk000002b1/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e3 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e2 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e1 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e0 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009df ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009de ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dd ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dc ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009db ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009da ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d9 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d8 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d7 ), + .Q(\blk00000003/sig000002ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d6 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d5 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d4 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d3 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d2 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d1 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d0 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cf ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ce ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cd ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cc ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cb ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ca ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c9 ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c8 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c7 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c6 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c5 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c4 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c3 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c2 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c1 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c0 ), + .Q(\blk00000003/sig000004ec ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig000009bf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002ea/blk00000310 ( + .I0(ce), + .I1(\blk00000003/sig0000042a ), + .O(\blk00000003/blk000002ea/sig00000a27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030f ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004db ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a26 ) + ); + RAM32X1D #( + .INIT ( 32'h000000D5 )) + \blk00000003/blk000002ea/blk0000030e ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dc ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030d ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dd ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002ea/blk0000030c ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004de ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000025 )) + \blk00000003/blk000002ea/blk0000030b ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004df ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000079 )) + \blk00000003/blk000002ea/blk0000030a ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e0 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a21 ) + ); + RAM32X1D #( + .INIT ( 32'h000000FB )) + \blk00000003/blk000002ea/blk00000309 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e2 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000056 )) + \blk00000003/blk000002ea/blk00000308 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e3 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1e ) + ); + RAM32X1D #( + .INIT ( 32'h0000002E )) + \blk00000003/blk000002ea/blk00000307 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e1 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000015 )) + \blk00000003/blk000002ea/blk00000306 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e4 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1d ) + ); + RAM32X1D #( + .INIT ( 32'h000000B2 )) + \blk00000003/blk000002ea/blk00000305 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e5 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1c ) + ); + RAM32X1D #( + .INIT ( 32'h0000009F )) + \blk00000003/blk000002ea/blk00000304 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e6 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1b ) + ); + RAM32X1D #( + .INIT ( 32'h000000CE )) + \blk00000003/blk000002ea/blk00000303 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e7 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1a ) + ); + RAM32X1D #( + .INIT ( 32'h000000C4 )) + \blk00000003/blk000002ea/blk00000302 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e8 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000094 )) + \blk00000003/blk000002ea/blk00000301 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e9 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000024 )) + \blk00000003/blk000002ea/blk00000300 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004eb ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002ea/blk000002ff ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ec ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a15 ) + ); + RAM32X1D #( + .INIT ( 32'h000000E6 )) + \blk00000003/blk000002ea/blk000002fe ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ea ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a26 ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a25 ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a24 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a23 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a22 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a21 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a20 ), + .Q(\blk00000003/sig000003ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1f ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1e ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1d ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1c ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1b ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1a ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a19 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a18 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a17 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a16 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a15 ), + .Q(\blk00000003/sig000003c5 ) + ); + GND \blk00000003/blk000002ea/blk000002eb ( + .G(\blk00000003/blk000002ea/sig00000a14 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000371/blk00000397 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk00000371/sig00000a64 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000371/blk00000396 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a63 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000395 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a62 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000394 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a61 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000393 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a60 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000392 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000391 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000390 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038f ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038e ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038d ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038c ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a59 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038b ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a58 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038a ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a57 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000389 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a56 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000388 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a55 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000387 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a53 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000386 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a52 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000385 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a63 ), + .Q(\blk00000003/sig000000f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a62 ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a61 ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a60 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5f ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5e ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5d ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5c ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5b ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5a ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a59 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a58 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a57 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a56 ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a55 ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a54 ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a53 ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a52 ), + .Q(\blk00000003/sig00000103 ) + ); + GND \blk00000003/blk00000371/blk00000372 ( + .G(\blk00000003/blk00000371/sig00000a51 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs new file mode 100644 index 000000000..2439e8b40 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/Makefile.srcs @@ -0,0 +1,18 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# DB COMMON Sources +################################################## +DB_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/common/, \ +PkgRegs.vhd \ +sync/CrossTrigger.vhd \ +sync/Pulser.vhd \ +sync/TdcTop.vhd \ +sync/TdcWrapper.vhd \ +sync/TdcCore.edf \ +sync/SyncRegsIfc.edf \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd new file mode 100644 index 000000000..783e86e9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/PkgRegs.vhd @@ -0,0 +1,314 @@ +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- This package contains functions for reading and writing N310 registers. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + + +package PkgRegs is + + + -- RegPort Type Definitions : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kAddressWidth : integer := 16; + + subtype InterfaceData_t is std_logic_vector(31 downto 0); + type RegDataAry_t is array (natural range <>) of InterfaceData_t; + constant kRegPortDataZero : InterfaceData_t := (others => '0'); + + -- The type of the signal used to communicate from the Interface + -- component to the frameworks + type RegPortIn_t is record + Address : unsigned(kAddressWidth - 1 downto 0); + Data : InterfaceData_t; + Rd : boolean; -- Must be a one clock cycle pulse + Wt : boolean; -- Must be a one clock cycle pulse + end record; + + -- The type of the signal used to communicate to the Interface + -- component from the frameworks + -- Ready is just the Ready signal from the Handshake component. + -- Address in RegPortIn_t should be valid in the cycle where Data, DataValid, + -- or Ready are being sampled by the bus communication interface. + type RegPortOut_t is record + Data : InterfaceData_t; + DataValid : boolean; -- Must be a one clock cycle pulse + Ready : boolean; -- Must be valid one clock after Wt assertion + end record; + + -- Constants for the RegPort + constant kRegPortInZero : RegPortIn_t := ( + Address => to_unsigned(0,kAddressWidth), + Data => (others => '0'), + Rd => false, + Wt => false); + + constant kRegPortOutZero : RegPortOut_t := ( + Data => (others=>'0'), + DataValid => false, + Ready => true); + + + + -- Register Offset Types : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + -- Custom type for defining register spaces. Is it assumed that all defined register + -- addresses for each space are kOffset <= Address < kOffset+kWidth. Therefore when + -- Address equals kOffset+kWidth, we are not talking to this space but the space + -- above it. + type RegOffset_t is record + kOffset : integer; + kWidth : integer; + end record; + + constant kRegOffsetZero : RegOffset_t := (kOffset => 16#0#, kWidth => 16#04#); + + + + -- Access Functions : ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- Helper function to combine register ports on their way back upstream. + function "+" (L, R : RegPortOut_t) return RegPortOut_t; + + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t; + + -- Helper functions to determine when a register is targeted by the RegPort. There + -- are three groups: RegSelected, RegWrite, and RegRead. The latter two call + -- RegSelected to determine if a register is targeted and being read or written. + -- RegSelected is also overloaded to accommodate the RegOffset_t type. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean; + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector; + + + + + -- Flattening Functions : ------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + constant kFlatRegPortInSize : natural := kAddressWidth + + InterfaceData_t'length + + 2; + + subtype FlatRegPortIn_t is std_logic_vector(kFlatRegPortInSize-1 downto 0); + + constant kFlatRegPortOutSize : natural := InterfaceData_t'length + + 2; + + subtype FlatRegPortOut_t is std_logic_vector(kFlatRegPortOutSize-1 downto 0); + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t; + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t; + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t; + + + + +end PkgRegs; + + +package body PkgRegs is + + -- Combines RegPortOut_t types together + function "+" (L, R : RegPortOut_t) return RegPortOut_t + is + variable ReturnVal : RegPortOut_t; + begin + ReturnVal := kRegPortOutZero; + ReturnVal.Data := L.Data or R.Data; + ReturnVal.DataValid := L.DataValid or R.DataValid; + ReturnVal.Ready := L.Ready and R.Ready; + return ReturnVal; + end function; + + + -- This function lops off the portion of the register bus that is + -- decoded in the InAddrSpace function in order to reduce the number of bits + -- decoded by the register read logic. Also, the Rd and Wt strobes are gated + -- as well. + function Mask(RegPortIn : in RegPortIn_t; + kRegisterOffset : in RegOffset_t) return RegPortIn_t + is + variable RegPortInVar : RegPortIn_t; + variable InSpace : boolean := false; + begin + + InSpace := (RegPortIn.Address >= kRegisterOffset.kOffset) and + (RegPortIn.Address < kRegisterOffset.kOffset + kRegisterOffset.kWidth); + + -- Compare the most significant bits of the address bus downto the LSb + -- that we just calculated. + if InSpace then + -- If in address space then allow Rd and Wt to assert + RegPortInVar.Rd := RegPortIn.Rd; + RegPortInVar.Wt := RegPortIn.Wt; + else + RegPortInVar.Rd := kRegPortInZero.Rd; + RegPortInVar.Wt := kRegPortInZero.Wt; + end if; + + RegPortInVar.Data := RegPortIn.Data; + RegPortInVar.Address := RegPortIn.Address - kRegisterOffset.kOffset; + return RegPortInVar; + end function Mask; + + + -- Returns true when this chip is selected and the address matches the register. + -- Note that RegOffset is divided by 4 before being compared against the register + -- port Address value. + function RegSelected (RegOffset : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegPortIn.Address = to_unsigned(RegOffset, RegPortIn.Address'length); + end function RegSelected; + + -- Returns true when the register is being written. + function RegWrite (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Wt; + end function RegWrite; + + -- Returns true when the register is being read. + function RegRead (Address : integer; + RegPortIn : RegPortIn_t) return boolean is + begin + return RegSelected(Address, RegPortIn) and RegPortIn.Rd; + end function RegRead; + + -- Overloaded version of RegSelected for the RegOffset_t + -- NOTE!!! Offset <= Address < Offset+Width + -- Therefore, this function assumes that when Address = Offset+Width we are talking to + -- a different register group than the one given in RegisterOffset. + -- function RegSelected (RegPortIn : RegPortIn_t; + -- RegisterOffset : RegOffset_t) return boolean is + -- begin + -- return (RegPortIn.Address >= to_unsigned(RegisterOffset.kOffset, RegPortIn.Address'length)) and + -- (RegPortIn.Address < to_unsigned(RegisterOffset.kOffset + RegisterOffset.kWidth, RegPortIn.Address'length)); + -- end function RegSelected; + + function OrArray(ArrayIn : RegDataAry_t) return std_logic_vector + is + variable ReturnVar : std_logic_vector(ArrayIn(ArrayIn'right)'range); + begin + ReturnVar := (others => '0'); + for i in ArrayIn'range loop + ReturnVar := ReturnVar or ArrayIn(i); + end loop; + return ReturnVar; + end function OrArray; + + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + + + ----------------------------------------------------- + -- REG PORTS (FROM PkgCommunicationInterface) + -- + -- subtype InterfaceData_t is std_logic_vector(31 downto 0); + -- + -- constant kAddressWidth : positive := kAddressWidth - 2; + -- + -- type RegPortIn_t is record + -- Address : unsigned(kAddressWidth - 1 downto 0); + -- Data : InterfaceData_t; + -- Rd : boolean; -- Must be a one clock cycle pulse + -- Wt : boolean; -- Must be a one clock cycle pulse + -- end record; + + function Flatten(Var : RegPortIn_t) return FlatRegPortIn_t is + variable Index : natural; + variable RetVar : FlatRegPortIn_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Wt); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.Rd); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + RetVar(Index + Var.Address'length - 1 downto Index) := std_logic_vector(Var.Address); + Index := Index + Var.Address'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortIn_t) return RegPortIn_t is + variable Index : natural; + variable RetVal : RegPortIn_t; + begin + Index := 0; + RetVal.Wt := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Rd := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + RetVal.Address := unsigned(Var(Index + RetVal.Address'length - 1 downto Index)); + Index := Index + RetVal.Address'length; + + return RetVal; + end function Unflatten; + + -- type RegPortOut_t is record + -- Data : InterfaceData_t; + -- DataValid : boolean; -- Must be a one clock cycle pulse + -- Ready : boolean; -- Must be valid one clock after Wt assertion + -- end record; + + function Flatten(Var : RegPortOut_t) return FlatRegPortOut_t is + variable Index : natural; + variable RetVar : FlatRegPortOut_t; + begin + Index := 0; + RetVar(Index) := to_StdLogic(Var.Ready); Index := Index + 1; + RetVar(Index) := to_StdLogic(Var.DataValid); Index := Index + 1; + RetVar(Index + Var.Data'length - 1 downto Index) := std_logic_vector(Var.Data); + Index := Index + Var.Data'length; + + return RetVar; + end function Flatten; + + function Unflatten(Var : FlatRegPortOut_t) return RegPortOut_t is + variable Index : natural; + variable RetVal : RegPortOut_t; + begin + Index := 0; + RetVal.Ready := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.DataValid := to_Boolean(Var(Index)); Index := Index + 1; + RetVal.Data := InterfaceData_t(Var(Index + RetVal.Data'length - 1 downto Index)); + Index := Index + RetVal.Data'length; + + return RetVal; + end function Unflatten; + + + +end PkgRegs; diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd new file mode 100644 index 000000000..70a873501 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/CrossTrigger.vhd @@ -0,0 +1,414 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Uses the RP and SP edges to cross a trigger from the RefClk domain to +-- the SampleClk domain. The RP FE captures the input trigger and sends it to +-- the SampleClk domain. There, it is double-synchronized but only allowed to pass +-- when the SP RE occurs. The trigger (now in the SampleClk domain) is then passed +-- through an elastic buffer before being sent on it's merry way. +-- +-- Below is the latency through this module. If you assert rTriggerIn before or after +-- the rRP RE, then you need to add/subtract the distance to the rRP RE. +-- +-- Deterministic latency through this module is (starting at the rRP RE): +-- Measured difference between rRP and sSP rising edges (using a TDC, positive value +-- if rRP rises before sSP). +-- + One period of sSP +-- + Two periods of SampleClk (Double Sync) +-- + (sElasticBufferPtr value + 1) * SampleClk Period +-- + One period of SampleClk +-- +-- How much skew between RP and SP can we allow and still safely pass triggers? +-- Our "launch" edge is essentially the RP FE, and our "latch" edge is the SP RE. +-- Consider the no skew (RP and SP edges align) case first. Our setup and hold budget +-- is balanced at T/2. Based on this, it seems we can tolerate almost T/2 skew in either +-- direction (ignoring a few Reference and Sample Clock cycles here and there). +-- My recommendation is to keep the skew to a minimum, like less than T/4. +-- In the context of the FTDC project for N310, this should be a no-brainer since +-- the SP pulses are started only a few RefClk cycles after RP. The skew is +-- easily verified by taking a FTDC measurement. If the skew is less than T/4, you can +-- sleep easy. If not, then I recommend doing a comprehensive analysis of how much +-- settling time you have between the trigger being launched from the RefClk domain +-- and latched in the SampleClk domain. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + + +entity CrossTrigger is + port ( + aReset : in boolean; + + RefClk : in std_logic; + -- For convenience while writing this, I have only considered the N3x0 case where + -- rRP is slightly ahead of sSP in phase. + rRP : in boolean; + -- De-asserts the clock cycle after rTriggerIn asserts. Re-asserts after the + -- second falling edge of rRP, indicating new triggers can be accepted. + rReadyForInput : out boolean; + -- Only one pulse will be output for each rising edge of rTriggerIn. rTriggerIn is + -- ignored when rReadyForInput is de-asserted. All levels are ignored when Enable + -- is de-asserted. + rEnableTrigger : in boolean; + rTriggerIn : in boolean; + + SampleClk : in std_logic; + sSP : in boolean; + -- An elastic buffer just before the output is used to compensate for skew + -- in sSP pulses across boards. Default should be in the middle of the 4 bit + -- range at 7. + sElasticBufferPtr : in unsigned(3 downto 0); + -- Single-cycle pulse output. + sTriggerOut : out boolean + ); +end CrossTrigger; + + +architecture rtl of CrossTrigger is + + --vhook_sigstart + --vhook_sigend + + signal rRpFE, + rRpDly, + rTriggerToSClk, + rTriggerCaptured, + sSpRE, + sSpDly : boolean; + + signal sTriggerBuffer : unsigned(2**sElasticBufferPtr'length-1 downto 0); + signal sTriggerInSClk, sTriggerInSClk_ms : boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute async_reg : string; + attribute async_reg of sTriggerInSClk : signal is "TRUE"; + attribute async_reg of sTriggerInSClk_ms : signal is "TRUE"; + +begin + + -- Reference Clock Domain Trigger Capture : ------------------------------------------- + -- The trigger input is captured whenever it is high. The captured value is reset + -- by the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + + rRpFE <= rRpDly and not rRP; + + CaptureTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerCaptured <= false; + rRpDly <= false; + elsif rising_edge(RefClk) then + rRpDly <= rRP; + if not rEnableTrigger then + rTriggerCaptured <= false; + elsif rTriggerIn then + -- Capture trigger whenever the input is asserted (so this will work with single + -- cycle and multi-cycle pulses). + rTriggerCaptured <= true; + elsif rRpFE then + -- Reset the captured trigger one cycle after the rRP FE. + rTriggerCaptured <= false; + end if; + end if; + end process; + + + -- Send Trigger To Sample Clock Domain : ---------------------------------------------- + -- Send the captured trigger on the falling edge of rRP. + -- ------------------------------------------------------------------------------------ + SendTrigger : process(aReset, RefClk) + begin + if aReset then + rTriggerToSClk <= false; + elsif rising_edge(RefClk) then + if not rEnableTrigger then + rTriggerToSClk <= false; + elsif rRpFE then + rTriggerToSClk <= rTriggerCaptured; + end if; + end if; + end process; + + rReadyForInput <= not (rTriggerToSClk or rTriggerCaptured); + + -- Capture Trigger in Sample Clock Domain : ------------------------------------------- + -- On the rising edge of sSP, capture the trigger. To keep things free of + -- metastability, we double-sync the trigger into the SampleClk domain first. + -- ------------------------------------------------------------------------------------ + + ReceiveAndProcessTrigger : process(aReset, SampleClk) + begin + if aReset then + sSpDly <= false; + sTriggerBuffer <= (others => '0'); + sTriggerOut <= false; + sTriggerInSClk_ms <= false; + sTriggerInSClk <= false; + elsif rising_edge(SampleClk) then + -- Edge detector delays. + sSpDly <= sSP; + + -- Double-synchronizer for trigger. + sTriggerInSClk_ms <= rTriggerToSClk; + sTriggerInSClk <= sTriggerInSClk_ms; + + -- Delay chain for the elastic buffer. Move to the left people! Note that this + -- operation incurs at least one cycle of delay. Also note the trigger input is + -- gated with the SP RE. + sTriggerBuffer <= sTriggerBuffer(sTriggerBuffer'high-1 downto 0) & + to_stdlogic(sTriggerInSClk and sSpRE); + + -- Based on the buffer pointer value select and flop the output one more time. + sTriggerOut <= to_boolean(sTriggerBuffer(to_integer(sElasticBufferPtr))); + end if; + end process; + + -- Rising edge detectors. + sSpRE <= sSP and not sSpDly; + + +end rtl; + + + + + +-------------------------------------------------------------------------------- +-- Testbench for CrossTrigger +-- +-- Meh coverage on the triggers so far... but this tests general operation +-- and latency. +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity tb_CrossTrigger is end tb_CrossTrigger; + +architecture test of tb_CrossTrigger is + + -- Sets up a 1.25 MHz period. + constant kClksPerPulseMaxBits: integer := 10; + constant kRpPeriodInRClks : integer := 8; + constant kRpHighTimeInRClks : integer := 4; + constant kSpPeriodInRClks : integer := 100; + constant kSpHighTimeInRClks : integer := 50; + + --vhook_sigstart + signal aReset: boolean; + signal RefClk: std_logic := '0'; + signal rEnablePulser: boolean; + signal rEnableTrigger: boolean; + signal rReadyForInput: boolean; + signal rRP: boolean; + signal rTriggerIn: boolean; + signal SampleClk: std_logic := '0'; + signal sElasticBufferPtr: unsigned(3 downto 0); + signal sEnablePulser: boolean; + signal sSP: boolean; + signal sTriggerOut: boolean; + --vhook_sigend + + signal StopSim : boolean; + -- shared variable Rand : Random_t; + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + signal rRfiExpected: boolean:= true; + signal sTriggerOutExpected: boolean:= false; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + + --vhook_e Pulser RpPulser + --vhook_a Clk RefClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse rEnablePulser + --vhook_a cPulse rRP + RpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kRpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kRpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rEnablePulser, --in boolean + cPulse => rRP); --out boolean + + --vhook_e Pulser SpPulser + --vhook_a Clk SampleClk + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits) + --vhook_a cEnablePulse sEnablePulser + --vhook_a cPulse sSP + SpPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(kSpPeriodInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(kSpHighTimeInRClks,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sEnablePulser, --in boolean + cPulse => sSP); --out boolean + + + main: process + procedure SendTrigger is + begin + assert rReadyForInput + report "RFI isn't high, so we can't issue a trigger" severity error; + + -- Give it some action. We need to ideally test this for every phase offset of + -- rTriggerIn with respect to the rising edge of rRP, but let's get to that later. + -- For now, wait until a rising edge on rRP and then wait for most of the period + -- to issue the trigger. + wait until rRP and not rRP'delayed; + wait for (kRpPeriodInRClks-3)*kRPer; + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + rRfiExpected <= false; + + -- At this point, we wait until a sSP RE, plus two SampleClks, plus sElasticBufferPtr + -- plus 1 worth of SampleClks, plus one more SampleClk, and then the trigger + -- should appear. + wait until not rRP and rRP'delayed; + wait until sSP and not sSP'delayed; + ClkWait(SampleClk,1); + ClkWait(SampleClk, to_integer(sElasticBufferPtr)+1); + sTriggerOutExpected <= true; + ClkWait(SampleClk,1); + sTriggerOutExpected <= false; + wait until not rRP and rRP'delayed; + ClkWait(RefClk,1); + rRfiExpected <= true; + end procedure SendTrigger; + + begin + rEnablePulser <= false; + sEnablePulser <= false; + rEnableTrigger <= true; + sElasticBufferPtr <= to_unsigned(7, sElasticBufferPtr'length); + + aReset <= true, false after 10 ns; + ClkWait(RefClk,5); + + -- Start up the pulsers and ensure nothing comes out of the trigger for a while. + rEnablePulser <= true; + ClkWait(RefClk, 3); + ClkWait(SampleClk, 2); + sEnablePulser <= true; + + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + assert (rReadyForInput) and rReadyForInput'stable(kRpPeriodInRClks*5*kRPer) + report "Ready for Input was not high before trigger!" severity error; + + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + SendTrigger; + + ClkWait(RefClk, kRpPeriodInRClks*5); + + -- Turn off the trigger enable and send a trigger. + rEnableTrigger <= false; + ClkWait(RefClk); + rTriggerIn <= true; + ClkWait(RefClk); + rTriggerIn <= false; + + -- And nothing should happen. + ClkWait(RefClk, kRpPeriodInRClks*5); + assert (not sTriggerOut) and sTriggerOut'stable(kRpPeriodInRClks*5*kRPer) + report "Rogue activity on sTriggerOut before rTriggerIn asserted!" severity error; + + + ClkWait(RefClk, kRpPeriodInRClks*5); + StopSim <= true; + wait; + end process; + + + CheckRfi : process(RefClk) + begin + if falling_edge(RefClk) then + assert rReadyForInput = rRfiExpected + report "RFI didn't match expected" severity error; + end if; + end process; + + CheckTrigOut : process(SampleClk) + begin + if falling_edge(SampleClk) then + assert sTriggerOut = sTriggerOutExpected + report "Trigger Out didn't match expected" severity error; + end if; + end process; + + + --vhook_e CrossTrigger dutx + dutx: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRP, --in boolean + rReadyForInput => rReadyForInput, --out boolean + rEnableTrigger => rEnableTrigger, --in boolean + rTriggerIn => rTriggerIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSP, --in boolean + sElasticBufferPtr => sElasticBufferPtr, --in unsigned(3:0) + sTriggerOut => sTriggerOut); --out boolean + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd new file mode 100644 index 000000000..c6cb30f24 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/Pulser.vhd @@ -0,0 +1,362 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- The purpose of this module is to create a psuedo-clock "pulse" on the output +-- cPulse whenever cEnablePulse is asserted. +-- +-- The output period and high time are determined by the inputs cPeriod and +-- cHighTime, where cPeriod must be greater than cHighTime+2. When these values +-- are valid at the inputs, pulse cLoadLimits to load them into the pulser routine. +-- It is not recommended to leave cEnablePulse asserted when loading new limits. +-- +-- Dynamic period and duty cycle setup: +-- 1) Disable the pulser by de-asserting cEnablePulse. +-- 2) Load new period and duty cycle by modifying cPeriod and cHighTime. Pulse +-- cLoadLimits for at least one Clk cycle. +-- 3) Enable the pulser by asserting cEnablePulse. +-- 4) Repeat 1-3 as necessary. +-- +-- Static period and duty cycle setup: +-- 1) Tie cLoadLimits to asserted. +-- 2) Tie cPeriod and cHighTime to static values. +-- 3) Enable and disable the pulser by asserting and de-asserting cEnablePulser at will. +-- This input can also be tied asserted in this case. +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity Pulser is + generic ( + -- The pulse counter is kClksPerPulseMaxBits wide. + -- Why 16? Then both cPeriod and cHighTime fit nicely into one 32 bit register! + -- Minimum of 3 to make our default values for cHighTime work out. + kClksPerPulseMaxBits : integer range 3 to 32 := 16 + ); + port ( + aReset : in boolean; + Clk : in std_logic; + + -- Pulse cLoadLimits when cPeriod and cHighTime are valid. Is it not recommended to + -- load new limits when the output is enabled. + -- Alternatively, cLoadLimits can be tied high if cPeriod and cHighTime are also + -- tied to static values. + cLoadLimits : in boolean; + cPeriod : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + cHighTime : in unsigned(kClksPerPulseMaxBits - 1 downto 0); + + -- When cEnablePulse is de-asserted, cPulse idles low on the following cycle. + -- When asserted, cPulse will then assert within a few cycles. + -- This input can be tied high, if desired, and the pulses will start several + -- clock cycles after aReset de-assertion. + cEnablePulse : in boolean; + + -- When cEnablePulse is asserted, cPulse will produce a rising edge every + -- cPeriod of the Clk input and a falling edge cHighTime cycles after + -- the rising edge. + cPulse : out boolean + ); +end Pulser; + + +architecture rtl of Pulser is + + signal cCounter, + cPeriodStored, + cHighTimeStored : unsigned(cPeriod'range); + + signal cSafeToStart_ms, cSafeToStart, cSafeToStartDly : boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of cSafeToStart_ms : signal is "true"; + attribute ASYNC_REG of cSafeToStart : signal is "true"; + +begin + + --synthesis translate_off + CheckInputRanges : process(Clk) + begin + if falling_edge(Clk) then + -- +2 since we have the output high offset from the zero of the counter + assert (cPeriodStored > cHighTimeStored + 2) + report "cPeriod is not greater than cHighTime + 2" severity error; + -- Ensure the high time is greater than 1... + assert (cHighTimeStored > 1) + report "cHighTime is not greater than 1" severity error; + end if; + end process; + --synthesis translate_on + + + -- ------------------------------------------------------------------------------------ + -- !!! SAFE COUNTER STARTUP !!! + -- This counter starts safely, meaning it cannot start counting immediately after + -- aReset de-assertion, because the counter cannot start until cSafeToStart asserts, + -- which cannot happen until 1-2 clock cycles after aReset de-assertion. + -- ------------------------------------------------------------------------------------ + CountFreqRefPeriod: process(aReset, Clk) + begin + if aReset then + cCounter <= (others => '0'); + cSafeToStart_ms <= false; + cSafeToStart <= false; + cSafeToStartDly <= false; + cPulse <= false; + cPeriodStored <= (others => '1'); + -- This is a rather arbitrary start value, but we are guaranteed that it is + -- less than the reset value of cPeriodStored as well as greater than 2, + -- so it works well enough in case the module isn't set up correctly. + cHighTimeStored <= to_unsigned(kClksPerPulseMaxBits+2,cHighTimeStored'length); + elsif rising_edge(Clk) then + -- Create a safe counter startup signal that asserts shortly after + -- aReset de-assertion. + cSafeToStart_ms <= true; + cSafeToStart <= cSafeToStart_ms; + -- In the case where cLoadLimits and cEnablePulse are tied high, we need to give + -- them one cycle to load before starting the counter, so we delay cSafeToStart + -- by one for the counter. + cSafeToStartDly <= cSafeToStart; + + if cEnablePulse and cSafeToStartDly then + -- Simple counter increment until ceiling reached, then roll over. + if cCounter >= cPeriodStored - 1 then + cCounter <= (others => '0'); + else + cCounter <= cCounter + 1; + end if; + + -- Pulse the output when counter is between 1 and cHighTimeStored. + if cCounter = 1 then + cPulse <= true; + elsif cCounter >= cHighTimeStored+1 then + cPulse <= false; + end if; + + else + cPulse <= false; + cCounter <= (others => '0'); + end if; + + if cLoadLimits and cSafeToStart then + cPeriodStored <= cPeriod; + cHighTimeStored <= cHighTime; + end if; + end if; + end process; + +end rtl; + + +-------------------------------------------------------------------------------- +-- Testbench for Pulser +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_Pulser is end tb_Pulser; + +architecture test of tb_Pulser is + + constant kClksPerPulseMaxBits : integer := 16; + + --vhook_sigstart + signal aReset: boolean; + signal cEnablePulse: boolean; + signal cHighTime: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal Clk: std_logic := '0'; + signal cLoadLimits: boolean; + signal cPeriod: unsigned(kClksPerPulseMaxBits-1 downto 0); + signal cPulse: boolean; + signal cPulseDut2: boolean; + --vhook_sigend + + signal StopSim : boolean; + constant kPer : time := 10 ns; + + signal CheckPulse : boolean := false; + signal cPulseSl : std_logic := '0'; + signal cPulseDut2Sl : std_logic := '0'; + + procedure ClkWait(X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + +begin + + Clk <= not Clk after kPer/2 when not StopSim else '0'; + + main: process + begin + cEnablePulse <= false; + aReset <= true, false after 10 ns; + ClkWait(5); + + -- Ensure the pulse is quiet for a while. + ClkWait(100); + assert cPulse'stable(kPer*100) and not cPulse + report "pulse not stable at false at startup" + severity error; + + + -- Set up, then enable the pulse; expect it to go high after a few cycles. + cPeriod <= to_unsigned(250,cPeriod'length); + cHighTime <= to_unsigned(100,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + -- Disable pulse, and check that it goes away for a long time + cEnablePulse <= false; + CheckPulse <= false; + -- 2 is about the max time for it to go away. + ClkWait(2); + ClkWait(2**kClksPerPulseMaxBits); + assert (not cPulse) and cPulse'stable(2**kClksPerPulseMaxBits*kPer) + report "disable didn't work" severity error; + + + -- Re-do all the initial tests with different periods and such. + + -- Enable the pulse, expect it to go high after a few cycles + cPeriod <= to_unsigned(10,cPeriod'length); + cHighTime <= to_unsigned(5,cPeriod'length); + cLoadLimits <= true; + ClkWait; + cLoadLimits <= false; + cEnablePulse <= true; + ClkWait(2); -- pulse rises here + wait until falling_edge(Clk); + assert cPulse report "cPulse not high two cycles after enabling" severity error; + -- After another clock cycle the checker below should be primed, so we can enable it. + ClkWait; + CheckPulse <= true; + ClkWait(to_integer(cHighTime)-1); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + + -- Check the pulse high and low for a few cycles (duplicated below, but this also + -- checks that it actually is toggling). + for i in 0 to 100 loop + ClkWait(to_integer(cPeriod) - to_integer(cHighTime)); + wait until falling_edge(Clk); + assert cPulse report "Pulse not high when expected" severity error; + ClkWait(to_integer(cHighTime)); + wait until falling_edge(Clk); + assert not cPulse report "Pulse not low after high requirement" severity error; + end loop; + + ClkWait(100); + + + StopSim <= true; + wait; + end process; + + cPulseSl <= '1' when cPulse else '0'; + + -- Test the period and duty cycle of the pulse. + CheckPulseSpecs : process(cPulseSl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cHighTime)) + report "High cycles requirement not met" severity error; + elsif rising_edge(cPulseSl) then + assert (not CheckPulse) or (now - LastRise = kPer*to_integer(cPeriod)) + report "Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*to_integer(cPeriod)) + severity error; + LastRise := now; + end if; + end process; + + --vhook_e Pulser dutx + dutx: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => cLoadLimits, --in boolean + cPeriod => cPeriod, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => cHighTime, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => cEnablePulse, --in boolean + cPulse => cPulse); --out boolean + + + --vhook_e Pulser dut2 + --vhook_a cLoadLimits true + --vhook_a cPeriod to_unsigned(5,kClksPerPulseMaxBits) + --vhook_a cHighTime to_unsigned(2,kClksPerPulseMaxBits) + --vhook_a cEnablePulse true + --vhook_a cPulse cPulseDut2 + dut2: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kClksPerPulseMaxBits) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => Clk, --in std_logic + cLoadLimits => true, --in boolean + cPeriod => to_unsigned(5,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => to_unsigned(2,kClksPerPulseMaxBits), --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => true, --in boolean + cPulse => cPulseDut2); --out boolean + + cPulseDut2Sl <= '1' when cPulseDut2 else '0'; + + CheckDut2 : process (cPulseDut2Sl) + variable LastRise : time := 0 ns; + begin + if falling_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*2) + report "DUT 2 High cycles requirement not met" severity error; + elsif rising_edge(cPulseDut2Sl) then + assert (not CheckPulse) or (now - LastRise = kPer*5) + report "DUT 2 Period requirement not met" & LF & + "Act: " & time'image(now-LastRise) & LF & + "Req: " & time'image(kPer*5) + severity error; + LastRise := now; + end if; + end process; + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf new file mode 100644 index 000000000..a3886f6d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/SyncRegsIfc.edf @@ -0,0 +1,23420 @@ +(edif SyncRegsIfc + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2018 03 16 14 23 36) + (program "Vivado" (version "2017.4")) + (comment "Built on 'Fri Dec 15 20:55:39 MST 2017'") + (comment "Built by 'xbuild'") + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell FDCE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port CLR (direction INPUT)) + (port D (direction INPUT)) + ) + ) + ) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell LUT1 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell LUT6 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + (port I5 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell FDPE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port PRE (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell SyncRegsIfc (celltype GENERIC) + (view SyncRegsIfc (viewtype NETLIST) + (interface + (port BusClk (direction INPUT)) + (port MeasClk (direction INPUT)) + (port RefClk (direction INPUT)) + (port SampleClk (direction INPUT)) + (port aBusReset (direction INPUT)) + (port aTdcReset (direction OUTPUT)) + (port bBusReset (direction INPUT)) + (port mOffsetsDone (direction INPUT)) + (port mOffsetsValid (direction INPUT)) + (port rEnablePpsCrossing (direction OUTPUT)) + (port rEnableTdc (direction OUTPUT)) + (port rLoadRePulseCounts (direction OUTPUT)) + (port rLoadRpCounts (direction OUTPUT)) + (port rLoadRptCounts (direction OUTPUT)) + (port rPpsPulseCaptured (direction INPUT)) + (port rReRunEnable (direction OUTPUT)) + (port rResetTdc (direction OUTPUT)) + (port rResetTdcDone (direction INPUT)) + (port sLoadSpCounts (direction OUTPUT)) + (port sLoadSptCounts (direction OUTPUT)) + (port (array (rename bRegPortInFlat "bRegPortInFlat[49:0]") 50) (direction INPUT)) + (port (array (rename bRegPortOutFlat "bRegPortOutFlat[33:0]") 34) (direction OUTPUT)) + (port (array (rename mRpOffset "mRpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename mSpOffset "mSpOffset[39:0]") 40) (direction INPUT)) + (port (array (rename rPulserEnableDelayVal "rPulserEnableDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename rRePulseHighTimeInRClks "rRePulseHighTimeInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRePulsePeriodInRClks "rRePulsePeriodInRClks[23:0]") 24) (direction OUTPUT)) + (port (array (rename rRpHighTimeInRClks "rRpHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRpPeriodInRClks "rRpPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptHighTimeInRClks "rRptHighTimeInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename rRptPeriodInRClks "rRptPeriodInRClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sPpsClkCrossDelayVal "sPpsClkCrossDelayVal[3:0]") 4) (direction OUTPUT)) + (port (array (rename sSpHighTimeInSClks "sSpHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSpPeriodInSClks "sSpPeriodInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptHighTimeInSClks "sSptHighTimeInSClks[15:0]") 16) (direction OUTPUT)) + (port (array (rename sSptPeriodInSClks "sSptPeriodInSClks[15:0]") 16) (direction OUTPUT)) + ) + (contents + (instance (rename BlkIn_iDlyPush_i_1 "BlkIn.iDlyPush_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance (rename BlkIn_iDlyPush_i_1__0 "BlkIn.iDlyPush_i_1__0") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename BlkIn_iDlyPush_i_1__1 "BlkIn.iDlyPush_i_1__1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__2 "BlkIn.iDlyPush_i_1__2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair24")) + ) + (instance (rename BlkIn_iDlyPush_i_1__3 "BlkIn.iDlyPush_i_1__3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h80")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance (rename BlkIn_iDlyPush_i_1__4 "BlkIn.iDlyPush_i_1__4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h20")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename BlkOut_oDataValid_i_1 "BlkOut.oDataValid_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__0 "BlkOut.oDataValid_i_1__0") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__1 "BlkOut.oDataValid_i_1__1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__2 "BlkOut.oDataValid_i_1__2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename BlkOut_oDataValid_i_1__3 "BlkOut.oDataValid_i_1__3") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "EnableTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance (rename Gen0_FDCEx_i_1 "Gen0.FDCEx_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__0 "Gen0.FDCEx_i_1__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__1 "Gen0.FDCEx_i_1__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__10 "Gen0.FDCEx_i_1__10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__11 "Gen0.FDCEx_i_1__11") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_1__2 "Gen0.FDCEx_i_1__2") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0100")) + ) + (instance (rename Gen0_FDCEx_i_1__3 "Gen0.FDCEx_i_1__3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h4000")) + ) + (instance (rename Gen0_FDCEx_i_1__4 "Gen0.FDCEx_i_1__4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + ) + (instance (rename Gen0_FDCEx_i_1__5 "Gen0.FDCEx_i_1__5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__6 "Gen0.FDCEx_i_1__6") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__7 "Gen0.FDCEx_i_1__7") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__8 "Gen0.FDCEx_i_1__8") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h6")) + ) + (instance (rename Gen0_FDCEx_i_1__9 "Gen0.FDCEx_i_1__9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename Gen0_FDCEx_i_2 "Gen0.FDCEx_i_2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__0 "Gen0.FDCEx_i_2__0") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__1 "Gen0.FDCEx_i_2__1") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__2 "Gen0.FDCEx_i_2__2") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__3 "Gen0.FDCEx_i_2__3") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__4 "Gen0.FDCEx_i_2__4") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__5 "Gen0.FDCEx_i_2__5") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__6 "Gen0.FDCEx_i_2__6") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_2__7 "Gen0.FDCEx_i_2__7") (viewref netlist (cellref LUT1 (libraryref hdi_primitives))) + (property INIT (string "2'h1")) + ) + (instance (rename Gen0_FDCEx_i_3 "Gen0.FDCEx_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0400")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename Gen0_FDCEx_i_3__0 "Gen0.FDCEx_i_3__0") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename Gen0_FDCEx_i_3__1 "Gen0.FDCEx_i_3__1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0002")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg "IncomingOffsetHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[40]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[41]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[42]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[43]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[44]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[45]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[46]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[47]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[48]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[49]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[50]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[51]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[52]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[53]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[54]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[55]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[56]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[57]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[58]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[59]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[60]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[61]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[62]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[63]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[64]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[65]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[66]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[67]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[68]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[69]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[70]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[71]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[72]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[73]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[74]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[75]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[76]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[77]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[78]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[79]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[34].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[35].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename 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IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[42].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[43].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename 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IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[50].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[51].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[52].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[53].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx 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(property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[59].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[60].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[61].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[62].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[63].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[64].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[65].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[66].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[67].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[68].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[69].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[70].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[71].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[72].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[73].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[74].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[75].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[76].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[77].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[78].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[79].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oDataValid_reg "IncomingOffsetHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "IncomingOffsetHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[20].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[21].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[22].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[23].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[24].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[25].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[26].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[27].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[28].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[29].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[2].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[30].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[31].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[32].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[33].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[34].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[35].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[36].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[37].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[38].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[39].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[3].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[40].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[41].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[42].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[43].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[44].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[45].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[46].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[47].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[48].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[49].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[4].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[50].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[51].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[52].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[53].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[54].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[55].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[56].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[57].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[58].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[59].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[5].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[60].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[61].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[62].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[63].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[64].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[65].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[66].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[67].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[68].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCapturedDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "PpsCrossEnDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PpsDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PpsDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PpsDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg "PulserEnableDelayValCrossingHs/HBx/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkIn_iDlyPush_reg "RePulse1CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse1CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse1CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse1CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle2_reg "RePulse1CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse1CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkIn_iDlyPush_reg "RePulse2CntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_0_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_10_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_11_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_12_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_13_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_14_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_15_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_16_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_17_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_18_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_19_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_1_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_20_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_21_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_22_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_23_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_24_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_25_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_26_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_27_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_28_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_29_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_2_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_30_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_31_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_3_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_4_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_5_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_6_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_7_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_8_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iLclStoredData_reg_9_ "RePulse2CntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RePulse2CntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RePulse2CntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oDataValid_reg "RePulse2CntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle2_reg "RePulse2CntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RePulse2CntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ReRunEnableDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetDoneDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx "ResetTdcDs/DoubleSyncBasex/iDlySigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkIn_iDlyPush_reg "RpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_0_ "RpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_10_ "RpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_11_ "RpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_12_ "RpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_13_ "RpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_14_ "RpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_15_ "RpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_16_ "RpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_17_ "RpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_18_ "RpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_19_ "RpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_1_ "RpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_20_ "RpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_21_ "RpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_22_ "RpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_23_ "RpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_24_ "RpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_25_ "RpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_26_ "RpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_27_ "RpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_28_ "RpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_29_ "RpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_2_ "RpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_30_ "RpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_31_ "RpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_3_ "RpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_4_ "RpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_5_ "RpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_6_ "RpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_7_ "RpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_8_ "RpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iLclStoredData_reg_9_ "RpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oDataValid_reg "RpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle2_reg "RpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkIn_iDlyPush_reg "RptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_0_ "RptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_10_ "RptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_11_ "RptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_12_ "RptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_13_ "RptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_14_ "RptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_15_ "RptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_16_ "RptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_17_ "RptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_18_ "RptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_19_ "RptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_1_ "RptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_20_ "RptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_21_ "RptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_22_ "RptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_23_ "RptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_24_ "RptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_25_ "RptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_26_ "RptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_27_ "RptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_28_ "RptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_29_ "RptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_2_ "RptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_30_ "RptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_31_ "RptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_3_ "RptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_4_ "RptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_5_ "RptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_6_ "RptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_7_ "RptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_8_ "RptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iLclStoredData_reg_9_ "RptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "RptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "RptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oDataValid_reg "RptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle2_reg "RptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "RptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkIn_iDlyPush_reg "SpCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_0_ "SpCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_10_ "SpCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_11_ "SpCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_12_ "SpCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_13_ "SpCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_14_ "SpCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_15_ "SpCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_16_ "SpCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_17_ "SpCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_18_ "SpCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_19_ "SpCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_1_ "SpCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_20_ "SpCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_21_ "SpCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_22_ "SpCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_23_ "SpCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_24_ "SpCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_25_ "SpCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_26_ "SpCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_27_ "SpCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_28_ "SpCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_29_ "SpCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_2_ "SpCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_30_ "SpCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_31_ "SpCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_3_ "SpCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_4_ "SpCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_5_ "SpCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_6_ "SpCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_7_ "SpCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_8_ "SpCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iLclStoredData_reg_9_ "SpCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SpCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SpCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oDataValid_reg "SpCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle2_reg "SpCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SpCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkIn_iDlyPush_reg "SptCntHs/BlkIn.iDlyPush_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_0_ "SptCntHs/BlkIn.iLclStoredData_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_10_ "SptCntHs/BlkIn.iLclStoredData_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_11_ "SptCntHs/BlkIn.iLclStoredData_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_12_ "SptCntHs/BlkIn.iLclStoredData_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_13_ "SptCntHs/BlkIn.iLclStoredData_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_14_ "SptCntHs/BlkIn.iLclStoredData_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_15_ "SptCntHs/BlkIn.iLclStoredData_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_16_ "SptCntHs/BlkIn.iLclStoredData_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_17_ "SptCntHs/BlkIn.iLclStoredData_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_18_ "SptCntHs/BlkIn.iLclStoredData_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_19_ "SptCntHs/BlkIn.iLclStoredData_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_1_ "SptCntHs/BlkIn.iLclStoredData_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_20_ "SptCntHs/BlkIn.iLclStoredData_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_21_ "SptCntHs/BlkIn.iLclStoredData_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_22_ "SptCntHs/BlkIn.iLclStoredData_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_23_ "SptCntHs/BlkIn.iLclStoredData_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_24_ "SptCntHs/BlkIn.iLclStoredData_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_25_ "SptCntHs/BlkIn.iLclStoredData_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_26_ "SptCntHs/BlkIn.iLclStoredData_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_27_ "SptCntHs/BlkIn.iLclStoredData_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_28_ "SptCntHs/BlkIn.iLclStoredData_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_29_ "SptCntHs/BlkIn.iLclStoredData_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_2_ "SptCntHs/BlkIn.iLclStoredData_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_30_ "SptCntHs/BlkIn.iLclStoredData_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_31_ "SptCntHs/BlkIn.iLclStoredData_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_3_ "SptCntHs/BlkIn.iLclStoredData_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_4_ "SptCntHs/BlkIn.iLclStoredData_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_5_ "SptCntHs/BlkIn.iLclStoredData_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_6_ "SptCntHs/BlkIn.iLclStoredData_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_7_ "SptCntHs/BlkIn.iLclStoredData_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_8_ "SptCntHs/BlkIn.iLclStoredData_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iLclStoredData_reg_9_ "SptCntHs/BlkIn.iLclStoredData_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx "SptCntHs/BlkIn.iPushTogglex/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[0].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[10].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[11].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[12].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[13].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[14].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[15].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[16].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[17].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[18].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[19].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[1].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[20].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[21].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[22].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[23].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[24].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[25].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[26].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[27].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[28].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[29].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[2].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[30].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[3].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[4].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[5].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[6].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[7].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[8].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx "SptCntHs/BlkOut.ODataFlop/GenFlops[9].DFlopx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oDataValid_reg "SptCntHs/BlkOut.oDataValid_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle1x/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle2_reg "SptCntHs/BlkOut.oPushToggle2_reg") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx "SptCntHs/BlkOut.oPushToggle_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_msx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSigx/Gen0.FDCEx") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property IS_CLR_INVERTED (string "1'b0")) + (property IS_C_INVERTED (string "1'b0")) + (property IS_D_INVERTED (string "1'b0")) + (property ASYNC_REG (boolean (true))) + (property box_type (string "PRIMITIVE")) + ) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance aTdcResetLcl_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0200000000000000")) + ) + (instance aTdcResetLcl_i_3 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00001000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance aTdcResetLcl_i_4 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_i_5 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0001")) + ) + (instance aTdcResetLcl_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__0 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__1 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__2 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_reg_rep__3 (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property ORIG_CELL_NAME (string "aTdcResetLcl_reg")) + ) + (instance aTdcResetLcl_rep_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__0 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__2 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance aTdcResetLcl_rep_i_1__3 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hBF80")) + ) + (instance bClearTdcRegs_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000080")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance bClearTdcRegs_i_2 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000080")) + ) + (instance bClearTdcRegs_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair22")) + ) + (instance bClearTdcRegs_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bEnableTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bEnableTdc_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bOffsetUpdated_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h05030500")) + ) + (instance bOffsetUpdated_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_0__i_1 "bPpsClkCrossDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPpsClkCrossDelayVal_1__i_1 "bPpsClkCrossDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bPpsClkCrossDelayVal_2__i_1 "bPpsClkCrossDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_1 "bPpsClkCrossDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_2 "bPpsClkCrossDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bPpsClkCrossDelayVal_3__i_3 "bPpsClkCrossDelayVal[3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000000100")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_0_ "bPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_1_ "bPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_2_ "bPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPpsClkCrossDelayVal_reg_3_ "bPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPpsClkCrossEn_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bPpsClkCrossEn_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_0__i_1 "bPulserEnableDelayVal[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + (property SOFT_HLUTNM (string "soft_lutpair8")) + ) + (instance (rename bPulserEnableDelayVal_1__i_1 "bPulserEnableDelayVal[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bPulserEnableDelayVal_2__i_1 "bPulserEnableDelayVal[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bPulserEnableDelayVal_3__i_1 "bPulserEnableDelayVal[3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFF8")) + ) + (instance (rename bPulserEnableDelayVal_3__i_2 "bPulserEnableDelayVal[3]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bPulserEnableDelayVal_reg_0_ "bPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bPulserEnableDelayVal_reg_1_ "bPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_2_ "bPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bPulserEnableDelayVal_reg_3_ "bPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPpsDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPpsDelayVal_i_2 (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h01")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance bPushPpsDelayVal_i_3 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance bPushPpsDelayVal_i_4 (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair25")) + ) + (instance bPushPpsDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bPushPulserEnableDelayVal_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0080000000000000")) + ) + (instance bPushPulserEnableDelayVal_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bReRunEnable_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h1101111111000000")) + ) + (instance bReRunEnable_reg (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_1 "bRegPortOutLcl[Data][0]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_2 "bRegPortOutLcl[Data][0]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_3 "bRegPortOutLcl[Data][0]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_4 "bRegPortOutLcl[Data][0]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_5 "bRegPortOutLcl[Data][0]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hAAAAFAAAAAAAEEAA")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_6 "bRegPortOutLcl[Data][0]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__0__i_7 "bRegPortOutLcl[Data][0]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000002000")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_1 "bRegPortOutLcl[Data][10]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_2 "bRegPortOutLcl[Data][10]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_3 "bRegPortOutLcl[Data][10]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__10__i_4 "bRegPortOutLcl[Data][10]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_1 "bRegPortOutLcl[Data][11]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_2 "bRegPortOutLcl[Data][11]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_3 "bRegPortOutLcl[Data][11]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__11__i_4 "bRegPortOutLcl[Data][11]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_1 "bRegPortOutLcl[Data][12]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_2 "bRegPortOutLcl[Data][12]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_3 "bRegPortOutLcl[Data][12]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__12__i_4 "bRegPortOutLcl[Data][12]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_1 "bRegPortOutLcl[Data][13]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFBAA")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_2 "bRegPortOutLcl[Data][13]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_3 "bRegPortOutLcl[Data][13]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__13__i_4 "bRegPortOutLcl[Data][13]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_1 "bRegPortOutLcl[Data][14]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_2 "bRegPortOutLcl[Data][14]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_3 "bRegPortOutLcl[Data][14]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__14__i_4 "bRegPortOutLcl[Data][14]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_1 "bRegPortOutLcl[Data][15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_2 "bRegPortOutLcl[Data][15]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_3 "bRegPortOutLcl[Data][15]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__15__i_4 "bRegPortOutLcl[Data][15]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_1 "bRegPortOutLcl[Data][16]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEEE")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_2 "bRegPortOutLcl[Data][16]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_3 "bRegPortOutLcl[Data][16]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF002000200020")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_4 "bRegPortOutLcl[Data][16]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hF080008000000000")) + ) + (instance (rename bRegPortOutLcl_Data__16__i_5 "bRegPortOutLcl[Data][16]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_1 "bRegPortOutLcl[Data][17]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_2 "bRegPortOutLcl[Data][17]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_3 "bRegPortOutLcl[Data][17]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__17__i_4 "bRegPortOutLcl[Data][17]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_1 "bRegPortOutLcl[Data][18]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_2 "bRegPortOutLcl[Data][18]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_3 "bRegPortOutLcl[Data][18]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__18__i_4 "bRegPortOutLcl[Data][18]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_1 "bRegPortOutLcl[Data][19]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_2 "bRegPortOutLcl[Data][19]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_3 "bRegPortOutLcl[Data][19]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__19__i_4 "bRegPortOutLcl[Data][19]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_1 "bRegPortOutLcl[Data][1]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_2 "bRegPortOutLcl[Data][1]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_3 "bRegPortOutLcl[Data][1]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_4 "bRegPortOutLcl[Data][1]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__1__i_5 "bRegPortOutLcl[Data][1]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_1 "bRegPortOutLcl[Data][20]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_2 "bRegPortOutLcl[Data][20]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_3 "bRegPortOutLcl[Data][20]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__20__i_4 "bRegPortOutLcl[Data][20]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_1 "bRegPortOutLcl[Data][21]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_2 "bRegPortOutLcl[Data][21]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_3 "bRegPortOutLcl[Data][21]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__21__i_4 "bRegPortOutLcl[Data][21]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_1 "bRegPortOutLcl[Data][22]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_2 "bRegPortOutLcl[Data][22]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_3 "bRegPortOutLcl[Data][22]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__22__i_4 "bRegPortOutLcl[Data][22]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_1 "bRegPortOutLcl[Data][23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_2 "bRegPortOutLcl[Data][23]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_3 "bRegPortOutLcl[Data][23]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__23__i_4 "bRegPortOutLcl[Data][23]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_1 "bRegPortOutLcl[Data][24]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_2 "bRegPortOutLcl[Data][24]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_3 "bRegPortOutLcl[Data][24]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__24__i_4 "bRegPortOutLcl[Data][24]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_1 "bRegPortOutLcl[Data][25]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFEAA")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_2 "bRegPortOutLcl[Data][25]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_3 "bRegPortOutLcl[Data][25]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000100000000000")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_4 "bRegPortOutLcl[Data][25]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__25__i_5 "bRegPortOutLcl[Data][25]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_1 "bRegPortOutLcl[Data][26]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_2 "bRegPortOutLcl[Data][26]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_3 "bRegPortOutLcl[Data][26]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0020000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_4 "bRegPortOutLcl[Data][26]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__26__i_5 "bRegPortOutLcl[Data][26]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_1 "bRegPortOutLcl[Data][27]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFEA")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_2 "bRegPortOutLcl[Data][27]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_3 "bRegPortOutLcl[Data][27]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000200000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_4 "bRegPortOutLcl[Data][27]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000120000000000")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_5 "bRegPortOutLcl[Data][27]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_6 "bRegPortOutLcl[Data][27]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__27__i_7 "bRegPortOutLcl[Data][27]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0040000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_1 "bRegPortOutLcl[Data][28]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_10 "bRegPortOutLcl[Data][28]_i_10") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_2 "bRegPortOutLcl[Data][28]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_3 "bRegPortOutLcl[Data][28]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_4 "bRegPortOutLcl[Data][28]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0004000C00000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_5 "bRegPortOutLcl[Data][28]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_6 "bRegPortOutLcl[Data][28]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_7 "bRegPortOutLcl[Data][28]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0040")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_8 "bRegPortOutLcl[Data][28]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__28__i_9 "bRegPortOutLcl[Data][28]_i_9") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h1")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_1 "bRegPortOutLcl[Data][29]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_2 "bRegPortOutLcl[Data][29]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_3 "bRegPortOutLcl[Data][29]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__29__i_4 "bRegPortOutLcl[Data][29]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_1 "bRegPortOutLcl[Data][2]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_2 "bRegPortOutLcl[Data][2]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_3 "bRegPortOutLcl[Data][2]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_4 "bRegPortOutLcl[Data][2]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__2__i_5 "bRegPortOutLcl[Data][2]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_1 "bRegPortOutLcl[Data][30]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_2 "bRegPortOutLcl[Data][30]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_3 "bRegPortOutLcl[Data][30]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_4 "bRegPortOutLcl[Data][30]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000002000000000")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_5 "bRegPortOutLcl[Data][30]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__30__i_6 "bRegPortOutLcl[Data][30]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000004000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_1 "bRegPortOutLcl[Data][31]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hFE")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_10 "bRegPortOutLcl[Data][31]_i_10") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_11 "bRegPortOutLcl[Data][31]_i_11") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0800000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_12 "bRegPortOutLcl[Data][31]_i_12") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h8")) + (property SOFT_HLUTNM (string "soft_lutpair23")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_2 "bRegPortOutLcl[Data][31]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_3 "bRegPortOutLcl[Data][31]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_4 "bRegPortOutLcl[Data][31]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_5 "bRegPortOutLcl[Data][31]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0010000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_6 "bRegPortOutLcl[Data][31]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000800000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_7 "bRegPortOutLcl[Data][31]_i_7") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_8 "bRegPortOutLcl[Data][31]_i_8") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000200000000000")) + ) + (instance (rename bRegPortOutLcl_Data__31__i_9 "bRegPortOutLcl[Data][31]_i_9") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000020000000000")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_1 "bRegPortOutLcl[Data][3]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_2 "bRegPortOutLcl[Data][3]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_3 "bRegPortOutLcl[Data][3]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_4 "bRegPortOutLcl[Data][3]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__3__i_5 "bRegPortOutLcl[Data][3]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_1 "bRegPortOutLcl[Data][4]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_2 "bRegPortOutLcl[Data][4]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_3 "bRegPortOutLcl[Data][4]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_4 "bRegPortOutLcl[Data][4]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_5 "bRegPortOutLcl[Data][4]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0001000000000000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_6 "bRegPortOutLcl[Data][4]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h000000C00000E000")) + ) + (instance (rename bRegPortOutLcl_Data__4__i_7 "bRegPortOutLcl[Data][4]_i_7") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_1 "bRegPortOutLcl[Data][5]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFFFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_2 "bRegPortOutLcl[Data][5]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFF88F888F888F8")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_3 "bRegPortOutLcl[Data][5]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_4 "bRegPortOutLcl[Data][5]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__5__i_5 "bRegPortOutLcl[Data][5]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_1 "bRegPortOutLcl[Data][6]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFFFFFEFEFE")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_2 "bRegPortOutLcl[Data][6]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_3 "bRegPortOutLcl[Data][6]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_4 "bRegPortOutLcl[Data][6]_i_4") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'hF8")) + (property SOFT_HLUTNM (string "soft_lutpair21")) + ) + (instance (rename bRegPortOutLcl_Data__6__i_5 "bRegPortOutLcl[Data][6]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_1 "bRegPortOutLcl[Data][7]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_2 "bRegPortOutLcl[Data][7]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_3 "bRegPortOutLcl[Data][7]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_4 "bRegPortOutLcl[Data][7]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_5 "bRegPortOutLcl[Data][7]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__7__i_6 "bRegPortOutLcl[Data][7]_i_6") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h0000000000008000")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_1 "bRegPortOutLcl[Data][8]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_2 "bRegPortOutLcl[Data][8]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_3 "bRegPortOutLcl[Data][8]_i_3") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_4 "bRegPortOutLcl[Data][8]_i_4") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hF888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_5 "bRegPortOutLcl[Data][8]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__8__i_6 "bRegPortOutLcl[Data][8]_i_6") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h8000")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_1 "bRegPortOutLcl[Data][9]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFFFE")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_2 "bRegPortOutLcl[Data][9]_i_2") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_3 "bRegPortOutLcl[Data][9]_i_3") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF88F8")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_4 "bRegPortOutLcl[Data][9]_i_4") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'h88F8888888888888")) + ) + (instance (rename bRegPortOutLcl_Data__9__i_5 "bRegPortOutLcl[Data][9]_i_5") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFF888F888F888")) + ) + (instance (rename bRegPortOutLcl_reg_Data__0_ "bRegPortOutLcl_reg[Data][0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__10_ "bRegPortOutLcl_reg[Data][10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__11_ "bRegPortOutLcl_reg[Data][11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__12_ "bRegPortOutLcl_reg[Data][12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__13_ "bRegPortOutLcl_reg[Data][13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__14_ "bRegPortOutLcl_reg[Data][14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__15_ "bRegPortOutLcl_reg[Data][15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__16_ "bRegPortOutLcl_reg[Data][16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__17_ "bRegPortOutLcl_reg[Data][17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__18_ "bRegPortOutLcl_reg[Data][18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__19_ "bRegPortOutLcl_reg[Data][19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__1_ "bRegPortOutLcl_reg[Data][1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__20_ "bRegPortOutLcl_reg[Data][20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__21_ "bRegPortOutLcl_reg[Data][21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__22_ "bRegPortOutLcl_reg[Data][22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__23_ "bRegPortOutLcl_reg[Data][23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__24_ "bRegPortOutLcl_reg[Data][24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__25_ "bRegPortOutLcl_reg[Data][25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__26_ "bRegPortOutLcl_reg[Data][26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__27_ "bRegPortOutLcl_reg[Data][27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__28_ "bRegPortOutLcl_reg[Data][28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__29_ "bRegPortOutLcl_reg[Data][29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__2_ "bRegPortOutLcl_reg[Data][2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__30_ "bRegPortOutLcl_reg[Data][30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__31_ "bRegPortOutLcl_reg[Data][31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__3_ "bRegPortOutLcl_reg[Data][3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__4_ "bRegPortOutLcl_reg[Data][4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__5_ "bRegPortOutLcl_reg[Data][5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__6_ "bRegPortOutLcl_reg[Data][6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__7_ "bRegPortOutLcl_reg[Data][7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__8_ "bRegPortOutLcl_reg[Data][8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRegPortOutLcl_reg_Data__9_ "bRegPortOutLcl_reg[Data][9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance bResetTdc_i_1 (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFEFFFFFFFEEEEEE")) + ) + (instance bResetTdc_reg (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename bRpOffsetStored_0__i_1 "bRpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bRpOffsetStored_10__i_1 "bRpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_11__i_1 "bRpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_12__i_1 "bRpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair43")) + ) + (instance (rename bRpOffsetStored_13__i_1 "bRpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_14__i_1 "bRpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair42")) + ) + (instance (rename bRpOffsetStored_15__i_1 "bRpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_16__i_1 "bRpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair41")) + ) + (instance (rename bRpOffsetStored_17__i_1 "bRpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_18__i_1 "bRpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair40")) + ) + (instance (rename bRpOffsetStored_19__i_1 "bRpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_1__i_1 "bRpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_20__i_1 "bRpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair39")) + ) + (instance (rename bRpOffsetStored_21__i_1 "bRpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_22__i_1 "bRpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair38")) + ) + (instance (rename bRpOffsetStored_23__i_1 "bRpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_24__i_1 "bRpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair37")) + ) + (instance (rename bRpOffsetStored_25__i_1 "bRpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_26__i_1 "bRpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair36")) + ) + (instance (rename bRpOffsetStored_27__i_1 "bRpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_28__i_1 "bRpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair35")) + ) + (instance (rename bRpOffsetStored_29__i_1 "bRpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_2__i_1 "bRpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair48")) + ) + (instance (rename bRpOffsetStored_30__i_1 "bRpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair34")) + ) + (instance (rename bRpOffsetStored_31__i_1 "bRpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_32__i_1 "bRpOffsetStored[32]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair33")) + ) + (instance (rename bRpOffsetStored_33__i_1 "bRpOffsetStored[33]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_34__i_1 "bRpOffsetStored[34]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair32")) + ) + (instance (rename bRpOffsetStored_35__i_1 "bRpOffsetStored[35]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_36__i_1 "bRpOffsetStored[36]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair31")) + ) + (instance (rename bRpOffsetStored_37__i_1 "bRpOffsetStored[37]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_38__i_1 "bRpOffsetStored[38]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair30")) + ) + (instance (rename bRpOffsetStored_39__i_1 "bRpOffsetStored[39]_i_1") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'hFFFF8000")) + ) + (instance (rename bRpOffsetStored_39__i_2 "bRpOffsetStored[39]_i_2") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair29")) + ) + (instance (rename bRpOffsetStored_39__i_3 "bRpOffsetStored[39]_i_3") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0008")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + ) + (instance (rename bRpOffsetStored_39__i_4 "bRpOffsetStored[39]_i_4") (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h00000004")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + ) + (instance (rename bRpOffsetStored_3__i_1 "bRpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_4__i_1 "bRpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair47")) + ) + (instance (rename bRpOffsetStored_5__i_1 "bRpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_6__i_1 "bRpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair46")) + ) + (instance (rename bRpOffsetStored_7__i_1 "bRpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_8__i_1 "bRpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair45")) + ) + (instance (rename bRpOffsetStored_9__i_1 "bRpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair44")) + ) + (instance (rename bRpOffsetStored_reg_0_ "bRpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_10_ "bRpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_11_ "bRpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_12_ "bRpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_13_ "bRpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_14_ "bRpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_15_ "bRpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_16_ "bRpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_17_ "bRpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_18_ "bRpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_19_ "bRpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_1_ "bRpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_20_ "bRpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_21_ "bRpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_22_ "bRpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_23_ "bRpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_24_ "bRpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_25_ "bRpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_26_ "bRpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_27_ "bRpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_28_ "bRpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_29_ "bRpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_2_ "bRpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_30_ "bRpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_31_ "bRpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_32_ "bRpOffsetStored_reg[32]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_33_ "bRpOffsetStored_reg[33]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_34_ "bRpOffsetStored_reg[34]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_35_ "bRpOffsetStored_reg[35]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_36_ "bRpOffsetStored_reg[36]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_37_ "bRpOffsetStored_reg[37]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_38_ "bRpOffsetStored_reg[38]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_39_ "bRpOffsetStored_reg[39]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_3_ "bRpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_4_ "bRpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_5_ "bRpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_6_ "bRpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_7_ "bRpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_8_ "bRpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bRpOffsetStored_reg_9_ "bRpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_0__i_1 "bScratch[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_10__i_1 "bScratch[10]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_11__i_1 "bScratch[11]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_12__i_1 "bScratch[12]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_13__i_1 "bScratch[13]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_14__i_1 "bScratch[14]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair17")) + ) + (instance (rename bScratch_15__i_1 "bScratch[15]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_1__i_1 "bScratch[1]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair6")) + ) + (instance (rename bScratch_20__i_1 "bScratch[20]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair16")) + ) + (instance (rename bScratch_21__i_1 "bScratch[21]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_22__i_1 "bScratch[22]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair14")) + ) + (instance (rename bScratch_23__i_1 "bScratch[23]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair20")) + ) + (instance (rename bScratch_24__i_1 "bScratch[24]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair28")) + ) + (instance (rename bScratch_28__i_1 "bScratch[28]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_29__i_1 "bScratch[29]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair19")) + ) + (instance (rename bScratch_2__i_1 "bScratch[2]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair7")) + ) + (instance (rename bScratch_30__i_1 "bScratch[30]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_31__i_1 "bScratch[31]_i_1") (viewref netlist (cellref LUT6 (libraryref hdi_primitives))) + (property INIT (string "64'hFFFFFFFF00800000")) + ) + (instance (rename bScratch_31__i_2 "bScratch[31]_i_2") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_31__i_3 "bScratch[31]_i_3") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h40")) + (property SOFT_HLUTNM (string "soft_lutpair27")) + ) + (instance (rename bScratch_31__i_4 "bScratch[31]_i_4") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair26")) + ) + (instance (rename bScratch_31__i_5 "bScratch[31]_i_5") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + ) + (instance (rename bScratch_3__i_1 "bScratch[3]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair9")) + ) + (instance (rename bScratch_4__i_1 "bScratch[4]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair15")) + ) + (instance (rename bScratch_5__i_1 "bScratch[5]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair10")) + ) + (instance (rename bScratch_6__i_1 "bScratch[6]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair11")) + ) + (instance (rename bScratch_7__i_1 "bScratch[7]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair12")) + ) + (instance (rename bScratch_8__i_1 "bScratch[8]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair18")) + ) + (instance (rename bScratch_9__i_1 "bScratch[9]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h02")) + (property SOFT_HLUTNM (string "soft_lutpair13")) + ) + (instance (rename bScratch_reg_0_ "bScratch_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_10_ "bScratch_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_11_ "bScratch_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_12_ "bScratch_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_13_ "bScratch_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_14_ "bScratch_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_15_ "bScratch_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_16_ "bScratch_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_17_ "bScratch_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_18_ "bScratch_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_19_ "bScratch_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_1_ "bScratch_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_20_ "bScratch_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_21_ "bScratch_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_22_ "bScratch_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_23_ "bScratch_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_24_ "bScratch_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_25_ "bScratch_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_26_ "bScratch_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_27_ "bScratch_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_28_ "bScratch_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_29_ "bScratch_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_2_ "bScratch_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_30_ "bScratch_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_31_ "bScratch_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_3_ "bScratch_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_4_ "bScratch_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_5_ "bScratch_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_6_ "bScratch_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_7_ "bScratch_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_8_ "bScratch_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bScratch_reg_9_ "bScratch_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_0__i_1 "bSpOffsetStored[0]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + ) + (instance (rename bSpOffsetStored_10__i_1 "bSpOffsetStored[10]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_11__i_1 "bSpOffsetStored[11]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_12__i_1 "bSpOffsetStored[12]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair59")) + ) + (instance (rename bSpOffsetStored_13__i_1 "bSpOffsetStored[13]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_14__i_1 "bSpOffsetStored[14]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair58")) + ) + (instance (rename bSpOffsetStored_15__i_1 "bSpOffsetStored[15]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_16__i_1 "bSpOffsetStored[16]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair57")) + ) + (instance (rename bSpOffsetStored_17__i_1 "bSpOffsetStored[17]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_18__i_1 "bSpOffsetStored[18]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair56")) + ) + (instance (rename bSpOffsetStored_19__i_1 "bSpOffsetStored[19]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_1__i_1 "bSpOffsetStored[1]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_20__i_1 "bSpOffsetStored[20]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair55")) + ) + (instance (rename bSpOffsetStored_21__i_1 "bSpOffsetStored[21]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_22__i_1 "bSpOffsetStored[22]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair54")) + ) + (instance (rename bSpOffsetStored_23__i_1 "bSpOffsetStored[23]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_24__i_1 "bSpOffsetStored[24]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair53")) + ) + (instance (rename bSpOffsetStored_25__i_1 "bSpOffsetStored[25]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_26__i_1 "bSpOffsetStored[26]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair52")) + ) + (instance (rename bSpOffsetStored_27__i_1 "bSpOffsetStored[27]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_28__i_1 "bSpOffsetStored[28]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair51")) + ) + (instance (rename bSpOffsetStored_29__i_1 "bSpOffsetStored[29]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_2__i_1 "bSpOffsetStored[2]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair64")) + ) + (instance (rename bSpOffsetStored_30__i_1 "bSpOffsetStored[30]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair50")) + ) + (instance (rename bSpOffsetStored_31__i_1 "bSpOffsetStored[31]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair49")) + ) + (instance (rename bSpOffsetStored_3__i_1 "bSpOffsetStored[3]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_4__i_1 "bSpOffsetStored[4]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair63")) + ) + (instance (rename bSpOffsetStored_5__i_1 "bSpOffsetStored[5]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_6__i_1 "bSpOffsetStored[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair62")) + ) + (instance (rename bSpOffsetStored_7__i_1 "bSpOffsetStored[7]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_8__i_1 "bSpOffsetStored[8]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair61")) + ) + (instance (rename bSpOffsetStored_9__i_1 "bSpOffsetStored[9]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'h2")) + (property SOFT_HLUTNM (string "soft_lutpair60")) + ) + (instance (rename bSpOffsetStored_reg_0_ "bSpOffsetStored_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_10_ "bSpOffsetStored_reg[10]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_11_ "bSpOffsetStored_reg[11]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_12_ "bSpOffsetStored_reg[12]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_13_ "bSpOffsetStored_reg[13]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_14_ "bSpOffsetStored_reg[14]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_15_ "bSpOffsetStored_reg[15]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_16_ "bSpOffsetStored_reg[16]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_17_ "bSpOffsetStored_reg[17]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_18_ "bSpOffsetStored_reg[18]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_19_ "bSpOffsetStored_reg[19]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_1_ "bSpOffsetStored_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_20_ "bSpOffsetStored_reg[20]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_21_ "bSpOffsetStored_reg[21]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_22_ "bSpOffsetStored_reg[22]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_23_ "bSpOffsetStored_reg[23]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_24_ "bSpOffsetStored_reg[24]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_25_ "bSpOffsetStored_reg[25]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_26_ "bSpOffsetStored_reg[26]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_27_ "bSpOffsetStored_reg[27]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_28_ "bSpOffsetStored_reg[28]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_29_ "bSpOffsetStored_reg[29]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_2_ "bSpOffsetStored_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_30_ "bSpOffsetStored_reg[30]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_31_ "bSpOffsetStored_reg[31]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_3_ "bSpOffsetStored_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_4_ "bSpOffsetStored_reg[4]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_5_ "bSpOffsetStored_reg[5]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_6_ "bSpOffsetStored_reg[6]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_7_ "bSpOffsetStored_reg[7]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_8_ "bSpOffsetStored_reg[8]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename bSpOffsetStored_reg_9_ "bSpOffsetStored_reg[9]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_0_ "rPulserEnableDelayVal_reg[0]") (viewref netlist (cellref FDPE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + ) + (instance (rename rPulserEnableDelayVal_reg_1_ "rPulserEnableDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_2_ "rPulserEnableDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename rPulserEnableDelayVal_reg_3_ "rPulserEnableDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_0_ "sPpsClkCrossDelayVal_reg[0]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_1_ "sPpsClkCrossDelayVal_reg[1]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_2_ "sPpsClkCrossDelayVal_reg[2]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (instance (rename sPpsClkCrossDelayVal_reg_3_ "sPpsClkCrossDelayVal_reg[3]") (viewref netlist (cellref FDCE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + ) + (net (rename &_const0_ "") (joined + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref G (instanceref GND)) + (portref (member bRegPortOutFlat 32)) + (portref (member rRePulseHighTimeInRClks 0)) + (portref (member rRpHighTimeInRClks 0)) + (portref (member rRptHighTimeInRClks 0)) + (portref (member sSpHighTimeInSClks 0)) + (portref (member sSptHighTimeInSClks 0)) + ) + ) + (net (rename &_const1_ "") (joined + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_30__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_31__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_32__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_33__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CE (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CE (instanceref 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RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref C 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SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref aTdcResetLcl_reg)) + (portref C (instanceref aTdcResetLcl_reg_rep)) + (portref C (instanceref aTdcResetLcl_reg_rep__0)) + (portref C (instanceref aTdcResetLcl_reg_rep__1)) + (portref C (instanceref aTdcResetLcl_reg_rep__2)) + (portref C (instanceref aTdcResetLcl_reg_rep__3)) + (portref C (instanceref bClearTdcRegs_reg)) + (portref C (instanceref bEnableTdc_reg)) + (portref C (instanceref bOffsetUpdated_reg)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref C (instanceref bPpsClkCrossEn_reg)) + (portref C (instanceref bPulserEnableDelayVal_reg_0_)) + (portref C (instanceref bPulserEnableDelayVal_reg_1_)) + (portref C (instanceref bPulserEnableDelayVal_reg_2_)) + (portref C (instanceref bPulserEnableDelayVal_reg_3_)) + (portref C (instanceref bPushPpsDelayVal_reg)) + (portref C (instanceref bPushPulserEnableDelayVal_reg)) + (portref C (instanceref bReRunEnable_reg)) + (portref C (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__17_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__18_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__19_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__1_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__20_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__21_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__22_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__23_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__24_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__25_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__26_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__27_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__28_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref C (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref C (instanceref bResetTdc_reg)) + (portref C (instanceref bRpOffsetStored_reg_0_)) + (portref C (instanceref bRpOffsetStored_reg_10_)) + (portref C (instanceref bRpOffsetStored_reg_11_)) + (portref C (instanceref bRpOffsetStored_reg_12_)) + (portref C (instanceref bRpOffsetStored_reg_13_)) + (portref C (instanceref bRpOffsetStored_reg_14_)) + (portref C (instanceref bRpOffsetStored_reg_15_)) + (portref C (instanceref bRpOffsetStored_reg_16_)) + (portref C (instanceref bRpOffsetStored_reg_17_)) + (portref C (instanceref bRpOffsetStored_reg_18_)) + (portref C (instanceref bRpOffsetStored_reg_19_)) + (portref C (instanceref bRpOffsetStored_reg_1_)) + (portref C (instanceref bRpOffsetStored_reg_20_)) + (portref C (instanceref bRpOffsetStored_reg_21_)) + (portref C (instanceref bRpOffsetStored_reg_22_)) + (portref C (instanceref bRpOffsetStored_reg_23_)) + (portref C (instanceref bRpOffsetStored_reg_24_)) + (portref C (instanceref bRpOffsetStored_reg_25_)) + (portref C (instanceref bRpOffsetStored_reg_26_)) + (portref C (instanceref bRpOffsetStored_reg_27_)) + (portref C (instanceref bRpOffsetStored_reg_28_)) + (portref C (instanceref bRpOffsetStored_reg_29_)) + (portref C (instanceref bRpOffsetStored_reg_2_)) + (portref C (instanceref bRpOffsetStored_reg_30_)) + (portref C (instanceref bRpOffsetStored_reg_31_)) + (portref C (instanceref bRpOffsetStored_reg_32_)) + (portref C (instanceref bRpOffsetStored_reg_33_)) + (portref C (instanceref bRpOffsetStored_reg_34_)) + (portref C (instanceref bRpOffsetStored_reg_35_)) + (portref C (instanceref bRpOffsetStored_reg_36_)) + (portref C (instanceref bRpOffsetStored_reg_37_)) + (portref C (instanceref bRpOffsetStored_reg_38_)) + (portref C (instanceref bRpOffsetStored_reg_39_)) + (portref C (instanceref bRpOffsetStored_reg_3_)) + (portref C (instanceref bRpOffsetStored_reg_4_)) + (portref C (instanceref bRpOffsetStored_reg_5_)) + (portref C (instanceref bRpOffsetStored_reg_6_)) + (portref C (instanceref bRpOffsetStored_reg_7_)) + (portref C (instanceref bRpOffsetStored_reg_8_)) + (portref C (instanceref bRpOffsetStored_reg_9_)) + (portref C (instanceref bScratch_reg_0_)) + (portref C (instanceref bScratch_reg_10_)) + (portref C (instanceref bScratch_reg_11_)) + (portref C (instanceref bScratch_reg_12_)) + (portref C (instanceref bScratch_reg_13_)) + (portref C (instanceref bScratch_reg_14_)) + (portref C (instanceref bScratch_reg_15_)) + (portref C (instanceref bScratch_reg_16_)) + (portref C (instanceref bScratch_reg_17_)) + (portref C (instanceref bScratch_reg_18_)) + (portref C (instanceref bScratch_reg_19_)) + (portref C (instanceref bScratch_reg_1_)) + (portref C (instanceref bScratch_reg_20_)) + (portref C (instanceref bScratch_reg_21_)) + (portref C (instanceref bScratch_reg_22_)) + (portref C (instanceref bScratch_reg_23_)) + (portref C (instanceref bScratch_reg_24_)) + (portref C (instanceref bScratch_reg_25_)) + (portref C (instanceref bScratch_reg_26_)) + (portref C (instanceref bScratch_reg_27_)) + (portref C (instanceref bScratch_reg_28_)) + (portref C (instanceref bScratch_reg_29_)) + (portref C (instanceref bScratch_reg_2_)) + (portref C (instanceref bScratch_reg_30_)) + (portref C (instanceref bScratch_reg_31_)) + (portref C (instanceref bScratch_reg_3_)) + (portref C (instanceref bScratch_reg_4_)) + (portref C (instanceref bScratch_reg_5_)) + (portref C (instanceref bScratch_reg_6_)) + (portref C (instanceref bScratch_reg_7_)) + (portref C (instanceref bScratch_reg_8_)) + (portref C (instanceref bScratch_reg_9_)) + (portref C (instanceref bSpOffsetStored_reg_0_)) + (portref C (instanceref bSpOffsetStored_reg_10_)) + (portref C (instanceref bSpOffsetStored_reg_11_)) + (portref C (instanceref bSpOffsetStored_reg_12_)) + (portref C (instanceref bSpOffsetStored_reg_13_)) + (portref C (instanceref bSpOffsetStored_reg_14_)) + (portref C (instanceref bSpOffsetStored_reg_15_)) + (portref C (instanceref bSpOffsetStored_reg_16_)) + (portref C (instanceref bSpOffsetStored_reg_17_)) + (portref C (instanceref bSpOffsetStored_reg_18_)) + (portref C (instanceref bSpOffsetStored_reg_19_)) + (portref C (instanceref bSpOffsetStored_reg_1_)) + (portref C (instanceref bSpOffsetStored_reg_20_)) + (portref C (instanceref bSpOffsetStored_reg_21_)) + (portref C (instanceref bSpOffsetStored_reg_22_)) + (portref C (instanceref bSpOffsetStored_reg_23_)) + (portref C (instanceref bSpOffsetStored_reg_24_)) + (portref C (instanceref bSpOffsetStored_reg_25_)) + (portref C (instanceref bSpOffsetStored_reg_26_)) + (portref C (instanceref bSpOffsetStored_reg_27_)) + (portref C (instanceref bSpOffsetStored_reg_28_)) + (portref C (instanceref bSpOffsetStored_reg_29_)) + (portref C (instanceref bSpOffsetStored_reg_2_)) + (portref C (instanceref bSpOffsetStored_reg_30_)) + (portref C (instanceref bSpOffsetStored_reg_31_)) + (portref C (instanceref bSpOffsetStored_reg_3_)) + (portref C (instanceref bSpOffsetStored_reg_4_)) + (portref C (instanceref bSpOffsetStored_reg_5_)) + (portref C (instanceref bSpOffsetStored_reg_6_)) + (portref C (instanceref bSpOffsetStored_reg_7_)) + (portref C (instanceref bSpOffsetStored_reg_8_)) + (portref C (instanceref bSpOffsetStored_reg_9_)) + (portref BusClk) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "EnableTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename EnableTdcDs_DoubleSyncBasex_iDlySig "EnableTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename Gen0_FDCEx_i_1__10_n_0 "Gen0.FDCEx_i_1__10_n_0") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__10)) + ) + ) + (net (rename Gen0_FDCEx_i_1__11_n_0 "Gen0.FDCEx_i_1__11_n_0") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__11)) + ) + ) + (net (rename Gen0_FDCEx_i_1__9_n_0 "Gen0.FDCEx_i_1__9_n_0") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__9)) + ) + ) + (net (rename Gen0_FDCEx_i_3__0_n_0 "Gen0.FDCEx_i_3__0_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__2)) + (portref I3 (instanceref Gen0_FDCEx_i_1__1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__2)) + (portref O (instanceref Gen0_FDCEx_i_3__0)) + ) + ) + (net (rename Gen0_FDCEx_i_3__1_n_0 "Gen0.FDCEx_i_3__1_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1__3)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__4)) + (portref I3 (instanceref Gen0_FDCEx_i_1__3)) + (portref I3 (instanceref Gen0_FDCEx_i_1__4)) + (portref O (instanceref Gen0_FDCEx_i_3__1)) + ) + ) + (net (rename Gen0_FDCEx_i_3_n_0 "Gen0.FDCEx_i_3_n_0") (joined + (portref I0 (instanceref BlkIn_iDlyPush_i_1)) + (portref I0 (instanceref BlkIn_iDlyPush_i_1__0)) + (portref I3 (instanceref Gen0_FDCEx_i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_1__0)) + (portref O (instanceref Gen0_FDCEx_i_3)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__10_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__11_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__12_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__13_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__14_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__15_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__16_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__17_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__18_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__19_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__20_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__21_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__22_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__23_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__24_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__25_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__26_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__27_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__28_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__29_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__30_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__31_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__32_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__33_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__34_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__35_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__36_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__37_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__38_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__39_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__40_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[40]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__41_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[41]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__42_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[42]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__43_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[43]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__44_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[44]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__45_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[45]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__46_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[46]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__47_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[47]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__48_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[48]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__49_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[49]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__4_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__50_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[50]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__51_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[51]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__52_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[52]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__53_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[53]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__54_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[54]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__55_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[55]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__56_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[56]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__57_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[57]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__58_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[58]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__59_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[59]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__5_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__60_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[60]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__61_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[61]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__62_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[62]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__63_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[63]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__64_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[64]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__65_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[65]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__66_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[66]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__67_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[67]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__68_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[68]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__69_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[69]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__6_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__70_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[70]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__71_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[71]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__72_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[72]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__73_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[73]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__74_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[74]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__75_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[75]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__76_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[76]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__77_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[77]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__78_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[78]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__79_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[79]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__7_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__8_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_n_0__9_ "IncomingOffsetHs/HBx/BlkIn.iLclStoredData_reg_n_0_[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg_n_0 "IncomingOffsetHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iDlyPush "IncomingOffsetHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__11)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggle "IncomingOffsetHs/HBx/iPushToggle") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__1)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_iPushToggleNx "IncomingOffsetHs/HBx/iPushToggleNx") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__1)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle0_ms "IncomingOffsetHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggle1 "IncomingOffsetHs/HBx/oPushToggle1") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__7)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename IncomingOffsetHs_HBx_oPushToggleChanged "IncomingOffsetHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__7)) + ) + ) + (net MeasClk (joined + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref C (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref MeasClk) + ) + ) + (net (rename OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[0].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[10].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[11].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[12].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[13].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[14].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[15].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[16].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[17].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[18].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[19].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[1].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined 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OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[69].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[6].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[70].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[71].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[72].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[73].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[74].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[75].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[76].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[77].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[78].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[79].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[7].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[8].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_ms "OffsetsDsGen[9].OffsetsDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_ms "OffsetsValidDs/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCapturedDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCapturedDs_DoubleSyncBasex_iDlySig "PpsCapturedDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "PpsCrossEnDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsCrossEnDs_DoubleSyncBasex_iDlySig "PpsCrossEnDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PpsDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iDlyPush "PpsDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggle "PpsDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_iPushToggleNx "PpsDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle0_ms "PpsDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggle1 "PpsDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__5)) + (portref Q (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PpsDelayValCrossingHs_HBx_oPushToggleChanged "PpsDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__5)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__0_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__1_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__2_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_n_0__3_ "PulserEnableDelayValCrossingHs/HBx/BlkIn.iLclStoredData_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oDataValid_reg_n_0") (joined + (portref CE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg_n_0 "PulserEnableDelayValCrossingHs/HBx/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iDlyPush "PulserEnableDelayValCrossingHs/HBx/iDlyPush") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggle "PulserEnableDelayValCrossingHs/HBx/iPushToggle") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__0)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_iPushToggleNx "PulserEnableDelayValCrossingHs/HBx/iPushToggleNx") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__0)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle0_ms "PulserEnableDelayValCrossingHs/HBx/oPushToggle0_ms") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggle1 "PulserEnableDelayValCrossingHs/HBx/oPushToggle1") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__6)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename PulserEnableDelayValCrossingHs_HBx_oPushToggleChanged "PulserEnableDelayValCrossingHs/HBx/oPushToggleChanged") (joined + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref O (instanceref Gen0_FDCEx_i_1__6)) + ) + ) + (net (rename RePulse1CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse1CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__2)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse1CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse1CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse1CntHs_iPushPulse "RePulse1CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__2)) + ) + ) + (net (rename RePulse1CntHs_iPushToggle "RePulse1CntHs/iPushToggle") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__4)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_iPushToggleNx "RePulse1CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__4)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle0_ms "RePulse1CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggle1 "RePulse1CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__8)) + (portref Q (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse1CntHs_oPushToggleChanged "RePulse1CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__8)) + ) + ) + (net (rename RePulse2CntHs_BlkIn_iDlyPush_reg_n_0 "RePulse2CntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RePulse2CntHs_BlkOut_oPushToggle2_reg_n_0 "RePulse2CntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RePulse2CntHs_iPushPulse "RePulse2CntHs/iPushPulse") (joined + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__1)) + ) + ) + (net (rename RePulse2CntHs_iPushToggle "RePulse2CntHs/iPushToggle") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__5)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_iPushToggleNx "RePulse2CntHs/iPushToggleNx") (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__5)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle0_ms "RePulse2CntHs/oPushToggle0_ms") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggle1 "RePulse2CntHs/oPushToggle1") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__1)) + (portref Q (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RePulse2CntHs_oPushToggleChanged "RePulse2CntHs/oPushToggleChanged") (joined + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__1)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[0].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[10].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[11].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[12].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[13].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[14].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[15].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[16].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[17].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[18].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[19].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[1].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[20].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[21].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[22].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[23].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[24].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[25].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[26].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[27].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[28].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[29].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[2].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[30].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[31].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[3].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[4].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[5].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[6].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[7].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[8].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt1ReadbackDsGen[9].RePulse1ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[0].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[10].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[11].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[12].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[13].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[14].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[15].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[16].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[17].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[18].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[19].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[1].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[20].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[21].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[22].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[23].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[24].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[25].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[26].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[27].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[28].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[29].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[2].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[30].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[31].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[3].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[4].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[5].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[6].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[7].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[8].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RePulseCnt2ReadbackDsGen[9].RePulse2ReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ReRunEnableDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ReRunEnableDs_DoubleSyncBasex_iDlySig "ReRunEnableDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net RefClk (joined + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref C (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref rPulserEnableDelayVal_reg_0_)) + (portref C (instanceref rPulserEnableDelayVal_reg_1_)) + (portref C (instanceref rPulserEnableDelayVal_reg_2_)) + (portref C (instanceref rPulserEnableDelayVal_reg_3_)) + (portref RefClk) + ) + ) + (net RegWrite53_out (joined + (portref D (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1)) + ) + ) + (net RegWrite54_out (joined + (portref D (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__0)) + ) + ) + (net RegWrite55_out (joined + (portref D (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__1)) + ) + ) + (net RegWrite56_out (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__2)) + ) + ) + (net RegWrite57_out (joined + (portref D (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__3)) + ) + ) + (net RegWrite58_out (joined + (portref D (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref O (instanceref BlkIn_iDlyPush_i_1__4)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetDoneDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetDoneDs_DoubleSyncBasex_iDlySig "ResetDoneDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetDoneDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetDoneDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_ms "ResetTdcDs/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename ResetTdcDs_DoubleSyncBasex_iDlySig "ResetTdcDs/DoubleSyncBasex/iDlySig") (joined + (portref D (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + ) + + (property RTL_KEEP (string "true")) + ) + (net (rename RpCntHs_BlkOut_oPushToggle2_reg_n_0 "RpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RpCntHs_iPushPulse "RpCntHs/iPushPulse") (joined + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__4)) + ) + ) + (net (rename RpCntHs_iPushToggle "RpCntHs/iPushToggle") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__2)) + (portref Q (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_iPushToggleNx "RpCntHs/iPushToggleNx") (joined + (portref D (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__2)) + ) + ) + (net (rename RpCntHs_oPushToggle0_ms "RpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggle1 "RpCntHs/oPushToggle1") (joined + (portref D (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1)) + (portref Q (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RpCntHs_oPushToggleChanged "RpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1)) + ) + ) + (net (rename RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[0].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[10].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[11].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[12].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[13].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[14].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[15].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[16].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[17].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[18].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[19].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[1].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[20].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[21].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[22].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[23].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[24].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[25].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[26].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[27].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[28].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[29].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[2].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[30].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[31].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[3].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[4].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[5].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[6].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[7].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[8].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RpCntReadbackDsGen[9].RpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_BlkIn_iDlyPush_reg_n_0 "RptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__0)) + (portref Q (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename RptCntHs_BlkOut_oPushToggle2_reg_n_0 "RptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename RptCntHs_iPushPulse "RptCntHs/iPushPulse") (joined + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__0)) + ) + ) + (net (rename RptCntHs_iPushToggle "RptCntHs/iPushToggle") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__6)) + (portref Q (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_iPushToggleNx "RptCntHs/iPushToggleNx") (joined + (portref D (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__6)) + ) + ) + (net (rename RptCntHs_oPushToggle0_ms "RptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggle1 "RptCntHs/oPushToggle1") (joined + (portref D (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__2)) + (portref Q (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename RptCntHs_oPushToggleChanged "RptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__2)) + ) + ) + (net (rename RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[0].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[10].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[11].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[12].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[13].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[14].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[15].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[16].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[17].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[18].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[19].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[1].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[20].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[21].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[22].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[23].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[24].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[25].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[26].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[27].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[28].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[29].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[2].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[30].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[31].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[3].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[4].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[5].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[6].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[7].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[8].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "RptCntReadbackDsGen[9].RptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net SampleClk (joined + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref C (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref C (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref C (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref SampleClk) + ) + ) + (net (rename SpCntHs_BlkIn_iDlyPush_reg_n_0 "SpCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__3)) + (portref Q (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SpCntHs_BlkOut_oPushToggle2_reg_n_0 "SpCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SpCntHs_iPushPulse "SpCntHs/iPushPulse") (joined + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1__3)) + ) + ) + (net (rename SpCntHs_iPushToggle "SpCntHs/iPushToggle") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__3)) + (portref Q (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_iPushToggleNx "SpCntHs/iPushToggleNx") (joined + (portref D (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__3)) + ) + ) + (net (rename SpCntHs_oPushToggle0_ms "SpCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggle1 "SpCntHs/oPushToggle1") (joined + (portref D (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__0)) + (portref Q (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SpCntHs_oPushToggleChanged "SpCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__0)) + ) + ) + (net (rename SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[0].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[10].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[11].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[12].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[13].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[14].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[15].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[16].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[17].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[18].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[19].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[1].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[20].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[21].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[22].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[23].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[24].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[25].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[26].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[27].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[28].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[29].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[2].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[30].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[31].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[3].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[4].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[5].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[6].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[7].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[8].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SpCntReadbackDsGen[9].SpCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_BlkIn_iDlyPush_reg_n_0 "SptCntHs/BlkIn.iDlyPush_reg_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_1)) + (portref Q (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net (rename SptCntHs_BlkOut_oPushToggle2_reg_n_0 "SptCntHs/BlkOut.oPushToggle2_reg_n_0") (joined + (portref I1 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + ) + ) + (net (rename SptCntHs_iPushPulse "SptCntHs/iPushPulse") (joined + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CE (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CE (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_1)) + ) + ) + (net (rename SptCntHs_iPushToggle "SptCntHs/iPushToggle") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I0 (instanceref Gen0_FDCEx_i_2__7)) + (portref Q (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_iPushToggleNx "SptCntHs/iPushToggleNx") (joined + (portref D (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref O (instanceref Gen0_FDCEx_i_2__7)) + ) + ) + (net (rename SptCntHs_oPushToggle0_ms "SptCntHs/oPushToggle0_ms") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggle1 "SptCntHs/oPushToggle1") (joined + (portref D (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref I0 (instanceref BlkOut_oDataValid_i_1__3)) + (portref Q (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + ) + ) + (net (rename SptCntHs_oPushToggleChanged "SptCntHs/oPushToggleChanged") (joined + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CE (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref O (instanceref BlkOut_oDataValid_i_1__3)) + ) + ) + (net (rename SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[0].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[10].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[11].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[12].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[13].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[14].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[15].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[16].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[17].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[18].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[19].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[1].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[20].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[21].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[22].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[23].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[24].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[25].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[26].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[27].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[28].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[29].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[2].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[30].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[31].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[3].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[4].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[5].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[6].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[7].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[8].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net (rename SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_ms "SptCntReadbackDsGen[9].SptCntReadbackDs/DoubleSyncAsyncInBasex/oSig_ms") (joined + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + ) + ) + (net aBusReset (joined + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PpsDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref CLR (instanceref ResetTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref CLR (instanceref aTdcResetLcl_reg)) + (portref CLR (instanceref aTdcResetLcl_reg_rep)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__0)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__1)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__2)) + (portref CLR (instanceref aTdcResetLcl_reg_rep__3)) + (portref CLR (instanceref bClearTdcRegs_reg)) + (portref CLR (instanceref bEnableTdc_reg)) + (portref CLR (instanceref bOffsetUpdated_reg)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref CLR (instanceref bPpsClkCrossEn_reg)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref bPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref bPushPpsDelayVal_reg)) + (portref CLR (instanceref bPushPulserEnableDelayVal_reg)) + (portref CLR (instanceref bReRunEnable_reg)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__0_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__10_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__11_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__12_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__13_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__14_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__15_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__16_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__17_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__18_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__19_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__1_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__20_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__21_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__22_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__23_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__24_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__25_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__26_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__27_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__28_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__30_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__31_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__4_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__5_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__6_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__7_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__8_)) + (portref CLR (instanceref bRegPortOutLcl_reg_Data__9_)) + (portref CLR (instanceref bRpOffsetStored_reg_0_)) + (portref CLR (instanceref bRpOffsetStored_reg_10_)) + (portref CLR (instanceref bRpOffsetStored_reg_11_)) + (portref CLR (instanceref bRpOffsetStored_reg_12_)) + (portref CLR (instanceref bRpOffsetStored_reg_13_)) + (portref CLR (instanceref bRpOffsetStored_reg_14_)) + (portref CLR (instanceref bRpOffsetStored_reg_15_)) + (portref CLR (instanceref bRpOffsetStored_reg_16_)) + (portref CLR (instanceref bRpOffsetStored_reg_17_)) + (portref CLR (instanceref bRpOffsetStored_reg_18_)) + (portref CLR (instanceref bRpOffsetStored_reg_19_)) + (portref CLR (instanceref bRpOffsetStored_reg_1_)) + (portref CLR (instanceref bRpOffsetStored_reg_20_)) + (portref CLR (instanceref bRpOffsetStored_reg_21_)) + (portref CLR (instanceref bRpOffsetStored_reg_22_)) + (portref CLR (instanceref bRpOffsetStored_reg_23_)) + (portref CLR (instanceref bRpOffsetStored_reg_24_)) + (portref CLR (instanceref bRpOffsetStored_reg_25_)) + (portref CLR (instanceref bRpOffsetStored_reg_26_)) + (portref CLR (instanceref bRpOffsetStored_reg_27_)) + (portref CLR (instanceref bRpOffsetStored_reg_28_)) + (portref CLR (instanceref bRpOffsetStored_reg_29_)) + (portref CLR (instanceref bRpOffsetStored_reg_2_)) + (portref CLR (instanceref bRpOffsetStored_reg_30_)) + (portref CLR (instanceref bRpOffsetStored_reg_31_)) + (portref CLR (instanceref bRpOffsetStored_reg_32_)) + (portref CLR (instanceref bRpOffsetStored_reg_33_)) + (portref CLR (instanceref bRpOffsetStored_reg_34_)) + (portref CLR (instanceref bRpOffsetStored_reg_35_)) + (portref CLR (instanceref bRpOffsetStored_reg_36_)) + (portref CLR (instanceref bRpOffsetStored_reg_37_)) + (portref CLR (instanceref bRpOffsetStored_reg_38_)) + (portref CLR (instanceref bRpOffsetStored_reg_39_)) + (portref CLR (instanceref bRpOffsetStored_reg_3_)) + (portref CLR (instanceref bRpOffsetStored_reg_4_)) + (portref CLR (instanceref bRpOffsetStored_reg_5_)) + (portref CLR (instanceref bRpOffsetStored_reg_6_)) + (portref CLR (instanceref bRpOffsetStored_reg_7_)) + (portref CLR (instanceref bRpOffsetStored_reg_8_)) + (portref CLR (instanceref bRpOffsetStored_reg_9_)) + (portref CLR (instanceref bScratch_reg_0_)) + (portref CLR (instanceref bScratch_reg_10_)) + (portref CLR (instanceref bScratch_reg_11_)) + (portref CLR (instanceref bScratch_reg_12_)) + (portref CLR (instanceref bScratch_reg_13_)) + (portref CLR (instanceref bScratch_reg_14_)) + (portref CLR (instanceref bScratch_reg_15_)) + (portref CLR (instanceref bScratch_reg_16_)) + (portref CLR (instanceref bScratch_reg_17_)) + (portref CLR (instanceref bScratch_reg_18_)) + (portref CLR (instanceref bScratch_reg_19_)) + (portref CLR (instanceref bScratch_reg_1_)) + (portref CLR (instanceref bScratch_reg_20_)) + (portref CLR (instanceref bScratch_reg_21_)) + (portref CLR (instanceref bScratch_reg_22_)) + (portref CLR (instanceref bScratch_reg_23_)) + (portref CLR (instanceref bScratch_reg_24_)) + (portref CLR (instanceref bScratch_reg_25_)) + (portref CLR (instanceref bScratch_reg_26_)) + (portref CLR (instanceref bScratch_reg_27_)) + (portref CLR (instanceref bScratch_reg_28_)) + (portref CLR (instanceref bScratch_reg_29_)) + (portref CLR (instanceref bScratch_reg_2_)) + (portref CLR (instanceref bScratch_reg_30_)) + (portref CLR (instanceref bScratch_reg_31_)) + (portref CLR (instanceref bScratch_reg_3_)) + (portref CLR (instanceref bScratch_reg_4_)) + (portref CLR (instanceref bScratch_reg_5_)) + (portref CLR (instanceref bScratch_reg_6_)) + (portref CLR (instanceref bScratch_reg_7_)) + (portref CLR (instanceref bScratch_reg_8_)) + (portref CLR (instanceref bScratch_reg_9_)) + (portref CLR (instanceref bSpOffsetStored_reg_0_)) + (portref CLR (instanceref bSpOffsetStored_reg_10_)) + (portref CLR (instanceref bSpOffsetStored_reg_11_)) + (portref CLR (instanceref bSpOffsetStored_reg_12_)) + (portref CLR (instanceref bSpOffsetStored_reg_13_)) + (portref CLR (instanceref bSpOffsetStored_reg_14_)) + (portref CLR (instanceref bSpOffsetStored_reg_15_)) + (portref CLR (instanceref bSpOffsetStored_reg_16_)) + (portref CLR (instanceref bSpOffsetStored_reg_17_)) + (portref CLR (instanceref bSpOffsetStored_reg_18_)) + (portref CLR (instanceref bSpOffsetStored_reg_19_)) + (portref CLR (instanceref bSpOffsetStored_reg_1_)) + (portref CLR (instanceref bSpOffsetStored_reg_20_)) + (portref CLR (instanceref bSpOffsetStored_reg_21_)) + (portref CLR (instanceref bSpOffsetStored_reg_22_)) + (portref CLR (instanceref bSpOffsetStored_reg_23_)) + (portref CLR (instanceref bSpOffsetStored_reg_24_)) + (portref CLR (instanceref bSpOffsetStored_reg_25_)) + (portref CLR (instanceref bSpOffsetStored_reg_26_)) + (portref CLR (instanceref bSpOffsetStored_reg_27_)) + (portref CLR (instanceref bSpOffsetStored_reg_28_)) + (portref CLR (instanceref bSpOffsetStored_reg_29_)) + (portref CLR (instanceref bSpOffsetStored_reg_2_)) + (portref CLR (instanceref bSpOffsetStored_reg_30_)) + (portref CLR (instanceref bSpOffsetStored_reg_31_)) + (portref CLR (instanceref bSpOffsetStored_reg_3_)) + (portref CLR (instanceref bSpOffsetStored_reg_4_)) + (portref CLR (instanceref bSpOffsetStored_reg_5_)) + (portref CLR (instanceref bSpOffsetStored_reg_6_)) + (portref CLR (instanceref bSpOffsetStored_reg_7_)) + (portref CLR (instanceref bSpOffsetStored_reg_8_)) + (portref CLR (instanceref bSpOffsetStored_reg_9_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_1_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_2_)) + (portref CLR (instanceref rPulserEnableDelayVal_reg_3_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_0_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_1_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_2_)) + (portref CLR (instanceref sPpsClkCrossDelayVal_reg_3_)) + (portref PRE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref PRE (instanceref bResetTdc_reg)) + (portref PRE (instanceref rPulserEnableDelayVal_reg_0_)) + (portref aBusReset) + ) + ) + (net aTdcReset (joined + (portref CLR (instanceref RptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref I3 (instanceref aTdcResetLcl_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I3 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref Q (instanceref aTdcResetLcl_reg)) + (portref aTdcReset) + ) + ) + (net aTdcResetLcl_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg)) + (portref O (instanceref aTdcResetLcl_i_1)) + ) + ) + (net aTdcResetLcl_i_2_n_0 (joined + (portref I1 (instanceref aTdcResetLcl_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I1 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref O (instanceref aTdcResetLcl_i_2)) + ) + ) + (net aTdcResetLcl_i_3_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_7)) + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref I2 (instanceref aTdcResetLcl_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__0)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__1)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__2)) + (portref I2 (instanceref aTdcResetLcl_rep_i_1__3)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I5 (instanceref bPushPpsDelayVal_i_1)) + (portref I5 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref aTdcResetLcl_i_3)) + ) + ) + (net aTdcResetLcl_i_4_n_0 (joined + (portref I1 (instanceref bRpOffsetStored_39__i_3)) + (portref I2 (instanceref aTdcResetLcl_i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref O (instanceref aTdcResetLcl_i_4)) + ) + ) + (net aTdcResetLcl_i_5_n_0 (joined + (portref I0 (instanceref bRpOffsetStored_39__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I3 (instanceref aTdcResetLcl_i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref O (instanceref aTdcResetLcl_i_5)) + ) + ) + (net aTdcResetLcl_reg_rep__0_n_0 (joined + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_32_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_33_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_34_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_35_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_36_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_37_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_38_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_39_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_31__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_32__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_33__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_72__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_73__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_74__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_75__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref IncomingOffsetHs_HBx_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__0)) + ) + ) + (net aTdcResetLcl_reg_rep__1_n_0 (joined + (portref CLR (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__1)) + ) + ) + (net aTdcResetLcl_reg_rep__2_n_0 (joined + (portref CLR (instanceref RePulse1CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse1CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse1CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref RePulse2CntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref RePulse2CntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__2)) + ) + ) + (net aTdcResetLcl_reg_rep__3_n_0 (joined + (portref CLR (instanceref SptCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SptCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SptCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep__3)) + ) + ) + (net aTdcResetLcl_reg_rep_n_0 (joined + (portref CLR (instanceref SpCntHs_BlkIn_iDlyPush_reg)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref CLR (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref CLR (instanceref SpCntHs_BlkIn_iPushTogglex_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oDataValid_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle1x_Gen0_FDCEx)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle2_reg)) + (portref CLR (instanceref SpCntHs_BlkOut_oPushToggle_msx_Gen0_FDCEx)) + (portref Q (instanceref aTdcResetLcl_reg_rep)) + ) + ) + (net aTdcResetLcl_rep_i_1__0_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__0)) + (portref O (instanceref aTdcResetLcl_rep_i_1__0)) + ) + ) + (net aTdcResetLcl_rep_i_1__1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__1)) + (portref O (instanceref aTdcResetLcl_rep_i_1__1)) + ) + ) + (net aTdcResetLcl_rep_i_1__2_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__2)) + (portref O (instanceref aTdcResetLcl_rep_i_1__2)) + ) + ) + (net aTdcResetLcl_rep_i_1__3_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep__3)) + (portref O (instanceref aTdcResetLcl_rep_i_1__3)) + ) + ) + (net aTdcResetLcl_rep_i_1_n_0 (joined + (portref D (instanceref aTdcResetLcl_reg_rep)) + (portref O (instanceref aTdcResetLcl_rep_i_1)) + ) + ) + (net bBusReset (joined + (portref I0 (instanceref bOffsetUpdated_i_1)) + (portref I0 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_6)) + (portref I1 (instanceref bEnableTdc_i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I1 (instanceref bPpsClkCrossEn_i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I1 (instanceref bReRunEnable_i_1)) + (portref I1 (instanceref bResetTdc_i_1)) + (portref I1 (instanceref bRpOffsetStored_0__i_1)) + (portref I1 (instanceref bRpOffsetStored_10__i_1)) + (portref I1 (instanceref bRpOffsetStored_11__i_1)) + (portref I1 (instanceref bRpOffsetStored_12__i_1)) + (portref I1 (instanceref bRpOffsetStored_13__i_1)) + (portref I1 (instanceref bRpOffsetStored_14__i_1)) + (portref I1 (instanceref bRpOffsetStored_15__i_1)) + (portref I1 (instanceref bRpOffsetStored_16__i_1)) + (portref I1 (instanceref bRpOffsetStored_17__i_1)) + (portref I1 (instanceref bRpOffsetStored_18__i_1)) + (portref I1 (instanceref bRpOffsetStored_19__i_1)) + (portref I1 (instanceref bRpOffsetStored_1__i_1)) + (portref I1 (instanceref bRpOffsetStored_20__i_1)) + (portref I1 (instanceref bRpOffsetStored_21__i_1)) + (portref I1 (instanceref bRpOffsetStored_22__i_1)) + (portref I1 (instanceref bRpOffsetStored_23__i_1)) + (portref I1 (instanceref bRpOffsetStored_24__i_1)) + (portref I1 (instanceref bRpOffsetStored_25__i_1)) + (portref I1 (instanceref bRpOffsetStored_26__i_1)) + (portref I1 (instanceref bRpOffsetStored_27__i_1)) + (portref I1 (instanceref bRpOffsetStored_28__i_1)) + (portref I1 (instanceref bRpOffsetStored_29__i_1)) + (portref I1 (instanceref bRpOffsetStored_2__i_1)) + (portref I1 (instanceref bRpOffsetStored_30__i_1)) + (portref I1 (instanceref bRpOffsetStored_31__i_1)) + (portref I1 (instanceref bRpOffsetStored_32__i_1)) + (portref I1 (instanceref bRpOffsetStored_33__i_1)) + (portref I1 (instanceref bRpOffsetStored_34__i_1)) + (portref I1 (instanceref bRpOffsetStored_35__i_1)) + (portref I1 (instanceref bRpOffsetStored_36__i_1)) + (portref I1 (instanceref bRpOffsetStored_37__i_1)) + (portref I1 (instanceref bRpOffsetStored_38__i_1)) + (portref I1 (instanceref bRpOffsetStored_39__i_2)) + (portref I1 (instanceref bRpOffsetStored_3__i_1)) + (portref I1 (instanceref bRpOffsetStored_4__i_1)) + (portref I1 (instanceref bRpOffsetStored_5__i_1)) + (portref I1 (instanceref bRpOffsetStored_6__i_1)) + (portref I1 (instanceref bRpOffsetStored_7__i_1)) + (portref I1 (instanceref bRpOffsetStored_8__i_1)) + (portref I1 (instanceref bRpOffsetStored_9__i_1)) + (portref I1 (instanceref bScratch_0__i_1)) + (portref I1 (instanceref bScratch_10__i_1)) + (portref I1 (instanceref bScratch_11__i_1)) + (portref I1 (instanceref bScratch_12__i_1)) + (portref I1 (instanceref bScratch_13__i_1)) + (portref I1 (instanceref bScratch_14__i_1)) + (portref I1 (instanceref bScratch_15__i_1)) + (portref I1 (instanceref bScratch_1__i_1)) + (portref I1 (instanceref bScratch_20__i_1)) + (portref I1 (instanceref bScratch_21__i_1)) + (portref I1 (instanceref bScratch_22__i_1)) + (portref I1 (instanceref bScratch_23__i_1)) + (portref I1 (instanceref bScratch_24__i_1)) + (portref I1 (instanceref bScratch_28__i_1)) + (portref I1 (instanceref bScratch_29__i_1)) + (portref I1 (instanceref bScratch_2__i_1)) + (portref I1 (instanceref bScratch_30__i_1)) + (portref I1 (instanceref bScratch_31__i_2)) + (portref I1 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bScratch_3__i_1)) + (portref I1 (instanceref bScratch_4__i_1)) + (portref I1 (instanceref bScratch_5__i_1)) + (portref I1 (instanceref bScratch_6__i_1)) + (portref I1 (instanceref bScratch_7__i_1)) + (portref I1 (instanceref bScratch_8__i_1)) + (portref I1 (instanceref bScratch_9__i_1)) + (portref I1 (instanceref bSpOffsetStored_0__i_1)) + (portref I1 (instanceref bSpOffsetStored_10__i_1)) + (portref I1 (instanceref bSpOffsetStored_11__i_1)) + (portref I1 (instanceref bSpOffsetStored_12__i_1)) + (portref I1 (instanceref bSpOffsetStored_13__i_1)) + (portref I1 (instanceref bSpOffsetStored_14__i_1)) + (portref I1 (instanceref bSpOffsetStored_15__i_1)) + (portref I1 (instanceref bSpOffsetStored_16__i_1)) + (portref I1 (instanceref bSpOffsetStored_17__i_1)) + (portref I1 (instanceref bSpOffsetStored_18__i_1)) + (portref I1 (instanceref bSpOffsetStored_19__i_1)) + (portref I1 (instanceref bSpOffsetStored_1__i_1)) + (portref I1 (instanceref bSpOffsetStored_20__i_1)) + (portref I1 (instanceref bSpOffsetStored_21__i_1)) + (portref I1 (instanceref bSpOffsetStored_22__i_1)) + (portref I1 (instanceref bSpOffsetStored_23__i_1)) + (portref I1 (instanceref bSpOffsetStored_24__i_1)) + (portref I1 (instanceref bSpOffsetStored_25__i_1)) + (portref I1 (instanceref bSpOffsetStored_26__i_1)) + (portref I1 (instanceref bSpOffsetStored_27__i_1)) + (portref I1 (instanceref bSpOffsetStored_28__i_1)) + (portref I1 (instanceref bSpOffsetStored_29__i_1)) + (portref I1 (instanceref bSpOffsetStored_2__i_1)) + (portref I1 (instanceref bSpOffsetStored_30__i_1)) + (portref I1 (instanceref bSpOffsetStored_31__i_1)) + (portref I1 (instanceref bSpOffsetStored_3__i_1)) + (portref I1 (instanceref bSpOffsetStored_4__i_1)) + (portref I1 (instanceref bSpOffsetStored_5__i_1)) + (portref I1 (instanceref bSpOffsetStored_6__i_1)) + (portref I1 (instanceref bSpOffsetStored_7__i_1)) + (portref I1 (instanceref bSpOffsetStored_8__i_1)) + (portref I1 (instanceref bSpOffsetStored_9__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bClearTdcRegs_i_1)) + (portref I4 (instanceref aTdcResetLcl_i_3)) + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_8)) + (portref I4 (instanceref bRpOffsetStored_39__i_1)) + (portref bBusReset) + ) + ) + (net bClearTdcRegs (joined + (portref D (instanceref bScratch_reg_0_)) + (portref O (instanceref bScratch_0__i_1)) + ) + ) + (net bClearTdcRegs_i_1_n_0 (joined + (portref D (instanceref bClearTdcRegs_reg)) + (portref O (instanceref bClearTdcRegs_i_1)) + ) + ) + (net bClearTdcRegs_i_2_n_0 (joined + (portref I2 (instanceref bClearTdcRegs_i_1)) + (portref O (instanceref bClearTdcRegs_i_2)) + ) + ) + (net bClearTdcRegs_i_3_n_0 (joined + (portref I0 (instanceref bClearTdcRegs_i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_7)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_9)) + (portref O (instanceref bClearTdcRegs_i_3)) + ) + ) + (net bClearTdcRegs_reg_n_0 (joined + (portref I0 (instanceref bEnableTdc_i_1)) + (portref I0 (instanceref bPpsClkCrossEn_i_1)) + (portref I0 (instanceref bReRunEnable_i_1)) + (portref I0 (instanceref bResetTdc_i_1)) + (portref I0 (instanceref bScratch_31__i_5)) + (portref I1 (instanceref bPulserEnableDelayVal_0__i_1)) + (portref I2 (instanceref aTdcResetLcl_i_2)) + (portref I2 (instanceref bPpsClkCrossDelayVal_0__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_1__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_2__i_1)) + (portref I2 (instanceref bPpsClkCrossDelayVal_3__i_2)) + (portref I2 (instanceref bPulserEnableDelayVal_1__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_2__i_1)) + (portref I2 (instanceref bPulserEnableDelayVal_3__i_2)) + (portref I2 (instanceref bScratch_0__i_1)) + (portref I2 (instanceref bScratch_10__i_1)) + (portref I2 (instanceref bScratch_11__i_1)) + (portref I2 (instanceref bScratch_12__i_1)) + (portref I2 (instanceref bScratch_13__i_1)) + (portref I2 (instanceref bScratch_14__i_1)) + (portref I2 (instanceref bScratch_15__i_1)) + (portref I2 (instanceref bScratch_1__i_1)) + (portref I2 (instanceref bScratch_20__i_1)) + (portref I2 (instanceref bScratch_21__i_1)) + (portref I2 (instanceref bScratch_22__i_1)) + (portref I2 (instanceref bScratch_23__i_1)) + (portref I2 (instanceref bScratch_24__i_1)) + (portref I2 (instanceref bScratch_28__i_1)) + (portref I2 (instanceref bScratch_29__i_1)) + (portref I2 (instanceref bScratch_2__i_1)) + (portref I2 (instanceref bScratch_30__i_1)) + (portref I2 (instanceref bScratch_31__i_2)) + (portref I2 (instanceref bScratch_3__i_1)) + (portref I2 (instanceref bScratch_4__i_1)) + (portref I2 (instanceref bScratch_5__i_1)) + (portref I2 (instanceref bScratch_6__i_1)) + (portref I2 (instanceref bScratch_7__i_1)) + (portref I2 (instanceref bScratch_8__i_1)) + (portref I2 (instanceref bScratch_9__i_1)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I3 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I3 (instanceref bPushPpsDelayVal_i_1)) + (portref I3 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I4 (instanceref bClearTdcRegs_i_1)) + (portref Q (instanceref bClearTdcRegs_reg)) + ) + ) + (net bEnableTdc (joined + (portref D (instanceref bScratch_reg_4_)) + (portref O (instanceref bScratch_4__i_1)) + ) + ) + (net bEnableTdc_i_1_n_0 (joined + (portref D (instanceref bEnableTdc_reg)) + (portref O (instanceref bEnableTdc_i_1)) + ) + ) + (net bEnableTdc_reg_n_0 (joined + (portref D (instanceref EnableTdcDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref I5 (instanceref bEnableTdc_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_5)) + (portref Q (instanceref bEnableTdc_reg)) + ) + ) + (net bOffsetUpdated_i_1_n_0 (joined + (portref D (instanceref bOffsetUpdated_reg)) + (portref O (instanceref bOffsetUpdated_i_1)) + ) + ) + (net bOffsetUpdated_reg_n_0 (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I4 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref bOffsetUpdated_reg)) + ) + ) + (net bOffsetsValid (joined + (portref D (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_oDataValid_reg)) + ) + ) + (net bOffsetsValidSyncReset (joined + (portref I3 (instanceref bOffsetUpdated_i_1)) + (portref Q (instanceref OffsetsValidDs_DoubleSyncSlAsyncInx_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_0_ "bOffsets[0]") (joined + (portref D (instanceref OffsetsDsGen_0__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_10_ "bOffsets[10]") (joined + (portref D (instanceref OffsetsDsGen_10__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_11_ "bOffsets[11]") (joined + (portref D (instanceref OffsetsDsGen_11__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_12_ "bOffsets[12]") (joined + (portref D (instanceref OffsetsDsGen_12__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_13_ "bOffsets[13]") (joined + (portref D (instanceref OffsetsDsGen_13__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_14_ "bOffsets[14]") (joined + (portref D (instanceref OffsetsDsGen_14__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_15_ "bOffsets[15]") (joined + (portref D (instanceref OffsetsDsGen_15__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_16_ "bOffsets[16]") (joined + (portref D (instanceref OffsetsDsGen_16__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_17_ "bOffsets[17]") (joined + (portref D (instanceref OffsetsDsGen_17__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_18_ "bOffsets[18]") (joined + (portref D (instanceref OffsetsDsGen_18__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_19_ "bOffsets[19]") (joined + (portref D (instanceref OffsetsDsGen_19__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_1_ "bOffsets[1]") (joined + (portref D (instanceref OffsetsDsGen_1__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_20_ "bOffsets[20]") (joined + (portref D (instanceref OffsetsDsGen_20__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_21_ "bOffsets[21]") (joined + (portref D (instanceref OffsetsDsGen_21__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_22_ "bOffsets[22]") (joined + (portref D (instanceref OffsetsDsGen_22__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_23_ "bOffsets[23]") (joined + (portref D (instanceref OffsetsDsGen_23__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_24_ "bOffsets[24]") (joined + (portref D (instanceref OffsetsDsGen_24__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_25_ "bOffsets[25]") (joined + (portref D (instanceref OffsetsDsGen_25__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_26_ "bOffsets[26]") (joined + (portref D (instanceref OffsetsDsGen_26__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_27_ "bOffsets[27]") (joined + (portref D (instanceref OffsetsDsGen_27__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_28_ "bOffsets[28]") (joined + (portref D (instanceref OffsetsDsGen_28__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_29_ "bOffsets[29]") (joined + (portref D (instanceref OffsetsDsGen_29__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_2_ "bOffsets[2]") (joined + (portref D (instanceref OffsetsDsGen_2__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_30_ "bOffsets[30]") (joined + (portref D (instanceref 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(portref D (instanceref OffsetsDsGen_34__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_34__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_35_ "bOffsets[35]") (joined + (portref D (instanceref OffsetsDsGen_35__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_35__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_36_ "bOffsets[36]") (joined + (portref D (instanceref OffsetsDsGen_36__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_36__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_37_ "bOffsets[37]") (joined + (portref D (instanceref OffsetsDsGen_37__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_37__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_38_ "bOffsets[38]") (joined + (portref D (instanceref OffsetsDsGen_38__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_38__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_39_ "bOffsets[39]") (joined + (portref D (instanceref OffsetsDsGen_39__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_39__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_3_ "bOffsets[3]") (joined + (portref D (instanceref OffsetsDsGen_3__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_40_ "bOffsets[40]") (joined + (portref D (instanceref OffsetsDsGen_40__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_40__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_41_ "bOffsets[41]") (joined + (portref D (instanceref OffsetsDsGen_41__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_41__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_42_ "bOffsets[42]") (joined + (portref D (instanceref OffsetsDsGen_42__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_42__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_43_ "bOffsets[43]") (joined + (portref D (instanceref OffsetsDsGen_43__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_43__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_44_ "bOffsets[44]") (joined + (portref D (instanceref OffsetsDsGen_44__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_44__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_45_ "bOffsets[45]") (joined + (portref D (instanceref OffsetsDsGen_45__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_45__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_46_ "bOffsets[46]") (joined + (portref D (instanceref OffsetsDsGen_46__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_46__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_47_ "bOffsets[47]") (joined + (portref D (instanceref OffsetsDsGen_47__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_47__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_48_ "bOffsets[48]") (joined + (portref D (instanceref OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_48__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_49_ "bOffsets[49]") (joined + (portref D (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_49__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_4_ "bOffsets[4]") (joined + (portref D (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_50_ "bOffsets[50]") (joined + (portref D (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_50__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_51_ "bOffsets[51]") (joined + (portref D (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_51__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_52_ "bOffsets[52]") (joined + (portref D (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_52__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_53_ "bOffsets[53]") (joined + (portref D (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_53__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_54_ "bOffsets[54]") (joined + (portref D (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_54__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_55_ "bOffsets[55]") (joined + (portref D (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_55__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_56_ "bOffsets[56]") (joined + (portref D (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_56__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_57_ "bOffsets[57]") (joined + (portref D (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_57__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_58_ "bOffsets[58]") (joined + (portref D (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_58__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_59_ "bOffsets[59]") (joined + (portref D (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_59__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_5_ "bOffsets[5]") (joined + (portref D (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_60_ "bOffsets[60]") (joined + (portref D (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_60__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_61_ "bOffsets[61]") (joined + (portref D (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_61__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_62_ "bOffsets[62]") (joined + (portref D (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_62__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_63_ "bOffsets[63]") (joined + (portref D (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_63__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_64_ "bOffsets[64]") (joined + (portref D (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_64__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_65_ "bOffsets[65]") (joined + (portref D (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_65__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_66_ "bOffsets[66]") (joined + (portref D (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_66__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_67_ "bOffsets[67]") (joined + (portref D (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_67__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_68_ "bOffsets[68]") (joined + (portref D (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_68__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_69_ "bOffsets[69]") (joined + (portref D (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_69__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_6_ "bOffsets[6]") (joined + (portref D (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_70_ "bOffsets[70]") (joined + (portref D (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_70__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_71_ "bOffsets[71]") (joined + (portref D (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_71__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_72_ "bOffsets[72]") (joined + (portref D (instanceref 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(portref D (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_76__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_77_ "bOffsets[77]") (joined + (portref D (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_77__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_78_ "bOffsets[78]") (joined + (portref D (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_78__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_79_ "bOffsets[79]") (joined + (portref D (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_79__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_7_ "bOffsets[7]") (joined + (portref D (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_8_ "bOffsets[8]") (joined + (portref D (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bOffsets_9_ "bOffsets[9]") (joined + (portref D (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref IncomingOffsetHs_HBx_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename bPpsClkCrossDelayVal_1__i_1_n_0 "bPpsClkCrossDelayVal[1]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref D (instanceref bScratch_reg_17_)) + (portref O (instanceref bPpsClkCrossDelayVal_1__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_2__i_1_n_0 "bPpsClkCrossDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_18_)) + (portref O (instanceref bPpsClkCrossDelayVal_2__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_1_n_0 "bPpsClkCrossDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPpsClkCrossDelayVal_reg_0_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_1_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_2_)) + (portref CE (instanceref bPpsClkCrossDelayVal_reg_3_)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_1)) + ) + ) + (net (rename bPpsClkCrossDelayVal_3__i_3_n_0 "bPpsClkCrossDelayVal[3]_i_3_n_0") (joined + (portref I1 (instanceref bPpsClkCrossDelayVal_3__i_1)) + (portref I1 (instanceref bPulserEnableDelayVal_3__i_1)) + (portref I4 (instanceref bEnableTdc_i_1)) + (portref I4 (instanceref bPpsClkCrossEn_i_1)) + (portref I4 (instanceref bReRunEnable_i_1)) + (portref I4 (instanceref bResetTdc_i_1)) + (portref O (instanceref bPpsClkCrossDelayVal_3__i_3)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__0_ "bPpsClkCrossDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_0_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__1_ "bPpsClkCrossDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_1_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__2_ "bPpsClkCrossDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_2_)) + ) + ) + (net (rename bPpsClkCrossDelayVal_reg_n_0__3_ "bPpsClkCrossDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_1)) + (portref Q (instanceref bPpsClkCrossDelayVal_reg_3_)) + ) + ) + (net bPpsClkCrossEn (joined + (portref D (instanceref bScratch_reg_12_)) + (portref O (instanceref bScratch_12__i_1)) + ) + ) + (net bPpsClkCrossEn_i_1_n_0 (joined + (portref D (instanceref bPpsClkCrossEn_reg)) + (portref O (instanceref bPpsClkCrossEn_i_1)) + ) + ) + (net bPpsClkCrossEn_reg_n_0 (joined + (portref D (instanceref PpsCrossEnDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_1)) + (portref I5 (instanceref bPpsClkCrossEn_i_1)) + (portref Q (instanceref bPpsClkCrossEn_reg)) + ) + ) + (net bPpsPulseCaptured (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_6)) + (portref Q (instanceref PpsCapturedDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bPulserEnableDelayVal_0__i_1_n_0 "bPulserEnableDelayVal[0]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_0_)) + (portref O (instanceref bPulserEnableDelayVal_0__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_2__i_1_n_0 "bPulserEnableDelayVal[2]_i_1_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_2_)) + (portref D (instanceref bScratch_reg_26_)) + (portref O (instanceref bPulserEnableDelayVal_2__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_1_n_0 "bPulserEnableDelayVal[3]_i_1_n_0") (joined + (portref CE (instanceref bPulserEnableDelayVal_reg_0_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_1_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_2_)) + (portref CE (instanceref bPulserEnableDelayVal_reg_3_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_1)) + ) + ) + (net (rename bPulserEnableDelayVal_3__i_2_n_0 "bPulserEnableDelayVal[3]_i_2_n_0") (joined + (portref D (instanceref bPulserEnableDelayVal_reg_3_)) + (portref D (instanceref bScratch_reg_27_)) + (portref O (instanceref bPulserEnableDelayVal_3__i_2)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__0_ "bPulserEnableDelayVal_reg_n_0_[0]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_0_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__1_ "bPulserEnableDelayVal_reg_n_0_[1]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_1_)) + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_1)) + (portref Q (instanceref bPulserEnableDelayVal_reg_1_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__2_ "bPulserEnableDelayVal_reg_n_0_[2]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_2_)) + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bPulserEnableDelayVal_reg_2_)) + ) + ) + (net (rename bPulserEnableDelayVal_reg_n_0__3_ "bPulserEnableDelayVal_reg_n_0_[3]") (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iLclStoredData_reg_3_)) + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bPulserEnableDelayVal_reg_3_)) + ) + ) + (net bPushPpsDelayVal (joined + (portref D (instanceref bPushPpsDelayVal_reg)) + (portref O (instanceref bPushPpsDelayVal_i_1)) + ) + ) + (net bPushPpsDelayVal_i_2_n_0 (joined + (portref I0 (instanceref bPushPpsDelayVal_i_1)) + (portref I0 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_6)) + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_6)) + (portref I5 (instanceref aTdcResetLcl_i_2)) + (portref O (instanceref bPushPpsDelayVal_i_2)) + ) + ) + (net bPushPpsDelayVal_i_3_n_0 (joined + (portref I1 (instanceref bPushPpsDelayVal_i_1)) + (portref I1 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref O (instanceref bPushPpsDelayVal_i_3)) + ) + ) + (net bPushPpsDelayVal_i_4_n_0 (joined + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_4)) + (portref I4 (instanceref bPushPpsDelayVal_i_1)) + (portref I4 (instanceref bPushPulserEnableDelayVal_i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__25__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_7)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_11)) + (portref O (instanceref bPushPpsDelayVal_i_4)) + ) + ) + (net bPushPpsDelayVal_reg_n_0 (joined + (portref D (instanceref PpsDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__9)) + (portref Q (instanceref bPushPpsDelayVal_reg)) + ) + ) + (net bPushPulserEnableDelayVal (joined + (portref D (instanceref bPushPulserEnableDelayVal_reg)) + (portref O (instanceref bPushPulserEnableDelayVal_i_1)) + ) + ) + (net bPushPulserEnableDelayVal_reg_n_0 (joined + (portref D (instanceref PulserEnableDelayValCrossingHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__10)) + (portref Q (instanceref bPushPulserEnableDelayVal_reg)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_0_ "bRePulsePeriod1CtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_10_ "bRePulsePeriod1CtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_11_ "bRePulsePeriod1CtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_12_ "bRePulsePeriod1CtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_13_ "bRePulsePeriod1CtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_14_ "bRePulsePeriod1CtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_15_ "bRePulsePeriod1CtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_16_ "bRePulsePeriod1CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_17_ "bRePulsePeriod1CtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_18_ "bRePulsePeriod1CtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_19_ "bRePulsePeriod1CtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_1_ "bRePulsePeriod1CtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_20_ "bRePulsePeriod1CtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_21_ "bRePulsePeriod1CtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_22_ "bRePulsePeriod1CtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_23_ "bRePulsePeriod1CtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_24_ "bRePulsePeriod1CtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_25_ "bRePulsePeriod1CtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_26_ "bRePulsePeriod1CtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_27_ "bRePulsePeriod1CtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_28_ "bRePulsePeriod1CtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_29_ "bRePulsePeriod1CtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_2_ "bRePulsePeriod1CtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_30_ "bRePulsePeriod1CtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_31_ "bRePulsePeriod1CtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_3_ "bRePulsePeriod1CtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_4_ "bRePulsePeriod1CtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_5_ "bRePulsePeriod1CtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_6_ "bRePulsePeriod1CtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_7_ "bRePulsePeriod1CtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_8_ "bRePulsePeriod1CtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadbackSyncReset_9_ "bRePulsePeriod1CtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_0_ "bRePulsePeriod1CtrlReadback[0]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_0__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_10_ "bRePulsePeriod1CtrlReadback[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_10__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_11_ "bRePulsePeriod1CtrlReadback[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_11__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_12_ "bRePulsePeriod1CtrlReadback[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_12__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_13_ "bRePulsePeriod1CtrlReadback[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_13__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_14_ "bRePulsePeriod1CtrlReadback[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_14__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_15_ "bRePulsePeriod1CtrlReadback[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_15__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_16_ "bRePulsePeriod1CtrlReadback[16]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_16__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_17_ "bRePulsePeriod1CtrlReadback[17]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_17__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_18_ "bRePulsePeriod1CtrlReadback[18]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_18__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_19_ "bRePulsePeriod1CtrlReadback[19]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_19__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_1_ "bRePulsePeriod1CtrlReadback[1]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_1__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_20_ "bRePulsePeriod1CtrlReadback[20]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_20__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_21_ "bRePulsePeriod1CtrlReadback[21]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_21__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_22_ "bRePulsePeriod1CtrlReadback[22]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_22__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_23_ "bRePulsePeriod1CtrlReadback[23]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_23__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_24_ "bRePulsePeriod1CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_24__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_25_ "bRePulsePeriod1CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_25__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_26_ "bRePulsePeriod1CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_26__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_27_ "bRePulsePeriod1CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_27__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_28_ "bRePulsePeriod1CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_28__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_29_ "bRePulsePeriod1CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_29__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_2_ "bRePulsePeriod1CtrlReadback[2]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_2__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_30_ "bRePulsePeriod1CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_30__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_31_ "bRePulsePeriod1CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt1ReadbackDsGen_31__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_3_ "bRePulsePeriod1CtrlReadback[3]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_3__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_4_ "bRePulsePeriod1CtrlReadback[4]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_4__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_5_ "bRePulsePeriod1CtrlReadback[5]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_5__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_6_ "bRePulsePeriod1CtrlReadback[6]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_6__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_7_ "bRePulsePeriod1CtrlReadback[7]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_7__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_8_ "bRePulsePeriod1CtrlReadback[8]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_8__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod1CtrlReadback_9_ "bRePulsePeriod1CtrlReadback[9]") (joined + (portref D (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt1ReadbackDsGen_9__RePulse1ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_0_ "bRePulsePeriod2CtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_10_ "bRePulsePeriod2CtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_11_ "bRePulsePeriod2CtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_12_ "bRePulsePeriod2CtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_13_ "bRePulsePeriod2CtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_14_ "bRePulsePeriod2CtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_15_ "bRePulsePeriod2CtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_16_ "bRePulsePeriod2CtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_17_ "bRePulsePeriod2CtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_18_ "bRePulsePeriod2CtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_19_ "bRePulsePeriod2CtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_1_ "bRePulsePeriod2CtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_20_ "bRePulsePeriod2CtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_21_ "bRePulsePeriod2CtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_22_ "bRePulsePeriod2CtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_23_ "bRePulsePeriod2CtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_24_ "bRePulsePeriod2CtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_25_ "bRePulsePeriod2CtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_26_ "bRePulsePeriod2CtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_27_ "bRePulsePeriod2CtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_28_ "bRePulsePeriod2CtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_1)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_29_ "bRePulsePeriod2CtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_2_ "bRePulsePeriod2CtrlReadbackSyncReset[2]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_30_ "bRePulsePeriod2CtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_31_ "bRePulsePeriod2CtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_3_ "bRePulsePeriod2CtrlReadbackSyncReset[3]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_4_ "bRePulsePeriod2CtrlReadbackSyncReset[4]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_5_ "bRePulsePeriod2CtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_6_ "bRePulsePeriod2CtrlReadbackSyncReset[6]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__6__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_7_ "bRePulsePeriod2CtrlReadbackSyncReset[7]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_8_ "bRePulsePeriod2CtrlReadbackSyncReset[8]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadbackSyncReset_9_ "bRePulsePeriod2CtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref Q (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_0_ "bRePulsePeriod2CtrlReadback[0]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_0__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_10_ "bRePulsePeriod2CtrlReadback[10]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_10__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_11_ "bRePulsePeriod2CtrlReadback[11]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_11__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_12_ "bRePulsePeriod2CtrlReadback[12]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_12__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_13_ "bRePulsePeriod2CtrlReadback[13]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_13__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_14_ "bRePulsePeriod2CtrlReadback[14]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_14__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_15_ "bRePulsePeriod2CtrlReadback[15]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_15__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_16_ "bRePulsePeriod2CtrlReadback[16]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_16__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_17_ "bRePulsePeriod2CtrlReadback[17]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_17__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_18_ "bRePulsePeriod2CtrlReadback[18]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_18__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_19_ "bRePulsePeriod2CtrlReadback[19]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_19__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_1_ "bRePulsePeriod2CtrlReadback[1]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_1__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_20_ "bRePulsePeriod2CtrlReadback[20]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_20__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_21_ "bRePulsePeriod2CtrlReadback[21]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_21__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_22_ "bRePulsePeriod2CtrlReadback[22]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_22__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_23_ "bRePulsePeriod2CtrlReadback[23]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_23__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_24_ "bRePulsePeriod2CtrlReadback[24]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_24__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_25_ "bRePulsePeriod2CtrlReadback[25]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_25__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_26_ "bRePulsePeriod2CtrlReadback[26]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_26__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_27_ "bRePulsePeriod2CtrlReadback[27]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_27__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_28_ "bRePulsePeriod2CtrlReadback[28]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_28__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_29_ "bRePulsePeriod2CtrlReadback[29]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_29__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_2_ "bRePulsePeriod2CtrlReadback[2]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_2__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_30_ "bRePulsePeriod2CtrlReadback[30]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_30__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_31_ "bRePulsePeriod2CtrlReadback[31]") (joined + (portref D (instanceref RePulseCnt2ReadbackDsGen_31__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_3_ "bRePulsePeriod2CtrlReadback[3]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_3__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_4_ "bRePulsePeriod2CtrlReadback[4]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_4__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_5_ "bRePulsePeriod2CtrlReadback[5]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_5__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_6_ "bRePulsePeriod2CtrlReadback[6]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_6__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_7_ "bRePulsePeriod2CtrlReadback[7]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_7__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_8_ "bRePulsePeriod2CtrlReadback[8]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_8__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRePulsePeriod2CtrlReadback_9_ "bRePulsePeriod2CtrlReadback[9]") (joined + (portref D (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RePulseCnt2ReadbackDsGen_9__RePulse2ReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net bReRunEnable (joined + (portref D (instanceref bScratch_reg_8_)) + (portref O (instanceref bScratch_8__i_1)) + ) + ) + (net bReRunEnable_i_1_n_0 (joined + (portref D (instanceref bReRunEnable_reg)) + (portref O (instanceref bReRunEnable_i_1)) + ) + ) + (net bReRunEnable_reg_n_0 (joined + (portref D (instanceref ReRunEnableDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref I5 (instanceref bReRunEnable_i_1)) + (portref Q (instanceref bReRunEnable_reg)) + ) + ) + (net (rename bRegPortInFlat_0_ "bRegPortInFlat[0]") (joined + (portref I0 (instanceref bPushPpsDelayVal_i_3)) + (portref I1 (instanceref bClearTdcRegs_i_2)) + (portref I1 (instanceref bScratch_31__i_3)) + (portref I4 (instanceref aTdcResetLcl_i_2)) + (portref (member bRegPortInFlat 49)) + ) + ) + (net (rename bRegPortInFlat_10_ "bRegPortInFlat[10]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + (portref I0 (instanceref bScratch_8__i_1)) + (portref I3 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 39)) + ) + ) + (net (rename bRegPortInFlat_11_ "bRegPortInFlat[11]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + (portref I0 (instanceref bScratch_9__i_1)) + (portref I2 (instanceref bReRunEnable_i_1)) + (portref (member bRegPortInFlat 38)) + ) + ) + (net (rename bRegPortInFlat_12_ "bRegPortInFlat[12]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + (portref I0 (instanceref bScratch_10__i_1)) + (portref (member bRegPortInFlat 37)) + ) + ) + (net (rename bRegPortInFlat_13_ "bRegPortInFlat[13]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + (portref I0 (instanceref bScratch_11__i_1)) + (portref (member bRegPortInFlat 36)) + ) + ) + (net (rename bRegPortInFlat_14_ "bRegPortInFlat[14]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + (portref I0 (instanceref bScratch_12__i_1)) + (portref I3 (instanceref bPpsClkCrossEn_i_1)) + (portref (member bRegPortInFlat 35)) + ) + ) + (net (rename bRegPortInFlat_15_ "bRegPortInFlat[15]") (joined + (portref D (instanceref RePulse1CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RePulse2CntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref D (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + (portref I0 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bRegPortOutLcl_Data__28__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__28__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__28__i_4_n_0 "bRegPortOutLcl[Data][28]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_1)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_1)) + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__28__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__28__i_5_n_0 "bRegPortOutLcl[Data][28]_i_5_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_3)) + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_4)) + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref I2 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"bRegPortOutLcl[Data][29]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__29_)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_2_n_0 "bRegPortOutLcl[Data][29]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_3_n_0 "bRegPortOutLcl[Data][29]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__29__i_4_n_0 "bRegPortOutLcl[Data][29]_i_4_n_0") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__29__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_1_n_0 "bRegPortOutLcl[Data][2]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__2_)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_2_n_0 "bRegPortOutLcl[Data][2]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_3_n_0 "bRegPortOutLcl[Data][2]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_4_n_0 "bRegPortOutLcl[Data][2]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__2__i_5_n_0 "bRegPortOutLcl[Data][2]_i_5_n_0") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__2__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__30__i_1_n_0 "bRegPortOutLcl[Data][30]_i_1_n_0") (joined + (portref D (instanceref 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(instanceref bRegPortOutLcl_Data__30__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_10_n_0 "bRegPortOutLcl[Data][31]_i_10_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref I2 (instanceref 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bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_4_n_0 "bRegPortOutLcl[Data][31]_i_4_n_0") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_4)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_5_n_0 "bRegPortOutLcl[Data][31]_i_5_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I0 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bRegPortOutLcl_Data__26__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_5)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_6_n_0 "bRegPortOutLcl[Data][31]_i_6_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_6)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_7_n_0 "bRegPortOutLcl[Data][31]_i_7_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref I2 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_7)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_8_n_0 "bRegPortOutLcl[Data][31]_i_8_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref I5 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_8)) + ) + ) + (net (rename bRegPortOutLcl_Data__31__i_9_n_0 "bRegPortOutLcl[Data][31]_i_9_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref I0 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref I0 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref I0 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref I2 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref I2 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref I2 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref I2 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref I5 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref O (instanceref bRegPortOutLcl_Data__31__i_9)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_1_n_0 "bRegPortOutLcl[Data][3]_i_1_n_0") (joined + (portref D (instanceref bRegPortOutLcl_reg_Data__3_)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_1)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_2_n_0 "bRegPortOutLcl[Data][3]_i_2_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_2)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_3_n_0 "bRegPortOutLcl[Data][3]_i_3_n_0") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_1)) + (portref O (instanceref bRegPortOutLcl_Data__3__i_3)) + ) + ) + (net (rename bRegPortOutLcl_Data__3__i_4_n_0 "bRegPortOutLcl[Data][3]_i_4_n_0") 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(instanceref bRpOffsetStored_28__i_1)) + ) + ) + (net (rename bRpOffsetStored_29_ "bRpOffsetStored[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_29_)) + ) + ) + (net (rename bRpOffsetStored_29__i_1_n_0 "bRpOffsetStored[29]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_29_)) + (portref O (instanceref bRpOffsetStored_29__i_1)) + ) + ) + (net (rename bRpOffsetStored_2_ "bRpOffsetStored[2]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_2_)) + ) + ) + (net (rename bRpOffsetStored_2__i_1_n_0 "bRpOffsetStored[2]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_2_)) + (portref O (instanceref bRpOffsetStored_2__i_1)) + ) + ) + (net (rename bRpOffsetStored_30_ "bRpOffsetStored[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_30_)) + ) + ) + (net (rename bRpOffsetStored_30__i_1_n_0 "bRpOffsetStored[30]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_30_)) + (portref O (instanceref bRpOffsetStored_30__i_1)) + ) + ) + (net (rename bRpOffsetStored_31_ "bRpOffsetStored[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref bRpOffsetStored_reg_31_)) + ) + ) + (net (rename bRpOffsetStored_31__i_1_n_0 "bRpOffsetStored[31]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_31_)) + (portref O (instanceref bRpOffsetStored_31__i_1)) + ) + ) + (net (rename bRpOffsetStored_32_ "bRpOffsetStored[32]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_32_)) + ) + ) + (net (rename bRpOffsetStored_32__i_1_n_0 "bRpOffsetStored[32]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_32_)) + (portref O (instanceref bRpOffsetStored_32__i_1)) + ) + ) + (net (rename bRpOffsetStored_33_ "bRpOffsetStored[33]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_33_)) + ) + ) + (net (rename bRpOffsetStored_33__i_1_n_0 "bRpOffsetStored[33]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_33_)) + (portref O (instanceref bRpOffsetStored_33__i_1)) + ) + ) + (net (rename bRpOffsetStored_34_ "bRpOffsetStored[34]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_34_)) + ) + ) + (net (rename bRpOffsetStored_34__i_1_n_0 "bRpOffsetStored[34]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_34_)) + (portref O (instanceref bRpOffsetStored_34__i_1)) + ) + ) + (net (rename bRpOffsetStored_35_ "bRpOffsetStored[35]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_35_)) + ) + ) + (net (rename bRpOffsetStored_35__i_1_n_0 "bRpOffsetStored[35]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_35_)) + (portref O (instanceref bRpOffsetStored_35__i_1)) + ) + ) + (net (rename bRpOffsetStored_36_ "bRpOffsetStored[36]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_36_)) + ) + ) + (net (rename bRpOffsetStored_36__i_1_n_0 "bRpOffsetStored[36]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_36_)) + (portref O (instanceref bRpOffsetStored_36__i_1)) + ) + ) + (net (rename bRpOffsetStored_37_ "bRpOffsetStored[37]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_37_)) + ) + ) + (net (rename bRpOffsetStored_37__i_1_n_0 "bRpOffsetStored[37]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_37_)) + (portref O (instanceref bRpOffsetStored_37__i_1)) + ) + ) + (net (rename bRpOffsetStored_38_ "bRpOffsetStored[38]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_38_)) + ) + ) + (net (rename bRpOffsetStored_38__i_1_n_0 "bRpOffsetStored[38]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_38_)) + (portref O (instanceref bRpOffsetStored_38__i_1)) + ) + ) + (net (rename bRpOffsetStored_39_ "bRpOffsetStored[39]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_39_)) + ) + ) + (net (rename bRpOffsetStored_39__i_2_n_0 "bRpOffsetStored[39]_i_2_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_39_)) + (portref O (instanceref bRpOffsetStored_39__i_2)) + ) + ) + (net (rename bRpOffsetStored_39__i_3_n_0 "bRpOffsetStored[39]_i_3_n_0") (joined + (portref I0 (instanceref bRpOffsetStored_39__i_1)) + (portref I1 (instanceref bClearTdcRegs_i_1)) + (portref I2 (instanceref bScratch_31__i_3)) + (portref O (instanceref bRpOffsetStored_39__i_3)) + ) + ) + (net (rename bRpOffsetStored_39__i_4_n_0 "bRpOffsetStored[39]_i_4_n_0") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_6)) + (portref I3 (instanceref bRpOffsetStored_39__i_1)) + (portref O (instanceref bRpOffsetStored_39__i_4)) + ) + ) + (net (rename bRpOffsetStored_3_ "bRpOffsetStored[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_3_)) + ) + ) + (net (rename bRpOffsetStored_3__i_1_n_0 "bRpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_3_)) + (portref O (instanceref bRpOffsetStored_3__i_1)) + ) + ) + (net (rename bRpOffsetStored_4_ "bRpOffsetStored[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_4_)) + ) + ) + (net (rename bRpOffsetStored_4__i_1_n_0 "bRpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_4_)) + (portref O (instanceref bRpOffsetStored_4__i_1)) + ) + ) + (net (rename bRpOffsetStored_5_ "bRpOffsetStored[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_5_)) + ) + ) + (net (rename bRpOffsetStored_5__i_1_n_0 "bRpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_5_)) + (portref O (instanceref bRpOffsetStored_5__i_1)) + ) + ) + (net (rename bRpOffsetStored_6_ "bRpOffsetStored[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bRpOffsetStored_reg_6_)) + ) + ) + (net (rename bRpOffsetStored_6__i_1_n_0 "bRpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_6_)) + (portref O (instanceref bRpOffsetStored_6__i_1)) + ) + ) + (net (rename bRpOffsetStored_7_ "bRpOffsetStored[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_7_)) + ) + ) + (net (rename bRpOffsetStored_7__i_1_n_0 "bRpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_7_)) + (portref O (instanceref bRpOffsetStored_7__i_1)) + ) + ) + (net (rename bRpOffsetStored_8_ "bRpOffsetStored[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bRpOffsetStored_reg_8_)) + ) + ) + (net (rename bRpOffsetStored_8__i_1_n_0 "bRpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_8_)) + (portref O (instanceref bRpOffsetStored_8__i_1)) + ) + ) + (net (rename bRpOffsetStored_9_ "bRpOffsetStored[9]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bRpOffsetStored_reg_9_)) + ) + ) + (net (rename bRpOffsetStored_9__i_1_n_0 "bRpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bRpOffsetStored_reg_9_)) + (portref O (instanceref bRpOffsetStored_9__i_1)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_0_ "bRpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_10_ "bRpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_11_ "bRpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_12_ "bRpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_13_ "bRpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_14_ "bRpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_15_ "bRpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_16_ "bRpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_17_ "bRpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_18_ "bRpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_19_ "bRpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_1_ "bRpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_20_ "bRpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_21_ "bRpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_22_ "bRpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_23_ "bRpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_24_ "bRpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_25_ "bRpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_26_ "bRpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_27_ "bRpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_28_ "bRpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_29_ "bRpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_2_ "bRpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_30_ "bRpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_31_ "bRpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_3_ "bRpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_4_ "bRpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_5_ "bRpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_6_ "bRpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_7_ "bRpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_8_ "bRpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadbackSyncReset_9_ "bRpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRpPeriodCtrlReadback_0_ "bRpPeriodCtrlReadback[0]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_0__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_10_ "bRpPeriodCtrlReadback[10]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_10__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_11_ "bRpPeriodCtrlReadback[11]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_11__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_12_ "bRpPeriodCtrlReadback[12]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_12__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_13_ "bRpPeriodCtrlReadback[13]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_13__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_14_ "bRpPeriodCtrlReadback[14]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_14__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_15_ "bRpPeriodCtrlReadback[15]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_15__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_16_ "bRpPeriodCtrlReadback[16]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_16__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_17_ "bRpPeriodCtrlReadback[17]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_17__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_18_ "bRpPeriodCtrlReadback[18]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_18__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_19_ "bRpPeriodCtrlReadback[19]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_19__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_1_ "bRpPeriodCtrlReadback[1]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_1__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_20_ "bRpPeriodCtrlReadback[20]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_20__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_21_ "bRpPeriodCtrlReadback[21]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_21__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_22_ "bRpPeriodCtrlReadback[22]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_22__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_23_ "bRpPeriodCtrlReadback[23]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_23__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_24_ "bRpPeriodCtrlReadback[24]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_24__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_25_ "bRpPeriodCtrlReadback[25]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_25__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_26_ "bRpPeriodCtrlReadback[26]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_26__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_27_ "bRpPeriodCtrlReadback[27]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_27__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_28_ "bRpPeriodCtrlReadback[28]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_28__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_29_ "bRpPeriodCtrlReadback[29]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_29__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_2_ "bRpPeriodCtrlReadback[2]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_2__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_30_ "bRpPeriodCtrlReadback[30]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_30__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_31_ "bRpPeriodCtrlReadback[31]") (joined + (portref D (instanceref RpCntReadbackDsGen_31__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_3_ "bRpPeriodCtrlReadback[3]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_3__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_4_ "bRpPeriodCtrlReadback[4]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_4__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_5_ "bRpPeriodCtrlReadback[5]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_5__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_6_ "bRpPeriodCtrlReadback[6]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_6__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_7_ "bRpPeriodCtrlReadback[7]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_7__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_8_ "bRpPeriodCtrlReadback[8]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_8__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRpPeriodCtrlReadback_9_ "bRpPeriodCtrlReadback[9]") (joined + (portref D (instanceref RpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RpCntReadbackDsGen_9__RpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_0_ "bRptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_10_ "bRptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_11_ "bRptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_12_ "bRptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_13_ "bRptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_14_ "bRptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_15_ "bRptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_16_ "bRptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_17_ "bRptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_18_ "bRptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_19_ "bRptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_1_ "bRptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_20_ "bRptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_21_ "bRptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_22_ "bRptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_23_ "bRptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_24_ "bRptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_25_ "bRptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_26_ "bRptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_27_ "bRptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_28_ "bRptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_29_ "bRptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_2_ "bRptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_30_ "bRptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_31_ "bRptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_3_ "bRptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_4_ "bRptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_5_ "bRptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_6_ "bRptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_7_ "bRptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_8_ "bRptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadbackSyncReset_9_ "bRptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bRptPeriodCtrlReadback_0_ "bRptPeriodCtrlReadback[0]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_0__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_10_ "bRptPeriodCtrlReadback[10]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_10__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_11_ "bRptPeriodCtrlReadback[11]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_11__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_12_ "bRptPeriodCtrlReadback[12]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_12__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_13_ "bRptPeriodCtrlReadback[13]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_13__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_14_ "bRptPeriodCtrlReadback[14]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_14__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_15_ "bRptPeriodCtrlReadback[15]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_15__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_16_ "bRptPeriodCtrlReadback[16]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_16__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_17_ "bRptPeriodCtrlReadback[17]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_17__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_18_ "bRptPeriodCtrlReadback[18]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_18__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_19_ "bRptPeriodCtrlReadback[19]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_19__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_1_ "bRptPeriodCtrlReadback[1]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_1__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_20_ "bRptPeriodCtrlReadback[20]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_20__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_21_ "bRptPeriodCtrlReadback[21]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_21__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_22_ "bRptPeriodCtrlReadback[22]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_22__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_23_ "bRptPeriodCtrlReadback[23]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_23__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_24_ "bRptPeriodCtrlReadback[24]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_24__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_25_ "bRptPeriodCtrlReadback[25]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_25__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_26_ "bRptPeriodCtrlReadback[26]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_26__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_27_ "bRptPeriodCtrlReadback[27]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_27__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_28_ "bRptPeriodCtrlReadback[28]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_28__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_29_ "bRptPeriodCtrlReadback[29]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_29__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_2_ "bRptPeriodCtrlReadback[2]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_2__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_30_ "bRptPeriodCtrlReadback[30]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_30__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_31_ "bRptPeriodCtrlReadback[31]") (joined + (portref D (instanceref RptCntReadbackDsGen_31__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_3_ "bRptPeriodCtrlReadback[3]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_3__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_4_ "bRptPeriodCtrlReadback[4]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_4__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_5_ "bRptPeriodCtrlReadback[5]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_5__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_6_ "bRptPeriodCtrlReadback[6]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_6__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_7_ "bRptPeriodCtrlReadback[7]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_7__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_8_ "bRptPeriodCtrlReadback[8]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_8__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bRptPeriodCtrlReadback_9_ "bRptPeriodCtrlReadback[9]") (joined + (portref D (instanceref RptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref RptCntReadbackDsGen_9__RptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref RptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bScratch_0_ "bScratch[0]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__0__i_6)) + (portref Q (instanceref bScratch_reg_0_)) + ) + ) + (net (rename bScratch_10_ "bScratch[10]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__10__i_3)) + (portref Q (instanceref bScratch_reg_10_)) + ) + ) + (net (rename bScratch_11_ "bScratch[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_4)) + (portref Q (instanceref bScratch_reg_11_)) + ) + ) + (net (rename bScratch_12_ "bScratch[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_1)) + (portref Q (instanceref bScratch_reg_12_)) + ) + ) + (net (rename bScratch_13_ "bScratch[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_2)) + (portref Q (instanceref bScratch_reg_13_)) + ) + ) + (net (rename bScratch_14_ "bScratch[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_4)) + (portref Q (instanceref bScratch_reg_14_)) + ) + ) + (net (rename bScratch_15_ "bScratch[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_4)) + (portref Q (instanceref bScratch_reg_15_)) + ) + ) + (net (rename bScratch_16_ "bScratch[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref Q (instanceref bScratch_reg_16_)) + ) + ) + (net (rename bScratch_17_ "bScratch[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_1)) + (portref Q (instanceref bScratch_reg_17_)) + ) + ) + (net (rename bScratch_18_ "bScratch[18]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__18__i_1)) + (portref Q (instanceref bScratch_reg_18_)) + ) + ) + (net (rename bScratch_19_ "bScratch[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_2)) + (portref Q (instanceref bScratch_reg_19_)) + ) + ) + (net (rename bScratch_1_ "bScratch[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_2)) + (portref Q (instanceref bScratch_reg_1_)) + ) + ) + (net (rename bScratch_20_ "bScratch[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_4)) + (portref Q (instanceref bScratch_reg_20_)) + ) + ) + (net (rename bScratch_21_ "bScratch[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_4)) + (portref Q (instanceref bScratch_reg_21_)) + ) + ) + (net (rename bScratch_22_ "bScratch[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_4)) + (portref Q (instanceref bScratch_reg_22_)) + ) + ) + (net (rename bScratch_23_ "bScratch[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_4)) + (portref Q (instanceref bScratch_reg_23_)) + ) + ) + (net (rename bScratch_24_ "bScratch[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_2)) + (portref Q (instanceref bScratch_reg_24_)) + ) + ) + (net (rename bScratch_25_ "bScratch[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_2)) + (portref Q (instanceref bScratch_reg_25_)) + ) + ) + (net (rename bScratch_26_ "bScratch[26]") (joined + (portref I2 (instanceref bRegPortOutLcl_Data__26__i_1)) + (portref Q (instanceref bScratch_reg_26_)) + ) + ) + (net (rename bScratch_27_ "bScratch[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_1)) + (portref Q (instanceref bScratch_reg_27_)) + ) + ) + (net (rename bScratch_28_ "bScratch[28]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_3)) + (portref Q (instanceref bScratch_reg_28_)) + ) + ) + (net (rename bScratch_29_ "bScratch[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_4)) + (portref Q (instanceref bScratch_reg_29_)) + ) + ) + (net (rename bScratch_2_ "bScratch[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_1)) + (portref Q (instanceref bScratch_reg_2_)) + ) + ) + (net (rename bScratch_30_ "bScratch[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_5)) + (portref Q (instanceref bScratch_reg_30_)) + ) + ) + (net (rename bScratch_31_ "bScratch[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_4)) + (portref Q (instanceref bScratch_reg_31_)) + ) + ) + (net (rename bScratch_31__i_1_n_0 "bScratch[31]_i_1_n_0") (joined + (portref CE (instanceref bScratch_reg_0_)) + (portref CE (instanceref bScratch_reg_10_)) + (portref CE (instanceref bScratch_reg_11_)) + (portref CE (instanceref bScratch_reg_12_)) + (portref CE (instanceref bScratch_reg_13_)) + (portref CE (instanceref bScratch_reg_14_)) + (portref CE (instanceref bScratch_reg_15_)) + (portref CE (instanceref bScratch_reg_16_)) + (portref CE (instanceref bScratch_reg_17_)) + (portref CE (instanceref bScratch_reg_18_)) + (portref CE (instanceref bScratch_reg_19_)) + (portref CE (instanceref bScratch_reg_1_)) + (portref CE (instanceref bScratch_reg_20_)) + (portref CE (instanceref bScratch_reg_21_)) + (portref CE (instanceref bScratch_reg_22_)) + (portref CE (instanceref bScratch_reg_23_)) + (portref CE (instanceref bScratch_reg_24_)) + (portref CE (instanceref bScratch_reg_25_)) + (portref CE (instanceref bScratch_reg_26_)) + (portref CE (instanceref bScratch_reg_27_)) + (portref CE (instanceref bScratch_reg_28_)) + (portref CE (instanceref bScratch_reg_29_)) + (portref CE (instanceref bScratch_reg_2_)) + (portref CE (instanceref bScratch_reg_30_)) + (portref CE (instanceref bScratch_reg_31_)) + (portref CE (instanceref bScratch_reg_3_)) + (portref CE (instanceref bScratch_reg_4_)) + (portref CE (instanceref bScratch_reg_5_)) + (portref CE (instanceref bScratch_reg_6_)) + (portref CE (instanceref bScratch_reg_7_)) + (portref CE (instanceref bScratch_reg_8_)) + (portref CE (instanceref bScratch_reg_9_)) + (portref O (instanceref bScratch_31__i_1)) + ) + ) + (net (rename bScratch_31__i_3_n_0 "bScratch[31]_i_3_n_0") (joined + (portref I0 (instanceref Gen0_FDCEx_i_3__0)) + (portref I0 (instanceref Gen0_FDCEx_i_3__1)) + (portref I0 (instanceref bScratch_31__i_1)) + (portref I3 (instanceref Gen0_FDCEx_i_3)) + (portref I3 (instanceref bPpsClkCrossDelayVal_3__i_3)) + (portref O (instanceref bScratch_31__i_3)) + ) + ) + (net (rename bScratch_31__i_4_n_0 "bScratch[31]_i_4_n_0") (joined + (portref I2 (instanceref bScratch_31__i_1)) + (portref I5 (instanceref bRegPortOutLcl_Data__16__i_4)) + (portref I5 (instanceref bRegPortOutLcl_Data__26__i_3)) + (portref I5 (instanceref bRegPortOutLcl_Data__28__i_5)) + (portref I5 (instanceref bRegPortOutLcl_Data__31__i_5)) + (portref O (instanceref bScratch_31__i_4)) + ) + ) + (net (rename bScratch_31__i_5_n_0 "bScratch[31]_i_5_n_0") (joined + (portref I5 (instanceref bScratch_31__i_1)) + (portref O (instanceref bScratch_31__i_5)) + ) + ) + (net (rename bScratch_3_ "bScratch[3]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__3__i_4)) + (portref Q (instanceref bScratch_reg_3_)) + ) + ) + (net (rename bScratch_4_ "bScratch[4]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__4__i_7)) + (portref Q (instanceref bScratch_reg_4_)) + ) + ) + (net (rename bScratch_5_ "bScratch[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_2)) + (portref Q (instanceref bScratch_reg_5_)) + ) + ) + (net (rename bScratch_6_ "bScratch[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_1)) + (portref Q (instanceref bScratch_reg_6_)) + ) + ) + (net (rename bScratch_7_ "bScratch[7]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__7__i_4)) + (portref Q (instanceref bScratch_reg_7_)) + ) + ) + (net (rename bScratch_8_ "bScratch[8]") (joined + (portref I0 (instanceref bRegPortOutLcl_Data__8__i_4)) + (portref Q (instanceref bScratch_reg_8_)) + ) + ) + (net (rename bScratch_9_ "bScratch[9]") (joined + (portref I5 (instanceref bRegPortOutLcl_Data__9__i_4)) + (portref Q (instanceref bScratch_reg_9_)) + ) + ) + (net bSpOffsetStored (joined + (portref CE (instanceref bRpOffsetStored_reg_0_)) + (portref CE (instanceref bRpOffsetStored_reg_10_)) + (portref CE (instanceref bRpOffsetStored_reg_11_)) + (portref CE (instanceref bRpOffsetStored_reg_12_)) + (portref CE (instanceref bRpOffsetStored_reg_13_)) + (portref CE (instanceref bRpOffsetStored_reg_14_)) + (portref CE (instanceref bRpOffsetStored_reg_15_)) + (portref CE (instanceref bRpOffsetStored_reg_16_)) + (portref CE (instanceref bRpOffsetStored_reg_17_)) + (portref CE (instanceref bRpOffsetStored_reg_18_)) + (portref CE (instanceref bRpOffsetStored_reg_19_)) + (portref CE (instanceref bRpOffsetStored_reg_1_)) + (portref CE (instanceref bRpOffsetStored_reg_20_)) + (portref CE (instanceref bRpOffsetStored_reg_21_)) + (portref CE (instanceref bRpOffsetStored_reg_22_)) + (portref CE (instanceref bRpOffsetStored_reg_23_)) + (portref CE (instanceref bRpOffsetStored_reg_24_)) + (portref CE (instanceref bRpOffsetStored_reg_25_)) + (portref CE (instanceref bRpOffsetStored_reg_26_)) + (portref CE (instanceref bRpOffsetStored_reg_27_)) + (portref CE (instanceref bRpOffsetStored_reg_28_)) + (portref CE (instanceref bRpOffsetStored_reg_29_)) + (portref CE (instanceref bRpOffsetStored_reg_2_)) + (portref CE (instanceref bRpOffsetStored_reg_30_)) + (portref CE (instanceref bRpOffsetStored_reg_31_)) + (portref CE (instanceref bRpOffsetStored_reg_32_)) + (portref CE (instanceref bRpOffsetStored_reg_33_)) + (portref CE (instanceref bRpOffsetStored_reg_34_)) + (portref CE (instanceref bRpOffsetStored_reg_35_)) + (portref CE (instanceref bRpOffsetStored_reg_36_)) + (portref CE (instanceref bRpOffsetStored_reg_37_)) + (portref CE (instanceref bRpOffsetStored_reg_38_)) + (portref CE (instanceref bRpOffsetStored_reg_39_)) + (portref CE (instanceref bRpOffsetStored_reg_3_)) + (portref CE (instanceref bRpOffsetStored_reg_4_)) + (portref CE (instanceref bRpOffsetStored_reg_5_)) + (portref CE (instanceref bRpOffsetStored_reg_6_)) + (portref CE (instanceref bRpOffsetStored_reg_7_)) + (portref CE (instanceref bRpOffsetStored_reg_8_)) + (portref CE (instanceref bRpOffsetStored_reg_9_)) + (portref CE (instanceref bSpOffsetStored_reg_0_)) + (portref CE (instanceref bSpOffsetStored_reg_10_)) + (portref CE (instanceref bSpOffsetStored_reg_11_)) + (portref CE (instanceref bSpOffsetStored_reg_12_)) + (portref CE (instanceref bSpOffsetStored_reg_13_)) + (portref CE (instanceref bSpOffsetStored_reg_14_)) + (portref CE (instanceref bSpOffsetStored_reg_15_)) + (portref CE (instanceref bSpOffsetStored_reg_16_)) + (portref CE (instanceref bSpOffsetStored_reg_17_)) + (portref CE (instanceref bSpOffsetStored_reg_18_)) + (portref CE (instanceref bSpOffsetStored_reg_19_)) + (portref CE (instanceref bSpOffsetStored_reg_1_)) + (portref CE (instanceref bSpOffsetStored_reg_20_)) + (portref CE (instanceref bSpOffsetStored_reg_21_)) + (portref CE (instanceref bSpOffsetStored_reg_22_)) + (portref CE (instanceref bSpOffsetStored_reg_23_)) + (portref CE (instanceref bSpOffsetStored_reg_24_)) + (portref CE (instanceref bSpOffsetStored_reg_25_)) + (portref CE (instanceref bSpOffsetStored_reg_26_)) + (portref CE (instanceref bSpOffsetStored_reg_27_)) + (portref CE (instanceref bSpOffsetStored_reg_28_)) + (portref CE (instanceref bSpOffsetStored_reg_29_)) + (portref CE (instanceref bSpOffsetStored_reg_2_)) + (portref CE (instanceref bSpOffsetStored_reg_30_)) + (portref CE (instanceref bSpOffsetStored_reg_31_)) + (portref CE (instanceref bSpOffsetStored_reg_3_)) + (portref CE (instanceref bSpOffsetStored_reg_4_)) + (portref CE (instanceref bSpOffsetStored_reg_5_)) + (portref CE (instanceref bSpOffsetStored_reg_6_)) + (portref CE (instanceref bSpOffsetStored_reg_7_)) + (portref CE (instanceref bSpOffsetStored_reg_8_)) + (portref CE (instanceref bSpOffsetStored_reg_9_)) + (portref I1 (instanceref bOffsetUpdated_i_1)) + (portref O (instanceref bRpOffsetStored_39__i_1)) + ) + ) + (net (rename bSpOffsetStored_0__i_1_n_0 "bSpOffsetStored[0]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_0_)) + (portref O (instanceref bSpOffsetStored_0__i_1)) + ) + ) + (net (rename bSpOffsetStored_10__i_1_n_0 "bSpOffsetStored[10]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_10_)) + (portref O (instanceref bSpOffsetStored_10__i_1)) + ) + ) + (net (rename bSpOffsetStored_11__i_1_n_0 "bSpOffsetStored[11]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_11_)) + (portref O (instanceref bSpOffsetStored_11__i_1)) + ) + ) + (net (rename bSpOffsetStored_12__i_1_n_0 "bSpOffsetStored[12]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_12_)) + (portref O (instanceref bSpOffsetStored_12__i_1)) + ) + ) + (net (rename bSpOffsetStored_13__i_1_n_0 "bSpOffsetStored[13]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_13_)) + (portref O (instanceref bSpOffsetStored_13__i_1)) + ) + ) + (net (rename bSpOffsetStored_14__i_1_n_0 "bSpOffsetStored[14]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_14_)) + (portref O (instanceref bSpOffsetStored_14__i_1)) + ) + ) + (net (rename bSpOffsetStored_15__i_1_n_0 "bSpOffsetStored[15]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_15_)) + (portref O (instanceref bSpOffsetStored_15__i_1)) + ) + ) + (net (rename bSpOffsetStored_16__i_1_n_0 "bSpOffsetStored[16]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_16_)) + (portref O (instanceref bSpOffsetStored_16__i_1)) + ) + ) + (net (rename bSpOffsetStored_17__i_1_n_0 "bSpOffsetStored[17]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_17_)) + (portref O (instanceref bSpOffsetStored_17__i_1)) + ) + ) + (net (rename bSpOffsetStored_18__i_1_n_0 "bSpOffsetStored[18]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_18_)) + (portref O (instanceref bSpOffsetStored_18__i_1)) + ) + ) + (net (rename bSpOffsetStored_19__i_1_n_0 "bSpOffsetStored[19]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_19_)) + (portref O (instanceref bSpOffsetStored_19__i_1)) + ) + ) + (net (rename bSpOffsetStored_1__i_1_n_0 "bSpOffsetStored[1]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_1_)) + (portref O (instanceref bSpOffsetStored_1__i_1)) + ) + ) + (net (rename bSpOffsetStored_20__i_1_n_0 "bSpOffsetStored[20]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_20_)) + (portref O (instanceref bSpOffsetStored_20__i_1)) + ) + ) + (net (rename bSpOffsetStored_21__i_1_n_0 "bSpOffsetStored[21]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_21_)) + (portref O (instanceref bSpOffsetStored_21__i_1)) + ) + ) + (net (rename bSpOffsetStored_22__i_1_n_0 "bSpOffsetStored[22]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_22_)) + (portref O (instanceref bSpOffsetStored_22__i_1)) + ) + ) + (net (rename bSpOffsetStored_23__i_1_n_0 "bSpOffsetStored[23]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_23_)) + (portref O (instanceref bSpOffsetStored_23__i_1)) + ) + ) + (net (rename bSpOffsetStored_24__i_1_n_0 "bSpOffsetStored[24]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_24_)) + (portref O (instanceref bSpOffsetStored_24__i_1)) + ) + ) + (net (rename bSpOffsetStored_25__i_1_n_0 "bSpOffsetStored[25]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_25_)) + (portref O (instanceref bSpOffsetStored_25__i_1)) + ) + ) + (net (rename bSpOffsetStored_26__i_1_n_0 "bSpOffsetStored[26]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_26_)) + (portref O (instanceref bSpOffsetStored_26__i_1)) + ) + ) + (net (rename bSpOffsetStored_27__i_1_n_0 "bSpOffsetStored[27]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_27_)) + (portref O (instanceref bSpOffsetStored_27__i_1)) + ) + ) + (net (rename bSpOffsetStored_28__i_1_n_0 "bSpOffsetStored[28]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_28_)) + (portref O (instanceref bSpOffsetStored_28__i_1)) + ) + ) + (net (rename bSpOffsetStored_29__i_1_n_0 "bSpOffsetStored[29]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_29_)) + (portref O (instanceref bSpOffsetStored_29__i_1)) + ) + ) + (net (rename bSpOffsetStored_2__i_1_n_0 "bSpOffsetStored[2]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_2_)) + (portref O (instanceref bSpOffsetStored_2__i_1)) + ) + ) + (net (rename bSpOffsetStored_30__i_1_n_0 "bSpOffsetStored[30]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_30_)) + (portref O (instanceref bSpOffsetStored_30__i_1)) + ) + ) + (net (rename bSpOffsetStored_31__i_1_n_0 "bSpOffsetStored[31]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_31_)) + (portref O (instanceref bSpOffsetStored_31__i_1)) + ) + ) + (net (rename bSpOffsetStored_3__i_1_n_0 "bSpOffsetStored[3]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_3_)) + (portref O (instanceref bSpOffsetStored_3__i_1)) + ) + ) + (net (rename bSpOffsetStored_4__i_1_n_0 "bSpOffsetStored[4]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_4_)) + (portref O (instanceref bSpOffsetStored_4__i_1)) + ) + ) + (net (rename bSpOffsetStored_5__i_1_n_0 "bSpOffsetStored[5]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_5_)) + (portref O (instanceref bSpOffsetStored_5__i_1)) + ) + ) + (net (rename bSpOffsetStored_6__i_1_n_0 "bSpOffsetStored[6]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_6_)) + (portref O (instanceref bSpOffsetStored_6__i_1)) + ) + ) + (net (rename bSpOffsetStored_7__i_1_n_0 "bSpOffsetStored[7]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_7_)) + (portref O (instanceref bSpOffsetStored_7__i_1)) + ) + ) + (net (rename bSpOffsetStored_8__i_1_n_0 "bSpOffsetStored[8]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_8_)) + (portref O (instanceref bSpOffsetStored_8__i_1)) + ) + ) + (net (rename bSpOffsetStored_9__i_1_n_0 "bSpOffsetStored[9]_i_1_n_0") (joined + (portref D (instanceref bSpOffsetStored_reg_9_)) + (portref O (instanceref bSpOffsetStored_9__i_1)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__0_ "bSpOffsetStored_reg_n_0_[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_0_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__10_ "bSpOffsetStored_reg_n_0_[10]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_10_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__11_ "bSpOffsetStored_reg_n_0_[11]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__11__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_11_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__12_ "bSpOffsetStored_reg_n_0_[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_12_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__13_ "bSpOffsetStored_reg_n_0_[13]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__13__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_13_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__14_ "bSpOffsetStored_reg_n_0_[14]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__14__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_14_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__15_ "bSpOffsetStored_reg_n_0_[15]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__15__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_15_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__16_ "bSpOffsetStored_reg_n_0_[16]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_16_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__17_ "bSpOffsetStored_reg_n_0_[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_17_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__18_ "bSpOffsetStored_reg_n_0_[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_18_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__19_ "bSpOffsetStored_reg_n_0_[19]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__19__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_19_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__1_ "bSpOffsetStored_reg_n_0_[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_1_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__20_ "bSpOffsetStored_reg_n_0_[20]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__20__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_20_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__21_ "bSpOffsetStored_reg_n_0_[21]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__21__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_21_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__22_ "bSpOffsetStored_reg_n_0_[22]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__22__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_22_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__23_ "bSpOffsetStored_reg_n_0_[23]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__23__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_23_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__24_ "bSpOffsetStored_reg_n_0_[24]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__24__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_24_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__25_ "bSpOffsetStored_reg_n_0_[25]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__25__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_25_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__26_ "bSpOffsetStored_reg_n_0_[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_26_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__27_ "bSpOffsetStored_reg_n_0_[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_27_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__28_ "bSpOffsetStored_reg_n_0_[28]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_28_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__29_ "bSpOffsetStored_reg_n_0_[29]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__29__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_29_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__2_ "bSpOffsetStored_reg_n_0_[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_2_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__30_ "bSpOffsetStored_reg_n_0_[30]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__30__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_30_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__31_ "bSpOffsetStored_reg_n_0_[31]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__31__i_2)) + (portref Q (instanceref bSpOffsetStored_reg_31_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__3_ "bSpOffsetStored_reg_n_0_[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_3_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__4_ "bSpOffsetStored_reg_n_0_[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_4_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__5_ "bSpOffsetStored_reg_n_0_[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_4)) + (portref Q (instanceref bSpOffsetStored_reg_5_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__6_ "bSpOffsetStored_reg_n_0_[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_6_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__7_ "bSpOffsetStored_reg_n_0_[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_7_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__8_ "bSpOffsetStored_reg_n_0_[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_3)) + (portref Q (instanceref bSpOffsetStored_reg_8_)) + ) + ) + (net (rename bSpOffsetStored_reg_n_0__9_ "bSpOffsetStored_reg_n_0_[9]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref bSpOffsetStored_reg_9_)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_0_ "bSpPeriodCtrlReadbackSyncReset[0]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__0__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_10_ "bSpPeriodCtrlReadbackSyncReset[10]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__10__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_11_ "bSpPeriodCtrlReadbackSyncReset[11]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_12_ "bSpPeriodCtrlReadbackSyncReset[12]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__12__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_13_ "bSpPeriodCtrlReadbackSyncReset[13]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_14_ "bSpPeriodCtrlReadbackSyncReset[14]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_15_ "bSpPeriodCtrlReadbackSyncReset[15]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_16_ "bSpPeriodCtrlReadbackSyncReset[16]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__16__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_17_ "bSpPeriodCtrlReadbackSyncReset[17]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__17__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_18_ "bSpPeriodCtrlReadbackSyncReset[18]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__18__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_19_ "bSpPeriodCtrlReadbackSyncReset[19]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_1_ "bSpPeriodCtrlReadbackSyncReset[1]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__1__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_20_ "bSpPeriodCtrlReadbackSyncReset[20]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_21_ "bSpPeriodCtrlReadbackSyncReset[21]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_22_ "bSpPeriodCtrlReadbackSyncReset[22]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_23_ "bSpPeriodCtrlReadbackSyncReset[23]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_24_ "bSpPeriodCtrlReadbackSyncReset[24]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_25_ "bSpPeriodCtrlReadbackSyncReset[25]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_26_ "bSpPeriodCtrlReadbackSyncReset[26]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__26__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_27_ "bSpPeriodCtrlReadbackSyncReset[27]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__27__i_6)) + (portref Q (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_28_ "bSpPeriodCtrlReadbackSyncReset[28]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__28__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_29_ "bSpPeriodCtrlReadbackSyncReset[29]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_2_ "bSpPeriodCtrlReadbackSyncReset[2]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__2__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_30_ "bSpPeriodCtrlReadbackSyncReset[30]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_31_ "bSpPeriodCtrlReadbackSyncReset[31]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_3_ "bSpPeriodCtrlReadbackSyncReset[3]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__3__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_4_ "bSpPeriodCtrlReadbackSyncReset[4]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__4__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_5_ "bSpPeriodCtrlReadbackSyncReset[5]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__5__i_3)) + (portref Q (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_6_ "bSpPeriodCtrlReadbackSyncReset[6]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__6__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_7_ "bSpPeriodCtrlReadbackSyncReset[7]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__7__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_8_ "bSpPeriodCtrlReadbackSyncReset[8]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__8__i_2)) + (portref Q (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadbackSyncReset_9_ "bSpPeriodCtrlReadbackSyncReset[9]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__9__i_5)) + (portref Q (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSpPeriodCtrlReadback_0_ "bSpPeriodCtrlReadback[0]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_0__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_10_ "bSpPeriodCtrlReadback[10]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_10__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_11_ "bSpPeriodCtrlReadback[11]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_11__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_12_ "bSpPeriodCtrlReadback[12]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_12__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_13_ "bSpPeriodCtrlReadback[13]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_13__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_14_ "bSpPeriodCtrlReadback[14]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_14__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_15_ "bSpPeriodCtrlReadback[15]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_15__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_16_ "bSpPeriodCtrlReadback[16]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_16__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_17_ "bSpPeriodCtrlReadback[17]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_17__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_18_ "bSpPeriodCtrlReadback[18]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_18__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_19_ "bSpPeriodCtrlReadback[19]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_19__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_1_ "bSpPeriodCtrlReadback[1]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_1__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_20_ "bSpPeriodCtrlReadback[20]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_20__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_21_ "bSpPeriodCtrlReadback[21]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_21__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_22_ "bSpPeriodCtrlReadback[22]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_22__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_23_ "bSpPeriodCtrlReadback[23]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_23__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_24_ "bSpPeriodCtrlReadback[24]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_24__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_25_ "bSpPeriodCtrlReadback[25]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_25__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_26_ "bSpPeriodCtrlReadback[26]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_26__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_27_ "bSpPeriodCtrlReadback[27]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_27__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_28_ "bSpPeriodCtrlReadback[28]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_28__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_29_ "bSpPeriodCtrlReadback[29]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_29__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_2_ "bSpPeriodCtrlReadback[2]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_2__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_30_ "bSpPeriodCtrlReadback[30]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_30__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_31_ "bSpPeriodCtrlReadback[31]") (joined + (portref D (instanceref SpCntReadbackDsGen_31__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_3_ "bSpPeriodCtrlReadback[3]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_3__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_4_ "bSpPeriodCtrlReadback[4]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_4__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_5_ "bSpPeriodCtrlReadback[5]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_5__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_6_ "bSpPeriodCtrlReadback[6]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_6__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_7_ "bSpPeriodCtrlReadback[7]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_7__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_8_ "bSpPeriodCtrlReadback[8]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_8__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSpPeriodCtrlReadback_9_ "bSpPeriodCtrlReadback[9]") (joined + (portref D (instanceref SpCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SpCntReadbackDsGen_9__SpCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SpCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_0_ "bSptPeriodCtrlReadbackSyncReset[0]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__0__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_10_ "bSptPeriodCtrlReadbackSyncReset[10]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__10__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_11_ "bSptPeriodCtrlReadbackSyncReset[11]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__11__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_12_ "bSptPeriodCtrlReadbackSyncReset[12]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__12__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_13_ "bSptPeriodCtrlReadbackSyncReset[13]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__13__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_14_ "bSptPeriodCtrlReadbackSyncReset[14]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__14__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_15_ "bSptPeriodCtrlReadbackSyncReset[15]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__15__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_16_ "bSptPeriodCtrlReadbackSyncReset[16]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__16__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_17_ "bSptPeriodCtrlReadbackSyncReset[17]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__17__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_18_ "bSptPeriodCtrlReadbackSyncReset[18]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__18__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_19_ "bSptPeriodCtrlReadbackSyncReset[19]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__19__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_1_ "bSptPeriodCtrlReadbackSyncReset[1]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__1__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_20_ "bSptPeriodCtrlReadbackSyncReset[20]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__20__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_21_ "bSptPeriodCtrlReadbackSyncReset[21]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__21__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_22_ "bSptPeriodCtrlReadbackSyncReset[22]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__22__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_23_ "bSptPeriodCtrlReadbackSyncReset[23]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__23__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_24_ "bSptPeriodCtrlReadbackSyncReset[24]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__24__i_4)) + (portref Q (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_25_ "bSptPeriodCtrlReadbackSyncReset[25]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__25__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_26_ "bSptPeriodCtrlReadbackSyncReset[26]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__26__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_27_ "bSptPeriodCtrlReadbackSyncReset[27]") (joined + (portref I1 (instanceref bRegPortOutLcl_Data__27__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_28_ "bSptPeriodCtrlReadbackSyncReset[28]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__28__i_6)) + (portref Q (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_29_ "bSptPeriodCtrlReadbackSyncReset[29]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__29__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_2_ "bSptPeriodCtrlReadbackSyncReset[2]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__2__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_30_ "bSptPeriodCtrlReadbackSyncReset[30]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__30__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_31_ "bSptPeriodCtrlReadbackSyncReset[31]") (joined + (portref I4 (instanceref bRegPortOutLcl_Data__31__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_3_ "bSptPeriodCtrlReadbackSyncReset[3]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__3__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_4_ "bSptPeriodCtrlReadbackSyncReset[4]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__4__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_5_ "bSptPeriodCtrlReadbackSyncReset[5]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__5__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_6_ "bSptPeriodCtrlReadbackSyncReset[6]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__6__i_3)) + (portref Q (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_7_ "bSptPeriodCtrlReadbackSyncReset[7]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__7__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_8_ "bSptPeriodCtrlReadbackSyncReset[8]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__8__i_5)) + (portref Q (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadbackSyncReset_9_ "bSptPeriodCtrlReadbackSyncReset[9]") (joined + (portref I3 (instanceref bRegPortOutLcl_Data__9__i_2)) + (portref Q (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net (rename bSptPeriodCtrlReadback_0_ "bSptPeriodCtrlReadback[0]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_0__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_0_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_10_ "bSptPeriodCtrlReadback[10]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_10__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_10_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_11_ "bSptPeriodCtrlReadback[11]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_11__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_11_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_12_ "bSptPeriodCtrlReadback[12]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_12__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_12_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_13_ "bSptPeriodCtrlReadback[13]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_13__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_13_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_14_ "bSptPeriodCtrlReadback[14]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_14__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_14_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_15_ "bSptPeriodCtrlReadback[15]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_15__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_15_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_16_ "bSptPeriodCtrlReadback[16]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_16__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_16_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_17_ "bSptPeriodCtrlReadback[17]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_17__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_17_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_18_ "bSptPeriodCtrlReadback[18]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_18__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_18_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_19_ "bSptPeriodCtrlReadback[19]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_19__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_19_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_1_ "bSptPeriodCtrlReadback[1]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_1__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_1_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_20_ "bSptPeriodCtrlReadback[20]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_20__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_20_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_21_ "bSptPeriodCtrlReadback[21]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_21__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_21_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_22_ "bSptPeriodCtrlReadback[22]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_22__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_22_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_23_ "bSptPeriodCtrlReadback[23]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_23__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_23__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_23_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_24_ "bSptPeriodCtrlReadback[24]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_24__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_24__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_24_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_25_ "bSptPeriodCtrlReadback[25]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_25__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_25__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_25_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_26_ "bSptPeriodCtrlReadback[26]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_26__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_26__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_26_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_27_ "bSptPeriodCtrlReadback[27]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_27__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_27__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_27_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_28_ "bSptPeriodCtrlReadback[28]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_28__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_28__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_28_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_29_ "bSptPeriodCtrlReadback[29]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_29__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_29__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_29_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_2_ "bSptPeriodCtrlReadback[2]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_2__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_2_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_30_ "bSptPeriodCtrlReadback[30]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_30__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_30__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_30_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_31_ "bSptPeriodCtrlReadback[31]") (joined + (portref D (instanceref SptCntReadbackDsGen_31__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_31_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_3_ "bSptPeriodCtrlReadback[3]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_3__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_3_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_4_ "bSptPeriodCtrlReadback[4]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_4__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_4_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_5_ "bSptPeriodCtrlReadback[5]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_5__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_5_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_6_ "bSptPeriodCtrlReadback[6]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_6__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_6_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_7_ "bSptPeriodCtrlReadback[7]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_7__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_7_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_8_ "bSptPeriodCtrlReadback[8]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_8__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_8_)) + ) + ) + (net (rename bSptPeriodCtrlReadback_9_ "bSptPeriodCtrlReadback[9]") (joined + (portref D (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref D (instanceref SptCntReadbackDsGen_9__SptCntReadbackDs_DoubleSyncAsyncInBasex_oSig_msx_Gen0_FDCEx)) + (portref Q (instanceref SptCntHs_BlkIn_iLclStoredData_reg_9_)) + ) + ) + (net iDlyPush (joined + (portref I0 (instanceref Gen0_FDCEx_i_1__4)) + (portref Q (instanceref RpCntHs_BlkIn_iDlyPush_reg)) + ) + ) + (net mOffsetsValid (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iDlyPush_reg)) + (portref I0 (instanceref Gen0_FDCEx_i_1__11)) + (portref mOffsetsValid) + ) + ) + (net (rename mRpOffset_0_ "mRpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_40_)) + (portref (member mRpOffset 39)) + ) + ) + (net (rename mRpOffset_10_ "mRpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_50_)) + (portref (member mRpOffset 29)) + ) + ) + (net (rename mRpOffset_11_ "mRpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_51_)) + (portref (member mRpOffset 28)) + ) + ) + (net (rename mRpOffset_12_ "mRpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_52_)) + (portref (member mRpOffset 27)) + ) + ) + (net (rename mRpOffset_13_ "mRpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_53_)) + (portref (member mRpOffset 26)) + ) + ) + (net (rename mRpOffset_14_ "mRpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_54_)) + (portref (member mRpOffset 25)) + ) + ) + (net (rename mRpOffset_15_ "mRpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_55_)) + (portref (member mRpOffset 24)) + ) + ) + (net (rename mRpOffset_16_ "mRpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_56_)) + (portref (member mRpOffset 23)) + ) + ) + (net (rename mRpOffset_17_ "mRpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_57_)) + (portref (member mRpOffset 22)) + ) + ) + (net (rename mRpOffset_18_ "mRpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_58_)) + (portref (member mRpOffset 21)) + ) + ) + (net (rename mRpOffset_19_ "mRpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_59_)) + (portref (member mRpOffset 20)) + ) + ) + (net (rename mRpOffset_1_ "mRpOffset[1]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_41_)) + (portref (member mRpOffset 38)) + ) + ) + (net (rename mRpOffset_20_ "mRpOffset[20]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_60_)) + (portref (member mRpOffset 19)) + ) + ) + (net (rename mRpOffset_21_ "mRpOffset[21]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_61_)) + (portref (member mRpOffset 18)) + ) + ) + (net (rename mRpOffset_22_ "mRpOffset[22]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_62_)) + (portref (member mRpOffset 17)) + ) + ) + (net (rename mRpOffset_23_ "mRpOffset[23]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_63_)) + (portref (member mRpOffset 16)) + ) + ) + (net (rename mRpOffset_24_ "mRpOffset[24]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_64_)) + (portref (member mRpOffset 15)) + ) + ) + (net (rename mRpOffset_25_ "mRpOffset[25]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_65_)) + (portref (member mRpOffset 14)) + ) + ) + (net (rename mRpOffset_26_ "mRpOffset[26]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_66_)) + (portref (member mRpOffset 13)) + ) + ) + (net (rename mRpOffset_27_ "mRpOffset[27]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_67_)) + (portref (member mRpOffset 12)) + ) + ) + (net (rename mRpOffset_28_ "mRpOffset[28]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_68_)) + (portref (member mRpOffset 11)) + ) + ) + (net (rename mRpOffset_29_ "mRpOffset[29]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_69_)) + (portref (member mRpOffset 10)) + ) + ) + (net (rename mRpOffset_2_ "mRpOffset[2]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_42_)) + (portref (member mRpOffset 37)) + ) + ) + (net (rename mRpOffset_30_ "mRpOffset[30]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_70_)) + (portref (member mRpOffset 9)) + ) + ) + (net (rename mRpOffset_31_ "mRpOffset[31]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_71_)) + (portref (member mRpOffset 8)) + ) + ) + (net (rename mRpOffset_32_ "mRpOffset[32]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_72_)) + (portref (member mRpOffset 7)) + ) + ) + (net (rename mRpOffset_33_ "mRpOffset[33]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_73_)) + (portref (member mRpOffset 6)) + ) + ) + (net (rename mRpOffset_34_ "mRpOffset[34]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_74_)) + (portref (member mRpOffset 5)) + ) + ) + (net (rename mRpOffset_35_ "mRpOffset[35]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_75_)) + (portref (member mRpOffset 4)) + ) + ) + (net (rename mRpOffset_36_ "mRpOffset[36]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_76_)) + (portref (member mRpOffset 3)) + ) + ) + (net (rename mRpOffset_37_ "mRpOffset[37]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_77_)) + (portref (member mRpOffset 2)) + ) + ) + (net (rename mRpOffset_38_ "mRpOffset[38]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_78_)) + (portref (member mRpOffset 1)) + ) + ) + (net (rename mRpOffset_39_ "mRpOffset[39]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_79_)) + (portref (member mRpOffset 0)) + ) + ) + (net (rename mRpOffset_3_ "mRpOffset[3]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_43_)) + (portref (member mRpOffset 36)) + ) + ) + (net (rename mRpOffset_4_ "mRpOffset[4]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_44_)) + (portref (member mRpOffset 35)) + ) + ) + (net (rename mRpOffset_5_ "mRpOffset[5]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_45_)) + (portref (member mRpOffset 34)) + ) + ) + (net (rename mRpOffset_6_ "mRpOffset[6]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_46_)) + (portref (member mRpOffset 33)) + ) + ) + (net (rename mRpOffset_7_ "mRpOffset[7]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_47_)) + (portref (member mRpOffset 32)) + ) + ) + (net (rename mRpOffset_8_ "mRpOffset[8]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_48_)) + (portref (member mRpOffset 31)) + ) + ) + (net (rename mRpOffset_9_ "mRpOffset[9]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_49_)) + (portref (member mRpOffset 30)) + ) + ) + (net (rename mSpOffset_0_ "mSpOffset[0]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_0_)) + (portref (member mSpOffset 39)) + ) + ) + (net (rename mSpOffset_10_ "mSpOffset[10]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_10_)) + (portref (member mSpOffset 29)) + ) + ) + (net (rename mSpOffset_11_ "mSpOffset[11]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_11_)) + (portref (member mSpOffset 28)) + ) + ) + (net (rename mSpOffset_12_ "mSpOffset[12]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_12_)) + (portref (member mSpOffset 27)) + ) + ) + (net (rename mSpOffset_13_ "mSpOffset[13]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_13_)) + (portref (member mSpOffset 26)) + ) + ) + (net (rename mSpOffset_14_ "mSpOffset[14]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_14_)) + (portref (member mSpOffset 25)) + ) + ) + (net (rename mSpOffset_15_ "mSpOffset[15]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_15_)) + (portref (member mSpOffset 24)) + ) + ) + (net (rename mSpOffset_16_ "mSpOffset[16]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_16_)) + (portref (member mSpOffset 23)) + ) + ) + (net (rename mSpOffset_17_ "mSpOffset[17]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_17_)) + (portref (member mSpOffset 22)) + ) + ) + (net (rename mSpOffset_18_ "mSpOffset[18]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_18_)) + (portref (member mSpOffset 21)) + ) + ) + (net (rename mSpOffset_19_ "mSpOffset[19]") (joined + (portref D (instanceref IncomingOffsetHs_HBx_BlkIn_iLclStoredData_reg_19_)) + (portref (member mSpOffset 20)) + ) + ) + (net (rename mSpOffset_1_ "mSpOffset[1]") (joined + (portref D (instanceref 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OffsetsDsGen_48__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_49_out (joined + (portref I0 (instanceref bRpOffsetStored_9__i_1)) + (portref Q (instanceref OffsetsDsGen_49__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_4_out (joined + (portref I0 (instanceref bSpOffsetStored_4__i_1)) + (portref Q (instanceref OffsetsDsGen_4__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_50_out (joined + (portref I0 (instanceref bRpOffsetStored_10__i_1)) + (portref Q (instanceref OffsetsDsGen_50__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_51_out (joined + (portref I0 (instanceref bRpOffsetStored_11__i_1)) + (portref Q (instanceref OffsetsDsGen_51__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_52_out (joined + (portref I0 (instanceref bRpOffsetStored_12__i_1)) + (portref Q (instanceref OffsetsDsGen_52__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_53_out (joined + (portref I0 (instanceref bRpOffsetStored_13__i_1)) + (portref Q (instanceref OffsetsDsGen_53__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_54_out (joined + (portref I0 (instanceref bRpOffsetStored_14__i_1)) + (portref Q (instanceref OffsetsDsGen_54__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_55_out (joined + (portref I0 (instanceref bRpOffsetStored_15__i_1)) + (portref Q (instanceref OffsetsDsGen_55__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_56_out (joined + (portref I0 (instanceref bRpOffsetStored_16__i_1)) + (portref Q (instanceref OffsetsDsGen_56__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_57_out (joined + (portref I0 (instanceref bRpOffsetStored_17__i_1)) + (portref Q (instanceref OffsetsDsGen_57__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_58_out (joined + (portref I0 (instanceref bRpOffsetStored_18__i_1)) + (portref Q (instanceref OffsetsDsGen_58__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_59_out (joined + (portref I0 (instanceref bRpOffsetStored_19__i_1)) + (portref Q (instanceref OffsetsDsGen_59__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_5_out (joined + (portref I0 (instanceref bSpOffsetStored_5__i_1)) + (portref Q (instanceref OffsetsDsGen_5__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_60_out (joined + (portref I0 (instanceref bRpOffsetStored_20__i_1)) + (portref Q (instanceref OffsetsDsGen_60__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_61_out (joined + (portref I0 (instanceref bRpOffsetStored_21__i_1)) + (portref Q (instanceref OffsetsDsGen_61__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_62_out (joined + (portref I0 (instanceref bRpOffsetStored_22__i_1)) + (portref Q (instanceref OffsetsDsGen_62__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_63_out (joined + (portref I0 (instanceref bRpOffsetStored_23__i_1)) + (portref Q (instanceref OffsetsDsGen_63__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_64_out (joined + (portref I0 (instanceref bRpOffsetStored_24__i_1)) + (portref Q (instanceref OffsetsDsGen_64__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_65_out (joined + (portref I0 (instanceref bRpOffsetStored_25__i_1)) + (portref Q (instanceref OffsetsDsGen_65__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_66_out (joined + (portref I0 (instanceref bRpOffsetStored_26__i_1)) + (portref Q (instanceref OffsetsDsGen_66__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_67_out (joined + (portref I0 (instanceref bRpOffsetStored_27__i_1)) + (portref Q (instanceref OffsetsDsGen_67__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_68_out (joined + (portref I0 (instanceref bRpOffsetStored_28__i_1)) + (portref Q (instanceref OffsetsDsGen_68__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_69_out (joined + (portref I0 (instanceref bRpOffsetStored_29__i_1)) + (portref Q (instanceref OffsetsDsGen_69__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_6_out (joined + (portref I0 (instanceref bSpOffsetStored_6__i_1)) + (portref Q (instanceref OffsetsDsGen_6__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_70_out (joined + (portref I0 (instanceref bRpOffsetStored_30__i_1)) + (portref Q (instanceref OffsetsDsGen_70__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_71_out (joined + (portref I0 (instanceref bRpOffsetStored_31__i_1)) + (portref Q (instanceref OffsetsDsGen_71__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_72_out (joined + (portref I0 (instanceref bRpOffsetStored_32__i_1)) + (portref Q (instanceref OffsetsDsGen_72__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_73_out (joined + (portref I0 (instanceref bRpOffsetStored_33__i_1)) + (portref Q (instanceref OffsetsDsGen_73__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_74_out (joined + (portref I0 (instanceref bRpOffsetStored_34__i_1)) + (portref Q (instanceref OffsetsDsGen_74__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_75_out (joined + (portref I0 (instanceref bRpOffsetStored_35__i_1)) + (portref Q (instanceref OffsetsDsGen_75__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_76_out (joined + (portref I0 (instanceref bRpOffsetStored_36__i_1)) + (portref Q (instanceref OffsetsDsGen_76__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_77_out (joined + (portref I0 (instanceref bRpOffsetStored_37__i_1)) + (portref Q (instanceref OffsetsDsGen_77__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_78_out (joined + (portref I0 (instanceref bRpOffsetStored_38__i_1)) + (portref Q (instanceref OffsetsDsGen_78__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_79_out (joined + (portref I0 (instanceref bRpOffsetStored_39__i_2)) + (portref Q (instanceref OffsetsDsGen_79__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_7_out (joined + (portref I0 (instanceref bSpOffsetStored_7__i_1)) + (portref Q (instanceref OffsetsDsGen_7__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_8_out (joined + (portref I0 (instanceref bSpOffsetStored_8__i_1)) + (portref Q (instanceref OffsetsDsGen_8__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net p_9_out (joined + (portref I0 (instanceref bSpOffsetStored_9__i_1)) + (portref Q (instanceref OffsetsDsGen_9__OffsetsDs_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + ) + ) + (net rEnablePpsCrossing (joined + (portref Q (instanceref PpsCrossEnDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnablePpsCrossing) + ) + ) + (net rEnableTdc (joined + (portref Q (instanceref EnableTdcDs_DoubleSyncBasex_DoubleSyncAsyncInBasex_oSigx_Gen0_FDCEx)) + (portref rEnableTdc) + ) + ) + (net rLoadRePulseCounts (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_oDataValid_reg)) + (portref rLoadRePulseCounts) + ) + ) + (net rLoadRpCounts (joined + (portref Q (instanceref RpCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRpCounts) + ) + ) + (net rLoadRptCounts (joined + (portref Q (instanceref RptCntHs_BlkOut_oDataValid_reg)) + (portref rLoadRptCounts) + ) + ) + (net rPpsPulseCaptured (joined + (portref D (instanceref PpsCapturedDs_DoubleSyncBasex_iDlySigx_Gen0_FDCEx)) + (portref rPpsPulseCaptured) + ) + ) + (net (rename rPulserEnableDelayValTemp_0_ "rPulserEnableDelayValTemp[0]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_0_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_1_ "rPulserEnableDelayValTemp[1]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_1_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_2_ "rPulserEnableDelayValTemp[2]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_2_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayValTemp_3_ "rPulserEnableDelayValTemp[3]") (joined + (portref D (instanceref rPulserEnableDelayVal_reg_3_)) + (portref Q (instanceref PulserEnableDelayValCrossingHs_HBx_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + ) + ) + (net (rename rPulserEnableDelayVal_0_ "rPulserEnableDelayVal[0]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_0_)) + (portref (member rPulserEnableDelayVal 3)) + ) + ) + (net (rename rPulserEnableDelayVal_1_ "rPulserEnableDelayVal[1]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_1_)) + (portref (member rPulserEnableDelayVal 2)) + ) + ) + (net (rename rPulserEnableDelayVal_2_ "rPulserEnableDelayVal[2]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_2_)) + (portref (member rPulserEnableDelayVal 1)) + ) + ) + (net (rename rPulserEnableDelayVal_3_ "rPulserEnableDelayVal[3]") (joined + (portref Q (instanceref rPulserEnableDelayVal_reg_3_)) + (portref (member rPulserEnableDelayVal 0)) + ) + ) + (net (rename rRePulseHighTimeInRClks_0_ "rRePulseHighTimeInRClks[0]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 23)) + ) + ) + (net (rename rRePulseHighTimeInRClks_10_ "rRePulseHighTimeInRClks[10]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 13)) + ) + ) + (net (rename rRePulseHighTimeInRClks_11_ "rRePulseHighTimeInRClks[11]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 12)) + ) + ) + (net (rename rRePulseHighTimeInRClks_12_ "rRePulseHighTimeInRClks[12]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 11)) + ) + ) + (net (rename rRePulseHighTimeInRClks_13_ "rRePulseHighTimeInRClks[13]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 10)) + ) + ) + (net (rename rRePulseHighTimeInRClks_14_ "rRePulseHighTimeInRClks[14]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 9)) + ) + ) + (net (rename rRePulseHighTimeInRClks_15_ "rRePulseHighTimeInRClks[15]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 8)) + ) + ) + (net (rename rRePulseHighTimeInRClks_16_ "rRePulseHighTimeInRClks[16]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 7)) + ) + ) + (net (rename rRePulseHighTimeInRClks_17_ "rRePulseHighTimeInRClks[17]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 6)) + ) + ) + (net (rename rRePulseHighTimeInRClks_18_ "rRePulseHighTimeInRClks[18]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 5)) + ) + ) + (net (rename rRePulseHighTimeInRClks_19_ "rRePulseHighTimeInRClks[19]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_19__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 4)) + ) + ) + (net (rename rRePulseHighTimeInRClks_1_ "rRePulseHighTimeInRClks[1]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 22)) + ) + ) + (net (rename rRePulseHighTimeInRClks_20_ "rRePulseHighTimeInRClks[20]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_20__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 3)) + ) + ) + (net (rename rRePulseHighTimeInRClks_21_ "rRePulseHighTimeInRClks[21]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_21__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 2)) + ) + ) + (net (rename rRePulseHighTimeInRClks_22_ "rRePulseHighTimeInRClks[22]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_22__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 1)) + ) + ) + (net (rename rRePulseHighTimeInRClks_2_ "rRePulseHighTimeInRClks[2]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 21)) + ) + ) + (net (rename rRePulseHighTimeInRClks_3_ "rRePulseHighTimeInRClks[3]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 20)) + ) + ) + (net (rename rRePulseHighTimeInRClks_4_ "rRePulseHighTimeInRClks[4]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 19)) + ) + ) + (net (rename rRePulseHighTimeInRClks_5_ "rRePulseHighTimeInRClks[5]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 18)) + ) + ) + (net (rename rRePulseHighTimeInRClks_6_ "rRePulseHighTimeInRClks[6]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 17)) + ) + ) + (net (rename rRePulseHighTimeInRClks_7_ "rRePulseHighTimeInRClks[7]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 16)) + ) + ) + (net (rename rRePulseHighTimeInRClks_8_ "rRePulseHighTimeInRClks[8]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 15)) + ) + ) + (net (rename rRePulseHighTimeInRClks_9_ "rRePulseHighTimeInRClks[9]") (joined + (portref Q (instanceref RePulse2CntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member rRePulseHighTimeInRClks 14)) + ) + ) + (net (rename rRePulsePeriodInRClks_0_ "rRePulsePeriodInRClks[0]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_0__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 23)) + ) + ) + (net (rename rRePulsePeriodInRClks_10_ "rRePulsePeriodInRClks[10]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_10__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 13)) + ) + ) + (net (rename rRePulsePeriodInRClks_11_ "rRePulsePeriodInRClks[11]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_11__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 12)) + ) + ) + (net (rename rRePulsePeriodInRClks_12_ "rRePulsePeriodInRClks[12]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_12__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 11)) + ) + ) + (net (rename rRePulsePeriodInRClks_13_ "rRePulsePeriodInRClks[13]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_13__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 10)) + ) + ) + (net (rename rRePulsePeriodInRClks_14_ "rRePulsePeriodInRClks[14]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_14__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 9)) + ) + ) + (net (rename rRePulsePeriodInRClks_15_ "rRePulsePeriodInRClks[15]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 8)) + ) + ) + (net (rename rRePulsePeriodInRClks_16_ "rRePulsePeriodInRClks[16]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_16__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 7)) + ) + ) + (net (rename rRePulsePeriodInRClks_17_ "rRePulsePeriodInRClks[17]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_17__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 6)) + ) + ) + (net (rename rRePulsePeriodInRClks_18_ "rRePulsePeriodInRClks[18]") (joined + (portref Q (instanceref RePulse1CntHs_BlkOut_ODataFlop_GenFlops_18__DFlopx_Gen0_FDCEx)) + (portref (member rRePulsePeriodInRClks 5)) + ) + ) + (net (rename rRePulsePeriodInRClks_19_ "rRePulsePeriodInRClks[19]") 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(portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_15__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 0)) + ) + ) + (net (rename sSptPeriodInSClks_1_ "sSptPeriodInSClks[1]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_1__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 14)) + ) + ) + (net (rename sSptPeriodInSClks_2_ "sSptPeriodInSClks[2]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_2__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 13)) + ) + ) + (net (rename sSptPeriodInSClks_3_ "sSptPeriodInSClks[3]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_3__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 12)) + ) + ) + (net (rename sSptPeriodInSClks_4_ "sSptPeriodInSClks[4]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_4__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 11)) + ) + ) + (net (rename sSptPeriodInSClks_5_ "sSptPeriodInSClks[5]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_5__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 10)) + ) + ) + (net (rename sSptPeriodInSClks_6_ "sSptPeriodInSClks[6]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_6__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 9)) + ) + ) + (net (rename sSptPeriodInSClks_7_ "sSptPeriodInSClks[7]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_7__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 8)) + ) + ) + (net (rename sSptPeriodInSClks_8_ "sSptPeriodInSClks[8]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_8__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 7)) + ) + ) + (net (rename sSptPeriodInSClks_9_ "sSptPeriodInSClks[9]") (joined + (portref Q (instanceref SptCntHs_BlkOut_ODataFlop_GenFlops_9__DFlopx_Gen0_FDCEx)) + (portref (member sSptPeriodInSClks 6)) + ) + ) + ) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design SyncRegsIfc + (cellref SyncRegsIfc (libraryref work)) + (property part (string "xc7z100ffg900-2")) + ) +) diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf new file mode 100644 index 000000000..9679f2c63 Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd new file mode 100644 index 000000000..6535bbd04 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcTop.vhd @@ -0,0 +1,1147 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- This top level module orchestrates both of the TDC Cores for the RP and SP. It +-- handles PPS capture, resets, re-run logic, and PPS crossing logic. The guts of the TDC +-- are all located in the Cores. +-- +-- This file (and the Cores) follows exactly the "TDC Detail" diagram from this document: +-- //MI/RF/HW/USRP/N310/HWCode/Common/Synchronization/design/Diagrams.vsdx +-- +-- +-- +-- To control this module: +-- 0) Default values expected to be driven on the control inputs: +-- aReset <= true +-- rResetTdc <= true +-- rEnableTdc <= false +-- rReRunEnable <= false +-- rEnablePpsCrossing <= false +-- sPpsClkCrossDelayVal <= don't care +-- Prior to starting the core, the Sync Pulse counters must be loaded. Apply the +-- correct count values to rRpPeriodInRClks, etc, and then pulse the load bit for +-- each RP and SP. It is critical that this step is performed before de-asserting +-- reset. +-- +-- 1) De-assert the global reset, aReset, as well as the synchronous reset, rResetTdc, +-- after all clocks are active and stable. Wait until rResetTdcDone is de-asserted. +-- If it doesn't de-assert, then one of your clocks isn't running. +-- +-- 2) At any point after rResetTdcDone de-asserts it is safe to assert rEnableTdc. +-- The rPpsPulse input is now actively listening for PPS activity and the TDC +-- will begin on the first PPS pulse received. After a PPS is received, the +-- rPpsPulseCaptured bit will assert and will remain asserted until aReset or +-- rResetTdc is asserted. +-- +-- 3) When the TDC measurement completes, mRpOffsetDone and mSpOffsetDone will assert +-- (not necessarily at the same time). The results of the measurements will be valid +-- on mRpOffset and mSpOffset. +-- +-- 4) To cross the PPS trigger into the SampleClk domain, first write the correct delay +-- value to sPpsClkCrossDelayVal. Then (or at the same time), enable the crossing +-- logic by asserting rEnablePpsCrossing. All subsequent PPS pulses will be crossed +-- deterministically. Although not the typical use case, sPpsClkCrossDelayVal can +-- be adjusted on the fly without producing output glitches, although output pulses +-- may be skipped. +-- +-- 5) To run the measurement again, assert the rReRunEnable input and capture the new +-- offsets whenever mRpOffsetValid or mSpOffsetValid asserts. +-- +-- +-- +-- Sync Pulse = RP and SP, which are the repeated pulses that are some integer +-- divisor of the Reference and Sample clocks. RP = Reference Pulse in the +-- RefClk domain. SP = Repeated TClk pulse in the SampleClk domain. +-- +-- +-- Clock period relationship requirements to meet system concerns: +-- 1) MeasClkPeriod < 2*RefClkPeriod +-- 2) MeasClkPeriod < 4*SampleClkPeriod +-- +-- +-- vreview_group Tdc +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity TdcTop is + generic ( + -- Determines the maximum number of bits required to create the restart + -- pulser. This value is based off of the RefClk and RePulse rates. + kRClksPerRePulsePeriodBitsMax : integer range 3 to 32 := 24; + -- Determines the maximum number of bits required to create the Gated and Freerunning + -- sync pulsers. This value is based off of the RefClk and SyncPulse rates. + kRClksPerRpPeriodBitsMax : integer range 3 to 16 := 16; + -- This value is based off of the SampleClk and SyncPulse rates. + kSClksPerSpPeriodBitsMax : integer range 3 to 16 := 16; + -- Number of MeasClk periods required to count one period of RP or SP (in bits). + kPulsePeriodCntSize : integer := 13; + -- Number of FreqRef periods to be measured (in bits). + kFreqRefPeriodsToCheckSize: integer := 17; + -- Number of Sync Pulse Periods to be timestamped (in bits). + kSyncPeriodsToStampSize : integer := 10 + ); + port ( + + -- Clocks and Resets : -------------------------------------------------------------- + -- Asynchronous global reset. + aReset : in boolean; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math/luck. + MeasClk : in std_logic; + + + -- Controls and Status : ------------------------------------------------------------ + -- Soft reset for the module. Wait until rResetTdcDone asserts before de-asserting + -- the reset. + rResetTdc : in boolean; + rResetTdcDone : out boolean; + -- Once enabled, the TDC waits for the next PPS pulse to begin measurements. Leave + -- this signal asserted for the measurement duration (there is no need to de-assert + -- it unless you want to capture a different PPS edge). + rEnableTdc : in boolean; + -- Assert this bit to allow the TDC to perform repeated measurements. + rReRunEnable : in boolean; + + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in boolean; + -- Debug, held asserted when pulse is captured. + rPpsPulseCaptured : out boolean; + + -- Programmable value for delaying the RP and SP pulsers from when the Restart + -- Pulser begins. + rPulserEnableDelayVal : in unsigned(3 downto 0); + + + -- Crossing PPS into Sample Clock : ------------------------------------------------- + -- Enable crossing rPpsPulse into SampleClk domain. This should remain de-asserted + -- until the TDC measurements are complete and sPpsClkCrossDelayVal is written. + rEnablePpsCrossing : in boolean; + -- Programmable delay value for crossing clock domains. This is used to compensate + -- for differences in sSP pulses across modules. This value is typically set once + -- after running initial synchronization. + sPpsClkCrossDelayVal : in unsigned(3 downto 0); + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out boolean; + + + -- FTDC Measurement Results : ------------------------------------------------------- + -- Final FTDC measurements in MeasClk ticks. Done will assert when *Offset + -- becomes valid and will remain asserted until aReset or rResetTdc asserts. + -- FXP<+40,13> where kPulsePeriodCntSize is the number of integer bits. + mRpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mSpOffset : out unsigned(kPulsePeriodCntSize+ + kSyncPeriodsToStampSize+ + kFreqRefPeriodsToCheckSize-1 downto 0); + mOffsetsDone : out boolean; + mOffsetsValid : out boolean; + + + -- Setup for Pulsers : -------------------------------------------------------------- + -- Only load these counts when rResetTdc is asserted and rEnableTdc is de-asserted!!! + -- If both of the above conditions are met, load the counts by pulsing Load + -- when the counts are valid. It is not necessary to keep the count values valid + -- after pulsing Load. + rLoadRePulseCounts : in boolean; -- RePulse + rRePulsePeriodInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rRePulseHighTimeInRClks : in unsigned(kRClksPerRePulsePeriodBitsMax - 1 downto 0); + rLoadRpCounts : in boolean; -- RP + rRpPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRpHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rLoadRptCounts : in boolean; -- RP-transfer + rRptPeriodInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + rRptHighTimeInRClks : in unsigned(kRClksPerRpPeriodBitsMax - 1 downto 0); + sLoadSpCounts : in boolean; -- SP + sSpPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSpHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sLoadSptCounts : in boolean; -- SP-transfer + sSptPeriodInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + sSptHighTimeInSClks : in unsigned(kSClksPerSpPeriodBitsMax - 1 downto 0); + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + -- The rising edges will always have a fixed (but unknown) phase relationship to one + -- another. This fixed phase relationship is valid across daughterboards and all + -- modules using the same Reference Clock and Sample Clock rates and sources. + rRpTransfer : out boolean; + sSpTransfer : out boolean; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcTop; + + +architecture struct of TdcTop is + + component TdcCore + generic ( + kSourceClksPerPulseMaxBits : integer range 3 to 16 := 16; + kPulsePeriodCntSize : integer := 13; + kFreqRefPeriodsToCheckSize : integer := 17; + kSyncPeriodsToStampSize : integer := 10); + port ( + aReset : in boolean; + MeasClk : in std_logic; + mResetPeriodMeas : in boolean; + mPeriodMeasDone : out boolean; + mResetTdcMeas : in boolean; + mRunTdcMeas : in boolean; + mGatedPulse : out boolean; + mAvgOffset : out unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + mAvgOffsetDone : out boolean; + mAvgOffsetValid : out boolean; + SourceClk : in std_logic; + sResetTdc : in boolean; + sSyncPulseLoadCnt : in boolean; + sSyncPulsePeriod : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseHighTime : in unsigned(kSourceClksPerPulseMaxBits-1 downto 0); + sSyncPulseEnable : in boolean; + sGatedPulse : out boolean; + sGatedPulseToPin : inout std_logic); + end component; + + --vhook_sigstart + signal mRP: boolean; + signal mRpOffsetDoneLcl: boolean; + signal mRpOffsetValidLcl: boolean; + signal mRunTdc: boolean; + signal mSP: boolean; + signal mSpOffsetDoneLcl: boolean; + signal mSpOffsetValidLcl: boolean; + signal rCrossTrigRFI: boolean; + signal rGatedCptrPulseIn: boolean; + signal rRePulse: boolean; + signal rRePulseEnable: boolean; + signal rRpEnable: boolean; + signal rRptPulse: boolean; + signal sSpEnable: boolean; + signal sSptPulse: boolean; + --vhook_sigend + + signal sSpEnable_ms : boolean; + + -- Delay chain for enables. + constant kDelaySizeForRpEnable : integer := 15; + constant kAddtlDelayForSpEnable : integer := 3; + signal rSyncPulseEnableDly : + std_logic_vector(kDelaySizeForRpEnable+ + kAddtlDelayForSpEnable-1 downto 0) := (others => '0'); + -- Adding kAddtlDelayForSpEnable stages, so this vector needs to handle one extra + -- bit of range (hence no -1 downto 0). + signal rSyncPulseEnableDlyVal : unsigned(rPulserEnableDelayVal'length downto 0); + + signal rResetTdcFlop_ms, rResetTdcFlop, + rResetTdcDone_ms, + rSpEnable, + mRunTdcEnable_ms, mRunTdcEnable, + mRunTdcEnableDly, mRunTdcEnableRe, + mResetTdc_ms, mResetTdc, + sResetTdc_ms, sResetTdc, + mRpValidStored, mSpValidStored, + mOffsetsValidLcl, + rPpsPulseDly, rPpsPulseRe, + mReRunEnable_ms, mReRunEnable : boolean; + + signal rPpsCaptured : std_logic; + + type EnableFsmState_t is (Disabled, WaitForRunComplete, ReRuns); + signal mEnableState : EnableFsmState_t; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sSpEnable_ms : signal is "true"; + attribute ASYNC_REG of sSpEnable : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcFlop : signal is "true"; + attribute ASYNC_REG of rResetTdcDone_ms : signal is "true"; + attribute ASYNC_REG of rResetTdcDone : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable_ms : signal is "true"; + attribute ASYNC_REG of mRunTdcEnable : signal is "true"; + attribute ASYNC_REG of mResetTdc_ms : signal is "true"; + attribute ASYNC_REG of mResetTdc : signal is "true"; + attribute ASYNC_REG of sResetTdc_ms : signal is "true"; + attribute ASYNC_REG of sResetTdc : signal is "true"; + attribute ASYNC_REG of mReRunEnable_ms : signal is "true"; + attribute ASYNC_REG of mReRunEnable : signal is "true"; + +begin + + + -- Generate Resets : ------------------------------------------------------------------ + -- Double-sync the reset to the MeasClk domain and then back to the RefClk domain to + -- prove it made it all the way into the TDC. Also move it into the SampleClk domain. + -- ------------------------------------------------------------------------------------ + GenResets : process(aReset, RefClk) + begin + if aReset then + rResetTdcFlop_ms <= true; + rResetTdcFlop <= true; + rResetTdcDone_ms <= true; + rResetTdcDone <= true; + elsif rising_edge(RefClk) then + -- Run this through a double-sync in case the user defaults it to false, which + -- could cause rResetTdcFlop_ms to go meta-stable. + rResetTdcFlop_ms <= rResetTdc; + rResetTdcFlop <= rResetTdcFlop_ms; + -- Second double-sync to move the reset from the MeasClk domain back to RefClk. + rResetTdcDone_ms <= mResetTdc; + rResetTdcDone <= rResetTdcDone_ms; + end if; + end process; + + GenResetsMeasClk : process(aReset, MeasClk) + begin + if aReset then + mResetTdc_ms <= true; + mResetTdc <= true; + elsif rising_edge(MeasClk) then + -- Move the reset from the RefClk to the MeasClk domain. + mResetTdc_ms <= rResetTdcFlop; + mResetTdc <= mResetTdc_ms; + end if; + end process; + + GenResetsSampleClk : process(aReset, SampleClk) + begin + if aReset then + sResetTdc_ms <= true; + sResetTdc <= true; + elsif rising_edge(SampleClk) then + -- Move the reset from the RefClk to the SampleClk domain. + sResetTdc_ms <= rResetTdcFlop; + sResetTdc <= sResetTdc_ms; + end if; + end process; + + + -- Generate Enables for TDCs : -------------------------------------------------------- + -- When the TDC is enabled by asserting rEnableTdc, we start "listening" for a PPS + -- rising edge to occur. We capture the first edge we see and then keep the all the + -- enables asserted until the TDC is disabled. + -- ------------------------------------------------------------------------------------ + rPpsPulseRe <= rPpsPulse and not rPpsPulseDly; + + EnableTdc : process(aReset, RefClk) + begin + if aReset then + rPpsPulseDly <= false; + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + elsif rising_edge(RefClk) then + -- RE detector for PPS to ONLY trigger on the edge and not accidentally half + -- way through the high time. + rPpsPulseDly <= rPpsPulse; + -- When the TDC is enabled we capture the first PPS. This starts the Sync Pulses + -- (RP / SP) as well as enables the TDC measurement for capturing edges. Note + -- that this is independent from any synchronous reset such that we can control + -- the PPS capture and the edge capture independently. + if rEnableTdc then + if rPpsPulseRe then + rPpsCaptured <= '1'; + end if; + else + rPpsCaptured <= '0'; + rSyncPulseEnableDly <= (others => '0'); + end if; + + -- Delay chain for the enable bits. Shift left low to high. + rSyncPulseEnableDly <= + rSyncPulseEnableDly(rSyncPulseEnableDly'high-1 downto 0) & rPpsCaptured; + end if; + end process; + + rSyncPulseEnableDlyVal <= resize(rPulserEnableDelayVal, rSyncPulseEnableDlyVal'length); + + -- Enables for the RePulse/RP/SP. The RePulse enable must be asserted two cycles + -- before the other enables to allow the TDC to start running before the RP/SP begin. + rRePulseEnable <= rPpsCaptured = '1'; -- no delay + rRpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)) = '1'; + rSpEnable <= rSyncPulseEnableDly(to_integer(rSyncPulseEnableDlyVal)+kAddtlDelayForSpEnable-1) = '1'; + + -- Local to output. + rPpsPulseCaptured <= rPpsCaptured = '1'; + + -- Sync rSpEnable to the SampleClk now... based on the "TDC 2.0" diagram. + SyncEnableToSampleClk : process(aReset, SampleClk) + begin + if aReset then + sSpEnable_ms <= false; + sSpEnable <= false; + elsif rising_edge(SampleClk) then + sSpEnable_ms <= rSpEnable; + sSpEnable <= sSpEnable_ms; + end if; + end process; + + --vhook_e Pulser ReRunPulser + --vhook_a kClksPerPulseMaxBits kRClksPerRePulsePeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRePulseCounts + --vhook_a cPeriod rRePulsePeriodInRClks + --vhook_a cHighTime rRePulseHighTimeInRClks + --vhook_a cEnablePulse rRePulseEnable + --vhook_a cPulse rRePulse + ReRunPulser: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRePulsePeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRePulseCounts, --in boolean + cPeriod => rRePulsePeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRePulseHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRePulseEnable, --in boolean + cPulse => rRePulse); --out boolean + + mRunTdcEnableRe <= mRunTdcEnable and not mRunTdcEnableDly; + + -- FSM to generate the master Run signal, as well as the repeat run. + SyncEnableToMeasClk : process(aReset, MeasClk) + begin + if aReset then + mRunTdcEnable_ms <= false; + mRunTdcEnable <= false; + mReRunEnable_ms <= false; + mReRunEnable <= false; + mRunTdcEnableDly <= false; + mRunTdc <= false; + mEnableState <= Disabled; + elsif rising_edge(MeasClk) then + -- rRePulse is many, many MeasClk cycles high/low, so this is safe to double-sync. + mRunTdcEnable_ms <= rRePulse; + mRunTdcEnable <= mRunTdcEnable_ms; + mReRunEnable_ms <= rReRunEnable; + mReRunEnable <= mReRunEnable_ms; + + mRunTdcEnableDly <= mRunTdcEnable; + + -- STATE MACHINE STARTUP !!! ------------------------------------------------------ + -- This state machine starts safely because it cannot change state until + -- mRunTdcEnable is asserted, which cannot happen until several cycles after + -- aReset de-assertion due to the double-synchronizer from the RefClk domain. + -- -------------------------------------------------------------------------------- + -- De-assert strobe. + mRunTdc <= false; + + case mEnableState is + -- Transition to WaitForRunComplete when the TDC is enabled. Pulse mRunTdc here, + -- and then wait for it to complete in WaitForRunComplete. + when Disabled => + if mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + -- The TDC measurement is complete when both offsets are valid. Go to the re-run + -- state regardless of whether re-runs are enabled. If they aren't we just sit + -- there and wait for more instructions... + when WaitForRunComplete => + if mOffsetsValidLcl then + mEnableState <= ReRuns; + end if; + + -- Only pulse mRunTdc again if re-runs are enabled and the rising edge of + -- the enable signal occurs. This guarantees our RP/SP have the correct phase + -- relationship every time the TDC is run. + when ReRuns => + if mReRunEnable and mRunTdcEnableRe then + mRunTdc <= true; + mEnableState <= WaitForRunComplete; + end if; + + when others => + mEnableState <= Disabled; + end case; + + -- Synchronous reset for FSM. + if mResetTdc then + mEnableState <= Disabled; + mRunTdc <= false; + end if; + + end if; + end process; + + + + -- Generate Output Valid Signals : ---------------------------------------------------- + -- Depending on how fast SW can read the measurements (and in what order they read) + -- the readings could be out of sync with one another. This section conditions the + -- output valid signals from each core and asserts a single output valid pulse after + -- BOTH valids have asserted. It is agnostic to the order in which the valids assert. + -- It creates a delay in the output valid assertion. Minimal delay is one MeasClk cycle + -- if the core valids assert together. Worst-case delay is two MeasClk cycles after + -- the latter of the two valids asserts. This is acceptable delay because the core + -- cannot be re-run until both valids have asserted (mOffsetsValidLcl is fed back into + -- the ReRun FSM above). + -- ------------------------------------------------------------------------------------ + ConditionDataValidProc : process(aReset, MeasClk) is + begin + if aReset then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + elsif rising_edge(MeasClk) then + -- Reset the strobe signals. + mOffsetsValidLcl <= false; + + -- First, we're sensitive to the TDC sync reset signal. + if mResetTdc then + mOffsetsValidLcl <= false; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 1: Both Valid signals pulse at the same time. + -- Case 4: Both Valid signals have been stored independently. Yes, this incurs + -- a one-cycle delay in the output valid (from when the second one asserts) + -- but it makes for cleaner code and is safe because by design because the + -- valid signals cannot assert again for a longggg time. + elsif (mRpOffsetValidLcl and mSpOffsetValidLcl) or + (mRpValidStored and mSpValidStored) then + mOffsetsValidLcl <= true; + mRpValidStored <= false; + mSpValidStored <= false; + -- Case 2: RP Valid pulses alone. + elsif mRpOffsetValidLcl then + mRpValidStored <= true; + -- Case 3: SP Valid pulses alone. + elsif mSpOffsetValidLcl then + mSpValidStored <= true; + end if; + end if; + end process; + + -- Local to output. + mOffsetsValid <= mOffsetsValidLcl; + -- Only assert done with both cores are done. + mOffsetsDone <= mRpOffsetDoneLcl and mSpOffsetDoneLcl; + + + + -- Reference Clock TDC (RP) : --------------------------------------------------------- + -- mRP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mRP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore RpTdc + --vhook_g kSourceClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mRP + --vhook_a mAvgOffset mRpOffset + --vhook_a mAvgOffsetDone mRpOffsetDoneLcl + --vhook_a mAvgOffsetValid mRpOffsetValidLcl + --vhook_a SourceClk RefClk + --vhook_a sResetTdc rResetTdcFlop + --vhook_a sSyncPulseLoadCnt rLoadRpCounts + --vhook_a sSyncPulsePeriod rRpPeriodInRClks + --vhook_a sSyncPulseHighTime rRpHighTimeInRClks + --vhook_a sSyncPulseEnable rRpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} rGated$1 + RpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mRP, --out boolean + mAvgOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mRpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mRpOffsetValidLcl, --out boolean + SourceClk => RefClk, --in std_logic + sResetTdc => rResetTdcFlop, --in boolean + sSyncPulseLoadCnt => rLoadRpCounts, --in boolean + sSyncPulsePeriod => rRpPeriodInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => rRpHighTimeInRClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => rRpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => rGatedPulseToPin); --inout std_logic + + --vhook_e Pulser RpTransferPulse + --vhook_a kClksPerPulseMaxBits kRClksPerRpPeriodBitsMax + --vhook_a Clk RefClk + --vhook_a cLoadLimits rLoadRptCounts + --vhook_a cPeriod rRptPeriodInRClks + --vhook_a cHighTime rRptHighTimeInRClks + --vhook_a cEnablePulse rRpEnable + --vhook_a cPulse rRptPulse + RpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kRClksPerRpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => RefClk, --in std_logic + cLoadLimits => rLoadRptCounts, --in boolean + cPeriod => rRptPeriodInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => rRptHighTimeInRClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => rRpEnable, --in boolean + cPulse => rRptPulse); --out boolean + + -- Local to output + rRpTransfer <= rRptPulse; + + + -- Sample Clock TDC (SP) : ------------------------------------------------------------ + -- mSP is only used for testbenching purposes, so ignore vhook warnings. + --vhook_nowarn mSP + -- ------------------------------------------------------------------------------------ + + --vhook TdcCore SpTdc + --vhook_g kSourceClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a mResetPeriodMeas mResetTdc + --vhook_a mResetTdcMeas mResetTdc + --vhook_a mPeriodMeasDone open + --vhook_a mRunTdcMeas mRunTdc + --vhook_a mGatedPulse mSP + --vhook_a mAvgOffset mSpOffset + --vhook_a mAvgOffsetDone mSpOffsetDoneLcl + --vhook_a mAvgOffsetValid mSpOffsetValidLcl + --vhook_a SourceClk SampleClk + --vhook_a sResetTdc sResetTdc + --vhook_a sSyncPulseLoadCnt sLoadSpCounts + --vhook_a sSyncPulsePeriod sSpPeriodInSClks + --vhook_a sSyncPulseHighTime sSpHighTimeInSClks + --vhook_a sSyncPulseEnable sSpEnable + --vhook_a sGatedPulse open + --vhook_a {^sGated(.*)} sGated$1 + SpTdc: TdcCore + generic map ( + kSourceClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + MeasClk => MeasClk, --in std_logic + mResetPeriodMeas => mResetTdc, --in boolean + mPeriodMeasDone => open, --out boolean + mResetTdcMeas => mResetTdc, --in boolean + mRunTdcMeas => mRunTdc, --in boolean + mGatedPulse => mSP, --out boolean + mAvgOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mAvgOffsetDone => mSpOffsetDoneLcl, --out boolean + mAvgOffsetValid => mSpOffsetValidLcl, --out boolean + SourceClk => SampleClk, --in std_logic + sResetTdc => sResetTdc, --in boolean + sSyncPulseLoadCnt => sLoadSpCounts, --in boolean + sSyncPulsePeriod => sSpPeriodInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseHighTime => sSpHighTimeInSClks, --in unsigned(kSourceClksPerPulseMaxBits-1:0) + sSyncPulseEnable => sSpEnable, --in boolean + sGatedPulse => open, --out boolean + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + --vhook_e Pulser SpTransferPulse + --vhook_a kClksPerPulseMaxBits kSClksPerSpPeriodBitsMax + --vhook_a Clk SampleClk + --vhook_a cLoadLimits sLoadSptCounts + --vhook_a cPeriod sSptPeriodInSClks + --vhook_a cHighTime sSptHighTimeInSClks + --vhook_a cEnablePulse sSpEnable + --vhook_a cPulse sSptPulse + SpTransferPulse: entity work.Pulser (rtl) + generic map (kClksPerPulseMaxBits => kSClksPerSpPeriodBitsMax) --integer range 3:32 :=16 + port map ( + aReset => aReset, --in boolean + Clk => SampleClk, --in std_logic + cLoadLimits => sLoadSptCounts, --in boolean + cPeriod => sSptPeriodInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cHighTime => sSptHighTimeInSClks, --in unsigned(kClksPerPulseMaxBits-1:0) + cEnablePulse => sSpEnable, --in boolean + cPulse => sSptPulse); --out boolean + + -- Local to output + sSpTransfer <= sSptPulse; + + + -- Cross PPS to SampleClk : ---------------------------------------------------------- + -- Cross it safely and with deterministic delay. + -- ------------------------------------------------------------------------------------ + + -- Keep the module from over-pulsing itself by gating the input with the RFI signal, + -- although at 1 Hz, this module should never run into the RFI de-asserted case + -- by design. + rGatedCptrPulseIn <= rCrossTrigRFI and rPpsPulseRe; + + --vhook_e CrossTrigger CrossCptrPulse + --vhook_a rRP rRptPulse + --vhook_a rReadyForInput rCrossTrigRFI + --vhook_a rEnableTrigger rEnablePpsCrossing + --vhook_a rTriggerIn rGatedCptrPulseIn + --vhook_a sSP sSptPulse + --vhook_a sElasticBufferPtr sPpsClkCrossDelayVal + --vhook_a sTriggerOut sPpsPulse + CrossCptrPulse: entity work.CrossTrigger (rtl) + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + rRP => rRptPulse, --in boolean + rReadyForInput => rCrossTrigRFI, --out boolean + rEnableTrigger => rEnablePpsCrossing, --in boolean + rTriggerIn => rGatedCptrPulseIn, --in boolean + SampleClk => SampleClk, --in std_logic + sSP => sSptPulse, --in boolean + sElasticBufferPtr => sPpsClkCrossDelayVal, --in unsigned(3:0) + sTriggerOut => sPpsPulse); --out boolean + + +end struct; + + + + + + + +-------------------------------------------------------------------------------- +-- Testbench for TdcTop +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity tb_TdcTop is end tb_TdcTop; + +architecture test of tb_TdcTop is + + -- Constants for the clock periods. + constant kSPer : time := 8.000 ns; -- 125.00 MHz + constant kMPer : time := 5.050 ns; -- 198.00 MHz + constant kRPer : time := 100.000 ns; -- 10.00 MHz + + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + + -- Constants for the RP/SP pulses, based on the clock frequencies above. The periods + -- should all divide into one another without remainders, so this is safe to do... + -- High time is 50% duty cycle, or close to it if the period isn't a round number. + constant kRpPeriod : time := 1000 ns; + constant kRpPeriodInRClks : integer := kRpPeriod/kRPer; + constant kRpHighTimeInRClks : integer := integer(floor(real(kRpPeriodInRClks)/2.0)); + constant kRptPeriod : time := 25000 ns; + constant kRptPeriodInRClks : integer := kRptPeriod/kRPer; + constant kRptHighTimeInRClks : integer := integer(floor(real(kRptPeriodInRClks)/2.0)); + constant kSpPeriod : time := 800 ns; + constant kSpPeriodInSClks : integer := kSpPeriod/kSPer; + constant kSpHighTimeInSClks : integer := integer(floor(real(kSpPeriodInSClks)/2.0)); + constant kSptPeriod : time := 25000 ns; + constant kSptPeriodInSClks : integer := kSptPeriod/kSPer; + constant kSptHighTimeInSClks : integer := integer(floor(real(kSptPeriodInSClks)/2.0)); + constant kRePulsePeriod : time := 2.500 ms; + constant kRePulsePeriodInRClks : integer := kRePulsePeriod/kRPer; + constant kRePulseHighTimeInRClks : integer := integer(floor(real(kRePulsePeriodInRClks)/2.0)); + + -- This doesn't come out to a nice number (or shouldn't), but that's ok. Round up. + constant kMeasClksPerRp : integer := kRpPeriod/kMPer+1; + + -- Inputs to DUT + constant kPulsePeriodCntSize : integer := integer(ceil(log2(real(kMeasClksPerRp)))); + constant kFreqRefPeriodsToCheckSize: integer := 12; -- usually 17, but to save run time... + constant kSyncPeriodsToStampSize : integer := 10; + + constant kMeasurementTimeout : time := + kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + + 40*(2**kSyncPeriodsToStampSize) + + kMeasClksPerRp*(2**kFreqRefPeriodsToCheckSize) + ); + + --vhook_sigstart + signal aReset: boolean; + signal MeasClk: std_logic := '0'; + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal RefClk: std_logic := '0'; + signal rEnablePpsCrossing: boolean; + signal rEnableTdc: boolean; + signal rGatedPulseToPin: std_logic; + signal rLoadRePulseCounts: boolean; + signal rLoadRpCounts: boolean; + signal rLoadRptCounts: boolean; + signal rPpsPulse: boolean; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: unsigned(3 downto 0); + signal rReRunEnable: boolean; + signal rResetTdc: boolean; + signal rResetTdcDone: boolean; + signal rRpTransfer: boolean; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sLoadSpCounts: boolean; + signal sLoadSptCounts: boolean; + signal sPpsClkCrossDelayVal: unsigned(3 downto 0); + signal sPpsPulse: boolean; + signal sSpTransfer: boolean; + --vhook_sigend + + signal StopSim : boolean; + signal EnableOutputChecks : boolean := true; + + signal ExpectedRpOutput, + ExpectedFinalMeas, + ExpectedSpOutput : real := 0.0; + + alias mRunTdc is <>; + alias mSP is <>; + alias mRP is <>; + + procedure ClkWait( + signal Clk : in std_logic; + X : positive := 1) is + begin + for i in 1 to X loop + wait until rising_edge(Clk); + end loop; + end procedure ClkWait; + + function OffsetToReal (Offset : unsigned) return real is + variable TempVar : real := 0.0; + begin + TempVar := + real(to_integer( + Offset(Offset'high downto kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))) + + real(to_integer( + Offset(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize-1 downto 0)))* + real(2.0**(-(kFreqRefPeriodsToCheckSize+kSyncPeriodsToStampSize))); + return TempVar; + end OffsetToReal; + +begin + + SampleClk <= not SampleClk after kSPer/2 when not StopSim else '0'; + RefClk <= not RefClk after kRPer/2 when not StopSim else '0'; + MeasClk <= not MeasClk after kMPer/2 when not StopSim else '0'; + + + main: process + begin + -- Defaults, per instructions in Purpose + sPpsClkCrossDelayVal <= to_unsigned(0, sPpsClkCrossDelayVal'length); + rPulserEnableDelayVal <= to_unsigned(1, rPulserEnableDelayVal'length); + rResetTdc <= true; + rEnableTdc <= false; + rReRunEnable <= false; + rEnablePpsCrossing <= false; + rPpsPulse <= false; + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + aReset <= true, false after kRPer*4; + ClkWait(RefClk,10); + + -- Step 0 : ------------------------------------------------------------------------- + -- Prior to de-asserting reset, we need to load the counters, so pulse the loads. + ClkWait(RefClk); + rLoadRePulseCounts <= true; + rLoadRpCounts <= true; + rLoadRptCounts <= true; + ClkWait(RefClk); + rLoadRePulseCounts <= false; + rLoadRpCounts <= false; + rLoadRptCounts <= false; + ClkWait(SampleClk); + sLoadSpCounts <= true; + sLoadSptCounts <= true; + ClkWait(SampleClk); + sLoadSpCounts <= false; + sLoadSptCounts <= false; + + + -- Step 1 : ------------------------------------------------------------------------- + report "De-asserting Synchronous Reset..." severity note; + ClkWait(RefClk); + rResetTdc <= false; + wait until not rResetTdcDone for (kRPer*4)+(kMPer*2); + assert not rResetTdcDone + report "rRestTdcDone didn't de-assert in time" + severity error; + + + -- Step 2 : ------------------------------------------------------------------------- + report "Enabling TDC Measurement & Capturing PPS..." severity note; + rEnableTdc <= true; + ClkWait(RefClk,5); + + -- Trigger a PPS one-cycle pulse. + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + assert rPpsPulseCaptured report "PPS not captured" severity error; + + + -- Step 3 : ------------------------------------------------------------------------- + report "Waiting for Measurements to Complete..." severity note; + wait until mOffsetsDone for kMeasurementTimeout; + assert mOffsetsDone + report "Offset measurements not completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + + -- Step 4 : ------------------------------------------------------------------------- + -- Trigger another PPS one-cycle pulse to watch it all cross over correctly. + -- Issue the trigger around where a real PPS pulse will come (RE of RP). + -- First, set the programmable delay sPpsClkCrossDelayVal. + ClkWait(SampleClk); + sPpsClkCrossDelayVal <= to_unsigned(4, sPpsClkCrossDelayVal'length); + ClkWait(RefClk); + rEnablePpsCrossing <= true; + wait until rRpTransfer and not rRpTransfer'delayed; + rPpsPulse <= true; + ClkWait(RefClk); + rPpsPulse <= false; + ClkWait(RefClk); + + -- We expect the PPS output pulse to arrive after FE and RE of sSP have passed, + -- and then a few extra cycles of SampleClk delay on there as well. + wait until (not sSpTransfer) and ( sSpTransfer'delayed); -- FE + wait until ( sSpTransfer) and (not sSpTransfer'delayed); -- RE + ClkWait(SampleClk, 2 + to_integer(sPpsClkCrossDelayVal)); + -- Check on falling edge of clock. + wait until falling_edge(SampleClk); + assert sPpsPulse and not sPpsPulse'delayed(kSPer) report "sPpsPulse did not assert"; + wait until falling_edge(SampleClk); + assert not sPpsPulse report "sPpsPulse did not pulse correctly"; + + + -- Step 5 : ------------------------------------------------------------------------- + report "Repeating TDC Measurement..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + + -- Now wait for the measurement to complete. + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + + -- Offset values checked below in CheckOutput. + + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + + ClkWait(MeasClk,100); + + + -- Let it run for a while : --------------------------------------------------------- + for i in 0 to 9 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + -- And stop it : -------------------------------------------------------------------- + report "Stopping Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= false; + -- Wait to make sure it doesn't keep going. + wait until mOffsetsValid + for 2*(kMPer*(kMeasClksPerRp*(2**kSyncPeriodsToStampSize) + 40*(2**kSyncPeriodsToStampSize))); + assert not mOffsetsValid; + + + + -- Let it run for a while : --------------------------------------------------------- + report "Starting again Repeating TDC Measurements..." severity note; + ClkWait(RefClk); + rReRunEnable <= true; + for i in 0 to 2 loop + wait until mOffsetsValid for kMeasurementTimeout; + assert mOffsetsValid + report "Offset measurements not re-completed within timeout" + severity error; + report "Printing Results..." & LF & + "RP: " & real'image(OffsetToReal(mRpOffset)) & + " Expected: " & real'image(ExpectedRpOutput) & LF & + "SP: " & real'image(OffsetToReal(mSpOffset)) & + " Expected: " & real'image(ExpectedSpOutput) & LF & + "Meas: " & real'image((OffsetToReal(mSpOffset-mRpOffset)*real(kMPer/1 ns)+ + real(kRPer/1 ns)-real(kSPer/1 ns))/real(kSPer/1 ns)) & + " Expected: " & real'image(ExpectedFinalMeas) + severity note; + end loop; + + + StopSim <= true; + wait; + end process; + + + ExpectedFinalMeasGen : process + variable StartTime : time := 0 ns; + begin + wait until rPpsPulse; + wait until rRpTransfer; + StartTime := now; + wait until sSpTransfer; + ExpectedFinalMeas <= real((now - StartTime)/1 ps)/real((kSPer/1 ps)); + wait until rResetTdc; + end process; + + + ExpectedRpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mRP; + ExpectedRpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + ExpectedSpOutputGen : process + variable StartTime : time := 0 ns; + begin + wait until mRunTdc; + StartTime := now; + wait until mSP; + ExpectedSpOutput <= real((now - StartTime)/1 ps)/real((kMPer/1 ps)); + wait until mOffsetsValid; + end process; + + CheckOutput : process(MeasClk) + begin + if falling_edge(MeasClk) then + if EnableOutputChecks then + + if mOffsetsValid then + assert (OffsetToReal(mRpOffset) < ExpectedRpOutput + 1.0) and + (OffsetToReal(mRpOffset) > ExpectedRpOutput - 1.0) + report "Mismatch between mRpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mRpOffset)) & LF & + "Expect: " & real'image(ExpectedRpOutput) + severity error; + assert (OffsetToReal(mSpOffset) < ExpectedSpOutput + 1.0) and + (OffsetToReal(mSpOffset) > ExpectedSpOutput - 1.0) + report "Mismatch between mSpOffset and expected!" & LF & + "Actual: " & real'image(OffsetToReal(mSpOffset)) & LF & + "Expect: " & real'image(ExpectedSpOutput) + severity error; + end if; + end if; + end if; + end process; + + + --vhook_e TdcTop dutx + --vhook_a rRpPeriodInRClks to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRpHighTimeInRClks to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSpPeriodInSClks to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSpHighTimeInSClks to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRptPeriodInRClks to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a rRptHighTimeInRClks to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax) + --vhook_a sSptPeriodInSClks to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a sSptHighTimeInSClks to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax) + --vhook_a rRePulsePeriodInRClks to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax) + --vhook_a rRePulseHighTimeInRClks to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax) + dutx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => aReset, --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => rResetTdc, --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => rEnableTdc, --in boolean + rReRunEnable => rReRunEnable, --in boolean + rPpsPulse => rPpsPulse, --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => rPulserEnableDelayVal, --in unsigned(3:0) + rEnablePpsCrossing => rEnablePpsCrossing, --in boolean + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --in unsigned(3:0) + sPpsPulse => sPpsPulse, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => rLoadRePulseCounts, --in boolean + rRePulsePeriodInRClks => to_unsigned(kRePulsePeriodInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => to_unsigned(kRePulseHighTimeInRClks, kRClksPerRePulsePeriodBitsMax), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => rLoadRpCounts, --in boolean + rRpPeriodInRClks => to_unsigned(kRpPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => to_unsigned(kRpHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => rLoadRptCounts, --in boolean + rRptPeriodInRClks => to_unsigned(kRptPeriodInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => to_unsigned(kRptHighTimeInRClks, kRClksPerRpPeriodBitsMax), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => sLoadSpCounts, --in boolean + sSpPeriodInSClks => to_unsigned(kSpPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => to_unsigned(kSpHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => sLoadSptCounts, --in boolean + sSptPeriodInSClks => to_unsigned(kSptPeriodInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => to_unsigned(kSptHighTimeInSClks, kSClksPerSpPeriodBitsMax), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransfer, --out boolean + sSpTransfer => sSpTransfer, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd new file mode 100644 index 000000000..1ab235fe2 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/common/sync/TdcWrapper.vhd @@ -0,0 +1,397 @@ +------------------------------------------------------------------------------- +-- +-- Copyright 2018 Ettus Research, a National Instruments Company +-- +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- +-- Purpose: +-- +-- Wrapper for the TDC and register control modules. +-- +-- vreview_group Tdc +-- vreview_reviewers dabaker sgupta jmarsar +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity TdcWrapper is + port ( + -- Clocks and Resets : -------------------------------------------------------------- + -- Bus Clock and synchronous bus reset. + BusClk : in std_logic; + bBusReset : in std_logic; + -- Reference Clock + RefClk : in std_logic; + -- Sample Clock + SampleClk : in std_logic; + -- Measurement Clock must run at a very specific frequency, determined by the + -- SampleClk, RefClk, and Sync Pulse rates... oh and a lot of math. + MeasClk : in std_logic; + + + -- Register Port: ------------------------------------------------------------------- + bSyncRegPortOut : out RegPortOut_t; + bSyncRegPortIn : in RegPortIn_t; + + + -- PPS In and Out : ----------------------------------------------------------------- + -- Only required to pulse 1 RefClk cycle. + rPpsPulse : in std_logic; + -- PPS pulse output on the SampleClk domain. + sPpsPulse : out std_logic; + + + -- Sync Pulse Outputs : ------------------------------------------------------------- + -- The repeating pulses can be useful for many things, including passing triggers. + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + + -- Pin bouncers out and in. Must go to unused and unconnected pins on the FPGA! + rGatedPulseToPin : inout std_logic; + sGatedPulseToPin : inout std_logic + ); +end TdcWrapper; + + +architecture struct of TdcWrapper is + + component SyncRegsIfc + port ( + aBusReset : in std_logic; + bBusReset : in std_logic; + BusClk : in std_logic; + aTdcReset : out std_logic; + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + RefClk : in std_logic; + rResetTdc : out std_logic; + rResetTdcDone : in std_logic; + rEnableTdc : out std_logic; + rReRunEnable : out std_logic; + rEnablePpsCrossing : out std_logic; + rPpsPulseCaptured : in std_logic; + rPulserEnableDelayVal : out std_logic_vector(3 downto 0); + SampleClk : in std_logic; + sPpsClkCrossDelayVal : out std_logic_vector(3 downto 0); + MeasClk : in std_logic; + mRpOffset : in std_logic_vector(39 downto 0); + mSpOffset : in std_logic_vector(39 downto 0); + mOffsetsDone : in std_logic; + mOffsetsValid : in std_logic; + rLoadRePulseCounts : out std_logic; + rRePulsePeriodInRClks : out std_logic_vector(23 downto 0); + rRePulseHighTimeInRClks : out std_logic_vector(23 downto 0); + rLoadRpCounts : out std_logic; + rRpPeriodInRClks : out std_logic_vector(15 downto 0); + rRpHighTimeInRClks : out std_logic_vector(15 downto 0); + rLoadRptCounts : out std_logic; + rRptPeriodInRClks : out std_logic_vector(15 downto 0); + rRptHighTimeInRClks : out std_logic_vector(15 downto 0); + sLoadSpCounts : out std_logic; + sSpPeriodInSClks : out std_logic_vector(15 downto 0); + sSpHighTimeInSClks : out std_logic_vector(15 downto 0); + sLoadSptCounts : out std_logic; + sSptPeriodInSClks : out std_logic_vector(15 downto 0); + sSptHighTimeInSClks : out std_logic_vector(15 downto 0)); + end component; + + -- Generic values for the TdcTop instantiation below. These generics are the maximum + -- of possible values for all combinations of Sample and Reference clocks for the N3xx + -- family of devices. + constant kRClksPerRePulsePeriodBitsMax : integer := 24; + constant kRClksPerRpPeriodBitsMax : integer := 16; + constant kSClksPerSpPeriodBitsMax : integer := 16; + constant kPulsePeriodCntSize : integer := 13; + -- The following are ideal values for balancing measurement time and accuracy, based + -- on calcs given in the spec doc. + constant kFreqRefPeriodsToCheckSize : integer := 17; + constant kSyncPeriodsToStampSize : integer := 10; + + --vhook_sigstart + signal aTdcReset: std_logic; + signal bSyncRegPortInFlat: std_logic_vector(49 downto 0); + signal bSyncRegPortOutFlat: std_logic_vector(33 downto 0); + signal mOffsetsDone: boolean; + signal mOffsetsValid: boolean; + signal mRpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal mSpOffset: unsigned(kPulsePeriodCntSize+kSyncPeriodsToStampSize+kFreqRefPeriodsToCheckSize-1 downto 0); + signal rEnablePpsCrossing: std_logic; + signal rEnableTdc: std_logic; + signal rLoadRePulseCounts: std_logic; + signal rLoadRpCounts: std_logic; + signal rLoadRptCounts: std_logic; + signal rPpsPulseCaptured: boolean; + signal rPulserEnableDelayVal: std_logic_vector(3 downto 0); + signal rRePulseHighTimeInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rRePulsePeriodInRClks: std_logic_vector(kRClksPerRePulsePeriodBitsMax-1 downto 0); + signal rReRunEnable: std_logic; + signal rResetTdc: std_logic; + signal rResetTdcDone: boolean; + signal rRpHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptHighTimeInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRptPeriodInRClks: std_logic_vector(kRClksPerRpPeriodBitsMax-1 downto 0); + signal rRpTransferBool: boolean; + signal sLoadSpCounts: std_logic; + signal sLoadSptCounts: std_logic; + signal sPpsClkCrossDelayVal: std_logic_vector(3 downto 0); + signal sPpsPulseAsyncReset: boolean; + signal sSpHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptHighTimeInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSptPeriodInSClks: std_logic_vector(kSClksPerSpPeriodBitsMax-1 downto 0); + signal sSpTransferBool: boolean; + --vhook_sigend + + signal rPpsPulseAsyncReset_ms, rPpsPulseAsyncReset, + sPpsPulseOut_ms, sPpsPulseOut : std_logic := '0'; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of rPpsPulseAsyncReset_ms : signal is "true"; + attribute ASYNC_REG of rPpsPulseAsyncReset : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut_ms : signal is "true"; + attribute ASYNC_REG of sPpsPulseOut : signal is "true"; + +begin + + -- Cross the PPS from the no-reset domain into the aTdcReset domain since there is a + -- reset crossing going into the TdcWrapper (reset by aTdcReset)! No clock domain + -- crossing here, so crossing a single-cycle pulse is safe. + DoubleSyncToAsyncReset : process (aTdcReset, RefClk) + begin + if to_boolean(aTdcReset) then + rPpsPulseAsyncReset_ms <= '0'; + rPpsPulseAsyncReset <= '0'; + elsif rising_edge(RefClk) then + rPpsPulseAsyncReset_ms <= rPpsPulse; + rPpsPulseAsyncReset <= rPpsPulseAsyncReset_ms; + end if; + end process; + + -- In a similar fashion, cross the output PPS trigger from the async aTdcReset domain + -- to the no-reset of the rest of the design. The odds of this signal triggering a + -- failure are astronomically low (since it only pulses one clock cycle per second), + -- but two flops is worth the assurance it won't mess something else up downstream. + -- Note this double-sync mainly protects against the reset assertion case, since in the + -- de-assertion case sPpsPulseAsyncReset should be zero and not transition for a long + -- time afterwards. Again no clock crossing here, so crossing a single-cycle pulse + -- is safe. + DoubleSyncToNoReset : process (SampleClk) + begin + if rising_edge(SampleClk) then + sPpsPulseOut_ms <= to_stdlogic(sPpsPulseAsyncReset); + sPpsPulseOut <= sPpsPulseOut_ms; + end if; + end process; + + sPpsPulse <= sPpsPulseOut; + + + rRpTransfer <= to_stdlogic(rRpTransferBool); + sSpTransfer <= to_stdlogic(sSpTransferBool); + + --vhook_e TdcTop + --vhook_a aReset to_boolean(aTdcReset) + --vhook_a rResetTdc to_boolean(rResetTdc) + --vhook_a rEnableTdc to_boolean(rEnableTdc) + --vhook_a rReRunEnable to_boolean(rReRunEnable) + --vhook_a rPpsPulse to_boolean(rPpsPulseAsyncReset) + --vhook_a rLoadRePulseCounts to_boolean(rLoadRePulseCounts) + --vhook_a rLoadRpCounts to_boolean(rLoadRpCounts) + --vhook_a rLoadRptCounts to_boolean(rLoadRptCounts) + --vhook_a sLoadSpCounts to_boolean(sLoadSpCounts) + --vhook_a sLoadSptCounts to_boolean(sLoadSptCounts) + --vhook_a rEnablePpsCrossing to_boolean(rEnablePpsCrossing) + --vhook_a rPulserEnableDelayVal unsigned(rPulserEnableDelayVal) + --vhook_a sPpsClkCrossDelayVal unsigned(sPpsClkCrossDelayVal) + --vhook_a rRpTransfer rRpTransferBool + --vhook_a sSpTransfer sSpTransferBool + --vhook_a sPpsPulse sPpsPulseAsyncReset + --vhook_p {^rR(.*)In(.*)Clks} unsigned(rR$1In$2Clks) + --vhook_p {^sS(.*)In(.*)Clks} unsigned(sS$1In$2Clks) + TdcTopx: entity work.TdcTop (struct) + generic map ( + kRClksPerRePulsePeriodBitsMax => kRClksPerRePulsePeriodBitsMax, --integer range 3:32 :=24 + kRClksPerRpPeriodBitsMax => kRClksPerRpPeriodBitsMax, --integer range 3:16 :=16 + kSClksPerSpPeriodBitsMax => kSClksPerSpPeriodBitsMax, --integer range 3:16 :=16 + kPulsePeriodCntSize => kPulsePeriodCntSize, --integer:=13 + kFreqRefPeriodsToCheckSize => kFreqRefPeriodsToCheckSize, --integer:=17 + kSyncPeriodsToStampSize => kSyncPeriodsToStampSize) --integer:=10 + port map ( + aReset => to_boolean(aTdcReset), --in boolean + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + rResetTdc => to_boolean(rResetTdc), --in boolean + rResetTdcDone => rResetTdcDone, --out boolean + rEnableTdc => to_boolean(rEnableTdc), --in boolean + rReRunEnable => to_boolean(rReRunEnable), --in boolean + rPpsPulse => to_boolean(rPpsPulseAsyncReset), --in boolean + rPpsPulseCaptured => rPpsPulseCaptured, --out boolean + rPulserEnableDelayVal => unsigned(rPulserEnableDelayVal), --in unsigned(3:0) + rEnablePpsCrossing => to_boolean(rEnablePpsCrossing), --in boolean + sPpsClkCrossDelayVal => unsigned(sPpsClkCrossDelayVal), --in unsigned(3:0) + sPpsPulse => sPpsPulseAsyncReset, --out boolean + mRpOffset => mRpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mSpOffset => mSpOffset, --out unsigned(kPulsePeriodCntSize+ kSyncPeriodsToStampSize+ kFreqRefPeriodsToCheckSize-1:0) + mOffsetsDone => mOffsetsDone, --out boolean + mOffsetsValid => mOffsetsValid, --out boolean + rLoadRePulseCounts => to_boolean(rLoadRePulseCounts), --in boolean + rRePulsePeriodInRClks => unsigned(rRePulsePeriodInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rRePulseHighTimeInRClks => unsigned(rRePulseHighTimeInRClks), --in unsigned(kRClksPerRePulsePeriodBitsMax-1:0) + rLoadRpCounts => to_boolean(rLoadRpCounts), --in boolean + rRpPeriodInRClks => unsigned(rRpPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRpHighTimeInRClks => unsigned(rRpHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rLoadRptCounts => to_boolean(rLoadRptCounts), --in boolean + rRptPeriodInRClks => unsigned(rRptPeriodInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + rRptHighTimeInRClks => unsigned(rRptHighTimeInRClks), --in unsigned(kRClksPerRpPeriodBitsMax-1:0) + sLoadSpCounts => to_boolean(sLoadSpCounts), --in boolean + sSpPeriodInSClks => unsigned(sSpPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSpHighTimeInSClks => unsigned(sSpHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sLoadSptCounts => to_boolean(sLoadSptCounts), --in boolean + sSptPeriodInSClks => unsigned(sSptPeriodInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + sSptHighTimeInSClks => unsigned(sSptHighTimeInSClks), --in unsigned(kSClksPerSpPeriodBitsMax-1:0) + rRpTransfer => rRpTransferBool, --out boolean + sSpTransfer => sSpTransferBool, --out boolean + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + -- Expand/compress the RegPort for moving through the netlist boundary. + bSyncRegPortOut <= Unflatten(bSyncRegPortOutFlat); + bSyncRegPortInFlat <= Flatten(bSyncRegPortIn); + + --vhook SyncRegsIfc + --vhook_# Tying this low is safe because the sync reset is used inside SyncRegsIfc. + --vhook_a aBusReset '0' + --vhook_a bRegPortInFlat bSyncRegPortInFlat + --vhook_a bRegPortOutFlat bSyncRegPortOutFlat + --vhook_a rResetTdcDone to_stdlogic(rResetTdcDone) + --vhook_a rPpsPulseCaptured to_stdlogic(rPpsPulseCaptured) + --vhook_a mOffsetsDone to_stdlogic(mOffsetsDone) + --vhook_a mOffsetsValid to_stdlogic(mOffsetsValid) + --vhook_a mRpOffset std_logic_vector(mRpOffset) + --vhook_a mSpOffset std_logic_vector(mSpOffset) + SyncRegsIfcx: SyncRegsIfc + port map ( + aBusReset => '0', --in std_logic + bBusReset => bBusReset, --in std_logic + BusClk => BusClk, --in std_logic + aTdcReset => aTdcReset, --out std_logic + bRegPortInFlat => bSyncRegPortInFlat, --in std_logic_vector(49:0) + bRegPortOutFlat => bSyncRegPortOutFlat, --out std_logic_vector(33:0) + RefClk => RefClk, --in std_logic + rResetTdc => rResetTdc, --out std_logic + rResetTdcDone => to_stdlogic(rResetTdcDone), --in std_logic + rEnableTdc => rEnableTdc, --out std_logic + rReRunEnable => rReRunEnable, --out std_logic + rEnablePpsCrossing => rEnablePpsCrossing, --out std_logic + rPpsPulseCaptured => to_stdlogic(rPpsPulseCaptured), --in std_logic + rPulserEnableDelayVal => rPulserEnableDelayVal, --out std_logic_vector(3:0) + SampleClk => SampleClk, --in std_logic + sPpsClkCrossDelayVal => sPpsClkCrossDelayVal, --out std_logic_vector(3:0) + MeasClk => MeasClk, --in std_logic + mRpOffset => std_logic_vector(mRpOffset), --in std_logic_vector(39:0) + mSpOffset => std_logic_vector(mSpOffset), --in std_logic_vector(39:0) + mOffsetsDone => to_stdlogic(mOffsetsDone), --in std_logic + mOffsetsValid => to_stdlogic(mOffsetsValid), --in std_logic + rLoadRePulseCounts => rLoadRePulseCounts, --out std_logic + rRePulsePeriodInRClks => rRePulsePeriodInRClks, --out std_logic_vector(23:0) + rRePulseHighTimeInRClks => rRePulseHighTimeInRClks, --out std_logic_vector(23:0) + rLoadRpCounts => rLoadRpCounts, --out std_logic + rRpPeriodInRClks => rRpPeriodInRClks, --out std_logic_vector(15:0) + rRpHighTimeInRClks => rRpHighTimeInRClks, --out std_logic_vector(15:0) + rLoadRptCounts => rLoadRptCounts, --out std_logic + rRptPeriodInRClks => rRptPeriodInRClks, --out std_logic_vector(15:0) + rRptHighTimeInRClks => rRptHighTimeInRClks, --out std_logic_vector(15:0) + sLoadSpCounts => sLoadSpCounts, --out std_logic + sSpPeriodInSClks => sSpPeriodInSClks, --out std_logic_vector(15:0) + sSpHighTimeInSClks => sSpHighTimeInSClks, --out std_logic_vector(15:0) + sLoadSptCounts => sLoadSptCounts, --out std_logic + sSptPeriodInSClks => sSptPeriodInSClks, --out std_logic_vector(15:0) + sSptHighTimeInSClks => sSptHighTimeInSClks); --out std_logic_vector(15:0) + + +end struct; + + +-------------------------------------------------------------------------------- +-- Testbench for TdcWrapper +-------------------------------------------------------------------------------- + +--synopsys translate_off +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + +entity tb_TdcWrapper is end tb_TdcWrapper; + +architecture test of tb_TdcWrapper is + + --vhook_sigstart + signal bBusReset: std_logic; + signal bSyncRegPortIn: RegPortIn_t; + signal bSyncRegPortOut: RegPortOut_t; + signal BusClk: std_logic := '0'; + signal MeasClk: std_logic := '0'; + signal RefClk: std_logic := '0'; + signal rGatedPulseToPin: std_logic; + signal rPpsPulse: std_logic; + signal rRpTransfer: std_logic; + signal SampleClk: std_logic := '0'; + signal sGatedPulseToPin: std_logic; + signal sPpsPulse: std_logic; + signal sSpTransfer: std_logic; + --vhook_sigend + +begin + + --vhook_e TdcWrapper dutx + dutx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sPpsPulse, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + main: process + + begin + report "TdcWrapper Test is EMPTY! (but that's ok in this case)" severity note; + --vhook_nowarn tb_TdcWrapper.test.* + wait; + end process; + +end test; +--synopsys translate_on diff --git a/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs new file mode 100644 index 000000000..85bb60752 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/Makefile.srcs @@ -0,0 +1,34 @@ +# +# Copyright 2017 Ettus Research LLC +# + +################################################## +# DB IFC Sources +################################################## +MAGNESIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgMgPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +MAGNESIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +n3xx.v \ +)) + +MAGNESIUM_DB_TIMING_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db_timing.xdc \ +)) + +MAGNESIUM_DB0_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db0_pins.xdc \ +)) + +MAGNESIUM_DB1_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/mg/, \ +db1_pins.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile new file mode 100644 index 000000000..3fbb7d3bb --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Makefile @@ -0,0 +1,22 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=TopCpld.qpf TopCpld.qsf Timing.sdc PkgMgCpld.vhd PkgSetup.vhd TopCpld.vhd + +all: output_files/TopCpld.svf + +cpld-magnesium-revc.svf: output_files/TopCpld.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 3.3 --operation p $? $@ + +output_files/TopCpld.pof: $(SRCS) + quartus_map TopCpld + quartus_fit TopCpld + quartus_asm TopCpld + quartus_sta TopCpld + +clean: + rm -rf db incremental_db output_files simulation cpld-magnesium-revc.svf + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd new file mode 100644 index 000000000..327183bea --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgMgCpld.vhd @@ -0,0 +1,424 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgCpld.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgMgCpld is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- SignatureReg : 0x0 (TopCpld.vhd) + -- MinorRevReg : 0x1 (TopCpld.vhd) + -- MajorRevReg : 0x2 (TopCpld.vhd) + -- BuildCodeLSB : 0x3 (TopCpld.vhd) + -- BuildCodeMSB : 0x4 (TopCpld.vhd) + -- Scratch : 0x5 (TopCpld.vhd) + -- CpldControl : 0x10 (TopCpld.vhd) + -- LmkControl : 0x11 (TopCpld.vhd) + -- LoStatus : 0x12 (TopCpld.vhd) + -- MykonosControl : 0x13 (TopCpld.vhd) + -- PlScratch : 0x40 (TopCpld.vhd) + -- PlCpldControl : 0x41 (TopCpld.vhd) + -- TxCh1_Idle : 0x50 (TopCpld.vhd) + -- RxCh1_0_Idle : 0x51 (TopCpld.vhd) + -- RxCh1_1_Idle : 0x52 (TopCpld.vhd) + -- TxCh1_TxOn : 0x53 (TopCpld.vhd) + -- RxCh1_0_RxOn : 0x54 (TopCpld.vhd) + -- RxCh1_1_RxOn : 0x55 (TopCpld.vhd) + -- TxCh2_Idle : 0x60 (TopCpld.vhd) + -- RxCh2_0_Idle : 0x61 (TopCpld.vhd) + -- RxCh2_1_Idle : 0x62 (TopCpld.vhd) + -- TxCh2_TxOn : 0x63 (TopCpld.vhd) + -- RxCh2_0_RxOn : 0x64 (TopCpld.vhd) + -- RxCh2_1_RxOn : 0x65 (TopCpld.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group PsSpi_CpldRegisters +--=============================================================================== + + -- SignatureReg Register (from TopCpld.vhd) + constant kSignatureReg : integer := 16#0#; -- Register Offset + constant kSignatureRegSize: integer := 16; -- register width in bits + constant kSignatureRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kProductSignatureSize : integer := 16; --SignatureReg:ProductSignature + constant kProductSignatureMsb : integer := 15; --SignatureReg:ProductSignature + constant kProductSignature : integer := 0; --SignatureReg:ProductSignature + + -- MinorRevReg Register (from TopCpld.vhd) + constant kMinorRevReg : integer := 16#1#; -- Register Offset + constant kMinorRevRegSize: integer := 16; -- register width in bits + constant kMinorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMinorRevisionSize : integer := 16; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevisionMsb : integer := 15; --MinorRevReg:CpldMinorRevision + constant kCpldMinorRevision : integer := 0; --MinorRevReg:CpldMinorRevision + + -- MajorRevReg Register (from TopCpld.vhd) + constant kMajorRevReg : integer := 16#2#; -- Register Offset + constant kMajorRevRegSize: integer := 16; -- register width in bits + constant kMajorRevRegMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kCpldMajorRevisionSize : integer := 16; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevisionMsb : integer := 15; --MajorRevReg:CpldMajorRevision + constant kCpldMajorRevision : integer := 0; --MajorRevReg:CpldMajorRevision + + -- BuildCodeLSB Register (from TopCpld.vhd) + constant kBuildCodeLSB : integer := 16#3#; -- Register Offset + constant kBuildCodeLSBSize: integer := 16; -- register width in bits + constant kBuildCodeLSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeHHSize : integer := 8; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHHMsb : integer := 7; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeHH : integer := 0; --BuildCodeLSB:BuildCodeHH + constant kBuildCodeDDSize : integer := 8; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDDMsb : integer := 15; --BuildCodeLSB:BuildCodeDD + constant kBuildCodeDD : integer := 8; --BuildCodeLSB:BuildCodeDD + + -- BuildCodeMSB Register (from TopCpld.vhd) + constant kBuildCodeMSB : integer := 16#4#; -- Register Offset + constant kBuildCodeMSBSize: integer := 16; -- register width in bits + constant kBuildCodeMSBMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kBuildCodeMMSize : integer := 8; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMMMsb : integer := 7; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeMM : integer := 0; --BuildCodeMSB:BuildCodeMM + constant kBuildCodeYYSize : integer := 8; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYYMsb : integer := 15; --BuildCodeMSB:BuildCodeYY + constant kBuildCodeYY : integer := 8; --BuildCodeMSB:BuildCodeYY + + -- Scratch Register (from TopCpld.vhd) + constant kScratch : integer := 16#5#; -- Register Offset + constant kScratchSize: integer := 16; -- register width in bits + constant kScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kScratchValSize : integer := 16; --Scratch:ScratchVal + constant kScratchValMsb : integer := 15; --Scratch:ScratchVal + constant kScratchVal : integer := 0; --Scratch:ScratchVal + + -- CpldControl Register (from TopCpld.vhd) + constant kCpldControl : integer := 16#10#; -- Register Offset + constant kCpldControlSize: integer := 16; -- register width in bits + constant kCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kCpldResetSize : integer := 1; --CpldControl:CpldReset + constant kCpldResetMsb : integer := 0; --CpldControl:CpldReset + constant kCpldReset : integer := 0; --CpldControl:CpldReset + + -- LmkControl Register (from TopCpld.vhd) + constant kLmkControl : integer := 16#11#; -- Register Offset + constant kLmkControlSize: integer := 16; -- register width in bits + constant kLmkControlMask : std_logic_vector(15 downto 0) := X"0010"; + constant kVcxoControlSize : integer := 1; --LmkControl:VcxoControl + constant kVcxoControlMsb : integer := 4; --LmkControl:VcxoControl + constant kVcxoControl : integer := 4; --LmkControl:VcxoControl + + -- LoStatus Register (from TopCpld.vhd) + constant kLoStatus : integer := 16#12#; -- Register Offset + constant kLoStatusSize: integer := 16; -- register width in bits + constant kLoStatusMask : std_logic_vector(15 downto 0) := X"0011"; + constant kRxLoLockDetectSize : integer := 1; --LoStatus:RxLoLockDetect + constant kRxLoLockDetectMsb : integer := 0; --LoStatus:RxLoLockDetect + constant kRxLoLockDetect : integer := 0; --LoStatus:RxLoLockDetect + constant kTxLoLockDetectSize : integer := 1; --LoStatus:TxLoLockDetect + constant kTxLoLockDetectMsb : integer := 4; --LoStatus:TxLoLockDetect + constant kTxLoLockDetect : integer := 4; --LoStatus:TxLoLockDetect + + -- MykonosControl Register (from TopCpld.vhd) + constant kMykonosControl : integer := 16#13#; -- Register Offset + constant kMykonosControlSize: integer := 16; -- register width in bits + constant kMykonosControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kMykonosResetSize : integer := 1; --MykonosControl:MykonosReset + constant kMykonosResetMsb : integer := 0; --MykonosControl:MykonosReset + constant kMykonosReset : integer := 0; --MykonosControl:MykonosReset + +--=============================================================================== +-- Register Group PlSpi_FrontEndControl +--=============================================================================== + + -- Enumerated type Rx1Switch1 + constant kRx1Switch1Size : integer := 4; + constant kTxRxInput : integer := 0; -- Rx1Switch1:TxRxInput + constant kRxLoCalInput : integer := 1; -- Rx1Switch1:RxLoCalInput + constant kTrxSwitchOutput : integer := 2; -- Rx1Switch1:TrxSwitchOutput + constant kRx2Input : integer := 3; -- Rx1Switch1:Rx2Input + + -- Enumerated type Rx1Switch2 + constant kRx1Switch2Size : integer := 4; + constant kShutdownSw2 : integer := 0; -- Rx1Switch2:ShutdownSw2 + constant kLowerFilterBankToSwitch3 : integer := 1; -- Rx1Switch2:LowerFilterBankToSwitch3 + constant kBypassPathToSwitch6 : integer := 2; -- Rx1Switch2:BypassPathToSwitch6 + constant kUpperFilterBankToSwitch4 : integer := 3; -- Rx1Switch2:UpperFilterBankToSwitch4 + + -- Enumerated type Rx1Switch3 + constant kRx1Switch3Size : integer := 7; + constant kFilter2100x2850MHz : integer := 0; -- Rx1Switch3:Filter2100x2850MHz + constant kFilter0490LpMHz : integer := 1; -- Rx1Switch3:Filter0490LpMHz + constant kFilter1600x2250MHz : integer := 2; -- Rx1Switch3:Filter1600x2250MHz + constant kFilter0440x0530MHz : integer := 4; -- Rx1Switch3:Filter0440x0530MHz + constant kFilter0650x1000MHz : integer := 5; -- Rx1Switch3:Filter0650x1000MHz + constant kFilter1100x1575MHz : integer := 6; -- Rx1Switch3:Filter1100x1575MHz + constant kShutdownSw3 : integer := 7; -- Rx1Switch3:ShutdownSw3 + + -- Enumerated type Rx1Switch4 + constant kRx1Switch4Size : integer := 3; + constant kFilter2100x2850MHzFrom : integer := 1; -- Rx1Switch4:Filter2100x2850MHzFrom + constant kFilter1600x2250MHzFrom : integer := 2; -- Rx1Switch4:Filter1600x2250MHzFrom + constant kFilter2700HpMHz : integer := 4; -- Rx1Switch4:Filter2700HpMHz + + -- Enumerated type Rx1Switch5 + constant kRx1Switch5Size : integer := 4; + constant kFilter0440x0530MHzFrom : integer := 1; -- Rx1Switch5:Filter0440x0530MHzFrom + constant kFilter1100x1575MHzFrom : integer := 2; -- Rx1Switch5:Filter1100x1575MHzFrom + constant kFilter0490LpMHzFrom : integer := 4; -- Rx1Switch5:Filter0490LpMHzFrom + constant kFilter0650x1000MHzFrom : integer := 8; -- Rx1Switch5:Filter0650x1000MHzFrom + + -- Enumerated type Rx1Switch6 + constant kRx1Switch6Size : integer := 3; + constant kLowerFilterBankFromSwitch5 : integer := 1; -- Rx1Switch6:LowerFilterBankFromSwitch5 + constant kUpperFilterBankFromSwitch4 : integer := 2; -- Rx1Switch6:UpperFilterBankFromSwitch4 + constant kBypassPathFromSwitch2 : integer := 4; -- Rx1Switch6:BypassPathFromSwitch2 + + -- Enumerated type TrxSwitch + constant kTrxSwitchSize : integer := 4; + constant kFromLowerFilterBankTxSw1 : integer := 0; -- TrxSwitch:FromLowerFilterBankTxSw1 + constant kFromTxUpperFilterBankLp6400MHz : integer := 1; -- TrxSwitch:FromTxUpperFilterBankLp6400MHz + constant kRxChannelPath : integer := 2; -- TrxSwitch:RxChannelPath + constant kBypassPathToTxSw3 : integer := 3; -- TrxSwitch:BypassPathToTxSw3 + + -- Enumerated type TxSwitch1 + constant kTxSwitch1Size : integer := 4; + constant kShutdownTxSw1 : integer := 0; -- TxSwitch1:ShutdownTxSw1 + constant kFromTxFilterLp1700MHz : integer := 1; -- TxSwitch1:FromTxFilterLp1700MHz + constant kFromTxFilterLp3400MHz : integer := 2; -- TxSwitch1:FromTxFilterLp3400MHz + constant kFromTxFilterLp0800MHz : integer := 3; -- TxSwitch1:FromTxFilterLp0800MHz + + -- Enumerated type TxSwitch2 + constant kTxSwitch2Size : integer := 4; + constant kToTxFilterLp3400MHz : integer := 1; -- TxSwitch2:ToTxFilterLp3400MHz + constant kToTxFilterLp1700MHz : integer := 2; -- TxSwitch2:ToTxFilterLp1700MHz + constant kToTxFilterLp0800MHz : integer := 4; -- TxSwitch2:ToTxFilterLp0800MHz + constant kToTxFilterLp6400MHz : integer := 8; -- TxSwitch2:ToTxFilterLp6400MHz + + -- Enumerated type TxSwitch3 + constant kTxSwitch3Size : integer := 2; + constant kToTxFilterBanks : integer := 0; -- TxSwitch3:ToTxFilterBanks + constant kBypassPathToTrxSw : integer := 1; -- TxSwitch3:BypassPathToTrxSw + + -- PlScratch Register (from TopCpld.vhd) + constant kPlScratch : integer := 16#40#; -- Register Offset + constant kPlScratchSize: integer := 16; -- register width in bits + constant kPlScratchMask : std_logic_vector(15 downto 0) := X"ffff"; + constant kPlScratchValSize : integer := 16; --PlScratch:PlScratchVal + constant kPlScratchValMsb : integer := 15; --PlScratch:PlScratchVal + constant kPlScratchVal : integer := 0; --PlScratch:PlScratchVal + + -- PlCpldControl Register (from TopCpld.vhd) + constant kPlCpldControl : integer := 16#41#; -- Register Offset + constant kPlCpldControlSize: integer := 16; -- register width in bits + constant kPlCpldControlMask : std_logic_vector(15 downto 0) := X"0001"; + constant kPlCpldResetSize : integer := 1; --PlCpldControl:PlCpldReset + constant kPlCpldResetMsb : integer := 0; --PlCpldControl:PlCpldReset + constant kPlCpldReset : integer := 0; --PlCpldControl:PlCpldReset + + -- TxCh1_Idle Register (from TopCpld.vhd) + constant kTxCh1_Idle : integer := 16#50#; -- Register Offset + constant kTxCh1_IdleSize: integer := 16; -- register width in bits + constant kTxCh1_IdleMask : std_logic_vector(15 downto 0) := X"7fff"; + constant kCh1TxSw1Size : integer := 2; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1Msb : integer := 1; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw1 : integer := 0; --TxCh1_Idle:Ch1TxSw1 + constant kCh1TxSw2Size : integer := 4; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2Msb : integer := 5; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw2 : integer := 2; --TxCh1_Idle:Ch1TxSw2 + constant kCh1TxSw3Size : integer := 1; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3Msb : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxSw3 : integer := 6; --TxCh1_Idle:Ch1TxSw3 + constant kCh1TxLowbandMixerPathSelectSize : integer := 1; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelectMsb : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxLowbandMixerPathSelect : integer := 7; --TxCh1_Idle:Ch1TxLowbandMixerPathSelect + constant kCh1TxMixerEnSize : integer := 1; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEnMsb : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxMixerEn : integer := 8; --TxCh1_Idle:Ch1TxMixerEn + constant kCh1TxAmpEnSize : integer := 1; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEnMsb : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxAmpEn : integer := 9; --TxCh1_Idle:Ch1TxAmpEn + constant kCh1TxPaEnSize : integer := 1; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEnMsb : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1TxPaEn : integer := 10; --TxCh1_Idle:Ch1TxPaEn + constant kCh1SwTrxSize : integer := 2; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrxMsb : integer := 12; --TxCh1_Idle:Ch1SwTrx + constant kCh1SwTrx : integer := 11; --TxCh1_Idle:Ch1SwTrx + constant kCh1TxLedSize : integer := 1; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLedMsb : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1TxLed : integer := 13; --TxCh1_Idle:Ch1TxLed + constant kCh1MykEnTxSize : integer := 1; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTxMsb : integer := 14; --TxCh1_Idle:Ch1MykEnTx + constant kCh1MykEnTx : integer := 14; --TxCh1_Idle:Ch1MykEnTx + + -- RxCh1_0_Idle Register (from TopCpld.vhd) + constant kRxCh1_0_Idle : integer := 16#51#; -- Register Offset + constant kRxCh1_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_0_IdleMask : std_logic_vector(15 downto 0) := X"3fff"; + constant kCh1RxSw1Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1Msb : integer := 1; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw1 : integer := 0; --RxCh1_0_Idle:Ch1RxSw1 + constant kCh1RxSw2Size : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2Msb : integer := 3; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw2 : integer := 2; --RxCh1_0_Idle:Ch1RxSw2 + constant kCh1RxSw3Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3Msb : integer := 6; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw3 : integer := 4; --RxCh1_0_Idle:Ch1RxSw3 + constant kCh1RxSw4Size : integer := 3; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4Msb : integer := 9; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw4 : integer := 7; --RxCh1_0_Idle:Ch1RxSw4 + constant kCh1RxSw5Size : integer := 4; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5Msb : integer := 13; --RxCh1_0_Idle:Ch1RxSw5 + constant kCh1RxSw5 : integer := 10; --RxCh1_0_Idle:Ch1RxSw5 + + -- RxCh1_1_Idle Register (from TopCpld.vhd) + constant kRxCh1_1_Idle : integer := 16#52#; -- Register Offset + constant kRxCh1_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh1_1_IdleMask : std_logic_vector(15 downto 0) := X"07ff"; + constant kCh1RxSw6Size : integer := 3; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6Msb : integer := 2; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxSw6 : integer := 0; --RxCh1_1_Idle:Ch1RxSw6 + constant kCh1RxLowbandMixerPathSelectSize : integer := 1; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelectMsb : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxLowbandMixerPathSelect : integer := 3; --RxCh1_1_Idle:Ch1RxLowbandMixerPathSelect + constant kCh1RxMixerEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEnMsb : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxMixerEn : integer := 4; --RxCh1_1_Idle:Ch1RxMixerEn + constant kCh1RxAmpEnSize : integer := 1; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEnMsb : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxAmpEn : integer := 5; --RxCh1_1_Idle:Ch1RxAmpEn + constant kCh1RxLna1EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1EnMsb : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna1En : integer := 6; --RxCh1_1_Idle:Ch1RxLna1En + constant kCh1RxLna2EnSize : integer := 1; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2EnMsb : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1RxLna2En : integer := 7; --RxCh1_1_Idle:Ch1RxLna2En + constant kCh1Rx2LedSize : integer := 1; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2LedMsb : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1Rx2Led : integer := 8; --RxCh1_1_Idle:Ch1Rx2Led + constant kCh1RxLedSize : integer := 1; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLedMsb : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1RxLed : integer := 9; --RxCh1_1_Idle:Ch1RxLed + constant kCh1MykEnRxSize : integer := 1; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRxMsb : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + constant kCh1MykEnRx : integer := 10; --RxCh1_1_Idle:Ch1MykEnRx + + -- TxCh1_TxOn Register (from TopCpld.vhd) + constant kTxCh1_TxOn : integer := 16#53#; -- Register Offset + constant kTxCh1_TxOnSize: integer := 16; -- register width in bits + constant kTxCh1_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_0_RxOn Register (from TopCpld.vhd) + constant kRxCh1_0_RxOn : integer := 16#54#; -- Register Offset + constant kRxCh1_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh1_1_RxOn Register (from TopCpld.vhd) + constant kRxCh1_1_RxOn : integer := 16#55#; -- Register Offset + constant kRxCh1_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh1_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_Idle Register (from TopCpld.vhd) + constant kTxCh2_Idle : integer := 16#60#; -- Register Offset + constant kTxCh2_IdleSize: integer := 16; -- register width in bits + constant kTxCh2_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_Idle Register (from TopCpld.vhd) + constant kRxCh2_0_Idle : integer := 16#61#; -- Register Offset + constant kRxCh2_0_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_0_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_Idle Register (from TopCpld.vhd) + constant kRxCh2_1_Idle : integer := 16#62#; -- Register Offset + constant kRxCh2_1_IdleSize: integer := 16; -- register width in bits + constant kRxCh2_1_IdleMask : std_logic_vector(15 downto 0) := X"0000"; + + -- TxCh2_TxOn Register (from TopCpld.vhd) + constant kTxCh2_TxOn : integer := 16#63#; -- Register Offset + constant kTxCh2_TxOnSize: integer := 16; -- register width in bits + constant kTxCh2_TxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_0_RxOn Register (from TopCpld.vhd) + constant kRxCh2_0_RxOn : integer := 16#64#; -- Register Offset + constant kRxCh2_0_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_0_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + + -- RxCh2_1_RxOn Register (from TopCpld.vhd) + constant kRxCh2_1_RxOn : integer := 16#65#; -- Register Offset + constant kRxCh2_1_RxOnSize: integer := 16; -- register width in bits + constant kRxCh2_1_RxOnMask : std_logic_vector(15 downto 0) := X"0000"; + +end package; + +package body PkgMgCpld is + + -- function kSignatureRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMinorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMajorRevRegRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeLSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kBuildCodeMSBRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLmkControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kLoStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMykonosControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlScratchRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPlCpldControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh1_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh1_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_IdleRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kTxCh2_TxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_0_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRxCh2_1_RxOnRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd new file mode 100644 index 000000000..e19358912 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/PkgSetup.vhd @@ -0,0 +1,259 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgSetup.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 September 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Default values for front end config and CPLD constants. +-- +-- Contains the revision constants that must be bumped when the CPLD is updated. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgCpld.all; + +package PkgSetup is + + + constant kRdWtWidth : integer := 1; + constant kAddrWidth : integer := 7; + constant kDataWidth : integer := 16; + constant kTotalWidth : integer := kRdWtWidth + kAddrWidth + kDataWidth; + + subtype InterfaceData_t is std_logic_vector(kDataWidth-1 downto 0); + + constant kSignature : InterfaceData_t := x"CAFE"; + + + -- UPDATE THESE REVISIONS when making changes to the CPLD ----------------------------- + -- ------------------------------------------------------------------------------------ + constant kMinorRev : InterfaceData_t := std_logic_vector(to_unsigned(0,kDataWidth)); + constant kMajorRev : InterfaceData_t := std_logic_vector(to_unsigned(5,kDataWidth)); + -- Currently just the timestamp of the build time/date: yymmddhh + constant kBuildCode : std_logic_vector(31 downto 0) := X"18010408"; + + + function kTxChDefault return InterfaceData_t; + function kTxChDefaultRun return InterfaceData_t; + function kRxChDefault0 return InterfaceData_t; + function kRxChDefault1 return InterfaceData_t; + function kRxChDefault0Run return InterfaceData_t; + function kRxChDefault1Run return InterfaceData_t; + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Tx2TrxMod (kCh1Val : std_logic_vector) return std_logic_vector; + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector; + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector; + + +end package; + +package body PkgSetup is + + function kTxChDefault return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kShutdownTxSw1, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '0'; + RetVal(kCh1TxPaEn) := '0'; + RetVal(kCh1TxLed) := '0'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefault; + + function kTxChDefaultRun return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1SwTrxMsb downto kCh1SwTrx) := std_logic_vector(to_unsigned(kFromLowerFilterBankTxSw1, kCh1SwTrxSize)); + RetVal(kCh1TxSw1Msb downto kCh1TxSw1) := std_logic_vector(to_unsigned(kFromTxFilterLp3400MHz, kCh1TxSw1Size)); + RetVal(kCh1TxSw2Msb downto kCh1TxSw2) := std_logic_vector(to_unsigned(kToTxFilterLp3400MHz, kCh1TxSw2Size)); + RetVal(kCh1TxSw3 downto kCh1TxSw3) := std_logic_vector(to_unsigned(kToTxFilterBanks, kCh1TxSw3Size)); + RetVal(kCh1TxLowbandMixerPathSelect) := '0'; + RetVal(kCh1TxMixerEn) := '0'; + RetVal(kCh1TxAmpEn) := '1'; + RetVal(kCh1TxPaEn) := '1'; + RetVal(kCh1TxLed) := '1'; + RetVal(kCh1MykEnTx) := '1'; + return RetVal; + end kTxChDefaultRun; + + + + + function kRxChDefault0 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kShutdownSw2, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kShutdownSw3, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0; + + function kRxChDefault1 return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '0'; + RetVal(kCh1RxLna1En) := '0'; + RetVal(kCh1RxLna2En) := '0'; + RetVal(kCh1Rx2Led) := '0'; + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1; + + function kRxChDefault0Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw1Msb downto kCh1RxSw1) := std_logic_vector(to_unsigned(kRx2Input, kCh1RxSw1Size)); + RetVal(kCh1RxSw2Msb downto kCh1RxSw2) := std_logic_vector(to_unsigned(kLowerFilterBankToSwitch3, kCh1RxSw2Size)); + RetVal(kCh1RxSw3Msb downto kCh1RxSw3) := std_logic_vector(to_unsigned(kFilter2100x2850MHz, kCh1RxSw3Size)); + RetVal(kCh1RxSw4Msb downto kCh1RxSw4) := std_logic_vector(to_unsigned(kFilter2100x2850MHzFrom, kCh1RxSw4Size)); + RetVal(kCh1RxSw5Msb downto kCh1RxSw5) := std_logic_vector(to_unsigned(kFilter0490LpMHzFrom, kCh1RxSw5Size)); + return RetVal; + end kRxChDefault0Run; + + function kRxChDefault1Run return InterfaceData_t is + variable RetVal : InterfaceData_t := (others => '0'); + begin + RetVal(kCh1RxSw6Msb downto kCh1RxSw6) := std_logic_vector(to_unsigned(kUpperFilterBankFromSwitch4, kCh1RxSw6Size)); + RetVal(kCh1RxLowbandMixerPathSelect) := '0'; + RetVal(kCh1RxMixerEn) := '0'; + RetVal(kCh1RxAmpEn) := '1'; + RetVal(kCh1RxLna1En) := '1'; + RetVal(kCh1RxLna2En) := '1'; + RetVal(kCh1Rx2Led) := '1'; -- turn on a LED for grins + RetVal(kCh1RxLed) := '0'; + RetVal(kCh1MykEnRx) := '1'; + return RetVal; + end kRxChDefault1Run; + + + + + + + function Tx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Tx2Switch2Mod; + + function Tx2TrxMod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "10"; + elsif kCh1Val = "10" then RetVal := "01"; + elsif kCh1Val = "11" then RetVal := "11"; + else RetVal := "00"; end if; + return RetVal; + end Tx2TrxMod; + + + + function Rx2Switch1Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "01"; + elsif kCh1Val = "01" then RetVal := "00"; + elsif kCh1Val = "10" then RetVal := "11"; + elsif kCh1Val = "11" then RetVal := "10"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch1Mod; + + function Rx2Switch2Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "00" then RetVal := "00"; + elsif kCh1Val = "01" then RetVal := "11"; + elsif kCh1Val = "10" then RetVal := "10"; + elsif kCh1Val = "11" then RetVal := "01"; + else RetVal := "00"; end if; + return RetVal; + end Rx2Switch2Mod; + + function Rx2Switch3Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is binary, so we need to mux. + if kCh1Val = "000" then RetVal := "100"; + elsif kCh1Val = "001" then RetVal := "101"; + elsif kCh1Val = "010" then RetVal := "110"; + elsif kCh1Val = "011" then RetVal := "011"; + elsif kCh1Val = "100" then RetVal := "001"; + elsif kCh1Val = "101" then RetVal := "000"; + elsif kCh1Val = "110" then RetVal := "010"; + elsif kCh1Val = "111" then RetVal := "111"; + else RetVal := "000"; end if; + return RetVal; + end Rx2Switch3Mod; + + function Rx2Switch4Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch4Mod; + + function Rx2Switch5Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 3) := kCh1Val(kCh1Val'low + 2); + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 3); + return RetVal; + end Rx2Switch5Mod; + + function Rx2Switch6Mod(kCh1Val : std_logic_vector) return std_logic_vector is + variable RetVal : std_logic_vector(kCh1Val'range) := (others => '0'); + begin + -- Encoding for this switch is one-hot, so we just flip around the bits here. + RetVal(kCh1Val'low + 2) := kCh1Val(kCh1Val'low + 0); + RetVal(kCh1Val'low + 1) := kCh1Val(kCh1Val'low + 1); + RetVal(kCh1Val'low + 0) := kCh1Val(kCh1Val'low + 2); + return RetVal; + end Rx2Switch6Mod; + + +end package body; \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc new file mode 100644 index 000000000..496814662 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/Timing.sdc @@ -0,0 +1,160 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + +# All the magic numbers come from the "/n3xx/dboards/mg/doc/mg_timing.xlsx" timing +# analysis spreadsheet. Analysis should be re-performed every time a board rev occurs +# that affects the CPLD interfaces. + +## PS Slave Constraints ################################################################# +# - PsClk Rate +# - PsClk to SDI +# - PsClk to LE (sync and async paths) +# - PsClk to SDO + +# Maximum 4 MHz clock rate! This is heavily limited by the read data turnaround time... +# and could be up to 20 MHz if only performing writes. +create_clock -name PsClk -period 250 [get_ports {PsSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PsSdiInputDelayMax 22.303 +set PsSdiInputDelayMin -19.019 + +# SDI is driven from the PS on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-20ns due to FPGA routing delays and board buffering. Complete timing +# analysis is performed and recorded elsewhere. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiSdi] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PsClk -max $PsSdiInputDelayMax [get_ports sPsSpiLe] -clock_fall +set_input_delay -clock PsClk -min $PsSdiInputDelayMin [get_ports sPsSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMosiIndex[*]|*] +set_false_path -from [get_ports {sPsSpiLe}] -to [get_pins sPsMisoIndex[*]|*] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 60 = 250/2 - 60 = 65 ns. +set PsSdoOutputDelayMax 60 +set PsSdoOutputDelayMin -10 + +set_output_delay -clock PsClk -max $PsSdoOutputDelayMax [get_ports sPsSpiSdo] +set_output_delay -clock PsClk -min $PsSdoOutputDelayMin [get_ports sPsSpiSdo] + + + +## PL Slave Constraints ################################################################# +# - PlClk Rate +# - PlClk to SDI +# - PlClk to LE (sync and async paths) +# - PlClk to SDO + +# Maximum 5 MHz clock rate! +create_clock -name PlClk -period 200 [get_ports {PlSpiSck}] + +# SDI is both registered in the CPLD and used as a direct passthrough. First constrain +# the input delay on the local paths inside the CPLD. Passthrough constraints +# are handled elsewhere. + +set PlSdiInputDelayMax 10.445 +set PlSdiInputDelayMin -10.378 + +# SDI is driven from the FPGA on the falling edge of the Clk. Worst-case data-clock skew +# is around +/-10ns. Complete timing analysis is performed and recorded elsewhere. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiSdi] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiSdi] -clock_fall + +# For the CPLD Cs_n, the latch enable is used both as an asynchronous reset and +# synchronously to latch data. First, constrain the overall input delay for sync use. +# Technically, Cs_n is asserted and de-asserted many nanoseconds before the clock arrives +# but we still constrain it identically to the SDI in case something goes amiss. +set_input_delay -clock PlClk -max $PlSdiInputDelayMax [get_ports lPlSpiLe] -clock_fall +set_input_delay -clock PlClk -min $PlSdiInputDelayMin [get_ports lPlSpiLe] -clock_fall +# Then set a false path only on the async reset flops. +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMosiIndex[*]|*}] +set_false_path -from [get_ports {lPlSpiLe}] -to [get_pins {lPlMisoIndex[*]|*}] + +# Constrain MISO as snugly as possible through the CPLD without making the tools work +# too hard. At a 200 ns period, this sets the clock-to-out for the CPLD at [10, 65]ns. +# Math for Max = T_clk/2 - 35 = 200/2 - 35 = 65 ns. +set PlSdoOutputDelayMax 35 +set PlSdoOutputDelayMin -10 + +set_output_delay -clock PlClk -max $PlSdoOutputDelayMax [get_ports lPlSpiSdo] +set_output_delay -clock PlClk -min $PlSdoOutputDelayMin [get_ports lPlSpiSdo] + + + +## Passthrough Constraints ############################################################## +# - LMK SYNC +# - PlClk/PsClk passthrough +# - SDI passthrough for both +# - SDO return mux passthrough for both +# - Cs_n passthrough for both + +# LMK Sync Passthrough: constrain min and max delays for output +set_max_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 17 +set_min_delay -from [get_ports {aPlSpiAddr[2]}] -to [get_ports {aLmkSync}] 2 + +# SPI Passthroughs: constrain min and max delays for outputs and inputs. +# Since the SDI ports have input delays pre-defined above, we have to remove those from +# the delay analysis here by adding the input delay to the constraint. +# Similarly, for the SDO pins add the output delay to the constraint. +set SpiMaxDelay 25 +set SpiMinDelay 5 + +# PS +set_max_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aDacDin aLmkSpiSdio}] [expr $PsSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSync_n aLmkSpiCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aDacSck aLmkSpiSck}] $SpiMinDelay +set_max_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMaxDelay + $PsSdoOutputDelayMax] +set_min_delay -from [get_ports {aLmkClkinSel*}] [expr $SpiMinDelay + $PsSdoOutputDelayMin] + +# PL +set_max_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMax + $SpiMaxDelay] +set_min_delay -to [get_ports {aRxLoDin aTxLoDin}] [expr $PlSdiInputDelayMin + $SpiMinDelay] +set_max_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoCs_n aTxLoCs_n}] $SpiMinDelay +set_max_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMaxDelay +set_min_delay -to [get_ports {aRxLoSck aTxLoSck}] $SpiMinDelay +set_max_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMaxDelay + $PlSdoOutputDelayMax] +set_min_delay -from [get_ports {aTxLoMuxOut aRxLoMuxOut}] [expr $SpiMinDelay + $PlSdoOutputDelayMin] + + + +## Async Inputs ######################################################################### +# aLmkStatus2 aRxLoLockDetect aTxLoLockDetect +set_false_path -from [get_ports {aRxLoLockDetect}] +set_false_path -from [get_ports {aTxLoLockDetect}] + + + +## Async Outputs ######################################################################## +# aMkReset_n aVcxoCtrl +set_false_path -to [get_ports {aMkReset_n}] +set_false_path -to [get_ports {aVcxoCtrl}] + + + +## Sync Front End Outputs ############################################################### +# All we need to do here is constrain for maximum path delay from the aAtr(Rx|Tx)(1|2) +# control bits toggling to the outputs for aCh1* and aCh2* toggling. Just in case the +# user attempts to write the ATR while it's in use, we also constrain from the flops +# to the pins... which covers all paths... so just to -to option is needed. +set_max_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 40 +set_min_delay -to [get_ports {aCh1* aCh2* aMk*x*En}] 5 + +# We don't care about the LED timing whatsoever. Let's not have them clogging up our +# precious timing paths. +set_false_path -to [get_ports {aCh*Led*}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf new file mode 100644 index 000000000..e16aaf0af --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "16.1" +DATE = "14:51:27 February 24, 2017" + +# Revisions + +PROJECT_REVISION = "TopCpld" diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf new file mode 100644 index 000000000..64238c87a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.qsf @@ -0,0 +1,313 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 14:51:27 February 24, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M570ZF256I5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:51:27 FEBRUARY 24, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name SDC_FILE Timing.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + +set_location_assignment PIN_C3 -to aCh2RxSw4[0] +set_location_assignment PIN_C2 -to aCh2TxPaEn +set_location_assignment PIN_D3 -to aCh2RxSw6[0] +set_location_assignment PIN_D1 -to aCh2RxSw4[1] +set_location_assignment PIN_D2 -to aCh2TxSw3 +set_location_assignment PIN_E1 -to aCh2RxSw4[2] +set_location_assignment PIN_E4 -to aCh2RxSw7[1] +set_location_assignment PIN_F2 -to aCh2RxSw6[1] +set_location_assignment PIN_E3 -to aCh2RxSw7[0] +set_location_assignment PIN_F1 -to aCh2RxSw5[0] +set_location_assignment PIN_E2 -to aCh2RxSw5[1] +set_location_assignment PIN_G2 -to aCh2RxSw5[3] +set_location_assignment PIN_F3 -to aCh2TxSw4[0] +set_location_assignment PIN_G1 -to aCh2RxSw6[2] +set_location_assignment PIN_G3 -to aCh2TxSw4[1] +set_location_assignment PIN_H2 -to aCh2TxAmpEn +set_location_assignment PIN_H1 -to aCh2RxSw5[2] +set_location_assignment PIN_J1 -to aCh2TxMixerEn +set_location_assignment PIN_H5 -to aLoSpiSync +set_location_assignment PIN_J2 -to aCh2RxMixerEn +#set_location_assignment PIN_L3 -to aLmkSpiSdio +set_location_assignment PIN_K1 -to aCh2TxSw5[1] +set_location_assignment PIN_K2 -to aCh2TxSw5[0] +set_location_assignment PIN_M2 -to aLmkSpiSdio +set_location_assignment PIN_L1 -to aCh2RxSw8[0] +set_location_assignment PIN_M3 -to lPlSpiSdi +set_location_assignment PIN_L2 -to aCh2RxSw8[1] +set_location_assignment PIN_M1 -to aCh2RxAmpEn +set_location_assignment PIN_N2 -to aLmkSpiSck +set_location_assignment PIN_N1 -to aLmkSpiCs_n +set_location_assignment PIN_N3 -to PlSpiSck +# set_location_assignment PIN_P2 -to lPlSpiLe +set_location_assignment PIN_R3 -to aMkReset_n +set_location_assignment PIN_R1 -to lPlSpiLe +set_location_assignment PIN_T2 -to aLmkSync +set_location_assignment PIN_R4 -to aVcxoCtrl +set_location_assignment PIN_T4 -to aDacDin +set_location_assignment PIN_T5 -to aDacSync_n +set_location_assignment PIN_R6 -to aPlSpiAddr[2] +set_location_assignment PIN_R5 -to aDacSck +set_location_assignment PIN_T6 -to aPlSpiAddr[1] +set_location_assignment PIN_R7 -to aLmkClkinSel[0] +set_location_assignment PIN_T7 -to lPlSpiSdo +set_location_assignment PIN_P8 -to sPsSpiLe +set_location_assignment PIN_R8 -to aPsSpiAddr[1] +set_location_assignment PIN_P9 -to aPlSpiAddr[0] +set_location_assignment PIN_T8 -to PsSpiSck +set_location_assignment PIN_T9 -to aPsSpiAddr[0] +set_location_assignment PIN_R9 -to sPsSpiSdi +set_location_assignment PIN_P10 -to aAtrRx1 +set_location_assignment PIN_T10 -to sPsSpiSdo +set_location_assignment PIN_P11 -to aAtrTx2 +set_location_assignment PIN_R10 -to aRxLoLockDetect +set_location_assignment PIN_R12 -to aRxLoSck +set_location_assignment PIN_T11 -to aTxLoLockDetect +set_location_assignment PIN_P12 -to aAtrRx2 +set_location_assignment PIN_R11 -to aRxLoDin +set_location_assignment PIN_T12 -to aRxLoCs_n +set_location_assignment PIN_R13 -to aTxLoDin +set_location_assignment PIN_T13 -to aRxLoMuxOut +set_location_assignment PIN_P13 -to aAtrTx1 +set_location_assignment PIN_T15 -to aTxLoSck +set_location_assignment PIN_R14 -to aTxLoCs_n +set_location_assignment PIN_R16 -to aTxLoMuxOut +set_location_assignment PIN_P14 -to aMkTx1En +set_location_assignment PIN_N15 -to aMkRx2En +set_location_assignment PIN_P15 -to aMkRx1En +set_location_assignment PIN_N16 -to aMkTx2En +set_location_assignment PIN_K15 -to aCh1TxSw5[1] +set_location_assignment PIN_L14 -to aCh1RxMixerEn +set_location_assignment PIN_K16 -to aCh1TxMixerEn +set_location_assignment PIN_K14 -to aCh1RxSw8[0] +set_location_assignment PIN_J15 -to aCh1TxAmpEn +set_location_assignment PIN_J14 -to aCh1RxSw8[1] +set_location_assignment PIN_J16 -to aCh1TxSw5[0] +set_location_assignment PIN_H14 -to aCh1RxAmpEn +set_location_assignment PIN_H16 -to aCh1TxSw4[0] +set_location_assignment PIN_G14 -to aCh1TxSw4[1] +set_location_assignment PIN_H15 -to aCh1RxSw5[1] +set_location_assignment PIN_F14 -to aCh1RxSw7[1] +set_location_assignment PIN_G16 -to aCh1RxSw5[0] +set_location_assignment PIN_G15 -to aCh1RxSw4[0] +set_location_assignment PIN_E14 -to aCh1RxSw6[1] +set_location_assignment PIN_F16 -to aCh1RxSw2[1] +set_location_assignment PIN_E13 -to aCh1RxSw7[0] +set_location_assignment PIN_F15 -to aCh1RxSw2[0] +set_location_assignment PIN_D14 -to aCh1RxSw6[2] +set_location_assignment PIN_E16 -to aCh1RxSw6[0] +set_location_assignment PIN_E15 -to aCh1TxSw3 +set_location_assignment PIN_C15 -to aCh1RxSw5[2] +set_location_assignment PIN_D16 -to aCh1TxPaEn +set_location_assignment PIN_C14 -to aCh1RxSw4[1] +set_location_assignment PIN_D15 -to aCh1RxSw5[3] +set_location_assignment PIN_B14 -to aCh1TxSw2[3] +set_location_assignment PIN_B16 -to aCh1RxLna2En +set_location_assignment PIN_C13 -to aCh1RxSw4[2] +set_location_assignment PIN_A15 -to aCh1TxSw2[2] +set_location_assignment PIN_B13 -to aCh1TxSw2[1] +set_location_assignment PIN_A13 -to aCh1TxSw2[0] +set_location_assignment PIN_C12 -to aCh1RxSw1[0] +set_location_assignment PIN_B12 -to aCh1TxSw1[0] +set_location_assignment PIN_D12 -to aCh1RxSw1[1] +set_location_assignment PIN_A12 -to aCh1TxSw1[1] +set_location_assignment PIN_C11 -to aCh1LedTx +set_location_assignment PIN_B11 -to aCh1RxLna1En +set_location_assignment PIN_D11 -to aCh2RxSw1[1] +set_location_assignment PIN_A11 -to aCh1RxSw3[2] +set_location_assignment PIN_C10 -to aCh1LedRx +set_location_assignment PIN_B10 -to aCh1RxSw3[1] +set_location_assignment PIN_C9 -to aCh1LedRx2 +set_location_assignment PIN_A10 -to aCh1RxSw3[0] +set_location_assignment PIN_C8 -to aCh2LedRx2 +set_location_assignment PIN_B9 -to aCh1SwTrx[1] +set_location_assignment PIN_A9 -to aCh1SwTrx[0] +set_location_assignment PIN_A8 -to aCh2SwTrx[0] +set_location_assignment PIN_C7 -to aCh2RxSw3[0] +set_location_assignment PIN_B8 -to aCh2SwTrx[1] +set_location_assignment PIN_C6 -to aCh2LedRx +set_location_assignment PIN_A7 -to aCh2RxSw3[1] +set_location_assignment PIN_B5 -to aCh2TxSw1[0] +set_location_assignment PIN_C5 -to aCh2RxSw1[0] +set_location_assignment PIN_A6 -to aCh2TxSw1[1] +set_location_assignment PIN_D5 -to aCh2LedTx +set_location_assignment PIN_B6 -to aCh2RxSw3[2] +set_location_assignment PIN_B4 -to aCh2RxLna2En +set_location_assignment PIN_A5 -to aCh2RxLna1En +set_location_assignment PIN_C4 -to aCh2RxSw2[0] +set_location_assignment PIN_A4 -to aCh2TxSw2[1] +set_location_assignment PIN_D4 -to aCh2RxSw2[1] +set_location_assignment PIN_A2 -to aCh2TxSw2[3] +set_location_assignment PIN_B3 -to aCh2TxSw2[0] +set_location_assignment PIN_B1 -to aCh2TxSw2[2] + +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name GENERATE_JAM_FILE ON +set_global_assignment -name GENERATE_JBC_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSdio +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSpiCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkReset_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aLmkSync +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aVcxoCtrl +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSync_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aDacSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to lPlSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to sPsSpiSdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aRxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoDin +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoSck +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aTxLoCs_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkRx1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aMkTx2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxMixerEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw8[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxAmpEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw7[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw6[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxPaEn +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw5[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw4[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh1SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2SwTrx[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedRx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw1[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw1[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2LedTx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw3[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna2En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxLna1En +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2RxSw2[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to aCh2TxSw2[2] +set_global_assignment -name SEED 11 +set_global_assignment -name VHDL_FILE PkgMgCpld.vhd +set_global_assignment -name VHDL_FILE PkgSetup.vhd +set_global_assignment -name VHDL_FILE TopCpld.vhd +set_global_assignment -name TOP_LEVEL_ENTITY TopCpld diff --git a/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd new file mode 100644 index 000000000..4e3488f54 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/cpld/TopCpld.vhd @@ -0,0 +1,1228 @@ +------------------------------------------------------------------------------- +-- +-- File: TopCpld.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 24 October 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Top level file for the Magnesium CPLD. +-- +-- This file instantiates two SPI slave ports. One slave port comes from the PS +-- of the motherboard Zynq. It has three slave select pins, mapped as follows: +-- sPlsSpiLe = CPLD Internal Registers +-- aPsSpiAddr(0) = LMK Endpoint +-- aPsSpiAddr(1) = Phase DAC Endpoint +-- +-- The other slave port comes from the PL of the motherboard Zynq. It also has +-- three slave select pins: +-- lPlSpiLe = CPLD Internal Registers +-- aPlSpiAddr(0) = TX Lowband LO +-- aPlSpiAddr(1) = RX Lowband LO +-- +-- The final address line for the PL slave is used as a passthrough for the LMK +-- SYNC pin. +-- +-- +-- For either SPI interface, the CPLD has internal registers that can be addressed +-- whenever the appropriate slave select is driven asserted. These register groups +-- are completely independent from one another, meaning the PS SPI interface cannot +-- access the PL registers, and vice-versa. +-- +-- See the register interface XML at the bottom of this file for details on how +-- each SPI port is expected to be driven, and for the register maps for the PS +-- and PL slaves. +-- +-- +-- BUMPING THE REVISION: +-- In PkgSetup the kMinorRev and kMajorRev are defined. Whenever a change +-- is made to the CPLD, no matter how small, bump the kMinorRev value. If this change +-- breaks compatibility with current HW or SW drivers, increment the kMajorRev value +-- and reset the kMinorRev to zero. Similarly, there is a constant to define the build +-- code, kBuildCode. Currently this is simply the year, month, day, and hour the CPLD is +-- built, but could be user-definable. +-- +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +library work; + use work.PkgMgCpld.all; + use work.PkgSetup.all; + +entity TopCpld is + port( + + -- SPI Port Incoming from FPGA -- + PlSpiSck : in std_logic; + lPlSpiSdi : in std_logic; + lPlSpiSdo : out std_logic; + lPlSpiLe : in std_logic; + aPlSpiAddr : in std_logic_vector(2 downto 0); + + -- SPI Port Incoming from PS -- + PsSpiSck : in std_logic; + sPsSpiSdi : in std_logic; + sPsSpiSdo : out std_logic; + sPsSpiLe : in std_logic; + aPsSpiAddr : in std_logic_vector(1 downto 0); + + -- ATR bits from FPGA -- + aAtrRx1 : in std_logic; + aAtrRx2 : in std_logic; + aAtrTx1 : in std_logic; + aAtrTx2 : in std_logic; + + -- Ch 1 TX (15 bits) -- + aCh1LedTx : out std_logic; + + aCh1TxPaEn : out std_logic; + aCh1TxAmpEn : out std_logic; + aCh1TxMixerEn : out std_logic; + + aCh1TxSw1 : out std_logic_vector(1 downto 0); + aCh1TxSw2 : out std_logic_vector(3 downto 0); + aCh1TxSw3 : out std_logic; + aCh1TxSw4 : out std_logic_vector(1 downto 0); + aCh1TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 1 RX (29 bits) -- + aCh1LedRx : out std_logic; + aCh1LedRx2 : out std_logic; + + aCh1RxAmpEn : out std_logic; + aCh1RxMixerEn : out std_logic; + aCh1RxLna1En : out std_logic; + aCh1RxLna2En : out std_logic; + aCh1SwTrx : out std_logic_vector(1 downto 0); + + aCh1RxSw1 : out std_logic_vector(1 downto 0); + aCh1RxSw2 : out std_logic_vector(1 downto 0); + aCh1RxSw3 : out std_logic_vector(2 downto 0); + aCh1RxSw4 : out std_logic_vector(2 downto 0); + aCh1RxSw5 : out std_logic_vector(3 downto 0); + aCh1RxSw6 : out std_logic_vector(2 downto 0); + aCh1RxSw7 : out std_logic_vector(1 downto 0); + aCh1RxSw8 : out std_logic_vector(1 downto 0); + + -- Ch 2 TX -- + aCh2LedTx : out std_logic; + + aCh2TxPaEn : out std_logic; + aCh2TxAmpEn : out std_logic; + aCh2TxMixerEn : out std_logic; + + aCh2TxSw1 : out std_logic_vector(1 downto 0); + aCh2TxSw2 : out std_logic_vector(3 downto 0); + aCh2TxSw3 : out std_logic; + aCh2TxSw4 : out std_logic_vector(1 downto 0); + aCh2TxSw5 : out std_logic_vector(1 downto 0); + + -- Ch 2 RX -- + aCh2LedRx : out std_logic; + aCh2LedRx2 : out std_logic; + + aCh2RxAmpEn : out std_logic; + aCh2RxMixerEn : out std_logic; + aCh2RxLna1En : out std_logic; + aCh2RxLna2En : out std_logic; + aCh2SwTrx : out std_logic_vector(1 downto 0); + + aCh2RxSw1 : out std_logic_vector(1 downto 0); + aCh2RxSw2 : out std_logic_vector(1 downto 0); + aCh2RxSw3 : out std_logic_vector(2 downto 0); + aCh2RxSw4 : out std_logic_vector(2 downto 0); + aCh2RxSw5 : out std_logic_vector(3 downto 0); + aCh2RxSw6 : out std_logic_vector(2 downto 0); + aCh2RxSw7 : out std_logic_vector(1 downto 0); + aCh2RxSw8 : out std_logic_vector(1 downto 0); + + -- LMK -- + aLmkSpiSdio : out std_logic; + aLmkSpiSck : out std_logic; + aLmkSpiCs_n : out std_logic; + aLmkClkinSel : in std_logic_vector(0 downto 0); -- SDO + aLmkSync : out std_logic; -- direct connect to aPlSpiAddr(2) + + -- Phase DAC -- + aDacDin : out std_logic; + aDacSync_n : out std_logic; + aDacSck : out std_logic; + aVcxoCtrl : out std_logic; -- @PS-REG-WR + + -- RX and TX LOs -- (timed) + aLoSpiSync : in std_logic; -- Clock! (unused atm, only for reclocking + aRxLoSck : out std_logic; -- the SPI bus if needed for sync) + aRxLoDin : out std_logic; + aRxLoCs_n : out std_logic; + aRxLoMuxOut : in std_logic; + aRxLoLockDetect : in std_logic; -- @PS-REG-RD + aTxLoSck : out std_logic; + aTxLoDin : out std_logic; + aTxLoCs_n : out std_logic; + aTxLoMuxOut : in std_logic; + aTxLoLockDetect : in std_logic; -- @PS-REG-RD + + -- Mykonos Interface -- + aMkReset_n : out std_logic; -- @PS-REG-WR + aMkRx1En : out std_logic; + aMkRx2En : out std_logic; + aMkTx1En : out std_logic; + aMkTx2En : out std_logic + + ); +end TopCpld; + + +architecture RTL of TopCpld is + + -- PS MOSI + signal sCpldPsSpiActive : boolean; + signal sPsMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMosiBuffer : InterfaceData_t := (others => '0'); + signal sPsRd : boolean := false; + signal sPsRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PS MISO + signal sPsCpldMiso : std_logic; + signal sPsMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal sPsMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PS Register Signals + signal aRxLoLockDetect_ms, sRxLoLockDetect, + aTxLoLockDetect_ms, sTxLoLockDetect : std_logic := '0'; + signal sReset : boolean := false; + signal sScratchVal : InterfaceData_t := (others => '0'); + signal sVcxoControl : std_logic := '1'; + signal sMykonosReset : std_logic := '0'; + + -- PL MOSI + signal lCpldPlSpiActive : boolean; + signal lPlMosiIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMosiBuffer : InterfaceData_t := (others => '0'); + signal lPlRd : boolean := false; + signal lPlRegAddr : unsigned(kAddrWidth-1 downto 0) := (others => '0'); + + -- PL MISO + signal lPlCpldMiso : std_logic; + signal lPlMisoIndex : unsigned(integer(ceil(log2(real(kTotalWidth)))) downto 0); + signal lPlMisoBuffer : std_logic_vector(kTotalWidth-1 downto 0); + + -- PL Register Signals + signal lScratchVal : InterfaceData_t := (others => '0'); + signal lReset : boolean := false; + + -- See PkgSetup for each Default definition. + signal lTxCh1IdleReg : InterfaceData_t := kTxChDefault; + signal lTxCh2IdleReg : InterfaceData_t := kTxChDefault; + + signal lTxCh1TxOnReg : InterfaceData_t := kTxChDefaultRun; + signal lTxCh2TxOnReg : InterfaceData_t := kTxChDefaultRun; + + signal lRxCh1_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh1_1IdleReg : InterfaceData_t := kRxChDefault1; + signal lRxCh2_0IdleReg : InterfaceData_t := kRxChDefault0; + signal lRxCh2_1IdleReg : InterfaceData_t := kRxChDefault1; + + signal lRxCh1_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh1_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + signal lRxCh2_0RxOnReg : InterfaceData_t := kRxChDefault0Run; + signal lRxCh2_1RxOnReg : InterfaceData_t := kRxChDefault1Run; + + signal lTxCh1 : InterfaceData_t; + signal lTxCh2 : InterfaceData_t; + signal lRxCh1_0 : InterfaceData_t; + signal lRxCh1_1 : InterfaceData_t; + signal lRxCh2_0 : InterfaceData_t; + signal lRxCh2_1 : InterfaceData_t; + +begin + + + -- Direct Pass-through Pins : --------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + -- LMK SYNC assignment for direct passthrough to LMK from SPI Addr line. + aLmkSync <= aPlSpiAddr(2); + + + + -- PS SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PsMosiIndex - generate pointer for MOSI Buffer + -- 2) PsMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PsMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PsMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PsMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PS SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PS. + sCpldPsSpiActive <= sPsSpiLe = '0'; + aLmkSpiCs_n <= aPsSpiAddr(0); + aDacSync_n <= aPsSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LMK and DAC. + aLmkSpiSck <= PsSpiSck; + aLmkSpiSdio <= sPsSpiSdi; + aDacSck <= PsSpiSck; + aDacDin <= sPsSpiSdi; + + -- Output mux for data back to the FPGA (PS core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + sPsSpiSdo <= aLmkClkinSel(0) when aPsSpiAddr(0) = '0' else + sPsCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMosiIndex : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMosiIndex <= (others => '0'); + elsif rising_edge(PsSpiSck) then + sPsMosiIndex <= sPsMosiIndex + 1; + end if; + end process PsMosiIndex; + + + -- Shift in SDI (MOSI) data from the PS on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PsMosiBuffer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + if sReset then + sPsMosiBuffer <= (others => '0'); + else + if sCpldPsSpiActive then + sPsMosiBuffer <= sPsMosiBuffer(sPsMosiBuffer'high-1 downto 0) & sPsSpiSdi; -- left shift + end if; + end if; + end if; + end process PsMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PS SPI clock. + PsMosiProcessing : process(PsSpiSck) + begin + if falling_edge(PsSpiSck) then + if sReset then + -- sReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + sReset <= false; + sScratchVal <= (others => '0'); + sVcxoControl <= '1'; + sMykonosReset <= '0'; + sPsRd <= false; + sPsRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (sPsMosiIndex = (kRdWtWidth)) then + sPsRd <= sPsMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (sPsMosiIndex = (kAddrWidth + kRdWtWidth)) then + sPsRegAddr <= unsigned(sPsMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (sPsMosiIndex = kTotalWidth) and (not sPsRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (sPsRegAddr = kScratch) then + sScratchVal <= sPsMosiBuffer; + end if; + + if (sPsRegAddr = kCpldControl) then + sReset <= sPsMosiBuffer(kCpldReset) = '1'; + end if; + + if (sPsRegAddr = kLmkControl) then + sVcxoControl <= sPsMosiBuffer(kVcxoControl); + end if; + + if (sPsRegAddr = kMykonosControl) then + sMykonosReset <= sPsMosiBuffer(kMykonosReset); + end if; + + end if; + end if; + end if; + end process PsMosiProcessing; + + + -- Send MISO back to FPGA (PS) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PsSpiSck will not start toggling + -- until long after the asynchronous reset (sCpldPsSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PsMisoBuffer : process(PsSpiSck, sCpldPsSpiActive) + begin + if not sCpldPsSpiActive then + sPsMisoIndex <= to_unsigned(kTotalWidth-1, sPsMisoIndex'length); + elsif falling_edge(PsSpiSck) then + if sPsMisoIndex > 0 then + sPsMisoIndex <= sPsMisoIndex - 1; + end if; + end if; + end process PsMisoBuffer; + + sPsCpldMiso <= sPsMisoBuffer(to_integer(sPsMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PsMisoBufferMux : process(sPsRegAddr, sScratchVal, sVcxoControl, + sTxLoLockDetect, sRxLoLockDetect, sMykonosReset) + begin + sPsMisoBuffer <= (others => '0'); + case to_integer(sPsRegAddr) is + when kSignatureReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kSignature; + when kMinorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMinorRev; + when kMajorRevReg => sPsMisoBuffer(kDataWidth-1 downto 0) <= kMajorRev; + when kBuildCodeLSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(15 downto 0); + when kBuildCodeMSB => sPsMisoBuffer(kDataWidth-1 downto 0) <= kBuildCode(31 downto 16); + when kScratch => sPsMisoBuffer(kDataWidth-1 downto 0) <= sScratchVal; + when kLmkControl => sPsMisoBuffer(kVcxoControl) <= sVcxoControl; + when kLoStatus => sPsMisoBuffer(kTxLoLockDetect) <= sTxLoLockDetect; + sPsMisoBuffer(kRxLoLockDetect) <= sRxLoLockDetect; + when kMykonosControl => sPsMisoBuffer(kMykonosReset) <= sMykonosReset; + when others => sPsMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PsMisoBufferMux; + + + -- Double-synchronize the async inputs to the PS clock domain. However, this clock + -- isn't toggling all the time. Whenever it is toggling, let's capture these bits. + StatusSynchronizer : process(PsSpiSck) + begin + if rising_edge(PsSpiSck) then + aRxLoLockDetect_ms <= aRxLoLockDetect; + sRxLoLockDetect <= aRxLoLockDetect_ms; + + aTxLoLockDetect_ms <= aTxLoLockDetect; + sTxLoLockDetect <= aTxLoLockDetect_ms; + end if; + end process; + + + -- PS SPI locals to outputs. + aVcxoCtrl <= sVcxoControl; + aMkReset_n <= not sMykonosReset; + + + + -- PL SPI Interface : ----------------------------------------------------------------- + -- Composed of a few modules: + -- 1) PlMosiIndex - generate pointer for MOSI Buffer + -- 2) PlMosiBuffer - actually implement the buffer, only when the CPLD is targeted. + -- 3) PlMosiProcessing - process the MOSI data: sort into Rd/!Wt, Address, and Data. + -- This process works on the falling edge of the clock to register the pieces + -- of the MOSI packet as they are complete. The final falling edge registers + -- the data into the individual registers, so it is critical that the clock idle + -- LOW after the transaction is complete such that this final falling edge occurs. + -- 4) PlMisoBuffer - generate pointer for the MISO buffer. The buffer itself is + -- completely async. + -- 5) PlMisoBufferMux - Mux all the register data back into the MISO buffer. + -- 6) StatusSynchronizer - double-synchronizers for status bits from the LMK and LOs. + -- ------------------------------------------------------------------------------------ + + -- Decode the PL SPI Address bits... which are actually going to be used as individual + -- chip selects coming from the PL. + lCpldPlSpiActive <= lPlSpiLe = '0'; + aTxLoCs_n <= aPlSpiAddr(0); + aRxLoCs_n <= aPlSpiAddr(1); + + -- Assign the remainder of the SPI lines to the LOs. + aRxLoSck <= PlSpiSck; + aRxLoDin <= lPlSpiSdi; + aTxLoSck <= PlSpiSck; + aTxLoDin <= lPlSpiSdi; + + -- Output mux for data back to the FPGA (PL core). The LMK and CPLD are the only + -- endpoints that have readback enabled. + lPlSpiSdo <= aTxLoMuxOut when aPlSpiAddr(0) = '0' else + aRxLoMuxOut when aPlSpiAddr(1) = '0' else + lPlCpldMiso; + + + + -- Use the LE signal (Cs_n) as the asynchronous reset to the shift register counter. + -- LE will hold the counter in reset until this endpoint is targeted, when it will + -- release the reset (long before the clock toggles) and allow the shift operation + -- to begin. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMosiIndex : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMosiIndex <= (others => '0'); + elsif rising_edge(PlSpiSck) then + lPlMosiIndex <= lPlMosiIndex + 1; + end if; + end process PlMosiIndex; + + + -- Shift in SDI (MOSI) data from the PL on the rising edge of the clock. Only use + -- synchronous resets from here on out. + PlMosiBuffer : process(PlSpiSck) + begin + if rising_edge(PlSpiSck) then + if lReset then + lPlMosiBuffer <= (others => '0'); + else + if lCpldPlSpiActive then + lPlMosiBuffer <= lPlMosiBuffer(lPlMosiBuffer'high-1 downto 0) & lPlSpiSdi; -- left shift + end if; + end if; + end if; + end process PlMosiBuffer; + + + -- As portions of the command and data packets become available, register them here + -- using the falling edge of the PL SPI clock. + PlMosiProcessing : process(PlSpiSck) + begin + if falling_edge(PlSpiSck) then + if lReset then + -- lReset is intentionally self-clearing. It clears on the first falling edge of + -- the next SPI transaction after it is set. Logic on the first rising edge of + -- that next transaction is therefore held in reset. This will not matter + -- as long as SW follows the recommended reset procedure (writing a '1' to reset + -- then writing a '0'), since the first bit of the transaction is '0' for a + -- write operation. + lReset <= false; + lScratchVal <= (others => '0'); + lTxCh1IdleReg <= kTxChDefault; + lTxCh1TxOnReg <= kTxChDefault; + lTxCh2IdleReg <= kTxChDefault; + lTxCh2TxOnReg <= kTxChDefault; + lRxCh1_0IdleReg <= kRxChDefault0; + lRxCh1_1IdleReg <= kRxChDefault1; + lRxCh1_0RxOnReg <= kRxChDefault0; + lRxCh1_1RxOnReg <= kRxChDefault1; + lRxCh2_0IdleReg <= kRxChDefault0; + lRxCh2_1IdleReg <= kRxChDefault1; + lRxCh2_0RxOnReg <= kRxChDefault0; + lRxCh2_1RxOnReg <= kRxChDefault1; + lPlRd <= false; + lPlRegAddr <= (others => '0'); + else + -- After the first bit is captured, we can determine if it is a write or read. + if (lPlMosiIndex = (kRdWtWidth)) then + lPlRd <= lPlMosiBuffer(0) = '1'; + end if; + + -- After the entire command word is captured, the address is ready for capture. + if (lPlMosiIndex = (kAddrWidth + kRdWtWidth)) then + lPlRegAddr <= unsigned(lPlMosiBuffer(kAddrWidth - 1 downto 0)); + end if; + + -- And finally after the entire transaction is complete we can save off the data + -- on the final falling edge of the SPI clock into it's appropriate place, based + -- off the address value captured above. + if (lPlMosiIndex = kTotalWidth) and (not lPlRd) then + + -- ---------------------------------------------------------------------------- + -- Assign writable register values here! -------------------------------------- + -- ---------------------------------------------------------------------------- + if (lPlRegAddr = kPlScratch) then + lScratchVal <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kPlCpldControl) then + lReset <= lPlMosiBuffer(kCpldReset) = '1'; + end if; + + if (lPlRegAddr = kTxCh1_Idle) then + lTxCh1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh1_TxOn) then + lTxCh1TxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_Idle) then + lTxCh2IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kTxCh2_TxOn) then + lTxCh2TxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh1_0_Idle) then + lRxCh1_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_Idle) then + lRxCh1_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_0_RxOn) then + lRxCh1_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh1_1_RxOn) then + lRxCh1_1RxOnReg <= lPlMosiBuffer; + end if; + + if (lPlRegAddr = kRxCh2_0_Idle) then + lRxCh2_0IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_Idle) then + lRxCh2_1IdleReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_0_RxOn) then + lRxCh2_0RxOnReg <= lPlMosiBuffer; + end if; + if (lPlRegAddr = kRxCh2_1_RxOn) then + lRxCh2_1RxOnReg <= lPlMosiBuffer; + end if; + + end if; + end if; + end if; + end process PlMosiProcessing; + + + -- Send MISO back to FPGA (PL) on the falling edge as well. + -- + -- !!! SAFE COUNTER STARTUP!!! + -- This counter starts safely from reset because the PlSpiSck will not start toggling + -- until long after the asynchronous reset (lCpldPlSpiActive) de-asserts. Similarly, + -- the reset will only assert long after the last clock edge is received. + PlMisoBuffer : process(PlSpiSck, lCpldPlSpiActive) + begin + if not lCpldPlSpiActive then + lPlMisoIndex <= to_unsigned(kTotalWidth-1, lPlMisoIndex'length); + elsif falling_edge(PlSpiSck) then + if lPlMisoIndex > 0 then + lPlMisoIndex <= lPlMisoIndex - 1; + end if; + end if; + end process PlMisoBuffer; + + lPlCpldMiso <= lPlMisoBuffer(to_integer(lPlMisoIndex)); + + + -- Mux the register data from the CPLD back to the FPGA. + PlMisoBufferMux : process(lPlRegAddr, lScratchVal, lTxCh1IdleReg, lTxCh1TxOnReg, + lTxCh2IdleReg, lTxCh2TxOnReg, lRxCh1_0IdleReg, + lRxCh1_1IdleReg, lRxCh1_0RxOnReg, lRxCh1_1RxOnReg, + lRxCh2_0IdleReg, lRxCh2_1IdleReg, lRxCh2_0RxOnReg, + lRxCh2_1RxOnReg) + begin + lPlMisoBuffer <= (others => '0'); + case to_integer(lPlRegAddr) is + when kPlScratch => lPlMisoBuffer(kDataWidth-1 downto 0) <= lScratchVal; + when kTxCh1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1IdleReg; + when kTxCh1_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh1TxOnReg; + when kTxCh2_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2IdleReg; + when kTxCh2_TxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lTxCh2TxOnReg; + when kRxCh1_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0IdleReg; + when kRxCh1_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1IdleReg; + when kRxCh1_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_0RxOnReg; + when kRxCh1_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh1_1RxOnReg; + when kRxCh2_0_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0IdleReg; + when kRxCh2_1_Idle => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1IdleReg; + when kRxCh2_0_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_0RxOnReg; + when kRxCh2_1_RxOn => lPlMisoBuffer(kDataWidth-1 downto 0) <= lRxCh2_1RxOnReg; + when others => lPlMisoBuffer(kDataWidth-1 downto 0) <= (others => '0'); + end case; + end process PlMisoBufferMux; + + + -- Use the ATR bits to mux the output values. + lTxCh1 <= lTxCh1IdleReg when aAtrTx1 = '0' else lTxCh1TxOnReg; + lTxCh2 <= lTxCh2IdleReg when aAtrTx2 = '0' else lTxCh2TxOnReg; + + lRxCh1_0 <= lRxCh1_0IdleReg when aAtrRx1 = '0' else lRxCh1_0RxOnReg; + lRxCh1_1 <= lRxCh1_1IdleReg when aAtrRx1 = '0' else lRxCh1_1RxOnReg; + lRxCh2_0 <= lRxCh2_0IdleReg when aAtrRx2 = '0' else lRxCh2_0RxOnReg; + lRxCh2_1 <= lRxCh2_1IdleReg when aAtrRx2 = '0' else lRxCh2_1RxOnReg; + + -- PL SPI locals to outputs. All the register values are set for Channel 1. Channel 2 + -- values are mixed around here in order for the same register settings to work for + -- Channel 1 and Channel 2, even though Ch2 switch configuration is different in HW. + aCh1LedTx <= lTxCh1(kCh1TxLed); + aCh1TxPaEn <= lTxCh1(kCh1TxPaEn); + aCh1TxAmpEn <= lTxCh1(kCh1TxAmpEn); + aCh1TxMixerEn <= lTxCh1(kCh1TxMixerEn); + aCh1TxSw1 <= lTxCh1(kCh1TxSw1Msb downto kCh1TxSw1); + aCh1TxSw2 <= lTxCh1(kCh1TxSw2Msb downto kCh1TxSw2); + aCh1TxSw3 <= lTxCh1(kCh1TxSw3); + aCh1TxSw4 <= "01" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh1TxSw5 <= "10" when lTxCh1(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh1SwTrx <= lTxCh1(kCh1SwTrxMsb downto kCh1SwTrx); + aMkTx1En <= lTxCh1(kCh1MykEnTx); + + aCh2LedTx <= lTxCh2(kCh1TxLed); + aCh2TxPaEn <= lTxCh2(kCh1TxPaEn); + aCh2TxAmpEn <= lTxCh2(kCh1TxAmpEn); + aCh2TxMixerEn <= lTxCh2(kCh1TxMixerEn); + aCh2TxSw1 <= lTxCh2(kCh1TxSw1Msb downto kCh1TxSw1); + aCh2TxSw2 <= Tx2Switch2Mod(lTxCh2(kCh1TxSw2Msb downto kCh1TxSw2)); + aCh2TxSw3 <= lTxCh2(kCh1TxSw3); + aCh2TxSw4 <= "10" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "01"; + aCh2TxSw5 <= "01" when lTxCh2(kCh1TxLowbandMixerPathSelect) = '1' else "10"; + aCh2SwTrx <= Tx2TrxMod(lTxCh2(kCh1SwTrxMsb downto kCh1SwTrx)); + aMkTx2En <= lTxCh2(kCh1MykEnTx); + + aCh1RxSw1 <= lRxCh1_0(kCh1RxSw1Msb downto kCh1RxSw1); + aCh1RxSw2 <= lRxCh1_0(kCh1RxSw2Msb downto kCh1RxSw2); + aCh1RxSw3 <= lRxCh1_0(kCh1RxSw3Msb downto kCh1RxSw3); + aCh1RxSw4 <= lRxCh1_0(kCh1RxSw4Msb downto kCh1RxSw4); + aCh1RxSw5 <= lRxCh1_0(kCh1RxSw5Msb downto kCh1RxSw5); + aCh1RxSw6 <= lRxCh1_1(kCh1RxSw6Msb downto kCh1RxSw6); + aCh1RxSw7 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1RxSw8 <= "01" when lRxCh1_1(kCh1RxLowbandMixerPathSelect) = '1' else "10"; + aCh1LedRx <= lRxCh1_1(kCh1RxLed) and not lTxCh1(kCh1TxLed); + aCh1LedRx2 <= lRxCh1_1(kCh1Rx2Led); + aCh1RxAmpEn <= lRxCh1_1(kCh1RxAmpEn); + aCh1RxMixerEn <= lRxCh1_1(kCh1RxMixerEn); + aCh1RxLna1En <= lRxCh1_1(kCh1RxLna1En); + aCh1RxLna2En <= lRxCh1_1(kCh1RxLna2En); + aMkRx1En <= lRxCh1_1(kCh1MykEnRx); + + aCh2RxSw1 <= Rx2Switch1Mod(lRxCh2_0(kCh1RxSw1Msb downto kCh1RxSw1)); + aCh2RxSw2 <= Rx2Switch2Mod(lRxCh2_0(kCh1RxSw2Msb downto kCh1RxSw2)); + aCh2RxSw3 <= Rx2Switch3Mod(lRxCh2_0(kCh1RxSw3Msb downto kCh1RxSw3)); + aCh2RxSw4 <= Rx2Switch4Mod(lRxCh2_0(kCh1RxSw4Msb downto kCh1RxSw4)); + aCh2RxSw5 <= Rx2Switch5Mod(lRxCh2_0(kCh1RxSw5Msb downto kCh1RxSw5)); + aCh2RxSw6 <= Rx2Switch6Mod(lRxCh2_1(kCh1RxSw6Msb downto kCh1RxSw6)); + aCh2RxSw7 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2RxSw8 <= "10" when lRxCh2_1(kCh1RxLowbandMixerPathSelect) = '1' else "01"; + aCh2LedRx <= lRxCh2_1(kCh1RxLed) and not lTxCh2(kCh1TxLed); + aCh2LedRx2 <= lRxCh2_1(kCh1Rx2Led); + aCh2RxAmpEn <= lRxCh2_1(kCh1RxAmpEn); + aCh2RxMixerEn <= lRxCh2_1(kCh1RxMixerEn); + aCh2RxLna1En <= lRxCh2_1(kCh1RxLna1En); + aCh2RxLna2En <= lRxCh2_1(kCh1RxLna2En); + aMkRx2En <= lRxCh2_1(kCh1MykEnRx); + + +end RTL; + + + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- These registers are accessed via the PS SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PS-SPI-SLE-33" as an active-low select. +-- +-- +-- +-- +-- This register contains the device signature. +-- +-- +-- +-- Represents the product family name/number. This field reads back as +-- 0xCAFE. +-- +-- +-- +-- +-- +-- +-- This register contains the device revision numeric code. +-- +-- +-- +-- Contains minor revision code (0,1,2,...). +-- +-- +-- +-- +-- +-- +-- This register contains the major revision value. +-- +-- +-- +-- Contains major revision code. +-- +-- +-- +-- +-- +-- +-- Build code... right now it's the date it was built. LSB in this register. +-- +-- +-- +-- Contains build code hour code. +-- +-- +-- +-- +-- Contains build code day code. +-- +-- +-- +-- +-- +-- +-- Build code... right now it's the date it was built. MSB in this register. +-- +-- +-- +-- Contains build code month code. +-- +-- +-- +-- +-- Contains build code revision year code. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Contains scratch value for testing. The state of this register has +-- no effect on any other operation in the CPLD. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Asserting this bit resets all the CPLD logic. +-- This reset will return all registers on the PS SPI interface to their default +-- state! To use this reset correctly, first write CpldReset to '1', then write +-- it to '0'. Registers will be reset on the _falling_ edge of CpldReset. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Setting this bit to '0' will allow the Phase DAC to exclusively control the +-- VCXO voltage. Defaults to '1', which allows the Phase DAC to adjust the +-- voltage (but the LMK still has control as well). +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live lock detect status from the RX LO. +-- +-- +-- +-- +-- Live lock detect status from the TX LO. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Drives the Mykonos hard reset line. Defaults to de-asserted. Write a '1' to +-- assert the reset, and a '0' to de-assert. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- These registers are accessed via the PL SPI interface to the CPLD. They are all +-- internal to the CPLD. The SPI format is 24 bits total. On MOSI, shift (msb first) +-- Rd/!Wt | Addr(6:0) | Data(15:0) (lsb). The SPI clock {b}MUST{/b} idle LOW before +-- and after the transaction. CPOL=CPHA=0. To access these registers, use the chip +-- select line named "CPLD-PL-SPI-LE-25" as an active-low select. {br}{br} +-- +-- The ATR bits ultimately control which of these registers actually control +-- the RF front end. +-- +-- +-- +-- +-- +-- Contains scratch value for testing. The state of this register has no effect +-- on any other operation in the CPLD. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Asserting this bit resets all the CPLD logic on the PL SPI interface. +-- This reset will return all registers to their default state! To use this +-- reset correctly, first write PlCpldReset to '1', then write it to '0'. +-- Registers will be reset on the _falling_ edge of PlCpldReset. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 0, RX = don't-care. +-- +-- +-- +-- Controls Switch 1. Filter bank receive switch. +-- +-- +-- +-- +-- Controls Switch 2. Filter bank distribution switch. +-- +-- +-- +-- +-- Controls Switch 3. Bypasses the filter bank and PA, or doesn't. +-- +-- +-- +-- +-- Controls Switches 4 and 5. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register. +-- +-- +-- +-- +-- Write a '1' to enable the lowband mixer. Note that Ch1TxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- +-- +-- +-- +-- Write a '1' to enable the TX path Amp in between TX switches 3 and 4. The path +-- (from Mykonos) is: TxSw4 -> Amp -> DSA -> TxSw3. +-- +-- +-- +-- +-- Write a '1' to enable the TX path PA in between TX switches 2 and 3. +-- +-- +-- +-- +-- TRX switch control. +-- +-- +-- +-- +-- Red/Green combo LED for the TRX channel. +-- +-- +-- +-- +-- Drives the Mykonos input port TX1_ENABLE. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 1 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 0, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel TX 2 when the +-- ATR bits are configured: TX = 1, RX = don't-care. The bitfields are the same +-- as for the Tx1_Off register. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- +-- +-- +-- Controls Switch 1. Selects between the cal, bypass, RX2, and TRX paths. +-- +-- +-- +-- +-- Controls Switch 2. First filter switch. Selects between bypass path and +-- the upper/lower filter banks. +-- +-- +-- +-- +-- Controls Switch 3. Lower filter bank transmit switch. +-- +-- +-- +-- +-- Controls Switch 4. Upper filter bank receive switch. +-- +-- +-- +-- +-- Controls Switch 5. Lower filter bank receive switch. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 0. +-- +-- +-- +-- Controls Switch 6. Selects between the upper and lower filter banks and +-- bypass path. +-- +-- +-- +-- +-- Controls Switches 7 and 8. Write a '1' to select the Lowband Mixer path. +-- Writing '0' will select the bypass path around the mixer. Default is '0'. Note: +-- Individual control over these switches was removed as an optimization to +-- allow all TX controls to fit in one 16 bit register... so the same was done +-- for the RX path for continuity. +-- +-- +-- +-- +-- Write a '1' to enable the lowband mixer. Note that Ch1RxLowbandMixerPathSelect +-- must be properly configured to select the mixer path. +-- +-- +-- +-- +-- Write a '1' to enable the RX path Amp directly before the Mykonos inputs. +-- +-- +-- +-- +-- Write a '1' to enable the RX path LNA1 between RxSw4 and RxSw6. +-- +-- +-- +-- +-- Write a '1' to enable the RX path LNA2 between RxSw5 and RxSw6. +-- +-- +-- +-- +-- Green LED for RX2 channel. +-- +-- +-- +-- +-- Red/Green combo LED for the TRX channel. +-- +-- +-- +-- +-- Drives the Mykonos input port RX1_ENABLE. +-- +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 1 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 0. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_0_Idle register. +-- +-- +-- +-- +-- +-- Load this register with the front-end configuration for channel RX 2 when the +-- ATR bits are configured: TX = don't-care, RX = 1. The bitfields are the same +-- as for the RxCh1_1_Idle register. +-- +-- +-- +-- +-- +-- +--XmlParse xml_off + + + diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc new file mode 100644 index 000000000..b89183a2e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db0_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + +## USRP IO A : ########################################################################## +## Banks 10/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN G1 [get_ports {DBA_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN H2 [get_ports {DBA_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D1 [get_ports {DBA_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN E1 [get_ports {nc}] +set_property PACKAGE_PIN H1 [get_ports {DBA_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN J1 [get_ports {DBA_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN A5 [get_ports {DBA_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN A4 [get_ports {DBA_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN F5 [get_ports {DBA_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN E5 [get_ports {DBA_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN E3 [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN E2 [get_ports {DBA_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN A3 [get_ports {DBA_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN A2 [get_ports {DBA_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN K1 [get_ports {DBA_ATR_RX_1}] +set_property PACKAGE_PIN L1 [get_ports {DBA_ATR_TX_2}] +set_property PACKAGE_PIN C4 [get_ports {DBA_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN C3 [get_ports {DBA_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN F4 [get_ports {DBA_ATR_TX_1}] +set_property PACKAGE_PIN F3 [get_ports {DBA_ATR_RX_2}] +# set_property PACKAGE_PIN B1 [get_ports {nc}] +set_property PACKAGE_PIN B2 [get_ports {DBA_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN C1 [get_ports {DBA_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN C2 [get_ports {DBA_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AG12 [get_ports {DBA_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AH12 [get_ports {DBA_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AJ13 [get_ports {DBA_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ14 [get_ports {DBA_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AG15 [get_ports {DBA_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AF15 [get_ports {DBA_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH13 [get_ports {DBA_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AH14 [get_ports {DBA_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK15 [get_ports {DBA_MYK_GPIO_1}] +set_property PACKAGE_PIN AJ15 [get_ports {DBA_MYK_GPIO_4}] +set_property PACKAGE_PIN AH16 [get_ports {DBA_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH17 [get_ports {DBA_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AE12 [get_ports {DBA_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF12 [get_ports {DBA_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK12 [get_ports {DBA_MYK_GPIO_13}] +set_property PACKAGE_PIN AK13 [get_ports {DBA_MYK_GPIO_0}] +set_property PACKAGE_PIN AK16 [get_ports {DBA_MYK_INTRQ}] +set_property PACKAGE_PIN AJ16 [get_ports {DBA_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AH18 [get_ports {DBA_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AJ18 [get_ports {DBA_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF14 [get_ports {DBA_FPGA_CLK_P}] +set_property PACKAGE_PIN AG14 [get_ports {DBA_FPGA_CLK_N}] +set_property PACKAGE_PIN AG17 [get_ports {DBA_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AG16 [get_ports {DBA_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AD15 [get_ports {DBA_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AD16 [get_ports {DBA_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AE13 [get_ports {DBA_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AF13 [get_ports {DBA_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AE15 [get_ports {DBA_MYK_GPIO_15}] +set_property PACKAGE_PIN AE16 [get_ports {DBA_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AF17 [get_ports {DBA_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AF18 [get_ports {DBA_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AC16 [get_ports {DBA_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AC17 [get_ports {DBA_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD13 [get_ports {DBA_MYK_GPIO_12}] +set_property PACKAGE_PIN AD14 [get_ports {DBA_MYK_GPIO_14}] +set_property PACKAGE_PIN AE17 [get_ports {DBA_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AE18 [get_ports {DBA_MYK_GPIO_3}] +set_property PACKAGE_PIN AB12 [get_ports {DBA_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AC12 [get_ports {DBA_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AC13 [get_ports {DBA_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AC14 [get_ports {DBA_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AB25 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property IOSTANDARD LVCMOS33 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property DRIVE 4 [get_ports {DBA_SWITCHER_CLOCK}] +# set_property SLEW SLOW [get_ports {DBA_SWITCHER_CLOCK}] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoAHpPinsSe [get_ports {DBA_CPLD_PS_* \ + DBA_CH1_* \ + DBA_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 4 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSe [get_ports {DBA_MYK_SPI_* \ + DBA_MYK_INTRQ \ + DBA_MYK_SYNC* \ + DBA_MYK_GPIO* \ + DBA_CPLD_PL_* \ + DBA_CPLD_JTAG_* \ + DBA_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSe +set_property DRIVE 4 $UsrpIoAHrPinsSe +set_property SLEW SLOW $UsrpIoAHrPinsSe + +set UsrpIoAHrPinsDiff [get_ports {DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBA_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN N8 [get_ports {USRPIO_A_MGTCLK_P}] +set_property PACKAGE_PIN N7 [get_ports {USRPIO_A_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN V6 [get_ports {USRPIO_A_RX_P[0]}] +set_property PACKAGE_PIN V5 [get_ports {USRPIO_A_RX_N[0]}] +set_property PACKAGE_PIN U4 [get_ports {USRPIO_A_RX_P[1]}] +set_property PACKAGE_PIN U3 [get_ports {USRPIO_A_RX_N[1]}] +set_property PACKAGE_PIN T6 [get_ports {USRPIO_A_RX_P[2]}] +set_property PACKAGE_PIN T5 [get_ports {USRPIO_A_RX_N[2]}] +set_property PACKAGE_PIN P6 [get_ports {USRPIO_A_RX_P[3]}] +set_property PACKAGE_PIN P5 [get_ports {USRPIO_A_RX_N[3]}] + +set_property PACKAGE_PIN T2 [get_ports {USRPIO_A_TX_P[0]}] +set_property PACKAGE_PIN T1 [get_ports {USRPIO_A_TX_N[0]}] +set_property PACKAGE_PIN R4 [get_ports {USRPIO_A_TX_P[1]}] +set_property PACKAGE_PIN R3 [get_ports {USRPIO_A_TX_N[1]}] +set_property PACKAGE_PIN P2 [get_ports {USRPIO_A_TX_P[2]}] +set_property PACKAGE_PIN P1 [get_ports {USRPIO_A_TX_N[2]}] +set_property PACKAGE_PIN N4 [get_ports {USRPIO_A_TX_P[3]}] +set_property PACKAGE_PIN N3 [get_ports {USRPIO_A_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc new file mode 100644 index 000000000..f95051ba7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db1_pins.xdc @@ -0,0 +1,156 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Daughterboard Pin Definitions for the N310. +# + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + +### USRP IO B : ######################################################################### +## Bank 11/33 +######################################################################################### + +## HP GPIO, Bank 33, 1.8V + +set_property PACKAGE_PIN J4 [get_ports {DBB_CPLD_PS_SPI_LE}] +set_property PACKAGE_PIN J3 [get_ports {DBB_CPLD_PS_SPI_SCLK}] +set_property PACKAGE_PIN D4 [get_ports {DBB_CH1_TX_DSA_DATA[5]}] +# set_property PACKAGE_PIN D3 [get_ports {nc}] +set_property PACKAGE_PIN K2 [get_ports {DBB_CPLD_PS_SPI_ADDR[0]}] +set_property PACKAGE_PIN K3 [get_ports {DBB_CPLD_PS_SPI_ADDR[1]}] +set_property PACKAGE_PIN B5 [get_ports {DBB_CH1_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN B4 [get_ports {DBB_CH1_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN G5 [get_ports {DBB_CPLD_PS_SPI_SDO}] +set_property PACKAGE_PIN G4 [get_ports {DBB_CPLD_PS_SPI_SDI}] +set_property PACKAGE_PIN J5 [get_ports {DBB_CH1_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN K5 [get_ports {DBB_CH1_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN D5 [get_ports {DBB_CH1_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN E6 [get_ports {DBB_CH1_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN L3 [get_ports {DBB_ATR_RX_1}] +set_property PACKAGE_PIN L2 [get_ports {DBB_ATR_TX_2}] +set_property PACKAGE_PIN G6 [get_ports {DBB_CH1_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN H6 [get_ports {DBB_CH1_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN H4 [get_ports {DBB_ATR_TX_1}] +set_property PACKAGE_PIN H3 [get_ports {DBB_ATR_RX_2}] +# set_property PACKAGE_PIN F2 [get_ports {nc}] +set_property PACKAGE_PIN G2 [get_ports {DBB_CH1_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN J6 [get_ports {DBB_CH1_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN K6 [get_ports {DBB_CH1_RX_DSA_DATA[2]}] + +## HR GPIO, Bank 10, 2.5V + +set_property PACKAGE_PIN AK17 [get_ports {DBB_MYK_SYNC_IN_n}] +set_property PACKAGE_PIN AK18 [get_ports {DBB_CPLD_PL_SPI_ADDR[0]}] +set_property PACKAGE_PIN AK21 [get_ports {DBB_MYK_SPI_SDO}] +set_property PACKAGE_PIN AJ21 [get_ports {DBB_MYK_SPI_SDIO}] +set_property PACKAGE_PIN AF19 [get_ports {DBB_CPLD_PL_SPI_ADDR[1]}] +set_property PACKAGE_PIN AG19 [get_ports {DBB_CH2_TX_DSA_DATA[5]}] +set_property PACKAGE_PIN AH19 [get_ports {DBB_CPLD_JTAG_TDI}] +set_property PACKAGE_PIN AJ19 [get_ports {DBB_CPLD_JTAG_TDO}] +set_property PACKAGE_PIN AK22 [get_ports {DBB_MYK_GPIO_1}] +set_property PACKAGE_PIN AK23 [get_ports {DBB_MYK_GPIO_4}] +set_property PACKAGE_PIN AF20 [get_ports {DBB_CH2_TX_DSA_DATA[4]}] +set_property PACKAGE_PIN AG20 [get_ports {DBB_CH2_TX_DSA_DATA[3]}] +set_property PACKAGE_PIN AF23 [get_ports {DBB_MYK_SYNC_OUT_n}] +set_property PACKAGE_PIN AF24 [get_ports {DBB_CPLD_PL_SPI_SDO}] +set_property PACKAGE_PIN AK20 [get_ports {DBB_MYK_GPIO_13}] +set_property PACKAGE_PIN AJ20 [get_ports {DBB_MYK_GPIO_0}] +set_property PACKAGE_PIN AJ23 [get_ports {DBB_MYK_INTRQ}] +set_property PACKAGE_PIN AJ24 [get_ports {DBB_CH2_TX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG24 [get_ports {DBB_CH2_TX_DSA_DATA[0]}] +set_property PACKAGE_PIN AG25 [get_ports {DBB_CH2_TX_DSA_DATA[1]}] +set_property PACKAGE_PIN AG21 [get_ports {DBB_FPGA_CLK_P}] +set_property PACKAGE_PIN AH21 [get_ports {DBB_FPGA_CLK_N}] +set_property PACKAGE_PIN AE22 [get_ports {DBB_FPGA_SYSREF_P}] +set_property PACKAGE_PIN AF22 [get_ports {DBB_FPGA_SYSREF_N}] +set_property PACKAGE_PIN AJ25 [get_ports {DBB_CH2_RX_DSA_DATA[3]}] +set_property PACKAGE_PIN AK25 [get_ports {DBB_CH2_RX_DSA_DATA[5]}] +set_property PACKAGE_PIN AB21 [get_ports {DBB_CPLD_JTAG_TMS}] +set_property PACKAGE_PIN AB22 [get_ports {DBB_CPLD_JTAG_TCK}] +set_property PACKAGE_PIN AD23 [get_ports {DBB_MYK_GPIO_15}] +set_property PACKAGE_PIN AE23 [get_ports {DBB_MYK_SPI_CS_n}] +set_property PACKAGE_PIN AB24 [get_ports {DBB_CH2_RX_DSA_DATA[1]}] +set_property PACKAGE_PIN AA24 [get_ports {DBB_CH2_RX_DSA_DATA[2]}] +set_property PACKAGE_PIN AG22 [get_ports {DBB_CPLD_PL_SPI_LE}] +set_property PACKAGE_PIN AH22 [get_ports {DBB_CPLD_PL_SPI_SDI}] +set_property PACKAGE_PIN AD21 [get_ports {DBB_MYK_GPIO_12}] +set_property PACKAGE_PIN AE21 [get_ports {DBB_MYK_GPIO_14}] +set_property PACKAGE_PIN AC22 [get_ports {DBB_MYK_SPI_SCLK}] +set_property PACKAGE_PIN AC23 [get_ports {DBB_MYK_GPIO_3}] +set_property PACKAGE_PIN AC24 [get_ports {DBB_CH2_RX_DSA_DATA[0]}] +set_property PACKAGE_PIN AD24 [get_ports {DBB_CH2_RX_DSA_DATA[4]}] +set_property PACKAGE_PIN AH23 [get_ports {DBB_CPLD_PL_SPI_ADDR[2]}] +set_property PACKAGE_PIN AH24 [get_ports {DBB_CPLD_PL_SPI_SCLK}] + +# set_property PACKAGE_PIN AA25 [get_ports DBB_SWITCHER_CLOCK] +# set_property IOSTANDARD LVCMOS33 [get_ports DBB_SWITCHER_CLOCK] +# set_property DRIVE 4 [get_ports DBB_SWITCHER_CLOCK] +# set_property SLEW SLOW [get_ports DBB_SWITCHER_CLOCK] + +# During SI measurements with default drive strength, many of the FPGA-driven lines to +# the DB were showing high over/undershoot. Therefore for single-ended lines to the DBs +# we are decreasing the drive strength to the minimum value (4mA) and explicitly +# declaring the (default) slew rate as SLOW. + +set UsrpIoBHpPinsSe [get_ports {DBB_CPLD_PS_* \ + DBB_CH1_* \ + DBB_ATR*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 4 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSe [get_ports {DBB_MYK_SPI_* \ + DBB_MYK_INTRQ \ + DBB_MYK_SYNC* \ + DBB_MYK_GPIO* \ + DBB_CPLD_PL_* \ + DBB_CPLD_JTAG_* \ + DBB_CH2*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSe +set_property DRIVE 4 $UsrpIoBHrPinsSe +set_property SLEW SLOW $UsrpIoBHrPinsSe + +set UsrpIoBHrPinsDiff [get_ports {DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff + +# Do not allow the DSA lines to float... give them a weak pull if undriven. +set_property PULLUP TRUE [get_ports {DBB_CH*_*X_DSA_DATA[*]}] + + +### MGTs, Bank 112 + +set_property PACKAGE_PIN W8 [get_ports {USRPIO_B_MGTCLK_P}] +set_property PACKAGE_PIN W7 [get_ports {USRPIO_B_MGTCLK_N}] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the Mykonos lane crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports {USRPIO_B_RX_P[0]}] +set_property PACKAGE_PIN AC3 [get_ports {USRPIO_B_RX_N[0]}] +set_property PACKAGE_PIN AB6 [get_ports {USRPIO_B_RX_P[1]}] +set_property PACKAGE_PIN AB5 [get_ports {USRPIO_B_RX_N[1]}] +set_property PACKAGE_PIN Y6 [get_ports {USRPIO_B_RX_P[2]}] +set_property PACKAGE_PIN Y5 [get_ports {USRPIO_B_RX_N[2]}] +set_property PACKAGE_PIN AA4 [get_ports {USRPIO_B_RX_P[3]}] +set_property PACKAGE_PIN AA3 [get_ports {USRPIO_B_RX_N[3]}] + +set_property PACKAGE_PIN AB2 [get_ports {USRPIO_B_TX_P[0]}] +set_property PACKAGE_PIN AB1 [get_ports {USRPIO_B_TX_N[0]}] +set_property PACKAGE_PIN Y2 [get_ports {USRPIO_B_TX_P[1]}] +set_property PACKAGE_PIN Y1 [get_ports {USRPIO_B_TX_N[1]}] +set_property PACKAGE_PIN W4 [get_ports {USRPIO_B_TX_P[2]}] +set_property PACKAGE_PIN W3 [get_ports {USRPIO_B_TX_N[2]}] +set_property PACKAGE_PIN V2 [get_ports {USRPIO_B_TX_P[3]}] +set_property PACKAGE_PIN V1 [get_ports {USRPIO_B_TX_N[3]}] diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..ffaa64f68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- +-- +-- Phase Shift for RadioClkMmcm. +-- +-- +-- +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- +-- +-- +-- +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Read-only. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..7f8ef388a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- +-- +-- +-- +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd new file mode 100644 index 000000000..e1369ec00 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/DbCore.vhd @@ -0,0 +1,562 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgMgPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as one sample per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + sAdcDataValid : out std_logic; + sAdcDataSamples0I : out std_logic_vector(15 downto 0); + sAdcDataSamples0Q : out std_logic_vector(15 downto 0); + sAdcDataSamples1I : out std_logic_vector(15 downto 0); + sAdcDataSamples1Q : out std_logic_vector(15 downto 0); + sDacReadyForInput : out std_logic; + sDacDataSamples0I : in std_logic_vector(15 downto 0); + sDacDataSamples0Q : in std_logic_vector(15 downto 0); + sDacDataSamples1I : in std_logic_vector(15 downto 0); + sDacDataSamples1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fAdc1DataFlat : out STD_LOGIC_VECTOR(31 downto 0); + fDac0DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fDac1DataFlat : in STD_LOGIC_VECTOR(31 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdc0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sAdc1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDac0DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDac1DataFlat: STD_LOGIC_VECTOR(31 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdc0Data, sAdc1Data : AdcData_t; + signal sDac0Data, sDac1Data : DacData_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + aLmkSync => aLmkSync, --out STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdc0DataFlat => sAdc0DataFlat, --out STD_LOGIC_VECTOR(31:0) + fAdc1DataFlat => sAdc1DataFlat, --out STD_LOGIC_VECTOR(31:0) + fDac0DataFlat => sDac0DataFlat, --in STD_LOGIC_VECTOR(31:0) + fDac1DataFlat => sDac1DataFlat, --in STD_LOGIC_VECTOR(31:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdc0Data <= Unflatten(sAdc0DataFlat); + sAdc1Data <= Unflatten(sAdc1DataFlat); + sDac0DataFlat <= Flatten(sDac0Data); + sDac1DataFlat <= Flatten(sDac1Data); + + sAdcDataSamples0I <= sAdc0Data.I; + sAdcDataSamples0Q <= sAdc0Data.Q; + sAdcDataSamples1I <= sAdc1Data.I; + sAdcDataSamples1Q <= sAdc1Data.Q; + + sDac0Data.I <= sDacDataSamples0I; + sDac0Data.Q <= sDacDataSamples0Q; + sDac1Data.I <= sDacDataSamples1I; + sDac1Data.Q <= sDacDataSamples1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(16#150#,16)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(16#150#,16)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf new file mode 100644 index 000000000..27619d2a0 Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..84c461d26 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,56 @@ +-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016 +-- Date : Wed Jan 10 10:53:33 2018 +-- Host : djepson-lt running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + aLmkSync : out STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + CaptureSysRefClk : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdc0DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdc1DataFlat : out STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac0DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fDac1DataFlat : in STD_LOGIC_VECTOR ( 31 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],aLmkSync,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,CaptureSysRefClk,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdc0DataFlat[31:0],fAdc1DataFlat[31:0],fDac0DataFlat[31:0],fDac1DataFlat[31:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..c0f5244b5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,234 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: NI 5840 +-- Date: 11 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N310, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 16; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 1; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kQpllDrpAddrWidth : natural := 8; + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + + -- JESD shared setup - LMFS = 4421, HD = 0 + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 4; -- M + constant kOctetsPerFrame : natural := 2; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes/4; -- 4 lanes per quad + constant kHighDensity : boolean := false; -- HD + constant kConvResBits : positive := kDacDataWidth-2; -- Converter resolution in bits + constant kConvSampleBits : positive := kDacDataWidth; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 20; -- K + + -- In the N310 case we are one SPC, so this value is simply the number of frames + -- (samples) per multiframe. + constant kUserClksPerMulti : integer := kFramesPerMulti; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are as follows: + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + + + -- ADC & DAC Data Types + -- + + -- ADC Words from JESD204B RX Core. The array is 4 elements wide to accommodate the + -- I & Q elements from both RX channels. + subtype AdcWord_t is std_logic_vector(kAdcDataWidth - 1 downto 0); + type AdcWordArray_t is array(4 - 1 downto 0) of AdcWord_t; + + -- Data types for manipulation and presentation to outside world. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + + -- Flattened data types for passing into and out of pre-synthesized components. + subtype AdcDataFlat_t is std_logic_vector(2*kAdcDataWidth - 1 downto 0); + subtype DacDataFlat_t is std_logic_vector(2*kDacDataWidth - 1 downto 0); + + -- Functions to convert to/from types defined above. + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t; + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t; + + function Flatten (DacData : DacData_t) return DacDataFlat_t; + function Unflatten(DacData : DacDataFlat_t) return DacData_t; + + +end package; + + +package body PkgJesdConfig is + + + + + + -- Flattens AdcData_t to AdcDataFlat_t + function Flatten (AdcData : AdcData_t) return AdcDataFlat_t + is + variable ReturnVar : AdcDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := AdcData.I & AdcData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataFlat_t to AdcData_t + function Unflatten(AdcData : AdcDataFlat_t) return AdcData_t + is + variable ReturnVar : AdcData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := AdcData(2*kAdcDataWidth - 1 downto kAdcDataWidth); + ReturnVar.Q := AdcData( kAdcDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacData_t to DacDataFlat_t + function Flatten (DacData : DacData_t) return DacDataFlat_t + is + variable ReturnVar : DacDataFlat_t; + begin + ReturnVar := (others => '0'); + -- MSB is I + ReturnVar := DacData.I & DacData.Q; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataFlat_t to DacData_t + function Unflatten(DacData : DacDataFlat_t) return DacData_t + is + variable ReturnVar : DacData_t; + begin + ReturnVar := (others => (others => '0')); + -- MSB is I + ReturnVar.I := DacData(2*kDacDataWidth - 1 downto kDacDataWidth); + ReturnVar.Q := DacData( kDacDataWidth - 1 downto 0); + return ReturnVar; + end function Unflatten; + + + + + +end package body; \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd new file mode 100644 index 000000000..904653a8e --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/PkgMgPersonality.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgMgPersonality.vhd +-- Author: National Instruments +-- Original Project: N310 +-- Date: 13 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgMgPersonality is + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + + + + +end package PkgMgPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..ee0da9f84 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/RadioClocking.vhd @@ -0,0 +1,304 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 6.000, -- Feedback + CLKOUT0_DIVIDE_F => 6.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 3, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 6.510, -- 153.6 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc new file mode 100644 index 000000000..142ba9ab4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/db_timing.xdc @@ -0,0 +1,347 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/dboards/mg/doc/mg_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks + +# 122.88, 125, and 153.6 MHz Sample Clocks are allowable. Constrain the paths to the max +# rate in order to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 6.510 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_A_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports USRPIO_B_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the ADCs) to a +# typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. I tested this by setting the +# early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Divider values are 123, 125, or 154 based on what radio clock +# rate is set. To be ultra-conservative (which still provides 10s of ns of slack), we +# set an over-constrained divider value of 50. +set PL_SPI_DIVIDE_VAL 50 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B + +# Define one of the outputs of each bus as a clock (even though it isn't a clock). This +# allows us to constrain the overall bus skew with respect to one of the bus outputs. +# See the remainder of this constraint below for more details. +set DSA_CLK [get_ports {DBA_CH1_RX_DSA_DATA[0]}] +create_generated_clock -name dsa_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $DSA_CLK]/C] \ + -divide_by 2 $DSA_CLK + +set ATR_CLK [get_ports DBA_ATR_RX_1] +create_generated_clock -name atr_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $ATR_CLK]/C] \ + -divide_by 2 $ATR_CLK + +# Interface Unused +# set MGPIO_CLK [get_ports DBA_MYK_GPIO_0] +# create_generated_clock -name myk_gpio_bus_clk \ + # -source [get_pins [all_fanin -flat -only_cells -startpoints_only [get_ports $MGPIO_CLK]]/C] \ + # -divide_by 2 [get_ports $MGPIO_CLK] + + + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + + + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_SDI \ + DB*_CPLD_PS_SPI_LE \ + DB*_CPLD_PS_SPI_ADDR[0] \ + DB*_CPLD_PS_SPI_ADDR[1]}] + +set_max_delay 12.0 -to $CPLD_SPI_OUTS +set_min_delay 3.0 -to $CPLD_SPI_OUTS + +set MYK_SPI_OUTS [get_ports {DB*_MYK_SPI_SCLK \ + DB*_MYK_SPI_SDIO \ + DB*_MYK_SPI_CS_n}] + +set_max_delay 14.0 -to $MYK_SPI_OUTS +set_min_delay 3.0 -to $MYK_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming +# report_timing -to $MYK_SPI_OUTS -max_paths 20 -delay_type min_max -name MykSpiOutTiming + +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 20 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 20.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_LE \ + DBA_CPLD_PL_SPI_SDI \ + DBA_CPLD_PL_SPI_ADDR[0] \ + DBA_CPLD_PL_SPI_ADDR[1]}] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_LE \ + DBB_CPLD_PL_SPI_SDI \ + DBB_CPLD_PL_SPI_ADDR[0] \ + DBB_CPLD_PL_SPI_ADDR[1]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_SDO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_SDO] +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -max 68.041 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_a] -clock_fall -min 12.218 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -max 68.041 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_clk_b] -clock_fall -min 12.218 $MISO_INPUT_B +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +# One of the PL_SPI_ADDR lines is used instead for the LMK SYNC strobe. This line is +# driven asynchronously. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_CPLD_PL_SPI_ADDR[2]] +set_max_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 50.000 +set_min_delay -to [get_ports DB*_CPLD_PL_SPI_ADDR[2]] 0.000 + + + +#******************************************************************************* +## DSA Bus +# The DSA controls are driven from the DB-A radio clock. Although they are received async +# at the DSAs, they should be tightly constrained in the FPGA to arrive as closely as +# possible. The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports {DB*_CH*_*X_DSA_DATA[*]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks dsa_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +# The clock, which is essentially one of the data lines, should arrive at the pin +# +/- MAX_DELAY compared to the other data lines, so setup and hold checks need to be +# relative to the SAME edges for both the clock and the data. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks dsa_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DSA_CLK +set_max_delay -to $DSA_CLK 50.000 +set_min_delay -to $DSA_CLK 0.000 + + + +#******************************************************************************* +## ATR Bus +# The ATR bits are driven from the DB-A radio clock. Although they are received async in +# the CPLD, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +set MAX_SKEW 2.5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set PORT_LIST [get_ports DB*_ATR_*X_*] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks atr_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks atr_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks atr_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $ATR_CLK +set_max_delay -to $ATR_CLK 50.000 +set_min_delay -to $ATR_CLK 0.000 + + + +#******************************************************************************* +## Mykonos Ports +# Mykonos GPIO is driven from the DB-A radio clock. Although they are received async in +# Mykonos, they should be tightly constrained in the FPGA to avoid any race conditions. +# The best way to do this is a skew constraint across all the bits. +# set MAX_SKEW 2.5 +# set SETUP_SKEW [expr {($MAX_SKEW / 2)+0.5}] +# set HOLD_SKEW [expr {($MAX_SKEW / 2)-0.5}] +# set PORT_LIST [get_ports DB*_ATR_*X_*] +# # Then add the output delay on each of the ports. +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +# set_output_delay -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# set_output_delay -add_delay -clock_fall -clock [get_clocks myk_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# # Finally, make both the setup and hold checks use the same launching and latching edges. +# set_multicycle_path -setup -to [get_clocks myk_gpio_bus_clk] -start 0 +# set_multicycle_path -hold -to [get_clocks myk_gpio_bus_clk] -1 +# # Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# # they aren't supported in XDC files... so we do it the old fashioned way. +# set_output_delay -clock [get_clocks async_out_clk] 0.000 $MGPIO_CLK +# set_max_delay -to $MGPIO_CLK 50.000 +# set_min_delay -to $MGPIO_CLK 0.000 + +# Mykonos Interrupt is received asynchronously, and driven directly to the PS. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_INTRQ] +set_max_delay -from [get_ports DB*_MYK_INTRQ] 50.000 +set_min_delay -from [get_ports DB*_MYK_INTRQ] 0.000 + + + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output for both DBs is governed by the JESD cores, which are solely driven by +# DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_MYK_SYNC_IN_n] +set_max_delay -to [get_ports DB*_MYK_SYNC_IN_n] 50.000 +set_min_delay -to [get_ports DB*_MYK_SYNC_IN_n] 0.000 + +# The SYNC input for both DBs is received by the DB-A clock inside the JESD cores... but +# again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_MYK_SYNC_OUT_n] +set_max_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 50.000 +set_min_delay -from [get_ports DB*_MYK_SYNC_OUT_n] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.906 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.646 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.906 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.646 [get_ports DBB_FPGA_SYSREF_*] + + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md new file mode 100644 index 000000000..2071c46ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/doc/CPLD.md @@ -0,0 +1,2 @@ +Timing closure of the CPLD design relies on the pre-set seed value. The build +requires Quartus 16.1.2. diff --git a/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx new file mode 100644 index 000000000..c4ad8ac5c Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/mg/doc/mg_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v new file mode 100644 index 000000000..32fa84153 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v @@ -0,0 +1,3915 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2016-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N3xx devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CPLD_PS_SPI_LE, + output DBA_CPLD_PS_SPI_SDI, + input DBA_CPLD_PS_SPI_SDO, + output [1:0] DBA_CPLD_PS_SPI_ADDR, + + output DBA_ATR_RX_1, + output DBA_ATR_RX_2, + output DBA_ATR_TX_1, + output DBA_ATR_TX_2, + + output [5:0] DBA_CH1_TX_DSA_DATA, + output [5:0] DBA_CH1_RX_DSA_DATA, + output [5:0] DBA_CH2_TX_DSA_DATA, + output [5:0] DBA_CH2_RX_DSA_DATA, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_CPLD_PL_SPI_LE, + output DBA_CPLD_PL_SPI_SDI, + input DBA_CPLD_PL_SPI_SDO, + output [2:0] DBA_CPLD_PL_SPI_ADDR, + + output DBA_MYK_SPI_SCLK, + output DBA_MYK_SPI_CS_n, + input DBA_MYK_SPI_SDO, + output DBA_MYK_SPI_SDIO, + input DBA_MYK_INTRQ, + + output DBA_MYK_SYNC_IN_n, + input DBA_MYK_SYNC_OUT_n, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + output DBA_MYK_GPIO_0, + output DBA_MYK_GPIO_1, + output DBA_MYK_GPIO_3, + output DBA_MYK_GPIO_4, + output DBA_MYK_GPIO_12, + output DBA_MYK_GPIO_13, + output DBA_MYK_GPIO_14, + output DBA_MYK_GPIO_15, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input USRPIO_A_MGTCLK_P, + input USRPIO_A_MGTCLK_N, + + input [3:0] USRPIO_A_RX_P, + input [3:0] USRPIO_A_RX_N, + output [3:0] USRPIO_A_TX_P, + output [3:0] USRPIO_A_TX_N + +`ifndef N300 + //USRP IO B + ,output DBB_CPLD_PS_SPI_SCLK, + output DBB_CPLD_PS_SPI_LE, + output DBB_CPLD_PS_SPI_SDI, + input DBB_CPLD_PS_SPI_SDO, + output [1:0] DBB_CPLD_PS_SPI_ADDR, + + output DBB_ATR_RX_1, + output DBB_ATR_RX_2, + output DBB_ATR_TX_1, + output DBB_ATR_TX_2, + + output [5:0] DBB_CH1_TX_DSA_DATA, + output [5:0] DBB_CH1_RX_DSA_DATA, + output [5:0] DBB_CH2_TX_DSA_DATA, + output [5:0] DBB_CH2_RX_DSA_DATA, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_CPLD_PL_SPI_LE, + output DBB_CPLD_PL_SPI_SDI, + input DBB_CPLD_PL_SPI_SDO, + output [2:0] DBB_CPLD_PL_SPI_ADDR, + + output DBB_MYK_SPI_SCLK, + output DBB_MYK_SPI_CS_n, + input DBB_MYK_SPI_SDO, + output DBB_MYK_SPI_SDIO, + input DBB_MYK_INTRQ, + + output DBB_MYK_SYNC_IN_n, + input DBB_MYK_SYNC_OUT_n, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + output DBB_MYK_GPIO_0, + output DBB_MYK_GPIO_1, + output DBB_MYK_GPIO_3, + output DBB_MYK_GPIO_4, + output DBB_MYK_GPIO_12, + output DBB_MYK_GPIO_13, + output DBB_MYK_GPIO_14, + output DBB_MYK_GPIO_15, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input USRPIO_B_MGTCLK_P, + input USRPIO_B_MGTCLK_N, + + input [3:0] USRPIO_B_RX_P, + input [3:0] USRPIO_B_RX_N, + output [3:0] USRPIO_B_TX_P, + output [3:0] USRPIO_B_TX_N +`endif +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + +`ifdef N310 + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 2; +`elsif N300 + localparam NUM_RADIOS = 1; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_DBOARDS = 1; +`endif + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clk_2x; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign ps_gpio_in[10] = DBA_MYK_INTRQ; +`ifndef N300 + assign ps_gpio_in[11] = DBB_MYK_INTRQ; +`else + assign ps_gpio_in[11] = 1'b0; +`endif + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + `ifndef N300 + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + `else + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(), + .SPI1_MOSI_T(), + .SPI1_MISO_I(1'b0), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(), + .SPI1_SS1_O(), + .SPI1_SS2_O(), + .SPI1_SS_T(), + `endif + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + `ifndef N300 + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + `else + .JTAG1_TCK(), + .JTAG1_TMS(), + .JTAG1_TDI(), + .JTAG1_TDO('b0), + `endif + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + wire cpld_a_cs_n; + wire lmk_a_cs_n; + wire dac_a_cs_n; + wire myk_a_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_SDI = spi0_mosi; + + assign DBA_MYK_SPI_SCLK = spi0_sclk; + assign DBA_MYK_SPI_SDIO = spi0_mosi; + // Assign individual chip selects from PS SPI MASTER 0. + assign cpld_a_cs_n = spi0_ss0; + assign lmk_a_cs_n = spi0_ss1; + assign dac_a_cs_n = ps_gpio_out[8]; // DAC select driven through GPIO. + assign myk_a_cs_n = spi0_ss2; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = ~myk_a_cs_n ? DBA_MYK_SPI_SDO : // From Mykonos + DBA_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBA_CPLD_PS_SPI_LE = cpld_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[0] = lmk_a_cs_n; + assign DBA_CPLD_PS_SPI_ADDR[1] = dac_a_cs_n; + assign DBA_MYK_SPI_CS_n = myk_a_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_a_out_iob, dsa_rx1_a_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_a_out_iob, dsa_rx2_a_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_a_out_iob <= db_gpio_out[16*0+11:16*0+6]; + dsa_rx1_a_out_iob <= db_gpio_out[16*0+5:16*0+0]; + dsa_tx2_a_out_iob <= db_gpio_out[16*1+11:16*1+6]; + dsa_rx2_a_out_iob <= db_gpio_out[16*1+5:16*1+0]; + end + + assign DBA_CH1_TX_DSA_DATA = dsa_tx1_a_out_iob; + assign DBA_CH1_RX_DSA_DATA = dsa_rx1_a_out_iob; + assign DBA_CH2_TX_DSA_DATA = dsa_tx2_a_out_iob; + assign DBA_CH2_RX_DSA_DATA = dsa_rx2_a_out_iob; + + assign DBA_ATR_RX_1 = rx_atr_reg[0]; + assign DBA_ATR_RX_2 = rx_atr_reg[1]; + assign DBA_ATR_TX_1 = tx_atr_reg[0]; + assign DBA_ATR_TX_2 = tx_atr_reg[1]; + + assign DBA_MYK_GPIO_0 = 1'b0; + assign DBA_MYK_GPIO_1 = 1'b0; + assign DBA_MYK_GPIO_3 = 1'b0; + assign DBA_MYK_GPIO_4 = 1'b0; + assign DBA_MYK_GPIO_12 = 1'b0; + assign DBA_MYK_GPIO_13 = 1'b0; + assign DBA_MYK_GPIO_14 = 1'b0; + assign DBA_MYK_GPIO_15 = 1'b0; + +`ifndef N300 + + // DB B SPI Connections + wire cpld_b_cs_n; + wire lmk_b_cs_n; + wire dac_b_cs_n; + wire myk_b_cs_n; + + // Split out the SCLK and MOSI data to Mykonos and the CPLD. + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_SDI = spi1_mosi; + + assign DBB_MYK_SPI_SCLK = spi1_sclk; + assign DBB_MYK_SPI_SDIO = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign cpld_b_cs_n = spi1_ss0; + assign lmk_b_cs_n = spi1_ss1; + assign dac_b_cs_n = ps_gpio_out[9]; // DAC select driven through GPIO. + assign myk_b_cs_n = spi1_ss2; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = ~myk_b_cs_n ? DBB_MYK_SPI_SDO : // From Mykonos + DBB_CPLD_PS_SPI_SDO; + + // For the PS SPI connection to the CPLD, we use the LE and ADDR lines as individual + // chip selects for the CPLD endpoint as well as the LMK and DAC endpoints. + // LE = CPLD + // ADDR[0] = LMK + // ADDR[1] = DAC + assign DBB_CPLD_PS_SPI_LE = cpld_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[0] = lmk_b_cs_n; + assign DBB_CPLD_PS_SPI_ADDR[1] = dac_b_cs_n; + assign DBB_MYK_SPI_CS_n = myk_b_cs_n; + + // Instantiate DSA registers in the IOB + (* IOB = "true" *) reg [5:0] dsa_tx1_b_out_iob, dsa_rx1_b_out_iob; + (* IOB = "true" *) reg [5:0] dsa_tx2_b_out_iob, dsa_rx2_b_out_iob; + always @(posedge radio_clk) begin + dsa_tx1_b_out_iob <= db_gpio_out[16*2+11:16*2+6]; + dsa_rx1_b_out_iob <= db_gpio_out[16*2+5:16*2+0]; + dsa_tx2_b_out_iob <= db_gpio_out[16*3+11:16*3+6]; + dsa_rx2_b_out_iob <= db_gpio_out[16*3+5:16*3+0]; + end + + assign DBB_CH1_TX_DSA_DATA = dsa_tx1_b_out_iob; + assign DBB_CH1_RX_DSA_DATA = dsa_rx1_b_out_iob; + assign DBB_CH2_TX_DSA_DATA = dsa_tx2_b_out_iob; + assign DBB_CH2_RX_DSA_DATA = dsa_rx2_b_out_iob; + + assign DBB_ATR_RX_1 = rx_atr_reg[2]; + assign DBB_ATR_RX_2 = rx_atr_reg[3]; + assign DBB_ATR_TX_1 = tx_atr_reg[2]; + assign DBB_ATR_TX_2 = tx_atr_reg[3]; + + assign DBB_MYK_GPIO_0 = 1'b0; + assign DBB_MYK_GPIO_1 = 1'b0; + assign DBB_MYK_GPIO_3 = 1'b0; + assign DBB_MYK_GPIO_4 = 1'b0; + assign DBB_MYK_GPIO_12 = 1'b0; + assign DBB_MYK_GPIO_13 = 1'b0; + assign DBB_MYK_GPIO_14 = 1'b0; + assign DBB_MYK_GPIO_15 = 1'b0; + +`endif + + /////////////////////////////////////////////////////// + // + // N3xx CORE + // + /////////////////////////////////////////////////////// + + wire [31:0] rx[NUM_CHANNELS-1:0]; + wire [31:0] tx[NUM_CHANNELS-1:0]; + wire [32*NUM_CHANNELS-1:0] rx_flat; + wire [32*NUM_CHANNELS-1:0] tx_flat; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[32*i+31:32*i] = rx[i]; + assign tx[i] = tx_flat[32*i+31:32*i]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets + `ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), + `else + .radio_clk(radio_clk), + .radio_rst(radio_rst), + `endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + // CPLD RX_LO TX_LO SPI + `ifndef N300 + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({5'b0,DBB_CPLD_PL_SPI_ADDR[1],DBB_CPLD_PL_SPI_ADDR[0],DBB_CPLD_PL_SPI_LE, + 5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat({DBB_CPLD_PL_SPI_SDI, + DBA_CPLD_PL_SPI_SDI}), + .miso_flat({DBB_CPLD_PL_SPI_SDO, + DBA_CPLD_PL_SPI_SDO}), + `else + .sclk_flat(DBA_CPLD_PL_SPI_SCLK), + .sen_flat({5'b0,DBA_CPLD_PL_SPI_ADDR[1],DBA_CPLD_PL_SPI_ADDR[0],DBA_CPLD_PL_SPI_LE}), + .mosi_flat(DBA_CPLD_PL_SPI_SDI), + .miso_flat(DBA_CPLD_PL_SPI_SDO), + `endif + // DRAM signals + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire [49:0] bRegPortInFlatA; + wire [33:0] bRegPortOutFlatA; + wire rx_a_valid; + wire tx_a_rfi; +`ifndef N300 + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatB; + wire rx_b_valid; + wire tx_b_rfi; +`endif + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_A_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_A_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_A_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_A_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBA_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_A_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_A_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBA_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSamples0I(rx[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[0][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[1][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSamples0I(tx[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[0][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[1][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[0] = rx_a_valid; + assign rx_stb[1] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + assign tx_stb[1] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + +`ifndef N300 + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore #( + .kInclWhiteRabbitTdc(INCL_WR_TDC) + ) dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CPLD_PL_SPI_ADDR[2]), //out std_logic + .JesdRefClk_p(USRPIO_B_MGTCLK_P), //in std_logic + .JesdRefClk_n(USRPIO_B_MGTCLK_N), //in std_logic + .aAdcRx_p(USRPIO_B_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(USRPIO_B_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(DBB_MYK_SYNC_IN_n), //out std_logic + .aDacTx_p(USRPIO_B_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(USRPIO_B_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(DBB_MYK_SYNC_OUT_n), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSamples0I(rx[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples0Q(rx[2][15:0]), //out std_logic_vector(15:0) + .sAdcDataSamples1I(rx[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSamples1Q(rx[3][15:0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSamples0I(tx[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples0Q(tx[2][15:0]), //in std_logic_vector(15:0) + .sDacDataSamples1I(tx[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSamples1Q(tx[3][15:0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(), //out std_logic + .sPpsToIob(), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'b0), //out std_logic_vector(1:0) + .sAdcSync(), //out std_logic + .sDacSync(), //out std_logic + .sSysRef(), //out std_logic + .rRpTransfer(), //out std_logic + .sSpTransfer(), //out std_logic + .rWrRpTransfer(), //out std_logic + .sWrSpTransfer() //out std_logic + ); + + assign rx_stb[2] = rx_b_valid; + assign rx_stb[3] = rx_b_valid; + assign tx_stb[2] = tx_b_rfi; + assign tx_stb[3] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); +`else + // Tie off second daughterboard interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_dbb_core ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY) + ); + +`endif + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule diff --git a/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs new file mode 100644 index 000000000..1296e68e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/Makefile.srcs @@ -0,0 +1,32 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +################################################## +# DB IFC Sources +################################################## +RHODIUM_DB_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/db_ifc/, \ +DbCore.vhd \ +DaughterboardRegs.vhd \ +ClockingRegs.vhd \ +PkgRhPersonality.vhd \ +PkgDaughterboardRegMap.vhd \ +PkgClockingRegMap.vhd \ +PkgJesdConfig.vhd \ +PkgAdcDacInterfaceTypes.vhd \ +RadioClocking.vhd \ +Jesd204bXcvrCore.edf \ +)) + +RHODIUM_TOP_SRCS = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +n3xx.v \ +)) + +RHODIUM_DB_CLOCKS_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_clocks.xdc \ +)) + +RHODIUM_DB_XDC = $(abspath $(addprefix $(BASE_DIR)/n3xx/dboards/rh/, \ +db_pins.xdc \ +db_timing.xdc \ +)) diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile new file mode 100644 index 000000000..ff1598894 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile @@ -0,0 +1,27 @@ +# +# Copyright 2018 Ettus Research, a National Instruments Company +# + +.PHONY: all clean + +SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v +SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh)) + +all: cpld-rhodium-revb.svf + +output_files/rhodium_top.pof: $(SRCS) + quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)" + quartus_fit rhodium_top + quartus_asm rhodium_top + quartus_sta rhodium_top + +cpld-rhodium-revb.svf: output_files/rhodium_top.pof + quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@ + +clean: + rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf + +a.out: $(SIM_SRCS) + iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS) + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v new file mode 100644 index 000000000..fb5f62328 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rh_tb.v @@ -0,0 +1,410 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rh_tb +// Simple testbench for rhodium_top +// This creates a rudimentary stimulus only, to allow results to be viewed +// in the waveform viewer +////////////////////////////////////////////////////////////////////// + +`timescale 1ns/1ps + + +module rh_tb; + +reg ADC_A_Over_Range_18, ADC_B_Over_Range_18; + +wire [13:0] usrpio_io; // TODO: use one of these as pl_spi_addr[3] + +wire CPLD_PS_SPI_LE_25, CPLD_PS_SPI_CLK_25, + CPLD_PS_ADDR0_25, CPLD_PS_ADDR1_25, CPLD_PS_SPI_SDI_25; +wire CPLD_PS_SPI_SDO_25; + +wire CPLD_PL_SPI_SDO_18; +wire CPLD_PL_SPI_LE_18, CPLD_PL_SPI_SCLK_18, + CPLD_PL_SPI_SDI_18, + CPLD_PL_SPI_ADDR0_18, CPLD_PL_SPI_ADDR1_18, + CPLD_PL_SPI_ADDR2_18, + CPLD_ATR_TX_18, CPLD_ATR_RX_18; +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. + +wire ADC_SPI_CS_L_18, ADC_SPI_SCLK_18; +wire ADC_SPI_SDIO_18; + +wire DAC_SPI_CS_L_18, DAC_SPI_SCLK_18; +wire DAC_SPI_SDIO_18; +reg DAC_Alarm_18; // TODO: drive to gpio? + +wire PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI; + + +reg LO_SYNC; + +wire CLKDIST_SPI_CS_L, + CLKDIST_SPI_SCLK; +wire CLKDIST_SPI_SDIO; + +wire Tx_DSA_C1, + Tx_DSA_C2, + Tx_DSA_C4, + Tx_DSA_C8, + Tx_DSA_C16; + wire Tx_DSA1_LE, + Tx_DSA2_LE; + wire Tx_Sw1_Ctrl_1, + Tx_Sw1_Ctrl_2, + Tx_Sw2_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_4, + Rx_LO_Input_Select, + Rx_LO_Filter_Sw_1, + Rx_LO_Filter_Sw_2, + Tx_LO_Input_Select, + Tx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2; +wire CLKDIST_Status_LD1, + CLKDIST_Status_LD2; +wire LOSYNTH_RX_MUXOUT, + LOSYNTH_TX_MUXOUT; + +wire LO_SPI_SCLK, + LO_SPI_SDI, + LO_TX_CS_L, + LO_RX_CS_L, + Rx_Sw1_Ctrl_1, + Rx_Sw1_Ctrl_2, + Rx_DSA_C1, + Rx_DSA_C2, + Rx_DSA_C4, + Rx_DSA_C8, + Rx_DSA_C16; + wire Rx_DSA1_LE, + Rx_DSA2_LE; + wire Rx_Sw2_Ctrl, + Rx_Sw3_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_4, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2; +wire LO_DSA_C1, + LO_DSA_C2, + LO_DSA_C4, + LO_DSA_C8, + LO_DSA_C16; +wire RxLO_DSA_LE, + TxLO_DSA_LE; +wire LODIST_Bd_SPI_CS_L, + LODIST_Bd_SPI_SDI, + LODIST_Bd_SPI_SCLK, + Tx_Sw5_Ctrl_1, + Tx_Sw5_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw6_Ctrl_2; +wire LODIST_Bd_IO1; +wire Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl; + + +parameter dly = 20; + +integer scnt; +integer acnt; +integer ccnt; +integer ccnt_max; + +reg ps_sck; +reg ps_mosi; +reg clkdis_cs_b; +reg cpld_ps_cs_b; +reg phdac_cs_b; +reg adc_cs_b; +reg dac_cs_b; + +reg pl_sck; +reg pl_mosi; +reg txlo_cs_b; +reg rxlo_cs_b; +reg lodis_cs_b; +reg cpld_pl_cs_b; + +task ps_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + ps_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_ps_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + ps_sck <= 1'b0; + ps_mosi <= shiftreg[23-i]; + #(dly); + ps_sck <= 1'b1; + #(dly); + end + ps_sck <= 1'b0; + #(dly); + cpld_ps_cs_b <= 1'b1; + #(dly); +end +endtask + +task pl_cpld_xfer; + input [1:0] tbl; + input [5:0] cmd; + input [15:0] data; + reg [23:0] shiftreg; + integer i; +begin + pl_sck <= 1'b0; + clkdis_cs_b <= 1'b1; + cpld_ps_cs_b <= 1'b1; + phdac_cs_b <= 1'b1; + adc_cs_b <= 1'b1; + dac_cs_b <= 1'b1; + txlo_cs_b <= 1'b1; + rxlo_cs_b <= 1'b1; + lodis_cs_b <= 1'b1; + cpld_pl_cs_b <= 1'b1; + shiftreg <= {tbl,cmd,data}; + #(dly); + cpld_pl_cs_b <= 1'b0; + #(dly); + for (i = 0; i < 24; i = i + 1) begin + pl_sck <= 1'b0; + pl_mosi <= shiftreg[23-i]; + #(dly); + pl_sck <= 1'b1; + #(dly); + end + pl_sck <= 1'b0; + #(dly); + cpld_pl_cs_b <= 1'b1; + #(dly); +end +endtask + +assign CPLD_PS_SPI_LE_25 = clkdis_cs_b; +assign CPLD_PS_ADDR0_25 = cpld_ps_cs_b; +assign CPLD_PS_ADDR1_25 = phdac_cs_b; +assign usrpio_io[12] = adc_cs_b; +assign usrpio_io[13] = dac_cs_b; +assign CPLD_PS_SPI_CLK_25 = ps_sck; +assign CPLD_PS_SPI_SDI_25 = ps_mosi; + +assign CPLD_PL_SPI_LE_18 = txlo_cs_b; +assign CPLD_PL_SPI_ADDR1_18 = rxlo_cs_b; +assign CPLD_PL_SPI_ADDR2_18 = lodis_cs_b; +assign CPLD_PL_SPI_ADDR0_18 = cpld_pl_cs_b; +assign CPLD_PL_SPI_SCLK_18 = pl_sck; +assign CPLD_PL_SPI_SDI_18 = pl_mosi; + +assign CLKDIST_Status_LD1 = 1'b0; +assign LOSYNTH_RX_MUXOUT = 1'b1; +assign LOSYNTH_TX_MUXOUT = 1'b1; + +initial +begin + $dumpfile("rh_cpld.vcd"); + $dumpvars; + // Check Signature register read-back + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + // Check Signature register is read-only + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b0}, 16'h1234); + #(dly) ps_cpld_xfer(2'b00, {5'b00000, 1'b1}, 16'h0000); + + // Load portions of lower RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0000); /* Write GAIN_BAND_SEL for lower table */ + #(dly) ps_cpld_xfer(2'b01, 6'd0, {2'd0, 5'd0, 5'd1, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd1, {2'd0, 5'd0, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd2, {2'd0, 5'd1, 5'd2, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd3, {2'd0, 5'd1, 5'd3, 1'b1, 3'd0}); + + // Load portions of upper RX gain table with some values + #(dly) ps_cpld_xfer(2'b00, {5'b00110, 1'b0}, 16'h0101); /* Write GAIN_BAND_SEL for upper table */ + #(dly) ps_cpld_xfer(2'b01, 6'd4, {2'd0, 5'd2, 5'd3, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd5, {2'd0, 5'd2, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd6, {2'd0, 5'd3, 5'd4, 1'b1, 3'd0}); + #(dly) ps_cpld_xfer(2'b01, 6'd7, {2'd0, 5'd3, 5'd5, 1'b1, 3'd0}); + + // Check RX gain table readback + #(dly) ps_cpld_xfer(2'b01, 6'd0, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd1, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd2, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd3, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd4, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd5, 16'h0); + #(dly) ps_cpld_xfer(2'b01, 6'd6, 16'h0); + + // Check can write a couple registers on PL side + // (Also make sure we're looking at the lower gain tables) + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0000); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0000); + + // Check retrieval of gain values for RX table and program DSAs + #(dly) pl_cpld_xfer(2'b01, 6'd2, {2'b0, 1'b1, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd3, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b01, 6'd1, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check writes to RXBS and TXBS registers + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h1CAB); + + // Check TX DSA programming is independent of RX DSA programming + #(dly) pl_cpld_xfer(2'b10, 6'd4, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + + // Check LO gain programming works + #(dly) pl_cpld_xfer(2'b11, 6'd5, {2'b0, 1'b1, 6'b0, 1'b0, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd7, {2'b0, 1'b0, 6'b0, 1'b1, 6'b0}); + #(dly) pl_cpld_xfer(2'b11, 6'd0, {2'b0, 1'b0, 6'b0, 1'b0, 6'b0}); + + // More checks for PL register writes + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h0ABC); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0CAB); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'hAA5C); + #(dly) pl_cpld_xfer(2'b00, {5'd8, 1'b0}, 16'h5A5C); + #(dly) pl_cpld_xfer(2'b00, {5'd6, 1'b0}, 16'h1C42); + + // Check low/high gain tables and independence of RX vs. TX + #(dly) pl_cpld_xfer(2'b01, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h104C); + #(dly) pl_cpld_xfer(2'b10, 6'd0, 16'h2040); + #(dly) pl_cpld_xfer(2'b00, {5'd7, 1'b0}, 16'h0C80); + #(dly) pl_cpld_xfer(2'b10, 6'd5, 16'h2040); + $finish; +end + +rhodium_top toplevel_inst(usrpio_io, // bank 1A, 1B and 6 +ADC_A_Over_Range_18, ADC_B_Over_Range_18, // bank 1A + +// bank 6 +CPLD_PS_SPI_LE_25, +CPLD_PS_SPI_CLK_25, +CPLD_PS_ADDR0_25, +CPLD_PS_ADDR1_25, +CPLD_PS_SPI_SDI_25, +CPLD_PS_SPI_SDO_25, +PHDAC_SPI_CS_L, PHDAC_SPI_SCLK, PHDAC_SPI_SDI, +LO_SYNC, + +// bank 2 +CPLD_PL_SPI_SDO_18, +CPLD_PL_SPI_LE_18, +CPLD_PL_SPI_SCLK_18, +CPLD_PL_SPI_SDI_18, +CPLD_PL_SPI_ADDR0_18, +CPLD_PL_SPI_ADDR1_18, +CPLD_PL_SPI_ADDR2_18, +CPLD_ATR_TX_18, +CPLD_ATR_RX_18, +ADC_SPI_CS_L_18, +ADC_SPI_SCLK_18, +ADC_SPI_SDIO_18, +DAC_SPI_CS_L_18, +DAC_SPI_SCLK_18, +DAC_SPI_SDIO_18, +DAC_Alarm_18, + +// bank 3 + +CLKDIST_SPI_CS_L, +CLKDIST_SPI_SCLK, +CLKDIST_SPI_SDIO, +Tx_DSA_C1, +Tx_DSA_C2, +Tx_DSA_C4, +Tx_DSA_C8, +Tx_DSA_C16, +Tx_DSA1_LE, +Tx_DSA2_LE, +Tx_Sw1_Ctrl_1, +Tx_Sw1_Ctrl_2, +Tx_Sw2_Ctrl_1, +Tx_Sw2_Ctrl_2, +Tx_Sw3_Ctrl_1, +Tx_Sw3_Ctrl_2, +Tx_Sw3_Ctrl_3, +Tx_Sw3_Ctrl_4, +Rx_LO_Input_Select, +Rx_LO_Filter_Sw_1, +Rx_LO_Filter_Sw_2, +Tx_LO_Input_Select, +Tx_LO_Filter_Sw_1, +Tx_LO_Filter_Sw_2, +CLKDIST_Status_LD1, +CLKDIST_Status_LD2, +LOSYNTH_RX_MUXOUT, +LOSYNTH_TX_MUXOUT, + +// bank 8 +LO_SPI_SCLK, // fans out to both rx & tx synths +LO_SPI_SDI, +LO_TX_CS_L, +LO_RX_CS_L, +Rx_Sw1_Ctrl_1, +Rx_Sw1_Ctrl_2, +Rx_DSA_C1, +Rx_DSA_C2, +Rx_DSA_C4, +Rx_DSA_C8, +Rx_DSA_C16, +Rx_DSA1_LE, +Rx_DSA2_LE, +Rx_Sw2_Ctrl, +Rx_Sw3_Ctrl_1, +Rx_Sw3_Ctrl_2, +Rx_Sw4_Ctrl_1, +Rx_Sw4_Ctrl_2, +Rx_Sw4_Ctrl_3, +Rx_Sw4_Ctrl_4, +Rx_Demod_ADJ_1, +Rx_Demod_ADJ_2, + +// bank 5 +LO_DSA_C1, +LO_DSA_C2, +LO_DSA_C4, +LO_DSA_C8, +LO_DSA_C16, +RxLO_DSA_LE, +TxLO_DSA_LE, +LODIST_Bd_SPI_CS_L, +LODIST_Bd_SPI_SDI, +LODIST_Bd_SPI_SCLK, +LODIST_Bd_IO1, +Tx_Sw5_Ctrl_1, +Tx_Sw5_Ctrl_2, +Rx_Sw6_Ctrl_1, +Rx_Sw6_Ctrl_2, + +Tx_HB_LB_Select, +Rx_HB_LB_Select, +Cal_iso_Sw_Ctrl + + +); +endmodule // rh_tb diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v new file mode 100644 index 000000000..b13eca846 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_ctrl.v @@ -0,0 +1,203 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_ctrl +// Description: +// Gain controller for Rhodium +// Provides 2 SPI slaves: +// The "load" slave is used to load the gain table with DSA settings for +// each index. +// The "ctrl" slave takes in a gain index and drives the DSAs with the +// setting found in the gain table. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT +* LOADER +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], dsa1[4:0], dsa2[4:0], wr_en, rsvd[2:0]} +* S {-------------------------------, rsvd[1:0], dsa1[4:0], dsa2[4:0], -------rsvd[3:0]} +* CTRL +* M {table_sel[1:0], gain_index[5:0], rsvd[1:0], wr_dsa1, -rsvd[5:0], wr_dsa2, rsvd[5:0]} +* S {-------------------------------, ---------rsvd[2:0], gain1[5:0], ---rsvd, gain2[5:0]} +*/ +module rhodium_gain_ctrl +#( + parameter TABLE_NUM = 2'b01 +) ( + input wire load_table_sel, + input wire load_sck, + input wire load_csb, + input wire load_mosi, + output wire load_miso, + input wire ctrl_table_sel, + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +/****************** +* Gain table loader +*******************/ +reg [4:0] load_bit_cnt; +reg [1:0] load_tbl; +reg [5:0] load_index; +reg [15:0] load_rd_data; +reg [4:0] load_dsa1; +reg [4:0] load_dsa2; +wire [4:0] load_dsa1_prev; +wire [4:0] load_dsa2_prev; + +assign load_miso = load_rd_data[15]; // Shift out on neg edge + +wire wr_en; +assign wr_en = (!load_csb) && (load_tbl == TABLE_NUM) && (load_bit_cnt == 20) && (load_mosi); + +// Cycle counter for where we are in protocol and shift register for input +always @ (posedge load_sck or posedge load_csb) +begin + if (load_csb) begin + load_bit_cnt <= 5'd0; + end else if (!load_csb) begin + {load_dsa1, load_dsa2} <= {load_dsa1[3:0], load_dsa2, load_mosi}; + + if (load_bit_cnt < 23) begin + load_bit_cnt <= load_bit_cnt + 5'd1; + end + if (load_bit_cnt < 8) begin + {load_tbl, load_index} <= {load_tbl[0], load_index, load_mosi}; + end + end +end + +// Readback shift register +always @ (negedge load_sck) +begin + if (load_bit_cnt == 9) begin + load_rd_data <= {load_dsa1_prev, load_dsa2_prev, 5'b000}; + end else begin + load_rd_data <= {load_rd_data[14:0], 1'b0}; + end +end + +/****************** +* Gain table RAM +*******************/ +wire [4:0] ctrl_dsa1; +wire [4:0] ctrl_dsa2; + +/* Use half of table for low band, other half for high band + * Software decides address mapping + */ +rhodium_gain_table gain_table( + .wr_clk(load_sck), + .wr_en(wr_en), + .wr_addr({load_table_sel, load_index}), + .wr_data({load_dsa1, load_dsa2}), + .wr_data_prev({load_dsa1_prev, load_dsa2_prev}), + .rd_clk(ctrl_sck), + .rd_addr({ctrl_table_sel, ctrl_index}), + .rd_data({ctrl_dsa1, ctrl_dsa2}) +); + +/****************** +* Gain control +*******************/ +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; + +reg [5:0] gain1; +reg [5:0] gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = !gain1_t ? ctrl_dsa1 : + (!gain2_t ? ctrl_dsa2 : + 5'b11111); + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + +endmodule // rhodium_gain_ctrl +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v new file mode 100644 index 000000000..abaca43ba --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_gain_table.v @@ -0,0 +1,54 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_gain_table +// Description: +// Simple dual port memory for use as gain table +// Implements a 128 x 16 bit dual-port RAM for storing 10-bit gain values. +// Write and read domains are independent. Data takes 1 cycle to become valid +// on the output of the RAM once written. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_gain_table +( + input wire wr_clk, + input wire wr_en, + input wire [6:0] wr_addr, + input wire [9:0] wr_data, + + // Read data for wr_addr (read-first/read-before-write): One cycle latency + output wire [9:0] wr_data_prev, + + input wire rd_clk, + input wire [6:0] rd_addr, + output wire [9:0] rd_data // Read data for rd_addr: One cycle latency +); + +reg [15:0] gain_table[127:0]; +reg [15:0] wr_data_prev_r; +reg [15:0] rd_data_r; + +assign wr_data_prev = wr_data_prev_r[15:6]; +assign rd_data = rd_data_r[15:6]; + +always @ (posedge wr_clk) +begin + if (wr_en) + gain_table[wr_addr] <= {wr_data, 6'b0}; + wr_data_prev_r <= gain_table[wr_addr]; +end + +always @ (posedge rd_clk) +begin + rd_data_r <= gain_table[rd_addr]; +end + + +endmodule // rhodium_gain_table +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v new file mode 100644 index 000000000..0c4ed4c52 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_lo_gain.v @@ -0,0 +1,124 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_lo_gain +// Description: +// LO Gain controller for Rhodium +// Implements a gain index register (not a table) +// +// Provides 1 SPI slave: +// The "ctrl" slave takes in a gain index and drives the DSA with that +// value. +// The SPI formats are provided below. +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +/** +* SPI DATA FORMAT (left-most bit is first) +* CTRL +* M {table_sel[1:0], rsvd, gain[4:0], rsvd[1:0], wr_dsa1, ------rsvd[5:0], wr_dsa2, ----rsvd[5:0] +* S {-------------------------------, --------------rsvd[3:0], gain1[4:0], -rsvd[1:0], gain2[4:0]} +*/ +module rhodium_lo_gain #( + parameter TABLE_NUM = 2'b01 +) ( + input wire ctrl_sck, + input wire ctrl_csb, + input wire ctrl_mosi, + output reg ctrl_miso, + output wire [4:0] dsa, + output reg dsa1_le, + output reg dsa2_le +); + +localparam CNT_GAIN1_DRIVE = 10, + CNT_DSA1_LE_RISE = 11, + CNT_DSA1_LE_FALL = 14, + CNT_GAIN1_RELEASE = 17; +localparam CNT_GAIN2_DRIVE = 17, + CNT_DSA2_LE_RISE = 18, + CNT_DSA2_LE_FALL = 21, + CNT_GAIN2_RELEASE = 24; + +reg [4:0] ctrl_bit_cnt; +reg [1:0] ctrl_tbl; +reg [5:0] ctrl_index; +reg [5:0] gain1, gain2; +reg gain1_t; +reg gain2_t; + +assign dsa = (!gain1_t | !gain2_t) ? ctrl_index[4:0] : 5'b11111; + +// Cycle counter for where we are in protocol and shift register for input +// Also controls timing of DSAs' latch enable signals +always @ (posedge ctrl_sck or posedge ctrl_csb) +begin + if (ctrl_csb) begin + ctrl_bit_cnt <= 5'd0; + dsa1_le <= 1'b0; + dsa2_le <= 1'b0; + gain1_t <= 1'b1; + gain2_t <= 1'b1; + end else if (!ctrl_csb) begin + if (ctrl_bit_cnt < 23) begin + ctrl_bit_cnt <= ctrl_bit_cnt + 5'd1; + end + + if (ctrl_bit_cnt < 8) begin + {ctrl_tbl, ctrl_index} <= {ctrl_tbl[0], ctrl_index, ctrl_mosi}; + end + + if (ctrl_tbl == TABLE_NUM) begin + if ((ctrl_bit_cnt == CNT_GAIN1_DRIVE) && (ctrl_mosi)) begin + gain1 <= ctrl_index; + gain1_t <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_RISE)) begin + dsa1_le <= 1'b1; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA1_LE_FALL)) begin + dsa1_le <= 1'b0; + end else if ((gain1_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN1_RELEASE)) begin + gain1_t <= 1'b1; + end + + if ((ctrl_bit_cnt == CNT_GAIN2_DRIVE) && (ctrl_mosi)) begin + gain2 <= ctrl_index; + gain2_t <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_RISE)) begin + dsa2_le <= 1'b1; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_DSA2_LE_FALL)) begin + dsa2_le <= 1'b0; + end else if ((gain2_t == 1'b0) && (ctrl_bit_cnt == CNT_GAIN2_RELEASE)) begin + gain2_t <= 1'b1; + end + end + end +end + +// SPI readback for ctrl bus, based on current bit count +always @ (negedge ctrl_sck) +begin + case (ctrl_bit_cnt) // Shift out on neg edge + 11: ctrl_miso <= gain1[5]; + 12: ctrl_miso <= gain1[4]; + 13: ctrl_miso <= gain1[3]; + 14: ctrl_miso <= gain1[2]; + 15: ctrl_miso <= gain1[1]; + 16: ctrl_miso <= gain1[0]; + 18: ctrl_miso <= gain2[5]; + 19: ctrl_miso <= gain2[4]; + 20: ctrl_miso <= gain2[3]; + 21: ctrl_miso <= gain2[2]; + 22: ctrl_miso <= gain2[1]; + 23: ctrl_miso <= gain2[0]; + default: ctrl_miso <= 1'b0; + endcase +end + + +endmodule // rhodium_lo_gain +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf new file mode 100644 index 000000000..5e1bf4d57 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "08:22:34 September 13, 2017" + +# Revisions + +PROJECT_REVISION = "rhodium_top" diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf new file mode 100644 index 000000000..e94f0bbc8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf @@ -0,0 +1,306 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition +# Date created = 08:22:34 September 13, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# rhodium_top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M04SAU169I7G +set_global_assignment -name TOP_LEVEL_ENTITY rhodium_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:22:34 SEPTEMBER 13, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D11 -to CPLD_PS_SPI_LE_25 +set_location_assignment PIN_F13 -to CPLD_PS_SPI_CLK_25 +set_location_assignment PIN_E10 -to CPLD_PS_ADDR0_25 +set_location_assignment PIN_A12 -to CPLD_PS_ADDR1_25 +set_location_assignment PIN_F12 -to CPLD_PS_SPI_SDI_25 +set_location_assignment PIN_F10 -to CPLD_PS_SPI_SDO_25 +set_location_assignment PIN_B1 -to ADC_A_Over_Range_18 +set_location_assignment PIN_D1 -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_A_Over_Range_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_B_Over_Range_18 +set_instance_assignment -name IO_STANDARD LVDS -to LO_SYNC +set_location_assignment PIN_G9 -to LO_SYNC +set_location_assignment PIN_G10 -to "LO_SYNC(n)" +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C2 -to ADC_SPI_CS_L_18 +set_location_assignment PIN_C1 -to ADC_SPI_SCLK_18 +set_location_assignment PIN_E3 -to ADC_SPI_SDIO_18 +set_location_assignment PIN_M5 -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_CS_L +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to ADC_SPI_SDIO_18 +set_location_assignment PIN_L5 -to CLKDIST_SPI_SCLK +set_location_assignment PIN_N5 -to CLKDIST_SPI_SDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_SPI_SDIO +set_location_assignment PIN_K6 -to CLKDIST_Status_LD1 +set_location_assignment PIN_J6 -to CLKDIST_Status_LD2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLKDIST_Status_LD2 +set_location_assignment PIN_M1 -to CPLD_ATR_TX_18 +set_location_assignment PIN_L1 -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_RX_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_ATR_TX_18 +set_location_assignment PIN_H6 -to CPLD_PL_SPI_ADDR0_18 +set_location_assignment PIN_K2 -to CPLD_PL_SPI_ADDR1_18 +set_location_assignment PIN_J2 -to CPLD_PL_SPI_ADDR2_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR0_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR1_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_ADDR2_18 +set_location_assignment PIN_K1 -to CPLD_PL_SPI_LE_18 +set_location_assignment PIN_H5 -to CPLD_PL_SPI_SCLK_18 +set_location_assignment PIN_L3 -to CPLD_PL_SPI_SDI_18 +set_location_assignment PIN_L2 -to CPLD_PL_SPI_SDO_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_LE_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDI_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to CPLD_PL_SPI_SDO_18 +set_location_assignment PIN_M2 -to DAC_Alarm_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_Alarm_18 +set_location_assignment PIN_N3 -to DAC_SPI_SDIO_18 +set_location_assignment PIN_N2 -to DAC_SPI_SCLK_18 +set_location_assignment PIN_M3 -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_CS_L_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SCLK_18 +set_instance_assignment -name IO_STANDARD "1.8 V" -to DAC_SPI_SDIO_18 +set_location_assignment PIN_M7 -to LOSYNTH_RX_MUXOUT +set_location_assignment PIN_N7 -to LOSYNTH_TX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_RX_MUXOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LOSYNTH_TX_MUXOUT +set_location_assignment PIN_E6 -to LO_RX_CS_L +set_location_assignment PIN_B2 -to LO_SPI_SCLK +set_location_assignment PIN_M4 -to LO_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_RX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_SPI_SDI +set_location_assignment PIN_K5 -to LO_TX_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_TX_CS_L +set_location_assignment PIN_B6 -to Rx_DSA1_LE +set_location_assignment PIN_A9 -to Rx_DSA2_LE +set_location_assignment PIN_D8 -to Rx_DSA_C1 +set_location_assignment PIN_D6 -to Rx_DSA_C2 +set_location_assignment PIN_A11 -to Rx_DSA_C4 +set_location_assignment PIN_B10 -to Rx_DSA_C8 +set_location_assignment PIN_A10 -to Rx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_DSA_C16 +set_location_assignment PIN_B3 -to Rx_Demod_ADJ_1 +set_location_assignment PIN_N4 -to Rx_Demod_ADJ_2 +set_location_assignment PIN_J5 -to Rx_LO_Filter_Sw_1 +set_location_assignment PIN_J7 -to Rx_LO_Filter_Sw_2 +set_location_assignment PIN_L4 -to Rx_LO_Input_Select +set_location_assignment PIN_A6 -to Rx_Sw1_Ctrl_1 +set_location_assignment PIN_A7 -to Rx_Sw1_Ctrl_2 +set_location_assignment PIN_A5 -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Demod_ADJ_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw2_Ctrl +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_LO_Input_Select +set_location_assignment PIN_A4 -to Rx_Sw3_Ctrl_1 +set_location_assignment PIN_A3 -to Rx_Sw3_Ctrl_2 +set_location_assignment PIN_C10 -to Rx_Sw4_Ctrl_1 +set_location_assignment PIN_A8 -to Rx_Sw4_Ctrl_2 +set_location_assignment PIN_B9 -to Rx_Sw4_Ctrl_3 +set_location_assignment PIN_C9 -to Rx_Sw4_Ctrl_4 +set_location_assignment PIN_K13 -to Tx_DSA1_LE +set_location_assignment PIN_K12 -to Tx_DSA2_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw4_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA1_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA2_LE +set_location_assignment PIN_H13 -to Tx_DSA_C1 +set_location_assignment PIN_H8 -to Tx_DSA_C2 +set_location_assignment PIN_J13 -to Tx_DSA_C4 +set_location_assignment PIN_H10 -to Tx_DSA_C8 +set_location_assignment PIN_J12 -to Tx_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_DSA_C16 +set_location_assignment PIN_N6 -to Tx_LO_Filter_Sw_1 +set_location_assignment PIN_N12 -to Tx_LO_Filter_Sw_2 +set_location_assignment PIN_N8 -to Tx_LO_Input_Select +set_location_assignment PIN_L10 -to Tx_Sw1_Ctrl_1 +set_location_assignment PIN_N10 -to Tx_Sw1_Ctrl_2 +set_location_assignment PIN_N11 -to Tx_Sw2_Ctrl_1 +set_location_assignment PIN_L11 -to Tx_Sw2_Ctrl_2 +set_location_assignment PIN_L12 -to Tx_Sw3_Ctrl_1 +set_location_assignment PIN_M13 -to Tx_Sw3_Ctrl_2 +set_location_assignment PIN_K11 -to Tx_Sw3_Ctrl_3 +set_location_assignment PIN_J9 -to Tx_Sw3_Ctrl_4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Filter_Sw_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_LO_Input_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw1_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw2_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_3 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw3_Ctrl_4 +set_location_assignment PIN_B11 -to PHDAC_SPI_CS_L +set_location_assignment PIN_C11 -to PHDAC_SPI_SCLK +set_location_assignment PIN_D9 -to PHDAC_SPI_SDI +set_location_assignment PIN_N9 -to LODIST_Bd_SPI_CS_L +set_location_assignment PIN_J8 -to LODIST_Bd_SPI_SCLK +set_location_assignment PIN_M9 -to LODIST_Bd_SPI_SDI +set_location_assignment PIN_L13 -to LO_DSA_C1 +set_location_assignment PIN_K10 -to LO_DSA_C2 +set_location_assignment PIN_H9 -to LO_DSA_C4 +set_location_assignment PIN_G12 -to LO_DSA_C8 +set_location_assignment PIN_G13 -to LO_DSA_C16 +set_location_assignment PIN_J10 -to RxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_CS_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LODIST_Bd_SPI_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C4 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LO_DSA_C16 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RxLO_DSA_LE +set_location_assignment PIN_B4 -to Rx_Sw6_Ctrl_1 +set_location_assignment PIN_B5 -to Rx_Sw6_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_Sw6_Ctrl_2 +set_location_assignment PIN_M8 -to TxLO_DSA_LE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TxLO_DSA_LE +set_location_assignment PIN_M11 -to Tx_Sw5_Ctrl_1 +set_location_assignment PIN_M12 -to Tx_Sw5_Ctrl_2 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_Sw5_Ctrl_2 +set_location_assignment PIN_D12 -to Cal_iso_Sw_Ctrl +set_location_assignment PIN_K8 -to LODIST_Bd_IO1 +set_location_assignment PIN_M10 -to Tx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Tx_HB_LB_Select +set_location_assignment PIN_E8 -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Rx_HB_LB_Select +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_CS_L +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SCLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to PHDAC_SPI_SDI +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR0_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_ADDR1_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_CLK_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_LE_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDI_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CPLD_PS_SPI_SDO_25 +set_instance_assignment -name IO_STANDARD "2.5 V" -to Cal_iso_Sw_Ctrl +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to LODIST_Bd_IO1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_location_assignment PIN_E4 -to usrp_io[0] +set_location_assignment PIN_G5 -to usrp_io[1] +set_location_assignment PIN_H4 -to usrp_io[2] +set_location_assignment PIN_J1 -to usrp_io[3] +set_location_assignment PIN_F1 -to usrp_io[4] +set_location_assignment PIN_C12 -to usrp_io[5] +set_location_assignment PIN_C13 -to usrp_io[6] +set_location_assignment PIN_E12 -to usrp_io[7] +set_location_assignment PIN_E13 -to usrp_io[8] +set_location_assignment PIN_B13 -to usrp_io[9] +set_location_assignment PIN_F9 -to usrp_io[10] +set_location_assignment PIN_B12 -to usrp_io[11] +set_location_assignment PIN_E9 -to usrp_io[12] +set_location_assignment PIN_F8 -to usrp_io[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to usrp_io[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to usrp_io[13] +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH rh_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME rh_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "9000 ns" -section_id rh_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME rh_tb -section_id rh_tb +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name VERILOG_FILE rhodium_top.v +set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v +set_global_assignment -name VERILOG_FILE rhodium_gain_table.v +set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v +set_global_assignment -name VERILOG_FILE rh_tb.v +set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb + + +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc new file mode 100644 index 000000000..4b00a5053 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.sdc @@ -0,0 +1,415 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Copyright 2019 Ettus Research, A National Instruments Company +# +# Timing constraints for Rhodium's MAX 10 board controller + +set_time_format -unit ns -decimal_places 3 + +# Some constants for constraining the design with the FPGA-centric method: +# Maximum trace propagation delay is assumed to be 0.6 ns on any traces +# to on-dboard slaves +set board_delay 0.600 +set clk_uncertainty 0.150 + +############################################################################### +# Clocks +############################################################################### + +# The PS SPI clock is maximum 10 MHz. It is driven from another source and +# provided with the data. +# CPLD_PS_SPI_CLK_25: 8 MHz +set sclk_ps_period 125.000 + +# Create clock for the PS's SPI interface +create_clock -name sclk_ps -period $sclk_ps_period \ + [get_ports CPLD_PS_SPI_CLK_25] + +# The PL SPI clock is split into two pieces. For the normal case, the clock +# frequency is 10 MHz. This is for any read operations. +# +# CPLD_PL_SPI_SCLK_18 pass through / read back ONLY: 10 MHz +set sclk_pl_period 100.000 +create_clock -name sclk_pl -period $sclk_pl_period \ + [get_ports CPLD_PL_SPI_SCLK_18] + +# We can go faster for the PL writes to the internal registers and LOs. +# This rate is not supported for readback, but it helps with getting the DSA +# settings and LO settings in faster. +# CPLD_PL_SPI_SCLK_18 internal ONLY: 25 MHz +set sclk_pl_wr_period 40.000 +create_clock -name sclk_pl_wr -period $sclk_pl_wr_period \ + [get_ports CPLD_PL_SPI_SCLK_18] -add + +# Output clocks for the MAX 10's SPI master interfaces (1 for each slave IC) +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name clkdist_clk [get_ports CLKDIST_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name adc_clk [get_ports ADC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name dac_clk [get_ports DAC_SPI_SCLK_18] +create_generated_clock -source [get_ports CPLD_PS_SPI_CLK_25] \ + -name phdac_clk [get_ports PHDAC_SPI_SCLK] + +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lo_clk [get_ports LO_SPI_SCLK] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name lo_wr_clk [get_ports LO_SPI_SCLK] -add +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl] \ + -name lodist_clk [get_ports LODIST_Bd_SPI_SCLK] + +# Virtual clock for DSA writes for skew calculations +#create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|clk] +create_generated_clock -source [get_ports CPLD_PL_SPI_SCLK_18] \ + -master_clock [get_clocks sclk_pl_wr] \ + -name dsa_reg_clk [get_pins lo_gain_table\|dsa1_le\|q] + +create_generated_clock -source [get_pins lo_gain_table\|dsa1_le\|q] \ + -name dsa_clk [get_ports RxLO_DSA_LE] + +# PL's pass through clock doesn't interact with internal clock +set_clock_groups -physically_exclusive \ + -group [get_clocks {sclk_pl_wr lo_wr_clk dsa_reg_clk dsa_clk}] \ + -group [get_clocks {sclk_pl lo_clk lodist_clk}] + +set_clock_groups -asynchronous \ + -group [get_clocks {sclk_ps clkdist_clk adc_clk dac_clk phdac_clk}] \ + -group [get_clocks {sclk_pl sclk_pl_wr lo_clk lodist_clk}] + +set_clock_uncertainty -to [get_clocks {sclk_ps sclk_pl sclk_pl_wr clkdist_clk + adc_clk dac_clk phdac_clk lo_clk lo_wr_clk lodist_clk dsa_reg_clk dsa_clk}] \ + $clk_uncertainty + +############################################################################### +# Timing Budget Calculations +############################################################################### +# Here we carve out some timing budget for the master's SPI interfaces. +# The master will use these values to time its SPI interface. +# The PL's write-only values are smaller because there are no external chip +# dependencies. +set setup_ps 25 +set hold_ps 30 + +# PL SPI is constrained on the master with an allowed skew value of +/- 3 ns +# relative to the launch clock +# Increase to 5 ns here for more margin +set pl_skew 5 + +# Clocks are nominally a 50% duty cycle, so difference between latch and +# launch is half a period, so subtract allowed skew from that for setup/hold +# specification. The half period is due to launch being the falling edge and +# latch being the rising edge. +set setup_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set hold_pl [expr {$sclk_pl_period / 2 - $pl_skew}] +set setup_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] +set hold_pl_wr [expr {$sclk_pl_wr_period / 2 - $pl_skew}] + +# Calculate input delays relative to falling edge (launch) +# Min is hold time after previous rising edge (previous latch) +# Max is setup time before next rising edge (next latch) +set input_delay_min_ps [expr {-$sclk_ps_period / 2 + $hold_ps}] +set input_delay_max_ps [expr {$sclk_ps_period / 2 - $setup_ps}] +set input_delay_min_pl [expr {-$sclk_pl_period / 2 + $hold_pl}] +set input_delay_max_pl [expr {$sclk_pl_period / 2 - $setup_pl}] +set input_delay_min_pl_wr [expr {-$sclk_pl_wr_period / 2 + $hold_pl_wr}] +set input_delay_max_pl_wr [expr {$sclk_pl_wr_period / 2 - $setup_pl_wr}] + +# Again, carve out timing budget for master's SPI interface +# Readback on the master will depend on clk-to-q of our slave. +# These values will need to be at least as large as the worst slave. +# Clock arrival at the slave will be delayed by propagation through the MAX 10 +# Data to the MAX 10's input port will be further delayed by slave's clk-to-q +# On top of that, we then need budget for the data to cross the MAX 10, head +# out the I/O, and propagate to the master's pin. Then the master will need +# some budget for setup time. +# +# Here is what we'll budget: +# Clk propagation to I/O: 7 ns +# Clk trace delay: 1 ns +# Worst-case chip clk-to-q: 10 ns +# Data trace delay: 1 ns +# Data propagation delay from input pin to output pin: 8 ns +# Total clk-to-q from MAX 10 sclk input to MAX 10 output: 27 ns +# +# Then master's budget is 23 ns for clock delay + data delay + setup time +set clk_q_max_ps 27.000 + +# For the PL, the worst-case chip changes to 2 ns, so there is more budget +set clk_q_max_pl 20.000 + +# clk-to-q determines one side of the data invalid window +# The maximum output delay is simply latch edge - clk-to-q +# Launch is falling edge, and latch is rising edge, so... +set output_delay_max_ps [expr {$sclk_ps_period / 2 - $clk_q_max_ps}] +set output_delay_max_pl [expr {$sclk_pl_period / 2 - $clk_q_max_pl}] + +# The minimum output delay represents the other edge of the data invalid +# window. Our clock is likely quite delayed already, but add a little more +# margin for hold time. +set output_delay_min_ps -5.000 +set output_delay_min_pl -5.000 + + +############################################################################### +# I/O groups (for reference later) +############################################################################### + +# Chip selects +set ps_csb [get_ports { + CPLD_PS_ADDR0_25 + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] +}] +set pl_csb [get_ports { + CPLD_PL_SPI_ADDR0_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_LE_18 +}] + +# Data for internal PL SPI +set pl_src [get_ports { + CPLD_PL_SPI_SDI_18 +}] + +# Passthrough inputs (forward direction) +# CPLD_PS_SPI_CLK_25 and CPLD_PL_SPI_SCLK_18 are special +set ps_pt_src [get_ports {CPLD_PS_SPI_LE_25 + usrp_io[12] + usrp_io[13] + CPLD_PS_ADDR1_25 + CPLD_PS_SPI_SDI_25 + }] + +set pl_pt_src [get_ports {CPLD_PL_SPI_LE_18 + CPLD_PL_SPI_ADDR1_18 + CPLD_PL_SPI_ADDR2_18 + CPLD_PL_SPI_SDI_18 + }] + +# Passthrough outputs (forward direction) +# And inputs from the SPI slaves (readback direction) +set clkdist_spi_out [get_ports { + CLKDIST_SPI_CS_L + CLKDIST_SPI_SDIO +}] + +set clkdist_spi_in [get_ports { + CLKDIST_SPI_SDIO +}] + +set phdac_spi [get_ports { + PHDAC_SPI_CS_L + PHDAC_SPI_SDI +}] + +set dac_spi_out [get_ports { + DAC_SPI_CS_L_18 + DAC_SPI_SDIO_18 +}] + +set dac_spi_in [get_ports { + DAC_SPI_SDIO_18 +}] + +set adc_spi_out [get_ports { + ADC_SPI_CS_L_18 + ADC_SPI_SDIO_18 +}] + +set adc_spi_in [get_ports { + ADC_SPI_SDIO_18 +}] + +set lo_spi_out [get_ports { + LO_TX_CS_L + LO_RX_CS_L + LO_SPI_SDI +}] + +set lo_spi_in [get_ports { + LOSYNTH_RX_MUXOUT + LOSYNTH_TX_MUXOUT +}] + +set lodist_spi_out [get_ports { + LODIST_Bd_SPI_CS_L + LODIST_Bd_SPI_SDI +}] + +# Readback outputs +set ps_rb_out [get_ports CPLD_PS_SPI_SDO_25] +set pl_rb_out [get_ports CPLD_PL_SPI_SDO_18] + +############################################################################## +# Chip-selects provide async resets +############################################################################## +set_false_path -from $ps_csb -to [get_pins *|clrn] +set_false_path -from $pl_csb -to [get_pins *|clrn] + +# Also ignore setup/hold analysis for chip-selects affecting readback path +# These are available many cycles before readback begins and have +# combinatorial paths to the output +set_false_path -from $ps_csb -to $ps_rb_out +set_false_path -from $pl_csb -to $pl_rb_out + +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps \ + [get_ports CPLD_PS_ADDR0_25] +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps \ + [get_ports CPLD_PS_ADDR0_25] + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl \ + [get_ports CPLD_PL_SPI_ADDR0_18] + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr \ + [get_ports CPLD_PL_SPI_ADDR0_18] -add + + +############################################################################## +# Input delays from SPI master +############################################################################## +set_input_delay -clock sclk_ps -clock_fall -max $input_delay_max_ps $ps_pt_src +set_input_delay -clock sclk_ps -clock_fall -min $input_delay_min_ps $ps_pt_src + +set_input_delay -clock sclk_pl -clock_fall -max $input_delay_max_pl $pl_pt_src +set_input_delay -clock sclk_pl -clock_fall -min $input_delay_min_pl $pl_pt_src + +set_input_delay -clock sclk_pl_wr -clock_fall -max $input_delay_max_pl_wr $pl_src -add +set_input_delay -clock sclk_pl_wr -clock_fall -min $input_delay_min_pl_wr $pl_src -add + +############################################################################## +# Output delays to each SPI slave (uses setup/hold times from data sheet) +############################################################################## +set adc_setup 4 +set adc_hold 2 +set_output_delay -clock adc_clk -max [expr {$adc_setup + $board_delay}] \ + $adc_spi_out +set_output_delay -clock adc_clk -min [expr {-$adc_hold - $board_delay}] \ + $adc_spi_out + +set dac_setup 10 +set dac_hold 5 +set_output_delay -clock dac_clk -max [expr {$dac_setup + $board_delay}] \ + $dac_spi_out +set_output_delay -clock dac_clk -min [expr {-$dac_hold - $board_delay}] \ + $dac_spi_out + +set phdac_setup 5 +set phdac_hold 5 +set_output_delay -clock phdac_clk -max [expr {$phdac_setup + $board_delay}] \ + $phdac_spi +set_output_delay -clock phdac_clk -min [expr {-$phdac_hold - $board_delay}] \ + $phdac_spi + +set clkdist_setup 10 +set clkdist_hold 10 +set_output_delay -clock clkdist_clk -max [expr {$clkdist_setup + $board_delay}] \ + $clkdist_spi_out +set_output_delay -clock clkdist_clk -min [expr {-$clkdist_hold - $board_delay}] \ + $clkdist_spi_out + +set lo_setup 2 +set lo_hold 2 +set_output_delay -clock lo_wr_clk -max [expr {$lo_setup + $board_delay}] \ + $lo_spi_out +set_output_delay -clock lo_wr_clk -min [expr {-$lo_hold - $board_delay}] \ + $lo_spi_out + +############################################################################## +# Input delays from each SPI slave (uses clk-to-q times from data sheet) +# One board delay for clock, another for data +############################################################################## +set lo_clk_q 2 +set_input_delay -clock lo_clk -clock_fall -max [expr {$lo_clk_q + $board_delay + $board_delay}] \ + $lo_spi_in +set_input_delay -clock lo_clk -clock_fall -min 0 \ + $lo_spi_in + +set adc_clk_q 10 +set dac_clk_q 10 +set clkdist_clk_q 10 +set_input_delay -clock adc_clk -clock_fall -max [expr {$adc_clk_q + $board_delay + $board_delay}] \ + $adc_spi_in +set_input_delay -clock adc_clk -clock_fall -min 0 \ + $adc_spi_in +set_input_delay -clock dac_clk -clock_fall -max [expr {$dac_clk_q + $board_delay + $board_delay}] \ + $dac_spi_in +set_input_delay -clock dac_clk -clock_fall -min 0 \ + $dac_spi_in +set_input_delay -clock clkdist_clk -clock_fall -max [expr {$clkdist_clk_q + $board_delay + $board_delay}] \ + $clkdist_spi_in +set_input_delay -clock clkdist_clk -clock_fall -min 0 \ + $clkdist_spi_in + + +############################################################################## +# Output delays for readback path +############################################################################## +set_output_delay -clock sclk_ps -max $output_delay_max_ps $ps_rb_out +set_output_delay -clock sclk_ps -min $output_delay_min_ps $ps_rb_out + +set_output_delay -clock sclk_pl -max $output_delay_max_pl $pl_rb_out +set_output_delay -clock sclk_pl -min $output_delay_min_pl $pl_rb_out + +############################################################################## +# GPIOs and DSAs +# Outputs that aren't timing-critical +############################################################################## +set gpos [get_ports {Tx_Sw* + Rx_LO_* + Tx_LO_* + Rx_Sw* + Rx_Demod_* + Tx_HB_LB_Select + Rx_HB_LB_Select + Cal_iso_Sw_Ctrl + LODIST_Bd_IO1 + }] + +# Inputs that aren't timing-critical +set gpis [get_ports {LO_SYNC + CPLD_ATR_TX_18 + CPLD_ATR_RX_18 + DAC_Alarm_18 + CLKDIST_Status* + LODIST_Bd_IO1 + }] + +# DSAs (special skew needs) +# RxLO_DSA_LE used for skew basis +set dsas [get_ports {Tx_DSA* + Rx_DSA* + TxLO_DSA* + LO_DSA* + }] + +# Just do false paths for gpios +set_false_path -to $gpos +set_false_path -from $gpis + +# Unused +set_false_path -to $lodist_spi_out + +# DSA skew timing +# Earlier, we created a "clock" for one of the DSA latch enable signals +# Use set_output_delay to constrain skew around the latch enable +# set_multicycle_path is used to make latch clock = launch clock for setup +# Constrain skew to 8 ns -- controller nominally does 120 ns minimum between +# edges, and 100 ns is the DSA's requirement for setup/hold +set dsa_skew 8.0 +set_output_delay -clock dsa_clk -max -$dsa_skew $dsas +set_output_delay -clock dsa_clk -min $dsa_skew $dsas +set_multicycle_path -start -setup 0 -to $dsas + +set_max_delay -from [get_ports CPLD_ATR_TX_18] \ + -to [get_ports {Tx_Sw1_Ctrl_1 Tx_Sw1_Ctrl_2}] 10.0 + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v new file mode 100644 index 000000000..1d0d640da --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v @@ -0,0 +1,605 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rhodium_top +////////////////////////////////////////////////////////////////////// + +`default_nettype none + +module rhodium_top( + +input [13:0] usrp_io, // bank 1A, 1B and 6 + +input ADC_A_Over_Range_18, input ADC_B_Over_Range_18, // bank 1A + +// bank 6 +input CPLD_PS_SPI_LE_25, +input CPLD_PS_SPI_CLK_25, +input CPLD_PS_ADDR0_25, +input CPLD_PS_ADDR1_25, +input CPLD_PS_SPI_SDI_25, +output reg CPLD_PS_SPI_SDO_25, +output PHDAC_SPI_CS_L, +output PHDAC_SPI_SCLK, +output PHDAC_SPI_SDI, +input LO_SYNC, + +// bank 2 +output reg CPLD_PL_SPI_SDO_18, +input CPLD_PL_SPI_LE_18, +input CPLD_PL_SPI_SCLK_18, +input CPLD_PL_SPI_SDI_18, +input CPLD_PL_SPI_ADDR0_18, +input CPLD_PL_SPI_ADDR1_18, +input CPLD_PL_SPI_ADDR2_18, +// NOTE: TxRx front-end switches are driven direct from the motherboard, so these ATR +// lines have no function at this time. +input CPLD_ATR_TX_18, +input CPLD_ATR_RX_18, +output ADC_SPI_CS_L_18, +output ADC_SPI_SCLK_18, +inout ADC_SPI_SDIO_18, +output DAC_SPI_CS_L_18, +output DAC_SPI_SCLK_18, +inout DAC_SPI_SDIO_18, +input DAC_Alarm_18, // TODO: drive to gpio? + +// bank 3 + +output CLKDIST_SPI_CS_L, +output CLKDIST_SPI_SCLK, +inout CLKDIST_SPI_SDIO, +output Tx_DSA_C1, +output Tx_DSA_C2, +output Tx_DSA_C4, +output Tx_DSA_C8, +output Tx_DSA_C16, +output Tx_DSA1_LE, +output Tx_DSA2_LE, +output Tx_Sw1_Ctrl_1, +output Tx_Sw1_Ctrl_2, +output Tx_Sw2_Ctrl_1, +output Tx_Sw2_Ctrl_2, +output Tx_Sw3_Ctrl_1, +output Tx_Sw3_Ctrl_2, +output Tx_Sw3_Ctrl_3, +output Tx_Sw3_Ctrl_4, +output Rx_LO_Input_Select, +output Rx_LO_Filter_Sw_1, +output Rx_LO_Filter_Sw_2, +output Tx_LO_Input_Select, +output Tx_LO_Filter_Sw_1, +output Tx_LO_Filter_Sw_2, +input CLKDIST_Status_LD1, +input CLKDIST_Status_LD2, +input LOSYNTH_RX_MUXOUT, +input LOSYNTH_TX_MUXOUT, + +// bank 8 +output LO_SPI_SCLK, // fans out to both rx & tx synths +output LO_SPI_SDI, +output LO_TX_CS_L, +output LO_RX_CS_L, +output Rx_Sw1_Ctrl_1, +output Rx_Sw1_Ctrl_2, +output Rx_DSA_C1, +output Rx_DSA_C2, +output Rx_DSA_C4, +output Rx_DSA_C8, +output Rx_DSA_C16, +output Rx_DSA1_LE, +output Rx_DSA2_LE, +output Rx_Sw2_Ctrl, +output Rx_Sw3_Ctrl_1, +output Rx_Sw3_Ctrl_2, +output Rx_Sw4_Ctrl_1, +output Rx_Sw4_Ctrl_2, +output Rx_Sw4_Ctrl_3, +output Rx_Sw4_Ctrl_4, +output Rx_Demod_ADJ_1, +output Rx_Demod_ADJ_2, + +// bank 5 +output LO_DSA_C1, +output LO_DSA_C2, +output LO_DSA_C4, +output LO_DSA_C8, +output LO_DSA_C16, +output RxLO_DSA_LE, +output TxLO_DSA_LE, +output LODIST_Bd_SPI_CS_L, +output LODIST_Bd_SPI_SDI, +output LODIST_Bd_SPI_SCLK, +inout LODIST_Bd_IO1, +output Tx_Sw5_Ctrl_1, +output Tx_Sw5_Ctrl_2, +output Rx_Sw6_Ctrl_1, +output Rx_Sw6_Ctrl_2, + +output Tx_HB_LB_Select, +output Rx_HB_LB_Select, +output Cal_iso_Sw_Ctrl + + +); + +/* PS SPI */ + +localparam GIT_HASH = 36'h`GIT_HASH; +localparam PROD_SIGNATURE = 16'h0045; // Product signature (Rhodium atomic number in BCD) +localparam REVISION_MINOR = 16'h0002; +localparam REVISION_MAJOR = 16'h0004; +localparam CPLD_BUILD_LSB = GIT_HASH[15:0]; // Build code LSB +localparam CPLD_BUILD_MSB = GIT_HASH[31:16]; // Build code MSB +localparam PSADDR_SIGNATURE = 3'd0; +localparam PSADDR_REV_MINOR = 3'd1; // Minor version register +localparam PSADDR_REV_MAJOR = 3'd2; // Major version register +localparam PSADDR_BUILD_LSB = 3'd3; +localparam PSADDR_BUILD_MSB = 3'd4; +localparam PSADDR_SCRATCH = 3'd5; // scratchpad register +localparam PSADDR_GAIN_SEL = 3'd6; // band select for gain table loader +localparam PSADDR_DAC_ALARM = 3'd7; // DAC alarm pin register + +// Sub-device selection for PS SPI +localparam PS_CPLD_REGS = 2'b00; +localparam GAIN_TABLE_RX = 2'b01; +localparam GAIN_TABLE_TX = 2'b10; +localparam GAIN_TABLE_LO = 2'b11; + +// Setting to put TX SW1 in isolation mode +localparam [1:0] TX_SW1_TERM = 2'b11; + +wire clkdis_cs_b = CPLD_PS_SPI_LE_25; +wire cpld_ps_cs_b = CPLD_PS_ADDR0_25; +wire phdac_cs_b = CPLD_PS_ADDR1_25; +wire adc_cs_b = usrp_io[12]; +wire dac_cs_b = usrp_io[13]; + +// CPLD PS SPI format (left-most bit first): +// {table_sel[1:0], rsvd, reg_addr[3:0], rnw, data[15:0]} +wire [1:0] cpld_ps_table_sel; +wire [6:0] cpld_ps_spi_addr; +wire cpld_ps_spi_rnw; +reg [7:0] cpld_ps_spi_cmd; +reg [15:0] cpld_ps_spi_rdata; +reg [14:0] cpld_ps_spi_wdata; +reg cpld_ps_spi_sdo; +reg [4:0] cpld_ps_cnt; + +assign {cpld_ps_spi_addr, cpld_ps_spi_rnw} = cpld_ps_spi_cmd; + +// CPLD registers +reg [15:0] spad; +reg [15:0] gain_load_sel; + +// Double sync. the DAC ALARM pin (async). +reg dac_alarm_ms, dac_alarm = 0; +always @(posedge CPLD_PS_SPI_CLK_25) begin + {dac_alarm, dac_alarm_ms} <= {dac_alarm_ms, DAC_Alarm_18}; +end + +wire rx_gain_load_tbl_sel; +wire rx_gain_load_miso; +wire rx_gain_ctrl_tbl_sel; +wire rx_gain_ctrl_miso; +wire tx_gain_load_tbl_sel; +wire tx_gain_load_miso; +wire tx_gain_ctrl_tbl_sel; +wire tx_gain_ctrl_miso; +wire lo_gain_ctrl_miso; + +assign rx_gain_load_tbl_sel = gain_load_sel[0]; +assign tx_gain_load_tbl_sel = gain_load_sel[8]; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge cpld_ps_cs_b) +begin + if (cpld_ps_cs_b) begin + cpld_ps_cnt <= 5'd0; + end else if (!cpld_ps_cs_b) begin + if (cpld_ps_cnt < 8) begin // Address / command + cpld_ps_spi_cmd <= {cpld_ps_spi_cmd[6:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (cpld_ps_cnt < 23) begin // Shift in write data + cpld_ps_spi_wdata <= {cpld_ps_spi_wdata[13:0], CPLD_PS_SPI_SDI_25}; + cpld_ps_cnt <= cpld_ps_cnt + 5'd1; + end else if (!cpld_ps_spi_rnw && cpld_ps_cnt == 23 && cpld_ps_spi_addr[6:5] == PS_CPLD_REGS) begin // Write + case (cpld_ps_spi_addr[2:0]) + PSADDR_SIGNATURE: ; + PSADDR_REV_MINOR: ; + PSADDR_REV_MAJOR: ; + PSADDR_BUILD_LSB: ; + PSADDR_BUILD_MSB: ; + PSADDR_SCRATCH: spad <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + PSADDR_GAIN_SEL: gain_load_sel <= {cpld_ps_spi_wdata, CPLD_PS_SPI_SDI_25}; + endcase + end + if (cpld_ps_cnt == 7) begin // Set up read one cycle earlier + case (cpld_ps_spi_cmd[2:0]) + + PSADDR_SIGNATURE: cpld_ps_spi_rdata <= PROD_SIGNATURE; + PSADDR_REV_MINOR: cpld_ps_spi_rdata <= REVISION_MINOR; + PSADDR_REV_MAJOR: cpld_ps_spi_rdata <= REVISION_MAJOR; + PSADDR_BUILD_LSB: cpld_ps_spi_rdata <= CPLD_BUILD_LSB; + PSADDR_BUILD_MSB: cpld_ps_spi_rdata <= CPLD_BUILD_MSB; + PSADDR_SCRATCH: cpld_ps_spi_rdata <= spad; + PSADDR_GAIN_SEL: cpld_ps_spi_rdata <= gain_load_sel; + PSADDR_DAC_ALARM: cpld_ps_spi_rdata <= {15'b0, dac_alarm}; + endcase + end else begin + cpld_ps_spi_rdata <= {cpld_ps_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PS_SPI_CLK_25) +begin + cpld_ps_spi_sdo <= cpld_ps_spi_rdata[15]; // Shift out on negative edge +end + +// CLKDIST 3-wire to 4-wire +reg [4:0] clkdis_cnt; +reg clkdis_rd_pre, clkdis_rd, clkdis_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_cnt <= 5'd0; + clkdis_rd <= 1'b0; + clkdis_rd_pre <= 1'b0; + end else if (!clkdis_cs_b) begin + if (clkdis_cnt < 23) + clkdis_cnt <= clkdis_cnt + 5'd1; + + if (clkdis_cnt == 5'd0) // Check if read + clkdis_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (clkdis_cnt == 5'd15) + clkdis_rd <= clkdis_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge clkdis_cs_b) +begin + if (clkdis_cs_b) begin + clkdis_sdio_t <= 1'b0; + end else begin + clkdis_sdio_t <= clkdis_rd; + end +end + +// ADC 3-wire to 4-wire +reg [4:0] adc_cnt; +reg adc_rd_pre, adc_rd, adc_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_cnt <= 5'd0; + adc_rd <= 1'b0; + adc_rd_pre <= 1'b0; + end else if (!adc_cs_b) begin + if (adc_cnt < 23) + adc_cnt <= adc_cnt + 5'd1; + + if (adc_cnt == 5'd0) // Check if read + adc_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (adc_cnt == 5'd15) + adc_rd <= adc_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge adc_cs_b) +begin + if (adc_cs_b) begin + adc_sdio_t <= 1'b0; + end else begin + adc_sdio_t <= adc_rd; + end +end + +// DAC 3-wire to 4-wire +reg [4:0] dac_cnt; +reg dac_rd_pre, dac_rd, dac_sdio_t; + +always @(posedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_cnt <= 5'd0; + dac_rd <= 1'b0; + dac_rd_pre <= 1'b0; + end else if (!dac_cs_b) begin + if (dac_cnt < 23) + dac_cnt <= dac_cnt + 5'd1; + + if (dac_cnt == 5'd0) // Check if read + dac_rd_pre <= CPLD_PS_SPI_SDI_25; + + if (dac_cnt == 5'd7) + dac_rd <= dac_rd_pre; + end +end + +always @(negedge CPLD_PS_SPI_CLK_25 or posedge dac_cs_b) +begin + if (dac_cs_b) begin + dac_sdio_t <= 1'b0; + end else begin + dac_sdio_t <= dac_rd; + end +end + +// multiplexed slave device SPI ports +wire phdac_sck, phdac_sdi; +wire clkdis_sck, adc_sck, dac_sck; +assign clkdis_sck = (clkdis_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign CLKDIST_SPI_CS_L = clkdis_cs_b; +assign CLKDIST_SPI_SCLK = clkdis_sck; + +assign adc_sck = !adc_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign dac_sck = !dac_cs_b ? CPLD_PS_SPI_CLK_25 : 1'b0; + +assign ADC_SPI_CS_L_18 = adc_cs_b; +assign ADC_SPI_SCLK_18 = adc_sck; + +assign DAC_SPI_CS_L_18 = dac_cs_b; +assign DAC_SPI_SCLK_18 = dac_sck; + +assign CLKDIST_SPI_SDIO = (!clkdis_sdio_t && !clkdis_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign ADC_SPI_SDIO_18 = (!adc_sdio_t && !adc_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; +assign DAC_SPI_SDIO_18 = (!dac_sdio_t && !dac_cs_b) ? CPLD_PS_SPI_SDI_25 : 1'bz ; + +always @(*) +begin + CPLD_PS_SPI_SDO_25 = 1'b1; + case ({cpld_ps_cs_b, clkdis_cs_b, adc_cs_b, dac_cs_b}) + 4'b0111: begin + case (cpld_ps_spi_addr[6:5]) + PS_CPLD_REGS : CPLD_PS_SPI_SDO_25 = cpld_ps_spi_sdo; + GAIN_TABLE_RX: CPLD_PS_SPI_SDO_25 = rx_gain_load_miso; + GAIN_TABLE_TX: CPLD_PS_SPI_SDO_25 = tx_gain_load_miso; + GAIN_TABLE_LO: CPLD_PS_SPI_SDO_25 = 1'b1; + endcase + end + 4'b1011: CPLD_PS_SPI_SDO_25 = CLKDIST_SPI_SDIO; + 4'b1101: CPLD_PS_SPI_SDO_25 = ADC_SPI_SDIO_18; + 4'b1110: CPLD_PS_SPI_SDO_25 = DAC_SPI_SDIO_18; + default: ; + endcase +end + +// note: no readback from PHDAC +assign phdac_sck = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_CLK_25 : 1'b0; +assign phdac_sdi = (phdac_cs_b == 1'b0) ? CPLD_PS_SPI_SDI_25 : 1'b1; + + +assign PHDAC_SPI_SCLK = phdac_sck; +assign PHDAC_SPI_CS_L = phdac_cs_b; +assign PHDAC_SPI_SDI = phdac_sdi; + + +/* PL SPI */ +// CPLD PL SPI format (left-most bit first): +// {table_sel[1:0], reg_addr[4:0], rnw, data[15:0]} + +//TXLO, RXLO, LODIS, CPLD +localparam PLADDR_SCRATCH = 4'b0101; // scratchpad register +localparam PLADDR_RXBS = 4'b0110; +localparam PLADDR_TXBS = 4'b0111; +localparam PLADDR_RFCTRL = 4'b1000; +localparam PL_CPLD_REGS = 2'b00; + +// CPLD PL registers +reg [15:0] rxbs = 'h0; +reg [15:0] txbs = 'h0; +reg [15:0] rfctrl = 'h0; + +// register address on the falling edge of chip-select +wire txlo_cs_b = CPLD_PL_SPI_LE_18; +wire rxlo_cs_b = CPLD_PL_SPI_ADDR1_18; +wire lodis_cs_b = CPLD_PL_SPI_ADDR2_18; +wire cpld_pl_cs_b = CPLD_PL_SPI_ADDR0_18; + +wire cpld_pl_spi_rnw; +wire [6:0] cpld_pl_spi_addr; +reg [7:0] cpld_pl_spi_cmd; +reg [15:0] cpld_pl_spi_rdata; +reg [14:0] cpld_pl_spi_wdata; +reg cpld_pl_spi_sdo; +reg [4:0] cpld_pl_cnt; + +assign {cpld_pl_spi_addr, cpld_pl_spi_rnw} = cpld_pl_spi_cmd; + +reg [15:0] pl_spad; + +always @(posedge CPLD_PL_SPI_SCLK_18 or posedge cpld_pl_cs_b) +begin + if (cpld_pl_cs_b) begin + cpld_pl_cnt <= 5'd0; + end else if (!cpld_pl_cs_b) begin + if (cpld_pl_cnt < 8) begin // Address / command + cpld_pl_spi_cmd <= {cpld_pl_spi_cmd[6:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (cpld_pl_cnt < 23) begin // Shift in write data + cpld_pl_spi_wdata <= {cpld_pl_spi_wdata[13:0], CPLD_PL_SPI_SDI_18}; + cpld_pl_cnt <= cpld_pl_cnt + 5'd1; + end else if (!cpld_pl_spi_rnw && cpld_pl_cnt == 23 && cpld_pl_spi_addr[6:5] == PL_CPLD_REGS) begin // Write + case (cpld_pl_spi_addr[3:0]) + PLADDR_SCRATCH: pl_spad <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RXBS: rxbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_TXBS: txbs <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + PLADDR_RFCTRL: rfctrl <= {cpld_pl_spi_wdata, CPLD_PL_SPI_SDI_18}; + endcase + end + if (cpld_pl_cnt == 7) begin // Set up read one cycle earlier + case (cpld_pl_spi_cmd[3:0]) + PLADDR_SCRATCH: cpld_pl_spi_rdata <= pl_spad; + PLADDR_RXBS: cpld_pl_spi_rdata <= rxbs; + PLADDR_TXBS: cpld_pl_spi_rdata <= txbs; + PLADDR_RFCTRL: cpld_pl_spi_rdata <= rfctrl; + endcase + end else begin + cpld_pl_spi_rdata <= {cpld_pl_spi_rdata[14:0], 1'b1}; + end + end +end + +always @(negedge CPLD_PL_SPI_SCLK_18) +begin + cpld_pl_spi_sdo <= cpld_pl_spi_rdata[15]; // Shift out on negative edge +end + +// multiplexed slave device SPI ports, names aliased to protect the innocent +wire lo_sck, lodis_sck; +wire lo_sdi, lodis_sdi; +// Note: lo_sck and lo_sdi -> fan out to both rxlo and txlo synths + +assign { LO_TX_CS_L, LO_RX_CS_L } = { txlo_cs_b, rxlo_cs_b}; +assign LO_SPI_SCLK = lo_sck; +assign LO_SPI_SDI = lo_sdi; + + +assign LODIST_Bd_SPI_CS_L = lodis_cs_b; +assign LODIST_Bd_SPI_SDI = lodis_sdi; +assign LODIST_Bd_SPI_SCLK = lodis_sck; + + +assign lodis_sck = !lodis_cs_b ? CPLD_PL_SPI_SCLK_18 : 1'b0; +assign lodis_sdi = !lodis_cs_b ? CPLD_PL_SPI_SDI_18 : 1'b1; + +assign { lo_sck, lo_sdi } = (!txlo_cs_b | !rxlo_cs_b) ? {CPLD_PL_SPI_SCLK_18,CPLD_PL_SPI_SDI_18} : 2'b01; + + +always @(*) +begin + CPLD_PL_SPI_SDO_18 = 1'bz; + case ({cpld_pl_cs_b, txlo_cs_b, rxlo_cs_b}) + 3'b110: CPLD_PL_SPI_SDO_18 = LOSYNTH_RX_MUXOUT; + 3'b101: CPLD_PL_SPI_SDO_18 = LOSYNTH_TX_MUXOUT; + 3'b011: begin + case (cpld_pl_spi_addr[6:5]) + PL_CPLD_REGS : CPLD_PL_SPI_SDO_18 = cpld_pl_spi_sdo; + GAIN_TABLE_RX: CPLD_PL_SPI_SDO_18 = rx_gain_ctrl_miso; + GAIN_TABLE_TX: CPLD_PL_SPI_SDO_18 = tx_gain_ctrl_miso; + GAIN_TABLE_LO: CPLD_PL_SPI_SDO_18 = lo_gain_ctrl_miso; + endcase + end + default: ; + endcase +end + +assign rx_gain_ctrl_tbl_sel = rxbs[12]; +assign { Rx_Sw6_Ctrl_2, + Rx_Sw6_Ctrl_1, + Rx_Sw4_Ctrl_4, + Rx_Sw4_Ctrl_3, + Rx_Sw4_Ctrl_2, + Rx_Sw4_Ctrl_1, + Rx_Sw3_Ctrl_2, + Rx_Sw3_Ctrl_1, + Rx_Sw2_Ctrl, + Rx_Sw1_Ctrl_2, + Rx_Sw1_Ctrl_1 } = { rxbs[11:1] }; + +assign tx_gain_ctrl_tbl_sel = txbs[12]; +assign { Tx_Sw5_Ctrl_2, + Tx_Sw5_Ctrl_1, + Tx_Sw3_Ctrl_4, + Tx_Sw3_Ctrl_3, + Tx_Sw3_Ctrl_2, + Tx_Sw3_Ctrl_1, + Tx_Sw2_Ctrl_2, + Tx_Sw2_Ctrl_1} = { txbs[11:4] }; + +// Terminate TX when idle +assign {Tx_Sw1_Ctrl_2, Tx_Sw1_Ctrl_1} = CPLD_ATR_TX_18 ? txbs[3:2] : TX_SW1_TERM; + +assign { Rx_LO_Filter_Sw_2, + Rx_LO_Filter_Sw_1, + Tx_LO_Filter_Sw_2, + Tx_LO_Filter_Sw_1, + Rx_Demod_ADJ_1, + Rx_Demod_ADJ_2, + Rx_LO_Input_Select } = rfctrl[15:9]; + +assign { Rx_HB_LB_Select, + Tx_LO_Input_Select } = rfctrl[7:6]; + +assign { Tx_HB_LB_Select, + Cal_iso_Sw_Ctrl } + = { rfctrl[4:3] }; + + +// RX Gain Table +wire [4:0] rx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_RX) +) rx_gain_table ( + .load_table_sel(rx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(rx_gain_load_miso), + .ctrl_table_sel(rx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(rx_gain_ctrl_miso), + .dsa(rx_dsa), + .dsa1_le(Rx_DSA1_LE), + .dsa2_le(Rx_DSA2_LE) +); + +// TX Gain Table +wire [4:0] tx_dsa; + +rhodium_gain_ctrl #( + .TABLE_NUM(GAIN_TABLE_TX) +) tx_gain_table ( + .load_table_sel(tx_gain_load_tbl_sel), + .load_sck(CPLD_PS_SPI_CLK_25), + .load_csb(cpld_ps_cs_b), + .load_mosi(CPLD_PS_SPI_SDI_25), + .load_miso(tx_gain_load_miso), + .ctrl_table_sel(tx_gain_ctrl_tbl_sel), + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(tx_gain_ctrl_miso), + .dsa(tx_dsa), + .dsa1_le(Tx_DSA1_LE), + .dsa2_le(Tx_DSA2_LE) +); + +// LO Gain Table +wire [4:0] lo_dsa; + +rhodium_lo_gain #( + .TABLE_NUM(GAIN_TABLE_LO) +) lo_gain_table ( + .ctrl_sck(CPLD_PL_SPI_SCLK_18), + .ctrl_csb(cpld_pl_cs_b), + .ctrl_mosi(CPLD_PL_SPI_SDI_18), + .ctrl_miso(lo_gain_ctrl_miso), + .dsa(lo_dsa), + .dsa1_le(RxLO_DSA_LE), + .dsa2_le(TxLO_DSA_LE) +); + +// Rx data shared by DSA1, DSA2 +assign { Rx_DSA_C16, Rx_DSA_C8, Rx_DSA_C4, Rx_DSA_C2, Rx_DSA_C1 } = rx_dsa; + +// Tx data shared by DSA1, DSA2 +assign { Tx_DSA_C16, Tx_DSA_C8, Tx_DSA_C4, Tx_DSA_C2, Tx_DSA_C1 } = tx_dsa; + +// data shared by both tx and rx lo DSAs +assign { LO_DSA_C16, LO_DSA_C8, LO_DSA_C4, LO_DSA_C2, LO_DSA_C1 } = lo_dsa; + +endmodule +`default_nettype wire + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc new file mode 100644 index 000000000..e78342849 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_clocks.xdc @@ -0,0 +1,118 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Daughterboard Clocks +# +# 122.88, 200, 245.76 and 250 MHz Sample Rates are allowable with 2:1/1:2 DSP and +# 2 samples/cycle arriving at the FPGA: +# +# <-- 2:1/1:2 --> +# | Supported | Sample rate | FPGA Clk | +# |sample rates | at JESD core | Frequency | +# | (MSPS) | (MSPS) | (MHz) | +# |-------------|--------------|-----------| +# | 122.88 | 491.52 | 245.76 | (uses DUC/DDC) +# | 200.00 | 400.00 | 200.00 | +# | 245.76 | 491.52 | 245.76 | +# | 250.00 | 500.00 | 250.00 | +# +# Therefore, supported sample clocks are: 122.88, 200, 245.76 and 250 MHz. +# Constrain the paths to the max rate to support all rates in a single FPGA image. +set SAMPLE_CLK_PERIOD 4.00 +create_clock -name fpga_clk_a -period $SAMPLE_CLK_PERIOD [get_ports DBA_FPGA_CLK_P] +create_clock -name fpga_clk_b -period $SAMPLE_CLK_PERIOD [get_ports DBB_FPGA_CLK_P] +create_clock -name mgt_clk_dba -period $SAMPLE_CLK_PERIOD [get_ports DBA_MGTCLK_P] +create_clock -name mgt_clk_dbb -period $SAMPLE_CLK_PERIOD [get_ports DBB_MGTCLK_P] + +# The Radio Clocks coming from the DBs are synchronized together (at the converters) to +# a typical value of less than 100ps. To give ourselves and Vivado some margin, we claim +# here that the DB-B Radio Clock can arrive 500ps before or after the DB-A clock at +# the FPGA (note that the trace lengths of the Radio Clocks coming from the DBs to the +# FPGA are about 0.5" different, thereby incurring ~80ps of additional skew at the FPGA). +# There is one spot in the FPGA where we cross domains between the DB-A and +# DB-B clock, so we must ensure that Vivado can analyze that path safely. +set FPGA_CLK_EARLY -0.5 +set FPGA_CLK_LATE 0.5 +set_clock_latency -source -early $FPGA_CLK_EARLY [get_clocks fpga_clk_b] +set_clock_latency -source -late $FPGA_CLK_LATE [get_clocks fpga_clk_b] + +# Virtual clocks for constraining I/O (used below) +create_clock -name fpga_clk_a_v -period $SAMPLE_CLK_PERIOD +create_clock -name fpga_clk_b_v -period $SAMPLE_CLK_PERIOD + +# The set_clock_latency constraints set on fpga_clk_b are problematic when used with +# I/O timing, since the analyzer gives us a double-hit on the latency. One workaround +# (used here) is to simply swap the early and late times for the virtual clock so that +# it cancels out the source latency during analysis. D. Jepson tested this by setting +# the early and late numbers to zero and then their actual value, running timing reports +# on each. The slack report matches for both cases, showing that the reversed early/late +# numbers on the virtual clock zero out the latency effects on the actual clock. +# +# Note this is not a problem for the fpga_clk_a, since no latency is added. So only apply +# it to fpga_clk_b_v. +set_clock_latency -source -early $FPGA_CLK_LATE [get_clocks fpga_clk_b_v] +set_clock_latency -source -late $FPGA_CLK_EARLY [get_clocks fpga_clk_b_v] + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + +create_generated_clock -name radio_clk_b_fb [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKFBOUT}] +create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0}] +create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1}] + + + +#******************************************************************************* +## Generated clocks for output busses to the daughterboard +# +# These clock definitions need to come above the set_clock_groups commands below to work! + +# Define clocks on the PL SPI clock output pins for both DBs. Actual divider values are +# set by SW at run-time. Current divider value is 125 based on what radio clock +# rate is set. +# For the CPLD SPI endpoint alone, we need it to run at ~25 MHz (writes only), this means +# that at times, the PL SPI will have its divider set to 10 (radio_clock = 250 MHz) or 8 +# (radio_clock = 200 MHz). +# The readback clock is lower (~10 MHz), so create a separate clock for it. +# Use readback divide value of 24 for an even divider (and some overconstraining). +set PL_SPI_DIVIDE_VAL 10 +set PL_SPI_RB_DIVIDE_VAL 24 +set PL_SPI_CLK_A [get_ports DBA_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_a \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_A +create_generated_clock -name pl_spi_rb_clk_a \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_A +set PL_SPI_CLK_B [get_ports DBB_CPLD_PL_SPI_SCLK] +create_generated_clock -name pl_spi_clk_b \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_DIVIDE_VAL $PL_SPI_CLK_B +create_generated_clock -name pl_spi_rb_clk_b \ + -master_clock [get_clocks radio_clk] \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \ + -divide_by $PL_SPI_RB_DIVIDE_VAL -add $PL_SPI_CLK_B + +#******************************************************************************* +## JTAG +set DB_JTAG_DIVISOR 4 +create_generated_clock -name dba_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_0/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBA_CPLD_JTAG_TCK] + +create_generated_clock -name dbb_jtag_tck -divide_by $DB_JTAG_DIVISOR \ + -source [get_pins {inst_n310_ps/jtag_1/U0/bitq_ctrl/bitq_state_reg[1]/C}] \ + [get_ports DBB_CPLD_JTAG_TCK] + diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd new file mode 100644 index 000000000..52c68ab4a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ClockingRegs.vhd @@ -0,0 +1,345 @@ +------------------------------------------------------------------------------- +-- +-- File: ClockingRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 17 March 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register access to the control/status bits and interfaces for the +-- RadioClocking module. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgClockingRegMap.all; + use work.PkgRegs.all; + + +entity ClockingRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + -- Register Bus Clock -- this module connects the BusClk to PsClk, so it's limited + -- to 200 MHz! + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Phase shift interface to the RadioClkMmcm. + -- There is a reset crossing here between the MMCM reset and aReset. The outgoing + -- crossing is safe because (a) the enable signal driven to the MMCM is a strobe-only + -- signal and (b) this interface should only be used when the MMCM is not in reset + -- (SW waits for the MMCM to be out of reset and locked before using this interface). + -- The only input signal, pPsDone, is double-synced in this file before being used. + -- This is OK (even though it is a strobe signal) because there is only a reset + -- crossing and not a clock domain crossing. + pPsInc : out std_logic; + pPsEn : out std_logic; + pPsDone : in std_logic; + + -- PsClk is driven directly by BusClk, so p = b in the logic below! + PsClk : out std_logic; + + -- Sync reset strobes from the register bus to the RadioClkMmcm. + bRadioClkMmcmReset : out std_logic; + -- Status of RadioClk MMCM lock to register bus. + aRadioClksValid : in std_logic; + + bRadioClk1xEnabled : out std_logic; + bRadioClk2xEnabled : out std_logic; + bRadioClk3xEnabled : out std_logic; + + bJesdRefClkPresent : in std_logic + ); +end ClockingRegs; + + +architecture RTL of ClockingRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRadioClkMmcmResetInt : std_logic := '1'; + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + + signal bPsDone, + bPsEn, + bPsInc, + pPsDoneDs_ms, + pPsDoneDs : std_logic := '0'; + + signal bRadioClk1xEnabledInt, + bRadioClk2xEnabledInt, + bRadioClk3xEnabledInt, + bRadioClksValid_ms, + bRadioClksValid : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClksValid_ms : signal is "true"; + attribute ASYNC_REG of bRadioClksValid : signal is "true"; + attribute ASYNC_REG of pPsDoneDs_ms : signal is "true"; + attribute ASYNC_REG of pPsDoneDs : signal is "true"; + +begin + + -- Locals to outputs. + PsClk <= BusClk; + pPsInc <= bPsInc; + pPsEn <= bPsEn; + + bRadioClkMmcmReset <= bRadioClkMmcmResetInt; + + bRadioClk1xEnabled <= bRadioClk1xEnabledInt; + bRadioClk2xEnabled <= bRadioClk2xEnabledInt; + bRadioClk3xEnabled <= bRadioClk3xEnabledInt; + + + -- Write Registers : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + WriteRegisters: process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRadioClkMmcmResetInt <= '1'; + bPsInc <= '0'; + bPsEn <= '0'; + bRadioClk1xEnabledInt <= '0'; + bRadioClk2xEnabledInt <= '0'; + bRadioClk3xEnabledInt <= '0'; + else + -- Clear strobe + bPsEn <= '0'; + + if RegWrite(kPhaseShiftControl, bRegPortIn) then + if bRegPortIn.Data(kPsInc) = '1' then + bPsInc <= '1'; + bPsEn <= '1'; + elsif bRegPortIn.Data(kPsDec) = '1' then + bPsInc <= '0'; + bPsEn <= '1'; + end if; + end if; + + if RegWrite(kRadioClkMmcm, bRegPortIn) then + -- Set/Clear pair + if bRegPortIn.Data(kRadioClkMmcmResetSet) = '1' then + bRadioClkMmcmResetInt <= '1'; + elsif bRegPortIn.Data(kRadioClkMmcmResetClear) = '1' then + bRadioClkMmcmResetInt <= '0'; + end if; + end if; + + if RegWrite(kRadioClkEnables, bRegPortIn) then + bRadioClk1xEnabledInt <= bRegPortIn.Data(kRadioClk1xEnabled); + bRadioClk2xEnabledInt <= bRegPortIn.Data(kRadioClk2xEnabled); + bRadioClk3xEnabledInt <= bRegPortIn.Data(kRadioClk3xEnabled); + end if; + + end if; + end if; + end process WriteRegisters; + + + DoubleSyncs : process (aReset, BusClk) + begin + if aReset then + bRadioClksValid_ms <= '0'; + bRadioClksValid <= '0'; + pPsDoneDs_ms <= '0'; + pPsDoneDs <= '0'; + elsif rising_edge(BusClk) then + -- No sync reset on double-syncs (however there are default assignments above)! + bRadioClksValid_ms <= aRadioClksValid; + bRadioClksValid <= bRadioClksValid_ms; + pPsDoneDs_ms <= pPsDone; + pPsDoneDs <= pPsDoneDs_ms; + end if; + end process; + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + elsif rising_edge(BusClk) then + + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + bPsDone <= '0'; + else + -- Deassert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + -- Process the returned data from the phase shifter in the MMCM. Note that even + -- though the prefixes are different (p and b), we drive the PsClk from the BusClk + -- so this "crossing" is actually safe. Whenever the Done signal asserts (pPsDone - + -- pay attention to the prefix!) from the MMCM, we set a sticky bit to tell SW + -- that the shift operation is complete. + -- + -- However, if pPsDone asserts at the same time that SW tries to read the register, + -- we should accurately report that the operation is indeed complete and then NOT + -- store the sticky (since it has already been read by SW). If a read does not come + -- through at the same time pPsDone is asserted, then we store the done state as a + -- sticky, bPsDone, which is only cleared by a read to this register. + if RegRead(kPhaseShiftControl, bRegPortIn) then + -- The phase shift is always enabled for the feedback clock in RadioClocking.vhd + bRegPortOutLcl.Data(kPsEnabledForFdbClk) <= '1'; + bRegPortOutLcl.Data(kPsDone) <= bPsDone or pPsDoneDs; + bPsDone <= '0'; + elsif pPsDoneDs = '1' then + bPsDone <= '1'; + end if; + + if RegRead(kRadioClkMmcm, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClkMmcmLocked) <= bRadioClksValid; + end if; + + if RegRead(kRadioClkEnables, bRegPortIn) then + bRegPortOutLcl.Data(kRadioClk1xEnabled) <= bRadioClk1xEnabledInt; + bRegPortOutLcl.Data(kRadioClk2xEnabled) <= bRadioClk2xEnabledInt; + bRegPortOutLcl.Data(kRadioClk3xEnabled) <= bRadioClk3xEnabledInt; + end if; + + if RegRead(kMgtRefClkStatus, bRegPortIn) then + bRegPortOutLcl.Data(kJesdRefClkPresent) <= bJesdRefClkPresent; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- Reflects the locked status of the MMCM. '1' = locked. This bit is only valid +-- when the MMCM reset is de-asserted. Read-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to de-assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- Controls the reset to the Radio Clock MMCM. Strobe this bit to assert the +-- reset to the MMCM. Default is reset asserted. Write-only. +-- +-- +-- +-- +-- +-- +-- Phase Shift for RadioClkMmcm. +-- +-- +-- +-- This bit should set after a shift operation successfully completes. +-- Reading this register will clear this bit. Read-only. +-- +-- +-- +-- +-- Strobe this bit to increment the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Strobe this bit to decrement the phase. This bit is self-clearing and will +-- always return '0' when read. If PsInc and PsDec are asserted together, +-- the phase will increment. +-- +-- +-- +-- +-- Read-only. +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- Set to '1' to enable the clock. Default disabled = '0'. +-- Do so ONLY after the MMCM is out of reset and locked! +-- +-- +-- +-- +-- +-- +-- +-- +-- +-- Live indicator of the MGT Reference Clock toggling and within expected +-- frequency limits. If this bit is de-asserted, then the JESD204b core will +-- not function correctly! +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd new file mode 100644 index 000000000..8a9c20372 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DaughterboardRegs.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- +-- File: DaughterboardRegs.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N32x +-- Date: 27 April 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Register interface to the semi-static control lines for the Mg +-- Daughterboard. +-- +-- XML register definition is included below the module. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library work; + use work.PkgDaughterboardRegMap.all; + use work.PkgRegs.all; + + +entity DaughterboardRegs is + port( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + BusClk : in std_logic; + + bRegPortOut : out RegPortOut_t; + bRegPortIn : in RegPortIn_t; + + -- Slot and DB ID values. These should be tied to constants! + kDbId : in std_logic_vector(15 downto 0); + kSlotId : in std_logic + + ); +end DaughterboardRegs; + + +architecture RTL of DaughterboardRegs is + + --vhook_sigstart + --vhook_sigend + + signal bRegPortOutLcl : RegPortOut_t := kRegPortOutZero; + +begin + + + -- Read Registers : ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + ReadRegisters: process(aReset, BusClk) + begin + if aReset then + bRegPortOutLcl <= kRegPortOutZero; + elsif rising_edge(BusClk) then + if bReset then + bRegPortOutLcl <= kRegPortOutZero; + else + -- De-assert strobes + bRegPortOutLcl.Data <= kRegPortDataZero; + + -- All of these transactions only take one clock cycle, so we do not have to + -- de-assert the Ready signal (ever). + bRegPortOutLcl.Ready <= true; + + if RegRead(kDaughterboardId, bRegPortIn) then + bRegPortOutLcl.Data(kDbIdValMsb downto kDbIdVal) <= kDbId; + bRegPortOutLcl.Data(kSlotIdVal) <= kSlotId; + end if; + + end if; + end if; + end process ReadRegisters; + + -- Local to output + bRegPortOut <= bRegPortOutLcl; + + +end RTL; + + +--XmlParse xml_on +-- +-- +-- +-- +-- +-- +-- +-- +-- ID for the DB with which this file is designed to communicate. Matches the DB +-- EEPROM ID. +-- +-- +-- +-- +-- ID for the Slot this module controls. Options are 0 and 1 for the N310 MB. +-- +-- +-- +-- +-- +-- +-- +-- +--XmlParse xml_off diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd new file mode 100644 index 000000000..f54a976d1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/DbCore.vhd @@ -0,0 +1,563 @@ +------------------------------------------------------------------------------- +-- +-- File: DbCore.vhd +-- Author: Daniel Jepson; mods by Humberto Jimenez +-- Original Project: N310; N320 +-- Date: 12 April 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for Daughterboard Control. This includes the semi-static control +-- and status registers, clocking, synchronization, and JESD204B cores. +-- +-- There is no version register for the plain-text files here. +-- Version control for the Sync and JESD204B cores is internal to the netlists. +-- +-- The resets for this core are almost entirely local and/or synchronous. +-- bBusReset is a Synchronous reset on the BusClk domain that resets all of the +-- registers connected to the RegPort, as well as any other stray registers +-- connected to the BusClk. All other resets are local to the modules they touch. +-- No other reset drives all modules universally. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRhPersonality.all; + use work.PkgRegs.all; + use work.PkgJesdConfig.all; + use work.PkgAdcDacInterfaceTypes.all; + + +entity DbCore is + generic( + -- Set to '1' to include the White Rabbit TDC. + kInclWhiteRabbitTdc : std_logic := '0' + ); + port( + + -- Resets -- + -- Synchronous Reset for the BusClk domain (mainly for the RegPort) + bBusReset : in std_logic; + + -- Clocks -- + -- Register Bus Clock (any frequency) + BusClk : in std_logic; + -- Always-on at 40 MHz + Clk40 : in std_logic; + -- Super secret crazy awesome measurement clock at weird frequencies. + MeasClk : in std_logic; + -- FPGA Sample Clock from DB LMK + FpgaClk_p : in std_logic; + FpgaClk_n : in std_logic; + + -- Sample Clock Sharing. The clocks generated in this module are exported out to the + -- top level so they can be shared amongst daughterboards. Therefore they must be + -- driven back into the SampleClk*x inputs at a higher level in order for this module + -- to work correctly. There are a few isolated cases where SampleClk*xOut is used + -- directly in this module, and those are documented below. + SampleClk1xOut : out std_logic; + SampleClk1x : in std_logic; + SampleClk2xOut : out std_logic; + SampleClk2x : in std_logic; + + + -- Register Ports -- + -- + -- Only synchronous resets can be used for these ports! + bRegPortInFlat : in std_logic_vector(49 downto 0); + bRegPortOutFlat : out std_logic_vector(33 downto 0); + + -- Slot ID value. This should be tied to a constant! + kSlotId : in std_logic; + + + -- SYSREF -- + -- + -- SYSREF direct from the LMK + sSysRefFpgaLvds_p, + sSysRefFpgaLvds_n : in std_logic; + -- SYNC directly to the LMK + aLmkSync : out std_logic; + + + -- JESD Signals -- + -- + -- GTX Sample Clock Reference Input. Direct connect to FPGA pins. + JesdRefClk_p, + JesdRefClk_n : in std_logic; + + -- ADC JESD PHY Interface. Direct connect to FPGA pins. + aAdcRx_p, + aAdcRx_n : in std_logic_vector(3 downto 0); + aSyncAdcOut_n : out std_logic; + + -- DAC JESD PHY Interface. Direct connect to FPGA pins. + aDacTx_p, + aDacTx_n : out std_logic_vector(3 downto 0); + aSyncDacIn_n : in std_logic; + + + -- Data Pipes to/from the DACs/ADCs -- + -- + -- - Data is presented as two samples per cycle. + -- - sAdcDataValid asserts when ADC data is valid. + -- - sDacReadyForInput asserts when DAC data is ready to be received. + -- + -- Reset Crossings: + -- The ADC data and valid outputs are synchronously cleared before the asynchronous + -- reset is asserted--preventing any reset crossing issues here between the RX + -- (internal to the core) reset and the no-reset domain of RFNoC. + -- + -- The DAC samples should be zeros on reset de-assertion due to RFI being de-asserted + -- in reset. If they are not zeros, then it is still OK because data is ignored until + -- RFI is asserted. DAC RFI is double-synchronized to protect against the reset + -- crossing. This is safe to do because it simply delays the output of RFI by two + -- cycles on the assertion edge, and as long as reset is held for more than two + -- cycles, the de-assertion edge of RFI should come long before the TX module is + -- taken out of reset. + + -- Supporting 2 samples per clk cycle. + sAdcDataValid : out std_logic; + sAdcDataSample0I : out std_logic_vector(15 downto 0); + sAdcDataSample0Q : out std_logic_vector(15 downto 0); + sAdcDataSample1I : out std_logic_vector(15 downto 0); + sAdcDataSample1Q : out std_logic_vector(15 downto 0); + -- + sDacReadyForInput : out std_logic; + sDacDataSample0I : in std_logic_vector(15 downto 0); + sDacDataSample0Q : in std_logic_vector(15 downto 0); + sDacDataSample1I : in std_logic_vector(15 downto 0); + sDacDataSample1Q : in std_logic_vector(15 downto 0); + + + -- RefClk & Timing & Sync -- + RefClk : in std_logic; + rPpsPulse : in std_logic; + rGatedPulseToPin : inout std_logic; -- straight to pin + sGatedPulseToPin : inout std_logic; -- straight to pin + sPps : out std_logic; + sPpsToIob : out std_logic; + + -- White Rabbit Timing & Sync -- + WrRefClk : in std_logic; + rWrPpsPulse : in std_logic; + rWrGatedPulseToPin : inout std_logic; -- straight to pin + sWrGatedPulseToPin : inout std_logic; -- straight to pin + aPpsSfpSel : in std_logic_vector(1 downto 0); + + -- Debug for JESD + sAdcSync : out std_logic; + sDacSync : out std_logic; + sSysRef : out std_logic; + + -- Debug for Timing & Sync + rRpTransfer : out std_logic; + sSpTransfer : out std_logic; + rWrRpTransfer : out std_logic; + sWrSpTransfer : out std_logic + ); + +end DbCore; + + +architecture RTL of DbCore is + + component Jesd204bXcvrCore + port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR(49 downto 0); + bRegPortOutFlat : out STD_LOGIC_VECTOR(33 downto 0); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR(3 downto 0); + aAdcRx_n : in STD_LOGIC_VECTOR(3 downto 0); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR(3 downto 0); + aDacTx_n : out STD_LOGIC_VECTOR(3 downto 0); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR(63 downto 0); + fDacDataFlatter : in STD_LOGIC_VECTOR(63 downto 0); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC); + end component; + + function to_Boolean (s : std_ulogic) return boolean is + begin + return (To_X01(s)='1'); + end to_Boolean; + + function to_StdLogic(b : boolean) return std_ulogic is + begin + if b then + return '1'; + else + return '0'; + end if; + end to_StdLogic; + + --vhook_sigstart + signal aAdcSync: STD_LOGIC; + signal aDacSync: STD_LOGIC; + signal bClockingRegPortOut: RegPortOut_t; + signal bDbRegPortOut: RegPortOut_t; + signal bFpgaClksStable: STD_LOGIC; + signal bJesdCoreRegPortInFlat: STD_LOGIC_VECTOR(49 downto 0); + signal bJesdCoreRegPortOutFlat: STD_LOGIC_VECTOR(33 downto 0); + signal bJesdRefClkPresent: STD_LOGIC; + signal bRadioClk1xEnabled: std_logic; + signal bRadioClk2xEnabled: std_logic; + signal bRadioClk3xEnabled: std_logic; + signal bRadioClkMmcmReset: std_logic; + signal bRadioClksValid: std_logic; + signal pPsDone: std_logic; + signal pPsEn: std_logic; + signal pPsInc: std_logic; + signal PsClk: std_logic; + signal sAdcDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal SampleClk1xOutLcl: std_logic; + signal sDacDataFlatter: STD_LOGIC_VECTOR(63 downto 0); + signal sDacReadyForInputAsyncReset: STD_LOGIC; + signal sRegPps: std_logic; + signal sSysRefAsyncReset: STD_LOGIC; + signal sWrPps: std_logic; + --vhook_sigend + + signal bJesdRegPortInGrp, bSyncRegPortIn, bWrSyncRegPortIn, bRegPortIn : RegPortIn_t; + signal bJesdRegPortOut, bSyncRegPortOut, bWrSyncRegPortOut, bRegPortOut : RegPortOut_t; + + signal sDacReadyForInput_ms, sDacReadyForInputLcl, + sDacSync_ms, sDacSyncLcl, + sAdcSync_ms, sAdcSyncLcl, + sSysRef_ms, sSysRefLcl : std_logic := '0'; + + signal sAdcDataAry : AdcDataAry_t; + signal sDacDataAry : DacDataAry_t; + + signal sPpsSfpSel_ms, sPpsSfpSel : std_logic_vector(1 downto 0) := (others => '0'); + signal sUseWrTdcPps : boolean := false; + signal sPpsInt, sPpsMuxed : std_logic := '0'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of sDacReadyForInput_ms : signal is "true"; + attribute ASYNC_REG of sDacReadyForInputLcl : signal is "true"; + attribute ASYNC_REG of sDacSync_ms : signal is "true"; + attribute ASYNC_REG of sDacSyncLcl : signal is "true"; + attribute ASYNC_REG of sAdcSync_ms : signal is "true"; + attribute ASYNC_REG of sAdcSyncLcl : signal is "true"; + attribute ASYNC_REG of sSysRef_ms : signal is "true"; + attribute ASYNC_REG of sSysRefLcl : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel_ms : signal is "true"; + attribute ASYNC_REG of sPpsSfpSel : signal is "true"; + +begin + + bRegPortOutFlat <= Flatten(bRegPortOut); + bRegPortIn <= Unflatten(bRegPortInFlat); + + + -- Combine return RegPorts. + bRegPortOut <= bJesdRegPortOut + + bClockingRegPortOut + + bSyncRegPortOut + bWrSyncRegPortOut + + bDbRegPortOut; + + + -- Clocking : ------------------------------------------------------------------------- + -- Automatically export the Sample Clocks and only use the incoming clocks in the + -- remainder of the logic. For a single module, the clocks must be looped back + -- in at a higher level! + -- ------------------------------------------------------------------------------------ + + --vhook_e RadioClocking + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a RadioClk1x SampleClk1xOutLcl + --vhook_a RadioClk2x SampleClk2xOut + --vhook_a RadioClk3x open + RadioClockingx: entity work.RadioClocking (rtl) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --in std_logic + bRadioClksValid => bRadioClksValid, --out std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --in std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --in std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --in std_logic + pPsInc => pPsInc, --in std_logic + pPsEn => pPsEn, --in std_logic + PsClk => PsClk, --in std_logic + pPsDone => pPsDone, --out std_logic + FpgaClk_n => FpgaClk_n, --in std_logic + FpgaClk_p => FpgaClk_p, --in std_logic + RadioClk1x => SampleClk1xOutLcl, --out std_logic + RadioClk2x => SampleClk2xOut, --out std_logic + RadioClk3x => open); --out std_logic + + -- We need an internal copy of SampleClk1x for the TDC, since we don't want to try + -- and align the other DB's clock accidentally. + SampleClk1xOut <= SampleClk1xOutLcl; + + --vhook_e ClockingRegs + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bClockingRegPortOut + --vhook_a aRadioClksValid bRadioClksValid + ClockingRegsx: entity work.ClockingRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bClockingRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + pPsInc => pPsInc, --out std_logic + pPsEn => pPsEn, --out std_logic + pPsDone => pPsDone, --in std_logic + PsClk => PsClk, --out std_logic + bRadioClkMmcmReset => bRadioClkMmcmReset, --out std_logic + aRadioClksValid => bRadioClksValid, --in std_logic + bRadioClk1xEnabled => bRadioClk1xEnabled, --out std_logic + bRadioClk2xEnabled => bRadioClk2xEnabled, --out std_logic + bRadioClk3xEnabled => bRadioClk3xEnabled, --out std_logic + bJesdRefClkPresent => bJesdRefClkPresent); --in std_logic + + + + -- JESD204B : ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------ + + bJesdRegPortInGrp <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kJesdRegGroupInDbRegs); -- 0x2000 to 0x3FFC + + -- Expand/compress the RegPort for moving through the netlist boundary. + bJesdRegPortOut <= Unflatten(bJesdCoreRegPortOutFlat); + bJesdCoreRegPortInFlat <= Flatten(bJesdRegPortInGrp); + + + --vhook Jesd204bXcvrCore + --vhook_a bRegPortInFlat bJesdCoreRegPortInFlat + --vhook_a bRegPortOutFlat bJesdCoreRegPortOutFlat + --vhook_a FpgaClk1x SampleClk1x + --vhook_a FpgaClk2x SampleClk2x + --vhook_a ReliableClk40 Clk40 + --vhook_a CaptureSysRefClk SampleClk1xOutLcl + --vhook_a cSysRefFpgaLvds_p sSysRefFpgaLvds_p + --vhook_a cSysRefFpgaLvds_n sSysRefFpgaLvds_n + --vhook_a fSysRef sSysRefAsyncReset + --vhook_a fDacReadyForInput sDacReadyForInputAsyncReset + --vhook_a {^f(.*)} s$1 + Jesd204bXcvrCorex: Jesd204bXcvrCore + port map ( + bBusReset => bBusReset, --in STD_LOGIC + BusClk => BusClk, --in STD_LOGIC + ReliableClk40 => Clk40, --in STD_LOGIC + FpgaClk1x => SampleClk1x, --in STD_LOGIC + FpgaClk2x => SampleClk2x, --in STD_LOGIC + bFpgaClksStable => bFpgaClksStable, --in STD_LOGIC + JesdRefClk_p => JesdRefClk_p, --in STD_LOGIC + JesdRefClk_n => JesdRefClk_n, --in STD_LOGIC + bJesdRefClkPresent => bJesdRefClkPresent, --out STD_LOGIC + aLmkSync => aLmkSync, --out STD_LOGIC + bRegPortInFlat => bJesdCoreRegPortInFlat, --in STD_LOGIC_VECTOR(49:0) + bRegPortOutFlat => bJesdCoreRegPortOutFlat, --out STD_LOGIC_VECTOR(33:0) + CaptureSysRefClk => SampleClk1xOutLcl, --in STD_LOGIC + cSysRefFpgaLvds_p => sSysRefFpgaLvds_p, --in STD_LOGIC + cSysRefFpgaLvds_n => sSysRefFpgaLvds_n, --in STD_LOGIC + fSysRef => sSysRefAsyncReset, --out STD_LOGIC + aAdcRx_p => aAdcRx_p, --in STD_LOGIC_VECTOR(3:0) + aAdcRx_n => aAdcRx_n, --in STD_LOGIC_VECTOR(3:0) + aSyncAdcOut_n => aSyncAdcOut_n, --out STD_LOGIC + aDacTx_p => aDacTx_p, --out STD_LOGIC_VECTOR(3:0) + aDacTx_n => aDacTx_n, --out STD_LOGIC_VECTOR(3:0) + aSyncDacIn_n => aSyncDacIn_n, --in STD_LOGIC + fAdcDataFlatter => sAdcDataFlatter, --out STD_LOGIC_VECTOR(63:0) + fDacDataFlatter => sDacDataFlatter, --in STD_LOGIC_VECTOR(63:0) + fAdcDataValid => sAdcDataValid, --out STD_LOGIC + fDacReadyForInput => sDacReadyForInputAsyncReset, --out STD_LOGIC + aDacSync => aDacSync, --out STD_LOGIC + aAdcSync => aAdcSync); --out STD_LOGIC + + + JesdDoubleSyncToNoResetSampleClk : process (SampleClk1x) + begin + if rising_edge(SampleClk1x) then + sDacReadyForInput_ms <= sDacReadyForInputAsyncReset; + sDacReadyForInputLcl <= sDacReadyForInput_ms; + -- No clock crossing here -- just reset, although the prefix declares otherwise... + sDacSync_ms <= aDacSync; + sDacSyncLcl <= sDacSync_ms; + sAdcSync_ms <= aAdcSync; + sAdcSyncLcl <= sAdcSync_ms; + sSysRef_ms <= sSysRefAsyncReset; + sSysRefLcl <= sSysRef_ms; + end if; + end process; + + -- Locals to outputs. + sDacReadyForInput <= sDacReadyForInputLcl; + sDacSync <= sDacSyncLcl; + sAdcSync <= sAdcSyncLcl; + sSysRef <= sSysRefLcl; + + -- Just combine the first two enables, since they're the ones that are used for JESD. + -- No reset crossing here, since bFpgaClksStable is only received by a no-reset domain + -- and the MGTs directly. + bFpgaClksStable <= bRadioClksValid and bRadioClk1xEnabled and bRadioClk2xEnabled; + + -- Compress/expand the flat data types from the netlist and route to top level. + sAdcDataAry <= Unflatten(sAdcDataFlatter); + sDacDataFlatter <= Flatten(sDacDataAry); + + -- Data mapping using the array types. + sAdcDataSample0I <= (sAdcDataAry(0).Data.I & sAdcDataAry(0).Over.I & sAdcDataAry(0).CBit1.I); + sAdcDataSample0Q <= (sAdcDataAry(0).Data.Q & sAdcDataAry(0).Over.Q & sAdcDataAry(0).CBit1.Q); + sAdcDataSample1I <= (sAdcDataAry(1).Data.I & sAdcDataAry(1).Over.I & sAdcDataAry(1).CBit1.I); + sAdcDataSample1Q <= (sAdcDataAry(1).Data.Q & sAdcDataAry(1).Over.Q & sAdcDataAry(1).CBit1.Q); + -- + sDacDataAry(0).Data.I <= sDacDataSample0I; + sDacDataAry(0).Data.Q <= sDacDataSample0Q; + sDacDataAry(1).Data.I <= sDacDataSample1I; + sDacDataAry(1).Data.Q <= sDacDataSample1Q; + + + -- Timing and Sync : ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + bSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc0OffsetsInEndpoint); -- 0x0200 + + --vhook_e TdcWrapper + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a sPpsPulse sRegPps + TdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => RefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rPpsPulse, --in std_logic + sPpsPulse => sRegPps, --out std_logic + rRpTransfer => rRpTransfer, --out std_logic + sSpTransfer => sSpTransfer, --out std_logic + rGatedPulseToPin => rGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sGatedPulseToPin); --inout std_logic + + WrTdcGen: if kInclWhiteRabbitTdc = '1' generate + bWrSyncRegPortIn <= Mask(RegPortIn => bRegPortIn, + kRegisterOffset => kTdc1OffsetsInEndpoint); -- 0x0400 + + --vhook_e TdcWrapper WrTdcWrapperx + --vhook_# Use the local copy of the SampleClock, since we want the TDC to measure the + --vhook_# clock offset for this daughterboard, not the global SampleClock. + --vhook_a bSyncRegPortIn bWrSyncRegPortIn + --vhook_a bSyncRegPortOut bWrSyncRegPortOut + --vhook_a SampleClk SampleClk1xOutLcl + --vhook_a RefClk WrRefClk + --vhook_a rPpsPulse rWrPpsPulse + --vhook_a sPpsPulse sWrPps + --vhook_a rRpTransfer rWrRpTransfer + --vhook_a sSpTransfer sWrSpTransfer + --vhook_a rGatedPulseToPin rWrGatedPulseToPin + --vhook_a sGatedPulseToPin sWrGatedPulseToPin + WrTdcWrapperx: entity work.TdcWrapper (struct) + port map ( + BusClk => BusClk, --in std_logic + bBusReset => bBusReset, --in std_logic + RefClk => WrRefClk, --in std_logic + SampleClk => SampleClk1xOutLcl, --in std_logic + MeasClk => MeasClk, --in std_logic + bSyncRegPortOut => bWrSyncRegPortOut, --out RegPortOut_t + bSyncRegPortIn => bWrSyncRegPortIn, --in RegPortIn_t + rPpsPulse => rWrPpsPulse, --in std_logic + sPpsPulse => sWrPps, --out std_logic + rRpTransfer => rWrRpTransfer, --out std_logic + sSpTransfer => sWrSpTransfer, --out std_logic + rGatedPulseToPin => rWrGatedPulseToPin, --inout std_logic + sGatedPulseToPin => sWrGatedPulseToPin); --inout std_logic + end generate WrTdcGen; + + WrTdcNotGen: if kInclWhiteRabbitTdc = '0' generate + bWrSyncRegPortOut <= kRegPortOutZero; + sWrPps <= '0'; + rWrRpTransfer <= '0'; + sWrSpTransfer <= '0'; + rWrGatedPulseToPin <= '0'; + sWrGatedPulseToPin <= '0'; + end generate WrTdcNotGen; + + -- Mux the output PPS based on the SFP selection bits. Encoding is one-hot, with zero + -- also a valid state. Regardless of whether the user selects SFP0 or SFP1 as the time + -- source, there is only one White Rabbit TDC, so '01' and '10' are equivalent. + -- '00': Use the PPS output from the "regular" TDC. + -- '01': Use the PPS output from the "white rabbit" TDC. + -- '10': Use the PPS output from the "white rabbit" TDC. + PpsOutputMux : process (SampleClk1xOutLcl) + begin + if rising_edge(SampleClk1xOutLcl) then + -- Double-sync the control bits to the Sample Clock domain. + sPpsSfpSel_ms <= aPpsSfpSel; + sPpsSfpSel <= sPpsSfpSel_ms; + + -- OR the control bits together to produce a single override enable for the WR TDC. + sUseWrTdcPps <= to_boolean(sPpsSfpSel(0) or sPpsSfpSel(1)); + + -- Flop the outputs. One flop for the PPS output IOB, the other for use internally. + sPpsInt <= sPpsMuxed; + end if; + end process PpsOutputMux; + + sPpsMuxed <= sWrPps when sUseWrTdcPps else sRegPps; + sPps <= sPpsInt; + sPpsToIob <= sPpsMuxed; -- No added flop here since there's an IOB outside this module. + + + -- Daughterboard Control : ------------------------------------------------------------ + -- ------------------------------------------------------------------------------------ + + --vhook_e DaughterboardRegs + --vhook_# Tying this low is safe because the sync reset is used inside DaughterboardRegs. + --vhook_a aReset false + --vhook_a bReset to_boolean(bBusReset) + --vhook_a bRegPortOut bDbRegPortOut + --vhook_a kDbId std_logic_vector(to_unsigned(kDbId,kDbIdSize)) + DaughterboardRegsx: entity work.DaughterboardRegs (RTL) + port map ( + aReset => false, --in boolean + bReset => to_boolean(bBusReset), --in boolean + BusClk => BusClk, --in std_logic + bRegPortOut => bDbRegPortOut, --out RegPortOut_t + bRegPortIn => bRegPortIn, --in RegPortIn_t + kDbId => std_logic_vector(to_unsigned(kDbId,kDbIdSize)), --in std_logic_vector(15:0) + kSlotId => kSlotId); --in std_logic + + + + +end RTL; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf new file mode 100644 index 000000000..c9df3749b Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore.edf differ diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd new file mode 100644 index 000000000..bf75e9d0d --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/Jesd204bXcvrCore_stub.vhd @@ -0,0 +1,54 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 +-- Date : Fri Nov 9 16:19:51 2018 +-- Host : hjimenez running 64-bit major release (build 9200) +-- Command : write_vhdl -mode synth_stub -force -file ./Jesd204bXcvrCore_stub.vhd +-- Design : Jesd204bXcvrCore +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Jesd204bXcvrCore is + Port ( + bBusReset : in STD_LOGIC; + BusClk : in STD_LOGIC; + ReliableClk40 : in STD_LOGIC; + FpgaClk1x : in STD_LOGIC; + FpgaClk2x : in STD_LOGIC; + bFpgaClksStable : in STD_LOGIC; + JesdRefClk_p : in STD_LOGIC; + JesdRefClk_n : in STD_LOGIC; + bJesdRefClkPresent : out STD_LOGIC; + aLmkSync : out STD_LOGIC; + bRegPortInFlat : in STD_LOGIC_VECTOR ( 49 downto 0 ); + bRegPortOutFlat : out STD_LOGIC_VECTOR ( 33 downto 0 ); + CaptureSysRefClk : in STD_LOGIC; + cSysRefFpgaLvds_p : in STD_LOGIC; + cSysRefFpgaLvds_n : in STD_LOGIC; + fSysRef : out STD_LOGIC; + aAdcRx_p : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aAdcRx_n : in STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncAdcOut_n : out STD_LOGIC; + aDacTx_p : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aDacTx_n : out STD_LOGIC_VECTOR ( 3 downto 0 ); + aSyncDacIn_n : in STD_LOGIC; + fAdcDataFlatter : out STD_LOGIC_VECTOR ( 63 downto 0 ); + fDacDataFlatter : in STD_LOGIC_VECTOR ( 63 downto 0 ); + fAdcDataValid : out STD_LOGIC; + fDacReadyForInput : out STD_LOGIC; + aDacSync : out STD_LOGIC; + aAdcSync : out STD_LOGIC + ); + +end Jesd204bXcvrCore; + +architecture stub of Jesd204bXcvrCore is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "bBusReset,BusClk,ReliableClk40,FpgaClk1x,FpgaClk2x,bFpgaClksStable,JesdRefClk_p,JesdRefClk_n,bJesdRefClkPresent,aLmkSync,bRegPortInFlat[49:0],bRegPortOutFlat[33:0],CaptureSysRefClk,cSysRefFpgaLvds_p,cSysRefFpgaLvds_n,fSysRef,aAdcRx_p[3:0],aAdcRx_n[3:0],aSyncAdcOut_n,aDacTx_p[3:0],aDacTx_n[3:0],aSyncDacIn_n,fAdcDataFlatter[63:0],fDacDataFlatter[63:0],fAdcDataValid,fDacReadyForInput,aDacSync,aAdcSync"; +begin +end; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd new file mode 100644 index 000000000..8512d133a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgAdcDacInterfaceTypes.vhd @@ -0,0 +1,302 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgAdcDacInterfaceTypes.vhd +-- Author: National Instruments +-- Original Project: USRP N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- (c) 2018 Copyright National Instruments Corporation +-- All Rights Reserved +-- National Instruments Internal Information +------------------------------------------------------------------------------- +-- +-- Purpose: Contains types for ADC and DAC data so they can more easily be +-- passed through the design. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgJesdConfig.all; + + +package PkgAdcDacInterfaceTypes is + + -- Data type for the DACs. + type DacData_t is record + I : std_logic_vector(kDacDataWidth - 1 downto 0); + Q : std_logic_vector(kDacDataWidth - 1 downto 0); + end record; + + -- Data type for the ADCs. + type AdcData_t is record + I : std_logic_vector(kAdcDataWidth - 1 downto 0); + Q : std_logic_vector(kAdcDataWidth - 1 downto 0); + end record; + + -- Type has two bits that correspond to I and Q; example usage: overrange flags. + type IQFlags_t is record + I : std_logic; + Q : std_logic; + end record; + + -- Single data type for all information from the ADCs. + type AdcSamples_t is record + Data : AdcData_t; + Over : IQFlags_t; + CBit1 : IQFlags_t; + end record; + + -- Single data type for all information to the DACs. + type DacSamples_t is record + Data : DacData_t; + end record; + + -- To support multiple data values per clock cycle, these types + -- are arrays of the ADC and DAC data types where the size of the array + -- corresponds to the number of samples per cycle. + type AdcDataAry_t is array (kSamplesPerCycle - 1 downto 0) of AdcSamples_t; + type DacDataAry_t is array (kSamplesPerCycle - 1 downto 0) of DacSamples_t; + + -- Zero/default constant + constant kAdcDataAryZero : AdcDataAry_t := + (others => (Data => (others => (others => '0')), + Over => (others => '0'), + CBit1 => (others => '0')) + ); + + -- Zero/default constant + constant kDacDataAryZero : DacDataAry_t := + (others => (Data => (others => (others => '0'))) + ); + + -- Flattened type that converts the ADC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data to the top level. + type AdcDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kAdcDataWidth - 1 downto 0); + OverI : std_logic_vector(kSamplesPerCycle - 1 downto 0); + OverQ : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1I : std_logic_vector(kSamplesPerCycle - 1 downto 0); + CBit1Q : std_logic_vector(kSamplesPerCycle - 1 downto 0); + end record; + + -- Fully flattened ADC data for passing into and out of presynthesized components. + subtype AdcDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*(kAdcDataWidth + 2)) - 1 downto 0); + + -- Flattened type that converts the DAC data into std_logic_vector types. This type is + -- not suitable for use in the port maps of components that are presynthesized (into EDF + -- or NGC files) but is useful for passing data from the top level. + type DacDataAryFlat_t is record + DataI : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + DataQ : std_logic_vector(kSamplesPerCycle*kDacDataWidth - 1 downto 0); + end record; + + -- Fully flattened DAC data for passing into and out of presynthesized components. + subtype DacDataAryFlatter_t is std_logic_vector(2*(kSamplesPerCycle*kDacDataWidth) - 1 downto 0); + + -- Function to convert types defined above for the ADC data + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlat_t; + function Flatten (AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t; + function Flatten (AdcData : AdcDataAry_t) return AdcDataAryFlatter_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t; + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t; + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t; + + + -- Function to convert types defined above for the DAC data + function Flatten (DacData : DacDataAry_t) return DacDataAryFlat_t; + function Flatten (DacData : DacDataAryFlat_t) return DacDataAryFlatter_t; + function Flatten (DacData : DacDataAry_t) return DacDataAryFlatter_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t; + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t; + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t; + + +end package PkgAdcDacInterfaceTypes; + + +package body PkgAdcDacInterfaceTypes is + + -- Flattens AdcDataAry_t to AdcDataAryFlat_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar := (DataI => (others => '0'), -- Note (others => (others => '0')) does not work here + DataQ => (others => '0'), -- since DataX and OverX/CBit1X are of different lengths (ModelSim error) + OverI => (others => '0'), + OverQ => (others => '0'), + CBit1I => (others => '0'), + CBit1Q => (others => '0')); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar.DataI((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.I; -- Input Data 0 to MSB + ReturnVar.DataQ((kSamplesPerCycle - i)*kAdcDataWidth - 1 downto (kSamplesPerCycle - 1 - i)*kAdcDataWidth) := AdcData(i).Data.Q; + ReturnVar.OverI (kSamplesPerCycle - 1 - i) := AdcData(i).Over.I; -- Input Data 0 to MSB + ReturnVar.OverQ (kSamplesPerCycle - 1 - i) := AdcData(i).Over.Q; + ReturnVar.CBit1I(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.I; + ReturnVar.CBit1Q(kSamplesPerCycle - 1 - i) := AdcData(i).CBit1.Q; + end loop; + + return ReturnVar; + end function Flatten; + + + -- UnFlattens AdcDataAryFlat_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlat_t) return AdcDataAry_t + is + variable ReturnVar : AdcDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')), Over => (others => '0'), CBit1 => (others => '0'))); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := AdcData.DataI((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := AdcData.DataQ((i+1)*kAdcDataWidth - 1 downto i*kAdcDataWidth); + ReturnVar(kSamplesPerCycle - 1 - i).Over.I := AdcData.OverI(i); + ReturnVar(kSamplesPerCycle - 1 - i).Over.Q := AdcData.OverQ(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.I := AdcData.CBit1I(i); + ReturnVar(kSamplesPerCycle - 1 - i).CBit1.Q := AdcData.CBit1Q(i); + end loop; + return ReturnVar; + end function Unflatten; + + + + + -- Flattens AdcDataAryFlat_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAryFlat_t) return AdcDataAryFlatter_t + is + variable ReturnVar : AdcDataAryFlatter_t; + begin + ReturnVar := AdcData.OverQ & AdcData.CBit1Q & AdcData.OverI & AdcData.CBit1I & AdcData.DataQ & AdcData.DataI; + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAryFlat_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAryFlat_t + is + variable ReturnVar : AdcDataAryFlat_t; + begin + ReturnVar.DataI := AdcData(1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 0*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.DataQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle - 1 downto 1*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.CBit1I := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 0*kSamplesPerCycle); + ReturnVar.OverI := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 1*kSamplesPerCycle); + ReturnVar.CBit1Q := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 2*kSamplesPerCycle); + ReturnVar.OverQ := AdcData(2*kSamplesPerCycle*kAdcDataWidth + 4*kSamplesPerCycle - 1 downto 2*kSamplesPerCycle*kAdcDataWidth + 3*kSamplesPerCycle); + return ReturnVar; + end function Unflatten; + + + -- Flattens AdcDataAry_t to AdcDataAryFlatter_t + function Flatten(AdcData : AdcDataAry_t) return AdcDataAryFlatter_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAryFlatter_t; + begin + TempVar := Flatten(AdcData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens AdcDataAryFlatter_t to AdcDataAry_t + function Unflatten(AdcData : AdcDataAryFlatter_t) return AdcDataAry_t + is + variable TempVar : AdcDataAryFlat_t; + variable ReturnVar : AdcDataAry_t; + begin + TempVar := Unflatten(AdcData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + + + -- Flattens DacDataAry_t to DacDataAryFlat_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar := (others => (others => '0')); + for i in 0 to kSamplesPerCycle - 1 loop + -- MSB of flattened word = 0th element of ADC data array - this corresponds to how TheWindow + -- expects data arrays to be transferred. + ReturnVar.DataI((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.I; + ReturnVar.DataQ((i+1)*kDacDataWidth - 1 downto i*kDacDataWidth) := DacData(kSamplesPerCycle - 1 - i).Data.Q; + end loop; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlat_t to DacDataAry_t + function UnFlatten(DacData : DacDataAryFlat_t) return DacDataAry_t + is + variable ReturnVar : DacDataAry_t; + begin + ReturnVar := (others => (Data => (others => (others => '0')))); + + -- The upstream logic puts the 0th element of an array in the MSBs of its data word + for i in 0 to kSamplesPerCycle - 1 loop + ReturnVar(kSamplesPerCycle - 1 - i).Data.I := DacData.DataI(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + ReturnVar(kSamplesPerCycle - 1 - i).Data.Q := DacData.DataQ(kDacDataWidth*(i+1) - 1 downto kDacDataWidth*i); + end loop; + + return ReturnVar; + end function UnFlatten; + + + + -- Flattens DacDataAryFlat_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAryFlat_t) return DacDataAryFlatter_t + is + variable ReturnVar : DacDataAryFlatter_t; + begin + ReturnVar := DacData.DataQ & DacData.DataI; + return ReturnVar; + end function Flatten; + + + -- UnFlattens DacDataAryFlatter_t to DacDataAryFlat_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAryFlat_t + is + variable ReturnVar : DacDataAryFlat_t; + begin + ReturnVar.DataI := DacData(1*kSamplesPerCycle*kDacDataWidth - 1 downto 0*kSamplesPerCycle*kDacDataWidth); + ReturnVar.DataQ := DacData(2*kSamplesPerCycle*kDacDataWidth - 1 downto 1*kSamplesPerCycle*kDacDataWidth); + return ReturnVar; + end function Unflatten; + + + -- Flattens DacDataAry_t to DacDataAryFlatter_t + function Flatten(DacData : DacDataAry_t) return DacDataAryFlatter_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAryFlatter_t; + begin + TempVar := Flatten(DacData); + ReturnVar := Flatten(TempVar); + return ReturnVar; + end function Flatten; + + -- UnFlattens DacDataAryFlatter_t to DacDataAry_t + function Unflatten(DacData : DacDataAryFlatter_t) return DacDataAry_t + is + variable TempVar : DacDataAryFlat_t; + variable ReturnVar : DacDataAry_t; + begin + TempVar := Unflatten(DacData); + ReturnVar := Unflatten(TempVar); + return ReturnVar; + end function Unflatten; + + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd new file mode 100644 index 000000000..03b95c100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgClockingRegMap.vhd @@ -0,0 +1,107 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgClockingRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgClockingRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- RadioClkMmcm : 0x20 (ClockingRegs.vhd) + -- PhaseShiftControl : 0x24 (ClockingRegs.vhd) + -- RadioClkEnables : 0x28 (ClockingRegs.vhd) + -- MgtRefClkStatus : 0x30 (ClockingRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group ClockingRegs +--=============================================================================== + + -- RadioClkMmcm Register (from ClockingRegs.vhd) + constant kRadioClkMmcm : integer := 16#20#; -- Register Offset + constant kRadioClkMmcmSize: integer := 32; -- register width in bits + constant kRadioClkMmcmMask : std_logic_vector(31 downto 0) := X"00000013"; + constant kRadioClkMmcmResetSetSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSetMsb : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetSet : integer := 0; --RadioClkMmcm:RadioClkMmcmResetSet + constant kRadioClkMmcmResetClearSize : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClearMsb : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmResetClear : integer := 1; --RadioClkMmcm:RadioClkMmcmResetClear + constant kRadioClkMmcmLockedSize : integer := 1; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLockedMsb : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + constant kRadioClkMmcmLocked : integer := 4; --RadioClkMmcm:RadioClkMmcmLocked + + -- PhaseShiftControl Register (from ClockingRegs.vhd) + constant kPhaseShiftControl : integer := 16#24#; -- Register Offset + constant kPhaseShiftControlSize: integer := 32; -- register width in bits + constant kPhaseShiftControlMask : std_logic_vector(31 downto 0) := X"10010011"; + constant kPsIncSize : integer := 1; --PhaseShiftControl:PsInc + constant kPsIncMsb : integer := 0; --PhaseShiftControl:PsInc + constant kPsInc : integer := 0; --PhaseShiftControl:PsInc + constant kPsDecSize : integer := 1; --PhaseShiftControl:PsDec + constant kPsDecMsb : integer := 4; --PhaseShiftControl:PsDec + constant kPsDec : integer := 4; --PhaseShiftControl:PsDec + constant kPsEnabledForFdbClkSize : integer := 1; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClkMsb : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsEnabledForFdbClk : integer := 16; --PhaseShiftControl:PsEnabledForFdbClk + constant kPsDoneSize : integer := 1; --PhaseShiftControl:PsDone + constant kPsDoneMsb : integer := 28; --PhaseShiftControl:PsDone + constant kPsDone : integer := 28; --PhaseShiftControl:PsDone + + -- RadioClkEnables Register (from ClockingRegs.vhd) + constant kRadioClkEnables : integer := 16#28#; -- Register Offset + constant kRadioClkEnablesSize: integer := 32; -- register width in bits + constant kRadioClkEnablesMask : std_logic_vector(31 downto 0) := X"00000111"; + constant kRadioClk1xEnabledSize : integer := 1; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabledMsb : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk1xEnabled : integer := 0; --RadioClkEnables:RadioClk1xEnabled + constant kRadioClk2xEnabledSize : integer := 1; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabledMsb : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk2xEnabled : integer := 4; --RadioClkEnables:RadioClk2xEnabled + constant kRadioClk3xEnabledSize : integer := 1; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabledMsb : integer := 8; --RadioClkEnables:RadioClk3xEnabled + constant kRadioClk3xEnabled : integer := 8; --RadioClkEnables:RadioClk3xEnabled + + -- MgtRefClkStatus Register (from ClockingRegs.vhd) + constant kMgtRefClkStatus : integer := 16#30#; -- Register Offset + constant kMgtRefClkStatusSize: integer := 32; -- register width in bits + constant kMgtRefClkStatusMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kJesdRefClkPresentSize : integer := 1; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresentMsb : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + constant kJesdRefClkPresent : integer := 0; --MgtRefClkStatus:JesdRefClkPresent + +end package; + +package body PkgClockingRegMap is + + -- function kRadioClkMmcmRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kPhaseShiftControlRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kRadioClkEnablesRec not implemented because PkgXReg in this project does not support XReg2_t. + + -- function kMgtRefClkStatusRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd new file mode 100644 index 000000000..06708cde3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgDaughterboardRegMap.vhd @@ -0,0 +1,56 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgDaughterboardRegMap.vhd +-- Author: Autogenerated by XmlParse +-- Original Project: -- +-- Date: -- +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse and should +-- be used by testbench code to access specific register fields. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgDaughterboardRegMap is + +--=============================================================================== +-- A numerically ordered list of registers and their VHDL source files +--=============================================================================== + + -- DaughterboardId : 0x630 (DaughterboardRegs.vhd) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group StaticControl +--=============================================================================== + + -- DaughterboardId Register (from DaughterboardRegs.vhd) + constant kDaughterboardId : integer := 16#630#; -- Register Offset + constant kDaughterboardIdSize: integer := 32; -- register width in bits + constant kDaughterboardIdMask : std_logic_vector(31 downto 0) := X"0001ffff"; + constant kDbIdValSize : integer := 16; --DaughterboardId:DbIdVal + constant kDbIdValMsb : integer := 15; --DaughterboardId:DbIdVal + constant kDbIdVal : integer := 0; --DaughterboardId:DbIdVal + constant kSlotIdValSize : integer := 1; --DaughterboardId:SlotIdVal + constant kSlotIdValMsb : integer := 16; --DaughterboardId:SlotIdVal + constant kSlotIdVal : integer := 16; --DaughterboardId:SlotIdVal + +end package; + +package body PkgDaughterboardRegMap is + + -- function kDaughterboardIdRec not implemented because PkgXReg in this project does not support XReg2_t. + +end package body; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd new file mode 100644 index 000000000..4913b03fc --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgJesdConfig.vhd @@ -0,0 +1,165 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgJesdConfig.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: JESD204B setup constants and functions. These constants are shared +-- between RX and TX JESD cores. +-- +-- vreview_group JesdCoreN32x +-- vreview_reviewers djepson wfife +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgJesdConfig is + + -- "JESD" in ASCII - with the core number 0 or 1 on the LSb. + constant kJesdSignature : std_logic_vector(31 downto 0) := x"4a455344"; + + -- Register endpoints + constant kJesdDrpRegsInEndpoint : RegOffset_t := (kOffset => 16#0800#, -- 0x2800 to + kWidth => 16#0800#); -- 0x2FFF + + -- Selects the UsrClk2 for the transceivers. For 64-bit wide transceivers, the + -- UsrClk = 2*UserClk2 frequency. For 32-bit wide transceivers, UsrClk = UserClk2 + -- frequency. This is a generalization, the clock ratio should be confirmed based on + -- the transceiver configuration. + -- The N310 transceivers use the single rate reference, hence = false. + constant kDoubleRateUsrClk : boolean := false; + + -- For the N32x, all lanes are in one quad and we use the QPLL. + constant kJesdUseQpll : boolean := true; + + constant kAdcDataWidth : integer := 14; -- ADC data width in bits + constant kDacDataWidth : integer := 16; -- DAC data width in bits + constant kSamplesPerCycle : integer := 2; -- Number of samples per SampleClk1x + + constant kGtxDrpAddrWidth : natural := 9; + constant kGtxAddrLsbPosition : natural := 2; + constant kQpllDrpAddrWidth : natural := 8; + constant kGtxDrpDataWidth : natural := 16; + + -- Max supported number of lanes + constant kMaxNumLanes : natural := 4; + -- Max supported number of quads (normally there is 1 quad per 4 lanes but disconnect + -- the definitions to allow quad sharing) + constant kMaxNumQuads : natural := 1; + + -- Rhodium: + -- JESD shared setup - LMFS = 4211, HD = 1 (Samples are split across multiple lanes). + constant kNumLanes : natural := 4; -- L + constant kNumConvs : positive := 2; -- M + constant kOctetsPerFrame : natural := 1; -- F + constant kDacJesdSamplesPerCycle : integer := 1; -- S + constant kOctetsPerLane : natural := 2; -- MGT data is kOctetsPerLane*8 = 16 bits wide + constant kNumQuads : natural := kNumLanes / 4; -- 4 lanes per quad + constant kHighDensity : boolean := true; -- HD + constant kConvResBits : positive := kDacDataWidth; -- Converter resolution in bits + constant kConvSampleBits : positive := 16; -- Sample Length in bits + constant kInitLaneAlignCnt : positive := 4; + constant kFramesPerMulti : natural := 24; -- K + + -- Rhodium: + -- The converters are running at 400/491.52/500 MSPS (DeviceClk), and the sampling + -- clock at the FPGA (UserClk) is 200/245.76/250 MHz; so UsrClk = (DeviceClk / 2). + -- The frame rate = DeviceClk, and the Multiframe rate = (frame rate / kFramesPerMulti) + -- Thus, kUserClksPerMulti = (UsrClk / Multiframe rate) + -- = (UsrClk / (DeviceClk / kFramesPerMulti)) + -- since UsrClk = DeviceClk / 2 then, + -- kUserClksPerMulti = ((DeviceClk / 2) / (DeviceClk / kFramesPerMulti)) + -- therefore, + -- kUserClksPerMulti = kFramesPerMulti / 2 + constant kUserClksPerMulti : integer := kFramesPerMulti / 2; + + + type NaturalVector is array ( natural range <>) of natural; + + -- The PCB connections are are passed trough, any swapping is handled somewhere else. + -- + -- Transceiver MGT Channel ADC Lane DAC Lane + -- *********** *********** ******** ******** + -- GT0: X0Y8 0 0 0 + -- GT1: X0Y9 1 1 1 + -- GT2: X0Y10 2 2 2 + -- GT3: X0Y11 3 3 3 + constant kRxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => ADC (in above table) + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kTxLaneIndices : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- MGT => DAC lane + 0 => 0, + 1 => 1, + 2 => 2, + 3 => 3 + ); + + constant kLaneToQuadMap : NaturalVector(kNumLanes - 1 downto 0) := + ( + -- All lanes are in one quad + 0 => 0, + 1 => 0, + 2 => 0, + 3 => 0 + ); + + + -- The master transceiver channel for channel bonding. E(kMasterBondingChannel) + -- must have the highest value decrementing to b"000" for that last channels to bond. + constant kMasterBondingChannel : integer := 1; + + -- Channel bonding occurs when a master detects a K-char sequence and aligns its + -- internal FIFO to the start of this sequence. A signal is then generated to other + -- slave transceivers that cause them to bond to the sequence - this bonding signal is + -- cascaded from master to slave to slave to slave, etc where each slave must know how + -- many levels to the master there are. The last slave to bond must be at level b"000" + -- and the master is at the highest level; the number of levels in the sequence is + -- governed by the size of the transceiver FIFO (see the Xilinx user guides for more + -- information). + type BondLevels_t is array(0 to kNumLanes - 1) of std_logic_vector(2 downto 0); + constant kBondLevel : BondLevels_t := ( + 0 => b"000", -- Control from 1 + 1 => b"001", -- Master + 2 => b"000", -- Control from 1 + 3 => b"000" -- Control from 1 + ); + + + -- User Rx Data + -- ADC Word data width: 14 sample bits + 2 tails bits + constant kAdcWordWidth : integer := 16; + subtype AdcWord_t is std_logic_vector(kAdcWordWidth - 1 downto 0); + type AdcWordArray_t is array(kSamplesPerCycle*2 - 1 downto 0) of AdcWord_t; -- The *2 is because there are two samples (I and Q) per "sample" + + -- Constants to specify the contents of the AdcWord_t vector. + constant kAdcWordDataMsb : integer := 15; + constant kAdcWordDataLsb : integer := 2; + constant kAdcWordOver : integer := 1; + constant kAdcWordCBit1 : integer := 0; + + + -- Option to pipeline stages to improve timing, if needed + constant kPipelineDetectCharsStage : boolean := false; + constant kPipelineCharReplStage : boolean := false; + +end package; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd new file mode 100644 index 000000000..801a46d15 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/PkgRhPersonality.vhd @@ -0,0 +1,62 @@ +------------------------------------------------------------------------------- +-- +-- File: PkgRhPersonality.vhd +-- Author: National Instruments +-- Original Project: N32x +-- Date: 15 Dec 2017 +-- +------------------------------------------------------------------------------- +-- Copyright 2017 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: GPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: This package contains constants and helpful functions that enable +-- the FPGA to be compiled with different features. +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.PkgRegs.all; + + +package PkgRhPersonality is + + -- Rhodium daughterboard ID definition. + constant kDbId : integer := 16#152#; + constant kDbIdSize : integer := 16; + + + -- RegPort Address Definitions : ------------------------------------------------------ + -- + -- DB Regs ... + -- + -- Clocking Offset: 0x 000 Width: 0x 200 + -- Tdco0 Offset: 0x 200 Width: 0x 200 + -- Tdco1 Offset: 0x 400 Width: 0x 200 + -- Daughterboard Ctrl Offset: 0x 600 Width: 0x 200 + -- Total: 0x2000 + -- JESD 2x - A Offset: 0x2000 Width: 0x1000 + -- JESD 2x - B Offset: 0x3000 Width: 0x1000 + -- Total: 0x4000 + -- Total: 0x8000 for two DBs + -- ------------------------------------------------------------------------------------ + + -- A single RegPort runs to the JESD204B Core. + constant kJesdRegGroupInDbRegs : RegOffset_t := (kOffset => 16#2000#, -- 0x2000 to + kWidth => 16#1000#); -- 0x2FFF + + -- DB Regs : -------------------------------------------------------------------------- + constant kClockingOffsetInEndpoint : RegOffset_t := (kOffset => 16#0000#, -- 0x0000 to + kWidth => 16#0200#); -- 0x01FF + constant kTdc0OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0200#, -- 0x0200 to + kWidth => 16#0200#); -- 0x03FF + constant kTdc1OffsetsInEndpoint : RegOffset_t := (kOffset => 16#0400#, -- 0x0400 to + kWidth => 16#0200#); -- 0x05FF + constant kDaughterboardOffsetInEndpoint : RegOffset_t := (kOffset => 16#0600#, -- 0x0600 to + kWidth => 16#0200#); -- 0x07FF + +end package PkgRhPersonality; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd new file mode 100644 index 000000000..69a15d49a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/RadioClocking.vhd @@ -0,0 +1,305 @@ +------------------------------------------------------------------------------- +-- +-- File: RadioClocking.vhd +-- Author: Daniel Jepson +-- Original Project: N310 +-- Date: 22 February 2016 +-- +------------------------------------------------------------------------------- +-- Copyright 2016-2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Instantiates a MMCM to produce 1x, 2x, and 3x versions of the Radio Clock +-- coming from the FPGA input pin. Handles all the buffering for the input clock. +-- Additionally allows the clocks to be turned on and off, and phase shifted. +-- +-- NOTE: This module hard-codes the MMCM settings for a SPECIFIC clock rate! +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + +library unisim; + use unisim.vcomponents.all; + + +entity RadioClocking is + port ( + -- Async reset. Can be tied low if desired. + aReset : in boolean; + -- Sync reset... used in the same places as the async one. + bReset : in boolean; + + -- Should be a always-on clock + BusClk : in std_logic; + + -- Sync reset to the RadioClkMmcm. + bRadioClkMmcmReset : in std_logic; + + -- Locked indication from the RadioClkMmcm in BusClk and aReset domains. + bRadioClksValid : out std_logic; + + bRadioClk1xEnabled : in std_logic; + bRadioClk2xEnabled : in std_logic; + bRadioClk3xEnabled : in std_logic; + + -- Phase shift interface for the RadioClkMmcm. PsClk must be <= 200 MHz. + pPsInc : in std_logic; + pPsEn : in std_logic; + PsClk : in std_logic; + pPsDone : out std_logic; + + -- Straight from pins. Buffer included in here. + FpgaClk_n : in std_logic; + FpgaClk_p : in std_logic; + + RadioClk1x : out std_logic; + RadioClk2x : out std_logic; + RadioClk3x : out std_logic + + ); +end RadioClocking; + + +architecture rtl of RadioClocking is + + --vhook_sigstart + signal RadioClk1xLcl: std_logic; + signal RadioClk1xPll: std_logic; + signal RadioClk2xLcl: std_logic; + signal RadioClk2xPll: std_logic; + signal RadioClk3xLcl: std_logic; + signal RadioClk3xPll: std_logic; + --vhook_sigend + + signal RadioClkMmcmFeedbackIn, + RadioClkMmcmFeedbackOut, + FpgaClkSE, + aRadioClkMmcmLocked : std_logic; + + signal bRadioClkMmcmLocked_ms, + bRadioClkMmcmLocked, + bEnableRadioClkBufgOutputs, + bEnableRadioClk1xBufgOutput, + bEnableRadioClk2xBufgOutput, + bEnableRadioClk3xBufgOutput : std_logic := '0'; + + signal aRadioClkMmcmResetInternal : std_logic := '1'; + + attribute ASYNC_REG : string; + attribute ASYNC_REG of bRadioClkMmcmLocked_ms : signal is "true"; + attribute ASYNC_REG of bRadioClkMmcmLocked : signal is "true"; + +begin + + -- Radio Clock Buffering : ------------------------------------------------------------ + -- + -- ------------------------------------------------------------------------------------ + --vhook_i IBUFDS FpgaClkIbufg hidegeneric=true + --vhook_a I FpgaClk_p + --vhook_a IB FpgaClk_n + --vhook_a O FpgaClkSE + FpgaClkIbufg: IBUFDS + port map ( + O => FpgaClkSE, --out std_ulogic + I => FpgaClk_p, --in std_ulogic + IB => FpgaClk_n); --in std_ulogic + + + ResetDelay : process(aReset, BusClk) + begin + if aReset then + aRadioClkMmcmResetInternal <= '1'; + elsif rising_edge(BusClk) then + if bReset then + aRadioClkMmcmResetInternal <= '1'; + else + -- Delay by 1 to allow the BUFGs to turn off before the MMCM is reset. + aRadioClkMmcmResetInternal <= bRadioClkMmcmReset; + end if; + end if; + end process ResetDelay; + + + RadioClkMmcm: MMCME2_ADV + generic map( + COMPENSATION => "ZHOLD", + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 4.000, -- Feedback + CLKOUT0_DIVIDE_F => 4.000, -- Data Clock 1x, RadioClk1xPll + CLKOUT1_DIVIDE => 2, -- Data Clock 2x, RadioClk2xPll + CLKOUT2_DIVIDE => 2, -- Data Clock 3x, RadioClk3xPll + CLKOUT3_DIVIDE => 1, -- unused + CLKOUT4_DIVIDE => 1, -- unused + CLKOUT5_DIVIDE => 1, -- unused + CLKOUT6_DIVIDE => 1, -- unused + CLKFBOUT_PHASE => 0.000, -- Feedback + CLKOUT0_PHASE => 0.000, -- Data Clock 1x + CLKOUT1_PHASE => 0.000, -- Data Clock 2x + CLKOUT2_PHASE => 0.000, -- Data Clock 3x + CLKOUT3_PHASE => 0.000, -- unused + CLKOUT4_PHASE => 0.000, -- unused + CLKOUT5_PHASE => 0.000, -- unused + CLKOUT6_PHASE => 0.000, -- unused + CLKOUT0_DUTY_CYCLE => 0.500, + CLKOUT1_DUTY_CYCLE => 0.500, + CLKOUT2_DUTY_CYCLE => 0.500, + CLKOUT3_DUTY_CYCLE => 0.500, + CLKOUT4_DUTY_CYCLE => 0.500, + CLKOUT5_DUTY_CYCLE => 0.500, + CLKOUT6_DUTY_CYCLE => 0.500, + DIVCLK_DIVIDE => 1, + REF_JITTER1 => 0.010, + CLKIN1_PERIOD => 4.069, -- 245.76 MHz max + CLKFBOUT_USE_FINE_PS => true, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_USE_FINE_PS => false, + STARTUP_WAIT => false, + CLKOUT4_CASCADE => false) + port map ( + CLKINSEL => '1', + CLKIN1 => FpgaClkSE, + CLKIN2 => '0', + CLKFBIN => RadioClkMmcmFeedbackIn, + RST => aRadioClkMmcmResetInternal, + PWRDWN => '0', + DADDR => (others => '0'), + DI => (others => '0'), + DWE => '0', + DEN => '0', + DCLK => '0', + DO => open, + DRDY => open, + PSINCDEC => pPsInc, + PSEN => pPsEn, + PSCLK => PsClk, + PSDONE => pPsDone, + CLKOUT0 => RadioClk1xPll, + CLKOUT0B => open, + CLKOUT1 => RadioClk2xPll, + CLKOUT1B => open, + CLKOUT2 => RadioClk3xPll, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + CLKFBOUT => RadioClkMmcmFeedbackOut, + CLKFBOUTB => open, + LOCKED => aRadioClkMmcmLocked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open); + + RadioClkMmcmFeedbackBufg: BUFG + port map ( + I => RadioClkMmcmFeedbackOut, + O => RadioClkMmcmFeedbackIn + ); + + + -- Only enable the WRAPBUFGs when the MMCM is locked. If the MMCM is ever placed in + -- reset, we turn off the clocks one cycle before the asynchronous version + -- (aRadioClkMmcmResetInternal) reaches the MMCM inputs in order to prevent + -- output glitches. + CombineEnablesForBuffers : process(aReset, BusClk) + begin + if aReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + elsif rising_edge(BusClk) then + if bReset then + bRadioClkMmcmLocked_ms <= '0'; + bRadioClkMmcmLocked <= '0'; + bEnableRadioClk1xBufgOutput <= '0'; + bEnableRadioClk2xBufgOutput <= '0'; + bEnableRadioClk3xBufgOutput <= '0'; + bEnableRadioClkBufgOutputs <= '0'; + else + bRadioClkMmcmLocked_ms <= aRadioClkMmcmLocked; + bRadioClkMmcmLocked <= bRadioClkMmcmLocked_ms; + + bEnableRadioClkBufgOutputs <= bRadioClkMmcmLocked and + not bRadioClkMmcmReset; + bEnableRadioClk1xBufgOutput <= bRadioClk1xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk2xBufgOutput <= bRadioClk2xEnabled and bEnableRadioClkBufgOutputs; + bEnableRadioClk3xBufgOutput <= bRadioClk3xEnabled and bEnableRadioClkBufgOutputs; + end if; + end if; + end process CombineEnablesForBuffers; + + bRadioClksValid <= bEnableRadioClkBufgOutputs; + + --vhook_e WrapBufg RadioClk1xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk1xPll + --vhook_a aCe bEnableRadioClk1xBufgOutput + --vhook_a ClkOut RadioClk1xLcl + RadioClk1xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk1xPll, --in std_logic + aCe => bEnableRadioClk1xBufgOutput, --in std_logic + ClkOut => RadioClk1xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk2xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk2xPll + --vhook_a aCe bEnableRadioClk2xBufgOutput + --vhook_a ClkOut RadioClk2xLcl + RadioClk2xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk2xPll, --in std_logic + aCe => bEnableRadioClk2xBufgOutput, --in std_logic + ClkOut => RadioClk2xLcl); --out std_logic + + --vhook_e WrapBufg RadioClk3xBuf + --vhook_a kEnableByDefault false + --vhook_a kIgnore false + --vhook_a kEnableIsAsync true + --vhook_a ClkIn RadioClk3xPll + --vhook_a aCe bEnableRadioClk3xBufgOutput + --vhook_a ClkOut RadioClk3xLcl + RadioClk3xBuf: entity work.WrapBufg (rtl) + generic map ( + kEnableByDefault => false, --boolean:=false + kIgnore => false, --boolean:=false + kEnableIsAsync => true) --boolean:=false + port map ( + ClkIn => RadioClk3xPll, --in std_logic + aCe => bEnableRadioClk3xBufgOutput, --in std_logic + ClkOut => RadioClk3xLcl); --out std_logic + + + -- Assign outputs from locals. + RadioClk1x <= RadioClk1xLcl; + RadioClk2x <= RadioClk2xLcl; + RadioClk3x <= RadioClk3xLcl; + + + +end rtl; diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc new file mode 100644 index 000000000..b67269cd9 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_pins.xdc @@ -0,0 +1,280 @@ +## TDC : ################################################################################ +## Bank 10, 2.5V (DB A) +######################################################################################### + +set_property PACKAGE_PIN AB15 [get_ports {UNUSED_PIN_TDCA_0}] +set_property PACKAGE_PIN AB14 [get_ports {UNUSED_PIN_TDCA_1}] +set_property PACKAGE_PIN AB16 [get_ports {UNUSED_PIN_TDCA_2}] +set_property PACKAGE_PIN AB17 [get_ports {UNUSED_PIN_TDCA_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCA_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCA_*}] + + +## TDC : ################################################################################ +## Bank 11, 2.5V (DB B) +######################################################################################### + +set_property PACKAGE_PIN W21 [get_ports {UNUSED_PIN_TDCB_0}] +set_property PACKAGE_PIN Y21 [get_ports {UNUSED_PIN_TDCB_1}] +set_property PACKAGE_PIN Y22 [get_ports {UNUSED_PIN_TDCB_2}] +set_property PACKAGE_PIN Y23 [get_ports {UNUSED_PIN_TDCB_3}] +set_property IOSTANDARD LVCMOS25 [get_ports {UNUSED_PIN_TDCB_*}] +set_property IOB TRUE [get_ports {UNUSED_PIN_TDCB_*}] + + +## USRP IO A : ########################################################################## +# DBA +######################################################################################### + +set_property PACKAGE_PIN G1 [get_ports DBA_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN E5 [get_ports DBA_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AF14 [get_ports DBA_FPGA_CLK_P] +set_property PACKAGE_PIN AG14 [get_ports DBA_FPGA_CLK_N] + +set_property PACKAGE_PIN N8 [get_ports DBA_MGTCLK_P] +set_property PACKAGE_PIN N7 [get_ports DBA_MGTCLK_N] + +set_property PACKAGE_PIN AG17 [get_ports DBA_FPGA_SYSREF_P] +set_property PACKAGE_PIN AG16 [get_ports DBA_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBA_FPGA_SYSREF_*] + + +# set_property PACKAGE_PIN AD10 [get_ports NET2CLK_P] +# set_property PACKAGE_PIN AD9 [get_ports NET2CLK_N] + +set_property PACKAGE_PIN C2 [get_ports DBA_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN B1 [get_ports DBA_TXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_LE +set_property PACKAGE_PIN B2 [get_ports DBA_CPLD_PL_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN F4 [get_ports DBA_RXLO_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN F3 [get_ports DBA_LODIS_SPI_CS_B]; # DBA_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN C1 [get_ports DBA_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN A3 [get_ports DBA_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AC16 [get_ports DBA_CPLD_PS_SPI_SCLK]; # DBA_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE15 [get_ports DBA_CPLD_PS_SPI_CS_B]; # DBA_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AE16 [get_ports DBA_PHDAC_SPI_CS_B]; # DBA_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AF17 [get_ports DBA_CLKDIS_SPI_CS_B] +set_property PACKAGE_PIN AK16 [get_ports DBA_ADC_SPI_CS_B]; # DBA_CPLD_UNUSED[12] +set_property PACKAGE_PIN AJ16 [get_ports DBA_DAC_SPI_CS_B]; # DBA_CPLD_UNUSED[13] +set_property PACKAGE_PIN AC17 [get_ports DBA_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AF18 [get_ports DBA_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH13 [get_ports DBA_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AH14 [get_ports DBA_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AE13 [get_ports DBA_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AF13 [get_ports DBA_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN E1 [get_ports DBA_CLKDIST_SYNC] + +set_property PACKAGE_PIN A2 [get_ports DBA_ATR_TX] +set_property PACKAGE_PIN E3 [get_ports DBA_ATR_RX] + +set_property PACKAGE_PIN E2 [get_ports DBA_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN F5 [get_ports DBA_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AE12 [get_ports DBA_ADC_SYNCB_P] +set_property PACKAGE_PIN AF12 [get_ports DBA_ADC_SYNCB_N] +set_property PACKAGE_PIN AD14 [get_ports DBA_DAC_SYNCB_P]; # Layout swapped, RTL is negated. +set_property PACKAGE_PIN AD13 [get_ports DBA_DAC_SYNCB_N]; # Layout swapped, RTL is negated. + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN V6 [get_ports DBA_RX_P[0]] +set_property PACKAGE_PIN V5 [get_ports DBA_RX_N[0]] +set_property PACKAGE_PIN U4 [get_ports DBA_RX_P[1]] +set_property PACKAGE_PIN U3 [get_ports DBA_RX_N[1]] +set_property PACKAGE_PIN T6 [get_ports DBA_RX_P[2]] +set_property PACKAGE_PIN T5 [get_ports DBA_RX_N[2]] +set_property PACKAGE_PIN P6 [get_ports DBA_RX_P[3]] +set_property PACKAGE_PIN P5 [get_ports DBA_RX_N[3]] + +set_property PACKAGE_PIN T2 [get_ports DBA_TX_P[0]] +set_property PACKAGE_PIN T1 [get_ports DBA_TX_N[0]] +set_property PACKAGE_PIN R4 [get_ports DBA_TX_P[1]] +set_property PACKAGE_PIN R3 [get_ports DBA_TX_N[1]] +set_property PACKAGE_PIN P2 [get_ports DBA_TX_P[2]] +set_property PACKAGE_PIN P1 [get_ports DBA_TX_N[2]] +set_property PACKAGE_PIN N4 [get_ports DBA_TX_P[3]] +set_property PACKAGE_PIN N3 [get_ports DBA_TX_N[3]] + +set_property PACKAGE_PIN AG12 [get_ports DBA_LED_RX] +set_property PACKAGE_PIN AH12 [get_ports DBA_LED_RX2] +set_property PACKAGE_PIN AJ13 [get_ports DBA_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN C4 [get_ports DBA_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN C3 [get_ports DBA_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN K1 [get_ports DBA_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L1 [get_ports DBA_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D1 [get_ports DBA_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AE17 [get_ports DBA_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AE18 [get_ports DBA_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AB12 [get_ports DBA_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AC12 [get_ports DBA_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AG17 [get_ports DBA_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK12 [get_ports DBA_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AK13 [get_ports DBA_CPLD_UNUSED[11]] + +set UsrpIoAHpPinsSe [get_ports {DBA_MODULE_PWR_ENABLE \ + DBA_RF_PWR_ENABLE \ + DBA_CPLD_PL_SPI_* \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B \ + DBA_CLKDIST_SYNC \ + DBA_TXRX_SW_CTRL_* \ + DBA_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoAHpPinsSe +set_property DRIVE 6 $UsrpIoAHpPinsSe +set_property SLEW SLOW $UsrpIoAHpPinsSe + +set UsrpIoAHrPinsSeDr4 [get_ports {DBA_LED_* \ + DBA_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoAHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr4 + +set UsrpIoAHrPinsSeDr8 [get_ports {DBA_CPLD_PS_SPI_* \ + DBA_PHDAC_SPI_CS_B \ + DBA_CLKDIS_SPI_CS_B \ + DBA_ADC_SPI_CS_B \ + DBA_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoAHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoAHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoAHrPinsSeDr8 + +set UsrpIoAHrPinsDiff [get_ports {DBA_ADC_SYNCB_* \ + DBA_DAC_SYNCB_* \ + DBA_FPGA_CLK_* \ + DBA_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoAHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoAHrPinsDiff + + +## USRP IO B : ########################################################################## +# DBB +######################################################################################### + +set_property PACKAGE_PIN J4 [get_ports DBB_MODULE_PWR_ENABLE] +set_property PACKAGE_PIN G4 [get_ports DBB_RF_PWR_ENABLE] + +set_property PACKAGE_PIN AG21 [get_ports DBB_FPGA_CLK_P] +set_property PACKAGE_PIN AH21 [get_ports DBB_FPGA_CLK_N] + +set_property PACKAGE_PIN W8 [get_ports DBB_MGTCLK_P] +set_property PACKAGE_PIN W7 [get_ports DBB_MGTCLK_N] + +set_property PACKAGE_PIN AE22 [get_ports DBB_FPGA_SYSREF_P] +set_property PACKAGE_PIN AF22 [get_ports DBB_FPGA_SYSREF_N] +set_property IOB TRUE [get_ports DBB_FPGA_SYSREF_*] + +set_property PACKAGE_PIN K6 [get_ports DBB_CPLD_PL_SPI_SCLK] +set_property PACKAGE_PIN F2 [get_ports DBB_TXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_LE +set_property PACKAGE_PIN G2 [get_ports DBB_CPLD_PL_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[0] +set_property PACKAGE_PIN H4 [get_ports DBB_RXLO_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[1] +set_property PACKAGE_PIN H3 [get_ports DBB_LODIS_SPI_CS_B]; # DBB_CPLD_PL_SPI_ADDR[2] +set_property PACKAGE_PIN J6 [get_ports DBB_CPLD_PL_SPI_MISO] +set_property PACKAGE_PIN D5 [get_ports DBB_CPLD_PL_SPI_MOSI] + +set_property PACKAGE_PIN AG22 [get_ports DBB_CPLD_PS_SPI_SCLK] +set_property PACKAGE_PIN AD23 [get_ports DBB_CPLD_PS_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[0] +set_property PACKAGE_PIN AE23 [get_ports DBB_PHDAC_SPI_CS_B]; # DBB_CPLD_PS_SPI_ADDR[1] +set_property PACKAGE_PIN AB24 [get_ports DBB_CLKDIS_SPI_CS_B]; # DBB_CPLD_PS_SPI_LE +set_property PACKAGE_PIN AJ23 [get_ports DBB_ADC_SPI_CS_B]; # DBB_CPLD_UNUSED[12]] +set_property PACKAGE_PIN AJ24 [get_ports DBB_DAC_SPI_CS_B]; # DBB_CPLD_UNUSED[13]] +set_property PACKAGE_PIN AH22 [get_ports DBB_CPLD_PS_SPI_MISO] +set_property PACKAGE_PIN AA24 [get_ports DBB_CPLD_PS_SPI_MOSI] + +set_property PACKAGE_PIN AH19 [get_ports DBB_CPLD_JTAG_TDI] +set_property PACKAGE_PIN AJ19 [get_ports DBB_CPLD_JTAG_TDO] +set_property PACKAGE_PIN AB21 [get_ports DBB_CPLD_JTAG_TMS] +set_property PACKAGE_PIN AB22 [get_ports DBB_CPLD_JTAG_TCK] + +set_property PACKAGE_PIN D3 [get_ports DBB_CLKDIST_SYNC] + +set_property PACKAGE_PIN E6 [get_ports DBB_ATR_TX] +set_property PACKAGE_PIN J5 [get_ports DBB_ATR_RX] + +set_property PACKAGE_PIN K5 [get_ports DBB_TXRX_SW_CTRL_1] +set_property PACKAGE_PIN G5 [get_ports DBB_TXRX_SW_CTRL_2] + +set_property PACKAGE_PIN AF23 [get_ports DBB_ADC_SYNCB_P] +set_property PACKAGE_PIN AF24 [get_ports DBB_ADC_SYNCB_N] +set_property PACKAGE_PIN AD21 [get_ports DBB_DAC_SYNCB_P] +set_property PACKAGE_PIN AE21 [get_ports DBB_DAC_SYNCB_N] + +# This mapping uses the TX pins as the "master" and mimics RX off of them so Vivado +# places the transceivers in the correct places. The mixup in lanes is accounted for +# in the AD9695 and the DAC37J82 crossbar settings. +set_property PACKAGE_PIN AC4 [get_ports DBB_RX_P[0]] +set_property PACKAGE_PIN AC3 [get_ports DBB_RX_N[0]] +set_property PACKAGE_PIN AB6 [get_ports DBB_RX_P[1]] +set_property PACKAGE_PIN AB5 [get_ports DBB_RX_N[1]] +set_property PACKAGE_PIN Y6 [get_ports DBB_RX_P[2]] +set_property PACKAGE_PIN Y5 [get_ports DBB_RX_N[2]] +set_property PACKAGE_PIN AA4 [get_ports DBB_RX_P[3]] +set_property PACKAGE_PIN AA3 [get_ports DBB_RX_N[3]] + +set_property PACKAGE_PIN AB2 [get_ports DBB_TX_P[0]] +set_property PACKAGE_PIN AB1 [get_ports DBB_TX_N[0]] +set_property PACKAGE_PIN Y2 [get_ports DBB_TX_P[1]] +set_property PACKAGE_PIN Y1 [get_ports DBB_TX_N[1]] +set_property PACKAGE_PIN W4 [get_ports DBB_TX_P[2]] +set_property PACKAGE_PIN W3 [get_ports DBB_TX_N[2]] +set_property PACKAGE_PIN V2 [get_ports DBB_TX_P[3]] +set_property PACKAGE_PIN V1 [get_ports DBB_TX_N[3]] + +set_property PACKAGE_PIN AK17 [get_ports DBB_LED_RX] +set_property PACKAGE_PIN AK18 [get_ports DBB_LED_RX2] +set_property PACKAGE_PIN AK21 [get_ports DBB_LED_TX] + +# Possibly need to be used. Connected to CPLD. +# set_property PACKAGE_PIN G6 [get_ports DBB_CPLD_UNUSED[0]] +# set_property PACKAGE_PIN H6 [get_ports DBB_CPLD_UNUSED[1]] +# set_property PACKAGE_PIN L3 [get_ports DBB_CPLD_UNUSED[2]] +# set_property PACKAGE_PIN L2 [get_ports DBB_CPLD_UNUSED[3]] +# set_property PACKAGE_PIN D4 [get_ports DBB_CPLD_UNUSED[4]] +# set_property PACKAGE_PIN AC22 [get_ports DBB_CPLD_UNUSED[5]] +# set_property PACKAGE_PIN AC23 [get_ports DBB_CPLD_UNUSED[6]] +# set_property PACKAGE_PIN AC24 [get_ports DBB_CPLD_UNUSED[7]] +# set_property PACKAGE_PIN AD24 [get_ports DBB_CPLD_UNUSED[8]] +# set_property PACKAGE_PIN AE22 [get_ports DBB_CPLD_UNUSED[9]] +# set_property PACKAGE_PIN AK20 [get_ports DBB_CPLD_UNUSED[10]] +# set_property PACKAGE_PIN AJ20 [get_ports DBB_CPLD_UNUSED[11]] + +set UsrpIoBHpPinsSe [get_ports {DBB_MODULE_PWR_ENABLE \ + DBB_RF_PWR_ENABLE \ + DBB_CPLD_PL_SPI_* \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B \ + DBB_CLKDIST_SYNC \ + DBB_TXRX_SW_CTRL_* \ + DBB_ATR_*}] +set_property IOSTANDARD LVCMOS18 $UsrpIoBHpPinsSe +set_property DRIVE 6 $UsrpIoBHpPinsSe +set_property SLEW SLOW $UsrpIoBHpPinsSe + +set UsrpIoBHrPinsSeDr4 [get_ports {DBB_LED_* \ + DBB_CPLD_JTAG_*}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr4 +set_property DRIVE 4 $UsrpIoBHrPinsSeDr4 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr4 + +set UsrpIoBHrPinsSeDr8 [get_ports {DBB_CPLD_PS_SPI_* \ + DBB_PHDAC_SPI_CS_B \ + DBB_CLKDIS_SPI_CS_B \ + DBB_ADC_SPI_CS_B \ + DBB_DAC_SPI_CS_B}] +set_property IOSTANDARD LVCMOS25 $UsrpIoBHrPinsSeDr8 +set_property DRIVE 8 $UsrpIoBHrPinsSeDr8 +set_property SLEW SLOW $UsrpIoBHrPinsSeDr8 + +set UsrpIoBHrPinsDiff [get_ports {DBB_ADC_SYNCB_* \ + DBB_DAC_SYNCB_* \ + DBB_FPGA_CLK_* \ + DBB_FPGA_SYSREF_*}] +set_property IOSTANDARD LVDS_25 $UsrpIoBHrPinsDiff +set_property DIFF_TERM TRUE $UsrpIoBHrPinsDiff diff --git a/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc new file mode 100644 index 000000000..cffbd839a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/db_timing.xdc @@ -0,0 +1,264 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx". +# See this spreadsheet for more details and explanations. + +#******************************************************************************* +## Asynchronous clock groups + +# MGT reference clocks are also async to everything. +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dba -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks mgt_clk_dbb -include_generated_clocks] + +# fpga_clk_a and fpga_clk_b are related to one another after synchronization. +# However, we do need to declare that these clocks (both a and b) and their children +# are async to the remainder of the design. Use the wildcard at the end to grab the +# virtual clock as well as the real ones. +set_clock_groups -asynchronous -group [get_clocks {fpga_clk_a* fpga_clk_b*} -include_generated_clocks] + +# The SPI readback and write clocks cannot be active at the same time, as they +# originate from the same pin. +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_a] \ + -group [get_clocks pl_spi_clk_a] +set_clock_groups -physically_exclusive \ + -group [get_clocks pl_spi_rb_clk_b] \ + -group [get_clocks pl_spi_clk_b] + +#******************************************************************************* +## PS SPI: since these lines all come from the PS and I don't have access to the +# driving clock (or anything for that matter), I'm left with constraining the maximum +# and minimum delay on these lines, per a Xilinx AR: +# https://www.xilinx.com/support/answers/62122.html +set CPLD_SPI_OUTS [get_ports {DB*_CPLD_PS_SPI_SCLK \ + DB*_CPLD_PS_SPI_MOSI \ + DB*_CPLD_PS_SPI_CS_B \ + DB*_CLKDIS_SPI_CS_B \ + DB*_PHDAC_SPI_CS_B \ + DB*_ADC_SPI_CS_B \ + DB*_DAC_SPI_CS_B}] + +# The actual min and max path delays before applying constraints were (from report_timing): +# 3.332 ns (Min at Fast Process Corner) +# 10.596 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +# After implementation, the tools were unable to meet timing when leaving a 11 ns max +# delay value, so it was incremented. +set MIN_OUT_DELAY 3.0 +set MAX_OUT_DELAY 12.0 + +set_max_delay $MAX_OUT_DELAY -to $CPLD_SPI_OUTS +set_min_delay $MIN_OUT_DELAY -to $CPLD_SPI_OUTS + +# report_timing -to $CPLD_SPI_OUTS -max_paths 20 -delay_type min_max -name CpldSpiOutTiming + +# The actual min and max path delays before applying constraints were (from report_timing): +# 2.733 ns (Min at Fast Process Corner) +# 6.071 ns (Max at Slow Process Corner) +# Therefore, we round those number to their immediate succesor respectively. +set MIN_IN_DELAY 2.0 +set MAX_IN_DELAY 10.0 + +set PS_SPI_INPUTS_0 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI0MI"}] +set PS_SPI_INPUTS_1 [get_pins -hierarchical -filter {NAME =~ "*/PS7_i/EMIOSPI1MI"}] + +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_0 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_0 +set_max_delay $MAX_IN_DELAY -to $PS_SPI_INPUTS_1 +set_min_delay $MIN_IN_DELAY -to $PS_SPI_INPUTS_1 + +# report_timing -to $PS_SPI_INPUTS_0 -max_paths 30 -delay_type min_max -nworst 30 -name Spi0InTiming +# report_timing -to $PS_SPI_INPUTS_1 -max_paths 30 -delay_type min_max -nworst 30 -name Spi1InTiming + + + +#******************************************************************************* +## PL SPI to the CPLD +# +# All of these lines are driven or received from flops in simple_spi_core. The CPLD +# calculations assume the FPGA has less than 6 ns of skew between the SCK and +# SDI/CS_n. Pretty easy constraint to write! See above for the clock definition. +# Do this for DBA and DBB independently. +set MAX_SKEW 6.0 +set SETUP_SKEW [expr {$MAX_SKEW / 2}] +set HOLD_SKEW [expr {$MAX_SKEW / 2}] +# Do not set the output delay constraint on the clock line! +set PORT_LIST_A [get_ports {DBA_CPLD_PL_SPI_CS_B \ + DBA_CPLD_PL_SPI_MOSI \ + DBA_TXLO_SPI_CS_B \ + DBA_RXLO_SPI_CS_B \ + DBA_LODIS_SPI_CS_B }] +set PORT_LIST_B [get_ports {DBB_CPLD_PL_SPI_CS_B \ + DBB_CPLD_PL_SPI_MOSI \ + DBB_TXLO_SPI_CS_B \ + DBB_RXLO_SPI_CS_B \ + DBB_LODIS_SPI_CS_B }] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -max -$SETUP_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_a] -min $HOLD_SKEW $PORT_LIST_A +set_output_delay -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -max -$SETUP_SKEW $PORT_LIST_B +set_output_delay -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +set_output_delay -add_delay -clock_fall -clock [get_clocks pl_spi_clk_b] -min $HOLD_SKEW $PORT_LIST_B +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_a] -1 +set_multicycle_path -setup -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -start 0 +set_multicycle_path -hold -from [get_clocks radio_clk] -to [get_clocks pl_spi_clk_b] -1 + +# For SDO input timing (MISO), we need to look at the CPLD's constraints on turnaround +# time plus any board propagation delay. +# CPLD clk-to-q is 20 ns, then add 1.2 ns for board delay (once for clock, once for data) +# For hold time, assume zero delay (likely overconstraining here, due to board delays) +set MISO_INPUT_A [get_ports DBA_CPLD_PL_SPI_MISO] +set MISO_INPUT_B [get_ports DBB_CPLD_PL_SPI_MISO] +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -max 22.400 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_a] -clock_fall -min 0.000 $MISO_INPUT_A +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -max 22.400 $MISO_INPUT_B +set_input_delay -clock [get_clocks pl_spi_rb_clk_b] -clock_fall -min 0.000 $MISO_INPUT_B + +# Since the input delay span is clearly more than a period of the radio_clk, we need to +# add a multicycle path here as well to define the clock divider ratio. The MISO data +# is driven on the falling edge of the SPI clock and captured on the rising edge, so we +# only have one half of a SPI clock cycle for our setup. Hold is left alone and is OK +# as-is due to the delays in the CPLD and board. +set SETUP_CYCLES [expr {$PL_SPI_RB_DIVIDE_VAL / 2}] +set HOLD_CYCLES 0 +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_a] -through $MISO_INPUT_A -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] +set_multicycle_path -setup -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B \ + $SETUP_CYCLES +set_multicycle_path -hold -from [get_clocks pl_spi_rb_clk_b] -through $MISO_INPUT_B -end \ + [expr {$SETUP_CYCLES + $HOLD_CYCLES - 1}] + +#******************************************************************************* +## SYSREF/SYNC JESD Timing +# +# SYNC is async, SYSREF is tightly timed. + +# The SYNC output (to ADC) for both DBs is governed by the JESD cores, which are solely +# driven by DB-A clock... but it is an asynchronous signal so we use the async_out_clk. +set_output_delay -clock [get_clocks async_out_clk] 0.000 [get_ports DB*_ADC_SYNCB_P] +set_max_delay -to [get_ports DB*_ADC_SYNCB_P] 50.000 +set_min_delay -to [get_ports DB*_ADC_SYNCB_P] 0.000 + +# The SYNC input (from DAC) for both DBs is received by the DB-A clock inside the JESD +# cores... but again, it is asynchronous and therefore uses the async_in_clk. +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports DB*_DAC_SYNCB_P] +set_max_delay -from [get_ports DB*_DAC_SYNCB_P] 50.000 +set_min_delay -from [get_ports DB*_DAC_SYNCB_P] 0.000 + +# SYSREF is driven by the LMK directly to the FPGA. Timing analysis was performed once +# for the worst-case numbers across both DBs to produce one set of numbers for both DBs. +# Since we easily meet setup and hold in Vivado, then this is an acceptable approach. +# SYSREF is captured by the local clock from each DB, so we have two sets of constraints. +set_input_delay -clock fpga_clk_a_v -min -0.479 [get_ports DBA_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_a_v -max 0.661 [get_ports DBA_FPGA_SYSREF_*] + +set_input_delay -clock fpga_clk_b_v -min -0.479 [get_ports DBB_FPGA_SYSREF_*] +set_input_delay -clock fpga_clk_b_v -max 0.661 [get_ports DBB_FPGA_SYSREF_*] + + +#******************************************************************************* +## PPS Timing + +# Due to the N3xx synchronization and clocking structure, the PPS output is driven from +# the Sample Clock domain instead of the input Reference Clock. Constrain the output as +# tightly as possible to accurately mimic the internal Sample Clock timing. +set SETUP_SKEW 2.0 +set HOLD_SKEW -0.5 +set_output_delay -clock [get_clocks fpga_clk_a_v] -max -$SETUP_SKEW [get_ports REF_1PPS_OUT] +set_output_delay -clock [get_clocks fpga_clk_a_v] -min $HOLD_SKEW [get_ports REF_1PPS_OUT] +set_multicycle_path -setup -to [get_ports REF_1PPS_OUT] -start 0 +set_multicycle_path -hold -to [get_ports REF_1PPS_OUT] -1 + +#******************************************************************************* +### Async I/Os +set DB_ASYNC_OUTPUTS [get_ports { + DB*_MODULE_PWR_ENABLE + DB*_RF_PWR_ENABLE + DB*_CLKDIST_SYNC + DB*_ATR_TX + DB*_ATR_RX + DB*_TXRX_SW_CTRL_1 + DB*_TXRX_SW_CTRL_2 + DB*_LED_RX + DB*_LED_RX2 + DB*_LED_TX + QSFP_I2C_* +}] +set_output_delay -clock [get_clocks async_out_clk] 0.000 $DB_ASYNC_OUTPUTS +set_max_delay -to $DB_ASYNC_OUTPUTS 50.000 +set_min_delay -to $DB_ASYNC_OUTPUTS 0.000 + +set_input_delay -clock [get_clocks async_in_clk] 0.000 [get_ports QSFP_I2C_*] +set_max_delay -from [get_ports QSFP_I2C_*] 50.000 +set_min_delay -from [get_ports QSFP_I2C_*] 0.000 + +#******************************************************************************* +## JTAG + +## MAX 10 JTAG TDI setup: 2 ns +## MAX 10 JTAG TMS setup: 3 ns +## MAX 10 JTAG hold: 10 ns +## MAX 10 JTAG clk-to-q: 18 ns +## Board delay: < 1.5 ns +## +## Setup time = Board delay + TMS setup = 3 ns + 1.5 ns = 4.5 ns +## Hold time = Board delay + TMS hold = 1.5 ns + 10 ns = 11.5 ns +## Overconstrain output delay and keep skew to +/- 8 ns +## +## Input delay = 2x Board delay + clk-to-q = 3 ns + 18 ns = 21 ns + +# Constrain outputs for skew, with same latch/launch edge: +set_output_delay -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -max -4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dba_jtag_tck] -min 4.0 \ + [get_ports {DBA_CPLD_JTAG_TDI DBA_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -max -4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +set_output_delay -add_delay -clock_fall -clock [get_clocks dbb_jtag_tck] -min 4.0 \ + [get_ports {DBB_CPLD_JTAG_TDI DBB_CPLD_JTAG_TMS}] +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dba_jtag_tck] -1 +set_multicycle_path -setup -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -start 0 +set_multicycle_path -hold -from [get_clocks clk40] -to [get_clocks dbb_jtag_tck] -1 + +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -max 21 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dba_jtag_tck] -clock_fall -min 0 \ + [get_ports DBA_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -max 21 \ + [get_ports DBB_CPLD_JTAG_TDO] +set_input_delay -clock [get_clocks dbb_jtag_tck] -clock_fall -min 0 \ + [get_ports DBB_CPLD_JTAG_TDO] +# Inputs have setup checks relative to half a period of TCK (launch on fall, +# latch on rise). Actual latch clock is faster, so push back setup and hold +# checks to match. +set_multicycle_path -setup -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dba_jtag_tck] \ + -through [get_ports DBA_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] +set_multicycle_path -setup -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR / 2}] +set_multicycle_path -end -hold -from [get_clocks dbb_jtag_tck] \ + -through [get_ports DBB_CPLD_JTAG_TDO] \ + [expr {$DB_JTAG_DIVISOR - 1}] diff --git a/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx new file mode 100755 index 000000000..7782ee33c Binary files /dev/null and b/fpga/usrp3/top/n3xx/dboards/rh/doc/rh_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v new file mode 100644 index 000000000..e697f00d4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dboards/rh/n3xx.v @@ -0,0 +1,3855 @@ +/////////////////////////////////////////////////////////////////// +/// +// Copyright 2018-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx +// Description: +// Top Level for N320, N321 devices +// +////////////////////////////////////////////////////////////////////// + +module n3xx ( + inout [11:0] FPGA_GPIO, + + input FPGA_REFCLK_P, + input FPGA_REFCLK_N, + input REF_1PPS_IN, + input NETCLK_REF_P, + input NETCLK_REF_N, + //input REF_1PPS_IN_MGMT, + output REF_1PPS_OUT, + + //TDC + inout UNUSED_PIN_TDCA_0, + inout UNUSED_PIN_TDCA_1, + inout UNUSED_PIN_TDCA_2, + inout UNUSED_PIN_TDCA_3, + inout UNUSED_PIN_TDCB_0, + inout UNUSED_PIN_TDCB_1, + inout UNUSED_PIN_TDCB_2, + inout UNUSED_PIN_TDCB_3, + +`ifdef NPIO_LANES + input NPIO_RX0_P, + input NPIO_RX0_N, + output NPIO_TX0_P, + output NPIO_TX0_N, + input NPIO_RX1_P, + input NPIO_RX1_N, + output NPIO_TX1_P, + output NPIO_TX1_N, +`endif +`ifdef QSFP_LANES + input [`QSFP_LANES-1:0] QSFP_RX_P, + input [`QSFP_LANES-1:0] QSFP_RX_N, + output [`QSFP_LANES-1:0] QSFP_TX_P, + output [`QSFP_LANES-1:0] QSFP_TX_N, + output QSFP_RESET_B, + output QSFP_LED, + output QSFP_MODSEL_B, + output QSFP_LPMODE, + input QSFP_PRESENT_B, + input QSFP_INT_B, + inout QSFP_I2C_SCL, + inout QSFP_I2C_SDA, +`endif + //TODO: Uncomment when connected here + //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, + //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, + //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, + //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, + //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, + //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, + //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, + //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, + //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, + //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, + //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, + //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, + + //GPS + input GPS_1PPS, + //input GPS_1PPS_RAW, + + //Misc + input ENET0_CLK125, + //inout ENET0_PTP, + //output ENET0_PTP_DIR, + //inout ATSHA204_SDA, + input FPGA_PL_RESETN, // TODO: Add to reset logic + // output reg [1:0] FPGA_TEST, + //input PWR_CLK_FPGA, // TODO: check direction + input FPGA_PUDC_B, + + //White Rabbit + input WB_20MHZ_P, + input WB_20MHZ_N, + output WB_DAC_DIN, + output WB_DAC_NCLR, + output WB_DAC_NLDAC, + output WB_DAC_NSYNC, + output WB_DAC_SCLK, + + //LEDS + output PANEL_LED_GPS, + output PANEL_LED_LINK, + output PANEL_LED_PPS, + output PANEL_LED_REF, + + // ARM Connections (PS) + inout [53:0] MIO, + inout PS_SRSTB, + inout PS_CLK, + inout PS_PORB, + inout DDR_Clk, + inout DDR_Clk_n, + inout DDR_CKE, + inout DDR_CS_n, + inout DDR_RAS_n, + inout DDR_CAS_n, + inout DDR_WEB, + inout [2:0] DDR_BankAddr, + inout [14:0] DDR_Addr, + inout DDR_ODT, + inout DDR_DRSTB, + inout [31:0] DDR_DQ, + inout [3:0] DDR_DM, + inout [3:0] DDR_DQS, + inout [3:0] DDR_DQS_n, + inout DDR_VRP, + inout DDR_VRN, + + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + + // These clock inputs must always be enabled with a buffer regardless of the build + // target to avoid damage to the FPGA. + input NETCLK_P, + input NETCLK_N, + input MGT156MHZ_CLK1_P, + input MGT156MHZ_CLK1_N, + + input SFP_0_RX_P, input SFP_0_RX_N, + output SFP_0_TX_P, output SFP_0_TX_N, + input SFP_1_RX_P, input SFP_1_RX_N, + output SFP_1_TX_P, output SFP_1_TX_N, + + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [15:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_p, // Differential + input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. + + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + //SFP+ 0, Slow Speed, Bank 13 3.3V + input SFP_0_I2C_NPRESENT, + output SFP_0_LED_A, + output SFP_0_LED_B, + input SFP_0_LOS, + output SFP_0_RS0, + output SFP_0_RS1, + output SFP_0_TXDISABLE, + input SFP_0_TXFAULT, + + //SFP+ 1, Slow Speed, Bank 13 3.3V + //input SFP_1_I2C_NPRESENT, + output SFP_1_LED_A, + output SFP_1_LED_B, + input SFP_1_LOS, + output SFP_1_RS0, + output SFP_1_RS1, + output SFP_1_TXDISABLE, + input SFP_1_TXFAULT, + + //USRP IO A + output DBA_MODULE_PWR_ENABLE, + output DBA_RF_PWR_ENABLE, + + output DBA_CPLD_PS_SPI_SCLK, + output DBA_CLKDIS_SPI_CS_B, + output DBA_CPLD_PS_SPI_CS_B, + output DBA_PHDAC_SPI_CS_B, + output DBA_CPLD_PS_SPI_MOSI, + input DBA_CPLD_PS_SPI_MISO, + + output DBA_ATR_RX, + output DBA_ATR_TX, + output DBA_TXRX_SW_CTRL_1, + output DBA_TXRX_SW_CTRL_2, + + output DBA_CPLD_PL_SPI_SCLK, + output DBA_ADC_SPI_CS_B, + output DBA_DAC_SPI_CS_B, + output DBA_TXLO_SPI_CS_B, + output DBA_RXLO_SPI_CS_B, + output DBA_LODIS_SPI_CS_B, + output DBA_CPLD_PL_SPI_CS_B, + output DBA_CPLD_PL_SPI_MOSI, + input DBA_CPLD_PL_SPI_MISO, + + output DBA_ADC_SYNCB_P, + output DBA_ADC_SYNCB_N, + input DBA_DAC_SYNCB_P, + input DBA_DAC_SYNCB_N, + + output DBA_CLKDIST_SYNC, + + inout DBA_CPLD_JTAG_TCK, + inout DBA_CPLD_JTAG_TMS, + inout DBA_CPLD_JTAG_TDI, + input DBA_CPLD_JTAG_TDO, + + input DBA_FPGA_CLK_P, + input DBA_FPGA_CLK_N, + + input DBA_FPGA_SYSREF_P, + input DBA_FPGA_SYSREF_N, + + input DBA_MGTCLK_P, + input DBA_MGTCLK_N, + + input [3:0] DBA_RX_P, + input [3:0] DBA_RX_N, + output [3:0] DBA_TX_P, + output [3:0] DBA_TX_N, + + output DBA_LED_RX, + output DBA_LED_RX2, + output DBA_LED_TX, + + //USRP IO B + output DBB_MODULE_PWR_ENABLE, + output DBB_RF_PWR_ENABLE, + + output DBB_CPLD_PS_SPI_SCLK, + output DBB_CLKDIS_SPI_CS_B, + output DBB_CPLD_PS_SPI_CS_B, + output DBB_PHDAC_SPI_CS_B, + output DBB_CPLD_PS_SPI_MOSI, + input DBB_CPLD_PS_SPI_MISO, + + output DBB_ATR_RX, + output DBB_ATR_TX, + output DBB_TXRX_SW_CTRL_1, + output DBB_TXRX_SW_CTRL_2, + + output DBB_CPLD_PL_SPI_SCLK, + output DBB_ADC_SPI_CS_B, + output DBB_DAC_SPI_CS_B, + output DBB_TXLO_SPI_CS_B, + output DBB_RXLO_SPI_CS_B, + output DBB_LODIS_SPI_CS_B, + output DBB_CPLD_PL_SPI_CS_B, + output DBB_CPLD_PL_SPI_MOSI, + input DBB_CPLD_PL_SPI_MISO, + + output DBB_ADC_SYNCB_P, + output DBB_ADC_SYNCB_N, + input DBB_DAC_SYNCB_P, + input DBB_DAC_SYNCB_N, + + output DBB_CLKDIST_SYNC, + + inout DBB_CPLD_JTAG_TCK, + inout DBB_CPLD_JTAG_TMS, + inout DBB_CPLD_JTAG_TDI, + input DBB_CPLD_JTAG_TDO, + + input DBB_FPGA_CLK_P, + input DBB_FPGA_CLK_N, + + input DBB_FPGA_SYSREF_P, + input DBB_FPGA_SYSREF_N, + + input DBB_MGTCLK_P, + input DBB_MGTCLK_N, + + input [3:0] DBB_RX_P, + input [3:0] DBB_RX_N, + output [3:0] DBB_TX_P, + output [3:0] DBB_TX_N, + + output DBB_LED_RX, + output DBB_LED_RX2, + output DBB_LED_TX +); + + localparam N_AXILITE_SLAVES = 4; + localparam REG_AWIDTH = 14; // log2(0x4000) + localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) + localparam REG_DWIDTH = 32; + localparam FP_GPIO_OFFSET = 32; + localparam FP_GPIO_WIDTH = 12; + + localparam NUM_RADIOS = 2; + localparam NUM_CHANNELS_PER_RADIO = 1; + localparam NUM_DBOARDS = 2; + localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; + localparam CHANNEL_WIDTH = 32; + + + // Internal connections to PS + // HP0 -- High Performance port 0, FPGA is the master + wire [5:0] S_AXI_HP0_AWID; + wire [31:0] S_AXI_HP0_AWADDR; + wire [2:0] S_AXI_HP0_AWPROT; + wire S_AXI_HP0_AWVALID; + wire S_AXI_HP0_AWREADY; + wire [63:0] S_AXI_HP0_WDATA; + wire [7:0] S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP0_WREADY; + wire [1:0] S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire S_AXI_HP0_BREADY; + wire [5:0] S_AXI_HP0_ARID; + wire [31:0] S_AXI_HP0_ARADDR; + wire [2:0] S_AXI_HP0_ARPROT; + wire S_AXI_HP0_ARVALID; + wire S_AXI_HP0_ARREADY; + wire [63:0] S_AXI_HP0_RDATA; + wire [1:0] S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire S_AXI_HP0_RREADY; + wire S_AXI_HP0_RLAST; + wire [3:0] S_AXI_HP0_ARCACHE; + wire [7:0] S_AXI_HP0_AWLEN; + wire [2:0] S_AXI_HP0_AWSIZE; + wire [1:0] S_AXI_HP0_AWBURST; + wire [3:0] S_AXI_HP0_AWCACHE; + wire S_AXI_HP0_WLAST; + wire [7:0] S_AXI_HP0_ARLEN; + wire [1:0] S_AXI_HP0_ARBURST; + wire [2:0] S_AXI_HP0_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the master + wire [4:0] S_AXI_GP0_AWID; + wire [31:0] S_AXI_GP0_AWADDR; + wire [2:0] S_AXI_GP0_AWPROT; + wire S_AXI_GP0_AWVALID; + wire S_AXI_GP0_AWREADY; + wire [31:0] S_AXI_GP0_WDATA; + wire [3:0] S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP0_WREADY; + wire [1:0] S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire S_AXI_GP0_BREADY; + wire [4:0] S_AXI_GP0_ARID; + wire [31:0] S_AXI_GP0_ARADDR; + wire [2:0] S_AXI_GP0_ARPROT; + wire S_AXI_GP0_ARVALID; + wire S_AXI_GP0_ARREADY; + wire [31:0] S_AXI_GP0_RDATA; + wire [1:0] S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire S_AXI_GP0_RREADY; + wire S_AXI_GP0_RLAST; + wire [3:0] S_AXI_GP0_ARCACHE; + wire [7:0] S_AXI_GP0_AWLEN; + wire [2:0] S_AXI_GP0_AWSIZE; + wire [1:0] S_AXI_GP0_AWBURST; + wire [3:0] S_AXI_GP0_AWCACHE; + wire S_AXI_GP0_WLAST; + wire [7:0] S_AXI_GP0_ARLEN; + wire [1:0] S_AXI_GP0_ARBURST; + wire [2:0] S_AXI_GP0_ARSIZE; + + // HP1 -- High Performance port 1, FPGA is the master + wire [5:0] S_AXI_HP1_AWID; + wire [31:0] S_AXI_HP1_AWADDR; + wire [2:0] S_AXI_HP1_AWPROT; + wire S_AXI_HP1_AWVALID; + wire S_AXI_HP1_AWREADY; + wire [63:0] S_AXI_HP1_WDATA; + wire [7:0] S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP1_WREADY; + wire [1:0] S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire S_AXI_HP1_BREADY; + wire [5:0] S_AXI_HP1_ARID; + wire [31:0] S_AXI_HP1_ARADDR; + wire [2:0] S_AXI_HP1_ARPROT; + wire S_AXI_HP1_ARVALID; + wire S_AXI_HP1_ARREADY; + wire [63:0] S_AXI_HP1_RDATA; + wire [1:0] S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire S_AXI_HP1_RREADY; + wire S_AXI_HP1_RLAST; + wire [3:0] S_AXI_HP1_ARCACHE; + wire [7:0] S_AXI_HP1_AWLEN; + wire [2:0] S_AXI_HP1_AWSIZE; + wire [1:0] S_AXI_HP1_AWBURST; + wire [3:0] S_AXI_HP1_AWCACHE; + wire S_AXI_HP1_WLAST; + wire [7:0] S_AXI_HP1_ARLEN; + wire [1:0] S_AXI_HP1_ARBURST; + wire [2:0] S_AXI_HP1_ARSIZE; + + // GP1 -- General Purpose port 1, FPGA is the master + wire [4:0] S_AXI_GP1_AWID; + wire [31:0] S_AXI_GP1_AWADDR; + wire [2:0] S_AXI_GP1_AWPROT; + wire S_AXI_GP1_AWVALID; + wire S_AXI_GP1_AWREADY; + wire [31:0] S_AXI_GP1_WDATA; + wire [3:0] S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_GP1_WREADY; + wire [1:0] S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire S_AXI_GP1_BREADY; + wire [4:0] S_AXI_GP1_ARID; + wire [31:0] S_AXI_GP1_ARADDR; + wire [2:0] S_AXI_GP1_ARPROT; + wire S_AXI_GP1_ARVALID; + wire S_AXI_GP1_ARREADY; + wire [31:0] S_AXI_GP1_RDATA; + wire [1:0] S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire S_AXI_GP1_RREADY; + wire S_AXI_GP1_RLAST; + wire [3:0] S_AXI_GP1_ARCACHE; + wire [7:0] S_AXI_GP1_AWLEN; + wire [2:0] S_AXI_GP1_AWSIZE; + wire [1:0] S_AXI_GP1_AWBURST; + wire [3:0] S_AXI_GP1_AWCACHE; + wire S_AXI_GP1_WLAST; + wire [7:0] S_AXI_GP1_ARLEN; + wire [1:0] S_AXI_GP1_ARBURST; + wire [2:0] S_AXI_GP1_ARSIZE; + + // GP0 -- General Purpose port 0, FPGA is the slave + wire M_AXI_GP0_ARVALID; + wire M_AXI_GP0_AWVALID; + wire M_AXI_GP0_BREADY; + wire M_AXI_GP0_RREADY; + wire M_AXI_GP0_WVALID; + wire [11:0] M_AXI_GP0_ARID; + wire [11:0] M_AXI_GP0_AWID; + wire [11:0] M_AXI_GP0_WID; + wire [31:0] M_AXI_GP0_ARADDR; + wire [31:0] M_AXI_GP0_AWADDR; + wire [31:0] M_AXI_GP0_WDATA; + wire [3:0] M_AXI_GP0_WSTRB; + wire M_AXI_GP0_ARREADY; + wire M_AXI_GP0_AWREADY; + wire M_AXI_GP0_BVALID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RVALID; + wire M_AXI_GP0_WREADY; + wire [1:0] M_AXI_GP0_BRESP; + wire [1:0] M_AXI_GP0_RRESP; + wire [31:0] M_AXI_GP0_RDATA; + + wire M_AXI_ETH_DMA0_ARVALID; + wire M_AXI_ETH_DMA0_AWVALID; + wire M_AXI_ETH_DMA0_BREADY; + wire M_AXI_ETH_DMA0_RREADY; + wire M_AXI_ETH_DMA0_WVALID; + wire [11:0] M_AXI_ETH_DMA0_ARID; + wire [11:0] M_AXI_ETH_DMA0_AWID; + wire [11:0] M_AXI_ETH_DMA0_WID; + wire [31:0] M_AXI_ETH_DMA0_ARADDR; + wire [31:0] M_AXI_ETH_DMA0_AWADDR; + wire [31:0] M_AXI_ETH_DMA0_WDATA; + wire [3:0] M_AXI_ETH_DMA0_WSTRB; + wire M_AXI_ETH_DMA0_ARREADY; + wire M_AXI_ETH_DMA0_AWREADY; + wire M_AXI_ETH_DMA0_BVALID; + wire M_AXI_ETH_DMA0_RLAST; + wire M_AXI_ETH_DMA0_RVALID; + wire M_AXI_ETH_DMA0_WREADY; + wire [1:0] M_AXI_ETH_DMA0_BRESP; + wire [1:0] M_AXI_ETH_DMA0_RRESP; + wire [31:0] M_AXI_ETH_DMA0_RDATA; + + wire M_AXI_NET0_ARVALID; + wire M_AXI_NET0_AWVALID; + wire M_AXI_NET0_BREADY; + wire M_AXI_NET0_RREADY; + wire M_AXI_NET0_WVALID; + wire [11:0] M_AXI_NET0_ARID; + wire [11:0] M_AXI_NET0_AWID; + wire [11:0] M_AXI_NET0_WID; + wire [31:0] M_AXI_NET0_ARADDR; + wire [31:0] M_AXI_NET0_AWADDR; + wire [31:0] M_AXI_NET0_WDATA; + wire [3:0] M_AXI_NET0_WSTRB; + wire M_AXI_NET0_ARREADY; + wire M_AXI_NET0_AWREADY; + wire M_AXI_NET0_BVALID; + wire M_AXI_NET0_RLAST; + wire M_AXI_NET0_RVALID; + wire M_AXI_NET0_WREADY; + wire [1:0] M_AXI_NET0_BRESP; + wire [1:0] M_AXI_NET0_RRESP; + wire [31:0] M_AXI_NET0_RDATA; + + wire M_AXI_ETH_DMA1_ARVALID; + wire M_AXI_ETH_DMA1_AWVALID; + wire M_AXI_ETH_DMA1_BREADY; + wire M_AXI_ETH_DMA1_RREADY; + wire M_AXI_ETH_DMA1_WVALID; + wire [11:0] M_AXI_ETH_DMA1_ARID; + wire [11:0] M_AXI_ETH_DMA1_AWID; + wire [11:0] M_AXI_ETH_DMA1_WID; + wire [31:0] M_AXI_ETH_DMA1_ARADDR; + wire [31:0] M_AXI_ETH_DMA1_AWADDR; + wire [31:0] M_AXI_ETH_DMA1_WDATA; + wire [3:0] M_AXI_ETH_DMA1_WSTRB; + wire M_AXI_ETH_DMA1_ARREADY; + wire M_AXI_ETH_DMA1_AWREADY; + wire M_AXI_ETH_DMA1_BVALID; + wire M_AXI_ETH_DMA1_RLAST; + wire M_AXI_ETH_DMA1_RVALID; + wire M_AXI_ETH_DMA1_WREADY; + wire [1:0] M_AXI_ETH_DMA1_BRESP; + wire [1:0] M_AXI_ETH_DMA1_RRESP; + wire [31:0] M_AXI_ETH_DMA1_RDATA; + + wire M_AXI_NET1_ARVALID; + wire M_AXI_NET1_AWVALID; + wire M_AXI_NET1_BREADY; + wire M_AXI_NET1_RREADY; + wire M_AXI_NET1_WVALID; + wire [11:0] M_AXI_NET1_ARID; + wire [11:0] M_AXI_NET1_AWID; + wire [11:0] M_AXI_NET1_WID; + wire [31:0] M_AXI_NET1_ARADDR; + wire [31:0] M_AXI_NET1_AWADDR; + wire [31:0] M_AXI_NET1_WDATA; + wire [3:0] M_AXI_NET1_WSTRB; + wire M_AXI_NET1_ARREADY; + wire M_AXI_NET1_AWREADY; + wire M_AXI_NET1_BVALID; + wire M_AXI_NET1_RLAST; + wire M_AXI_NET1_RVALID; + wire M_AXI_NET1_WREADY; + wire [1:0] M_AXI_NET1_BRESP; + wire [1:0] M_AXI_NET1_RRESP; + wire [31:0] M_AXI_NET1_RDATA; + + wire M_AXI_NET2_ARVALID; + wire M_AXI_NET2_AWVALID; + wire M_AXI_NET2_BREADY; + wire M_AXI_NET2_RREADY; + wire M_AXI_NET2_WVALID; + wire [11:0] M_AXI_NET2_ARID; + wire [11:0] M_AXI_NET2_AWID; + wire [11:0] M_AXI_NET2_WID; + wire [31:0] M_AXI_NET2_ARADDR; + wire [31:0] M_AXI_NET2_AWADDR; + wire [31:0] M_AXI_NET2_WDATA; + wire [3:0] M_AXI_NET2_WSTRB; + wire M_AXI_NET2_ARREADY; + wire M_AXI_NET2_AWREADY; + wire M_AXI_NET2_BVALID; + wire M_AXI_NET2_RLAST; + wire M_AXI_NET2_RVALID; + wire M_AXI_NET2_WREADY; + wire [1:0] M_AXI_NET2_BRESP; + wire [1:0] M_AXI_NET2_RRESP; + wire [31:0] M_AXI_NET2_RDATA; + + wire M_AXI_XBAR_ARVALID; + wire M_AXI_XBAR_AWVALID; + wire M_AXI_XBAR_BREADY; + wire M_AXI_XBAR_RREADY; + wire M_AXI_XBAR_WVALID; + wire [11:0] M_AXI_XBAR_ARID; + wire [11:0] M_AXI_XBAR_AWID; + wire [11:0] M_AXI_XBAR_WID; + wire [31:0] M_AXI_XBAR_ARADDR; + wire [31:0] M_AXI_XBAR_AWADDR; + wire [31:0] M_AXI_XBAR_WDATA; + wire [3:0] M_AXI_XBAR_WSTRB; + wire M_AXI_XBAR_ARREADY; + wire M_AXI_XBAR_AWREADY; + wire M_AXI_XBAR_BVALID; + wire M_AXI_XBAR_RLAST; + wire M_AXI_XBAR_RVALID; + wire M_AXI_XBAR_WREADY; + wire [1:0] M_AXI_XBAR_BRESP; + wire [1:0] M_AXI_XBAR_RRESP; + wire [31:0] M_AXI_XBAR_RDATA; + + wire M_AXI_JESD0_ARVALID; + wire M_AXI_JESD0_AWVALID; + wire M_AXI_JESD0_BREADY; + wire M_AXI_JESD0_RREADY; + wire M_AXI_JESD0_WVALID; + wire [11:0] M_AXI_JESD0_ARID; + wire [11:0] M_AXI_JESD0_AWID; + wire [11:0] M_AXI_JESD0_WID; + wire [31:0] M_AXI_JESD0_ARADDR; + wire [31:0] M_AXI_JESD0_AWADDR; + wire [31:0] M_AXI_JESD0_WDATA; + wire [3:0] M_AXI_JESD0_WSTRB; + wire M_AXI_JESD0_ARREADY; + wire M_AXI_JESD0_AWREADY; + wire M_AXI_JESD0_BVALID; + wire M_AXI_JESD0_RLAST; + wire M_AXI_JESD0_RVALID; + wire M_AXI_JESD0_WREADY; + wire [1:0] M_AXI_JESD0_BRESP; + wire [1:0] M_AXI_JESD0_RRESP; + wire [31:0] M_AXI_JESD0_RDATA; + + wire M_AXI_JESD1_ARVALID; + wire M_AXI_JESD1_AWVALID; + wire M_AXI_JESD1_BREADY; + wire M_AXI_JESD1_RREADY; + wire M_AXI_JESD1_WVALID; + wire [11:0] M_AXI_JESD1_ARID; + wire [11:0] M_AXI_JESD1_AWID; + wire [11:0] M_AXI_JESD1_WID; + wire [31:0] M_AXI_JESD1_ARADDR; + wire [31:0] M_AXI_JESD1_AWADDR; + wire [31:0] M_AXI_JESD1_WDATA; + wire [3:0] M_AXI_JESD1_WSTRB; + wire M_AXI_JESD1_ARREADY; + wire M_AXI_JESD1_AWREADY; + wire M_AXI_JESD1_BVALID; + wire M_AXI_JESD1_RLAST; + wire M_AXI_JESD1_RVALID; + wire M_AXI_JESD1_WREADY; + wire [1:0] M_AXI_JESD1_BRESP; + wire [1:0] M_AXI_JESD1_RRESP; + wire [31:0] M_AXI_JESD1_RDATA; + + // White Rabbit + wire wr_uart_txd; + wire wr_uart_rxd; + wire pps_wr_refclk; + wire wr_ref_clk; + + // AXI bus from PS to WR Core + wire m_axi_wr_clk; + wire [31:0] m_axi_wr_araddr; + wire [0:0] m_axi_wr_arready; + wire [0:0] m_axi_wr_arvalid; + wire [31:0] m_axi_wr_awaddr; + wire [0:0] m_axi_wr_awready; + wire [0:0] m_axi_wr_awvalid; + wire [0:0] m_axi_wr_bready; + wire [1:0] m_axi_wr_bresp; + wire [0:0] m_axi_wr_bvalid; + wire [31:0] m_axi_wr_rdata; + wire [0:0] m_axi_wr_rready; + wire [1:0] m_axi_wr_rresp; + wire [0:0] m_axi_wr_rvalid; + wire [31:0] m_axi_wr_wdata; + wire [0:0] m_axi_wr_wready; + wire [3:0] m_axi_wr_wstrb; + wire [0:0] m_axi_wr_wvalid; + + wire [63:0] ps_gpio_out; + wire [63:0] ps_gpio_in; + wire [63:0] ps_gpio_tri; + + wire [15:0] IRQ_F2P; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire clk100; + wire clk40; + wire meas_clk_ref; + wire bus_clk; + wire gige_refclk; + wire gige_refclk_bufg; + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + wire global_rst; + wire radio_rst; + wire bus_rst; + wire FCLK_RESET0_N; + wire clk40_rst; + wire clk40_rstn; + + wire [1:0] USB0_PORT_INDCTL; + wire USB0_VBUS_PWRSELECT; + wire USB0_VBUS_PWRFAULT; + + wire ref_clk; + wire wr_refclk_buf; + wire netclk_buf; + wire meas_clk; + wire ddr3_dma_clk; + wire meas_clk_reset; + wire meas_clk_locked; + wire enable_ref_clk_async; + wire pps_radioclk1x_iob; + wire pps_radioclk1x; + wire [3:0] pps_select; + wire pps_out_enb; + wire [1:0] pps_select_sfp; + wire pps_refclk; + wire export_pps_radioclk; + wire radio_clk; + wire radio_clkB; + wire radio_clk_2x; + wire radio_clk_2xB; + + wire qsfp_sda_i; + wire qsfp_sda_o; + wire qsfp_sda_t; + wire qsfp_scl_i; + wire qsfp_scl_o; + wire qsfp_scl_t; + + ///////////////////////////////////////////////////////////////////// + // + // Resets + // + ////////////////////////////////////////////////////////////////////// + + // Global synchronous reset, on the bus_clk domain. De-asserts after 85 + // bus_clk cycles. Asserted by default. + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + // Synchronous reset for the radio_clk domain, based on the global_rst. + reset_sync radio_reset_gen ( + .clk(radio_clk), + .reset_in(global_rst), + .reset_out(radio_rst) + ); + + // Synchronous reset for the bus_clk domain, based on the global_rst. + reset_sync bus_reset_gen ( + .clk(bus_clk), + .reset_in(global_rst), + .reset_out(bus_rst) + ); + + + // PS-based Resets // + // + // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. + reset_sync clk40_reset_gen ( + .clk(clk40), + .reset_in(~FCLK_RESET0_N), + .reset_out(clk40_rst) + ); + // Invert for various modules. + assign clk40_rstn = ~clk40_rst; + + + ///////////////////////////////////////////////////////////////////// + // + // Timing + // + ////////////////////////////////////////////////////////////////////// + + // Clocks from the PS + // + // These clocks appear to have BUFGs already instantiated by the ip generator. + // Simply rename them here for clarity. + // FCLK_CLK0 : 100 MHz + // FCLK_CLK1 : 40 MHz + // FCLK_CLK2 : 166.6667 MHz + // FCLK_CLK3 : 200 MHz + assign clk100 = FCLK_CLK0; + assign clk40 = FCLK_CLK1; + assign meas_clk_ref = FCLK_CLK2; + assign bus_clk = FCLK_CLK3; + + //If bus_clk freq ever changes, update this paramter accordingly. + localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. + + n3xx_clocking n3xx_clocking_i ( + .enable_ref_clk_async(enable_ref_clk_async), + .FPGA_REFCLK_P(FPGA_REFCLK_P), + .FPGA_REFCLK_N(FPGA_REFCLK_N), + .ref_clk(ref_clk), + .WB_20MHz_P(WB_20MHZ_P), + .WB_20MHz_N(WB_20MHZ_N), + .wr_refclk_buf(wr_refclk_buf), + .NETCLK_REF_P(NETCLK_REF_P), + .NETCLK_REF_N(NETCLK_REF_N), + .netclk_buf(netclk_buf), + .NETCLK_P(NETCLK_P), + .NETCLK_N(NETCLK_N), + .gige_refclk_buf(gige_refclk), + .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), + .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), + .xgige_refclk_buf(xgige_refclk), + .misc_clks_ref(meas_clk_ref), + .meas_clk(meas_clk), + .ddr3_dma_clk(ddr3_dma_clk), + .misc_clks_reset(meas_clk_reset), + .misc_clks_locked(meas_clk_locked), + .ext_pps_from_pin(REF_1PPS_IN), + .gps_pps_from_pin(GPS_1PPS), + .pps_select(pps_select), + .pps_refclk(pps_refclk) + ); + + // Drive the rear panel connector with another controllable copy of the post-TDC PPS + // that SW can enable/disable. The user is free to hack this to be whatever + // they desire. Flop the PPS signal one more time in order that it can be packed into + // an IOB. This extra flop stage matches the additional flop inside DbCore to allow + // pps_radioclk1x and pps_out_radioclk to be in sync with one another. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) pps_export_dsync ( + .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) + ); + + // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, + // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, + // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, + // variable depending on our radio_clk rate. Create two of the same output signal + // in order that the PPS_OUT gets packed into an IOB for tight timing. + reg [24:0] pps_out_count = 'b0; + reg pps_out_radioclk = 1'b0; + reg pps_led_radioclk = 1'b0; + + always @(posedge radio_clk) begin + if (export_pps_radioclk) begin + if (pps_radioclk1x_iob) begin + pps_out_radioclk <= 1'b1; + pps_led_radioclk <= 1'b1; + pps_out_count <= {25{1'b1}}; + end else begin + if (pps_out_count > 0) begin + pps_out_count <= pps_out_count - 1'b1; + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + end else begin + pps_out_radioclk <= 1'b0; + pps_led_radioclk <= 1'b0; + end + end + // Local to output. + assign REF_1PPS_OUT = pps_out_radioclk; + assign PANEL_LED_PPS = pps_led_radioclk; + + ///////////////////////////////////////////////////////////////////// + // + // SFP, QSFP and NPIO MGT Connections + // + ////////////////////////////////////////////////////////////////////// + wire reg_wr_req_npio; + wire [REG_AWIDTH-1:0] reg_wr_addr_npio; + wire [REG_DWIDTH-1:0] reg_wr_data_npio; + wire reg_rd_req_npio; + wire [REG_AWIDTH-1:0] reg_rd_addr_npio; + wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; + wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; + + localparam NPIO_REG_BASE = 14'h0200; + + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) npio_resp_mux_i( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), + .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), + .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) + ); + + //-------------------------------------------------------------- + // SFP/MGT Reference Clocks + //-------------------------------------------------------------- + + // We support the HG, XG, XA, AA targets, all of which require + // the 156.25MHz reference clock. Instantiate it here. + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .refclk_ibuf(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + wire qpllreset; + wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; + wire qplllock; + wire qplloutclk; + wire qplloutrefclk; + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), //from 2nd sfp + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) + ); + + // The quad's QPLL should reset if any of the channels request it + // This should never really happen because we are not changing the reference clock + // source for the QPLL. + assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; + + // Use the 156.25MHz reference clock for Aurora + wire aurora_refclk = xgige_refclk; + wire aurora_clk156 = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + + // White Rabbit and 1GbE both use the same clocking +`ifdef SFP0_1GBE + `define SFP0_WR_1GBE +`endif +`ifdef SFP0_WR + `define SFP0_WR_1GBE +`endif + +`ifdef SFP0_WR_1GBE + // HG and WX targets require the 1GbE clock support + BUFG bufg_gige_refclk_i ( + .I(gige_refclk), + .O(gige_refclk_bufg) + ); + assign SFP_0_RS0 = 1'b0; + assign SFP_0_RS1 = 1'b0; +`else + assign SFP_0_RS0 = 1'b1; + assign SFP_0_RS1 = 1'b1; +`endif + + // SFP 1 is always set to run at ~10Gbps rates. + assign SFP_1_RS0 = 1'b1; + assign SFP_1_RS1 = 1'b1; + + // SFP port specific reference clocks + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_WR_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_clk156; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_clk156; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + // Instantiate Aurora MMCM if either of the SFPs + // or NPIOs are Aurora + wire au_tx_clk; + wire au_mmcm_reset; + wire au_user_clk; + wire au_sync_clk; + wire au_mmcm_locked; + wire sfp0_tx_out_clk, sfp1_tx_out_clk; + wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; + wire npio0_tx_out_clk, npio1_tx_out_clk; + wire npio0_gt_pll_lock, npio1_gt_pll_lock; + + //NOTE: need to declare one of these defines in order to enable Aurora on + //any SFP or NPIO lane. +`ifdef SFP1_AURORA + `define SFP_AU_MMCM + assign au_tx_clk = sfp1_tx_out_clk; + assign au_mmcm_reset = ~sfp1_gt_pll_lock; +`elsif NPIO0 + `define SFP_AU_MMCM + assign au_tx_clk = npio0_tx_out_clk; + assign au_mmcm_reset = ~npio0_gt_pll_lock; +`elsif NPIO1 + `define SFP_AU_MMCM + assign au_tx_clk = npio1_tx_out_clk; + assign au_mmcm_reset = ~npio1_gt_pll_lock; +`endif + + +`ifdef SFP_AU_MMCM + aurora_phy_mmcm au_phy_mmcm_i ( + .aurora_tx_clk_unbuf(au_tx_clk), + .mmcm_reset(au_mmcm_reset), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); +`else + assign au_user_clk = 1'b0; + assign au_sync_clk = 1'b0; + assign au_mmcm_locked = 1'b0; +`endif + + //-------------------------------------------------------------- + // NPIO-QSFP MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef QSFP_LANES + localparam NUM_QSFP_LANES = `QSFP_LANES; + + // QSFP wires to the ARM core and the crossbar + // These will only be connected if QSFP is 2x10 GbE + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; + wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; + wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; + wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; + + wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; + + wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; + wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; + + wire [NUM_QSFP_LANES-1:0] qsfp_link_up; + + // QSFP quad's specific reference clocks + wire qsfp_gt_refclk; + wire qsfp_gb_refclk; + wire qsfp_misc_clk; + + wire qsfp_qplloutclk; + wire qsfp_qplloutrefclk; + wire qsfp_qplllock; + wire qsfp_qpllreset; + + wire qsfp_gt_tx_out_clk; + wire qsfp_gt_pll_lock; + + wire qsfp_au_user_clk; + wire qsfp_au_sync_clk; + wire qsfp_au_mmcm_locked; + + +`ifdef QSFP_10GBE + assign qsfp_gt_refclk = xgige_refclk; + assign qsfp_gb_refclk = xgige_clk156; + assign qsfp_misc_clk = xgige_dclk; +`endif +`ifdef QSFP_AURORA + assign qsfp_gt_refclk = aurora_refclk; + assign qsfp_gb_refclk = aurora_clk156; + assign qsfp_misc_clk = aurora_init_clk; +`endif + + // We reuse this GT_COMMON wrapper for both ethernet and Aurora because + // the behavior is identical + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) qsfp_gt_common_block ( + .refclk(xgige_refclk), + .qpllreset(qsfp_qpllreset), + .qplllock(qsfp_qplllock), + .qplloutclk(qsfp_qplloutclk), + .qplloutrefclk(qsfp_qplloutrefclk), + .qpllrefclksel(3'b001 /*GTREFCLK0*/) + ); + + `ifdef QSFP_AURORA + aurora_phy_mmcm aurora_phy_mmcm ( + .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), + .mmcm_reset(~qsfp_gt_pll_lock), + .user_clk(qsfp_au_user_clk), + .sync_clk(qsfp_au_sync_clk), + .mmcm_locked(qsfp_au_mmcm_locked) + ); + `else + assign qsfp_au_user_clk = 1'b0; + assign qsfp_au_sync_clk = 1'b0; + assign qsfp_au_mmcm_locked = 1'b0; + `endif + + n3xx_mgt_channel_wrapper #( + `ifdef QSFP_10GBE + .PROTOCOL ("10GbE"), + .MDIO_EN (1'b1), + .MDIO_PHYADDR (5'd4), + `elsif QSFP_AURORA + .PROTOCOL ("Aurora"), + .MDIO_EN (1'b0), + `endif + .LANES (NUM_QSFP_LANES), + .GT_COMMON (1), + .PORTNUM_BASE (4), + .REG_DWIDTH (REG_DWIDTH), + .REG_AWIDTH (QSFP_REG_AWIDTH) + ) qsfp_wrapper_i ( + .areset (global_rst), + .gt_refclk (qsfp_gt_refclk), + .gb_refclk (qsfp_gb_refclk), + .misc_clk (qsfp_misc_clk), + .user_clk (qsfp_au_user_clk), + .sync_clk (qsfp_au_sync_clk), + .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), + + .bus_clk (bus_clk), + .bus_rst (bus_rst), + + // GT Common + .qpllrefclklost (), + .qplllock (qsfp_qplllock), + .qplloutclk (qsfp_qplloutclk), + .qplloutrefclk (qsfp_qplloutrefclk), + .qpllreset (qsfp_qpllreset), + + // Aurora MMCM + .mmcm_locked (qsfp_au_mmcm_locked), + .gt_pll_lock (qsfp_gt_pll_lock), + + .txp (QSFP_TX_P), + .txn (QSFP_TX_N), + .rxp (QSFP_RX_P), + .rxn (QSFP_RX_N), + + .mod_present_n (QSFP_PRESENT_B), + .mod_rxlos (1'b0), + .mod_tx_fault (1'b0), + .mod_tx_disable (), + .mod_int_n (QSFP_INT_B), + .mod_reset_n (QSFP_RESET_B), + .mod_lpmode (QSFP_LPMODE), + .mod_sel_n (QSFP_MODSEL_B), + + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_aresetn (clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_awvalid (M_AXI_NET2_AWVALID), + .s_axi_awready (M_AXI_NET2_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (M_AXI_NET2_WDATA), + .s_axi_wstrb (M_AXI_NET2_WSTRB), + .s_axi_wvalid (M_AXI_NET2_WVALID), + .s_axi_wready (M_AXI_NET2_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (M_AXI_NET2_BRESP), + .s_axi_bvalid (M_AXI_NET2_BVALID), + .s_axi_bready (M_AXI_NET2_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), + .s_axi_arvalid (M_AXI_NET2_ARVALID), + .s_axi_arready (M_AXI_NET2_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_NET2_RDATA), + .s_axi_rresp (M_AXI_NET2_RRESP), + .s_axi_rvalid (M_AXI_NET2_RVALID), + .s_axi_rready (M_AXI_NET2_RREADY), + + // Ethernet to Vita + .e2v_tdata (e2v_qsfp_tdata), + .e2v_tlast (e2v_qsfp_tlast), + .e2v_tvalid (e2v_qsfp_tvalid), + .e2v_tready (e2v_qsfp_tready), + + // Vita to Ethernet + .v2e_tdata (v2e_qsfp_tdata), + .v2e_tlast (v2e_qsfp_tlast), + .v2e_tvalid (v2e_qsfp_tvalid), + .v2e_tready (v2e_qsfp_tready), + + // Ethernet to CPU + .e2c_tdata (arm_eth_qsfp_rx_tdata_b), + .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), + .e2c_tlast (arm_eth_qsfp_rx_tlast_b), + .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), + .e2c_tready (arm_eth_qsfp_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata (arm_eth_qsfp_tx_tdata_b), + .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), + .c2e_tlast (arm_eth_qsfp_tx_tlast_b), + .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), + .c2e_tready (arm_eth_qsfp_tx_tready_b), + + // Sideband White Rabbit Control + .wr_reset_n (1'b1), + .wr_refclk (1'b0), + + .wr_dac_sclk (), + .wr_dac_din (), + .wr_dac_clr_n (), + .wr_dac_cs_n (), + .wr_dac_ldac_n (), + + .wr_eeprom_scl_o(), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), + + .wr_uart_rx (1'b0), + .wr_uart_tx (), + + .mod_pps (), + .mod_refclk (), + + // WR AXI Control + .wr_axi_aclk (), + .wr_axi_aresetn (1'b1), + .wr_axi_awaddr (), + .wr_axi_awvalid (), + .wr_axi_awready (), + .wr_axi_wdata (), + .wr_axi_wstrb (), + .wr_axi_wvalid (), + .wr_axi_wready (), + .wr_axi_bresp (), + .wr_axi_bvalid (), + .wr_axi_bready (), + .wr_axi_araddr (), + .wr_axi_arvalid (), + .wr_axi_arready (), + .wr_axi_rdata (), + .wr_axi_rresp (), + .wr_axi_rvalid (), + .wr_axi_rready (), + .wr_axi_rlast (), + + .port_info (), + .device_id (device_id), + + .link_up (qsfp_link_up), + .activity () + ); + + assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; + assign qsfp_scl_i = QSFP_I2C_SCL; + assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; + assign qsfp_sda_i = QSFP_I2C_SDA; + + assign QSFP_LED = |qsfp_link_up; +`else + + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_qsfp ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_NET2_AWADDR), + .s_axi_awvalid(M_AXI_NET2_AWVALID), + .s_axi_awready(M_AXI_NET2_AWREADY), + + .s_axi_wdata(M_AXI_NET2_WDATA), + .s_axi_wvalid(M_AXI_NET2_WVALID), + .s_axi_wready(M_AXI_NET2_WREADY), + + .s_axi_bresp(M_AXI_NET2_BRESP), + .s_axi_bvalid(M_AXI_NET2_BVALID), + .s_axi_bready(M_AXI_NET2_BREADY), + + .s_axi_araddr(M_AXI_NET2_ARADDR), + .s_axi_arvalid(M_AXI_NET2_ARVALID), + .s_axi_arready(M_AXI_NET2_ARREADY), + + .s_axi_rdata(M_AXI_NET2_RDATA), + .s_axi_rresp(M_AXI_NET2_RRESP), + .s_axi_rvalid(M_AXI_NET2_RVALID), + .s_axi_rready(M_AXI_NET2_RREADY) + + ); + + assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; + assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; + +`endif + + //-------------------------------------------------------------- + // NPIO MGT Lanes (Example loopback config) + //-------------------------------------------------------------- + +`ifdef NPIO_LANES + + wire [127:0] npio_loopback_tdata; + wire [1:0] npio_loopback_tvalid; + wire [1:0] npio_loopback_tready; + wire [1:0] npio_loopback_tlast; + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h00), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd2), + .MDIO_EN (0) + ) npio_ln_0_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio0_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio0), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX0_P), + .rxn (NPIO_RX0_N), + .txp (NPIO_TX0_P), + .txn (NPIO_TX0_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio0), + .reg_rd_data (reg_rd_data_npio0), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[0]), + .s_axis_tlast (npio_loopback_tlast[0]), + .s_axis_tready (npio_loopback_tready[0]), + .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[0]), + .m_axis_tlast (npio_loopback_tlast[0]), + .m_axis_tready (npio_loopback_tready[0]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio0_gt_pll_lock) + ); + + n3xx_mgt_io_core #( + .PROTOCOL ("Aurora"), + .REG_BASE (NPIO_REG_BASE + 14'h40), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .PORTNUM (8'd3), + .MDIO_EN (0) + ) npio_ln_1_i ( + .areset (global_rst), + .gt_refclk (aurora_refclk), + .gb_refclk (aurora_clk156), + .misc_clk (aurora_init_clk), + .user_clk (au_user_clk), + .sync_clk (au_sync_clk), + .gt_tx_out_clk_unbuf(npio1_tx_out_clk), + + .bus_clk (bus_clk),//clk for status reg reads to mdio interface + .bus_rst (bus_rst), + .qpllreset (qpllreset_npio1), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qplllock (qplllock), + .qpllrefclklost (), + + .rxp (NPIO_RX1_P), + .rxn (NPIO_RX1_N), + .txp (NPIO_TX1_P), + .txn (NPIO_TX1_N), + + .sfpp_rxlos (1'b0), + .sfpp_tx_fault (1'b0), + + //RegPort + .reg_wr_req (reg_wr_req_npio), + .reg_wr_addr (reg_wr_addr_npio), + .reg_wr_data (reg_wr_data_npio), + .reg_rd_req (reg_rd_req_npio), + .reg_rd_addr (reg_rd_addr_npio), + .reg_rd_resp (reg_rd_resp_npio1), + .reg_rd_data (reg_rd_data_npio1), + + //DATA (loopback mode) + .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core + .s_axis_tuser (4'b0), + .s_axis_tvalid (npio_loopback_tvalid[1]), + .s_axis_tlast (npio_loopback_tlast[1]), + .s_axis_tready (npio_loopback_tready[1]), + .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core + .m_axis_tuser (), + .m_axis_tvalid (npio_loopback_tvalid[1]), + .m_axis_tlast (npio_loopback_tlast[1]), + .m_axis_tready (npio_loopback_tready[1]), + + .mmcm_locked (au_mmcm_locked), + .gt_pll_lock (npio1_gt_pll_lock) + ); + +`else + + assign reg_rd_resp_npio0 = 1'b0; + assign reg_rd_data_npio0 = 'h0; + assign reg_rd_resp_npio1 = 1'b0; + assign reg_rd_data_npio1 = 'h0; + assign npio0_gt_pll_lock = 1'b1; + assign npio1_gt_pll_lock = 1'b1; + assign qpllreset_npio0 = 1'b0; + assign qpllreset_npio1 = 1'b0; + +`endif + + + // ARM ethernet 0 bridge signals + wire [63:0] arm_eth0_tx_tdata; + wire arm_eth0_tx_tvalid; + wire arm_eth0_tx_tlast; + wire arm_eth0_tx_tready; + wire [3:0] arm_eth0_tx_tuser; + wire [7:0] arm_eth0_tx_tkeep; + + wire [63:0] arm_eth0_tx_tdata_b; + wire arm_eth0_tx_tvalid_b; + wire arm_eth0_tx_tlast_b; + wire arm_eth0_tx_tready_b; + wire [3:0] arm_eth0_tx_tuser_b; + wire [7:0] arm_eth0_tx_tkeep_b; + + wire [63:0] arm_eth_sfp0_tx_tdata_b; + wire arm_eth_sfp0_tx_tvalid_b; + wire arm_eth_sfp0_tx_tlast_b; + wire arm_eth_sfp0_tx_tready_b; + wire [3:0] arm_eth_sfp0_tx_tuser_b; + wire [7:0] arm_eth_sfp0_tx_tkeep_b; + + wire [63:0] arm_eth0_rx_tdata; + wire arm_eth0_rx_tvalid; + wire arm_eth0_rx_tlast; + wire arm_eth0_rx_tready; + wire [3:0] arm_eth0_rx_tuser; + wire [7:0] arm_eth0_rx_tkeep; + + wire [63:0] arm_eth0_rx_tdata_b; + wire arm_eth0_rx_tvalid_b; + wire arm_eth0_rx_tlast_b; + wire arm_eth0_rx_tready_b; + wire [3:0] arm_eth0_rx_tuser_b; + wire [7:0] arm_eth0_rx_tkeep_b; + + wire [63:0] arm_eth_sfp0_rx_tdata_b; + wire arm_eth_sfp0_rx_tvalid_b; + wire arm_eth_sfp0_rx_tlast_b; + wire arm_eth_sfp0_rx_tready_b; + wire [3:0] arm_eth_sfp0_rx_tuser_b; + wire [7:0] arm_eth_sfp0_rx_tkeep_b; + + wire arm_eth0_rx_irq; + wire arm_eth0_tx_irq; + + // ARM ethernet 1 bridge signals + wire [63:0] arm_eth1_tx_tdata; + wire arm_eth1_tx_tvalid; + wire arm_eth1_tx_tlast; + wire arm_eth1_tx_tready; + wire [3:0] arm_eth1_tx_tuser; + wire [7:0] arm_eth1_tx_tkeep; + + wire [63:0] arm_eth1_tx_tdata_b; + wire arm_eth1_tx_tvalid_b; + wire arm_eth1_tx_tlast_b; + wire arm_eth1_tx_tready_b; + wire [3:0] arm_eth1_tx_tuser_b; + wire [7:0] arm_eth1_tx_tkeep_b; + + wire [63:0] arm_eth_sfp1_tx_tdata_b; + wire arm_eth_sfp1_tx_tvalid_b; + wire arm_eth_sfp1_tx_tlast_b; + wire arm_eth_sfp1_tx_tready_b; + wire [3:0] arm_eth_sfp1_tx_tuser_b; + wire [7:0] arm_eth_sfp1_tx_tkeep_b; + + wire [63:0] arm_eth1_rx_tdata; + wire arm_eth1_rx_tvalid; + wire arm_eth1_rx_tlast; + wire arm_eth1_rx_tready; + wire [3:0] arm_eth1_rx_tuser; + wire [7:0] arm_eth1_rx_tkeep; + + wire [63:0] arm_eth1_rx_tdata_b; + wire arm_eth1_rx_tvalid_b; + wire arm_eth1_rx_tlast_b; + wire arm_eth1_rx_tready_b; + wire [3:0] arm_eth1_rx_tuser_b; + wire [7:0] arm_eth1_rx_tkeep_b; + + wire [63:0] arm_eth_sfp1_rx_tdata_b; + wire arm_eth_sfp1_rx_tvalid_b; + wire arm_eth_sfp1_rx_tlast_b; + wire arm_eth_sfp1_rx_tready_b; + wire [3:0] arm_eth_sfp1_rx_tuser_b; + wire [7:0] arm_eth_sfp1_rx_tkeep_b; + + wire arm_eth1_tx_irq; + wire arm_eth1_rx_irq; + + // Vita to Ethernet + wire [63:0] v2e0_tdata; + wire v2e0_tlast; + wire v2e0_tvalid; + wire v2e0_tready; + + wire [63:0] v2e1_tdata; + wire v2e1_tlast; + wire v2e1_tvalid; + wire v2e1_tready; + + wire [63:0] v2e_sfp0_tdata; + wire v2e_sfp0_tlast; + wire v2e_sfp0_tvalid; + wire v2e_sfp0_tready; + + wire [63:0] v2e_sfp1_tdata; + wire v2e_sfp1_tlast; + wire v2e_sfp1_tvalid; + wire v2e_sfp1_tready; + + // Ethernet to Vita + wire [63:0] e2v0_tdata; + wire e2v0_tlast; + wire e2v0_tvalid; + wire e2v0_tready; + + wire [63:0] e2v1_tdata; + wire e2v1_tlast; + wire e2v1_tvalid; + wire e2v1_tready; + + wire [63:0] e2v_sfp0_tdata; + wire e2v_sfp0_tlast; + wire e2v_sfp0_tvalid; + wire e2v_sfp0_tready; + + wire [63:0] e2v_sfp1_tdata; + wire e2v_sfp1_tlast; + wire e2v_sfp1_tvalid; + wire e2v_sfp1_tready; + + // Ethernet crossover + wire [63:0] e01_tdata, e10_tdata; + wire [3:0] e01_tuser, e10_tuser; + wire e01_tlast, e01_tvalid, e01_tready; + wire e10_tlast, e10_tvalid, e10_tready; + + + // DMA xport adapter to PS + wire [63:0] m_axis_dma_tdata; + wire [3:0] m_axis_dma_tuser; + wire m_axis_dma_tlast; + wire m_axis_dma_tready; + wire m_axis_dma_tvalid; + + wire [63:0] s_axis_dma_tdata; + wire [3:0] s_axis_dma_tdest; + wire s_axis_dma_tlast; + wire s_axis_dma_tready; + wire s_axis_dma_tvalid; + + // Misc + wire [31:0] sfp_port0_info; + wire [31:0] sfp_port1_info; + wire sfp0_link_up, sfp1_link_up; + wire [15:0] device_id; + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 0: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP0_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `elsif SFP0_1GBE + .PROTOCOL("1GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP0_WR + .PROTOCOL("WhiteRabbit"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd0) + ) sfp_wrapper_0 ( + .areset(global_rst), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp0), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp0_gt_pll_lock), + + .txp(SFP_0_TX_P), + .txn(SFP_0_TX_N), + .rxp(SFP_0_RX_P), + .rxn(SFP_0_RX_N), + + .mod_present_n(SFP_0_I2C_NPRESENT), + .mod_rxlos(SFP_0_LOS), + .mod_tx_fault(SFP_0_TXFAULT), + .mod_tx_disable(SFP_0_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET0_AWVALID), + .s_axi_awready(M_AXI_NET0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET0_WDATA), + .s_axi_wstrb(M_AXI_NET0_WSTRB), + .s_axi_wvalid(M_AXI_NET0_WVALID), + .s_axi_wready(M_AXI_NET0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET0_BRESP), + .s_axi_bvalid(M_AXI_NET0_BVALID), + .s_axi_bready(M_AXI_NET0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET0_ARVALID), + .s_axi_arready(M_AXI_NET0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET0_RDATA), + .s_axi_rresp(M_AXI_NET0_RRESP), + .s_axi_rvalid(M_AXI_NET0_RVALID), + .s_axi_rready(M_AXI_NET0_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp0_tdata), + .e2v_tlast(e2v_sfp0_tlast), + .e2v_tvalid(e2v_sfp0_tvalid), + .e2v_tready(e2v_sfp0_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp0_tdata), + .v2e_tlast(v2e_sfp0_tlast), + .v2e_tvalid(v2e_sfp0_tvalid), + .v2e_tready(v2e_sfp0_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp0_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp0_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), + .e2c_tready(arm_eth_sfp0_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp0_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp0_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), + .c2e_tready(arm_eth_sfp0_tx_tready_b), + + // White Rabbit Specific +`ifdef SFP0_WR + .wr_reset_n (~ps_gpio_out[48]), // reset for WR only + .wr_refclk (wr_refclk_buf), + .wr_dac_sclk (WB_DAC_SCLK), + .wr_dac_din (WB_DAC_DIN), + .wr_dac_clr_n (WB_DAC_NCLR), + .wr_dac_cs_n (WB_DAC_NSYNC), + .wr_dac_ldac_n(WB_DAC_NLDAC), + .wr_eeprom_scl_o(), // storage for delay characterization + .wr_eeprom_scl_i(1'b0), // temp + .wr_eeprom_sda_o(), + .wr_eeprom_sda_i(1'b0), // temp + .wr_uart_rx(wr_uart_rxd), // to/from PS + .wr_uart_tx(wr_uart_txd), + .mod_pps(pps_wr_refclk), // out, reference clock and pps + .mod_refclk(wr_ref_clk), + // WR Slave Port to PS + .wr_axi_aclk(m_axi_wr_clk), // out to PS + .wr_axi_aresetn(1'b1), // in + .wr_axi_awaddr(m_axi_wr_awaddr), + .wr_axi_awvalid(m_axi_wr_awvalid), + .wr_axi_awready(m_axi_wr_awready), + .wr_axi_wdata(m_axi_wr_wdata), + .wr_axi_wstrb(m_axi_wr_wstrb), + .wr_axi_wvalid(m_axi_wr_wvalid), + .wr_axi_wready(m_axi_wr_wready), + .wr_axi_bresp(m_axi_wr_bresp), + .wr_axi_bvalid(m_axi_wr_bvalid), + .wr_axi_bready(m_axi_wr_bready), + .wr_axi_araddr(m_axi_wr_araddr), + .wr_axi_arvalid(m_axi_wr_arvalid), + .wr_axi_arready(m_axi_wr_arready), + .wr_axi_rdata(m_axi_wr_rdata), + .wr_axi_rresp(m_axi_wr_rresp), + .wr_axi_rvalid(m_axi_wr_rvalid), + .wr_axi_rready(m_axi_wr_rready), + .wr_axi_rlast(), +`else + .wr_reset_n(1'b1), + .wr_refclk(1'b0), + .wr_eeprom_scl_i(1'b0), + .wr_eeprom_sda_i(1'b0), + .wr_uart_rx(1'b0), +`endif + + // Misc + .port_info(sfp_port0_info), + .device_id(device_id), + + // LED + .link_up(sfp0_link_up), + .activity(SFP_0_LED_A) + ); + + assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; + assign SFP_0_LED_B = sfp0_link_up; + +`ifndef SFP0_WR + assign WB_DAC_SCLK = 1'b0; + assign WB_DAC_DIN = 1'b0; + assign WB_DAC_NCLR = 1'b1; + assign WB_DAC_NSYNC = 1'b1; + assign WB_DAC_NLDAC = 1'b1; + assign pps_wr_refclk = 1'b0; + assign wr_ref_clk = 1'b0; +`endif + + ///////////////////////////////////////////////////////////////////// + // + // SFP Wrapper 1: Network Interface (1/10G or Aurora) + // + ////////////////////////////////////////////////////////////////////// + + n3xx_mgt_channel_wrapper #( + .LANES(1), + `ifdef SFP1_10GBE + .PROTOCOL("10GbE"), + .MDIO_EN(1'b1), + .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file + `elsif SFP1_AURORA + .PROTOCOL("Aurora"), + .MDIO_EN(1'b0), + `endif + .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH(REG_AWIDTH), // Width of the address bus + .GT_COMMON(1), + .PORTNUM_BASE(8'd1) + ) sfp_wrapper_1 ( + .areset(global_rst), + + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + + .qpllreset(qpllreset_sfp1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclklost(), + + .mmcm_locked(au_mmcm_locked), + .gt_pll_lock(sfp1_gt_pll_lock), + + .txp(SFP_1_TX_P), + .txn(SFP_1_TX_N), + .rxp(SFP_1_RX_P), + .rxn(SFP_1_RX_N), + + .mod_rxlos(SFP_1_LOS), + .mod_tx_fault(SFP_1_TXFAULT), + .mod_tx_disable(SFP_1_TXDISABLE), + + // Clock and reset + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), + .s_axi_awvalid(M_AXI_NET1_AWVALID), + .s_axi_awready(M_AXI_NET1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_NET1_WDATA), + .s_axi_wstrb(M_AXI_NET1_WSTRB), + .s_axi_wvalid(M_AXI_NET1_WVALID), + .s_axi_wready(M_AXI_NET1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_NET1_BRESP), + .s_axi_bvalid(M_AXI_NET1_BVALID), + .s_axi_bready(M_AXI_NET1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), + .s_axi_arvalid(M_AXI_NET1_ARVALID), + .s_axi_arready(M_AXI_NET1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_NET1_RDATA), + .s_axi_rresp(M_AXI_NET1_RRESP), + .s_axi_rvalid(M_AXI_NET1_RVALID), + .s_axi_rready(M_AXI_NET1_RREADY), + + // Ethernet to Vita + .e2v_tdata(e2v_sfp1_tdata), + .e2v_tlast(e2v_sfp1_tlast), + .e2v_tvalid(e2v_sfp1_tvalid), + .e2v_tready(e2v_sfp1_tready), + + // Vita to Ethernet + .v2e_tdata(v2e_sfp1_tdata), + .v2e_tlast(v2e_sfp1_tlast), + .v2e_tvalid(v2e_sfp1_tvalid), + .v2e_tready(v2e_sfp1_tready), + + // Ethernet to CPU + .e2c_tdata(arm_eth_sfp1_rx_tdata_b), + .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), + .e2c_tlast(arm_eth_sfp1_rx_tlast_b), + .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), + .e2c_tready(arm_eth_sfp1_rx_tready_b), + + // CPU to Ethernet + .c2e_tdata(arm_eth_sfp1_tx_tdata_b), + .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), + .c2e_tlast(arm_eth_sfp1_tx_tlast_b), + .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), + .c2e_tready(arm_eth_sfp1_tx_tready_b), + + // Misc + .port_info(sfp_port1_info), + .device_id(device_id), + + // LED + .link_up(sfp1_link_up), + .activity(SFP_1_LED_A) + ); + + assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; + assign SFP_1_LED_B = sfp1_link_up; + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 0 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[0] = arm_eth0_rx_irq; + assign IRQ_F2P[1] = arm_eth0_tx_irq; + + assign {S_AXI_HP0_AWID, S_AXI_HP0_ARID} = 12'd0; + assign {S_AXI_GP0_AWID, S_AXI_GP0_ARID} = 10'd0; + +`ifdef QSFP_10GBE + // QSFP+ lanes connect to DMA engines and crossbar + // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; + assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; + assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; + assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; + assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; + assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; + + // Connect first QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; + assign v2e_qsfp_tlast[0] = v2e0_tlast; + assign v2e_qsfp_tvalid[0] = v2e0_tvalid; + assign v2e0_tready = v2e_qsfp_tready[0]; + + assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; + assign e2v0_tlast = e2v_qsfp_tlast[0]; + assign e2v0_tvalid = e2v_qsfp_tvalid[0]; + assign e2v_qsfp_tready[0] = e2v0_tready; + + // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; + assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; + assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; + assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; + assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; + assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; + assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; + assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; + assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; + + // Connect second QSFP+ 10 GbE port to the crossbar + assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; + assign v2e_qsfp_tlast[1] = v2e1_tlast; + assign v2e_qsfp_tvalid[1] = v2e1_tvalid; + assign v2e1_tready = v2e_qsfp_tready[1]; + + assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; + assign e2v1_tlast = e2v_qsfp_tlast[1]; + assign e2v1_tvalid = e2v_qsfp_tvalid[1]; + assign e2v_qsfp_tready[1] = e2v1_tready; +`else + // SFP+ ports connects to DMA engines and crossbar + // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; + assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; + assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; + assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; + assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; + assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; + + assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; + assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; + assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; + assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; + assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; + assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp0_tdata = v2e0_tdata; + assign v2e_sfp0_tlast = v2e0_tlast; + assign v2e_sfp0_tvalid = v2e0_tvalid; + assign v2e0_tready = v2e_sfp0_tready; + + assign e2v0_tdata = e2v_sfp0_tdata; + assign e2v0_tlast = e2v_sfp0_tlast; + assign e2v0_tvalid = e2v_sfp0_tvalid; + assign e2v_sfp0_tready = e2v0_tready; + + // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) + assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; + assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; + assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; + assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; + assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; + assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; + + assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; + assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; + assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; + assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; + assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; + assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; + + // Connect first SFP+ 10 GbE port to the crossbar + assign v2e_sfp1_tdata = v2e1_tdata; + assign v2e_sfp1_tlast = v2e1_tlast; + assign v2e_sfp1_tvalid = v2e1_tvalid; + assign v2e1_tready = v2e_sfp1_tready; + + assign e2v1_tdata = e2v_sfp1_tdata; + assign e2v1_tlast = e2v_sfp1_tlast; + assign e2v1_tvalid = e2v_sfp1_tvalid; + assign e2v_sfp1_tready = e2v1_tready; + + // Don't actually instantiate DMA engines if protocols can't use them + `ifdef SFP0_AURORA + `define NO_ETH_DMA_0 + `elsif SFP0_WR + `define NO_ETH_DMA_0 + `endif + + `ifdef SFP1_AURORA + `define NO_ETH_DMA_1 + `endif +`endif + +`ifdef NO_ETH_DMA_0 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #( + .DEC_ERR(1'b0) + ) inst_axi_dummy_sfp0_eth_dma ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_rready(M_AXI_ETH_DMA0_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP0_AWADDR = 32'h0; + assign S_AXI_GP0_AWLEN = 8'h0; + assign S_AXI_GP0_AWSIZE = 4'h0; + assign S_AXI_GP0_AWBURST = 3'h0; + assign S_AXI_GP0_AWPROT = 3'h0; + assign S_AXI_GP0_AWCACHE = 4'h0; + assign S_AXI_GP0_AWVALID = 1'b0; + //S_AXI_GP0_AWREADY output from PS + assign S_AXI_GP0_WDATA = 32'h0; + assign S_AXI_GP0_WSTRB = 4'h0; + assign S_AXI_GP0_WLAST = 1'b0; + assign S_AXI_GP0_WVALID = 1'b0; + //S_AXI_GP0_WREADY output from PS + //S_AXI_GP0_BRESP + //S_AXI_GP0_BVALID + assign S_AXI_GP0_BREADY = 1'b1; + assign S_AXI_GP0_ARADDR = 32'h0; + assign S_AXI_GP0_ARLEN = 8'h0; + assign S_AXI_GP0_ARSIZE = 3'h0; + assign S_AXI_GP0_ARBURST = 2'h0; + assign S_AXI_GP0_ARPROT = 3'h0; + assign S_AXI_GP0_ARCACHE = 4'h0; + assign S_AXI_GP0_ARVALID = 1'b0; + //S_AXI_GP0_ARREADY + //S_AXI_GP0_RDATA + //S_AXI_GP0_RRESP + //S_AXI_GP0_RLAST + //S_AXI_GP0_RVALID + assign S_AXI_GP0_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP0_ARADDR = 32'h0; + assign S_AXI_HP0_ARLEN = 8'h0; + assign S_AXI_HP0_ARSIZE = 3'h0; + assign S_AXI_HP0_ARBURST = 2'h0; + assign S_AXI_HP0_ARPROT = 3'h0; + assign S_AXI_HP0_ARCACHE = 4'h0; + assign S_AXI_HP0_ARVALID = 1'b0; + //S_AXI_HP0_ARREADY + //S_AXI_HP0_RDATA + //S_AXI_HP0_RRESP + //S_AXI_HP0_RLAST + //S_AXI_HP0_RVALID + assign S_AXI_HP0_RREADY = 1'b1; + assign S_AXI_HP0_AWADDR = 32'h0; + assign S_AXI_HP0_AWLEN = 8'h0; + assign S_AXI_HP0_AWSIZE = 3'h0; + assign S_AXI_HP0_AWBURST = 2'h0; + assign S_AXI_HP0_AWPROT = 3'h0; + assign S_AXI_HP0_AWCACHE = 4'h0; + assign S_AXI_HP0_AWVALID = 1'b0; + //S_AXI_HP0_AWREADY + assign S_AXI_HP0_WDATA = 64'h0; + assign S_AXI_HP0_WSTRB = 8'h0; + assign S_AXI_HP0_WLAST = 1'b0; + assign S_AXI_HP0_WVALID = 1'b0; + //S_AXI_HP0_WREADY + //S_AXI_HP0_BRESP + //S_AXI_HP0_BVALID + assign S_AXI_HP0_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma0 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), + .m_axi_sg_awlen(S_AXI_GP0_AWLEN), + .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP0_AWBURST), + .m_axi_sg_awprot(S_AXI_GP0_AWPROT), + .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), + .m_axi_sg_awready(S_AXI_GP0_AWREADY), + .m_axi_sg_wdata(S_AXI_GP0_WDATA), + .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), + .m_axi_sg_wlast(S_AXI_GP0_WLAST), + .m_axi_sg_wvalid(S_AXI_GP0_WVALID), + .m_axi_sg_wready(S_AXI_GP0_WREADY), + .m_axi_sg_bresp(S_AXI_GP0_BRESP), + .m_axi_sg_bvalid(S_AXI_GP0_BVALID), + .m_axi_sg_bready(S_AXI_GP0_BREADY), + .m_axi_sg_araddr(S_AXI_GP0_ARADDR), + .m_axi_sg_arlen(S_AXI_GP0_ARLEN), + .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP0_ARBURST), + .m_axi_sg_arprot(S_AXI_GP0_ARPROT), + .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), + .m_axi_sg_arready(S_AXI_GP0_ARREADY), + .m_axi_sg_rdata(S_AXI_GP0_RDATA), + .m_axi_sg_rresp(S_AXI_GP0_RRESP), + .m_axi_sg_rlast(S_AXI_GP0_RLAST), + .m_axi_sg_rvalid(S_AXI_GP0_RVALID), + .m_axi_sg_rready(S_AXI_GP0_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), + .m_axi_mm2s_rready(S_AXI_HP0_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth0_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), + .m_axis_mm2s_tready(arm_eth0_tx_tready), + .m_axis_mm2s_tlast(arm_eth0_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), + .m_axi_s2mm_wready(S_AXI_HP0_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), + .m_axi_s2mm_bready(S_AXI_HP0_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth0_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), + .s_axis_s2mm_tready(arm_eth0_rx_tready), + .s_axis_s2mm_tlast(arm_eth0_rx_tlast), + + .mm2s_introut(arm_eth0_tx_irq), + .s2mm_introut(arm_eth0_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_0_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), + .i_tvalid(arm_eth0_tx_tvalid), + .i_tready(arm_eth0_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), + .o_tvalid(arm_eth0_tx_tvalid_b), + .o_tready(arm_eth0_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_0_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), + .i_tvalid(arm_eth0_rx_tvalid_b), + .i_tready(arm_eth0_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), + .o_tvalid(arm_eth0_rx_tvalid), + .o_tready(arm_eth0_rx_tready) + ); + +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Ethernet DMA 1 + // + ////////////////////////////////////////////////////////////////////// + + assign IRQ_F2P[2] = arm_eth1_rx_irq; + assign IRQ_F2P[3] = arm_eth1_tx_irq; + + assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; + assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; + +`ifdef NO_ETH_DMA_1 + //If inst Aurora, tie off each axi/axi-lite interface + axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma + ( + .s_axi_aclk(bus_clk), + .s_axi_areset(bus_rst), + + .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_rready(M_AXI_ETH_DMA1_RREADY) + + ); + //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off + assign S_AXI_GP1_AWADDR = 32'h0; + assign S_AXI_GP1_AWLEN = 8'h0; + assign S_AXI_GP1_AWSIZE = 4'h0; + assign S_AXI_GP1_AWBURST = 3'h0; + assign S_AXI_GP1_AWPROT = 3'h0; + assign S_AXI_GP1_AWCACHE = 4'h0; + assign S_AXI_GP1_AWVALID = 1'b0; + //S_AXI_GP1_AWREADY output from PS + assign S_AXI_GP1_WDATA = 32'h0; + assign S_AXI_GP1_WSTRB = 4'h0; + assign S_AXI_GP1_WLAST = 1'b0; + assign S_AXI_GP1_WVALID = 1'b0; + //S_AXI_GP1_WREADY output from PS + //S_AXI_GP1_BRESP + //S_AXI_GP1_BVALID + assign S_AXI_GP1_BREADY = 1'b1; + assign S_AXI_GP1_ARADDR = 32'h0; + assign S_AXI_GP1_ARLEN = 8'h0; + assign S_AXI_GP1_ARSIZE = 3'h0; + assign S_AXI_GP1_ARBURST = 2'h0; + assign S_AXI_GP1_ARPROT = 3'h0; + assign S_AXI_GP1_ARCACHE = 4'h0; + assign S_AXI_GP1_ARVALID = 1'b0; + //S_AXI_GP1_ARREADY + //S_AXI_GP1_RDATA + //S_AXI_GP1_RRESP + //S_AXI_GP1_RLAST + //S_AXI_GP1_RVALID + assign S_AXI_GP1_RREADY = 1'b1; + + //S_AXI_HP0 from axi_eth_dma + assign S_AXI_HP1_ARADDR = 32'h0; + assign S_AXI_HP1_ARLEN = 8'h0; + assign S_AXI_HP1_ARSIZE = 3'h0; + assign S_AXI_HP1_ARBURST = 2'h0; + assign S_AXI_HP1_ARPROT = 3'h0; + assign S_AXI_HP1_ARCACHE = 4'h0; + assign S_AXI_HP1_ARVALID = 1'b0; + //S_AXI_HP1_ARREADY + //S_AXI_HP1_RDATA + //S_AXI_HP1_RRESP + //S_AXI_HP1_RLAST + //S_AXI_HP1_RVALID + assign S_AXI_HP1_RREADY = 1'b1; + assign S_AXI_HP1_AWADDR = 32'h0; + assign S_AXI_HP1_AWLEN = 8'h0; + assign S_AXI_HP1_AWSIZE = 3'h0; + assign S_AXI_HP1_AWBURST = 2'h0; + assign S_AXI_HP1_AWPROT = 3'h0; + assign S_AXI_HP1_AWCACHE = 4'h0; + assign S_AXI_HP1_AWVALID = 1'b0; + //S_AXI_HP1_AWREADY + assign S_AXI_HP1_WDATA = 64'h0; + assign S_AXI_HP1_WSTRB = 8'h0; + assign S_AXI_HP1_WLAST = 1'b0; + assign S_AXI_HP1_WVALID = 1'b0; + //S_AXI_HP1_WREADY + //S_AXI_HP1_BRESP + //S_AXI_HP1_BVALID + assign S_AXI_HP1_BREADY = 1'b1; + +`else + + axi_eth_dma inst_axi_eth_dma1 ( + .s_axi_lite_aclk(clk40), + .m_axi_sg_aclk(clk40), + .m_axi_mm2s_aclk(clk40), + .m_axi_s2mm_aclk(clk40), + .axi_resetn(clk40_rstn), + + .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), + .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), + .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), + + .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), + .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), + .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), + + .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), + .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), + .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), + + .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), + .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), + .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), + + .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), + .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), + .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), + .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), + + .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), + .m_axi_sg_awlen(S_AXI_GP1_AWLEN), + .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), + .m_axi_sg_awburst(S_AXI_GP1_AWBURST), + .m_axi_sg_awprot(S_AXI_GP1_AWPROT), + .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), + .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), + .m_axi_sg_awready(S_AXI_GP1_AWREADY), + .m_axi_sg_wdata(S_AXI_GP1_WDATA), + .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), + .m_axi_sg_wlast(S_AXI_GP1_WLAST), + .m_axi_sg_wvalid(S_AXI_GP1_WVALID), + .m_axi_sg_wready(S_AXI_GP1_WREADY), + .m_axi_sg_bresp(S_AXI_GP1_BRESP), + .m_axi_sg_bvalid(S_AXI_GP1_BVALID), + .m_axi_sg_bready(S_AXI_GP1_BREADY), + .m_axi_sg_araddr(S_AXI_GP1_ARADDR), + .m_axi_sg_arlen(S_AXI_GP1_ARLEN), + .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), + .m_axi_sg_arburst(S_AXI_GP1_ARBURST), + .m_axi_sg_arprot(S_AXI_GP1_ARPROT), + .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), + .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), + .m_axi_sg_arready(S_AXI_GP1_ARREADY), + .m_axi_sg_rdata(S_AXI_GP1_RDATA), + .m_axi_sg_rresp(S_AXI_GP1_RRESP), + .m_axi_sg_rlast(S_AXI_GP1_RLAST), + .m_axi_sg_rvalid(S_AXI_GP1_RVALID), + .m_axi_sg_rready(S_AXI_GP1_RREADY), + + .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), + .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), + .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), + .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), + .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), + .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), + .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), + .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), + .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), + .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), + .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), + .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), + .m_axi_mm2s_rready(S_AXI_HP1_RREADY), + + .mm2s_prmry_reset_out_n(), + .m_axis_mm2s_tdata(arm_eth1_tx_tdata), + .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), + .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), + .m_axis_mm2s_tready(arm_eth1_tx_tready), + .m_axis_mm2s_tlast(arm_eth1_tx_tlast), + + .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), + .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), + .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), + .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), + .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), + .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), + .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), + .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), + .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), + .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), + .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), + .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), + .m_axi_s2mm_wready(S_AXI_HP1_WREADY), + .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), + .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), + .m_axi_s2mm_bready(S_AXI_HP1_BREADY), + + .s2mm_prmry_reset_out_n(), + .s_axis_s2mm_tdata(arm_eth1_rx_tdata), + .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), + .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), + .s_axis_s2mm_tready(arm_eth1_rx_tready), + .s_axis_s2mm_tlast(arm_eth1_rx_tlast), + + .mm2s_introut(arm_eth1_tx_irq), + .s2mm_introut(arm_eth1_rx_irq), + .axi_dma_tstvec() + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_tx_1_fifo_2clk_i ( + .reset(clk40_rst), + .i_aclk(clk40), + .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), + .i_tvalid(arm_eth1_tx_tvalid), + .i_tready(arm_eth1_tx_tready), + .o_aclk(bus_clk), + .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), + .o_tvalid(arm_eth1_tx_tvalid_b), + .o_tready(arm_eth1_tx_tready_b) + ); + + axi_fifo_2clk #( + .WIDTH(1+8+64), + .SIZE(5) + ) eth_rx_1_fifo_2clk_i ( + .reset(bus_rst), + .i_aclk(bus_clk), + .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), + .i_tvalid(arm_eth1_rx_tvalid_b), + .i_tready(arm_eth1_rx_tready_b), + .o_aclk(clk40), + .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), + .o_tvalid(arm_eth1_rx_tvalid), + .o_tready(arm_eth1_rx_tready) + ); +`endif + + ///////////////////////////////////////////////////////////////////// + // + // Processing System + // + ////////////////////////////////////////////////////////////////////// + + wire spi0_sclk; + wire spi0_mosi; + wire spi0_miso; + wire spi0_ss0; + wire spi0_ss1; + wire spi0_ss2; + wire spi1_sclk; + wire spi1_mosi; + wire spi1_miso; + wire spi1_ss0; + wire spi1_ss1; + wire spi1_ss2; + + assign DBA_MODULE_PWR_ENABLE = ps_gpio_out[8]; + assign DBA_RF_PWR_ENABLE = ps_gpio_out[9]; + assign DBB_MODULE_PWR_ENABLE = ps_gpio_out[10]; + assign DBB_RF_PWR_ENABLE = ps_gpio_out[11]; + assign ps_gpio_in[8] = DBA_MODULE_PWR_ENABLE; + assign ps_gpio_in[9] = DBA_RF_PWR_ENABLE; + assign ps_gpio_in[10] = DBB_MODULE_PWR_ENABLE; + assign ps_gpio_in[11] = DBB_RF_PWR_ENABLE; + + // Processing System + n310_ps_bd inst_n310_ps ( + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(spi0_sclk), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(spi0_mosi), + .SPI0_MOSI_T(), + .SPI0_MISO_I(spi0_miso), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'b1), + .SPI0_SS_O(spi0_ss0), + .SPI0_SS1_O(spi0_ss1), + .SPI0_SS2_O(spi0_ss2), + .SPI0_SS_T(), + + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(spi1_sclk), + .SPI1_SCLK_T(), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(spi1_mosi), + .SPI1_MOSI_T(), + .SPI1_MISO_I(spi1_miso), + .SPI1_MISO_O(), + .SPI1_MISO_T(), + .SPI1_SS_I(1'b1), + .SPI1_SS_O(spi1_ss0), + .SPI1_SS1_O(spi1_ss1), + .SPI1_SS2_O(spi1_ss2), + .SPI1_SS_T(), + + .bus_clk(bus_clk), + .bus_rstn(~bus_rst), + .clk40(clk40), + .clk40_rstn(clk40_rstn), + + .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), + .M_AXI_ETH_DMA0_arprot(), + .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), + .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), + + .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), + .M_AXI_ETH_DMA0_awprot(), + .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), + .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), + + .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), + .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), + .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), + .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), + + .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), + .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), + .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), + .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), + + .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), + .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), + .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), + + .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), + .M_AXI_ETH_DMA1_arprot(), + .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), + .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), + + .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), + .M_AXI_ETH_DMA1_awprot(), + .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), + .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), + + .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), + .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), + .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), + + .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), + .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), + .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), + .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), + + .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), + .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), + .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), + .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), + + .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), + .M_AXI_JESD0_arprot(), + .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), + .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), + + .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), + .M_AXI_JESD0_awprot(), + .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), + .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), + + .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), + .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), + .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), + + .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), + .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), + .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), + .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), + + .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), + .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), + .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), + .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), + + .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), + .M_AXI_JESD1_arprot(), + .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), + .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), + + .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), + .M_AXI_JESD1_awprot(), + .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), + .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), + + .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), + .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), + .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), + + .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), + .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), + .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), + .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), + + .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), + .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), + .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), + .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), + + .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), + .M_AXI_NET0_arprot(), + .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), + .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), + + .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), + .M_AXI_NET0_awprot(), + .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), + .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), + + .M_AXI_NET0_bready(M_AXI_NET0_BREADY), + .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), + .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), + + .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), + .M_AXI_NET0_rready(M_AXI_NET0_RREADY), + .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), + .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), + + .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), + .M_AXI_NET0_wready(M_AXI_NET0_WREADY), + .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), + .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), + + .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), + .M_AXI_NET1_arprot(), + .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), + .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), + + .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), + .M_AXI_NET1_awprot(), + .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), + .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), + + .M_AXI_NET1_bready(M_AXI_NET1_BREADY), + .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), + .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), + + .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), + .M_AXI_NET1_rready(M_AXI_NET1_RREADY), + .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), + .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), + + .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), + .M_AXI_NET1_wready(M_AXI_NET1_WREADY), + .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), + .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), + + .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), + .M_AXI_NET2_arprot(), + .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), + .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), + + .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), + .M_AXI_NET2_awprot(), + .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), + .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), + + .M_AXI_NET2_bready(M_AXI_NET2_BREADY), + .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), + .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), + + .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), + .M_AXI_NET2_rready(M_AXI_NET2_RREADY), + .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), + .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), + + .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), + .M_AXI_NET2_wready(M_AXI_NET2_WREADY), + .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), + .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), + + .M_AXI_WR_CLK(m_axi_wr_clk), + .M_AXI_WR_RSTn(1'b1), + .M_AXI_WR_araddr(m_axi_wr_araddr), + .M_AXI_WR_arready(m_axi_wr_arready), + .M_AXI_WR_arvalid(m_axi_wr_arvalid), + .M_AXI_WR_arprot(), + .M_AXI_WR_awaddr(m_axi_wr_awaddr), + .M_AXI_WR_awready(m_axi_wr_awready), + .M_AXI_WR_awvalid(m_axi_wr_awvalid), + .M_AXI_WR_awprot(), + .M_AXI_WR_bready(m_axi_wr_bready), + .M_AXI_WR_bresp(m_axi_wr_bresp), + .M_AXI_WR_bvalid(m_axi_wr_bvalid), + .M_AXI_WR_rdata(m_axi_wr_rdata), + .M_AXI_WR_rready(m_axi_wr_rready), + .M_AXI_WR_rresp(m_axi_wr_rresp), + .M_AXI_WR_rvalid(m_axi_wr_rvalid), + .M_AXI_WR_wdata(m_axi_wr_wdata), + .M_AXI_WR_wready(m_axi_wr_wready), + .M_AXI_WR_wstrb(m_axi_wr_wstrb), + .M_AXI_WR_wvalid(m_axi_wr_wvalid), + + .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), + .M_AXI_XBAR_arprot(), + .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), + .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), + + .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), + .M_AXI_XBAR_awprot(), + .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), + .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), + + .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), + .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), + .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), + + .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), + .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), + .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), + .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), + + .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), + .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), + .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), + .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), + + .S_AXI_GP0_ACLK(clk40), + .S_AXI_GP0_ARESETN(clk40_rstn), + .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), + .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), + .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), + .S_AXI_GP0_arid(S_AXI_GP0_ARID), + .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), + .S_AXI_GP0_arlock(1'b0), + .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), + .S_AXI_GP0_arqos(4'b0000), + .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), + .S_AXI_GP0_arregion(4'b0000), + .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), + .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), + .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), + .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), + .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), + .S_AXI_GP0_awid(S_AXI_GP0_AWID), + .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), + .S_AXI_GP0_awlock(1'b0), + .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), + .S_AXI_GP0_awqos(4'b0000), + .S_AXI_GP0_awregion(4'b0000), + .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), + .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), + .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), + .S_AXI_GP0_bid(), + .S_AXI_GP0_bready(S_AXI_GP0_BREADY), + .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), + .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), + .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), + .S_AXI_GP0_rid(), + .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), + .S_AXI_GP0_rready(S_AXI_GP0_RREADY), + .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), + .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), + .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), + .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), + .S_AXI_GP0_wready(S_AXI_GP0_WREADY), + .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), + .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), + + .S_AXI_GP1_ACLK(clk40), + .S_AXI_GP1_ARESETN(clk40_rstn), + .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), + .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), + .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), + .S_AXI_GP1_arid(S_AXI_GP1_ARID), + .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), + .S_AXI_GP1_arlock(1'b0), + .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), + .S_AXI_GP1_arqos(4'b000), + .S_AXI_GP1_arregion(4'b0000), + .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), + .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), + .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), + .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), + .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), + .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), + .S_AXI_GP1_awid(S_AXI_GP1_AWID), + .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), + .S_AXI_GP1_awlock(1'b0), + .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), + .S_AXI_GP1_awqos(4'b0000), + .S_AXI_GP1_awregion(4'b0000), + .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), + .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), + .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), + .S_AXI_GP1_bid(), + .S_AXI_GP1_bready(S_AXI_GP1_BREADY), + .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), + .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), + .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), + .S_AXI_GP1_rid(), + .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), + .S_AXI_GP1_rready(S_AXI_GP1_RREADY), + .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), + .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), + .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), + .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), + .S_AXI_GP1_wready(S_AXI_GP1_WREADY), + .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), + .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), + + .S_AXI_HP0_ACLK(clk40), + .S_AXI_HP0_ARESETN(clk40_rstn), + .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), + .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), + .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_arid(S_AXI_HP0_ARID), + .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), + .S_AXI_HP0_arlock(1'b0), + .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), + .S_AXI_HP0_arqos(4'b0000), + .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), + .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), + .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), + .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), + .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_awid(S_AXI_HP0_AWID), + .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), + .S_AXI_HP0_awlock(1'b0), + .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), + .S_AXI_HP0_awqos(4'b0000), + .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), + .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), + .S_AXI_HP0_bid(), + .S_AXI_HP0_bready(S_AXI_HP0_BREADY), + .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), + .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), + .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), + .S_AXI_HP0_rid(), + .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), + .S_AXI_HP0_rready(S_AXI_HP0_RREADY), + .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), + .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), + .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), + .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), + .S_AXI_HP0_wready(S_AXI_HP0_WREADY), + .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), + .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), + + .S_AXI_HP1_ACLK(clk40), + .S_AXI_HP1_ARESETN(clk40_rstn), + .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), + .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), + .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), + .S_AXI_HP1_arid(S_AXI_HP1_ARID), + .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), + .S_AXI_HP1_arlock(1'b0), + .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), + .S_AXI_HP1_arqos(4'b0000), + .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), + .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), + .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), + .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), + .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), + .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), + .S_AXI_HP1_awid(S_AXI_HP1_AWID), + .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), + .S_AXI_HP1_awlock(1'b0), + .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), + .S_AXI_HP1_awqos(4'b0000), + .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), + .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), + .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), + .S_AXI_HP1_bid(), + .S_AXI_HP1_bready(S_AXI_HP1_BREADY), + .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), + .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), + .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), + .S_AXI_HP1_rid(), + .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), + .S_AXI_HP1_rready(S_AXI_HP1_RREADY), + .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), + .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), + .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), + .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), + .S_AXI_HP1_wready(S_AXI_HP1_WREADY), + .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), + .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), + + // ARM DMA + .s_axis_dma_tdata(s_axis_dma_tdata), + .s_axis_dma_tdest(s_axis_dma_tdest), + .s_axis_dma_tlast(s_axis_dma_tlast), + .s_axis_dma_tready(s_axis_dma_tready), + .s_axis_dma_tvalid(s_axis_dma_tvalid), + .m_axis_dma_tdata(m_axis_dma_tdata), + .m_axis_dma_tuser(m_axis_dma_tuser), + .m_axis_dma_tlast(m_axis_dma_tlast), + .m_axis_dma_tready(m_axis_dma_tready), + .m_axis_dma_tvalid(m_axis_dma_tvalid), + + // Misc Interrupts, GPIO, clk + .IRQ_F2P(IRQ_F2P), + + .GPIO_0_tri_i(ps_gpio_in), + .GPIO_0_tri_o(ps_gpio_out), + .GPIO_0_tri_t(ps_gpio_tri), + + .JTAG0_TCK(DBA_CPLD_JTAG_TCK), + .JTAG0_TMS(DBA_CPLD_JTAG_TMS), + .JTAG0_TDI(DBA_CPLD_JTAG_TDI), + .JTAG0_TDO(DBA_CPLD_JTAG_TDO), + + .JTAG1_TCK(DBB_CPLD_JTAG_TCK), + .JTAG1_TMS(DBB_CPLD_JTAG_TMS), + .JTAG1_TDI(DBB_CPLD_JTAG_TDI), + .JTAG1_TDO(DBB_CPLD_JTAG_TDO), + + .FCLK_CLK0(FCLK_CLK0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_RESET1_N(), + .FCLK_CLK2(FCLK_CLK2), + .FCLK_RESET2_N(), + .FCLK_CLK3(FCLK_CLK3), + .FCLK_RESET3_N(), + + .WR_UART_txd(wr_uart_rxd), // rx <-> tx + .WR_UART_rxd(wr_uart_txd), // rx <-> tx + + .qsfp_sda_i(qsfp_sda_i), + .qsfp_sda_o(qsfp_sda_o), + .qsfp_sda_t(qsfp_sda_t), + .qsfp_scl_i(qsfp_scl_i), + .qsfp_scl_o(qsfp_scl_o), + .qsfp_scl_t(qsfp_scl_t), + + .USBIND_0_port_indctl(), + .USBIND_0_vbus_pwrfault(), + .USBIND_0_vbus_pwrselect(), + + // Outward connections to the pins + .MIO(MIO), + .DDR_cas_n(DDR_CAS_n), + .DDR_cke(DDR_CKE), + .DDR_ck_n(DDR_Clk_n), + .DDR_ck_p(DDR_Clk), + .DDR_cs_n(DDR_CS_n), + .DDR_reset_n(DDR_DRSTB), + .DDR_odt(DDR_ODT), + .DDR_ras_n(DDR_RAS_n), + .DDR_we_n(DDR_WEB), + .DDR_ba(DDR_BankAddr), + .DDR_addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_dm(DDR_DM), + .DDR_dq(DDR_DQ), + .DDR_dqs_n(DDR_DQS_n), + .DDR_dqs_p(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire [3:0] ddr3_axi_awid; + wire [31:0] ddr3_axi_awaddr; + wire [7:0] ddr3_axi_awlen; + wire [2:0] ddr3_axi_awsize; + wire [1:0] ddr3_axi_awburst; + wire [0:0] ddr3_axi_awlock; + wire [3:0] ddr3_axi_awcache; + wire [2:0] ddr3_axi_awprot; + wire [3:0] ddr3_axi_awqos; + wire ddr3_axi_awvalid; + wire ddr3_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] ddr3_axi_wdata; + wire [31:0] ddr3_axi_wstrb; + wire ddr3_axi_wlast; + wire ddr3_axi_wvalid; + wire ddr3_axi_wready; + // Slave Interface Write Response Ports + wire ddr3_axi_bready; + wire [3:0] ddr3_axi_bid; + wire [1:0] ddr3_axi_bresp; + wire ddr3_axi_bvalid; + // Slave Interface Read Address Ports + wire [3:0] ddr3_axi_arid; + wire [31:0] ddr3_axi_araddr; + wire [7:0] ddr3_axi_arlen; + wire [2:0] ddr3_axi_arsize; + wire [1:0] ddr3_axi_arburst; + wire [0:0] ddr3_axi_arlock; + wire [3:0] ddr3_axi_arcache; + wire [2:0] ddr3_axi_arprot; + wire [3:0] ddr3_axi_arqos; + wire ddr3_axi_arvalid; + wire ddr3_axi_arready; + // Slave Interface Read Data Ports + wire ddr3_axi_rready; + wire [3:0] ddr3_axi_rid; + wire [255:0] ddr3_axi_rdata; + wire [1:0] ddr3_axi_rresp; + wire ddr3_axi_rlast; + wire ddr3_axi_rvalid; + + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + + // Instantiate the DDR3 MIG core + // + // The top-level IP block has no parameters defined for some reason. + // Most of configurable parameters are hard-coded in the mig so get + // some additional knobs we pull those out into verilog headers. + // + // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh + // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh + + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 200Hz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + // Slave Interface Write Address Ports + .s_axi_awid (ddr3_axi_awid), + .s_axi_awaddr (ddr3_axi_awaddr), + .s_axi_awlen (ddr3_axi_awlen), + .s_axi_awsize (ddr3_axi_awsize), + .s_axi_awburst (ddr3_axi_awburst), + .s_axi_awlock (ddr3_axi_awlock), + .s_axi_awcache (ddr3_axi_awcache), + .s_axi_awprot (ddr3_axi_awprot), + .s_axi_awqos (ddr3_axi_awqos), + .s_axi_awvalid (ddr3_axi_awvalid), + .s_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (ddr3_axi_wdata), + .s_axi_wstrb (ddr3_axi_wstrb), + .s_axi_wlast (ddr3_axi_wlast), + .s_axi_wvalid (ddr3_axi_wvalid), + .s_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (ddr3_axi_bid), + .s_axi_bresp (ddr3_axi_bresp), + .s_axi_bvalid (ddr3_axi_bvalid), + .s_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (ddr3_axi_arid), + .s_axi_araddr (ddr3_axi_araddr), + .s_axi_arlen (ddr3_axi_arlen), + .s_axi_arsize (ddr3_axi_arsize), + .s_axi_arburst (ddr3_axi_arburst), + .s_axi_arlock (ddr3_axi_arlock), + .s_axi_arcache (ddr3_axi_arcache), + .s_axi_arprot (ddr3_axi_arprot), + .s_axi_arqos (ddr3_axi_arqos), + .s_axi_arvalid (ddr3_axi_arvalid), + .s_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (ddr3_axi_rid), + .s_axi_rdata (ddr3_axi_rdata), + .s_axi_rresp (ddr3_axi_rresp), + .s_axi_rlast (ddr3_axi_rlast), + .s_axi_rvalid (ddr3_axi_rvalid), + .s_axi_rready (ddr3_axi_rready), + // System Clock Ports + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .clk_ref_i (bus_clk), + + .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), + .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + /////////////////////////////////////////////////////// + // + // DB PS SPI Connections + // + /////////////////////////////////////////////////////// + wire [NUM_CHANNELS-1:0] rx_atr; + wire [NUM_CHANNELS-1:0] tx_atr; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; + (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; + + // Radio GPIO control for DSA + wire [16*NUM_CHANNELS-1:0] db_gpio_out; + wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; + wire [16*NUM_CHANNELS-1:0] db_gpio_in; + wire [16*NUM_CHANNELS-1:0] db_gpio_fab; + + // DB A SPI Connections + assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; + assign DBA_CPLD_PS_SPI_MOSI = spi0_mosi; + + // Assign individual chip selects from PS SPI MASTER 0. + assign DBA_CPLD_PS_SPI_CS_B = spi0_ss0; + assign DBA_CLKDIS_SPI_CS_B = spi0_ss1; + assign DBA_PHDAC_SPI_CS_B = spi0_ss2; + assign DBA_ADC_SPI_CS_B = ps_gpio_out[13]; + assign DBA_DAC_SPI_CS_B = ps_gpio_out[14]; + + // Returned data mux from the SPI interfaces. + assign spi0_miso = DBA_CPLD_PS_SPI_MISO; + + // TODO: How to control? + assign DBA_ATR_RX = rx_atr_reg[0]; + assign DBA_ATR_TX = tx_atr_reg[0]; + assign DBA_TXRX_SW_CTRL_1 = db_gpio_out[16*0+0]; + assign DBA_TXRX_SW_CTRL_2 = db_gpio_out[16*0+1]; + assign DBA_LED_RX = db_gpio_out[16*0+2]; + assign DBA_LED_RX2 = db_gpio_out[16*0+3]; + assign DBA_LED_TX = db_gpio_out[16*0+4]; + + // DB B SPI Connections + assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; + assign DBB_CPLD_PS_SPI_MOSI = spi1_mosi; + + // Assign individual chip selects from PS SPI MASTER 1. + assign DBB_CPLD_PS_SPI_CS_B = spi1_ss0; + assign DBB_CLKDIS_SPI_CS_B = spi1_ss1; + assign DBB_PHDAC_SPI_CS_B = spi1_ss2; + assign DBB_ADC_SPI_CS_B = ps_gpio_out[15]; + assign DBB_DAC_SPI_CS_B = ps_gpio_out[16]; + + // Returned data mux from the SPI interfaces. + assign spi1_miso = DBB_CPLD_PS_SPI_MISO; + + + // TODO: How to control? + assign DBB_ATR_RX = rx_atr_reg[1]; + assign DBB_ATR_TX = tx_atr_reg[1]; + assign DBB_TXRX_SW_CTRL_1 = db_gpio_out[16*1+0]; + assign DBB_TXRX_SW_CTRL_2 = db_gpio_out[16*1+1]; + assign DBB_LED_RX = db_gpio_out[16*1+2]; + assign DBB_LED_RX2 = db_gpio_out[16*1+3]; + assign DBB_LED_TX = db_gpio_out[16*1+4]; + + + /////////////////////////////////////////////////////// + // + // N320 CORE + // + /////////////////////////////////////////////////////// + + wire [CHANNEL_WIDTH-1:0] rx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx_db[2*NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] rx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH-1:0] tx[NUM_CHANNELS-1:0]; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx_flat; + wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx_flat; + wire [47:0] rx_hb[NUM_CHANNELS-1:0]; + wire [95:0] tx_hb[NUM_CHANNELS-1:0]; + + wire [NUM_CHANNELS-1:0] rx_stb; + wire [NUM_CHANNELS-1:0] tx_stb; + + wire [31:0] build_datestamp; + + /* 2:1 and 1:2 filters to bring sample rates down + */ + genvar i; + generate for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + hb47_1to2 tx_1to2 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(tx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata(tx[i]), + .m_axis_data_tvalid(), + .m_axis_data_tready(tx_stb[i]), + .m_axis_data_tdata(tx_hb[i]) + ); + + assign tx_db[2*i] = {tx_hb[i][39:24], tx_hb[i][15:0]}; + assign tx_db[2*i+1] = {tx_hb[i][87:72], tx_hb[i][63:48]}; + + hb47_2to1 rx_2to1 ( + .aresetn(!radio_rst), + .aclk(radio_clk), + .s_axis_data_tvalid(rx_stb[i]), + .s_axis_data_tready(), + .s_axis_data_tdata({rx_db[2*i+1], rx_db[2*i]}), + .m_axis_data_tvalid(), + .m_axis_data_tdata(rx_hb[i]) + ); + + assign rx[i] = {rx_hb[i][39:24], rx_hb[i][15:0]}; + end endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = rx[i]; + assign tx[i] = tx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; + end + endgenerate + + USR_ACCESSE2 usr_access_i ( + .DATA(build_datestamp), .CFGCLK(), .DATAVALID() + ); + + n3xx_core #( + .REG_AWIDTH(14), + .BUS_CLK_RATE(BUS_CLK_RATE), + .FP_GPIO_WIDTH(FP_GPIO_WIDTH), + .CHANNEL_WIDTH(CHANNEL_WIDTH), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS), + .NUM_DBOARDS(NUM_DBOARDS), + .NUM_SPI_PER_DBOARD(4), + .USE_CORRECTION(1), + `ifdef USE_REPLAY + .USE_REPLAY(1) + `else + .USE_REPLAY(0) + `endif + ) n3xx_core( + // Clocks and resets +`ifdef NO_DB + .radio_clk(bus_clk), + .radio_rst(bus_rst), +`else + .radio_clk(radio_clk), + .radio_rst(radio_rst), +`endif + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .ddr3_dma_clk(ddr3_dma_clk), + .clk40(clk40), + + // Clocking and PPS Controls/Indicators + .pps(pps_radioclk1x), + .pps_select(pps_select), + .pps_out_enb(pps_out_enb), + .pps_select_sfp(pps_select_sfp), + .ref_clk_reset(), + .meas_clk_reset(meas_clk_reset), + .ref_clk_locked(1'b1), + .meas_clk_locked(meas_clk_locked), + .enable_ref_clk_async(enable_ref_clk_async), + + .s_axi_aclk(clk40), + .s_axi_aresetn(clk40_rstn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_XBAR_AWADDR), + .s_axi_awvalid(M_AXI_XBAR_AWVALID), + .s_axi_awready(M_AXI_XBAR_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_XBAR_WDATA), + .s_axi_wstrb(M_AXI_XBAR_WSTRB), + .s_axi_wvalid(M_AXI_XBAR_WVALID), + .s_axi_wready(M_AXI_XBAR_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_XBAR_BRESP), + .s_axi_bvalid(M_AXI_XBAR_BVALID), + .s_axi_bready(M_AXI_XBAR_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_XBAR_ARADDR), + .s_axi_arvalid(M_AXI_XBAR_ARVALID), + .s_axi_arready(M_AXI_XBAR_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_XBAR_RDATA), + .s_axi_rresp(M_AXI_XBAR_RRESP), + .s_axi_rvalid(M_AXI_XBAR_RVALID), + .s_axi_rready(M_AXI_XBAR_RREADY), + // ps gpio source + .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), + // FP_GPIO + .fp_gpio_inout(FPGA_GPIO), + // Radio ATR + .rx_atr(rx_atr), + .tx_atr(tx_atr), + // Radio GPIO DSA + .db_gpio_out_flat(db_gpio_out), + .db_gpio_in_flat(db_gpio_in), + .db_gpio_ddr_flat(db_gpio_ddr), + .db_gpio_fab_flat(db_gpio_fab), + // Radio Strobes + .rx_stb(rx_stb), + .tx_stb(tx_stb), + // Radio Data + .rx(rx_flat), + .tx(tx_flat), + //cpld rx_lo tx_lo spi + .sclk_flat({DBB_CPLD_PL_SPI_SCLK, + DBA_CPLD_PL_SPI_SCLK}), + .sen_flat({DBB_CPLD_PL_SPI_CS_B,DBB_LODIS_SPI_CS_B,DBB_RXLO_SPI_CS_B,DBB_TXLO_SPI_CS_B, + DBA_CPLD_PL_SPI_CS_B,DBA_LODIS_SPI_CS_B,DBA_RXLO_SPI_CS_B,DBA_TXLO_SPI_CS_B}), + .mosi_flat({DBB_CPLD_PL_SPI_MOSI, + DBA_CPLD_PL_SPI_MOSI}), + .miso_flat({DBB_CPLD_PL_SPI_MISO, + DBA_CPLD_PL_SPI_MISO}), + // DRAM signals. + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_rst (ddr3_axi_rst), + .ddr3_running (ddr3_running), + // Slave Interface Write Address Ports + .ddr3_axi_awid (ddr3_axi_awid), + .ddr3_axi_awaddr (ddr3_axi_awaddr), + .ddr3_axi_awlen (ddr3_axi_awlen), + .ddr3_axi_awsize (ddr3_axi_awsize), + .ddr3_axi_awburst (ddr3_axi_awburst), + .ddr3_axi_awlock (ddr3_axi_awlock), + .ddr3_axi_awcache (ddr3_axi_awcache), + .ddr3_axi_awprot (ddr3_axi_awprot), + .ddr3_axi_awqos (ddr3_axi_awqos), + .ddr3_axi_awvalid (ddr3_axi_awvalid), + .ddr3_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (ddr3_axi_wdata), + .ddr3_axi_wstrb (ddr3_axi_wstrb), + .ddr3_axi_wlast (ddr3_axi_wlast), + .ddr3_axi_wvalid (ddr3_axi_wvalid), + .ddr3_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (ddr3_axi_bid), + .ddr3_axi_bresp (ddr3_axi_bresp), + .ddr3_axi_bvalid (ddr3_axi_bvalid), + .ddr3_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (ddr3_axi_arid), + .ddr3_axi_araddr (ddr3_axi_araddr), + .ddr3_axi_arlen (ddr3_axi_arlen), + .ddr3_axi_arsize (ddr3_axi_arsize), + .ddr3_axi_arburst (ddr3_axi_arburst), + .ddr3_axi_arlock (ddr3_axi_arlock), + .ddr3_axi_arcache (ddr3_axi_arcache), + .ddr3_axi_arprot (ddr3_axi_arprot), + .ddr3_axi_arqos (ddr3_axi_arqos), + .ddr3_axi_arvalid (ddr3_axi_arvalid), + .ddr3_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (ddr3_axi_rid), + .ddr3_axi_rdata (ddr3_axi_rdata), + .ddr3_axi_rresp (ddr3_axi_rresp), + .ddr3_axi_rlast (ddr3_axi_rlast), + .ddr3_axi_rvalid (ddr3_axi_rvalid), + .ddr3_axi_rready (ddr3_axi_rready), + + // DMA to PS + .m_dma_tdata(s_axis_dma_tdata), + .m_dma_tdest(s_axis_dma_tdest), + .m_dma_tlast(s_axis_dma_tlast), + .m_dma_tready(s_axis_dma_tready), + .m_dma_tvalid(s_axis_dma_tvalid), + + .s_dma_tdata(m_axis_dma_tdata), + .s_dma_tuser(m_axis_dma_tuser), + .s_dma_tlast(m_axis_dma_tlast), + .s_dma_tready(m_axis_dma_tready), + .s_dma_tvalid(m_axis_dma_tvalid), + + // VITA to Ethernet + .v2e0_tdata(v2e0_tdata), + .v2e0_tvalid(v2e0_tvalid), + .v2e0_tlast(v2e0_tlast), + .v2e0_tready(v2e0_tready), + + .v2e1_tdata(v2e1_tdata), + .v2e1_tlast(v2e1_tlast), + .v2e1_tvalid(v2e1_tvalid), + .v2e1_tready(v2e1_tready), + + // Ethernet to VITA + .e2v0_tdata(e2v0_tdata), + .e2v0_tlast(e2v0_tlast), + .e2v0_tvalid(e2v0_tvalid), + .e2v0_tready(e2v0_tready), + + .e2v1_tdata(e2v1_tdata), + .e2v1_tlast(e2v1_tlast), + .e2v1_tvalid(e2v1_tvalid), + .e2v1_tready(e2v1_tready), + + //regport interface to npio + .reg_wr_req_npio(reg_wr_req_npio), + .reg_wr_addr_npio(reg_wr_addr_npio), + .reg_wr_data_npio(reg_wr_data_npio), + .reg_rd_req_npio(reg_rd_req_npio), + .reg_rd_addr_npio(reg_rd_addr_npio), + .reg_rd_resp_npio(reg_rd_resp_npio), + .reg_rd_data_npio(reg_rd_data_npio), + + .build_datestamp(build_datestamp), + .xadc_readback({20'h0, device_temp}), + .sfp_ports_info({sfp_port1_info, sfp_port0_info}), + .device_id(device_id) + ); + + // Register the ATR bits once between sending them out to the CPLD to avoid + // glitches on the outputs! + always @(posedge radio_clk) begin + rx_atr_reg <= rx_atr; + tx_atr_reg <= tx_atr; + end + + // ////////////////////////////////////////////////////////////////////// + // + // Daughterboard Cores + // + // ////////////////////////////////////////////////////////////////////// + + wire sAdcSyncUnusedA; + wire sAdcSyncUnusedB; + wire sDacSyncUnusedA; + wire sDacSyncUnusedB; + wire sSysrefUnusedA; + wire sSysrefUnusedB; + wire rRpTransferUnusedA; + wire rRpTransferUnusedB; + wire sSpTransferUnusedA; + wire sSpTransferUnusedB; + wire rWrRpTransferUnusedA; + wire rWrRpTransferUnusedB; + wire sWrSpTransferUnusedA; + wire sWrSpTransferUnusedB; + wire sPpsUnusedB; + wire sPpsToIobUnusedB; + + wire dba_adc_sync_b; + wire dba_dac_sync_b; + wire dba_dac_sync_b_n; // This is the swapped version coming from the IBUFDS. + wire dbb_adc_sync_b; + wire dbb_dac_sync_b; + + wire [49:0] bRegPortInFlatA; + wire [49:0] bRegPortInFlatB; + wire [33:0] bRegPortOutFlatA; + wire [33:0] bRegPortOutFlatB; + + wire rx_a_valid; + wire rx_b_valid; + wire tx_a_rfi; + wire tx_b_rfi; + +`ifdef BUILD_WR + localparam INCL_WR_TDC = 1'b1; +`else + localparam INCL_WR_TDC = 1'b0; +`endif + + wire reg_portA_rd; + wire reg_portA_wr; + wire [14-1:0] reg_portA_addr; + wire [32-1:0] reg_portA_wr_data; + wire [32-1:0] reg_portA_rd_data; + wire reg_portA_ready; + wire validA_unused; + + OBUFDS dba_adc_sync_buf( + .O(DBA_ADC_SYNCB_P), + .OB(DBA_ADC_SYNCB_N), + .I(dba_adc_sync_b) + ); + + IBUFDS dba_dac_sync_buf( + .I(DBA_DAC_SYNCB_P), + .IB(DBA_DAC_SYNCB_N), + .O(dba_dac_sync_b_n) + ); + + // The differential signals are swapped in the pins, so the SYNC signal + // must be negated after the IBUFDS. + assign dba_dac_sync_b = ~ dba_dac_sync_b_n; + + OBUFDS dbb_adc_sync_buf( + .O(DBB_ADC_SYNCB_P), + .OB(DBB_ADC_SYNCB_N), + .I(dbb_adc_sync_b) + ); + + IBUFDS dbb_dac_sync_buf( + .I(DBB_DAC_SYNCB_P), + .IB(DBB_DAC_SYNCB_N), + .O(dbb_dac_sync_b) + ); + + + assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; + assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dba_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clk), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2x), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) + .kSlotId(1'b0), //in std_logic + .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBA_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBA_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBA_MGTCLK_N), //in std_logic + .aAdcRx_p(DBA_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBA_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dba_adc_sync_b), //out std_logic + .aDacTx_p(DBA_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBA_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dba_dac_sync_b), //in std_logic + .sAdcDataValid(rx_a_valid), //out std_logic + .sAdcDataSample0I(rx_db[0][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[0][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[1][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[1][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_a_rfi), //out std_logic + .sDacDataSample0I(tx_db[0][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[0][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[1][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[1][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic + .sPps(pps_radioclk1x), //out std_logic + .sPpsToIob(pps_radioclk1x_iob), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic + .aPpsSfpSel(pps_select_sfp), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedA), //out std_logic + .sDacSync(sDacSyncUnusedA), //out std_logic + .sSysRef(sSysrefUnusedA), //out std_logic + .rRpTransfer(rRpTransferUnusedA), //out std_logic + .sSpTransfer(sSpTransferUnusedA), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedA), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedA)); //out std_logic + + + + assign rx_stb[0] = rx_a_valid; + assign tx_stb[0] = tx_a_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportA_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD0_AWADDR), + .s_axi_awvalid(M_AXI_JESD0_AWVALID), + .s_axi_awready(M_AXI_JESD0_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD0_WDATA), + .s_axi_wstrb(M_AXI_JESD0_WSTRB), + .s_axi_wvalid(M_AXI_JESD0_WVALID), + .s_axi_wready(M_AXI_JESD0_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD0_BRESP), + .s_axi_bvalid(M_AXI_JESD0_BVALID), + .s_axi_bready(M_AXI_JESD0_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD0_ARADDR), + .s_axi_arvalid(M_AXI_JESD0_ARVALID), + .s_axi_arready(M_AXI_JESD0_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata(M_AXI_JESD0_RDATA), + .s_axi_rresp(M_AXI_JESD0_RRESP), + .s_axi_rvalid(M_AXI_JESD0_RVALID), + .s_axi_rready(M_AXI_JESD0_RREADY), + // Register port + .reg_port_in_rd (reg_portA_rd), + .reg_port_in_wt (reg_portA_wr), + .reg_port_in_addr (reg_portA_addr), + .reg_port_in_data (reg_portA_wr_data), + .reg_port_out_data (reg_portA_rd_data), + .reg_port_out_ready(reg_portA_ready) + ); + + wire reg_portB_rd; + wire reg_portB_wr; + wire [14-1:0] reg_portB_addr; + wire [32-1:0] reg_portB_wr_data; + wire [32-1:0] reg_portB_rd_data; + wire reg_portB_ready; + wire validB_unused; + + assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; + assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; + + DbCore + # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' + dbb_core ( + .bBusReset(clk40_rst), //in std_logic + .BusClk(clk40), //in std_logic + .Clk40(clk40), //in std_logic + .MeasClk(meas_clk), //in std_logic + .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic + .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic + .SampleClk1xOut(radio_clkB), //out std_logic + .SampleClk1x(radio_clk), //in std_logic + .SampleClk2xOut(radio_clk_2xB), //out std_logic + .SampleClk2x(radio_clk_2x), //in std_logic + .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) + .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) + .kSlotId(1'b1), //in std_logic + .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic + .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic + .aLmkSync(DBB_CLKDIST_SYNC), //out std_logic + .JesdRefClk_p(DBB_MGTCLK_P), //in std_logic + .JesdRefClk_n(DBB_MGTCLK_N), //in std_logic + .aAdcRx_p(DBB_RX_P), //in std_logic_vector(3:0) + .aAdcRx_n(DBB_RX_N), //in std_logic_vector(3:0) + .aSyncAdcOut_n(dbb_adc_sync_b), //out std_logic + .aDacTx_p(DBB_TX_P), //out std_logic_vector(3:0) + .aDacTx_n(DBB_TX_N), //out std_logic_vector(3:0) + .aSyncDacIn_n(dbb_dac_sync_b), //in std_logic + .sAdcDataValid(rx_b_valid), //out std_logic + .sAdcDataSample0I(rx_db[2][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample0Q(rx_db[2][15: 0]), //out std_logic_vector(15:0) + .sAdcDataSample1I(rx_db[3][31:16]), //out std_logic_vector(15:0) + .sAdcDataSample1Q(rx_db[3][15: 0]), //out std_logic_vector(15:0) + .sDacReadyForInput(tx_b_rfi), //out std_logic + .sDacDataSample0I(tx_db[2][31:16]), //in std_logic_vector(15:0) + .sDacDataSample0Q(tx_db[2][15: 0]), //in std_logic_vector(15:0) + .sDacDataSample1I(tx_db[3][31:16]), //in std_logic_vector(15:0) + .sDacDataSample1Q(tx_db[3][15: 0]), //in std_logic_vector(15:0) + .RefClk(ref_clk), //in std_logic + .rPpsPulse(pps_refclk), //in std_logic + .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic + .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic + .sPps(sPpsUnusedB), //out std_logic + .sPpsToIob(sPpsToIobUnusedB), //out std_logic + .WrRefClk(wr_ref_clk), //in std_logic + .rWrPpsPulse(pps_wr_refclk), //in std_logic + .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic + .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic + .aPpsSfpSel(2'd0), //in std_logic_vector(1:0) + .sAdcSync(sAdcSyncUnusedB), //out std_logic + .sDacSync(sDacSyncUnusedB), //out std_logic + .sSysRef(sSysrefUnusedB), //out std_logic + .rRpTransfer(rRpTransferUnusedB), //out std_logic + .sSpTransfer(sSpTransferUnusedB), //out std_logic + .rWrRpTransfer(rWrRpTransferUnusedB), //out std_logic + .sWrSpTransfer(sWrSpTransferUnusedB)); //out std_logic + + + + assign rx_stb[1] = rx_b_valid; + assign tx_stb[1] = tx_b_rfi; + + axil_to_ni_regport #( + .RP_DWIDTH (32), + .RP_AWIDTH (14), + .TIMEOUT (512) + ) ni_regportB_inst ( + // Clock and reset + .s_axi_aclk (clk40), + .s_axi_areset (clk40_rst), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr(M_AXI_JESD1_AWADDR), + .s_axi_awvalid(M_AXI_JESD1_AWVALID), + .s_axi_awready(M_AXI_JESD1_AWREADY), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata(M_AXI_JESD1_WDATA), + .s_axi_wstrb(M_AXI_JESD1_WSTRB), + .s_axi_wvalid(M_AXI_JESD1_WVALID), + .s_axi_wready(M_AXI_JESD1_WREADY), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp(M_AXI_JESD1_BRESP), + .s_axi_bvalid(M_AXI_JESD1_BVALID), + .s_axi_bready(M_AXI_JESD1_BREADY), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr(M_AXI_JESD1_ARADDR), + .s_axi_arvalid(M_AXI_JESD1_ARVALID), + .s_axi_arready(M_AXI_JESD1_ARREADY), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (M_AXI_JESD1_RDATA), + .s_axi_rresp (M_AXI_JESD1_RRESP), + .s_axi_rvalid (M_AXI_JESD1_RVALID), + .s_axi_rready (M_AXI_JESD1_RREADY), + // Register port + .reg_port_in_rd (reg_portB_rd), + .reg_port_in_wt (reg_portB_wr), + .reg_port_in_addr (reg_portB_addr), + .reg_port_in_data (reg_portB_wr_data), + .reg_port_out_data (reg_portB_rd_data), + .reg_port_out_ready(reg_portB_ready) + ); + + + // ////////////////////////////////////////////////////////////////////// + // + // LEDS + // + // ////////////////////////////////////////////////////////////////////// + + assign PANEL_LED_LINK = ps_gpio_out[45]; + assign PANEL_LED_REF = ps_gpio_out[46]; + assign PANEL_LED_GPS = ps_gpio_out[47]; + + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule diff --git a/fpga/usrp3/top/n3xx/dev_config.json b/fpga/usrp3/top/n3xx/dev_config.json new file mode 100644 index 000000000..eb6ce9dc0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dev_config.json @@ -0,0 +1,3 @@ +{ + "warning": { "ignore": ["."]} +} diff --git a/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx b/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx new file mode 100644 index 000000000..ec3849d59 Binary files /dev/null and b/fpga/usrp3/top/n3xx/doc/mb_timing.xlsx differ diff --git a/fpga/usrp3/top/n3xx/dts/dma-common.dtsi b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi new file mode 100644 index 000000000..65d33cb76 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/dma-common.dtsi @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2017 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + tx_dma0: dma@43CA0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CA0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma1: dma@43CB0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CB0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma2: dma@43CC0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CC0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma3: dma@43CD0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CD0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma4: dma@43CE0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CE0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma5: dma@43CF0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43CF0000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma6: dma@43D00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D00000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma7: dma@43D10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D10000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma8: dma@43D20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D20000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + tx_dma9: dma@43D30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43D30000 0x10000>; + interrupts = <0 53 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <1>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma0: dma@43C00000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C00000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma1: dma@43C10000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C10000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma2: dma@43C20000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C20000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma3: dma@43C30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C30000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma4: dma@43C40000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C40000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma5: dma@43C50000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C50000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma6: dma@43C60000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C60000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma7: dma@43C70000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C70000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma8: dma@43C80000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C80000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + rx_dma9: dma@43C90000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x43C90000 0x10000>; + interrupts = <0 52 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 15>; + #dma-cells = <1>; + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <1>; + adi,source-bus-width = <0x20>; + adi,destination-bus-type = <0>; + adi,destination-bus-width = <0x20>; + adi,length-width = <24>; + }; + }; + }; + + + usrp_rx_dma0: usrp-rx-dma@43c00000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + status = "okay"; + + regmap = <&dma_conf0>; + offset = <0x0>; + }; + + usrp_rx_dma1: usrp-rx-dma@43c10000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + + regmap = <&dma_conf0>; + offset = <0x4>; + }; + + usrp_rx_dma2: usrp-rx-dma@43c20000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + + regmap = <&dma_conf0>; + offset = <0x8>; + }; + + usrp_rx_dma3: usrp-rx-dma@43c30000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + + regmap = <&dma_conf0>; + offset = <0xc>; + }; + + usrp_rx_dma4: usrp-rx-dma@43c40000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + + regmap = <&dma_conf0>; + offset = <0x10>; + }; + + usrp_rx_dma5: usrp-rx-dma@43c50000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + + regmap = <&dma_conf0>; + offset = <0x14>; + }; + + usrp_rx_dma6: usrp-rx-dma@43c60000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma6 0>; + dma-names = "dma"; + port-id = <6>; + + regmap = <&dma_conf0>; + offset = <0x18>; + }; + + usrp_rx_dma7: usrp-rx-dma@43c70000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma7 0>; + dma-names = "dma"; + port-id = <7>; + + regmap = <&dma_conf0>; + offset = <0x1c>; + }; + + usrp_rx_dma8: usrp-rx-dma@43c80000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma8 0>; + dma-names = "dma"; + port-id = <8>; + + regmap = <&dma_conf0>; + offset = <0x20>; + }; + + usrp_rx_dma9: usrp-rx-dma@43c90000 { + compatible = "ettus,usrp-rx-dma"; + dmas = <&rx_dma9 0>; + dma-names = "dma"; + port-id = <9>; + + regmap = <&dma_conf0>; + offset = <0x24>; + }; + + usrp_tx_dma0: usrp-tx-dma@43ca0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma0 0>; + dma-names = "dma"; + port-id = <0>; + }; + + usrp_tx_dma1: usrp-tx-dma@43cb0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma1 0>; + dma-names = "dma"; + port-id = <1>; + }; + + usrp_tx_dma2: usrp-tx-dma@43cc0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma2 0>; + dma-names = "dma"; + port-id = <2>; + status = "okay"; + }; + + usrp_tx_dma3: usrp-tx-dma@43cd0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma3 0>; + dma-names = "dma"; + port-id = <3>; + }; + + usrp_tx_dma4: usrp-tx-dma@43ce0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma4 0>; + dma-names = "dma"; + port-id = <4>; + status = "okay"; + }; + + usrp_tx_dma5: usrp-tx-dma@43cf0000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma5 0>; + dma-names = "dma"; + port-id = <5>; + }; + + usrp_tx_dma6: usrp-tx-dma@43d00000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma6 0>; + dma-names = "dma"; + port-id = <6>; + }; + + usrp_tx_dma7: usrp-tx-dma@43d10000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma7 0>; + dma-names = "dma"; + port-id = <7>; + }; + + usrp_tx_dma8: usrp-tx-dma@43d20000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma8 0>; + dma-names = "dma"; + port-id = <8>; + }; + + usrp_tx_dma9: usrp-tx-dma@43d30000 { + compatible = "ettus,usrp-tx-dma"; + dmas = <&tx_dma9 0>; + dma-names = "dma"; + port-id = <9>; + }; + + dma_conf0: dma_conf0@42080000 { + compatible = "syscon"; + reg = <0x42080000 0x1000>; + status = "okay"; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n300-common.dtsi b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi new file mode 100644 index 000000000..1042d9531 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n300-common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017 National Instruments Corp + * + * SPDX-License-Identifier: GPL-2.0 OR X11 + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi new file mode 100644 index 000000000..d6bbee1a3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n300-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n300.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n310-common.dtsi b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi new file mode 100644 index 000000000..14be62eaf --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n310-common.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@40018000 { + compatible = "usrp-uio"; + reg = <0x40018000 0x4000>; + reg-names = "dboard-regs-1"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; + + uio@42200000 { + compatible = "usrp-uio"; + reg = <0x42200000 0x1000>; + reg-names = "dboard-jtag-1"; + status = "okay"; + }; + +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 62 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 63 0>; + + spidev4: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev5: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev6: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev7: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi new file mode 100644 index 000000000..3859c84f0 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n310-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n310.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n320-common.dtsi b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi new file mode 100644 index 000000000..e7fd557b3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n320-common.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + uio@40010000 { + compatible = "usrp-uio"; + reg = <0x40010000 0x2000>; + reg-names = "mboard-regs"; + status = "okay"; + }; + + uio@40014000 { + compatible = "usrp-uio"; + reg = <0x40014000 0x4000>; + reg-names = "dboard-regs-0"; + status = "okay"; + }; + + uio@40018000 { + compatible = "usrp-uio"; + reg = <0x40018000 0x4000>; + reg-names = "dboard-regs-1"; + status = "okay"; + }; + + uio@42100000 { + compatible = "usrp-uio"; + reg = <0x42100000 0x1000>; + reg-names = "dboard-jtag-0"; + status = "okay"; + }; + + uio@42200000 { + compatible = "usrp-uio"; + reg = <0x42200000 0x1000>; + reg-names = "dboard-jtag-1"; + status = "okay"; + }; +}; + +&spi0 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 67 0>, <&gpio0 68 0>; + + spidev0: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev1: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev2: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev3: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev4: spidev@4 { + compatible = "rohm,dh2228fv"; + reg = <4>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&spi1 { + status = "okay"; + + cs-gpios = <0>, <0>, <0>, <&gpio0 69 0>, <&gpio0 70 0>; + + spidev5: spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev6: spidev@1 { + compatible = "rohm,dh2228fv"; + reg = <1>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev7: spidev@2 { + compatible = "rohm,dh2228fv"; + reg = <2>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev8: spidev@3 { + compatible = "rohm,dh2228fv"; + reg = <3>; + status = "okay"; + spi-max-frequency = <1000000>; + }; + + spidev9: spidev@4 { + compatible = "rohm,dh2228fv"; + reg = <4>; + status = "okay"; + spi-max-frequency = <1000000>; + }; +}; + +&usrpio_i2c0 { + rhodium_lodist_gpio: rhodium-lodist-gpio@22 { + compatible = "nxp,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi new file mode 100644 index 000000000..5934138a9 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/n320-fpga.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +&fpga_full { + firmware-name = "n320.bin"; +}; diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts new file mode 100644 index 000000000..f0099f08b --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_AA.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts new file mode 100644 index 000000000..6cdce8022 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HA.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts new file mode 100644 index 000000000..7f94f1126 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_HG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts new file mode 100644 index 000000000..904149270 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_WX.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts new file mode 100644 index 000000000..984591d08 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XA.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts new file mode 100644 index 000000000..3f01d18b1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n300_fpga_XG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n300-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n300-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts new file mode 100644 index 000000000..637e6371d --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_AA.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + uio@40004000 { + compatible = "usrp-uio"; + reg = <0x40004000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts new file mode 100644 index 000000000..bc03736e3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HA.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts new file mode 100644 index 000000000..0039d3b0a --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_HG.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full{ + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts new file mode 100644 index 000000000..41ee3c0a8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_WX.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts new file mode 100644 index 000000000..0838595dd --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XA.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + uio@4000c000 { + compatible = "usrp-uio"; + reg = <0x4000c000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts new file mode 100644 index 000000000..204f91515 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n310_fpga_XG.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2017 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n310-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n310-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts new file mode 100644 index 000000000..6382192b8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_AQ.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@40020000 { + compatible = "usrp-uio"; + reg = <0x40020000 0x1000>; + reg-names = "misc-auro-regs0"; + status = "okay"; + }; + + uio@40024000 { + compatible = "usrp-uio"; + reg = <0x40024000 0x1000>; + reg-names = "misc-auro-regs1"; + status = "okay"; + }; + + uio@40028000 { + compatible = "usrp-uio"; + reg = <0x40028000 0x1000>; + reg-names = "misc-auro-regs2"; + status = "okay"; + }; + + + uio@4002c000 { + compatible = "usrp-uio"; + reg = <0x4002c000 0x1000>; + reg-names = "misc-auro-regs3"; + status = "okay"; + }; + + qsfp_i2c: qsfp-i2c@43D80000 { + compatible = "xlnx,xps-iic-2.00.a"; + clocks = <&clkc 15>; + interrupt-parent = <&intc>; + interrupts = <0 55 4>; + reg = <0x43D80000 0x10000>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts new file mode 100644 index 000000000..d08aeb87b --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_HG.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + /* 114 = 54 (MIOs) + 60 (EMIO 60) */ + link-gpios = <&gpio0 114 0>; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts new file mode 100644 index 000000000..8b133ce98 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_WX.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + * + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts new file mode 100644 index 000000000..f585dbddb --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XG.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40008000 0x6000>; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@4000e000 { + compatible = "usrp-uio"; + reg = <0x4000e000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts new file mode 100644 index 000000000..037447932 --- /dev/null +++ b/fpga/usrp3/top/n3xx/dts/usrp_n320_fpga_XQ.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright (c) 2018 National Instruments Corp + */ + +/dts-v1/; +/plugin/; + +#include "n320-fpga.dtsi" + +&fpga_full { + nixge0: ethernet@40000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ni,xge-enet-3.00"; + reg = <0x40000000 0x4000 + 0x40020000 0x2000>; + reg-names = "dma", "ctrl"; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 4>, <0 30 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + mdio { + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40022000 { + compatible = "usrp-uio"; + reg = <0x40022000 0x2000>; + reg-names = "misc-enet-regs0"; + status = "okay"; + }; + + nixge1: ethernet@40008000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ni,xge-enet-3.00"; + reg = <0x40008000 0x4000 + 0x40024000 0x2000>; + reg-names = "dma", "ctrl"; + + clocks = <&clkc 15>; + clock-names = "bus_clk"; + + nvmem-cells = <ð2_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 31 4>, <0 32 4>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + status = "okay"; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy2>; + + mdio { + ethernet_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; + }; + + uio@40026000 { + compatible = "usrp-uio"; + reg = <0x40026000 0x2000>; + reg-names = "misc-enet-regs1"; + status = "okay"; + }; + + uio@40006000 { + compatible = "usrp-uio"; + reg = <0x40006000 0x2000>; + reg-names = "misc-enet-regs2"; + status = "okay"; + }; + + uio@43d40000 { + compatible = "usrp-uio"; + reg = <0x43d40000 0x40000>; + reg-names = "wr-regs"; + status = "okay"; + }; + + uart2@42c00000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x42c00000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + }; + + qsfp_i2c: qsfp-i2c@43D80000 { + compatible = "xlnx,xps-iic-2.00.a"; + clocks = <&clkc 15>; + interrupt-parent = <&intc>; + interrupts = <0 55 4>; + reg = <0x43D80000 0x10000>; + }; +}; + +#include "n320-common.dtsi" +#include "dma-common.dtsi" diff --git a/fpga/usrp3/top/n3xx/ip/Makefile.inc b/fpga/usrp3/top/n3xx/ip/Makefile.inc new file mode 100644 index 000000000..98021fcc7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/Makefile.inc @@ -0,0 +1,90 @@ +# +# Copyright 2017-2018 Ettus Research, a National Instruments Company +# + +#include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/hb47_1to2/Makefile.inc +include $(IP_DIR)/hb47_2to1/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_256_bd/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +#include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/misc_clock_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/axi3_to_axi4lite_protocol_converter/Makefile.inc +include $(IP_DIR)/axis_fifo_to_axi4lite/Makefile.inc +include $(IP_DIR)/axi_eth_dma/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_32/Makefile.inc +include $(IP_DIR)/axi4_to_axi3_protocol_converter_64/Makefile.inc +include $(IP_DIR)/n310_ps_bd/Makefile.inc + +BD_SRCS = \ +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_N310_PS_BD_SRCS) + +IP_XCI_SRCS = \ +$(IP_HB47_1TO2_SRCS) \ +$(IP_HB47_2TO1_SRCS) \ +$(IP_AXI4_BRAM_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) \ +$(IP_MISC_CLOCK_GEN_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI_ETH_DMA_SRCS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(ONE_GIGE_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_HB47_1TO2_OUTS) \ +$(IP_HB47_2TO1_OUTS) \ +$(IP_AXI4_BRAM_OUTS) \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) \ +$(IP_AXI_INTERCONNECT_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) \ +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) \ +$(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AXI_ETH_DMA_OUTS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_2X64_256_BD_OUTS) \ +$(IP_AXI_INTERCON_4X64_256_BD_OUTS) \ +$(IP_N310_PS_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..270f4e92e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,32 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..aaba9d9c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1780 @@ + + + xilinx.com + xci + unknown + 1.0 + + + aurora_64b66b_pcs_pma + + + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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+ 78.125 + 20 + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + 0 + false + false + Duplex + AXI4_LITE + None + Streaming + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..39ed52f8c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v new file mode 100644 index 000000000..9e98990c1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output init_clk +); + + wire init_clk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (init_clk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (init_clk_buf), + .O (init_clk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v new file mode 100644 index 000000000..c2107f8b1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_mmcm.v @@ -0,0 +1,108 @@ +// +// Copyright 2017 Ettus Research LLC +// + +module aurora_phy_mmcm +( + input aurora_tx_clk_unbuf, + input mmcm_reset, + output user_clk, + output sync_clk, + output mmcm_locked +); + + wire mmcm_fb_clk; + wire user_clk_i; + wire sync_clk_i; + wire aurora_tx_clk; + + BUFG txout_clock_net_i ( + .I(aurora_tx_clk_unbuf), + .O(aurora_tx_clk) + ); + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (aurora_tx_clk), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..6b768bfcf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,258 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input user_clk, + input sync_clk, + input init_clk, + input qpllclk, + input qpllrefclk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err, + input qplllock, + input qpllrefclklost, + output qpllreset, + output tx_out_clk, + input mmcm_locked, + output gt_pll_lock +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock_iclk, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_qpllclk_quad2_i; + wire gt_qpllrefclk_quad2_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + assign gt_qpllclk_quad1_i = qpllclk; + assign gt_qpllrefclk_quad1_i = qpllrefclk; + assign gt_qpllclk_quad2_i = qpllclk; + assign gt_qpllrefclk_quad2_i = qpllrefclk; + assign gt_qplllock_i = qplllock; + assign gt_qpllrefclklost_i = qpllrefclklost; + assign qpllreset = gt_to_common_qpllreset_i; + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; +aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc new file mode 100644 index 000000000..34dacff4f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS = $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + +IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS = $(addprefix $(IP_BUILD_DIR)/axi3_to_axi4lite_protocol_converter/, \ +axi3_to_axi4lite_protocol_converter.xci.out \ +synth/axi3_to_axi4lite_protocol_converter.v \ +) + +$(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_SRCS) $(IP_AXI3_TO_AXI4LITE_PROTOCOL_CONVERTER_OUTS) : $(IP_DIR)/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci + $(call BUILD_VIVADO_IP,axi3_to_axi4lite_protocol_converter,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci new file mode 100644 index 000000000..344851bf8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci @@ -0,0 +1,152 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi3_to_axi4lite_protocol_converter + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 12 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 32 + 12 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 2 + 1 + 2 + 32 + 0 + 0 + 0 + axi3_to_axi4lite_protocol_converter + 32 + 12 + AXI4LITE + READ_WRITE + 0 + AXI3 + 2 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc new file mode 100644 index 000000000..b7f92cf6f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS = $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_32/, \ +axi4_to_axi3_protocol_converter_32.xci.out \ +synth/axi4_to_axi3_protocol_converter_32.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_32_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci + $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_32,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci new file mode 100644 index 000000000..2fa5f4cac --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_32/axi4_to_axi3_protocol_converter_32.xci @@ -0,0 +1,149 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_to_axi3_protocol_converter_32 + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 6 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 32 + 6 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + axi4_to_axi3_protocol_converter_32 + 32 + 6 + AXI3 + READ_WRITE + 0 + AXI4 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc new file mode 100644 index 000000000..0c68b7a3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS = $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci + +IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_to_axi3_protocol_converter_64/, \ +axi4_to_axi3_protocol_converter_64.xci.out \ +synth/axi4_to_axi3_protocol_converter_64.v \ +) + +$(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_SRCS) $(IP_AXI4_TO_AXI3_PROTOCOL_CONVERTER_64_OUTS) : $(IP_DIR)/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci + $(call BUILD_VIVADO_IP,axi4_to_axi3_protocol_converter_64,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci new file mode 100644 index 000000000..fc8b9e67e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi4_to_axi3_protocol_converter_64/axi4_to_axi3_protocol_converter_64.xci @@ -0,0 +1,151 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_to_axi3_protocol_converter_64 + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 6 + 0 + 16 + 2 + 1 + 2 + 1 + 0.000 + AXI3 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 0 + ACTIVE_LOW + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 6 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 1 + 1 + 1 + 64 + 6 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + axi4_to_axi3_protocol_converter_64 + 64 + 6 + AXI3 + READ_WRITE + 0 + AXI4 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 19 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..26d706087 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_4k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 9 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_4k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..2f6ec0d88 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_8k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 1kx36 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_8k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc new file mode 100644 index 000000000..658891469 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_ETH_DMA_SRCS = $(IP_BUILD_DIR)/axi_eth_dma/axi_eth_dma.xci + +IP_AXI_ETH_DMA_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma/, \ +axi_eth_dma.xci.out \ +) + +$(IP_AXI_ETH_DMA_SRCS) $(IP_AXI_ETH_DMA_OUTS) : $(IP_DIR)/axi_eth_dma/axi_eth_dma.xci + $(call BUILD_VIVADO_IP,axi_eth_dma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci new file mode 100644 index 000000000..ec1df69ec --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_eth_dma/axi_eth_dma.xci @@ -0,0 +1,412 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_eth_dma + + + 0 + 0 + 1 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 256 + 1 + 2 + 1 + 0.000 + AXI4 + READ_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 256 + 2 + 1 + 1 + 0.000 + AXI4 + WRITE_ONLY + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 10 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0.000 + 125 + 0 + zynq + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 16 + 32 + 64 + 32 + 64 + 32 + 64 + 32 + 1 + 1 + 0 + 16 + 0 + 23 + 0 + 32 + 64 + axi_eth_dma + 32 + 125 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 64 + 64 + 64 + 0 + 16 + 1 + 1 + 0 + 16 + 64 + 0 + 23 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 20 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc new file mode 100644 index 000000000..02b27ee68 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_2X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v + +BD_AXI_INTERCON_2X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_256_bd/, \ +axi_intercon_2x64_256_bd.bd.out \ +axi_intercon_2x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_2X64_256_BD_SRCS) $(IP_AXI_INTERCON_2X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_2x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd new file mode 100644 index 000000000..121829558 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bd @@ -0,0 +1,715 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_256_bd + 1.00.a + + + isTop + true + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 200000000 + + + ADDR_WIDTH + 32 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 350000000 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 1 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + + + S01_AXI + + + + + + DATA_WIDTH + 64 + + + PROTOCOL + AXI4 + + + FREQ_HZ + 350000000 + + + ID_WIDTH + 1 + + + ADDR_WIDTH + 32 + + + AWUSER_WIDTH + 0 + + + ARUSER_WIDTH + 0 + + + WUSER_WIDTH + 0 + + + RUSER_WIDTH + 0 + + + BUSER_WIDTH + 0 + + + READ_WRITE_MODE + READ_WRITE + + + HAS_BURST + 1 + + + HAS_LOCK + 1 + + + HAS_PROT + 1 + + + HAS_CACHE + 1 + + + HAS_QOS + 1 + + + HAS_REGION + 1 + + + HAS_WSTRB + 1 + + + HAS_BRESP + 1 + + + HAS_RRESP + 1 + + + SUPPORTS_NARROW_BURST + 1 + + + NUM_READ_OUTSTANDING + 2 + + + NUM_WRITE_OUTSTANDING + 2 + + + MAX_BURST_LENGTH + 256 + + + PHASE + 0.000 + + + + + CLK.M00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + M00_AXI_ACLK + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + ASSOCIATED_RESET + M00_AXI_ARESETN + + + + + RST.M00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + M00_AXI_ARESETN + + + + + + + CLK.S00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S00_AXI_ACLK + + + + + + FREQ_HZ + 1000000000 + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 32M + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x02000000 + 32M + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_256_bd_imp + 1.00.a + + + m00_rs + + + axi_intercon_2x64_256_bd_m00_rs_0 + 1 + 1 + 1 + + + + s00_rs + + + axi_intercon_2x64_256_bd_s00_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_width_conv + + + axi_intercon_2x64_256_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_rs + + + axi_intercon_2x64_256_bd_s01_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_width_conv + + + axi_intercon_2x64_256_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_2x64_256_bd_xbar_0 + 2 + 1 + 2 + 256 + 1 + 0x00000001 + 0x00000002 + 0x00000003 + 0x00000004 + 0x00000005 + 0x00000006 + 0x00000007 + 0x00000008 + 0x00000009 + 0x0000000a + 0x0000000b + 0x0000000c + 0x0000000d + 0x0000000e + 0x0000000f + + + + s01_rs_256 + + + axi_intercon_2x64_256_bd_s01_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_256 + + + axi_intercon_2x64_256_bd_s00_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + + + s00_rs_M_AXI + + + + + s01_rs_M_AXI + + + + + xbar_M00_AXI + + + + + s00_rs_256_M_AXI + + + + + s01_rs_256_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml new file mode 100644 index 000000000..5e3a0c83e --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd.bxml @@ -0,0 +1,89 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v new file mode 100644 index 000000000..06a471d59 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_2x64_256_bd/axi_intercon_2x64_256_bd_wrapper.v @@ -0,0 +1,500 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_2x64_256_bd_wrapper + (M00_AXI_ACLK, + M00_AXI_ARESETN, + M00_AXI_ARADDR, + M00_AXI_ARBURST, + M00_AXI_ARCACHE, + M00_AXI_ARID, + M00_AXI_ARLEN, + M00_AXI_ARLOCK, + M00_AXI_ARPROT, + M00_AXI_ARQOS, + M00_AXI_ARREADY, + M00_AXI_ARREGION, + M00_AXI_ARSIZE, + M00_AXI_ARVALID, + M00_AXI_AWADDR, + M00_AXI_AWBURST, + M00_AXI_AWCACHE, + M00_AXI_AWID, + M00_AXI_AWLEN, + M00_AXI_AWLOCK, + M00_AXI_AWPROT, + M00_AXI_AWQOS, + M00_AXI_AWREADY, + M00_AXI_AWREGION, + M00_AXI_AWSIZE, + M00_AXI_AWVALID, + M00_AXI_BID, + M00_AXI_BREADY, + M00_AXI_BRESP, + M00_AXI_BVALID, + M00_AXI_RDATA, + M00_AXI_RID, + M00_AXI_RLAST, + M00_AXI_RREADY, + M00_AXI_RRESP, + M00_AXI_RVALID, + M00_AXI_WDATA, + M00_AXI_WLAST, + M00_AXI_WREADY, + M00_AXI_WSTRB, + M00_AXI_WVALID, + S00_AXI_ACLK, + S00_AXI_ARESETN, + S00_AXI_ARADDR, + S00_AXI_ARBURST, + S00_AXI_ARCACHE, + S00_AXI_ARID, + S00_AXI_ARLEN, + S00_AXI_ARLOCK, + S00_AXI_ARPROT, + S00_AXI_ARQOS, + S00_AXI_ARREADY, + S00_AXI_ARREGION, + S00_AXI_ARSIZE, + S00_AXI_ARVALID, + S00_AXI_AWADDR, + S00_AXI_AWBURST, + S00_AXI_AWCACHE, + S00_AXI_AWID, + S00_AXI_AWLEN, + S00_AXI_AWLOCK, + S00_AXI_AWPROT, + S00_AXI_AWQOS, + S00_AXI_AWREADY, + S00_AXI_AWREGION, + S00_AXI_AWSIZE, + S00_AXI_AWVALID, + S00_AXI_BID, + S00_AXI_BREADY, + S00_AXI_BRESP, + S00_AXI_BVALID, + S00_AXI_RDATA, + S00_AXI_RID, + S00_AXI_RLAST, + S00_AXI_RREADY, + S00_AXI_RRESP, + S00_AXI_RVALID, + S00_AXI_WDATA, + S00_AXI_WLAST, + S00_AXI_WREADY, + S00_AXI_WSTRB, + S00_AXI_WVALID, + S01_AXI_ACLK, + S01_AXI_ARESETN, + S01_AXI_ARADDR, + S01_AXI_ARBURST, + S01_AXI_ARCACHE, + S01_AXI_ARID, + S01_AXI_ARLEN, + S01_AXI_ARLOCK, + S01_AXI_ARPROT, + S01_AXI_ARQOS, + S01_AXI_ARREADY, + S01_AXI_ARREGION, + S01_AXI_ARSIZE, + S01_AXI_ARVALID, + S01_AXI_AWADDR, + S01_AXI_AWBURST, + S01_AXI_AWCACHE, + S01_AXI_AWID, + S01_AXI_AWLEN, + S01_AXI_AWLOCK, + S01_AXI_AWPROT, + S01_AXI_AWQOS, + S01_AXI_AWREADY, + S01_AXI_AWREGION, + S01_AXI_AWSIZE, + S01_AXI_AWVALID, + S01_AXI_BID, + S01_AXI_BREADY, + S01_AXI_BRESP, + S01_AXI_BVALID, + S01_AXI_RDATA, + S01_AXI_RID, + S01_AXI_RLAST, + S01_AXI_RREADY, + S01_AXI_RRESP, + S01_AXI_RVALID, + S01_AXI_WDATA, + S01_AXI_WLAST, + S01_AXI_WREADY, + S01_AXI_WSTRB, + S01_AXI_WVALID); + input M00_AXI_ACLK; + input M00_AXI_ARESETN; + output [31:0]M00_AXI_ARADDR; + output [1:0]M00_AXI_ARBURST; + output [3:0]M00_AXI_ARCACHE; + output [0:0]M00_AXI_ARID; + output [7:0]M00_AXI_ARLEN; + output [0:0]M00_AXI_ARLOCK; + output [2:0]M00_AXI_ARPROT; + output [3:0]M00_AXI_ARQOS; + input M00_AXI_ARREADY; + output [3:0]M00_AXI_ARREGION; + output [2:0]M00_AXI_ARSIZE; + output M00_AXI_ARVALID; + output [31:0]M00_AXI_AWADDR; + output [1:0]M00_AXI_AWBURST; + output [3:0]M00_AXI_AWCACHE; + output [0:0]M00_AXI_AWID; + output [7:0]M00_AXI_AWLEN; + output [0:0]M00_AXI_AWLOCK; + output [2:0]M00_AXI_AWPROT; + output [3:0]M00_AXI_AWQOS; + input M00_AXI_AWREADY; + output [3:0]M00_AXI_AWREGION; + output [2:0]M00_AXI_AWSIZE; + output M00_AXI_AWVALID; + input [0:0]M00_AXI_BID; + output M00_AXI_BREADY; + input [1:0]M00_AXI_BRESP; + input M00_AXI_BVALID; + input [255:0]M00_AXI_RDATA; + input [0:0]M00_AXI_RID; + input M00_AXI_RLAST; + output M00_AXI_RREADY; + input [1:0]M00_AXI_RRESP; + input M00_AXI_RVALID; + output [255:0]M00_AXI_WDATA; + output M00_AXI_WLAST; + input M00_AXI_WREADY; + output [31:0]M00_AXI_WSTRB; + output M00_AXI_WVALID; + input S00_AXI_ACLK; + input S00_AXI_ARESETN; + input [31:0]S00_AXI_ARADDR; + input [1:0]S00_AXI_ARBURST; + input [3:0]S00_AXI_ARCACHE; + input [0:0]S00_AXI_ARID; + input [7:0]S00_AXI_ARLEN; + input [0:0]S00_AXI_ARLOCK; + input [2:0]S00_AXI_ARPROT; + input [3:0]S00_AXI_ARQOS; + output S00_AXI_ARREADY; + input [3:0]S00_AXI_ARREGION; + input [2:0]S00_AXI_ARSIZE; + input S00_AXI_ARVALID; + input [31:0]S00_AXI_AWADDR; + input [1:0]S00_AXI_AWBURST; + input [3:0]S00_AXI_AWCACHE; + input [0:0]S00_AXI_AWID; + input [7:0]S00_AXI_AWLEN; + input [0:0]S00_AXI_AWLOCK; + input [2:0]S00_AXI_AWPROT; + input [3:0]S00_AXI_AWQOS; + output S00_AXI_AWREADY; + input [3:0]S00_AXI_AWREGION; + input [2:0]S00_AXI_AWSIZE; + input S00_AXI_AWVALID; + output [0:0]S00_AXI_BID; + input S00_AXI_BREADY; + output [1:0]S00_AXI_BRESP; + output S00_AXI_BVALID; + output [63:0]S00_AXI_RDATA; + output [0:0]S00_AXI_RID; + output S00_AXI_RLAST; + input S00_AXI_RREADY; + output [1:0]S00_AXI_RRESP; + output S00_AXI_RVALID; + input [63:0]S00_AXI_WDATA; + input S00_AXI_WLAST; + output S00_AXI_WREADY; + input [7:0]S00_AXI_WSTRB; + input S00_AXI_WVALID; + input S01_AXI_ACLK; + input S01_AXI_ARESETN; + input [31:0]S01_AXI_ARADDR; + input [1:0]S01_AXI_ARBURST; + input [3:0]S01_AXI_ARCACHE; + input [0:0]S01_AXI_ARID; + input [7:0]S01_AXI_ARLEN; + input [0:0]S01_AXI_ARLOCK; + input [2:0]S01_AXI_ARPROT; + input [3:0]S01_AXI_ARQOS; + output S01_AXI_ARREADY; + input [3:0]S01_AXI_ARREGION; + input [2:0]S01_AXI_ARSIZE; + input S01_AXI_ARVALID; + input [31:0]S01_AXI_AWADDR; + input [1:0]S01_AXI_AWBURST; + input [3:0]S01_AXI_AWCACHE; + input [0:0]S01_AXI_AWID; + input [7:0]S01_AXI_AWLEN; + input [0:0]S01_AXI_AWLOCK; + input [2:0]S01_AXI_AWPROT; + input [3:0]S01_AXI_AWQOS; + output S01_AXI_AWREADY; + input [3:0]S01_AXI_AWREGION; + input [2:0]S01_AXI_AWSIZE; + input S01_AXI_AWVALID; + output [0:0]S01_AXI_BID; + input S01_AXI_BREADY; + output [1:0]S01_AXI_BRESP; + output S01_AXI_BVALID; + output [63:0]S01_AXI_RDATA; + output [0:0]S01_AXI_RID; + output S01_AXI_RLAST; + input S01_AXI_RREADY; + output [1:0]S01_AXI_RRESP; + output S01_AXI_RVALID; + input [63:0]S01_AXI_WDATA; + input S01_AXI_WLAST; + output S01_AXI_WREADY; + input [7:0]S01_AXI_WSTRB; + input S01_AXI_WVALID; + + wire M00_AXI_ACLK; + wire M00_AXI_ARESETN; + wire [31:0]M00_AXI_ARADDR; + wire [1:0]M00_AXI_ARBURST; + wire [3:0]M00_AXI_ARCACHE; + wire [0:0]M00_AXI_ARID; + wire [7:0]M00_AXI_ARLEN; + wire [0:0]M00_AXI_ARLOCK; + wire [2:0]M00_AXI_ARPROT; + wire [3:0]M00_AXI_ARQOS; + wire M00_AXI_ARREADY; + wire [3:0]M00_AXI_ARREGION; + wire [2:0]M00_AXI_ARSIZE; + wire M00_AXI_ARVALID; + wire [31:0]M00_AXI_AWADDR; + wire [1:0]M00_AXI_AWBURST; + wire [3:0]M00_AXI_AWCACHE; + wire [0:0]M00_AXI_AWID; + wire [7:0]M00_AXI_AWLEN; + wire [0:0]M00_AXI_AWLOCK; + wire [2:0]M00_AXI_AWPROT; + wire [3:0]M00_AXI_AWQOS; + wire M00_AXI_AWREADY; + wire [3:0]M00_AXI_AWREGION; + wire [2:0]M00_AXI_AWSIZE; + wire M00_AXI_AWVALID; + wire [0:0]M00_AXI_BID; + wire M00_AXI_BREADY; + wire [1:0]M00_AXI_BRESP; + wire M00_AXI_BVALID; + wire [255:0]M00_AXI_RDATA; + wire [0:0]M00_AXI_RID; + wire M00_AXI_RLAST; + wire M00_AXI_RREADY; + wire [1:0]M00_AXI_RRESP; + wire M00_AXI_RVALID; + wire [255:0]M00_AXI_WDATA; + wire M00_AXI_WLAST; + wire M00_AXI_WREADY; + wire [31:0]M00_AXI_WSTRB; + wire M00_AXI_WVALID; + wire S00_AXI_ACLK; + wire S00_AXI_ARESETN; + wire [31:0]S00_AXI_ARADDR; + wire [1:0]S00_AXI_ARBURST; + wire [3:0]S00_AXI_ARCACHE; + wire [0:0]S00_AXI_ARID; + wire [7:0]S00_AXI_ARLEN; + wire [0:0]S00_AXI_ARLOCK; + wire [2:0]S00_AXI_ARPROT; + wire [3:0]S00_AXI_ARQOS; + wire S00_AXI_ARREADY; + wire [3:0]S00_AXI_ARREGION; + wire [2:0]S00_AXI_ARSIZE; + wire S00_AXI_ARVALID; + wire [31:0]S00_AXI_AWADDR; + wire [1:0]S00_AXI_AWBURST; + wire [3:0]S00_AXI_AWCACHE; + wire [0:0]S00_AXI_AWID; + wire [7:0]S00_AXI_AWLEN; + wire [0:0]S00_AXI_AWLOCK; + wire [2:0]S00_AXI_AWPROT; + wire [3:0]S00_AXI_AWQOS; + wire S00_AXI_AWREADY; + wire [3:0]S00_AXI_AWREGION; + wire [2:0]S00_AXI_AWSIZE; + wire S00_AXI_AWVALID; + wire [0:0]S00_AXI_BID; + wire S00_AXI_BREADY; + wire [1:0]S00_AXI_BRESP; + wire S00_AXI_BVALID; + wire [63:0]S00_AXI_RDATA; + wire [0:0]S00_AXI_RID; + wire S00_AXI_RLAST; + wire S00_AXI_RREADY; + wire [1:0]S00_AXI_RRESP; + wire S00_AXI_RVALID; + wire [63:0]S00_AXI_WDATA; + wire S00_AXI_WLAST; + wire S00_AXI_WREADY; + wire [7:0]S00_AXI_WSTRB; + wire S00_AXI_WVALID; + wire S01_AXI_ACLK; + wire S01_AXI_ARESETN; + wire [31:0]S01_AXI_ARADDR; + wire [1:0]S01_AXI_ARBURST; + wire [3:0]S01_AXI_ARCACHE; + wire [0:0]S01_AXI_ARID; + wire [7:0]S01_AXI_ARLEN; + wire [0:0]S01_AXI_ARLOCK; + wire [2:0]S01_AXI_ARPROT; + wire [3:0]S01_AXI_ARQOS; + wire S01_AXI_ARREADY; + wire [3:0]S01_AXI_ARREGION; + wire [2:0]S01_AXI_ARSIZE; + wire S01_AXI_ARVALID; + wire [31:0]S01_AXI_AWADDR; + wire [1:0]S01_AXI_AWBURST; + wire [3:0]S01_AXI_AWCACHE; + wire [0:0]S01_AXI_AWID; + wire [7:0]S01_AXI_AWLEN; + wire [0:0]S01_AXI_AWLOCK; + wire [2:0]S01_AXI_AWPROT; + wire [3:0]S01_AXI_AWQOS; + wire S01_AXI_AWREADY; + wire [3:0]S01_AXI_AWREGION; + wire [2:0]S01_AXI_AWSIZE; + wire S01_AXI_AWVALID; + wire [0:0]S01_AXI_BID; + wire S01_AXI_BREADY; + wire [1:0]S01_AXI_BRESP; + wire S01_AXI_BVALID; + wire [63:0]S01_AXI_RDATA; + wire [0:0]S01_AXI_RID; + wire S01_AXI_RLAST; + wire S01_AXI_RREADY; + wire [1:0]S01_AXI_RRESP; + wire S01_AXI_RVALID; + wire [63:0]S01_AXI_WDATA; + wire S01_AXI_WLAST; + wire S01_AXI_WREADY; + wire [7:0]S01_AXI_WSTRB; + wire S01_AXI_WVALID; + + axi_intercon_2x64_256_bd axi_intercon_2x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID)); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc new file mode 100644 index 000000000..2f5ba57c6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/Makefile.inc @@ -0,0 +1,17 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_4X64_256_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v + +BD_AXI_INTERCON_4X64_256_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/, \ +axi_intercon_4x64_256_bd.bd.out \ +axi_intercon_4x64_256_bd_ooc.xdc \ +) + +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) $(IP_AXI_INTERCON_4X64_256_BD_OUTS) : $(IP_DIR)/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_4x64_256_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd new file mode 100644 index 000000000..eb6c30100 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bd @@ -0,0 +1,2191 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd + 1.00.a + + + isTop + true + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 200000000 + + + + + + + + ID_WIDTH + 4 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_M00_ACLK + + + + + + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 350000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + 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+ + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S01_ACLK + + + + + + + + ASSOCIATED_BUSIF + S01_AXI + + + + + + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S02_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S02_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S02_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN:S02_AXI_ARESETN + + + + + + + + + + RST.S02_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S02_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S03_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S03_AXI_ACLK + + + + + + FREQ_HZ + 350000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_4x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S02_AXI:S03_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN:S02_AXI_ARESETN:S03_AXI_ARESETN + + + + + + + + + + RST.S03_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S03_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + S02_AXI_ACLK + + in + + + + S02_AXI_ARESETN + + in + + + + S03_AXI_ACLK + + in + + + + S03_AXI_ARESETN + + in + + + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S02_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + S03_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 1G + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_4x64_256_bd_imp + 1.00.a + + + m00_rs + + + axi_intercon_4x64_256_bd_m00_rs_0 + 4 + 1 + 1 + 1 + + + + s00_rs + + + axi_intercon_4x64_256_bd_s00_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_width_conv + + + axi_intercon_4x64_256_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_rs + + + axi_intercon_4x64_256_bd_s01_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_width_conv + + + axi_intercon_4x64_256_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_4x64_256_bd_xbar_0 + 4 + 1 + 2 + 256 + SAMD + 4 + 0 + 0x00000004 + 0x00000008 + 0x0000000c + 0x00000010 + 0x00000014 + 0x00000018 + 0x0000001c + 0x00000020 + 0x00000024 + 0x00000028 + 0x0000002c + 0x00000030 + 0x00000034 + 0x00000038 + 0x0000003c + + + + s01_rs_256 + + + axi_intercon_4x64_256_bd_s01_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_256 + + + axi_intercon_4x64_256_bd_s00_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs + + + axi_intercon_4x64_256_bd_s02_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s03_rs + + + axi_intercon_4x64_256_bd_s03_rs_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_width_conv + + + axi_intercon_4x64_256_bd_s02_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_width_conv + + + axi_intercon_4x64_256_bd_s03_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s03_rs_256 + + + axi_intercon_4x64_256_bd_s03_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + s02_rs_256 + + + axi_intercon_4x64_256_bd_s02_rs_256_0 + 1 + 1 + 1 + 1 + 1 + + + + + + s00_rs_M_AXI + + + + + s01_rs_M_AXI + + + + + xbar_M00_AXI + + + + + s00_rs_256_M_AXI + + + + + s01_rs_256_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + s02_rs_M_AXI + + + + + s03_rs_M_AXI + + + + + s02_width_conv_M_AXI + + + + + s03_width_conv_M_AXI + + + + + s02_rs_256_M_AXI + + + + + s03_rs_256_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + S02_AXI_ACLK_1 + + + + + + S02_AXI_ARESETN_1 + + + + + + S03_AXI_ACLK_1 + + + + + + S03_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml new file mode 100644 index 000000000..217597784 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd.bxml @@ -0,0 +1,123 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v new file mode 100644 index 000000000..71e446f92 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_intercon_4x64_256_bd/axi_intercon_4x64_256_bd_wrapper.v @@ -0,0 +1,419 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +`timescale 1 ps / 1 ps + +module axi_intercon_4x64_256_bd_wrapper ( + input M00_AXI_ACLK, + input M00_AXI_ARESETN, + output [31:0]M00_AXI_ARADDR, + output [1:0]M00_AXI_ARBURST, + output [3:0]M00_AXI_ARCACHE, + output [3:0]M00_AXI_ARID, + output [7:0]M00_AXI_ARLEN, + output [0:0]M00_AXI_ARLOCK, + output [2:0]M00_AXI_ARPROT, + output [3:0]M00_AXI_ARQOS, + input M00_AXI_ARREADY, + output [3:0]M00_AXI_ARREGION, + output [2:0]M00_AXI_ARSIZE, + output M00_AXI_ARVALID, + output [31:0]M00_AXI_AWADDR, + output [1:0]M00_AXI_AWBURST, + output [3:0]M00_AXI_AWCACHE, + output [3:0]M00_AXI_AWID, + output [7:0]M00_AXI_AWLEN, + output [0:0]M00_AXI_AWLOCK, + output [2:0]M00_AXI_AWPROT, + output [3:0]M00_AXI_AWQOS, + input M00_AXI_AWREADY, + output [3:0]M00_AXI_AWREGION, + output [2:0]M00_AXI_AWSIZE, + output M00_AXI_AWVALID, + input [3:0]M00_AXI_BID, + output M00_AXI_BREADY, + input [1:0]M00_AXI_BRESP, + input M00_AXI_BVALID, + input [255:0]M00_AXI_RDATA, + input [3:0]M00_AXI_RID, + input M00_AXI_RLAST, + output M00_AXI_RREADY, + input [1:0]M00_AXI_RRESP, + input M00_AXI_RVALID, + output [255:0]M00_AXI_WDATA, + output M00_AXI_WLAST, + input M00_AXI_WREADY, + output [31:0]M00_AXI_WSTRB, + output M00_AXI_WVALID, + input S00_AXI_ACLK, + input S00_AXI_ARESETN, + input [31:0]S00_AXI_ARADDR, + input [1:0]S00_AXI_ARBURST, + input [3:0]S00_AXI_ARCACHE, + input [0:0]S00_AXI_ARID, + input [7:0]S00_AXI_ARLEN, + input [0:0]S00_AXI_ARLOCK, + input [2:0]S00_AXI_ARPROT, + input [3:0]S00_AXI_ARQOS, + output S00_AXI_ARREADY, + input [3:0]S00_AXI_ARREGION, + input [2:0]S00_AXI_ARSIZE, + input S00_AXI_ARVALID, + input [31:0]S00_AXI_AWADDR, + input [1:0]S00_AXI_AWBURST, + input [3:0]S00_AXI_AWCACHE, + input [0:0]S00_AXI_AWID, + input [7:0]S00_AXI_AWLEN, + input [0:0]S00_AXI_AWLOCK, + input [2:0]S00_AXI_AWPROT, + input [3:0]S00_AXI_AWQOS, + output S00_AXI_AWREADY, + input [3:0]S00_AXI_AWREGION, + input [2:0]S00_AXI_AWSIZE, + input S00_AXI_AWVALID, + output [0:0]S00_AXI_BID, + input S00_AXI_BREADY, + output [1:0]S00_AXI_BRESP, + output S00_AXI_BVALID, + output [63:0]S00_AXI_RDATA, + output [0:0]S00_AXI_RID, + output S00_AXI_RLAST, + input S00_AXI_RREADY, + output [1:0]S00_AXI_RRESP, + output S00_AXI_RVALID, + input [63:0]S00_AXI_WDATA, + input S00_AXI_WLAST, + output S00_AXI_WREADY, + input [7:0]S00_AXI_WSTRB, + input S00_AXI_WVALID, + input S01_AXI_ACLK, + input S01_AXI_ARESETN, + input [31:0]S01_AXI_ARADDR, + input [1:0]S01_AXI_ARBURST, + input [3:0]S01_AXI_ARCACHE, + input [0:0]S01_AXI_ARID, + input [7:0]S01_AXI_ARLEN, + input [0:0]S01_AXI_ARLOCK, + input [2:0]S01_AXI_ARPROT, + input [3:0]S01_AXI_ARQOS, + output S01_AXI_ARREADY, + input [3:0]S01_AXI_ARREGION, + input [2:0]S01_AXI_ARSIZE, + input S01_AXI_ARVALID, + input [31:0]S01_AXI_AWADDR, + input [1:0]S01_AXI_AWBURST, + input [3:0]S01_AXI_AWCACHE, + input [0:0]S01_AXI_AWID, + input [7:0]S01_AXI_AWLEN, + input [0:0]S01_AXI_AWLOCK, + input [2:0]S01_AXI_AWPROT, + input [3:0]S01_AXI_AWQOS, + output S01_AXI_AWREADY, + input [3:0]S01_AXI_AWREGION, + input [2:0]S01_AXI_AWSIZE, + input S01_AXI_AWVALID, + output [0:0]S01_AXI_BID, + input S01_AXI_BREADY, + output [1:0]S01_AXI_BRESP, + output S01_AXI_BVALID, + output [63:0]S01_AXI_RDATA, + output [0:0]S01_AXI_RID, + output S01_AXI_RLAST, + input S01_AXI_RREADY, + output [1:0]S01_AXI_RRESP, + output S01_AXI_RVALID, + input [63:0]S01_AXI_WDATA, + input S01_AXI_WLAST, + output S01_AXI_WREADY, + input [7:0]S01_AXI_WSTRB, + input S01_AXI_WVALID, + input S02_AXI_ACLK, + input S02_AXI_ARESETN, + input [31:0]S02_AXI_ARADDR, + input [1:0]S02_AXI_ARBURST, + input [3:0]S02_AXI_ARCACHE, + input [0:0]S02_AXI_ARID, + input [7:0]S02_AXI_ARLEN, + input [0:0]S02_AXI_ARLOCK, + input [2:0]S02_AXI_ARPROT, + input [3:0]S02_AXI_ARQOS, + output S02_AXI_ARREADY, + input [3:0]S02_AXI_ARREGION, + input [2:0]S02_AXI_ARSIZE, + input S02_AXI_ARVALID, + input [31:0]S02_AXI_AWADDR, + input [1:0]S02_AXI_AWBURST, + input [3:0]S02_AXI_AWCACHE, + input [0:0]S02_AXI_AWID, + input [7:0]S02_AXI_AWLEN, + input [0:0]S02_AXI_AWLOCK, + input [2:0]S02_AXI_AWPROT, + input [3:0]S02_AXI_AWQOS, + output S02_AXI_AWREADY, + input [3:0]S02_AXI_AWREGION, + input [2:0]S02_AXI_AWSIZE, + input S02_AXI_AWVALID, + output [0:0]S02_AXI_BID, + input S02_AXI_BREADY, + output [1:0]S02_AXI_BRESP, + output S02_AXI_BVALID, + output [63:0]S02_AXI_RDATA, + output [0:0]S02_AXI_RID, + output S02_AXI_RLAST, + input S02_AXI_RREADY, + output [1:0]S02_AXI_RRESP, + output S02_AXI_RVALID, + input [63:0]S02_AXI_WDATA, + input S02_AXI_WLAST, + output S02_AXI_WREADY, + input [7:0]S02_AXI_WSTRB, + input S02_AXI_WVALID, + input S03_AXI_ACLK, + input S03_AXI_ARESETN, + input [31:0]S03_AXI_ARADDR, + input [1:0]S03_AXI_ARBURST, + input [3:0]S03_AXI_ARCACHE, + input [0:0]S03_AXI_ARID, + input [7:0]S03_AXI_ARLEN, + input [0:0]S03_AXI_ARLOCK, + input [2:0]S03_AXI_ARPROT, + input [3:0]S03_AXI_ARQOS, + output S03_AXI_ARREADY, + input [3:0]S03_AXI_ARREGION, + input [2:0]S03_AXI_ARSIZE, + input S03_AXI_ARVALID, + input [31:0]S03_AXI_AWADDR, + input [1:0]S03_AXI_AWBURST, + input [3:0]S03_AXI_AWCACHE, + input [0:0]S03_AXI_AWID, + input [7:0]S03_AXI_AWLEN, + input [0:0]S03_AXI_AWLOCK, + input [2:0]S03_AXI_AWPROT, + input [3:0]S03_AXI_AWQOS, + output S03_AXI_AWREADY, + input [3:0]S03_AXI_AWREGION, + input [2:0]S03_AXI_AWSIZE, + input S03_AXI_AWVALID, + output [0:0]S03_AXI_BID, + input S03_AXI_BREADY, + output [1:0]S03_AXI_BRESP, + output S03_AXI_BVALID, + output [63:0]S03_AXI_RDATA, + output [0:0]S03_AXI_RID, + output S03_AXI_RLAST, + input S03_AXI_RREADY, + output [1:0]S03_AXI_RRESP, + output S03_AXI_RVALID, + input [63:0]S03_AXI_WDATA, + input S03_AXI_WLAST, + output S03_AXI_WREADY, + input [7:0]S03_AXI_WSTRB, + input S03_AXI_WVALID +); + + axi_intercon_4x64_256_bd axi_intercon_4x64_256_bd_i ( + .M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID), + .S02_AXI_ACLK(S02_AXI_ACLK), + .S02_AXI_ARESETN(S02_AXI_ARESETN), + .S02_AXI_araddr(S02_AXI_ARADDR), + .S02_AXI_arburst(S02_AXI_ARBURST), + .S02_AXI_arcache(S02_AXI_ARCACHE), + .S02_AXI_arid(S02_AXI_ARID), + .S02_AXI_arlen(S02_AXI_ARLEN), + .S02_AXI_arlock(S02_AXI_ARLOCK), + .S02_AXI_arprot(S02_AXI_ARPROT), + .S02_AXI_arqos(S02_AXI_ARQOS), + .S02_AXI_arready(S02_AXI_ARREADY), + .S02_AXI_arregion(S02_AXI_ARREGION), + .S02_AXI_arsize(S02_AXI_ARSIZE), + .S02_AXI_arvalid(S02_AXI_ARVALID), + .S02_AXI_awaddr(S02_AXI_AWADDR), + .S02_AXI_awburst(S02_AXI_AWBURST), + .S02_AXI_awcache(S02_AXI_AWCACHE), + .S02_AXI_awid(S02_AXI_AWID), + .S02_AXI_awlen(S02_AXI_AWLEN), + .S02_AXI_awlock(S02_AXI_AWLOCK), + .S02_AXI_awprot(S02_AXI_AWPROT), + .S02_AXI_awqos(S02_AXI_AWQOS), + .S02_AXI_awready(S02_AXI_AWREADY), + .S02_AXI_awregion(S02_AXI_AWREGION), + .S02_AXI_awsize(S02_AXI_AWSIZE), + .S02_AXI_awvalid(S02_AXI_AWVALID), + .S02_AXI_bid(S02_AXI_BID), + .S02_AXI_bready(S02_AXI_BREADY), + .S02_AXI_bresp(S02_AXI_BRESP), + .S02_AXI_bvalid(S02_AXI_BVALID), + .S02_AXI_rdata(S02_AXI_RDATA), + .S02_AXI_rid(S02_AXI_RID), + .S02_AXI_rlast(S02_AXI_RLAST), + .S02_AXI_rready(S02_AXI_RREADY), + .S02_AXI_rresp(S02_AXI_RRESP), + .S02_AXI_rvalid(S02_AXI_RVALID), + .S02_AXI_wdata(S02_AXI_WDATA), + .S02_AXI_wlast(S02_AXI_WLAST), + .S02_AXI_wready(S02_AXI_WREADY), + .S02_AXI_wstrb(S02_AXI_WSTRB), + .S02_AXI_wvalid(S02_AXI_WVALID), + .S03_AXI_ACLK(S03_AXI_ACLK), + .S03_AXI_ARESETN(S03_AXI_ARESETN), + .S03_AXI_araddr(S03_AXI_ARADDR), + .S03_AXI_arburst(S03_AXI_ARBURST), + .S03_AXI_arcache(S03_AXI_ARCACHE), + .S03_AXI_arid(S03_AXI_ARID), + .S03_AXI_arlen(S03_AXI_ARLEN), + .S03_AXI_arlock(S03_AXI_ARLOCK), + .S03_AXI_arprot(S03_AXI_ARPROT), + .S03_AXI_arqos(S03_AXI_ARQOS), + .S03_AXI_arready(S03_AXI_ARREADY), + .S03_AXI_arregion(S03_AXI_ARREGION), + .S03_AXI_arsize(S03_AXI_ARSIZE), + .S03_AXI_arvalid(S03_AXI_ARVALID), + .S03_AXI_awaddr(S03_AXI_AWADDR), + .S03_AXI_awburst(S03_AXI_AWBURST), + .S03_AXI_awcache(S03_AXI_AWCACHE), + .S03_AXI_awid(S03_AXI_AWID), + .S03_AXI_awlen(S03_AXI_AWLEN), + .S03_AXI_awlock(S03_AXI_AWLOCK), + .S03_AXI_awprot(S03_AXI_AWPROT), + .S03_AXI_awqos(S03_AXI_AWQOS), + .S03_AXI_awready(S03_AXI_AWREADY), + .S03_AXI_awregion(S03_AXI_AWREGION), + .S03_AXI_awsize(S03_AXI_AWSIZE), + .S03_AXI_awvalid(S03_AXI_AWVALID), + .S03_AXI_bid(S03_AXI_BID), + .S03_AXI_bready(S03_AXI_BREADY), + .S03_AXI_bresp(S03_AXI_BRESP), + .S03_AXI_bvalid(S03_AXI_BVALID), + .S03_AXI_rdata(S03_AXI_RDATA), + .S03_AXI_rid(S03_AXI_RID), + .S03_AXI_rlast(S03_AXI_RLAST), + .S03_AXI_rready(S03_AXI_RREADY), + .S03_AXI_rresp(S03_AXI_RRESP), + .S03_AXI_rvalid(S03_AXI_RVALID), + .S03_AXI_wdata(S03_AXI_WDATA), + .S03_AXI_wlast(S03_AXI_WLAST), + .S03_AXI_wready(S03_AXI_WREADY), + .S03_AXI_wstrb(S03_AXI_WSTRB), + .S03_AXI_wvalid(S03_AXI_WVALID) + ); +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc new file mode 100644 index 000000000..a169c12bf --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2015 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCONNECT_SRCS = $(IP_BUILD_DIR)/axi_interconnect/axi_interconnect.xci + +IP_AXI_INTERCONNECT = $(addprefix $(IP_BUILD_DIR)/axi_interconnect/, \ +axi_interconnect.xci.out \ +synth/axi_interconnect.v \ +) + +$(IP_AXI_INTERCONNECT_SRCS) $(IP_AXI_INTERCONNECT_OUTS) : $(IP_DIR)/axi_interconnect/axi_interconnect.xci + $(call BUILD_VIVADO_IP,axi_interconnect,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci new file mode 100644 index 000000000..8af91b716 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axi_interconnect/axi_interconnect.xci @@ -0,0 +1,2674 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi_interconnect + + + + + + 10000000 + 0 + 0.000 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 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1 + 0 + 0x0000000e + 1 + 0 + 0 + 1 + 0 + 0x0000000f + 1 + 0 + 0 + 1 + 0 + 0 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 20 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc new file mode 100644 index 000000000..a78954885 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/Makefile.inc @@ -0,0 +1,14 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXIS_FIFO_TO_AXI4LITE_SRCS = $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + +IP_AXIS_FIFO_TO_AXI4LITE_OUTS = $(addprefix $(IP_BUILD_DIR)/axis_fifo_to_axi4lite/, \ +axis_fifo_to_axi4lite.xci.out \ +) + +$(IP_AXIS_FIFO_TO_AXI4LITE_SRCS) $(IP_AXIS_FIFO_TO_AXI4LITE_OUTS) : $(IP_DIR)/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci + $(call BUILD_VIVADO_IP,axis_fifo_to_axi4lite,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci new file mode 100644 index 000000000..80d8104d5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/axis_fifo_to_axi4lite/axis_fifo_to_axi4lite.xci @@ -0,0 +1,267 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axis_fifo_to_axi4lite + + + 4096 + 4096 + + 100000000 + 0 + 0.000 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0x80001000 + 0x80002FFF + 4 + 4 + 4 + 0x80000000 + 0 + zynq + 0 + 0 + 1 + 0 + 0 + 0x80000FFF + 32768 + 5 + 4091 + 32 + 32 + 32 + 4 + 2048 + 5 + 2043 + 0 + 1 + 0 + 0 + 1 + 0x80001000 + 0x80002FFF + 4 + 4 + 4 + XIL_AXI_STREAM_ETH_DATA + 32 + XIL_AXI_STREAM_ETH_CTRL + 32 + XIL_AXI_STREAM_ETH_DATA + 32 + 0x80000000 + 0 + false + false + true + false + false + 0x80000FFF + 32768 + 5 + 4091 + 0 + 32 + 32 + 32 + 4 + AXI4LITE + 2048 + 5 + 2043 + false + 1 + 0 + 0 + 1 + axis_fifo_to_axi4lite + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..e96eaf838 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2017 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_xc7z*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..f72f56759 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2648 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_32bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj new file mode 100644 index 000000000..495ca2a8b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z035ffg900-2.prj @@ -0,0 +1,164 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7z035-ffg900/-2 + 4.0 + Differential + No Buffer + ACTIVE LOW + FALSE + 0 + 50 Ohms + 0 + + 7z/xc7z035-ffg900 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 1538 + 1.8V + 4:1 + 100.03 + 0 + 650 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + TRUE + MT41K512M16XX-125 + 16 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 31 + 256 + 4 + 1 + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj new file mode 100644 index 000000000..ffad2f7f8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ddr3_32bit/mig_xc7z100ffg900-2.prj @@ -0,0 +1,164 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7z100-ffg900/-2 + 4.0 + Differential + No Buffer + ACTIVE LOW + FALSE + 0 + 50 Ohms + 0 + + 7z/xc7z035-ffg900 + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 1538 + 1.8V + 4:1 + 100.03 + 0 + 650 + 1.000 + 1 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + TRUE + MT41K512M16XX-125 + 16 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 31 + 256 + 4 + 1 + + + + diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..888840273 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 0 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + true + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..cc0f896b8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynq + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc new file mode 100644 index 000000000..14b705d1d --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_1TO2_SRCS = $(IP_BUILD_DIR)/hb47_1to2/hb47_1to2.xci + +IP_HB47_1TO2_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_1to2/, \ +hb47_1to2.xci.out \ +synth/hb47_1to2.vhd \ +) + +$(IP_HB47_1TO2_SRCS) $(IP_HB47_1TO2_OUTS) : $(IP_DIR)/hb47_1to2/hb47_1to2.xci + $(call BUILD_VIVADO_IP,hb47_1to2,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci new file mode 100644 index 000000000..a192027fb --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_1to2/hb47_1to2.xci @@ -0,0 +1,294 @@ + + + xilinx.com + xci + unknown + 1.0 + + + hb47_1to2 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 12 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 4 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35,35,35 + 35,35,35,35 + fixed + hb47_1to2.mif + 48 + 2 + 0 + 0,0,0,0 + 0,0,2,2 + 18,18,18,18 + 0 + 18 + 24 + 1 + 4 + hb47_1to2 + 0 + 0 + 1 + 0 + 0 + 16,16 + 0 + 0 + -0;-1;-0;-1 + 0,0,0,0 + 0,1,0,1 + 16,16,16,16 + 16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 0 + 29 + 2 + 1 + 0 + 96 + 1 + 1 + 1 + 24 + 1 + 47 + 0 + 0 + none;none + -0;-1;-0;-1 + 18,18,18,18 + 1 + 18 + 1 + 0,1,2,3 + 1 + 7 + 0 + 1 + 0 + 32 + 1 + zynq + 1 + false + false + Basic + 300.0 + Vector + -62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62 + Automatic + no_coe_file_loaded + 0 + false + 1 + Signed + Inferred + 18 + 24 + hb47_1to2 + Not_Required + 1 + Automatic + 0 + Signed + 16 + 1 + false + Systolic_Multiply_Accumulate + 1 + Interpolation + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 2 + true + Not_Required + Automatic + 1 + 1 + 2 + Area + None + None + Automatic + Non_Symmetric_Rounding_Up + 18 + 0.5 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Output_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + true + Not_Required + 0.5 + 0.001 + All + 1.0 + 0.5 + 1 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc new file mode 100644 index 000000000..293f64d3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_HB47_2TO1_SRCS = $(IP_BUILD_DIR)/hb47_2to1/hb47_2to1.xci + +IP_HB47_2TO1_OUTS = $(addprefix $(IP_BUILD_DIR)/hb47_2to1/, \ +hb47_2to1.xci.out \ +synth/hb47_2to1.vhd \ +) + +$(IP_HB47_2TO1_SRCS) $(IP_HB47_2TO1_OUTS) : $(IP_DIR)/hb47_2to1/hb47_2to1.xci $(IP_DIR)/hb47_2to1/hb47.coe + $(call BUILD_VIVADO_IP,hb47_2to1,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe new file mode 100644 index 000000000..4c9a6c406 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0 + 194, + 0, +-62; diff --git a/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci new file mode 100644 index 000000000..7a8522f9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/hb47_2to1/hb47_2to1.xci @@ -0,0 +1,310 @@ + + + xilinx.com + xci + unknown + 1.0 + + + hb47_2to1 + + + ACTIVE_LOW + + 100000000 + 0 + 0.000 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 6 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + 35,35 + 35,35,35,35 + fixed + hb47_2to1.mif + 47 + 2 + 0 + 0,0,0,0 + 0,0,0,0 + 18,18,18,18 + 0 + 18 + 47 + 1 + 4 + hb47_2to1 + 0 + 0 + 1 + 2 + 0 + 16,16,16,16 + 0 + 0 + -0,2;-1,3;0,-2;1,-3 + 0,0,0,0 + 0,1,2,3 + 16,16,16,16 + 16,16,16,16 + 16 + 1 + ./ + none + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 2 + 52 + 2 + 0 + 0 + 48 + 1 + 1 + 1 + 47 + 1 + 47 + 0 + 0 + none + 0,-2;1,-3 + 17,17 + 1 + 17 + 1 + 2,3,2,3 + 1 + 7 + 0 + 0 + 0 + 64 + 1 + zynq + 1 + false + false + Basic + 300.0 + COE_File + 6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 + Automatic + hb47.coe + 0 + false + 1 + Signed + Inferred + 18 + 47 + hb47_2to1 + Not_Required + 1 + Automatic + 0 + Signed + 16 + 2 + false + Systolic_Multiply_Accumulate + 1 + Decimation + Coregen + false + false + false + 1 + false + true + Automatic + 4 + 1 + false + Not_Required + Automatic + 1 + 1 + 2 + Area + None + None + Automatic + Non_Symmetric_Rounding_Up + 17 + 0.4 + 0.0 + P4-0,P4-1,P4-2,P4-3,P4-4 + Automatic + Integer_Coefficients + Input_Sample_Period + Integer + no_coe_file_loaded + true + Single + On_Vector + false + Not_Required + 0.5 + 0.001 + All + 1.0 + 0.59 + 1 + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc new file mode 100644 index 000000000..2caa3384b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/Makefile.inc @@ -0,0 +1,18 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_MISC_CLOCK_GEN_SRCS = $(IP_BUILD_DIR)/misc_clock_gen/misc_clock_gen.xci + +IP_MISC_CLOCK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/misc_clock_gen/, \ +misc_clock_gen.xci.out \ +misc_clock_gen.v \ +) + +# We have to patch the XDC file to remove constraints on the source clock for the module +# All timing constraints are handled in one place (timing.xdc) +$(IP_MISC_CLOCK_GEN_SRCS) $(IP_MISC_CLOCK_GEN_OUTS) : $(IP_DIR)/misc_clock_gen/misc_clock_gen.xci + $(call BUILD_VIVADO_IP,misc_clock_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + diff --git a/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci new file mode 100644 index 000000000..2a2cc31ef --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/misc_clock_gen/misc_clock_gen.xci @@ -0,0 +1,739 @@ + + + xilinx.com + xci + unknown + 1.0 + + + misc_clock_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 59.989999999999995 + 100.0 + 0000 + 0000 + 198.413 + 0000 + 0000 + 303.819 + BUFGCE + 50.0 + false + 198.413 + 0.000 + 50.0 + 198.412704761 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.0 + false + 303.819 + 0.000 + 50.0 + 305.55555 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFGCE + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + meas_clk + ddr3_dma_clk + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.6493506819332852 + 1.98412704761 + 1.98412704761 + 1.98412704761 + 1.98412704761 + 1.98412704761 + dout + drdy + dwe + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary________166.666667____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 21.875 + 0.000 + FALSE + 6.000 + 10.000 + 6.125 + 0.500 + 0.000 + FALSE + 4 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 3 + None + 0.010 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + meas_clk___198.413______0.000______50.0______113.755____141.292 + ddr3_dma_clk___303.819______0.000______50.0______105.705____141.292 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in + MMCM + AUTO + 166.666667 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + misc_clock_gen + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 59.989999999999995 + 0.010 + 100.0 + 0.010 + BUFGCE + 113.755 + false + 141.292 + 50.0 + 198.412704761 + 0.000 + 1 + true + BUFGCE + 105.705 + false + 141.292 + 50.0 + 305.55555 + 0.000 + 1 + true + BUFGCE + 81.390 + false + 326.622 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 81.390 + false + 326.622 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFGCE + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + meas_clk + false + ddr3_dma_clk + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + misc_clock_gen + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 21.875 + 0.000 + false + 6.000 + 10.000 + 6.125 + 0.500 + 0.000 + false + 4 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 3 + None + 0.010 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in + MMCM + mmcm_adv + 166.666667 + 0.010 + 10.000 + No_buffer + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + false + false + true + true + false + false + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc new file mode 100644 index 000000000..26f994676 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/Makefile.inc @@ -0,0 +1,35 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak +include $(LIB_DIR)/rfnoc/utils/Makefile.srcs + +IP_N310_PS_ORIG_SRCS = $(addprefix $(IP_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.tcl \ +chdr_dma_rx.tcl \ +chdr_dma_tx.tcl \ +chdr_dma_frame_size.tcl \ +chdr_dma_top.tcl \ +) + +IP_N310_PS_HDL_SRCS = $(RFNOC_UTIL_SRCS) + +IP_N310_PS_BD_SRCS = $(IP_BUILD_DIR)/n310_ps_bd/n310_ps_bd/n310_ps_bd.bd + +BD_N310_PS_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/n310_ps_bd/, \ +n310_ps_bd.bd.out \ +n310_ps_bd/n310_ps_bd_ooc.xdc \ +) + +$(IP_N310_PS_BD_SRCS) $(BD_N310_PS_BD_OUTS) $(IP_N310_PS_BDTCL_SRCS): $(IP_N310_PS_ORIG_SRCS) $(IP_N310_PS_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,n310_ps_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_N310_PS_HDL_SRCS)) + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl new file mode 100644 index 000000000..387f67d9c --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_frame_size.tcl @@ -0,0 +1,59 @@ +# Hierarchical cell: mtu +proc create_hier_cell_mtu { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_mtu() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create cells and wire everything up + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + connect_bd_net -net mtu_regs_1 [get_bd_pins mtu_regs] + # BUG: Vivado 2015.4 does not connect nets the first time with just the driver + connect_bd_net -quiet -net mtu_regs_1 [get_bd_pins mtu_regs] + + for {set i 0} {$i < $numPorts} {incr i} { + # Create instance: xlslice_0, and set properties + set xlslice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_$i ] + set_property -dict [ list \ + CONFIG.DIN_FROM [expr $i * 32 + 15] \ + CONFIG.DIN_TO [expr $i * 32] \ + CONFIG.DIN_WIDTH [expr $numPorts * 32] \ + CONFIG.DOUT_WIDTH {16} \ + ] $xlslice + + connect_bd_net -net mtu_regs_1 [get_bd_pins $xlslice/Din] + + create_bd_pin -dir O -from 15 -to 0 mtu$i + connect_bd_net [get_bd_pins mtu$i] [get_bd_pins $xlslice/Dout] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl new file mode 100644 index 000000000..500771071 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_rx.tcl @@ -0,0 +1,339 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_frame_size.tcl" + +proc create_hier_cell_rx_dma_channel { parentCell nameHier } { + + if { $parentCell eq "" || $nameHier eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_dest_axi + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi + + create_bd_pin -dir I -from 15 -to 0 frame_size + create_bd_pin -dir O -type intr irq + create_bd_pin -dir I -type rst m_dest_axi_aresetn + create_bd_pin -dir I -type clk s_axi_aclk + create_bd_pin -dir I -type rst s_axi_aresetn + create_bd_pin -dir I -type clk s_axis_aclk + + ######################### + # Instantiate IPs + ######################### + set reset_inv [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_inv ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + CONFIG.C_OPERATION {not} \ + ] $reset_inv + + set chdr_padder [ create_bd_cell -type module -reference chdr_pad_packet chdr_padder ] + set_property -dict [ list \ + CONFIG.CHDR_W {64} \ + ] $chdr_padder + set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_pins chdr_padder/rst] + + set axi_rx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_rx_dmac ] + set_property -dict [ list \ + CONFIG.ASYNC_CLK_DEST_REQ {true} \ + CONFIG.ASYNC_CLK_REQ_SRC {true} \ + CONFIG.ASYNC_CLK_SRC_DEST {false} \ + CONFIG.DMA_AXI_PROTOCOL_DEST {1} \ + CONFIG.DMA_TYPE_SRC {1} \ + CONFIG.SYNC_TRANSFER_START {false} \ + ] $axi_rx_dmac + + ######################### + # Wiring + ######################### + + # Top-level connections + connect_bd_net -net aclk_1 \ + [get_bd_pins s_axis_aclk] \ + [get_bd_pins chdr_padder/clk] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axis_aclk] + connect_bd_net -net aresetn_1 \ + [get_bd_pins m_dest_axi_aresetn] \ + [get_bd_pins reset_inv/Op1] \ + [get_bd_pins axi_rx_dmac/m_dest_axi_aresetn] + connect_bd_net -net areset_1 \ + [get_bd_pins reset_inv/Res] \ + [get_bd_pins chdr_padder/rst] + connect_bd_net -net s_axi_aclk_1 \ + [get_bd_pins s_axi_aclk] \ + [get_bd_pins axi_rx_dmac/s_axi_aclk] + connect_bd_net -net s_axi_aresetn_1 \ + [get_bd_pins s_axi_aresetn] \ + [get_bd_pins axi_rx_dmac/s_axi_aresetn] + connect_bd_net -net axi_rx_dmac_irq \ + [get_bd_pins irq] \ + [get_bd_pins axi_rx_dmac/irq] + connect_bd_net -net mtu \ + [get_bd_pins frame_size] \ + [get_bd_pins chdr_padder/len] + + # Control and DMA ports + connect_bd_intf_net -intf_net axi_rx_dmac_s_axi \ + [get_bd_intf_pins s_axi] \ + [get_bd_intf_pins axi_rx_dmac/s_axi] + connect_bd_intf_net -intf_net axi_rx_dmac_m_dest_axi \ + [get_bd_intf_pins m_dest_axi] \ + [get_bd_intf_pins axi_rx_dmac/m_dest_axi] + + # AXI-Stream ports + connect_bd_intf_net -intf_net s_axis_dma \ + [get_bd_intf_pins S_AXIS] \ + [get_bd_intf_pins chdr_padder/s_axis] + connect_bd_intf_net -intf_net s_axis_dma_padded \ + [get_bd_intf_pins chdr_padder/m_axis] \ + [get_bd_intf_pins axi_rx_dmac/s_axis] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: rx +proc create_hier_cell_rx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_rx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + create_bd_pin -dir I -from [expr $numPorts * 32 - 1] -to 0 mtu_regs + ######################### + # Instantiate IPs + ######################### + # For sharing one S_AXI_HP port across all RX DMA engines + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + CONFIG.R_REGISTER {1} \ + ] $axi_crossbar_0 + + # For fanning out AXI-Lite bus to all RX DMA engines + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + # Routes AXI-Stream to appropriate RX DMA engine + set axis_switch_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_switch:1.1 axis_switch_0 ] + set_property -dict [ list \ + CONFIG.DECODER_REG {1} \ + CONFIG.NUM_MI $numPorts \ + CONFIG.NUM_SI {1} \ + ] $axis_switch_0 + + # Cross domains from incoming AXI-Stream to RX DMA engines domain + # Note that the fifo_generator_0 is hard-coded to have 4 TDEST bits, so we + # are limited to 16 RX DMA channels + set fifo_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 fifo_generator_0 ] + set_property -dict [ list \ + CONFIG.Clock_Type_AXI {Independent_Clock} \ + CONFIG.Empty_Threshold_Assert_Value_axis {1021} \ + CONFIG.Empty_Threshold_Assert_Value_rach {13} \ + CONFIG.Empty_Threshold_Assert_Value_rdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wach {13} \ + CONFIG.Empty_Threshold_Assert_Value_wdch {1021} \ + CONFIG.Empty_Threshold_Assert_Value_wrch {13} \ + CONFIG.Enable_TLAST {true} \ + CONFIG.FIFO_Implementation_axis {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_rach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_rdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wach {Independent_Clocks_Distributed_RAM} \ + CONFIG.FIFO_Implementation_wdch {Independent_Clocks_Block_RAM} \ + CONFIG.FIFO_Implementation_wrch {Independent_Clocks_Distributed_RAM} \ + CONFIG.Full_Flags_Reset_Value {1} \ + CONFIG.Full_Threshold_Assert_Value_axis {1023} \ + CONFIG.Full_Threshold_Assert_Value_rach {15} \ + CONFIG.Full_Threshold_Assert_Value_wach {15} \ + CONFIG.Full_Threshold_Assert_Value_wrch {15} \ + CONFIG.HAS_TKEEP {false} \ + CONFIG.INTERFACE_TYPE {AXI_STREAM} \ + CONFIG.Input_Depth_axis {1024} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.TDATA_NUM_BYTES {8} \ + CONFIG.TDEST_WIDTH {4} \ + CONFIG.TKEEP_WIDTH {0} \ + CONFIG.TSTRB_WIDTH {8} \ + CONFIG.TUSER_WIDTH {0} \ + ] $fifo_generator_0 + + set rx_dmac_irq_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 rx_dmac_irq_concat ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $rx_dmac_irq_concat + + create_hier_cell_mtu $hier_obj mtu $numPorts + + ######################### + # Wiring + ######################### + connect_bd_intf_net -intf_net S00_AXIS_1 \ + [get_bd_intf_pins S_AXIS_DMA] \ + [get_bd_intf_pins fifo_generator_0/S_AXIS] + + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + + connect_bd_intf_net -intf_net fifo_generator_0_M_AXIS \ + [get_bd_intf_pins axis_switch_0/S00_AXIS] \ + [get_bd_intf_pins fifo_generator_0/M_AXIS] + + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + + connect_bd_net -net aresetn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins fifo_generator_0/s_aresetn] + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins fifo_generator_0/s_aclk] + + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] \ + [get_bd_pins axis_switch_0/aclk] \ + [get_bd_pins fifo_generator_0/m_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] \ + [get_bd_pins axis_switch_0/aresetn] + + connect_bd_net -net mtu_regs_1 \ + [get_bd_pins mtu_regs] \ + [get_bd_pins mtu/mtu_regs] + + connect_bd_net -net rx_dmac_irq_concat_dout \ + [get_bd_pins irq] \ + [get_bd_pins rx_dmac_irq_concat/dout] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + puts "Instantiating rx_dma port ${i}" + create_hier_cell_rx_dma_channel $hier_obj dma$i + + set_property -dict [ list \ + [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} \ + ] $axi_crossbar_0 + + connect_bd_intf_net -intf_net [format "axis_switch_0_M%02d_AXIS" ${i}] \ + [get_bd_intf_pins [format "axis_switch_0/M%02d_AXIS" ${i}]] \ + [get_bd_intf_pins dma${i}/S_AXIS] + + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/s_axi] + + connect_bd_intf_net -intf_net dma${i}_m_dest_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins dma${i}/m_dest_axi] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]] \ + [get_bd_pins dma${i}/s_axi_aclk] \ + [get_bd_pins dma${i}/s_axis_aclk] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins dma${i}/m_dest_axi_aresetn] \ + [get_bd_pins dma${i}/s_axi_aresetn] + + connect_bd_net -net dma${i}_irq \ + [get_bd_pins dma${i}/irq] \ + [get_bd_pins rx_dmac_irq_concat/In${i}] + + connect_bd_net -net frame_size_${i} \ + [get_bd_pins dma${i}/frame_size] \ + [get_bd_pins mtu/mtu${i}] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl new file mode 100644 index 000000000..9a4e832aa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_top.tcl @@ -0,0 +1,159 @@ +set scriptDir [file dirname [info script]] + +source "$scriptDir/chdr_dma_rx.tcl" +source "$scriptDir/chdr_dma_tx.tcl" + +# Hierarchical cell: dma +proc create_hier_cell_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_dma() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 2 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_RX_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_rx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_regfile + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O rx_irq + create_bd_pin -dir O tx_irq + + ######################### + # Instantiate IPs + ######################### + # Create instance: rx + create_hier_cell_rx_dma $hier_obj rx $numPorts + + # Create instance: tx + create_hier_cell_tx_dma $hier_obj tx $numPorts + + # Used to set frame size of RX DMA engines + set axi_regfile_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_regfile:1.0 axi_regfile_0 ] + set_property -dict [ list \ +CONFIG.NUM_REGS $numPorts \ + ] $axi_regfile_0 + + set util_reduced_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_0 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_0 + + set util_reduced_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 util_reduced_logic_1 ] + set_property -dict [ list \ +CONFIG.C_OPERATION {or} \ +CONFIG.C_SIZE $numPorts \ + ] $util_reduced_logic_1 + + ######################### + # Wiring + ######################### + # Clocks and resets + connect_bd_net -net bus_clk_1 \ + [get_bd_pins bus_clk] \ + [get_bd_pins rx/bus_clk] \ + [get_bd_pins tx/bus_clk] + connect_bd_net -net bus_rstn_1 \ + [get_bd_pins bus_rstn] \ + [get_bd_pins rx/bus_rstn] \ + [get_bd_pins tx/bus_rstn] + connect_bd_net -net clk40_1 \ + [get_bd_pins clk40] \ + [get_bd_pins rx/clk40] \ + [get_bd_pins tx/clk40] \ + [get_bd_pins axi_regfile_0/S_AXI_ACLK] + connect_bd_net -net clk40_rstn_1 \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_regfile_0/S_AXI_ARESETN] \ + [get_bd_pins rx/clk40_rstn] \ + [get_bd_pins tx/clk40_rstn] + + # AXI buses + connect_bd_intf_net -intf_net s_axi_rx_dmac_1 \ + [get_bd_intf_pins s_axi_rx_dmac] \ + [get_bd_intf_pins rx/s_axi_rx_dmac] + connect_bd_intf_net -intf_net rx_dma_M_AXI_RX_DMA \ + [get_bd_intf_pins M_AXI_RX_DMA] \ + [get_bd_intf_pins rx/M_AXI_RX_DMA] + connect_bd_intf_net -intf_net s_axi_tx_dmac_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins tx/s_axi_tx_dmac] + connect_bd_intf_net -intf_net tx_M_AXI_TX_DMA \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins tx/M_AXI_TX_DMA] + connect_bd_intf_net -intf_net s_axi_regfile_1 \ + [get_bd_intf_pins s_axi_regfile] \ + [get_bd_intf_pins axi_regfile_0/S_AXI] + + # RX CHDR + connect_bd_intf_net -intf_net s_axis_dma_1 \ + [get_bd_intf_pins s_axis_dma] \ + [get_bd_intf_pins rx/S_AXIS_DMA] + + # TX CHDR + connect_bd_intf_net -intf_net m_axis_dma_1 \ + [get_bd_intf_pins tx/M_AXIS_DMA] \ + [get_bd_intf_pins m_axis_dma] + + # IRQs and Frame Sizes + connect_bd_net -net frame_sizes \ + [get_bd_pins axi_regfile_0/regs] \ + [get_bd_pins rx/mtu_regs] + connect_bd_net -net rx_irq1 \ + [get_bd_pins rx/irq] \ + [get_bd_pins util_reduced_logic_0/Op1] + connect_bd_net -net tx_irq1 \ + [get_bd_pins tx/irq] \ + [get_bd_pins util_reduced_logic_1/Op1] + connect_bd_net -net util_reduced_logic_0_Res \ + [get_bd_pins rx_irq] \ + [get_bd_pins util_reduced_logic_0/Res] + connect_bd_net -net util_reduced_logic_1_Res \ + [get_bd_pins tx_irq] \ + [get_bd_pins util_reduced_logic_1/Res] + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl new file mode 100644 index 000000000..e2d160f69 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/chdr_dma_tx.tcl @@ -0,0 +1,193 @@ +# Hierarchical cell: tx +proc create_hier_cell_tx_dma { parentCell nameHier numPorts } { + + if { $parentCell eq "" || $nameHier eq "" || $numPorts eq "" } { + puts "ERROR: create_hier_cell_tx() - Empty argument(s)!" + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + if { $numPorts < 1 } { + puts "ERROR: numPorts invalid: $numPorts" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + ######################### + # Pin list + ######################### + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DMA + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_TX_DMA + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_tx_dmac + + create_bd_pin -dir I bus_clk + create_bd_pin -dir I bus_rstn + create_bd_pin -dir I clk40 + create_bd_pin -dir I clk40_rstn + create_bd_pin -dir O -from [expr $numPorts - 1] -to 0 irq + + ######################### + # Instantiate IPs + ######################### + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI $numPorts \ + ] $axi_interconnect_0 + + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts + ] $axi_crossbar_0 + + set axis_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_interconnect:2.1 axis_interconnect_0 ] + set_property -dict [ list \ + CONFIG.ARB_ON_TLAST {1} \ + CONFIG.ARB_ON_MAX_XFERS {0} \ + CONFIG.ENABLE_ADVANCED_OPTIONS {1} \ + CONFIG.M00_HAS_REGSLICE {1} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI $numPorts \ + ] $axis_interconnect_0 + + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS $numPorts \ + ] $xlconcat_0 + + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $xlconstant_0 + + ######################### + # Wiring + ######################### + connect_bd_net -net bus_clk \ + [get_bd_pins bus_clk] \ + [get_bd_pins axis_interconnect_0/ACLK] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ACLK] + connect_bd_net -net bus_rstn \ + [get_bd_pins bus_rstn] \ + [get_bd_pins axis_interconnect_0/ARESETN] \ + [get_bd_pins axis_interconnect_0/M00_AXIS_ARESETN] + connect_bd_net -net clk40 \ + [get_bd_pins clk40] \ + [get_bd_pins axi_crossbar_0/aclk] \ + [get_bd_pins axi_interconnect_0/ACLK] \ + [get_bd_pins axi_interconnect_0/S00_ACLK] + connect_bd_net -net clk40_rstn \ + [get_bd_pins clk40_rstn] \ + [get_bd_pins axi_crossbar_0/aresetn] \ + [get_bd_pins axi_interconnect_0/ARESETN] \ + [get_bd_pins axi_interconnect_0/S00_ARESETN] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconcat_0_dout \ + [get_bd_pins irq] \ + [get_bd_pins xlconcat_0/dout] + + connect_bd_intf_net -intf_net M_AXI_TX_DMAC_1 \ + [get_bd_intf_pins s_axi_tx_dmac] \ + [get_bd_intf_pins axi_interconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI \ + [get_bd_intf_pins M_AXI_TX_DMA] \ + [get_bd_intf_pins axi_crossbar_0/M00_AXI] + connect_bd_intf_net -intf_net axis_interconnect_0_M00_AXIS \ + [get_bd_intf_pins M_AXIS_DMA] \ + [get_bd_intf_pins axis_interconnect_0/M00_AXIS] + + ######################### + # Per-port Section + ######################### + for {set i 0} {$i < $numPorts} {incr i} { + # Configure each port on axi_crossbar and axis_interconnect + puts "Creating TX dma port ${i}" + set_property [format "CONFIG.S%02d_SINGLE_THREAD" ${i}] {1} $axi_crossbar_0 + set_property -dict [ list \ + [format "CONFIG.S%02d_HAS_REGSLICE" ${i}] {1} \ + ] $axis_interconnect_0 + + set axi_tx_dmac [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_tx_dmac_$i ] + set_property -dict [ list \ + CONFIG.DMA_TYPE_DEST {1} \ + CONFIG.DMA_TYPE_SRC {0} \ + ] $axi_tx_dmac + + # Add a tuser signal indicating which DMA channel originated the packet + # Hard-coded to handle up to 16 DMA channels + # Convert i (in decimal) to 4-bit binary: + binary scan [binary format c ${i}] B* i_binary + set i_binary [string range ${i_binary} end-3 end] + + set tuser_appender [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_${i} ] + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH.VALUE_SRC USER \ + ] $tuser_appender + set_property -dict [ list \ + CONFIG.M_TUSER_WIDTH {4} \ + CONFIG.TUSER_REMAP 4'b${i_binary} \ + ] $tuser_appender + + connect_bd_intf_net -intf_net [format "axis_subset_converter_%d_S_AXIS" ${i}] \ + [get_bd_intf_pins $axi_tx_dmac/m_axis] \ + [get_bd_intf_pins ${tuser_appender}/S_AXIS] + connect_bd_intf_net -intf_net [format "S%02d_AXIS_1" ${i}] \ + [get_bd_intf_pins ${tuser_appender}/M_AXIS] \ + [get_bd_intf_pins [format "axis_interconnect_0/S%02d_AXIS" ${i}]] + connect_bd_intf_net -intf_net axi_dmac_${i}_m_src_axi \ + [get_bd_intf_pins [format "axi_crossbar_0/S%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/m_src_axi] + connect_bd_intf_net -intf_net [format "axi_interconnect_0_M%02d_AXI" ${i}] \ + [get_bd_intf_pins [format "axi_interconnect_0/M%02d_AXI" ${i}]] \ + [get_bd_intf_pins $axi_tx_dmac/s_axi] + + connect_bd_net [get_bd_pins $axi_tx_dmac/irq] [get_bd_pins xlconcat_0/In${i}] + + connect_bd_net -net clk40 \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ACLK" ${i}]]\ + [get_bd_pins $axi_tx_dmac/m_axis_aclk] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aclk] \ + [get_bd_pins $axi_tx_dmac/s_axi_aclk] \ + [get_bd_pins $tuser_appender/aclk] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ACLK" ${i}]] + + connect_bd_net -net clk40_rstn \ + [get_bd_pins [format "axi_interconnect_0/M%02d_ARESETN" ${i}]] \ + [get_bd_pins $axi_tx_dmac/m_src_axi_aresetn] \ + [get_bd_pins $axi_tx_dmac/s_axi_aresetn] \ + [get_bd_pins $tuser_appender/aresetn] \ + [get_bd_pins [format "axis_interconnect_0/S%02d_AXIS_ARESETN" ${i}]] + + connect_bd_net -net xlconstant_0_dout \ + [get_bd_pins [format "axis_interconnect_0/S%02d_ARB_REQ_SUPPRESS" ${i}]] + } + + # Restore current instance + current_bd_instance $oldCurInst +} + + diff --git a/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl new file mode 100644 index 000000000..b3516e2fa --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/n310_ps_bd/n310_ps_bd.tcl @@ -0,0 +1,726 @@ +# CHANGE DESIGN NAME HERE +set design_name n310_ps_bd + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +create_bd_design $design_name +current_bd_design $design_name + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +set scriptDir [file dirname [info script]] + +################################################################## +# DESIGN PROCs +################################################################## +source "$scriptDir/chdr_dma_top.tcl" + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ] + set m_axis_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_dma ] + set s_axis_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_dma ] + set_property -dict [ list \ + CONFIG.HAS_TLAST 1 \ + CONFIG.TDATA_NUM_BYTES 8 \ + CONFIG.TDEST_WIDTH 4 \ + ] $s_axis_dma + set WR_UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 WR_UART ] + set M_AXI_ETH_DMA0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA0 + set M_AXI_WR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_WR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {62500000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_WR + set M_AXI_ETH_DMA1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_ETH_DMA1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_ETH_DMA1 + set M_AXI_JESD0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD0 + set M_AXI_JESD1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_JESD1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_JESD1 + set M_AXI_NET0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET0 + set M_AXI_NET1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET1 + set M_AXI_NET2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_NET2 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_NET2 + set M_AXI_XBAR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_XBAR ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BURST {0} \ +CONFIG.HAS_CACHE {0} \ +CONFIG.HAS_LOCK {0} \ +CONFIG.HAS_PROT {0} \ +CONFIG.HAS_QOS {0} \ +CONFIG.HAS_WSTRB {0} \ +CONFIG.NUM_READ_OUTSTANDING {2} \ +CONFIG.NUM_WRITE_OUTSTANDING {2} \ +CONFIG.PROTOCOL {AXI4LITE} \ + ] $M_AXI_XBAR + set S_AXI_GP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP0 + set S_AXI_GP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {32} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_GP1 + set S_AXI_HP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP0 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP0 + set S_AXI_HP1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_HP1 ] + set_property -dict [ list \ +CONFIG.ADDR_WIDTH {32} \ +CONFIG.ARUSER_WIDTH {0} \ +CONFIG.AWUSER_WIDTH {0} \ +CONFIG.BUSER_WIDTH {0} \ +CONFIG.DATA_WIDTH {64} \ +CONFIG.FREQ_HZ {40000000} \ +CONFIG.HAS_BRESP {1} \ +CONFIG.HAS_BURST {1} \ +CONFIG.HAS_CACHE {1} \ +CONFIG.HAS_LOCK {1} \ +CONFIG.HAS_PROT {1} \ +CONFIG.HAS_QOS {1} \ +CONFIG.HAS_REGION {0} \ +CONFIG.HAS_RRESP {1} \ +CONFIG.HAS_WSTRB {1} \ +CONFIG.ID_WIDTH {5} \ +CONFIG.MAX_BURST_LENGTH {16} \ +CONFIG.NUM_READ_OUTSTANDING {8} \ +CONFIG.NUM_WRITE_OUTSTANDING {8} \ +CONFIG.PROTOCOL {AXI4} \ +CONFIG.READ_WRITE_MODE {READ_WRITE} \ +CONFIG.RUSER_WIDTH {0} \ +CONFIG.SUPPORTS_NARROW_BURST {1} \ +CONFIG.WUSER_WIDTH {0} \ + ] $S_AXI_HP1 + set USBIND_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:usbctrl_rtl:1.0 USBIND_0 ] + + # Create ports + set DDR_VRN [ create_bd_port -dir IO DDR_VRN ] + set DDR_VRP [ create_bd_port -dir IO DDR_VRP ] + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_CLK2 [ create_bd_port -dir O -type clk FCLK_CLK2 ] + set FCLK_CLK3 [ create_bd_port -dir O -type clk FCLK_CLK3 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set FCLK_RESET1_N [ create_bd_port -dir O -type rst FCLK_RESET1_N ] + set FCLK_RESET2_N [ create_bd_port -dir O -type rst FCLK_RESET2_N ] + set FCLK_RESET3_N [ create_bd_port -dir O -type rst FCLK_RESET3_N ] + set IRQ_F2P [ create_bd_port -dir I -from 15 -to 0 -type intr IRQ_F2P ] + set_property -dict [ list \ +CONFIG.PortWidth {16} \ +CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $IRQ_F2P + set MIO [ create_bd_port -dir IO -from 53 -to 0 MIO ] + set PS_CLK [ create_bd_port -dir IO PS_CLK ] + set PS_PORB [ create_bd_port -dir IO PS_PORB ] + set PS_SRSTB [ create_bd_port -dir IO PS_SRSTB ] + set SPI0_MISO_I [ create_bd_port -dir I SPI0_MISO_I ] + set SPI0_MISO_O [ create_bd_port -dir O SPI0_MISO_O ] + set SPI0_MISO_T [ create_bd_port -dir O SPI0_MISO_T ] + set SPI0_MOSI_I [ create_bd_port -dir I SPI0_MOSI_I ] + set SPI0_MOSI_O [ create_bd_port -dir O SPI0_MOSI_O ] + set SPI0_MOSI_T [ create_bd_port -dir O SPI0_MOSI_T ] + set SPI0_SCLK_I [ create_bd_port -dir I SPI0_SCLK_I ] + set SPI0_SCLK_O [ create_bd_port -dir O SPI0_SCLK_O ] + set SPI0_SCLK_T [ create_bd_port -dir O SPI0_SCLK_T ] + set SPI0_SS1_O [ create_bd_port -dir O SPI0_SS1_O ] + set SPI0_SS2_O [ create_bd_port -dir O SPI0_SS2_O ] + set SPI0_SS_I [ create_bd_port -dir I SPI0_SS_I ] + set SPI0_SS_O [ create_bd_port -dir O SPI0_SS_O ] + set SPI0_SS_T [ create_bd_port -dir O SPI0_SS_T ] + set SPI1_MISO_I [ create_bd_port -dir I SPI1_MISO_I ] + set SPI1_MISO_O [ create_bd_port -dir O SPI1_MISO_O ] + set SPI1_MISO_T [ create_bd_port -dir O SPI1_MISO_T ] + set SPI1_MOSI_I [ create_bd_port -dir I SPI1_MOSI_I ] + set SPI1_MOSI_O [ create_bd_port -dir O SPI1_MOSI_O ] + set SPI1_MOSI_T [ create_bd_port -dir O SPI1_MOSI_T ] + set SPI1_SCLK_I [ create_bd_port -dir I SPI1_SCLK_I ] + set SPI1_SCLK_O [ create_bd_port -dir O SPI1_SCLK_O ] + set SPI1_SCLK_T [ create_bd_port -dir O SPI1_SCLK_T ] + set SPI1_SS1_O [ create_bd_port -dir O SPI1_SS1_O ] + set SPI1_SS2_O [ create_bd_port -dir O SPI1_SS2_O ] + set SPI1_SS_I [ create_bd_port -dir I SPI1_SS_I ] + set SPI1_SS_O [ create_bd_port -dir O SPI1_SS_O ] + set SPI1_SS_T [ create_bd_port -dir O SPI1_SS_T ] + set JTAG0_TCK [ create_bd_port -dir IO JTAG0_TCK ] + set JTAG0_TMS [ create_bd_port -dir IO JTAG0_TMS ] + set JTAG0_TDI [ create_bd_port -dir IO JTAG0_TDI ] + set JTAG0_TDO [ create_bd_port -dir I JTAG0_TDO ] + set JTAG1_TCK [ create_bd_port -dir IO JTAG1_TCK ] + set JTAG1_TMS [ create_bd_port -dir IO JTAG1_TMS ] + set JTAG1_TDI [ create_bd_port -dir IO JTAG1_TDI ] + set JTAG1_TDO [ create_bd_port -dir I JTAG1_TDO ] + set S_AXI_GP0_ACLK [ create_bd_port -dir I -type clk S_AXI_GP0_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP0_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP0_ACLK + set S_AXI_GP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP0_ARESETN ] + set S_AXI_GP1_ACLK [ create_bd_port -dir I -type clk S_AXI_GP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_GP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_GP1_ACLK + set S_AXI_GP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_GP1_ARESETN ] + set S_AXI_HP0_ACLK [ create_bd_port -dir I -type clk S_AXI_HP0_ACLK ] + set_property -dict [ list \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP0_ACLK + set S_AXI_HP0_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP0_ARESETN ] + set S_AXI_HP1_ACLK [ create_bd_port -dir I -type clk S_AXI_HP1_ACLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_RESET {S_AXI_HP1_ARESETN} \ +CONFIG.FREQ_HZ {40000000} \ + ] $S_AXI_HP1_ACLK + set S_AXI_HP1_ARESETN [ create_bd_port -dir I -type rst S_AXI_HP1_ARESETN ] + set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {m_axis_dma:s_axis_dma} \ +CONFIG.ASSOCIATED_RESET {bus_rstn} \ +CONFIG.FREQ_HZ {200000000} \ + ] $bus_clk + set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] + + set M_AXI_WR_CLK [ create_bd_port -dir I -type clk M_AXI_WR_CLK ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_WR} \ +CONFIG.ASSOCIATED_RESET {M_AXI_WR_RSTn} \ +CONFIG.FREQ_HZ {62500000} \ + ] $M_AXI_WR_CLK + set M_AXI_WR_RSTn [ create_bd_port -dir I -type rst M_AXI_WR_RSTn ] + + set clk40 [ create_bd_port -dir I -type clk clk40 ] + set_property -dict [ list \ +CONFIG.ASSOCIATED_BUSIF {M_AXI_NET0:M_AXI_NET1:M_AXI_XBAR:M_AXI_JESD0:M_AXI_JESD1:M_AXI_ETH_DMA0:M_AXI_ETH_DMA1:M_AXI_NET2} \ +CONFIG.ASSOCIATED_RESET {clk40_rstn} \ +CONFIG.FREQ_HZ {40000000} \ + ] $clk40 + set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] + + create_bd_port -dir I qsfp_sda_i + create_bd_port -dir O qsfp_sda_o + create_bd_port -dir O qsfp_sda_t + create_bd_port -dir I qsfp_scl_i + create_bd_port -dir O qsfp_scl_o + create_bd_port -dir O qsfp_scl_t + + # Create instance: axi_interconnect_hp0, and set properties + set axi_interconnect_hp0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp0 + + set axi_interconnect_hp1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_hp1 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {1} \ +CONFIG.NUM_SI {2} \ + ] $axi_interconnect_hp1 + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ +CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ +CONFIG.NUM_MI {16} \ + ] $axi_interconnect_0 + + # Create instance: axi_uartlite_0, and set properties + set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ +CONFIG.C_BAUDRATE {115200} \ + ] $axi_uartlite_0 + + # Create instance: dma + create_hier_cell_dma [current_bd_instance .] dma 10 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ +CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {800} \ +CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ +CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ +CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_ENABLE {1} \ +CONFIG.PCW_ENET0_RESET_IO {MIO 6} \ +CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} \ +CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_RST1_PORT {1} \ +CONFIG.PCW_EN_RST2_PORT {1} \ +CONFIG.PCW_EN_RST3_PORT {1} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {40} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {166.6667} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_ENABLE {1} \ +CONFIG.PCW_I2C0_RESET_IO {MIO 3} \ +CONFIG.PCW_IRQ_F2P_INTR {1} \ +CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_PJTAG_PJTAG_IO {MIO 10 .. 13} \ +CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ +CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.096} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.102} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.100} \ +CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.090} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.054} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.040} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.041} \ +CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.010} \ +CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 7} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ +CONFIG.PCW_USE_S_AXI_GP0 {0} \ +CONFIG.PCW_USE_S_AXI_GP1 {0} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ +CONFIG.PCW_USE_S_AXI_HP2 {1} \ +CONFIG.PCW_USE_S_AXI_HP3 {1} \ + ] $processing_system7_0 + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ +CONFIG.IN0_WIDTH {8} \ +CONFIG.NUM_PORTS {9} \ + ] $xlconcat_0 + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {7} \ +CONFIG.DIN_TO {0} \ +CONFIG.DIN_WIDTH {16} \ +CONFIG.DOUT_WIDTH {8} \ + ] $xlslice_2 + + # Create instance: jtag_0, jtag_1 + set jtag_0 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_0 ] + set jtag_1 [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 jtag_1 ] + + # Create instance: axi_iic_0 for QSFP i2c + set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ] + + + # Create interface connections + connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net S_AXI_GP0_1 [get_bd_intf_ports S_AXI_GP0] [get_bd_intf_pins axi_interconnect_hp0/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_GP1_1 [get_bd_intf_ports S_AXI_GP1] [get_bd_intf_pins axi_interconnect_hp1/S01_AXI] + connect_bd_intf_net -intf_net S_AXI_HP0_1 [get_bd_intf_ports S_AXI_HP0] [get_bd_intf_pins axi_interconnect_hp0/S00_AXI] + connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports S_AXI_HP1] [get_bd_intf_pins axi_interconnect_hp1/S00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports M_AXI_ETH_DMA0] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports M_AXI_NET0] [get_bd_intf_pins axi_interconnect_0/M01_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports M_AXI_ETH_DMA1] [get_bd_intf_pins axi_interconnect_0/M02_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports M_AXI_NET1] [get_bd_intf_pins axi_interconnect_0/M03_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports M_AXI_XBAR] [get_bd_intf_pins axi_interconnect_0/M04_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports M_AXI_JESD0] [get_bd_intf_pins axi_interconnect_0/M05_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports M_AXI_JESD1] [get_bd_intf_pins axi_interconnect_0/M06_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports M_AXI_NET2] [get_bd_intf_pins axi_interconnect_0/M07_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_pins axi_interconnect_0/M08_AXI] [get_bd_intf_pins dma/s_axi_rx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_pins axi_interconnect_0/M09_AXI] [get_bd_intf_pins dma/s_axi_tx_dmac] + connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_pins axi_interconnect_0/M10_AXI] [get_bd_intf_pins dma/s_axi_regfile] + connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_pins jtag_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M11_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M12_AXI [get_bd_intf_pins jtag_1/S_AXI] [get_bd_intf_pins axi_interconnect_0/M12_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M13_AXI [get_bd_intf_pins axi_interconnect_0/M13_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M14_AXI [get_bd_intf_ports M_AXI_WR] [get_bd_intf_pins axi_interconnect_0/M14_AXI] + connect_bd_intf_net -intf_net axi_interconnect_0_M15_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M15_AXI] + + connect_bd_intf_net -intf_net axi_protocol_converter_hp0_M_AXI [get_bd_intf_pins axi_interconnect_hp0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + connect_bd_intf_net -intf_net axi_protocol_converter_hp1_M_AXI [get_bd_intf_pins axi_interconnect_hp1/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP1] + connect_bd_intf_net -intf_net dma_M_AXI_RX_DMA [get_bd_intf_pins dma/M_AXI_RX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP2] + connect_bd_intf_net -intf_net dma_M_AXI_TX_DMA [get_bd_intf_pins dma/M_AXI_TX_DMA] [get_bd_intf_pins processing_system7_0/S_AXI_HP3] + connect_bd_intf_net -intf_net s_axis_dma_1 [get_bd_intf_ports s_axis_dma] [get_bd_intf_pins dma/s_axis_dma] + connect_bd_intf_net -intf_net m_axis_dma_1 [get_bd_intf_ports m_axis_dma] [get_bd_intf_pins dma/m_axis_dma] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_USBIND_0 [get_bd_intf_ports USBIND_0] [get_bd_intf_pins processing_system7_0/USBIND_0] + connect_bd_intf_net -intf_net WR_UART [get_bd_intf_ports WR_UART] [get_bd_intf_pins axi_uartlite_0/UART] + + # Create port connections + connect_bd_net -net IRQ_F2P_1 [get_bd_ports IRQ_F2P] [get_bd_pins xlslice_2/Din] + connect_bd_net -net SPI0_MISO_I_1 [get_bd_ports SPI0_MISO_I] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MOSI_I_1 [get_bd_ports SPI0_MOSI_I] [get_bd_pins processing_system7_0/SPI0_MOSI_I] + connect_bd_net -net SPI0_SCLK_I_1 [get_bd_ports SPI0_SCLK_I] [get_bd_pins processing_system7_0/SPI0_SCLK_I] + connect_bd_net -net SPI0_SS_I_1 [get_bd_ports SPI0_SS_I] [get_bd_pins processing_system7_0/SPI0_SS_I] + connect_bd_net -net SPI1_MISO_I_1 [get_bd_ports SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] + connect_bd_net -net SPI1_MOSI_I_1 [get_bd_ports SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] + connect_bd_net -net SPI1_SCLK_I_1 [get_bd_ports SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] + connect_bd_net -net SPI1_SS_I_1 [get_bd_ports SPI1_SS_I] [get_bd_pins processing_system7_0/SPI1_SS_I] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_pins axi_interconnect_hp0/S01_ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_pins axi_interconnect_hp0/S01_ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_pins axi_interconnect_hp1/S01_ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_pins axi_interconnect_hp1/S01_ARESETN] + connect_bd_net -net S_AXI_HP0_ACLK_1 [get_bd_ports S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/M00_ACLK] [get_bd_pins axi_interconnect_hp0/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins axi_interconnect_hp0/ACLK] + connect_bd_net -net S_AXI_HP0_ARESETN_1 [get_bd_ports S_AXI_HP0_ARESETN] [get_bd_pins axi_interconnect_hp0/M00_ARESETN] [get_bd_pins axi_interconnect_hp0/S00_ARESETN] [get_bd_pins axi_interconnect_hp0/ARESETN] + connect_bd_net -net S_AXI_HP1_ACLK_1 [get_bd_ports S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/M00_ACLK] [get_bd_pins axi_interconnect_hp1/S00_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins axi_interconnect_hp1/ACLK] + connect_bd_net -net S_AXI_HP1_ARESETN_1 [get_bd_ports S_AXI_HP1_ARESETN] [get_bd_pins axi_interconnect_hp1/M00_ARESETN] [get_bd_pins axi_interconnect_hp1/S00_ARESETN] [get_bd_pins axi_interconnect_hp1/ARESETN] + connect_bd_net -net bus_clk [get_bd_ports bus_clk] [get_bd_pins dma/bus_clk] + connect_bd_net -net bus_rstn [get_bd_ports bus_rstn] [get_bd_pins dma/bus_rstn] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins dma/clk40] [get_bd_pins processing_system7_0/S_AXI_HP2_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP3_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/M12_ACLK] [get_bd_pins axi_interconnect_0/M15_ACLK] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/M12_ARESETN] [get_bd_pins axi_interconnect_0/M15_ARESETN] [get_bd_pins dma/clk40_rstn] + connect_bd_net -net M_AXI_WR_CLK [get_bd_ports M_AXI_WR_CLK] [get_bd_pins axi_interconnect_0/M14_ACLK] + connect_bd_net -net M_AXI_WR_RSTn [get_bd_ports M_AXI_WR_RSTn] [get_bd_pins axi_interconnect_0/M14_ARESETN] + connect_bd_net -net ddr_vrn [get_bd_ports DDR_VRN] [get_bd_pins processing_system7_0/DDR_VRN] + connect_bd_net -net ddr_vrp [get_bd_ports DDR_VRP] [get_bd_pins processing_system7_0/DDR_VRP] + connect_bd_net -net dma_tx_irq [get_bd_pins dma/tx_irq] [get_bd_pins xlconcat_0/In2] + connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins jtag_0/S_AXI_ACLK] [get_bd_pins jtag_1/S_AXI_ACLK] [get_bd_pins axi_iic_0/s_axi_aclk] + connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins jtag_0/S_AXI_ARESETN] [get_bd_pins jtag_1/S_AXI_ARESETN] [get_bd_pins axi_iic_0/s_axi_aresetn] + connect_bd_net -net mio [get_bd_ports MIO] [get_bd_pins processing_system7_0/MIO] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports FCLK_CLK2] [get_bd_pins processing_system7_0/FCLK_CLK2] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_ports FCLK_CLK3] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_ports FCLK_RESET1_N] [get_bd_pins processing_system7_0/FCLK_RESET1_N] + connect_bd_net -net processing_system7_0_FCLK_RESET2_N [get_bd_ports FCLK_RESET2_N] [get_bd_pins processing_system7_0/FCLK_RESET2_N] + connect_bd_net -net processing_system7_0_FCLK_RESET3_N [get_bd_ports FCLK_RESET3_N] [get_bd_pins processing_system7_0/FCLK_RESET3_N] + connect_bd_net -net processing_system7_0_SPI0_MISO_O [get_bd_ports SPI0_MISO_O] [get_bd_pins processing_system7_0/SPI0_MISO_O] + connect_bd_net -net processing_system7_0_SPI0_MISO_T [get_bd_ports SPI0_MISO_T] [get_bd_pins processing_system7_0/SPI0_MISO_T] + connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_O] [get_bd_pins processing_system7_0/SPI0_MOSI_O] + connect_bd_net -net processing_system7_0_SPI0_MOSI_T [get_bd_ports SPI0_MOSI_T] [get_bd_pins processing_system7_0/SPI0_MOSI_T] + connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_O] [get_bd_pins processing_system7_0/SPI0_SCLK_O] + connect_bd_net -net processing_system7_0_SPI0_SCLK_T [get_bd_ports SPI0_SCLK_T] [get_bd_pins processing_system7_0/SPI0_SCLK_T] + connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_SS1_O] [get_bd_pins processing_system7_0/SPI0_SS1_O] + connect_bd_net -net processing_system7_0_SPI0_SS2_O [get_bd_ports SPI0_SS2_O] [get_bd_pins processing_system7_0/SPI0_SS2_O] + connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_SS_O] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI0_SS_T [get_bd_ports SPI0_SS_T] [get_bd_pins processing_system7_0/SPI0_SS_T] + connect_bd_net -net processing_system7_0_SPI1_MISO_O [get_bd_ports SPI1_MISO_O] [get_bd_pins processing_system7_0/SPI1_MISO_O] + connect_bd_net -net processing_system7_0_SPI1_MISO_T [get_bd_ports SPI1_MISO_T] [get_bd_pins processing_system7_0/SPI1_MISO_T] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI1_MOSI_O] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_T [get_bd_ports SPI1_MOSI_T] [get_bd_pins processing_system7_0/SPI1_MOSI_T] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI1_SCLK_O] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_T [get_bd_ports SPI1_SCLK_T] [get_bd_pins processing_system7_0/SPI1_SCLK_T] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI1_SS1_O] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS2_O [get_bd_ports SPI1_SS2_O] [get_bd_pins processing_system7_0/SPI1_SS2_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI1_SS_O] [get_bd_pins processing_system7_0/SPI1_SS_O] + connect_bd_net -net processing_system7_0_SPI1_SS_T [get_bd_ports SPI1_SS_T] [get_bd_pins processing_system7_0/SPI1_SS_T] + connect_bd_net -net ps_clk [get_bd_ports PS_CLK] [get_bd_pins processing_system7_0/PS_CLK] + connect_bd_net -net ps_porb [get_bd_ports PS_PORB] [get_bd_pins processing_system7_0/PS_PORB] + connect_bd_net -net ps_srstb [get_bd_ports PS_SRSTB] [get_bd_pins processing_system7_0/PS_SRSTB] + connect_bd_net -net rx_dma_irq [get_bd_pins dma/rx_irq] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlconcat_0/In0] [get_bd_pins xlslice_2/Dout] + connect_bd_net -net JTAG0_TCK [get_bd_ports JTAG0_TCK] [get_bd_pins jtag_0/bit_clk] + connect_bd_net -net JTAG0_TMS [get_bd_ports JTAG0_TMS] [get_bd_pins jtag_0/bit_stb] + connect_bd_net -net JTAG0_TDI [get_bd_ports JTAG0_TDI] [get_bd_pins jtag_0/bit_out] + connect_bd_net -net JTAG0_TDO [get_bd_ports JTAG0_TDO] [get_bd_pins jtag_0/bit_in] + connect_bd_net -net JTAG1_TCK [get_bd_ports JTAG1_TCK] [get_bd_pins jtag_1/bit_clk] + connect_bd_net -net JTAG1_TMS [get_bd_ports JTAG1_TMS] [get_bd_pins jtag_1/bit_stb] + connect_bd_net -net JTAG1_TDI [get_bd_ports JTAG1_TDI] [get_bd_pins jtag_1/bit_out] + connect_bd_net -net JTAG1_TDO [get_bd_ports JTAG1_TDO] [get_bd_pins jtag_1/bit_in] + connect_bd_net [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In3] + connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins xlconcat_0/In4] + connect_bd_net -net qsfp_sda_i [get_bd_pins axi_iic_0/sda_i] [get_bd_ports qsfp_sda_i] + connect_bd_net -net qsfp_sda_o [get_bd_pins axi_iic_0/sda_o] [get_bd_ports qsfp_sda_o] + connect_bd_net -net qsfp_sda_t [get_bd_pins axi_iic_0/sda_t] [get_bd_ports qsfp_sda_t] + connect_bd_net -net qsfp_scl_i [get_bd_pins axi_iic_0/scl_i] [get_bd_ports qsfp_scl_i] + connect_bd_net -net qsfp_scl_o [get_bd_pins axi_iic_0/scl_o] [get_bd_ports qsfp_scl_o] + connect_bd_net -net qsfp_scl_t [get_bd_pins axi_iic_0/scl_t] [get_bd_ports qsfp_scl_t] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_uartlite_0/s_axi_aclk] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] + connect_bd_net [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/M13_ACLK] + connect_bd_net [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/M13_ARESETN] + + # Create address segments + create_bd_addr_seg -range 0x4000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA0/Reg] SEG_M_AXI_ETH_DMA0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40008000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_ETH_DMA1/Reg] SEG_M_AXI_ETH_DMA1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40014000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD0/Reg] SEG_M_AXI_JESD0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40004000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET0/Reg] SEG_M_AXI_NET0_Reg + create_bd_addr_seg -range 0x4000 -offset 0x4000C000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET1/Reg] SEG_M_AXI_NET1_Reg + create_bd_addr_seg -range 0x20000 -offset 0x40020000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_NET2/Reg] SEG_M_AXI_NET2_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40018000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_JESD1/Reg] SEG_M_AXI_JESD1_Reg + create_bd_addr_seg -range 0x4000 -offset 0x40010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_XBAR/Reg] SEG_M_AXI_XBAR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43CA0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_0/s_axi/axi_lite] SEG_axi_dmac_0_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CB0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_1/s_axi/axi_lite] SEG_axi_dmac_1_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CC0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_2/s_axi/axi_lite] SEG_axi_dmac_2_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CD0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_3/s_axi/axi_lite] SEG_axi_dmac_3_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CE0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_4/s_axi/axi_lite] SEG_axi_dmac_4_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43CF0000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_5/s_axi/axi_lite] SEG_axi_dmac_5_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_6/s_axi/axi_lite] SEG_axi_dmac_6_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_7/s_axi/axi_lite] SEG_axi_dmac_7_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_8/s_axi/axi_lite] SEG_axi_dmac_8_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43D30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/tx/axi_tx_dmac_9/s_axi/axi_lite] SEG_axi_dmac_9_axi_lite + create_bd_addr_seg -range 0x40000 -offset 0x43D40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs M_AXI_WR/Reg] SEG_M_AXI_WR_Reg + create_bd_addr_seg -range 0x10000 -offset 0x43D80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg + create_bd_addr_seg -range 0x1000 -offset 0x42080000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/axi_regfile_0/S_AXI/regs] SEG_axi_regfile_0_regs + create_bd_addr_seg -range 0x10000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma0/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite + create_bd_addr_seg -range 0x10000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma1/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite11 + create_bd_addr_seg -range 0x10000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma2/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite13 + create_bd_addr_seg -range 0x10000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma3/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite15 + create_bd_addr_seg -range 0x10000 -offset 0x43C40000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma4/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite17 + create_bd_addr_seg -range 0x10000 -offset 0x43C50000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma5/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite19 + create_bd_addr_seg -range 0x10000 -offset 0x43C60000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma6/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite21 + create_bd_addr_seg -range 0x10000 -offset 0x43C70000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma7/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite23 + create_bd_addr_seg -range 0x10000 -offset 0x43C80000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma8/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite25 + create_bd_addr_seg -range 0x10000 -offset 0x43C90000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs dma/rx/dma9/axi_rx_dmac/s_axi/axi_lite] SEG_axi_rx_dmac_axi_lite27 + create_bd_addr_seg -range 0x1000 -offset 0x42100000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_0/S_AXI/reg0] SEG_jtag_0_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42200000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs jtag_1/S_AXI/reg0] SEG_jtag_1_reg0 + create_bd_addr_seg -range 0x1000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs {axi_uartlite_0/S_AXI/Reg }] SEG_WR_UART_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_0/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_1/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_2/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_3/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_4/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_5/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_6/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_7/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_8/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/tx/axi_tx_dmac_9/m_src_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_0_HP3_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma0/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma1/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma2/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma3/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma4/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma5/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma6/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma7/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma8/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces dma/rx/dma9/axi_rx_dmac/m_dest_axi] [get_bd_addr_segs processing_system7_0/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_0_HP2_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_GP1_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x0 [get_bd_addr_spaces S_AXI_HP1] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..b159ce4b6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,45 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..79d8850b4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,353 @@ + + + xilinx.com + xci + unknown + 1.0 + + + one_gig_eth_pcs_pma + + + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + true + 0 + 0 + false + false + DIFF_PAIR_0 + DIFF_PAIR_1 + false + DIFF_PAIR_0 + DIFF_PAIR_1 + zynq + 0 + one_gig_eth_pcs_pma + 50 + false + . + false + false + false + false + zynq + 8 + 9 + X0Y0 + 7 + 4 + GTH + false + false + false + false + true + false + false + 1 + clk0 + 125 + TXOUTCLK + true + false + one_gig_eth_pcs_pma_gt + false + GTXE2 + false + 1 + false + false + true + xc7z100 + false + 1 + false + false + Sync + one_gig_eth_pcs_pma + Custom + 50 + TEMAC + Custom + 0 + false + false + false + false + X0Y0 + GTH + false + false + 125 + Custom + true + 1G + 1 + Transceiver + 125 + clk0 + TXOUTCLK + DIFF_PAIR_0 + DIFF_PAIR_1 + false + 10_100_1000 + false + 1000BASEX + Include_Shared_Logic_in_Example_Design + Time_of_day + false + DIFF_PAIR_0 + DIFF_PAIR_1 + 1 + false + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v new file mode 100644 index 000000000..e5e05c62b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v @@ -0,0 +1,188 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_clocking.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the Clocking logic for pcs/pma core. + + +`timescale 1 ps/1 ps + + +//------------------------------------------------------------------------------ +// The module declaration for the example design +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_clocking + ( + input txoutclk, // txoutclk from GT transceiver. + input rxoutclk, // rxoutclk from GT transceiver. + input mmcm_reset, // MMCM Reset + output wire mmcm_locked, // MMCM locked + + output userclk, // for GT PMA reference clock + output userclk2, // 125MHz clock for core reference clock. + output rxuserclk, // for GT PMA reference clock + output rxuserclk2 // 125MHz clock for core reference clock. + ); + + wire clkout0; // MMCM output clock + wire clkout1; // MMCM output clock + wire clkfbout; // MMCM Feedback clock +// Route txoutclk input through a BUFG + wire txoutclk_bufg; + wire userclk_i; + wire rxoutclk_buf; + + //--------------------------------------------------------------------------- + // Transceiver Clock Management + //--------------------------------------------------------------------------- + + // Route txoutclk input through a BUFG + BUFG bufg_txoutclk ( + .I (txoutclk), + .O (txoutclk_bufg) + ); + + // The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is + // routed to an MMCM module where it is used to create phase and frequency + // related 62.5MHz and 125MHz clock sources + MMCME2_ADV # ( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.5), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.5), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (16.0), + .CLKFBOUT_MULT_F (16.000), + .CLKOUT0_DIVIDE_F (8.000), + .CLKOUT1_DIVIDE (16), + + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + // Output clocks + .CLKFBOUT (clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clkout0), + .CLKOUT0B (), + .CLKOUT1 (clkout1), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clkfbout), + .CLKIN1 (txoutclk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_reset) + ); + // This 62.5MHz clock is placed onto global clock routing and is then used + // for tranceiver TXUSRCLK/RXUSRCLK. + BUFG bufg_userclk ( + .I (clkout1), + .O (userclk_i) + ); + + + // This 125MHz clock is placed onto global clock routing and is then used + // to clock all Ethernet core logic. + BUFG bufg_userclk2 ( + .I (clkout0), + .O (userclk2) + ); + + + +assign userclk = userclk_i; + + + // Place the Rx recovered clock on a Global Clock Buffer (it may be possible + // to switch this for a BUFHCE/BUFR and BUFMR combination) + BUFG rxrecclkbufg ( + .I (rxoutclk), + .O (rxoutclk_buf) + ); + + assign rxuserclk2 = rxoutclk_buf; + assign rxuserclk = rxoutclk_buf; + +endmodule // one_gig_eth_pcs_pma_clocking diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v new file mode 100644 index 000000000..4c92d105a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v @@ -0,0 +1,238 @@ +//------------------------------------------------------------------------------ +// File : one_gig_eth_pcs_pma_support.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2011 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This module holds the support level for the pcs/pma core +// This can be used as-is in a single core design, or adapted +// for use with multi-core implementations + +`timescale 1 ps/1 ps +(* DowngradeIPIdentifiedWarnings="yes" *) + +//------------------------------------------------------------------------------ +// The module declaration for the Core Block wrapper. +//------------------------------------------------------------------------------ + +module one_gig_eth_pcs_pma_support + ( + // Transceiver Interface + //---------------------- + + + input gtrefclk, // gtrefclk routed through an IBUFG. + input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + output userclk_out, + output userclk2_out, + output rxuserclk_out, + output rxuserclk2_out, + input independent_clock_bufg, // Freerun Independent clock, + output pma_reset_out, // transceiver PMA reset signal + output mmcm_locked_out, // MMCM Locked + output resetdone, + // GMII Interface + //--------------- + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output [7:0] gmii_rxd, // Received Data to client MAC. + output gmii_rx_dv, // Received control signal to client MAC. + output gmii_rx_er, // Received control signal to client MAC. + output gmii_isolate, // Tristate control to electrically isolate GMII. + + // Management: MDIO Interface + //--------------------------- + + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + + input signal_detect, // Input from PMD to indicate presence of optical input. + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in + + + + ); + + + //--------------------------------------------------------------------------- + // Internal signals used in this block level wrapper. + //--------------------------------------------------------------------------- + + // Core <=> Transceiver interconnect + wire cplllock; // reset done indication from transceiver + wire mmcm_reset; // Reset to MMCM based on resetdone + wire mmcm_locked; // Signal indicating that MMCM has locked + wire pma_reset; // Reset synchronized to system clock + wire txoutclk; // txoutclk from GT transceiver (62.5MHz) + wire rxoutclk; // txoutclk from GT transceiver (62.5MHz) + wire userclk; + wire userclk2; + wire rxuserclk; + wire rxuserclk2; + + // GT Interface + //------------- + //wire gt0_qplloutclk; + //wire gt0_qplloutrefclk; + +one_gig_eth_pcs_pma +pcs_pma_i + ( + + // Transceiver Interface + //---------------------- + + .gtrefclk (gtrefclk), // Very high quality clock for GT transceiver. + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), // Differential +ve of serial transmission from PMA to PMD. + .txn (txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp (rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn (rxn), // Differential -ve for serial reception from PMD to PMA. + + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .resetdone (resetdone), + .cplllock (cplllock), + .mmcm_reset (mmcm_reset), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2), + .independent_clock_bufg (independent_clock_bufg), + .pma_reset (pma_reset), + .mmcm_locked (mmcm_locked), + + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .gmii_isolate (gmii_isolate), + + // Management: MDIO Interface + //--------------------------- + + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + + + // General IO's + //------------- + .status_vector (status_vector), // Core status. + .reset (pma_reset), // Asynchronous reset for entire core. + + .signal_detect (signal_detect) , // Input from PMD to indicate presence of optical input. + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + + //---------------------------------------------------------------------------- + // Instantiate the clocking module. + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_clocking core_clocking_i + ( + .txoutclk (txoutclk), + .rxoutclk (rxoutclk), + .mmcm_reset (mmcm_reset), + .mmcm_locked (mmcm_locked), + .userclk (userclk), + .userclk2 (userclk2), + .rxuserclk (rxuserclk), + .rxuserclk2 (rxuserclk2) + ); + +assign gtrefclk_out = gtrefclk; +assign gtrefclk_bufg_out = gtrefclk_bufg; +assign userclk_out = userclk; +assign userclk2_out = userclk2; +assign rxuserclk_out = rxuserclk; +assign rxuserclk2_out = rxuserclk2; + + + //--------------------------------------------------------------------------- + // Transceiver PMA reset circuitry + //--------------------------------------------------------------------------- + one_gig_eth_pcs_pma_resets core_resets_i + ( + .reset (reset), + .independent_clock_bufg (independent_clock_bufg), + + .pma_reset (pma_reset) + ); + +assign pma_reset_out = pma_reset; + + + assign mmcm_locked_out = mmcm_locked; + +endmodule // one_gig_eth_pcs_pma_support + diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..b02424f03 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,105 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + input gt0_qplloutclk_in, + input gt0_qplloutrefclk_in, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] phyaddr, // MDIO PHY Address + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect, // Input from PMD to indicate presence of optical input. + output pma_reset_out +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (pma_reset_out), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .phyaddr (phyaddr), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_in (gt0_qplloutclk_in), + .gt0_qplloutrefclk_in (gt0_qplloutrefclk_in) + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc new file mode 100644 index 000000000..4dadace3b --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc @@ -0,0 +1,164 @@ + + +#*********************************************************** +# The following constraints target the Transceiver Physical* +# Interface which is instantiated in the Example Design. * +#*********************************************************** +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] + + +#----------------------------------------------------------- +# Clock source used for the IDELAY Controller (if present) - +# and for the transceiver reset circuitry - +#----------------------------------------------------------- + + +create_clock -name independent_clock -period 5.000 [get_ports independent_clock] + +#----------------------------------------------------------- +# PCS/PMA Clock period Constraints: please do not relax - +#----------------------------------------------------------- + +create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p] + + +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC H6 [get_ports gtrefclk_p] +#set_property LOC H5 [get_ports gtrefclk_n] + + +#*********************************************************** +# The following constraints target the GMII implemented in * +# the Example Design. * +#*********************************************************** +# If the GMII is intended to be an internal interface, * +# the GMII signals can be connected directly to user * +# logic and all of the following constraints in this file * +# should be removed. * +# * +# If the GMII is intended to be an external interface, * +# all of the following constraints in this file should be * +# maintained. * +#*********************************************************** + +#----------------------------------------------------------- +# GMII IOSTANDARD Constraints: please select an I/O - +# Standard (LVTTL is suggested). - +#----------------------------------------------------------- + +# Please update the IOSTANDARD according to that available in the device + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] + +#----------------------------------------------------------- +# Lock down the GMII Tx signals to the same bank for low - +# skew. This is an example placement only. - +#----------------------------------------------------------- + + +#----------------------------------------------------------- +# To Adjust GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- +# These constraints will be set at a later date when device speed files have matured + +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] + +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] + + + +#----------------------------------------------------------- +# To check (analyze) GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- + +create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] + + + +#----------------------------------------------------------- +# Fast Skew maximises output setup and hold timing - +#----------------------------------------------------------- +set_property SLEW FAST [get_ports {gmii_rxd[*]}] +set_property SLEW FAST [get_ports gmii_rx_dv] +set_property SLEW FAST [get_ports gmii_rx_er] +set_property SLEW FAST [get_ports gmii_rx_clk] + + +#----------------------------------------------------------- +# GMII Transmitter Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_txd_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*] + +#----------------------------------------------------------- +# GMII Receiver Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*] +#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] +#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] + + + +#----------------------------------------------------------- +# GMII Tx Elastic Buffer Constraints - +#----------------------------------------------------------- + +# Control Gray Code delay and skew across clock boundary +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] + +# Constrain between Distributed Memory (output data) and the 1st set of flip-flops +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}] + +set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] + +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..db95346bd --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \ +ten_gig_eth_pcs_pma_example_design.v \ +ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +ten_gig_eth_pcs_pma_support.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..8af7da882 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,192 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma + + + 0 + 0 + 0 + 0 + 0 + + + 0 + 0.000 + + + + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 0 + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + false + 0 + 0 + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + + 0 + 0.000 + + + + 0 + 0.000 + 0 + ten_gig_eth_pcs_pma + 100.00 + zynq + X0Y0 + 32 + 0 + false + false + true + false + false + false + clk0 + 156 + 10 + ten_gig_eth_pcs_pma_gt + ten_gig_eth_pcs_pma + 100.00 + None + X0Y0 + true + clk0 + 156.25 + 0 + Time_of_day + false + false + false + BASE-R + 64bit + false + false + 10Gig + GTH + zynq + + + xc7z100 + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 15 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v new file mode 100644 index 000000000..8d03d78df --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_gt_common.v @@ -0,0 +1,202 @@ +//----------------------------------------------------------------------------- +// Title : GT Common wrapper +// Project : 10GBASE-R +//----------------------------------------------------------------------------- +// File : ten_gig_eth_pcs_pma_gt_common.v +//----------------------------------------------------------------------------- +// Description: This file contains the +// 10GBASE-R Transceiver GT Common block. +//----------------------------------------------------------------------------- +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. + +`timescale 1ps / 1ps + +module ten_gig_eth_pcs_pma_gt_common # ( + parameter WRAPPER_SIM_GTRESET_SPEEDUP = "false" ) //Does not affect hardware + ( + input refclk, + input qpllreset, + output qplllock, + output qplloutclk, + output qplloutrefclk, + input [2:0] qpllrefclksel + ); + + +//***************************** Parameter Declarations ************************ + localparam QPLL_FBDIV_TOP = 66; + + localparam QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 : + (QPLL_FBDIV_TOP == 20) ? 10'b0000110000 : + (QPLL_FBDIV_TOP == 32) ? 10'b0001100000 : + (QPLL_FBDIV_TOP == 40) ? 10'b0010000000 : + (QPLL_FBDIV_TOP == 64) ? 10'b0011100000 : + (QPLL_FBDIV_TOP == 66) ? 10'b0101000000 : + (QPLL_FBDIV_TOP == 80) ? 10'b0100100000 : + (QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000; + + localparam QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 : + (QPLL_FBDIV_TOP == 20) ? 1'b1 : + (QPLL_FBDIV_TOP == 32) ? 1'b1 : + (QPLL_FBDIV_TOP == 40) ? 1'b1 : + (QPLL_FBDIV_TOP == 64) ? 1'b1 : + (QPLL_FBDIV_TOP == 66) ? 1'b0 : + (QPLL_FBDIV_TOP == 80) ? 1'b1 : + (QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1; + +//***************************** Wire Declarations ***************************** + + // ground and vcc signals + wire tied_to_ground_i; + wire [63:0] tied_to_ground_vec_i; + wire tied_to_vcc_i; + wire [63:0] tied_to_vcc_vec_i; + +//********************************* Main Body of Code************************** + + assign tied_to_ground_i = 1'b0; + assign tied_to_ground_vec_i = 64'h0000000000000000; + assign tied_to_vcc_i = 1'b1; + assign tied_to_vcc_vec_i = 64'hffffffffffffffff; + + + wire gt0_gtrefclk0_common_in; + wire gt0_qpllreset_in; + wire gt0_qplllock_out; + wire gt0_qplloutclk_i; + wire gt0_qplloutrefclk_i; + + assign gt0_gtrefclk0_common_in = refclk; + assign gt0_qpllreset_in = qpllreset; + assign qplllock = gt0_qplllock_out; + assign qplloutclk = gt0_qplloutclk_i; + assign qplloutrefclk = gt0_qplloutrefclk_i; + + + //_________________________________________________________________________ + //_________________________________________________________________________ + //_________________________GTXE2_COMMON____________________________________ + + GTXE2_COMMON # + ( + // Simulation attributes + .SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_VERSION ("4.0"), + + + //----------------COMMON BLOCK Attributes--------------- + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .QPLL_CFG (27'h0680181), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV_IN), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (1) + ) + gtxe2_common_0_i + ( + //----------- Common Block - Dynamic Reconfiguration Port (DRP) ----------- + .DRPADDR (tied_to_ground_vec_i[7:0]), + .DRPCLK (tied_to_ground_i), + .DRPDI (tied_to_ground_vec_i[15:0]), + .DRPDO (), + .DRPEN (tied_to_ground_i), + .DRPRDY (), + .DRPWE (tied_to_ground_i), + //-------------------- Common Block - Ref Clock Ports --------------------- + .GTGREFCLK (tied_to_ground_i), + .GTNORTHREFCLK0 (tied_to_ground_i), + .GTNORTHREFCLK1 (tied_to_ground_i), + .GTREFCLK0 (gt0_gtrefclk0_common_in), + .GTREFCLK1 (tied_to_ground_i), + .GTSOUTHREFCLK0 (tied_to_ground_i), + .GTSOUTHREFCLK1 (tied_to_ground_i), + //--------------------- Common Block - Clocking Ports ---------------------- + .QPLLOUTCLK (gt0_qplloutclk_i), + .QPLLOUTREFCLK (gt0_qplloutrefclk_i), + .REFCLKOUTMONITOR (), + //----------------------- Common Block - QPLL Ports ------------------------ + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .QPLLLOCK (gt0_qplllock_out), + .QPLLLOCKDETCLK (1'b0), + .QPLLLOCKEN (tied_to_vcc_i), + .QPLLOUTRESET (tied_to_ground_i), + .QPLLPD (tied_to_ground_i), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (qpllrefclksel), + .QPLLRESET (gt0_qpllreset_in), + .QPLLRSVD1 (16'b0000000000000000), + .QPLLRSVD2 (5'b11111), + //------------------------------- QPLL Ports ------------------------------- + .BGBYPASSB (tied_to_vcc_i), + .BGMONITORENB (tied_to_vcc_i), + .BGPDB (tied_to_vcc_i), + .BGRCALOVRD (5'b11111), + .PMARSVD (8'b00000000), + .RCALENB (tied_to_vcc_i) + + ); + + + + + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..5c798136f --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,241 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable, + output qpllreset, + input qplllock, + input qplloutclk, + input qplloutrefclk, + output tx_out_clk +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + assign tx_out_clk = txclk322; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .rxrecclk_out(), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc new file mode 100644 index 000000000..3e637368a --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc @@ -0,0 +1,91 @@ +## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + +create_clock -period 6.400 [get_ports {dclk}] + +create_clock -period 6.400 [get_ports refclk_p] + +create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] + +# False paths for async reset removal synchronizers +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] + + +## Sample constraint for GT location +#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] +#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] + +set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] +set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] + +set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] + + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] +################################################################### + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] +################################################################### + diff --git a/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..7c1d09fe6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,37 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input refclk_ibuf, + output clk156, + output dclk +); + + wire dclk_buf; + + BUFG clk156_bufg_inst ( + .I (refclk_ibuf), + .O (clk156) + ); + + // Dividing independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/n3xx/mb_clocks.xdc b/fpga/usrp3/top/n3xx/mb_clocks.xdc new file mode 100644 index 000000000..30736155f --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_clocks.xdc @@ -0,0 +1,86 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Motherboard Clocks + +# 10/20/25 MHz reference clock from rear panel connector. Constrain to the fastest +# possible clock rate. +set REF_CLK_PERIOD 40.00 +create_clock -name ref_clk -period $REF_CLK_PERIOD [get_ports FPGA_REFCLK_P] +# 125 MHz RJ45 Ethernet clock +create_clock -name ge_phy_clk -period 8.000 [get_ports ENET0_CLK125] +# 156.25 MHz oscillator to MGT bank 110 +create_clock -name xge_clk -period 6.400 [get_ports MGT156MHZ_CLK1_P] +# 125 MHz PLL for MG bank 109 +create_clock -name net_clk -period 8.000 [get_ports NETCLK_P] + +# Virtual clocks for constraining I/O (used below) +create_clock -name async_in_clk -period 50.00 +create_clock -name async_out_clk -period 50.00 + + + +#******************************************************************************* +## Aliases for auto-generated clocks + +# Rename the PS clocks. These are originally declared in the PS7 IP block, but do not +# have super descriptive names. We rename them here for additional clarity, and to match +# the rest of the design. + +# First save off the input jitter setting for each, before we nuke the original clocks. +set clk100_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_0]] +set clk40_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_1]] +set meas_clk_ref_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_2]] +set bus_clk_jitter [get_property INPUT_JITTER [get_clocks clk_fpga_3]] + +# Create the new clocks based on the old ones. This generates critical warnings that +# we are completely rewriting the old clock definition... this is OK. +create_clock -name clk100 \ + -period [get_property PERIOD [get_clocks clk_fpga_0]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]] +create_clock -name clk40 \ + -period [get_property PERIOD [get_clocks clk_fpga_1]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]] +create_clock -name meas_clk_ref \ + -period [get_property PERIOD [get_clocks clk_fpga_2]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]] +create_clock -name bus_clk \ + -period [get_property PERIOD [get_clocks clk_fpga_3]] \ + [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]] + +# Apply the jitter setting from the original clocks. +set_input_jitter [get_clocks clk100] $clk100_jitter +set_input_jitter [get_clocks clk40] $clk40_jitter +set_input_jitter [get_clocks meas_clk_ref] $meas_clk_ref_jitter +set_input_jitter [get_clocks bus_clk] $bus_clk_jitter + + +# TDC Measurement Clock +create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}] +create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}] + +#******************************************************************************* +## White Rabbit DAC +# Constrain the DIN and NSYNC bits around the clock output. No readback. + +set WR_OUT_CLK [get_ports {WB_DAC_SCLK}] +create_generated_clock -name wr_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $WR_OUT_CLK]/C] \ + -divide_by 2 $WR_OUT_CLK + +#******************************************************************************* +## Front Panel GPIO +# These bits are driven from the DB-A radio clock. Although they are received async in +# the outside world, they should be constrained in the FPGA to avoid any race +# conditions. The best way to do this is a skew constraint across all the bits. + +set FP_GPIO_CLK [get_ports {FPGA_GPIO[0]}] +create_generated_clock -name fp_gpio_bus_clk \ + -source [get_pins [all_fanin -flat -only_cells -startpoints_only $FP_GPIO_CLK]/C] \ + -divide_by 2 $FP_GPIO_CLK + diff --git a/fpga/usrp3/top/n3xx/mb_pins.xdc b/fpga/usrp3/top/n3xx/mb_pins.xdc new file mode 100644 index 000000000..6eecc42d5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_pins.xdc @@ -0,0 +1,386 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Motherboard Pin Definitions for the N3xx Product Family. +# + +## Bank 12: 3.3V Logic : ################################################################ +## Front-panel GPIO +## FPGA test outputs +######################################################################################### + +set_property PACKAGE_PIN AF25 [get_ports {FPGA_GPIO[0]}] +set_property PACKAGE_PIN AE25 [get_ports {FPGA_GPIO[1]}] +set_property PACKAGE_PIN AG26 [get_ports {FPGA_GPIO[2]}] +set_property PACKAGE_PIN AG27 [get_ports {FPGA_GPIO[3]}] +set_property PACKAGE_PIN AE26 [get_ports {FPGA_GPIO[4]}] +set_property PACKAGE_PIN AB26 [get_ports {FPGA_GPIO[5]}] +set_property PACKAGE_PIN AF27 [get_ports {FPGA_GPIO[6]}] +set_property PACKAGE_PIN AA27 [get_ports {FPGA_GPIO[7]}] +set_property PACKAGE_PIN AE27 [get_ports {FPGA_GPIO[8]}] +set_property PACKAGE_PIN AC26 [get_ports {FPGA_GPIO[9]}] +set_property PACKAGE_PIN AD25 [get_ports {FPGA_GPIO[10]}] +set_property PACKAGE_PIN AD26 [get_ports {FPGA_GPIO[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_GPIO[*]}] +set_property DRIVE 4 [get_ports {FPGA_GPIO[*]}] +set_property SLEW SLOW [get_ports {FPGA_GPIO[*]}] + +# These pins should be commented out for release hardware. +set_property PACKAGE_PIN Y30 [get_ports {FPGA_TEST[0]}] +set_property PACKAGE_PIN AA30 [get_ports {FPGA_TEST[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_TEST[*]}] + +# set_property PACKAGE_PIN AH27 [get_ports {MGMT-GPIO0}] +# set_property PACKAGE_PIN AH26 [get_ports {MGMT-GPIO1}] +# set_property PACKAGE_PIN AC27 [get_ports {MGMT-JTAG-TCK}] +# set_property PACKAGE_PIN AF29 [get_ports {MGMT-JTAG-TDI}] +# set_property PACKAGE_PIN AG29 [get_ports {MGMT-JTAG-TDO}] +# set_property PACKAGE_PIN AB27 [get_ports {MGMT-JTAG-TMS}] +# set_property PACKAGE_PIN Y28 [get_ports {MGMT-SPI-LE}] +# set_property PACKAGE_PIN AD28 [get_ports {MGMT-SPI-MISO}] +# set_property PACKAGE_PIN AA28 [get_ports {MGMT-SPI-MOSI}] +# set_property PACKAGE_PIN AE28 [get_ports {MGMT-SPI-RESET}] +# set_property PACKAGE_PIN AC28 [get_ports {MGMT-SPI-SCLK}] +# When implemented, the MGMT signals need DRIVE and SLEW attributes applied. + +# NPIO and QSFP located elsewhere + + +## Bank 9, 2.5V Logic : ################################################################# +## All of these are inputs and all require internal termination to meet voltage +## swing requirements at the pin. These ports and buffers should always be instantiated +## to meet the internal termination requirement. +######################################################################################### + +set_property PACKAGE_PIN AC18 [get_ports FPGA_REFCLK_P] +set_property PACKAGE_PIN AC19 [get_ports FPGA_REFCLK_N] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_REFCLK_*] +set_property DIFF_TERM TRUE [get_ports FPGA_REFCLK_*] + +set_property PACKAGE_PIN AD18 [get_ports NETCLK_REF_P] +set_property PACKAGE_PIN AD19 [get_ports NETCLK_REF_N] +set_property DIFF_TERM TRUE [get_ports NETCLK_REF_*] +set_property IOSTANDARD LVDS_25 [get_ports NETCLK_REF_*] + +set_property PACKAGE_PIN AA18 [get_ports WB_20MHZ_P] +set_property PACKAGE_PIN AA19 [get_ports WB_20MHZ_N] +set_property DIFF_TERM TRUE [get_ports WB_20MHZ_*] +set_property IOSTANDARD LVDS_25 [get_ports WB_20MHZ_*] + + +## Bank 13, 3.3V : ###################################################################### +## PPS In/Out (including MGMT PPS, unused) +## GPS PPS Raw/Disciplined +## RJ45 signaling (unused) +## Authentication IC +## Resets +## Rear-panel LEDs +######################################################################################### + +set_property PACKAGE_PIN U24 [get_ports REF_1PPS_IN] +set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_IN] + +set_property PACKAGE_PIN V29 [get_ports REF_1PPS_OUT] +set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_OUT] +set_property DRIVE 12 [get_ports REF_1PPS_OUT] +set_property SLEW SLOW [get_ports REF_1PPS_OUT] +set_property IOB TRUE [get_ports REF_1PPS_OUT] + +# set_property PACKAGE_PIN U29 [get_ports REF_1PPS_IN_MGMT] +# set_property IOSTANDARD LVCMOS33 [get_ports REF_1PPS_IN_MGMT] + +set_property PACKAGE_PIN W30 [get_ports GPS_1PPS] +set_property IOSTANDARD LVCMOS33 [get_ports GPS_1PPS] + +# set_property PACKAGE_PIN V28 [get_ports GPS_1PPS_RAW] +# set_property IOSTANDARD LVCMOS33 [get_ports GPS_1PPS_RAW] + +set_property PACKAGE_PIN U26 [get_ports ENET0_CLK125] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_CLK125] + +# set_property PACKAGE_PIN R25 [get_ports ENET0_PTP] +# set_property IOSTANDARD LVCMOS33 [get_ports ENET0_PTP] + +# set_property PACKAGE_PIN R30 [get_ports ENET0_PTP_DIR] +# set_property IOSTANDARD LVCMOS33 [get_ports ENET0_PTP_DIR] + +# set_property PACKAGE_PIN U30 [get_ports ATSHA204_SDA] +# set_property IOSTANDARD LVCMOS33 [get_ports ATSHA204_SDA] + +set_property PACKAGE_PIN P26 [get_ports FPGA_PL_RESETN] +set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PL_RESETN] + +set_property PACKAGE_PIN U25 [get_ports PANEL_LED_GPS] +set_property PACKAGE_PIN T25 [get_ports PANEL_LED_LINK] +set_property PACKAGE_PIN W29 [get_ports PANEL_LED_PPS] +set_property PACKAGE_PIN V24 [get_ports PANEL_LED_REF] +set_property IOSTANDARD LVCMOS33 [get_ports PANEL_LED_*] +set_property DRIVE 4 [get_ports PANEL_LED_*] +set_property SLEW SLOW [get_ports PANEL_LED_*] + +# SFP+ Sideband and White Rabbit DAC Control located elsewhere + + +## NanoPitch Interface : ################################################################ +## Bank 12, 3.3V +######################################################################################### + +# set_property PACKAGE_PIN AD29 [get_ports {NPIO-GPIO0}] +# set_property PACKAGE_PIN AC29 [get_ports {NPIO-GPIO1}] +# set_property PACKAGE_PIN AE30 [get_ports {NPIO-GPIO2}] +# set_property PACKAGE_PIN AD30 [get_ports {NPIO-GPIO3}] +# set_property PACKAGE_PIN AH29 [get_ports {NPIO-GPIO4}] +# set_property PACKAGE_PIN AH28 [get_ports {NPIO-GPIO5}] +# set_property PACKAGE_PIN AF30 [get_ports {NPIO-GPIO6}] +# set_property PACKAGE_PIN AG30 [get_ports {NPIO-GPIO7}] +# When implemented, the QSFP signals need DRIVE and SLEW attributes applied. + +set_property PACKAGE_PIN AE8 [get_ports {NPIO_RX0_P}] +set_property PACKAGE_PIN AE7 [get_ports {NPIO_RX0_N}] +set_property PACKAGE_PIN AG8 [get_ports {NPIO_RX1_P}] +set_property PACKAGE_PIN AG7 [get_ports {NPIO_RX1_N}] +set_property PACKAGE_PIN AK2 [get_ports {NPIO_TX0_P}] +set_property PACKAGE_PIN AK1 [get_ports {NPIO_TX0_N}] +set_property PACKAGE_PIN AJ4 [get_ports {NPIO_TX1_P}] +set_property PACKAGE_PIN AJ3 [get_ports {NPIO_TX1_N}] + + +## QSFP : ############################################################################### +## Bank 12, 3.3V +######################################################################################### + +set_property PACKAGE_PIN AJ26 [get_ports {QSFP_I2C_SCL}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_I2C_SCL}] +set_property DRIVE 8 [get_ports {QSFP_I2C_SCL}] + +set_property PACKAGE_PIN AK26 [get_ports {QSFP_I2C_SDA}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_I2C_SDA}] +set_property DRIVE 8 [get_ports {QSFP_I2C_SDA}] + +set_property PACKAGE_PIN AK28 [get_ports {QSFP_INT_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_INT_B}] + +set_property PACKAGE_PIN AK30 [get_ports {QSFP_LED}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_LED}] + +set_property PACKAGE_PIN AJ29 [get_ports {QSFP_LPMODE}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_LPMODE}] + +set_property PACKAGE_PIN AK27 [get_ports {QSFP_PRESENT_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_PRESENT_B}] + +set_property PACKAGE_PIN AJ28 [get_ports {QSFP_MODSEL_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_MODSEL_B}] + +set_property PACKAGE_PIN AJ30 [get_ports {QSFP_RESET_B}] +set_property IOSTANDARD LVCMOS33 [get_ports {QSFP_RESET_B}] + +# When implemented, the QSFP signals need DRIVE and SLEW attributes applied. + +set_property PACKAGE_PIN AD5 [get_ports {QSFP_RX_N[0]}] +set_property PACKAGE_PIN AD6 [get_ports {QSFP_RX_P[0]}] +set_property PACKAGE_PIN AF5 [get_ports {QSFP_RX_N[1]}] +set_property PACKAGE_PIN AF6 [get_ports {QSFP_RX_P[1]}] +set_property PACKAGE_PIN AG3 [get_ports {QSFP_RX_N[2]}] +set_property PACKAGE_PIN AG4 [get_ports {QSFP_RX_P[2]}] +set_property PACKAGE_PIN AH5 [get_ports {QSFP_RX_N[3]}] +set_property PACKAGE_PIN AH6 [get_ports {QSFP_RX_P[3]}] +set_property PACKAGE_PIN AD1 [get_ports {QSFP_TX_N[0]}] +set_property PACKAGE_PIN AD2 [get_ports {QSFP_TX_P[0]}] +set_property PACKAGE_PIN AE3 [get_ports {QSFP_TX_N[1]}] +set_property PACKAGE_PIN AE4 [get_ports {QSFP_TX_P[1]}] +set_property PACKAGE_PIN AF1 [get_ports {QSFP_TX_N[2]}] +set_property PACKAGE_PIN AF2 [get_ports {QSFP_TX_P[2]}] +set_property PACKAGE_PIN AH1 [get_ports {QSFP_TX_N[3]}] +set_property PACKAGE_PIN AH2 [get_ports {QSFP_TX_P[3]}] + + +## White Rabbit : ####################################################################### +## Bank 13, 3.3V +######################################################################################### + +set_property PACKAGE_PIN T29 [get_ports {WB_DAC_DIN}] +set_property PACKAGE_PIN T28 [get_ports {WB_DAC_NCLR}] +set_property PACKAGE_PIN T30 [get_ports {WB_DAC_NLDAC}] +set_property PACKAGE_PIN N29 [get_ports {WB_DAC_NSYNC}] +set_property PACKAGE_PIN P29 [get_ports {WB_DAC_SCLK}] +set_property IOSTANDARD LVCMOS33 [get_ports {WB_DAC_*}] +set_property DRIVE 4 [get_ports {WB_DAC_*}] +set_property SLEW SLOW [get_ports {WB_DAC_*}] + + +## SFP+ : ############################################################################### +## +######################################################################################### + +## Clocks, Bank 109 and 110 + +# These need to have the internal buffer in the FPGA enabled at all times to avoid +# damage to the part. Therefore declare them here in the top level pins file. +set_property PACKAGE_PIN AA8 [get_ports {MGT156MHZ_CLK1_P}] +set_property PACKAGE_PIN AA7 [get_ports {MGT156MHZ_CLK1_N}] + +set_property PACKAGE_PIN AF10 [get_ports {NETCLK_P}] +set_property PACKAGE_PIN AF9 [get_ports {NETCLK_N}] + +# Swapping SFP_0 and SFP_1 pinout to match the label on the silkscreen. +# These FPGA pins are reversed with respect to the schematic now. +## MGTs, Bank 109 + +set_property PACKAGE_PIN AJ7 [get_ports SFP_0_RX_N] +set_property PACKAGE_PIN AJ8 [get_ports SFP_0_RX_P] +set_property PACKAGE_PIN AK5 [get_ports SFP_0_TX_N] +set_property PACKAGE_PIN AK6 [get_ports SFP_0_TX_P] + +set_property PACKAGE_PIN AH9 [get_ports SFP_1_RX_N] +set_property PACKAGE_PIN AH10 [get_ports SFP_1_RX_P] +set_property PACKAGE_PIN AK9 [get_ports SFP_1_TX_N] +set_property PACKAGE_PIN AK10 [get_ports SFP_1_TX_P] + +## SFP+ 0, Sideband, Bank 13 3.3V + +set_property PACKAGE_PIN T27 [get_ports {SFP_0_I2C_NPRESENT}] +set_property IOSTANDARD LVCMOS33 [get_ports {SFP_0_I2C_NPRESENT}] + +set_property PACKAGE_PIN N27 [get_ports SFP_0_LED_A] +set_property PACKAGE_PIN N28 [get_ports SFP_0_LED_B] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_LED_*] +set_property DRIVE 4 [get_ports SFP_0_LED_*] +set_property SLEW SLOW [get_ports SFP_0_LED_*] + +set_property PACKAGE_PIN R27 [get_ports SFP_0_LOS] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_LOS] + +set_property PACKAGE_PIN R26 [get_ports SFP_0_RS0] +set_property PACKAGE_PIN P28 [get_ports SFP_0_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_RS*] +set_property DRIVE 4 [get_ports SFP_0_RS*] +set_property SLEW SLOW [get_ports SFP_0_RS*] + +set_property PACKAGE_PIN U27 [get_ports SFP_0_TXDISABLE] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_TXDISABLE] +set_property DRIVE 4 [get_ports SFP_0_TXDISABLE] +set_property SLEW SLOW [get_ports SFP_0_TXDISABLE] + +set_property PACKAGE_PIN V26 [get_ports SFP_0_TXFAULT] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_0_TXFAULT] + +## SFP+ 1, Slow Speed, Bank 13 3.3V + +# set_property PACKAGE_PIN V23 [get_ports {SFP_1_I2C_NPRESENT}] +# set_property IOSTANDARD LVCMOS33 [get_ports {SFP_1_I2C_NPRESENT}] + +set_property PACKAGE_PIN N26 [get_ports SFP_1_LED_A] +set_property PACKAGE_PIN P30 [get_ports SFP_1_LED_B] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_LED_*] +set_property DRIVE 4 [get_ports SFP_1_LED_*] +set_property SLEW SLOW [get_ports SFP_1_LED_*] + +set_property PACKAGE_PIN R28 [get_ports SFP_1_LOS] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_LOS] + +set_property PACKAGE_PIN T24 [get_ports SFP_1_RS0] +set_property PACKAGE_PIN P25 [get_ports SFP_1_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_RS*] +set_property DRIVE 4 [get_ports SFP_1_RS*] +set_property SLEW SLOW [get_ports SFP_1_RS*] + +set_property PACKAGE_PIN V27 [get_ports SFP_1_TXDISABLE] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_TXDISABLE] +set_property DRIVE 4 [get_ports SFP_1_TXDISABLE] +set_property SLEW SLOW [get_ports SFP_1_TXDISABLE] + +set_property PACKAGE_PIN W24 [get_ports SFP_1_TXFAULT] +set_property IOSTANDARD LVCMOS33 [get_ports SFP_1_TXFAULT] + + +## PL DDR : ############################################################################# +## +######################################################################################### + +# This port must be always enabled due to a Xilinx bug in the silicon. +# https://www.xilinx.com/support/answers/63950.html +set_property PACKAGE_PIN A8 [get_ports FPGA_PUDC_B] +set_property IOSTANDARD LVDCI_15 [get_ports FPGA_PUDC_B] + +set_property PACKAGE_PIN D8 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN A7 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN C7 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN D9 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN J9 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN E8 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN G7 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN E7 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN G11 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN C6 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN H7 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN F7 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN F8 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN F9 [get_ports {ddr3_addr[15]}] + +set_property PACKAGE_PIN C9 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN E10 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN B9 [get_ports {ddr3_ba[2]}] + +set_property PACKAGE_PIN A10 [get_ports ddr3_cas_n] +set_property PACKAGE_PIN E11 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN H8 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN J8 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN D11 [get_ports {ddr3_cs_n[0]}] + +set_property PACKAGE_PIN B16 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN B11 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN H13 [get_ports {ddr3_dm[2]}] +set_property PACKAGE_PIN G15 [get_ports {ddr3_dm[3]}] + +set_property PACKAGE_PIN B17 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN A17 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN D15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN D14 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN C17 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN E15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN C16 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN D16 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN A13 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN A12 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C14 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN B12 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN B14 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN C12 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A14 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN C11 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN J15 [get_ports {ddr3_dq[16]}] +set_property PACKAGE_PIN L14 [get_ports {ddr3_dq[17]}] +set_property PACKAGE_PIN L15 [get_ports {ddr3_dq[18]}] +set_property PACKAGE_PIN J13 [get_ports {ddr3_dq[19]}] +set_property PACKAGE_PIN J14 [get_ports {ddr3_dq[20]}] +set_property PACKAGE_PIN K15 [get_ports {ddr3_dq[21]}] +set_property PACKAGE_PIN J16 [get_ports {ddr3_dq[22]}] +set_property PACKAGE_PIN H14 [get_ports {ddr3_dq[23]}] +set_property PACKAGE_PIN F15 [get_ports {ddr3_dq[24]}] +set_property PACKAGE_PIN G16 [get_ports {ddr3_dq[25]}] +set_property PACKAGE_PIN F14 [get_ports {ddr3_dq[26]}] +set_property PACKAGE_PIN E13 [get_ports {ddr3_dq[27]}] +set_property PACKAGE_PIN G14 [get_ports {ddr3_dq[28]}] +set_property PACKAGE_PIN D13 [get_ports {ddr3_dq[29]}] +set_property PACKAGE_PIN F13 [get_ports {ddr3_dq[30]}] +set_property PACKAGE_PIN E12 [get_ports {ddr3_dq[31]}] + +set_property PACKAGE_PIN F17 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN E17 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN B15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN A15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN L13 [get_ports {ddr3_dqs_p[2]}] +set_property PACKAGE_PIN K13 [get_ports {ddr3_dqs_n[2]}] +set_property PACKAGE_PIN F12 [get_ports {ddr3_dqs_n[3]}] +set_property PACKAGE_PIN G12 [get_ports {ddr3_dqs_p[3]}] + +set_property PACKAGE_PIN D10 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN B10 [get_ports ddr3_ras_n] +set_property PACKAGE_PIN D6 [get_ports ddr3_reset_n] +set_property PACKAGE_PIN G9 [get_ports sys_clk_n] +set_property PACKAGE_PIN H9 [get_ports sys_clk_p] +set_property PACKAGE_PIN A9 [get_ports ddr3_we_n] diff --git a/fpga/usrp3/top/n3xx/mb_timing.xdc b/fpga/usrp3/top/n3xx/mb_timing.xdc new file mode 100644 index 000000000..6aa3f8132 --- /dev/null +++ b/fpga/usrp3/top/n3xx/mb_timing.xdc @@ -0,0 +1,111 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# +# Timing analysis is performed in "/n3xx/doc/mb_timing.xlsx". See +# the spreadsheet for more details and explanations. + +#******************************************************************************* +## Asynchronous clock groups + +# All the clocks from the PS are async to everything else except clocks generated +# from themselves. +set_clock_groups -asynchronous -group [get_clocks clk100 -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks clk40 -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks bus_clk -include_generated_clocks] +set_clock_groups -asynchronous -group [get_clocks meas_clk_ref -include_generated_clocks] + + + +#******************************************************************************* +## PPS Input Timing + +# The external PPS is synchronous to the external reference clock, which is expected to +# be at 10 MHz. Given [setup, hold] of [5ns, 5ns] at the rear panel inputs of the N310, +# we have an adequate data valid window at the FPGA. However, since we overconstrain the +# reference clock to 25 MHz, we use the alternative period here for setup analysis. +set_input_delay -clock ref_clk -min 4.651 [get_ports REF_1PPS_IN] +set_input_delay -clock ref_clk -max [expr {$REF_CLK_PERIOD - 0.235}] [get_ports REF_1PPS_IN] + +# The GPS PPS is also synchronous to the external reference clock (since there is a +# switch on the clock input outside the FPGA). Again, use the overconstrained period. +set_input_delay -clock ref_clk -min 1.234 [get_ports GPS_1PPS] +set_input_delay -clock ref_clk -max [expr {$REF_CLK_PERIOD - 2.111}] [get_ports GPS_1PPS] + + + +#******************************************************************************* +## White Rabbit DAC +# Constrain the DIN and NSYNC bits around the clock output. No readback. + +set MAX_SKEW 5 +set SETUP_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set PORT_LIST [get_ports {WB_DAC_DIN WB_DAC_NCLR WB_DAC_NSYNC WB_DAC_NLDAC}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks wr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks wr_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks wr_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks wr_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks wr_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks wr_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $WR_OUT_CLK +set_max_delay -to $WR_OUT_CLK 50.000 +set_min_delay -to $WR_OUT_CLK 0.000 + + + +#******************************************************************************* +## MB Async Ins/Outs + +set ASYNC_MB_INPUTS [get_ports {SFP_*_LOS SFP_*_TXFAULT UNUSED_PIN_TDC*}] + +set_input_delay -clock [get_clocks async_in_clk] 0.000 $ASYNC_MB_INPUTS +set_max_delay -from $ASYNC_MB_INPUTS 50.000 +set_min_delay -from $ASYNC_MB_INPUTS 0.000 + + +set ASYNC_MB_OUTPUTS [get_ports {*LED* SFP_*TXDISABLE UNUSED_PIN_TDC* \ + FPGA_TEST[*]}] + +set_output_delay -clock [get_clocks async_out_clk] 0.000 $ASYNC_MB_OUTPUTS +set_max_delay -to $ASYNC_MB_OUTPUTS 50.000 +set_min_delay -to $ASYNC_MB_OUTPUTS 0.000 + + + +#******************************************************************************* +## Front Panel GPIO +# These bits are driven from the DB-A radio clock. Although they are received async in +# the outside world, they should be constrained in the FPGA to avoid any race +# conditions. The best way to do this is a skew constraint across all the bits. + +set MAX_SKEW 10 +set SETUP_SKEW [expr {($MAX_SKEW / 2)-0.5}] +set HOLD_SKEW [expr {($MAX_SKEW / 2)+0.5}] +set PORT_LIST [get_ports {FPGA_GPIO[*]}] +# Then add the output delay on each of the ports. +set_output_delay -clock [get_clocks fp_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks fp_gpio_bus_clk] -max -$SETUP_SKEW $PORT_LIST +set_output_delay -clock [get_clocks fp_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +set_output_delay -add_delay -clock_fall -clock [get_clocks fp_gpio_bus_clk] -min $HOLD_SKEW $PORT_LIST +# Finally, make both the setup and hold checks use the same launching and latching edges. +set_multicycle_path -setup -to [get_clocks fp_gpio_bus_clk] -start 0 +set_multicycle_path -hold -to [get_clocks fp_gpio_bus_clk] -1 +# Remove analysis from the output "clock" pin. There are ways to do this using TCL, but +# they aren't supported in XDC files... so we do it the old fashioned way. +set_output_delay -clock [get_clocks async_out_clk] 0.000 $FP_GPIO_CLK +set_max_delay -to $FP_GPIO_CLK 50.000 +set_min_delay -to $FP_GPIO_CLK 0.000 +# All inputs on this interface are async. +set_input_delay -clock [get_clocks async_in_clk] 0.000 $PORT_LIST +set_max_delay -from $PORT_LIST 50.000 +set_min_delay -from $PORT_LIST 0.000 + +#****************************************************************************** +## Reset Sync False Path +set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D] +set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/C] diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.v b/fpga/usrp3/top/n3xx/n300_bist_image_core.v new file mode 100644 index 000000000..31d4eeb86 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.v @@ -0,0 +1,885 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n300) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.938765 +// Source: ./n3xx/n300_bist_image_core.yml +// Source SHA256: 3bed6bab7b614594eb5ea4e49b34a6e9560b10ff4622c1033c206bec1f4a0f2c + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [CHDR_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [CHDR_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (7), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; + wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep4_tdata ), + .s_axis_chdr_tlast (xb_to_ep4_tlast ), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), + .s_axis_chdr_tready (xb_to_ep4_tready ), + .m_axis_chdr_tdata (ep4_to_xb_tdata ), + .m_axis_chdr_tlast (ep4_to_xb_tlast ), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), + .m_axis_chdr_tready (ep4_to_xb_tready ), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; + wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep5_tdata ), + .s_axis_chdr_tlast (xb_to_ep5_tlast ), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), + .s_axis_chdr_tready (xb_to_ep5_tready ), + .m_axis_chdr_tdata (ep5_to_xb_tdata ), + .m_axis_chdr_tlast (ep5_to_xb_tlast ), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), + .m_axis_chdr_tready (ep5_to_xb_tready ), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; + wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (4), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_fifo0_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_fifo0_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (2), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // fifo0 + // ---------------------------------------------------- + wire fifo0_mem_clk; + wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; + wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; + wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; + wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; + wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; + wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; + wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; + wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; + + // axi_ram + wire [ 1-1:0] fifo0_axi_rst; + wire [ 4-1:0] fifo0_m_axi_awid; + wire [128-1:0] fifo0_m_axi_awaddr; + wire [ 32-1:0] fifo0_m_axi_awlen; + wire [ 12-1:0] fifo0_m_axi_awsize; + wire [ 8-1:0] fifo0_m_axi_awburst; + wire [ 4-1:0] fifo0_m_axi_awlock; + wire [ 16-1:0] fifo0_m_axi_awcache; + wire [ 12-1:0] fifo0_m_axi_awprot; + wire [ 16-1:0] fifo0_m_axi_awqos; + wire [ 16-1:0] fifo0_m_axi_awregion; + wire [ 4-1:0] fifo0_m_axi_awuser; + wire [ 4-1:0] fifo0_m_axi_awvalid; + wire [ 4-1:0] fifo0_m_axi_awready; + wire [256-1:0] fifo0_m_axi_wdata; + wire [ 32-1:0] fifo0_m_axi_wstrb; + wire [ 4-1:0] fifo0_m_axi_wlast; + wire [ 4-1:0] fifo0_m_axi_wuser; + wire [ 4-1:0] fifo0_m_axi_wvalid; + wire [ 4-1:0] fifo0_m_axi_wready; + wire [ 4-1:0] fifo0_m_axi_bid; + wire [ 8-1:0] fifo0_m_axi_bresp; + wire [ 4-1:0] fifo0_m_axi_buser; + wire [ 4-1:0] fifo0_m_axi_bvalid; + wire [ 4-1:0] fifo0_m_axi_bready; + wire [ 4-1:0] fifo0_m_axi_arid; + wire [128-1:0] fifo0_m_axi_araddr; + wire [ 32-1:0] fifo0_m_axi_arlen; + wire [ 12-1:0] fifo0_m_axi_arsize; + wire [ 8-1:0] fifo0_m_axi_arburst; + wire [ 4-1:0] fifo0_m_axi_arlock; + wire [ 16-1:0] fifo0_m_axi_arcache; + wire [ 12-1:0] fifo0_m_axi_arprot; + wire [ 16-1:0] fifo0_m_axi_arqos; + wire [ 16-1:0] fifo0_m_axi_arregion; + wire [ 4-1:0] fifo0_m_axi_aruser; + wire [ 4-1:0] fifo0_m_axi_arvalid; + wire [ 4-1:0] fifo0_m_axi_arready; + wire [ 4-1:0] fifo0_m_axi_rid; + wire [256-1:0] fifo0_m_axi_rdata; + wire [ 8-1:0] fifo0_m_axi_rresp; + wire [ 4-1:0] fifo0_m_axi_rlast; + wire [ 4-1:0] fifo0_m_axi_ruser; + wire [ 4-1:0] fifo0_m_axi_rvalid; + wire [ 4-1:0] fifo0_m_axi_rready; + + rfnoc_block_axi_ram_fifo #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(4), + .MEM_DATA_W(64), + .MEM_ADDR_W(31), + .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE(303819444), + .MTU(MTU) + ) b_fifo0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk(fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + .axi_rst(fifo0_axi_rst), + .m_axi_awid(fifo0_m_axi_awid), + .m_axi_awaddr(fifo0_m_axi_awaddr), + .m_axi_awlen(fifo0_m_axi_awlen), + .m_axi_awsize(fifo0_m_axi_awsize), + .m_axi_awburst(fifo0_m_axi_awburst), + .m_axi_awlock(fifo0_m_axi_awlock), + .m_axi_awcache(fifo0_m_axi_awcache), + .m_axi_awprot(fifo0_m_axi_awprot), + .m_axi_awqos(fifo0_m_axi_awqos), + .m_axi_awregion(fifo0_m_axi_awregion), + .m_axi_awuser(fifo0_m_axi_awuser), + .m_axi_awvalid(fifo0_m_axi_awvalid), + .m_axi_awready(fifo0_m_axi_awready), + .m_axi_wdata(fifo0_m_axi_wdata), + .m_axi_wstrb(fifo0_m_axi_wstrb), + .m_axi_wlast(fifo0_m_axi_wlast), + .m_axi_wuser(fifo0_m_axi_wuser), + .m_axi_wvalid(fifo0_m_axi_wvalid), + .m_axi_wready(fifo0_m_axi_wready), + .m_axi_bid(fifo0_m_axi_bid), + .m_axi_bresp(fifo0_m_axi_bresp), + .m_axi_buser(fifo0_m_axi_buser), + .m_axi_bvalid(fifo0_m_axi_bvalid), + .m_axi_bready(fifo0_m_axi_bready), + .m_axi_arid(fifo0_m_axi_arid), + .m_axi_araddr(fifo0_m_axi_araddr), + .m_axi_arlen(fifo0_m_axi_arlen), + .m_axi_arsize(fifo0_m_axi_arsize), + .m_axi_arburst(fifo0_m_axi_arburst), + .m_axi_arlock(fifo0_m_axi_arlock), + .m_axi_arcache(fifo0_m_axi_arcache), + .m_axi_arprot(fifo0_m_axi_arprot), + .m_axi_arqos(fifo0_m_axi_arqos), + .m_axi_arregion(fifo0_m_axi_arregion), + .m_axi_aruser(fifo0_m_axi_aruser), + .m_axi_arvalid(fifo0_m_axi_arvalid), + .m_axi_arready(fifo0_m_axi_arready), + .m_axi_rid(fifo0_m_axi_rid), + .m_axi_rdata(fifo0_m_axi_rdata), + .m_axi_rresp(fifo0_m_axi_rresp), + .m_axi_rlast(fifo0_m_axi_rlast), + .m_axi_ruser(fifo0_m_axi_ruser), + .m_axi_rvalid(fifo0_m_axi_rvalid), + .m_axi_rready(fifo0_m_axi_rready), + + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_fifo0_in_0_tready; + + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; + assign m_fifo0_out_0_tready = s_ep4_in0_tready; + + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_fifo0_in_1_tready; + + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; + assign m_fifo0_out_1_tready = s_ep5_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_2_tlast = 1'b0; + assign s_fifo0_in_2_tvalid = 1'b0; + assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_3_tlast = 1'b0; + assign s_fifo0_in_3_tvalid = 1'b0; + assign m_fifo0_out_2_tready = 1'b1; + assign m_fifo0_out_3_tready = 1'b1; + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign fifo0_mem_clk = dram_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign fifo0_axi_rst = axi_rst; + assign m_axi_awid = fifo0_m_axi_awid; + assign m_axi_awaddr = fifo0_m_axi_awaddr; + assign m_axi_awlen = fifo0_m_axi_awlen; + assign m_axi_awsize = fifo0_m_axi_awsize; + assign m_axi_awburst = fifo0_m_axi_awburst; + assign m_axi_awlock = fifo0_m_axi_awlock; + assign m_axi_awcache = fifo0_m_axi_awcache; + assign m_axi_awprot = fifo0_m_axi_awprot; + assign m_axi_awqos = fifo0_m_axi_awqos; + assign m_axi_awregion = fifo0_m_axi_awregion; + assign m_axi_awuser = fifo0_m_axi_awuser; + assign m_axi_awvalid = fifo0_m_axi_awvalid; + assign fifo0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = fifo0_m_axi_wdata; + assign m_axi_wstrb = fifo0_m_axi_wstrb; + assign m_axi_wlast = fifo0_m_axi_wlast; + assign m_axi_wuser = fifo0_m_axi_wuser; + assign m_axi_wvalid = fifo0_m_axi_wvalid; + assign fifo0_m_axi_wready = m_axi_wready; + assign fifo0_m_axi_bid = m_axi_bid; + assign fifo0_m_axi_bresp = m_axi_bresp; + assign fifo0_m_axi_buser = m_axi_buser; + assign fifo0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = fifo0_m_axi_bready; + assign m_axi_arid = fifo0_m_axi_arid; + assign m_axi_araddr = fifo0_m_axi_araddr; + assign m_axi_arlen = fifo0_m_axi_arlen; + assign m_axi_arsize = fifo0_m_axi_arsize; + assign m_axi_arburst = fifo0_m_axi_arburst; + assign m_axi_arlock = fifo0_m_axi_arlock; + assign m_axi_arcache = fifo0_m_axi_arcache; + assign m_axi_arprot = fifo0_m_axi_arprot; + assign m_axi_arqos = fifo0_m_axi_arqos; + assign m_axi_arregion = fifo0_m_axi_arregion; + assign m_axi_aruser = fifo0_m_axi_aruser; + assign m_axi_arvalid = fifo0_m_axi_arvalid; + assign fifo0_m_axi_arready = m_axi_arready; + assign fifo0_m_axi_rid = m_axi_rid; + assign fifo0_m_axi_rdata = m_axi_rdata; + assign fifo0_m_axi_rresp = m_axi_rresp; + assign fifo0_m_axi_rlast = m_axi_rlast; + assign fifo0_m_axi_ruser = m_axi_ruser; + assign fifo0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = fifo0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml new file mode 100644 index 000000000..446c0ae6b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.yml @@ -0,0 +1,87 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n300' +default_target: 'N300_AA' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + # We call the next endpoints 4 and 5 to keep them consistent with the + # N310 version of this file + ep4: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep5: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio_2x64.yml' + fifo0: + block_desc: 'axi_ram_fifo_4x64.yml' + parameters: + # These parameters match the memory interface on the N3XX + NUM_PORTS: 4 + MEM_DATA_W: 64 + MEM_ADDR_W: 31 + FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RF0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RF0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # ep1 to radio0(1) - RF1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # radio0(1) to ep1 - RF1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep4 to fifo0(0) + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + # ep5 to fifo0(1) + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n300_bist_static_router.hex b/fpga/usrp3/top/n3xx/n300_bist_static_router.hex new file mode 100644 index 000000000..99c3acfdf --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_static_router.hex @@ -0,0 +1,9 @@ +00000008 +00400140 +01400040 +00800141 +01410080 +00c00180 +018000c0 +01000181 +01810100 diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v new file mode 100644 index 000000000..064dcf16b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v @@ -0,0 +1,652 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n300) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:12.572410 +// Source: ./n3xx/n300_rfnoc_image_core.yml +// Source SHA256: 0137aa82c54cb7f7e539f2b09d75ec9c2b5d0c97479431953ab78fc8c56b7201 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (5), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_1_tready, m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = rfnoc_chdr_clk; + assign duc0_ce_clk = rfnoc_chdr_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml new file mode 100644 index 000000000..54df51725 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.yml @@ -0,0 +1,78 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n300' +default_target: 'N300_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: # Block HDL parameters + NUM_PORTS: 2 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } diff --git a/fpga/usrp3/top/n3xx/n300_static_router.hex b/fpga/usrp3/top/n3xx/n300_static_router.hex new file mode 100644 index 000000000..6e8701d3a --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_static_router.hex @@ -0,0 +1,9 @@ +00000008 +004000c0 +00c00140 +01400100 +01000040 +008000c1 +00c10141 +01410101 +01010080 diff --git a/fpga/usrp3/top/n3xx/n310_10ge.xdc b/fpga/usrp3/top/n3xx/n310_10ge.xdc new file mode 100644 index 000000000..a55fc1298 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_10ge.xdc @@ -0,0 +1,22 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between bus_clk and the recovered clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. + +# Remove analysis between the xge_clk and the recovered clocks from the MGT PHYs, +# since they cannot be related to one another with any known phase or period. +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks xge_clk] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks xge_clk] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] diff --git a/fpga/usrp3/top/n3xx/n310_1ge.xdc b/fpga/usrp3/top/n3xx/n310_1ge.xdc new file mode 100644 index 000000000..1f38f56b6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_1ge.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# No need for any asynchronous clock groups between clk100 and the recovered clocks, +# because clk100 already has a blanket asynchronous constraint from the top level XDC. +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks net_clk] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT1]] + +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*reset_sync*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige_phy_i/*/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/n3xx/n310_aurora.xdc b/fpga/usrp3/top/n3xx/n310_aurora.xdc new file mode 100644 index 000000000..1a76687e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_aurora.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.v b/fpga/usrp3/top/n3xx/n310_bist_image_core.v new file mode 100644 index 000000000..64989fb3f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.v @@ -0,0 +1,1169 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n310) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:14.371732 +// Source: ./n3xx/n310_bist_image_core.yml +// Source SHA256: 1a9ffb97d9678e700ad2aa172d206b6be9af30c7c0b014c21007d1de028a59d4 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// x300_radio1 + input wire [ 64-1:0] radio_rx_data_radio1, + input wire [ 2-1:0] radio_rx_stb_radio1, + output wire [ 2-1:0] radio_rx_running_radio1, + output wire [ 64-1:0] radio_tx_data_radio1, + input wire [ 2-1:0] radio_tx_stb_radio1, + output wire [ 2-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [CHDR_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [CHDR_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (9), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; + wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (4), + .CTRL_XBAR_PORT (5), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep4_tdata ), + .s_axis_chdr_tlast (xb_to_ep4_tlast ), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), + .s_axis_chdr_tready (xb_to_ep4_tready ), + .m_axis_chdr_tdata (ep4_to_xb_tdata ), + .m_axis_chdr_tlast (ep4_to_xb_tlast ), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), + .m_axis_chdr_tready (ep4_to_xb_tready ), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; + wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (5), + .CTRL_XBAR_PORT (6), + .INGRESS_BUFF_SIZE (14), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep5_tdata ), + .s_axis_chdr_tlast (xb_to_ep5_tlast ), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), + .s_axis_chdr_tready (xb_to_ep5_tready ), + .m_axis_chdr_tdata (ep5_to_xb_tdata ), + .m_axis_chdr_tlast (ep5_to_xb_tlast ), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), + .m_axis_chdr_tready (ep5_to_xb_tready ), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; + wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; + wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; + wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_fifo0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_fifo0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(6), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (12), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // x300_radio + wire [ 64-1:0] radio1_radio_rx_data; + wire [ 2-1:0] radio1_radio_rx_stb; + wire [ 2-1:0] radio1_radio_rx_running; + wire [ 64-1:0] radio1_radio_tx_data; + wire [ 2-1:0] radio1_radio_tx_stb; + wire [ 2-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // fifo0 + // ---------------------------------------------------- + wire fifo0_mem_clk; + wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; + wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; + wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; + wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; + wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; + wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; + wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; + wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; + + // axi_ram + wire [ 1-1:0] fifo0_axi_rst; + wire [ 4-1:0] fifo0_m_axi_awid; + wire [128-1:0] fifo0_m_axi_awaddr; + wire [ 32-1:0] fifo0_m_axi_awlen; + wire [ 12-1:0] fifo0_m_axi_awsize; + wire [ 8-1:0] fifo0_m_axi_awburst; + wire [ 4-1:0] fifo0_m_axi_awlock; + wire [ 16-1:0] fifo0_m_axi_awcache; + wire [ 12-1:0] fifo0_m_axi_awprot; + wire [ 16-1:0] fifo0_m_axi_awqos; + wire [ 16-1:0] fifo0_m_axi_awregion; + wire [ 4-1:0] fifo0_m_axi_awuser; + wire [ 4-1:0] fifo0_m_axi_awvalid; + wire [ 4-1:0] fifo0_m_axi_awready; + wire [256-1:0] fifo0_m_axi_wdata; + wire [ 32-1:0] fifo0_m_axi_wstrb; + wire [ 4-1:0] fifo0_m_axi_wlast; + wire [ 4-1:0] fifo0_m_axi_wuser; + wire [ 4-1:0] fifo0_m_axi_wvalid; + wire [ 4-1:0] fifo0_m_axi_wready; + wire [ 4-1:0] fifo0_m_axi_bid; + wire [ 8-1:0] fifo0_m_axi_bresp; + wire [ 4-1:0] fifo0_m_axi_buser; + wire [ 4-1:0] fifo0_m_axi_bvalid; + wire [ 4-1:0] fifo0_m_axi_bready; + wire [ 4-1:0] fifo0_m_axi_arid; + wire [128-1:0] fifo0_m_axi_araddr; + wire [ 32-1:0] fifo0_m_axi_arlen; + wire [ 12-1:0] fifo0_m_axi_arsize; + wire [ 8-1:0] fifo0_m_axi_arburst; + wire [ 4-1:0] fifo0_m_axi_arlock; + wire [ 16-1:0] fifo0_m_axi_arcache; + wire [ 12-1:0] fifo0_m_axi_arprot; + wire [ 16-1:0] fifo0_m_axi_arqos; + wire [ 16-1:0] fifo0_m_axi_arregion; + wire [ 4-1:0] fifo0_m_axi_aruser; + wire [ 4-1:0] fifo0_m_axi_arvalid; + wire [ 4-1:0] fifo0_m_axi_arready; + wire [ 4-1:0] fifo0_m_axi_rid; + wire [256-1:0] fifo0_m_axi_rdata; + wire [ 8-1:0] fifo0_m_axi_rresp; + wire [ 4-1:0] fifo0_m_axi_rlast; + wire [ 4-1:0] fifo0_m_axi_ruser; + wire [ 4-1:0] fifo0_m_axi_rvalid; + wire [ 4-1:0] fifo0_m_axi_rready; + + rfnoc_block_axi_ram_fifo #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(4), + .MEM_DATA_W(64), + .MEM_ADDR_W(31), + .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), + .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), + .MEM_CLK_RATE(303819444), + .MTU(MTU) + ) b_fifo0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk(fifo0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .axi_rst(fifo0_axi_rst), + .m_axi_awid(fifo0_m_axi_awid), + .m_axi_awaddr(fifo0_m_axi_awaddr), + .m_axi_awlen(fifo0_m_axi_awlen), + .m_axi_awsize(fifo0_m_axi_awsize), + .m_axi_awburst(fifo0_m_axi_awburst), + .m_axi_awlock(fifo0_m_axi_awlock), + .m_axi_awcache(fifo0_m_axi_awcache), + .m_axi_awprot(fifo0_m_axi_awprot), + .m_axi_awqos(fifo0_m_axi_awqos), + .m_axi_awregion(fifo0_m_axi_awregion), + .m_axi_awuser(fifo0_m_axi_awuser), + .m_axi_awvalid(fifo0_m_axi_awvalid), + .m_axi_awready(fifo0_m_axi_awready), + .m_axi_wdata(fifo0_m_axi_wdata), + .m_axi_wstrb(fifo0_m_axi_wstrb), + .m_axi_wlast(fifo0_m_axi_wlast), + .m_axi_wuser(fifo0_m_axi_wuser), + .m_axi_wvalid(fifo0_m_axi_wvalid), + .m_axi_wready(fifo0_m_axi_wready), + .m_axi_bid(fifo0_m_axi_bid), + .m_axi_bresp(fifo0_m_axi_bresp), + .m_axi_buser(fifo0_m_axi_buser), + .m_axi_bvalid(fifo0_m_axi_bvalid), + .m_axi_bready(fifo0_m_axi_bready), + .m_axi_arid(fifo0_m_axi_arid), + .m_axi_araddr(fifo0_m_axi_araddr), + .m_axi_arlen(fifo0_m_axi_arlen), + .m_axi_arsize(fifo0_m_axi_arsize), + .m_axi_arburst(fifo0_m_axi_arburst), + .m_axi_arlock(fifo0_m_axi_arlock), + .m_axi_arcache(fifo0_m_axi_arcache), + .m_axi_arprot(fifo0_m_axi_arprot), + .m_axi_arqos(fifo0_m_axi_arqos), + .m_axi_arregion(fifo0_m_axi_arregion), + .m_axi_aruser(fifo0_m_axi_aruser), + .m_axi_arvalid(fifo0_m_axi_arvalid), + .m_axi_arready(fifo0_m_axi_arready), + .m_axi_rid(fifo0_m_axi_rid), + .m_axi_rdata(fifo0_m_axi_rdata), + .m_axi_rresp(fifo0_m_axi_rresp), + .m_axi_rlast(fifo0_m_axi_rlast), + .m_axi_ruser(fifo0_m_axi_ruser), + .m_axi_rvalid(fifo0_m_axi_rvalid), + .m_axi_rready(fifo0_m_axi_rready), + + .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + assign s_radio1_in_0_tdata = m_ep2_out0_tdata ; + assign s_radio1_in_0_tlast = m_ep2_out0_tlast ; + assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_radio1_in_0_tready; + + assign s_ep2_in0_tdata = m_radio1_out_0_tdata ; + assign s_ep2_in0_tlast = m_radio1_out_0_tlast ; + assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep2_in0_tready; + + assign s_radio1_in_1_tdata = m_ep3_out0_tdata ; + assign s_radio1_in_1_tlast = m_ep3_out0_tlast ; + assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_radio1_in_1_tready; + + assign s_ep3_in0_tdata = m_radio1_out_1_tdata ; + assign s_ep3_in0_tlast = m_radio1_out_1_tlast ; + assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ep3_in0_tready; + + assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; + assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; + assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_fifo0_in_0_tready; + + assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; + assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; + assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; + assign m_fifo0_out_0_tready = s_ep4_in0_tready; + + assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; + assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; + assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_fifo0_in_1_tready; + + assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; + assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; + assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; + assign m_fifo0_out_1_tready = s_ep5_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_2_tlast = 1'b0; + assign s_fifo0_in_2_tvalid = 1'b0; + assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}}; + assign s_fifo0_in_3_tlast = 1'b0; + assign s_fifo0_in_3_tvalid = 1'b0; + assign m_fifo0_out_2_tready = 1'b1; + assign m_fifo0_out_3_tready = 1'b1; + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign radio1_radio_clk = radio_clk; + assign fifo0_mem_clk = dram_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + assign fifo0_axi_rst = axi_rst; + assign m_axi_awid = fifo0_m_axi_awid; + assign m_axi_awaddr = fifo0_m_axi_awaddr; + assign m_axi_awlen = fifo0_m_axi_awlen; + assign m_axi_awsize = fifo0_m_axi_awsize; + assign m_axi_awburst = fifo0_m_axi_awburst; + assign m_axi_awlock = fifo0_m_axi_awlock; + assign m_axi_awcache = fifo0_m_axi_awcache; + assign m_axi_awprot = fifo0_m_axi_awprot; + assign m_axi_awqos = fifo0_m_axi_awqos; + assign m_axi_awregion = fifo0_m_axi_awregion; + assign m_axi_awuser = fifo0_m_axi_awuser; + assign m_axi_awvalid = fifo0_m_axi_awvalid; + assign fifo0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = fifo0_m_axi_wdata; + assign m_axi_wstrb = fifo0_m_axi_wstrb; + assign m_axi_wlast = fifo0_m_axi_wlast; + assign m_axi_wuser = fifo0_m_axi_wuser; + assign m_axi_wvalid = fifo0_m_axi_wvalid; + assign fifo0_m_axi_wready = m_axi_wready; + assign fifo0_m_axi_bid = m_axi_bid; + assign fifo0_m_axi_bresp = m_axi_bresp; + assign fifo0_m_axi_buser = m_axi_buser; + assign fifo0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = fifo0_m_axi_bready; + assign m_axi_arid = fifo0_m_axi_arid; + assign m_axi_araddr = fifo0_m_axi_araddr; + assign m_axi_arlen = fifo0_m_axi_arlen; + assign m_axi_arsize = fifo0_m_axi_arsize; + assign m_axi_arburst = fifo0_m_axi_arburst; + assign m_axi_arlock = fifo0_m_axi_arlock; + assign m_axi_arcache = fifo0_m_axi_arcache; + assign m_axi_arprot = fifo0_m_axi_arprot; + assign m_axi_arqos = fifo0_m_axi_arqos; + assign m_axi_arregion = fifo0_m_axi_arregion; + assign m_axi_aruser = fifo0_m_axi_aruser; + assign m_axi_arvalid = fifo0_m_axi_arvalid; + assign fifo0_m_axi_arready = m_axi_arready; + assign fifo0_m_axi_rid = m_axi_rid; + assign fifo0_m_axi_rdata = m_axi_rdata; + assign fifo0_m_axi_rresp = m_axi_rresp; + assign fifo0_m_axi_rlast = m_axi_rlast; + assign fifo0_m_axi_ruser = m_axi_ruser; + assign fifo0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = fifo0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml new file mode 100644 index 000000000..cb4331b15 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.yml @@ -0,0 +1,107 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bitwidth of the CHDR bus for this block +device: 'n310' +default_target: 'N310_AA' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep4: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep5: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio_2x64.yml' + radio1: + block_desc: 'radio_2x64.yml' + fifo0: + block_desc: 'axi_ram_fifo_4x64.yml' + parameters: + # These parameters match the memory interface on the N3XX + NUM_PORTS: 4 + MEM_DATA_W: 64 + MEM_ADDR_W: 31 + FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RF0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RF0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # ep1 to radio0(1) - RF0 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # radio0(1) to ep1 - RF0 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep2 to radio1(0) - RF1 TX + - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 } + # radio1(0) to ep2 - RF1 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 } + # ep3 to radio1(1) - RF1 TX + - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 } + # radio1(1) to ep3 - RF1 RX + - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 } + # ep4 to fifo0(0) + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + # ep5 to fifo0(1) + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n310_bist_static_router.hex b/fpga/usrp3/top/n3xx/n310_bist_static_router.hex new file mode 100644 index 000000000..1e8382a50 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_bist_static_router.hex @@ -0,0 +1,13 @@ +0000000C +004001c0 +01c00040 +008001c1 +01c10080 +00c00200 +020000c0 +01000201 +02010100 +01400240 +02400140 +01800241 +02410180 diff --git a/fpga/usrp3/top/n3xx/n310_dram.xdc b/fpga/usrp3/top/n3xx/n310_dram.xdc new file mode 100644 index 000000000..4b8218b2b --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_dram.xdc @@ -0,0 +1,33 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# Declare the 100 MHz DRAM subsystem clock. +create_clock -name ddr3_ext_refclk -period 10.0 [get_ports sys_clk_p] + +# Rename IODELAY reference clock outputs from the MMCM inside MIG. +# These are based off the 200 MHz bus_clk. +create_generated_clock -name ddr3_iodelay_refclk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}] +create_generated_clock -name ddr3_iodelay_refclk_fb \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}] + +# Rename the UI clock appropriately. This clocks the slave AXI4 ports of the MIG as well +# as the AXI logic/interconnects in the remainder of the FPGA design. Should be 200 MHz. +create_generated_clock -name ddr3_ui_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT}] + +# Another UI clock at 300 MHz... not quite at 2x due to timing. +create_generated_clock -name ddr3_ui_clk_2x \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0}] + +# Phase shifting clock for the MIG. Drives a few resets. +create_generated_clock -name ddr3_ps_clk \ + [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT5}] + + + +# No need for any asynchronous clock groups between bus_clk and the MIG UI clocks, +# because bus_clk already has a blanket asynchronous constraint from the top level XDC. \ No newline at end of file diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v new file mode 100644 index 000000000..027f176ce --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v @@ -0,0 +1,1062 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n310) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.073656 +// Source: ./n3xx/n310_rfnoc_image_core.yml +// Source SHA256: a4a2464a5fdebb8ac35e78c2ea53ad7be23f8106376098188c9a4caeba8bcf0e + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// x300_radio1 + input wire [ 64-1:0] radio_rx_data_radio1, + input wire [ 2-1:0] radio_rx_stb_radio1, + output wire [ 2-1:0] radio_rx_running_radio1, + output wire [ 64-1:0] radio_tx_data_radio1, + input wire [ 2-1:0] radio_tx_stb_radio1, + output wire [ 2-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (7), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; + wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; + wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (16), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; + wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; + wire s_duc0_in_1_tvalid, s_duc0_in_0_tvalid; + wire s_duc0_in_1_tready, s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_1_tdata , m_duc0_out_0_tdata ; + wire m_duc0_out_1_tlast , m_duc0_out_0_tlast ; + wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; + wire m_duc0_out_1_tready, m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_1_tready, s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_1_tdata , m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_1_tready, m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // duc1 + // ---------------------------------------------------- + wire duc1_ce_clk; + wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; + wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; + wire s_duc1_in_1_tvalid, s_duc1_in_0_tvalid; + wire s_duc1_in_1_tready, s_duc1_in_0_tready; + wire [CHDR_W-1:0] m_duc1_out_1_tdata , m_duc1_out_0_tdata ; + wire m_duc1_out_1_tlast , m_duc1_out_0_tlast ; + wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; + wire m_duc1_out_1_tready, m_duc1_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc1_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + + .s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc1_in_1_tready, s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_1_tdata , m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc1_out_1_tready, m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc1 + // ---------------------------------------------------- + wire ddc1_ce_clk; + wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; + wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; + wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; + wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; + wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; + wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; + wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; + wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(6), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + + + .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // x300_radio + wire [ 64-1:0] radio1_radio_rx_data; + wire [ 2-1:0] radio1_radio_rx_stb; + wire [ 2-1:0] radio1_radio_rx_running; + wire [ 64-1:0] radio1_radio_tx_data; + wire [ 2-1:0] radio1_radio_tx_stb; + wire [ 2-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(7), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc0_in_1_tdata = m_ep1_out0_tdata ; + assign s_duc0_in_1_tlast = m_ep1_out0_tlast ; + assign s_duc0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc0_in_1_tready; + + assign s_radio0_in_1_tdata = m_duc0_out_1_tdata ; + assign s_radio0_in_1_tlast = m_duc0_out_1_tlast ; + assign s_radio0_in_1_tvalid = m_duc0_out_1_tvalid; + assign m_duc0_out_1_tready = s_radio0_in_1_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + assign s_duc1_in_0_tdata = m_ep2_out0_tdata ; + assign s_duc1_in_0_tlast = m_ep2_out0_tlast ; + assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ; + assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep2_in0_tready; + + assign s_duc1_in_1_tdata = m_ep3_out0_tdata ; + assign s_duc1_in_1_tlast = m_ep3_out0_tlast ; + assign s_duc1_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_duc1_in_1_tready; + + assign s_radio1_in_1_tdata = m_duc1_out_1_tdata ; + assign s_radio1_in_1_tlast = m_duc1_out_1_tlast ; + assign s_radio1_in_1_tvalid = m_duc1_out_1_tvalid; + assign m_duc1_out_1_tready = s_radio1_in_1_tready; + + assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ; + assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ; + assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ddc1_in_1_tready; + + assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ; + assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ; + assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid; + assign m_ddc1_out_1_tready = s_ep3_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = rfnoc_chdr_clk; + assign duc0_ce_clk = rfnoc_chdr_clk; + assign radio1_radio_clk = radio_clk; + assign ddc1_ce_clk = rfnoc_chdr_clk; + assign duc1_ce_clk = rfnoc_chdr_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml new file mode 100644 index 000000000..d930baf6f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.yml @@ -0,0 +1,111 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n310' +default_target: 'N310_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 2 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 2 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio1: + block_desc: 'radio_2x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 } + - { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 } + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + - { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 } + - { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 } + - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 } + - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: rfnoc_chdr, dstblk: duc1, dstport: ce } +# - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n310_static_router.hex b/fpga/usrp3/top/n3xx/n310_static_router.hex new file mode 100644 index 000000000..73449b968 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_static_router.hex @@ -0,0 +1,17 @@ +00000010 +00400140 +014001c0 +01c00180 +01800040 +00800141 +014101c1 +01c10181 +01810080 +00c00200 +02000280 +02800240 +024000c0 +01000201 +02010281 +02810241 +02410100 diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v new file mode 100644 index 000000000..875c8ade1 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v @@ -0,0 +1,884 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for n320) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-08T15:58:13.514800 +// Source: ./n3xx/n320_rfnoc_image_core.yml +// Source SHA256: 2641d416e72d1a537f6a832837fc0c9b69675bfe6be7521370900c067742b0bb + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// radio_ch0 + input wire [ 32-1:0] radio_rx_data_radio0, + input wire [ 1-1:0] radio_rx_stb_radio0, + output wire [ 1-1:0] radio_rx_running_radio0, + output wire [ 32-1:0] radio_tx_data_radio0, + input wire [ 1-1:0] radio_tx_stb_radio0, + output wire [ 1-1:0] radio_tx_running_radio0, +// radio_ch1 + input wire [ 32-1:0] radio_rx_data_radio1, + input wire [ 1-1:0] radio_rx_stb_radio1, + output wire [ 1-1:0] radio_rx_running_radio1, + output wire [ 32-1:0] radio_tx_data_radio1, + input wire [ 1-1:0] radio_tx_stb_radio1, + output wire [ 1-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 4-1:0] m_axi_awid, + output wire [128-1:0] m_axi_awaddr, + output wire [ 32-1:0] m_axi_awlen, + output wire [ 12-1:0] m_axi_awsize, + output wire [ 8-1:0] m_axi_awburst, + output wire [ 4-1:0] m_axi_awlock, + output wire [ 16-1:0] m_axi_awcache, + output wire [ 12-1:0] m_axi_awprot, + output wire [ 16-1:0] m_axi_awqos, + output wire [ 16-1:0] m_axi_awregion, + output wire [ 4-1:0] m_axi_awuser, + output wire [ 4-1:0] m_axi_awvalid, + input wire [ 4-1:0] m_axi_awready, + output wire [256-1:0] m_axi_wdata, + output wire [ 32-1:0] m_axi_wstrb, + output wire [ 4-1:0] m_axi_wlast, + output wire [ 4-1:0] m_axi_wuser, + output wire [ 4-1:0] m_axi_wvalid, + input wire [ 4-1:0] m_axi_wready, + input wire [ 4-1:0] m_axi_bid, + input wire [ 8-1:0] m_axi_bresp, + input wire [ 4-1:0] m_axi_buser, + input wire [ 4-1:0] m_axi_bvalid, + output wire [ 4-1:0] m_axi_bready, + output wire [ 4-1:0] m_axi_arid, + output wire [128-1:0] m_axi_araddr, + output wire [ 32-1:0] m_axi_arlen, + output wire [ 12-1:0] m_axi_arsize, + output wire [ 8-1:0] m_axi_arburst, + output wire [ 4-1:0] m_axi_arlock, + output wire [ 16-1:0] m_axi_arcache, + output wire [ 12-1:0] m_axi_arprot, + output wire [ 16-1:0] m_axi_arqos, + output wire [ 16-1:0] m_axi_arregion, + output wire [ 4-1:0] m_axi_aruser, + output wire [ 4-1:0] m_axi_arvalid, + input wire [ 4-1:0] m_axi_arready, + input wire [ 4-1:0] m_axi_rid, + input wire [256-1:0] m_axi_rdata, + input wire [ 8-1:0] m_axi_rresp, + input wire [ 4-1:0] m_axi_rlast, + input wire [ 4-1:0] m_axi_ruser, + input wire [ 4-1:0] m_axi_rvalid, + output wire [ 4-1:0] m_axi_rready, + // Transport 0 (eth0 1G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 10G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (dma dma) + input wire [64-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [64-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (5), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (15), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; + wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; + wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'h1320), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_0_tdata ; + wire s_duc0_in_0_tlast ; + wire s_duc0_in_0_tvalid; + wire s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_0_tdata ; + wire m_duc0_out_0_tlast ; + wire m_duc0_out_0_tvalid; + wire m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_0_tdata ; + wire s_ddc0_in_0_tlast ; + wire s_ddc0_in_0_tvalid; + wire s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_0_tdata ; + wire m_ddc0_out_0_tlast ; + wire m_ddc0_out_0_tvalid; + wire m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_0_tdata ; + wire s_radio0_in_0_tlast ; + wire s_radio0_in_0_tvalid; + wire s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_0_tdata ; + wire m_radio0_out_0_tlast ; + wire m_radio0_out_0_tvalid; + wire m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // radio_iface + wire [ 32-1:0] radio0_radio_rx_data; + wire [ 1-1:0] radio0_radio_rx_stb; + wire [ 1-1:0] radio0_radio_rx_running; + wire [ 32-1:0] radio0_radio_tx_data; + wire [ 1-1:0] radio0_radio_tx_stb; + wire [ 1-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // duc1 + // ---------------------------------------------------- + wire duc1_ce_clk; + wire [CHDR_W-1:0] s_duc1_in_0_tdata ; + wire s_duc1_in_0_tlast ; + wire s_duc1_in_0_tvalid; + wire s_duc1_in_0_tready; + wire [CHDR_W-1:0] m_duc1_out_0_tdata ; + wire m_duc1_out_0_tlast ; + wire m_duc1_out_0_tvalid; + wire m_duc1_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc1_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + + .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc1 + // ---------------------------------------------------- + wire ddc1_ce_clk; + wire [CHDR_W-1:0] s_ddc1_in_0_tdata ; + wire s_ddc1_in_0_tlast ; + wire s_ddc1_in_0_tvalid; + wire s_ddc1_in_0_tready; + wire [CHDR_W-1:0] m_ddc1_out_0_tdata ; + wire m_ddc1_out_0_tlast ; + wire m_ddc1_out_0_tvalid; + wire m_ddc1_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(6), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + + + .s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_0_tdata ; + wire s_radio1_in_0_tlast ; + wire s_radio1_in_0_tvalid; + wire s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_0_tdata ; + wire m_radio1_out_0_tlast ; + wire m_radio1_out_0_tvalid; + wire m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // radio_iface + wire [ 32-1:0] radio1_radio_rx_data; + wire [ 1-1:0] radio1_radio_rx_stb; + wire [ 1-1:0] radio1_radio_rx_running; + wire [ 32-1:0] radio1_radio_tx_data; + wire [ 1-1:0] radio1_radio_tx_stb; + wire [ 1-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(7), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .MTU(MTU) + ) b_radio1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_duc1_in_0_tdata = m_ep1_out0_tdata ; + assign s_duc1_in_0_tlast = m_ep1_out0_tlast ; + assign s_duc1_in_0_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep1_in0_tdata = m_ddc1_out_0_tdata ; + assign s_ep1_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep1_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep1_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = radio_clk; + assign duc0_ce_clk = radio_clk; + assign radio1_radio_clk = radio_clk; + assign ddc1_ce_clk = radio_clk; + assign duc1_ce_clk = radio_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml new file mode 100644 index 000000000..e107eebc7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.yml @@ -0,0 +1,95 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n320' +default_target: 'N320_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 32768 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 1 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + radio0: + block_desc: 'radio_1x64.yml' + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 1 + radio1: + block_desc: 'radio_1x64.yml' + #fifo0: + #block_desc: 'axi_ram_fifo_4x64.yml' + #parameters: + ## These parameters match the memory interface on the N3XX + #NUM_PORTS: 4 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 31 + #FIFO_ADDR_BASE: "{30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + - { srcblk: ep1, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep1, dstport: in0 } + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio_ch0, dstblk: radio0, dstport: radio_iface } + - { srcblk: _device_, srcport: radio_ch1, dstblk: radio1, dstport: radio_iface } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce } +# - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } diff --git a/fpga/usrp3/top/n3xx/n320_static_router.hex b/fpga/usrp3/top/n3xx/n320_static_router.hex new file mode 100644 index 000000000..eeaf5024d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n320_static_router.hex @@ -0,0 +1,9 @@ +00000008 +004000c0 +00c00140 +01400100 +01000040 +00800180 +01800200 +020001c0 +01c00080 diff --git a/fpga/usrp3/top/n3xx/n3xx_clocking.v b/fpga/usrp3/top/n3xx/n3xx_clocking.v new file mode 100644 index 000000000..fc7ecbe49 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_clocking.v @@ -0,0 +1,238 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2017 Ettus Research, A National Instruments Company +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_clocking.v +// +// Purpose: +// +// First, instantiate clock input buffers on all clocks to provide termination +// for the PCB traces. This file also includes the MMCM for generating meas_clk at +// specific rates and a global buffer for the reference clock to be able to use it +// directly within and outside of this module. +// +// Second, PPS inputs from the back panel (called external) and the GPSDO are captured by +// the Reference Clock. Selection is performed amongst these and the internally-generated +// options. +// +// NOTE: BUFGs are NOT instantiated on the following clocks, denoted by the _buf suffix: +// wr_refclk_buf, netclk_buf, gige_refclk_buf, xgige_refclk_buf +// +////////////////////////////////////////////////////////////////////// + +module n3xx_clocking ( + // Input buffers for clocks + input enable_ref_clk_async, // enables the ref_clk BUFG (driven async to ref_clk) + input FPGA_REFCLK_P, FPGA_REFCLK_N, + output ref_clk, + + input WB_20MHz_P, WB_20MHz_N, + output wr_refclk_buf, + + input NETCLK_REF_P, NETCLK_REF_N, + output netclk_buf, + + input NETCLK_P, NETCLK_N, + output gige_refclk_buf, + + input MGT156MHZ_CLK1_P, MGT156MHZ_CLK1_N, + output xgige_refclk_buf, + + // Measurement Clock Generation + input misc_clks_ref, + output meas_clk, + output ddr3_dma_clk, + input misc_clks_reset, + output misc_clks_locked, + + // PPS Capture & Selection + input ext_pps_from_pin, + input gps_pps_from_pin, + input [3:0] pps_select, + output reg pps_refclk + ); + + // Clock Buffering and Generation : /////////////////////////////////////////////////// + // + // Manually instantiate input buffers on all clocks, and a global buffer on the + // Reference Clock for use in the rest of the design. All other clocks must have + // global buffers other places, since the declarations here are for SI purposes. + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire ref_clk_buf; + + // FPGA Reference Clock Buffering + // + // Only require an IBUF and BUFG here, since an MMCM is (thankfully) not needed + // to meet timing with the PPS signal. + IBUFGDS ref_clk_ibuf ( + .O(ref_clk_buf), + .I(FPGA_REFCLK_P), + .IB(FPGA_REFCLK_N) + ); + + // BUFG ref_clk_bufg ( + // .I(ref_clk_buf), + // .O(ref_clk) + // ); + WrapBufg #( + .kEnableIsAsync(1'b1) + ) ref_clk_bufg ( + .ClkIn(ref_clk_buf), + .aCe(enable_ref_clk_async), + .ClkOut(ref_clk) + ); + + // Buffers for SI Purposes + // + // Instantiate buffers on each of these differential clock inputs with DONT_TOUCH + // attributes in order to preserve the internal termination regardless of whether + // these clocks are used in the design. The lack of termination would place the + // voltage swings for these pins outside the acceptable range for the FPGA inputs. + (* dont_touch = "true" *) IBUFGDS wr_refclk_ibuf ( + .I (WB_20MHz_P), + .IB(WB_20MHz_N), + .O (wr_refclk_buf) + ); + + (* dont_touch = "true" *) IBUFGDS netclk_ref_ibuf ( + .I (NETCLK_REF_P), + .IB(NETCLK_REF_N), + .O (netclk_buf) + ); + + // Same deal for the MGT reference clock buffers. + (* dont_touch = "true" *) IBUFDS_GTE2 gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (NETCLK_P), + .IB(NETCLK_N), + .O (gige_refclk_buf) + ); + + (* dont_touch = "true" *) IBUFDS_GTE2 ten_gige_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (MGT156MHZ_CLK1_P), + .IB(MGT156MHZ_CLK1_N), + .O (xgige_refclk_buf) + ); + + // Measurement Clock MMCM Instantiation + // + // This must be an MMCM to hit the weird rates we need for meas_clk. It takes the + // 166.6667 MHz clock from the PS and provides the correct meas_clk rate for the TDC. + // BUFG is embedded in the MMCM files. + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // CLK_OUT1___170.543______0.000______50.0______105.052_____94.905 (meas_clk) + // CLK_OUT2___305.556______0.000______50.0_______93.867_____94.905 (ddr3_dma_clk) + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary________166.666667____________0.010 + + misc_clock_gen misc_clock_gen_i ( + .clk_in (misc_clks_ref), + .meas_clk (meas_clk), + .ddr3_dma_clk (ddr3_dma_clk), + .reset (misc_clks_reset), + .locked (misc_clks_locked) + ); + + + // PPS Capture and Generation : /////////////////////////////////////////////////////// + // + // The following shows the support matrix for PPS with respect to the + // reference clock source and rate. + // _______________________________ + // ____________| PPS | + // | Clocks | External | FPGA | GPSDO | WR | + // |--------------------------------------------| + // |External 10 | x | x | | | + // |Internal 25 | | x | | x | + // |GPSDO 20 | | | x | | + // |--------------------------------------------| + // + /////////////////////////////////////////////////////////////////////////////////////// + + wire pps_ext_refclk; + wire pps_gps_refclk; + wire [3:0] pps_select_refclk; + + // Generate two internal PPS signals, each with a 25% duty cycle, based on + // 10 MHz and 25 MHz Reference Clock rates. Only one will be used at a time. + wire int_pps_10mhz_refclk; + pps_generator #( + .CLK_FREQ(32'd10_000_000), .DUTY_CYCLE(25) + ) pps_gen_10 ( + .clk(ref_clk), .reset(1'b0), .pps(int_pps_10mhz_refclk) + ); + wire int_pps_25mhz_refclk; + pps_generator #( + .CLK_FREQ(32'd25_000_000), .DUTY_CYCLE(25) + ) pps_gen_25 ( + .clk(ref_clk), .reset(1'b0), .pps(int_pps_25mhz_refclk) + ); + + // Capture the external PPSs with a FF before sending them to the mux. To be safe, + // we double-synchronize the external signals. If we meet timing (which we should) + // then this is a two-cycle delay. If we don't meet timing, then it's 1-2 cycles + // and our system timing is thrown off--but at least our downstream logic doesn't + // go metastable! + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) ext_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk) + ); + // Same deal with the GPSDO PPS input. Double-sync, then use it. + synchronizer #( + .FALSE_PATH_TO_IN(0) + ) gps_pps_dsync ( + .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk) + ); + + // Synchronize the select bits over to the reference clock as well. Note that this is + // a vector, so we could have some non-one-hot values creep through when changing. + // See the note below as to why this is safe. + synchronizer #( + .FALSE_PATH_TO_IN(1), + .WIDTH(4) + ) pps_select_dsync ( + .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk) + ); + + // Bit locations for the pps_select vector. + localparam BIT_PPS_SEL_INT_10 = 0; + localparam BIT_PPS_SEL_INT_25 = 1; + localparam BIT_PPS_SEL_EXT = 2; + localparam BIT_PPS_SEL_GPSDO = 3; + + // PPS MUX - selects internal or external PPS. + always @(posedge ref_clk) begin + + // Encoding is one-hot on these bits. It is possible when the vector is being double- + // synchronized to the reference clock domain that there could be multiple bits + // asserted simultaneously. This is not problematic because the order of operations + // in the following selection mux should take over and only one PPS should win. + // This could result in glitches, but that is expected during ANY PPS switchover + // since the switch is performed asynchronously to the PPS signal. + if (pps_select_refclk[BIT_PPS_SEL_INT_10]) + pps_refclk <= int_pps_10mhz_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_INT_25]) + pps_refclk <= int_pps_25mhz_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_EXT]) + pps_refclk <= pps_ext_refclk; + else if (pps_select_refclk[BIT_PPS_SEL_GPSDO]) + pps_refclk <= pps_gps_refclk; + else + pps_refclk <= pps_ext_refclk; // Compatibility with old SW stacks, pps_select_refclk = 0 = external + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/n3xx_core.v b/fpga/usrp3/top/n3xx/n3xx_core.v new file mode 100644 index 000000000..676bc782d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_core.v @@ -0,0 +1,1287 @@ +///////////////////////////////////////////////////////////////////// +// +// Copyright 2017-2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_core +// Description: +// - Motherboard Registers +// - Crossbar +// - Noc Block Radios +// - Noc Block Dram fifo +// - Radio Front End control +// +///////////////////////////////////////////////////////////////////// + +module n3xx_core #( + parameter REG_DWIDTH = 32, // Width of the AXI4-Lite data bus (must be 32 or 64) + parameter REG_AWIDTH = 32, // Width of the address bus + parameter BUS_CLK_RATE = 200000000, // BUS_CLK rate + parameter CHANNEL_WIDTH = 32, + parameter NUM_CHANNELS_PER_RADIO = 1, + parameter NUM_CHANNELS = 4, + parameter NUM_DBOARDS = 2, + parameter NUM_SPI_PER_DBOARD = 8, + parameter USE_CORRECTION = 0, + parameter USE_REPLAY = 0, // 1 for Replay block instead of DMA FIFO + parameter FP_GPIO_WIDTH = 12, // Front panel GPIO width + parameter RFNOC_PROTOVER = {8'd1, 8'd0}, + parameter CHDR_WIDTH = 16'd64 +)( + // Clocks and resets + input radio_clk, + input radio_rst, + input bus_clk, + input bus_rst, + input ddr3_dma_clk, + input clk40, + + // Clocking and PPS Controls/Indicators + input pps, + output reg[3:0] pps_select = 4'h1, + output reg pps_out_enb, + output reg[1:0] pps_select_sfp = 2'b0, + output reg ref_clk_reset, + output reg meas_clk_reset, + input ref_clk_locked, + input meas_clk_locked, + output reg enable_ref_clk_async, + + // Motherboard Registers: AXI lite interface + input s_axi_aclk, + input s_axi_aresetn, + input [REG_AWIDTH-1:0] s_axi_awaddr, + input s_axi_awvalid, + output s_axi_awready, + + input [REG_DWIDTH-1:0] s_axi_wdata, + input [REG_DWIDTH/8-1:0] s_axi_wstrb, + input s_axi_wvalid, + output s_axi_wready, + + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + input [REG_AWIDTH-1:0] s_axi_araddr, + input s_axi_arvalid, + output s_axi_arready, + + output [REG_DWIDTH-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input s_axi_rready, + + // PS GPIO source + input [FP_GPIO_WIDTH-1:0] ps_gpio_out, + input [FP_GPIO_WIDTH-1:0] ps_gpio_tri, + output [FP_GPIO_WIDTH-1:0] ps_gpio_in, + + // Front Panel GPIO + inout [FP_GPIO_WIDTH-1:0] fp_gpio_inout, + + // Radio GPIO control for DSA + output [16*NUM_CHANNELS-1:0] db_gpio_out_flat, + output [16*NUM_CHANNELS-1:0] db_gpio_ddr_flat, + input [16*NUM_CHANNELS-1:0] db_gpio_in_flat, + input [16*NUM_CHANNELS-1:0] db_gpio_fab_flat, + + // Radio ATR + output [NUM_CHANNELS-1:0] rx_atr, + output [NUM_CHANNELS-1:0] tx_atr, + + // Radio Data + input [NUM_CHANNELS-1:0] rx_stb, + input [NUM_CHANNELS-1:0] tx_stb, + input [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx, + output [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx, + + // CPLD + output [NUM_SPI_PER_DBOARD*NUM_DBOARDS-1:0] sen_flat, + output [NUM_DBOARDS-1:0] sclk_flat, + output [NUM_DBOARDS-1:0] mosi_flat, + input [NUM_DBOARDS-1:0] miso_flat, + + // DMA xport adapter to PS + input wire [63:0] s_dma_tdata, + input wire [3:0] s_dma_tuser, + input wire s_dma_tlast, + output wire s_dma_tready, + input wire s_dma_tvalid, + + output wire [63:0] m_dma_tdata, + output wire [3:0] m_dma_tdest, + output wire m_dma_tlast, + input wire m_dma_tready, + output wire m_dma_tvalid, + + // AXI4 (256b@200MHz) interface to DDR3 controller + input ddr3_axi_clk, + input ddr3_axi_rst, + input ddr3_running, + // Write Address Ports + output [3:0] ddr3_axi_awid, + output [31:0] ddr3_axi_awaddr, + output [7:0] ddr3_axi_awlen, + output [2:0] ddr3_axi_awsize, + output [1:0] ddr3_axi_awburst, + output [0:0] ddr3_axi_awlock, + output [3:0] ddr3_axi_awcache, + output [2:0] ddr3_axi_awprot, + output [3:0] ddr3_axi_awqos, + output ddr3_axi_awvalid, + input ddr3_axi_awready, + // Write Data Ports + output [255:0] ddr3_axi_wdata, + output [31:0] ddr3_axi_wstrb, + output ddr3_axi_wlast, + output ddr3_axi_wvalid, + input ddr3_axi_wready, + // Write Response Ports + output ddr3_axi_bready, + input [3:0] ddr3_axi_bid, + input [1:0] ddr3_axi_bresp, + input ddr3_axi_bvalid, + // Read Address Ports + output [3:0] ddr3_axi_arid, + output [31:0] ddr3_axi_araddr, + output [7:0] ddr3_axi_arlen, + output [2:0] ddr3_axi_arsize, + output [1:0] ddr3_axi_arburst, + output [0:0] ddr3_axi_arlock, + output [3:0] ddr3_axi_arcache, + output [2:0] ddr3_axi_arprot, + output [3:0] ddr3_axi_arqos, + output ddr3_axi_arvalid, + input ddr3_axi_arready, + // Read Data Ports + output ddr3_axi_rready, + input [3:0] ddr3_axi_rid, + input [255:0] ddr3_axi_rdata, + input [1:0] ddr3_axi_rresp, + input ddr3_axi_rlast, + input ddr3_axi_rvalid, + + // v2e (vita to ethernet) and e2v (eth to vita) + output [63:0] v2e0_tdata, + output v2e0_tvalid, + output v2e0_tlast, + input v2e0_tready, + + output [63:0] v2e1_tdata, + output v2e1_tlast, + output v2e1_tvalid, + input v2e1_tready, + + input [63:0] e2v0_tdata, + input e2v0_tlast, + input e2v0_tvalid, + output e2v0_tready, + + input [63:0] e2v1_tdata, + input e2v1_tlast, + input e2v1_tvalid, + output e2v1_tready, + + // RegPort interface to NPIO + output reg_wr_req_npio, + output [REG_AWIDTH-1:0] reg_wr_addr_npio, + output [REG_DWIDTH-1:0] reg_wr_data_npio, + output reg_rd_req_npio, + output [REG_AWIDTH-1:0] reg_rd_addr_npio, + input reg_rd_resp_npio, + input [REG_DWIDTH-1:0] reg_rd_data_npio, + + // Misc + input [31:0] build_datestamp, + input [31:0] xadc_readback, + input [63:0] sfp_ports_info, + output reg [15:0] device_id +); + + ///////////////////////////////////////////////////////////////////////////////// + // + // FPGA Compatibility Number + // Rules for modifying compat number: + // - Major is updated when the FPGA is changed and requires a software + // change as a result. + // - Minor is updated when a new feature is added to the FPGA that does not + // break software compatibility. + // + ///////////////////////////////////////////////////////////////////////////////// + + localparam [15:0] COMPAT_MAJOR = 16'd7; + localparam [15:0] COMPAT_MINOR = 16'd0; + ///////////////////////////////////////////////////////////////////////////////// + + ///////////////////////////////////////////////////////////////////////////////// + // Motherboard Registers + ///////////////////////////////////////////////////////////////////////////////// + + // Register base + localparam REG_BASE_MISC = 14'h0; + localparam REG_BASE_TIMEKEEPER = 14'h1000; + + // Misc Motherboard Registers + localparam REG_COMPAT_NUM = REG_BASE_MISC + 14'h00; + localparam REG_DATESTAMP = REG_BASE_MISC + 14'h04; + localparam REG_GIT_HASH = REG_BASE_MISC + 14'h08; + localparam REG_SCRATCH = REG_BASE_MISC + 14'h0C; + localparam REG_DEVICE_ID = REG_BASE_MISC + 14'h10; + localparam REG_RFNOC_INFO = REG_BASE_MISC + 14'h14; + localparam REG_CLOCK_CTRL = REG_BASE_MISC + 14'h18; + localparam REG_XADC_READBACK = REG_BASE_MISC + 14'h1C; + localparam REG_BUS_CLK_RATE = REG_BASE_MISC + 14'h20; + localparam REG_BUS_CLK_COUNT = REG_BASE_MISC + 14'h24; + localparam REG_SFP_PORT0_INFO = REG_BASE_MISC + 14'h28; + localparam REG_SFP_PORT1_INFO = REG_BASE_MISC + 14'h2C; + localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; + localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; + localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + + localparam NUM_TIMEKEEPERS = 16'd1; + + wire m_ctrlport_req_wr_radio0; + wire m_ctrlport_req_rd_radio0; + wire [19:0] m_ctrlport_req_addr_radio0; + wire [31:0] m_ctrlport_req_data_radio0; + wire [3:0] m_ctrlport_req_byte_en_radio0; + wire m_ctrlport_req_has_time_radio0; + wire [63:0] m_ctrlport_req_time_radio0; + wire m_ctrlport_resp_ack_radio0; + wire [1:0] m_ctrlport_resp_status_radio0; + wire [31:0] m_ctrlport_resp_data_radio0; + `ifndef N300 + wire m_ctrlport_req_wr_radio1; + wire m_ctrlport_req_rd_radio1; + wire [19:0] m_ctrlport_req_addr_radio1; + wire [31:0] m_ctrlport_req_data_radio1; + wire [3:0] m_ctrlport_req_byte_en_radio1; + wire m_ctrlport_req_has_time_radio1; + wire [63:0] m_ctrlport_req_time_radio1; + wire m_ctrlport_resp_ack_radio1; + wire [1:0] m_ctrlport_resp_status_radio1; + wire [31:0] m_ctrlport_resp_data_radio1; + `endif + + reg [31:0] scratch_reg = 32'b0; + reg [31:0] bus_counter = 32'h0; + reg [31:0] fp_gpio_master_reg = 32'h0; + reg [31:0] fp_gpio_src_reg = 32'h0; + + always @(posedge bus_clk) begin + if (bus_rst) + bus_counter <= 32'd0; + else + bus_counter <= bus_counter + 32'd1; + end + + // Regport + wire reg_wr_req; + wire [REG_AWIDTH-1:0] reg_wr_addr; + wire [REG_DWIDTH-1:0] reg_wr_data; + wire reg_rd_req; + wire [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [REG_DWIDTH-1:0] reg_rd_data; + + reg reg_rd_resp_glob; + reg [REG_DWIDTH-1:0] reg_rd_data_glob; + wire reg_rd_resp_tk; + wire [REG_DWIDTH-1:0] reg_rd_data_tk; + + regport_resp_mux #( + .WIDTH(REG_DWIDTH), + .NUM_SLAVES(3) + ) inst_mboard_regport_resp_mux ( + .clk(bus_clk), + .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_npio, reg_rd_resp_glob, reg_rd_resp_tk}), + .sla_rd_data({reg_rd_data_npio, reg_rd_data_glob, reg_rd_data_tk}), + .mst_rd_resp(reg_rd_resp), + .mst_rd_data(reg_rd_data) + ); + + // Regport Master to convert AXI4-Lite to regport + axil_regport_master #( + .DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .AWIDTH (REG_AWIDTH), // Width of the address bus + .WRBASE (0), // Write address base + .RDBASE (0), // Read address base + .TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles + ) mboard_regport_master_i ( + // Clock and reset + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + // AXI4-Lite: Write address port (domain: s_axi_aclk) + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // AXI4-Lite: Write data port (domain: s_axi_aclk) + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // AXI4-Lite: Write response port (domain: s_axi_aclk) + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // AXI4-Lite: Read address port (domain: s_axi_aclk) + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // AXI4-Lite: Read data port (domain: s_axi_aclk) + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // Register port: Write port (domain: reg_clk) + .reg_clk (bus_clk), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_wr_keep (/*unused*/), + // Register port: Read port (domain: reg_clk) + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp), + .reg_rd_data (reg_rd_data) + ); + + assign reg_wr_req_npio = reg_wr_req; + assign reg_wr_addr_npio = reg_wr_addr; + assign reg_wr_data_npio = reg_wr_data; + assign reg_rd_req_npio = reg_rd_req; + assign reg_rd_addr_npio = reg_rd_addr; + + reg b_ref_clk_locked_ms; + reg b_ref_clk_locked; + reg b_meas_clk_locked_ms; + reg b_meas_clk_locked; + + // Write Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + scratch_reg <= 32'h0; + fp_gpio_master_reg <= 32'h0; + fp_gpio_src_reg <= 32'h0; + pps_select <= 4'h1; + pps_select_sfp <= 2'h0; + pps_out_enb <= 1'b0; + ref_clk_reset <= 1'b0; + meas_clk_reset <= 1'b0; + enable_ref_clk_async <= 1'b1; + device_id <= 16'h0; + end else if (reg_wr_req) begin + case (reg_wr_addr) + REG_DEVICE_ID: begin + device_id <= reg_wr_data[15:0]; + end + REG_FP_GPIO_MASTER: begin + fp_gpio_master_reg <= reg_wr_data; + end + REG_FP_GPIO_RADIO_SRC: begin + fp_gpio_src_reg <= reg_wr_data; + end + REG_SCRATCH: begin + scratch_reg <= reg_wr_data; + end + REG_CLOCK_CTRL: begin + pps_select <= reg_wr_data[3:0]; + pps_out_enb <= reg_wr_data[4]; + pps_select_sfp <= reg_wr_data[6:5]; + ref_clk_reset <= reg_wr_data[8]; + meas_clk_reset <= reg_wr_data[12]; + // This bit is defined as "to disable, write '1' to bit 16" for backwards + // compatibility. + enable_ref_clk_async <= ~reg_wr_data[16]; + end + endcase + end + end + + // Read Registers + always @ (posedge bus_clk) begin + if (bus_rst) begin + reg_rd_resp_glob <= 1'b0; + b_ref_clk_locked_ms <= 1'b0; + b_ref_clk_locked <= 1'b0; + b_meas_clk_locked_ms <= 1'b0; + b_meas_clk_locked <= 1'b0; + end + else begin + + // double-sync the locked bits into the bus_clk domain before using them + b_ref_clk_locked_ms <= ref_clk_locked; + b_ref_clk_locked <= b_ref_clk_locked_ms; + b_meas_clk_locked_ms <= meas_clk_locked; + b_meas_clk_locked <= b_meas_clk_locked_ms; + + if (reg_rd_req) begin + reg_rd_resp_glob <= 1'b1; + + case (reg_rd_addr) + REG_DEVICE_ID: + reg_rd_data_glob <= device_id; + + REG_RFNOC_INFO: + reg_rd_data_glob <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + + REG_COMPAT_NUM: + reg_rd_data_glob <= {COMPAT_MAJOR, COMPAT_MINOR}; + + REG_DATESTAMP: + reg_rd_data_glob <= build_datestamp; + + REG_GIT_HASH: + `ifndef GIT_HASH + `define GIT_HASH 32'h0BADC0DE + `endif + reg_rd_data_glob <= `GIT_HASH; + + REG_FP_GPIO_MASTER: + reg_rd_data_glob <= fp_gpio_master_reg; + + REG_FP_GPIO_RADIO_SRC: + reg_rd_data_glob <= fp_gpio_src_reg; + + REG_SCRATCH: + reg_rd_data_glob <= scratch_reg; + + REG_CLOCK_CTRL: begin + reg_rd_data_glob <= 32'b0; + reg_rd_data_glob[3:0] <= pps_select; + reg_rd_data_glob[4] <= pps_out_enb; + reg_rd_data_glob[6:5] <= pps_select_sfp; + reg_rd_data_glob[8] <= ref_clk_reset; + reg_rd_data_glob[9] <= b_ref_clk_locked; + reg_rd_data_glob[12] <= meas_clk_reset; + reg_rd_data_glob[13] <= b_meas_clk_locked; + reg_rd_data_glob[16] <= ~enable_ref_clk_async; + end + + REG_XADC_READBACK: + reg_rd_data_glob <= xadc_readback; + + REG_BUS_CLK_RATE: + reg_rd_data_glob <= BUS_CLK_RATE; + + REG_BUS_CLK_COUNT: + reg_rd_data_glob <= bus_counter; + + REG_SFP_PORT0_INFO: + reg_rd_data_glob <= sfp_ports_info[31:0]; + + REG_SFP_PORT1_INFO: + reg_rd_data_glob <= sfp_ports_info[63:32]; + + REG_NUM_TIMEKEEPERS: + reg_rd_data_glob <= NUM_TIMEKEEPERS; + + default: + reg_rd_resp_glob <= 1'b0; + endcase + end + else if (reg_rd_resp_glob) begin + reg_rd_resp_glob <= 1'b0; + end + end + end + + ///////////////////////////////////////////////////////////////////////////// + // + // DMA Transport Adapter + // + ///////////////////////////////////////////////////////////////////////////// + wire [63:0] dmao_tdata; + wire dmao_tlast; + wire dmao_tvalid; + wire dmao_tready; + + wire [63:0] dmai_tdata; + wire dmai_tlast; + wire dmai_tvalid; + wire dmai_tready; + + liberio_chdr64_adapter #( + .DMA_ID_WIDTH (4) + ) dma_xport_adapter ( + .clk (bus_clk), + .rst (bus_rst), + .device_id (device_id), + // From DMA engine to core + .s_dma_tdata (s_dma_tdata), + .s_dma_tuser (s_dma_tuser), + .s_dma_tlast (s_dma_tlast), + .s_dma_tvalid (s_dma_tvalid), + .s_dma_tready (s_dma_tready), + // From core to DMA engine + .m_dma_tdata (m_dma_tdata), + .m_dma_tuser (m_dma_tdest), + .m_dma_tlast (m_dma_tlast), + .m_dma_tvalid (m_dma_tvalid), + .m_dma_tready (m_dma_tready), + // CHDR buses + .s_chdr_tdata (dmao_tdata), + .s_chdr_tlast (dmao_tlast), + .s_chdr_tvalid (dmao_tvalid), + .s_chdr_tready (dmao_tready), + .m_chdr_tdata (dmai_tdata), + .m_chdr_tlast (dmai_tlast), + .m_chdr_tvalid (dmai_tvalid), + .m_chdr_tready (dmai_tready) + ); + + ///////////////////////////////////////////////////////////////////// + // + // AXI Interconnect + // + ///////////////////////////////////////////////////////////////////// + + localparam NUM_DRAM_FIFOS = 4; + localparam DRAM_FIFO_INPUT_BUFF_SIZE = 8'd13; + + wire ddr3_dma_rst; + synchronizer #( + .INITIAL_VAL(1'b1) + ) ddr3_dma_rst_sync_i ( + .clk(ddr3_dma_clk), .rst(1'b0), .in(ddr3_axi_rst), .out(ddr3_dma_rst) + ); + + // AXI4 MM buses + wire [0:0] dram_axi_awid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_awaddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_awlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_awburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_awprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_awregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_awuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_awready [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_wdata [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_wstrb [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_wuser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_wready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_bid [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_bresp [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_buser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_bready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arid [0:NUM_DRAM_FIFOS-1]; + wire [31:0] dram_axi_araddr [0:NUM_DRAM_FIFOS-1]; + wire [7:0] dram_axi_arlen [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arsize [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_arburst [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_arlock [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arcache [0:NUM_DRAM_FIFOS-1]; + wire [2:0] dram_axi_arprot [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arqos [0:NUM_DRAM_FIFOS-1]; + wire [3:0] dram_axi_arregion [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_aruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_arready [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_rid [0:NUM_DRAM_FIFOS-1]; + wire [63:0] dram_axi_rdata [0:NUM_DRAM_FIFOS-1]; + wire [1:0] dram_axi_rresp [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rlast [0:NUM_DRAM_FIFOS-1]; + wire [0:0] dram_axi_ruser [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rvalid [0:NUM_DRAM_FIFOS-1]; + wire dram_axi_rready [0:NUM_DRAM_FIFOS-1]; + + axi_intercon_4x64_256_bd_wrapper axi_intercon_2x64_256_bd_i ( + .S00_AXI_ACLK (ddr3_dma_clk ), + .S00_AXI_ARESETN (~ddr3_dma_rst ), + .S00_AXI_AWID (dram_axi_awid [0]), + .S00_AXI_AWADDR (dram_axi_awaddr [0]), + .S00_AXI_AWLEN (dram_axi_awlen [0]), + .S00_AXI_AWSIZE (dram_axi_awsize [0]), + .S00_AXI_AWBURST (dram_axi_awburst [0]), + .S00_AXI_AWLOCK (dram_axi_awlock [0]), + .S00_AXI_AWCACHE (dram_axi_awcache [0]), + .S00_AXI_AWPROT (dram_axi_awprot [0]), + .S00_AXI_AWQOS (dram_axi_awqos [0]), + .S00_AXI_AWREGION (dram_axi_awregion[0]), + .S00_AXI_AWVALID (dram_axi_awvalid [0]), + .S00_AXI_AWREADY (dram_axi_awready [0]), + .S00_AXI_WDATA (dram_axi_wdata [0]), + .S00_AXI_WSTRB (dram_axi_wstrb [0]), + .S00_AXI_WLAST (dram_axi_wlast [0]), + .S00_AXI_WVALID (dram_axi_wvalid [0]), + .S00_AXI_WREADY (dram_axi_wready [0]), + .S00_AXI_BID (dram_axi_bid [0]), + .S00_AXI_BRESP (dram_axi_bresp [0]), + .S00_AXI_BVALID (dram_axi_bvalid [0]), + .S00_AXI_BREADY (dram_axi_bready [0]), + .S00_AXI_ARID (dram_axi_arid [0]), + .S00_AXI_ARADDR (dram_axi_araddr [0]), + .S00_AXI_ARLEN (dram_axi_arlen [0]), + .S00_AXI_ARSIZE (dram_axi_arsize [0]), + .S00_AXI_ARBURST (dram_axi_arburst [0]), + .S00_AXI_ARLOCK (dram_axi_arlock [0]), + .S00_AXI_ARCACHE (dram_axi_arcache [0]), + .S00_AXI_ARPROT (dram_axi_arprot [0]), + .S00_AXI_ARQOS (dram_axi_arqos [0]), + .S00_AXI_ARREGION (dram_axi_arregion[0]), + .S00_AXI_ARVALID (dram_axi_arvalid [0]), + .S00_AXI_ARREADY (dram_axi_arready [0]), + .S00_AXI_RID (dram_axi_rid [0]), + .S00_AXI_RDATA (dram_axi_rdata [0]), + .S00_AXI_RRESP (dram_axi_rresp [0]), + .S00_AXI_RLAST (dram_axi_rlast [0]), + .S00_AXI_RVALID (dram_axi_rvalid [0]), + .S00_AXI_RREADY (dram_axi_rready [0]), + // + .S01_AXI_ACLK (ddr3_dma_clk ), + .S01_AXI_ARESETN (~ddr3_dma_rst ), + .S01_AXI_AWID (dram_axi_awid [1]), + .S01_AXI_AWADDR (dram_axi_awaddr [1]), + .S01_AXI_AWLEN (dram_axi_awlen [1]), + .S01_AXI_AWSIZE (dram_axi_awsize [1]), + .S01_AXI_AWBURST (dram_axi_awburst [1]), + .S01_AXI_AWLOCK (dram_axi_awlock [1]), + .S01_AXI_AWCACHE (dram_axi_awcache [1]), + .S01_AXI_AWPROT (dram_axi_awprot [1]), + .S01_AXI_AWQOS (dram_axi_awqos [1]), + .S01_AXI_AWREGION (dram_axi_awregion[1]), + .S01_AXI_AWVALID (dram_axi_awvalid [1]), + .S01_AXI_AWREADY (dram_axi_awready [1]), + .S01_AXI_WDATA (dram_axi_wdata [1]), + .S01_AXI_WSTRB (dram_axi_wstrb [1]), + .S01_AXI_WLAST (dram_axi_wlast [1]), + .S01_AXI_WVALID (dram_axi_wvalid [1]), + .S01_AXI_WREADY (dram_axi_wready [1]), + .S01_AXI_BID (dram_axi_bid [1]), + .S01_AXI_BRESP (dram_axi_bresp [1]), + .S01_AXI_BVALID (dram_axi_bvalid [1]), + .S01_AXI_BREADY (dram_axi_bready [1]), + .S01_AXI_ARID (dram_axi_arid [1]), + .S01_AXI_ARADDR (dram_axi_araddr [1]), + .S01_AXI_ARLEN (dram_axi_arlen [1]), + .S01_AXI_ARSIZE (dram_axi_arsize [1]), + .S01_AXI_ARBURST (dram_axi_arburst [1]), + .S01_AXI_ARLOCK (dram_axi_arlock [1]), + .S01_AXI_ARCACHE (dram_axi_arcache [1]), + .S01_AXI_ARPROT (dram_axi_arprot [1]), + .S01_AXI_ARQOS (dram_axi_arqos [1]), + .S01_AXI_ARREGION (dram_axi_arregion[1]), + .S01_AXI_ARVALID (dram_axi_arvalid [1]), + .S01_AXI_ARREADY (dram_axi_arready [1]), + .S01_AXI_RID (dram_axi_rid [1]), + .S01_AXI_RDATA (dram_axi_rdata [1]), + .S01_AXI_RRESP (dram_axi_rresp [1]), + .S01_AXI_RLAST (dram_axi_rlast [1]), + .S01_AXI_RVALID (dram_axi_rvalid [1]), + .S01_AXI_RREADY (dram_axi_rready [1]), + // + .S02_AXI_ACLK (ddr3_dma_clk ), + .S02_AXI_ARESETN (~ddr3_dma_rst ), + .S02_AXI_AWID (dram_axi_awid [2]), + .S02_AXI_AWADDR (dram_axi_awaddr [2]), + .S02_AXI_AWLEN (dram_axi_awlen [2]), + .S02_AXI_AWSIZE (dram_axi_awsize [2]), + .S02_AXI_AWBURST (dram_axi_awburst [2]), + .S02_AXI_AWLOCK (dram_axi_awlock [2]), + .S02_AXI_AWCACHE (dram_axi_awcache [2]), + .S02_AXI_AWPROT (dram_axi_awprot [2]), + .S02_AXI_AWQOS (dram_axi_awqos [2]), + .S02_AXI_AWREGION (dram_axi_awregion[2]), + .S02_AXI_AWVALID (dram_axi_awvalid [2]), + .S02_AXI_AWREADY (dram_axi_awready [2]), + .S02_AXI_WDATA (dram_axi_wdata [2]), + .S02_AXI_WSTRB (dram_axi_wstrb [2]), + .S02_AXI_WLAST (dram_axi_wlast [2]), + .S02_AXI_WVALID (dram_axi_wvalid [2]), + .S02_AXI_WREADY (dram_axi_wready [2]), + .S02_AXI_BID (dram_axi_bid [2]), + .S02_AXI_BRESP (dram_axi_bresp [2]), + .S02_AXI_BVALID (dram_axi_bvalid [2]), + .S02_AXI_BREADY (dram_axi_bready [2]), + .S02_AXI_ARID (dram_axi_arid [2]), + .S02_AXI_ARADDR (dram_axi_araddr [2]), + .S02_AXI_ARLEN (dram_axi_arlen [2]), + .S02_AXI_ARSIZE (dram_axi_arsize [2]), + .S02_AXI_ARBURST (dram_axi_arburst [2]), + .S02_AXI_ARLOCK (dram_axi_arlock [2]), + .S02_AXI_ARCACHE (dram_axi_arcache [2]), + .S02_AXI_ARPROT (dram_axi_arprot [2]), + .S02_AXI_ARQOS (dram_axi_arqos [2]), + .S02_AXI_ARREGION (dram_axi_arregion[2]), + .S02_AXI_ARVALID (dram_axi_arvalid [2]), + .S02_AXI_ARREADY (dram_axi_arready [2]), + .S02_AXI_RID (dram_axi_rid [2]), + .S02_AXI_RDATA (dram_axi_rdata [2]), + .S02_AXI_RRESP (dram_axi_rresp [2]), + .S02_AXI_RLAST (dram_axi_rlast [2]), + .S02_AXI_RVALID (dram_axi_rvalid [2]), + .S02_AXI_RREADY (dram_axi_rready [2]), + // + .S03_AXI_ACLK (ddr3_dma_clk ), + .S03_AXI_ARESETN (~ddr3_dma_rst ), + .S03_AXI_AWID (dram_axi_awid [3]), + .S03_AXI_AWADDR (dram_axi_awaddr [3]), + .S03_AXI_AWLEN (dram_axi_awlen [3]), + .S03_AXI_AWSIZE (dram_axi_awsize [3]), + .S03_AXI_AWBURST (dram_axi_awburst [3]), + .S03_AXI_AWLOCK (dram_axi_awlock [3]), + .S03_AXI_AWCACHE (dram_axi_awcache [3]), + .S03_AXI_AWPROT (dram_axi_awprot [3]), + .S03_AXI_AWQOS (dram_axi_awqos [3]), + .S03_AXI_AWREGION (dram_axi_awregion[3]), + .S03_AXI_AWVALID (dram_axi_awvalid [3]), + .S03_AXI_AWREADY (dram_axi_awready [3]), + .S03_AXI_WDATA (dram_axi_wdata [3]), + .S03_AXI_WSTRB (dram_axi_wstrb [3]), + .S03_AXI_WLAST (dram_axi_wlast [3]), + .S03_AXI_WVALID (dram_axi_wvalid [3]), + .S03_AXI_WREADY (dram_axi_wready [3]), + .S03_AXI_BID (dram_axi_bid [3]), + .S03_AXI_BRESP (dram_axi_bresp [3]), + .S03_AXI_BVALID (dram_axi_bvalid [3]), + .S03_AXI_BREADY (dram_axi_bready [3]), + .S03_AXI_ARID (dram_axi_arid [3]), + .S03_AXI_ARADDR (dram_axi_araddr [3]), + .S03_AXI_ARLEN (dram_axi_arlen [3]), + .S03_AXI_ARSIZE (dram_axi_arsize [3]), + .S03_AXI_ARBURST (dram_axi_arburst [3]), + .S03_AXI_ARLOCK (dram_axi_arlock [3]), + .S03_AXI_ARCACHE (dram_axi_arcache [3]), + .S03_AXI_ARPROT (dram_axi_arprot [3]), + .S03_AXI_ARQOS (dram_axi_arqos [3]), + .S03_AXI_ARREGION (dram_axi_arregion[3]), + .S03_AXI_ARVALID (dram_axi_arvalid [3]), + .S03_AXI_ARREADY (dram_axi_arready [3]), + .S03_AXI_RID (dram_axi_rid [3]), + .S03_AXI_RDATA (dram_axi_rdata [3]), + .S03_AXI_RRESP (dram_axi_rresp [3]), + .S03_AXI_RLAST (dram_axi_rlast [3]), + .S03_AXI_RVALID (dram_axi_rvalid [3]), + .S03_AXI_RREADY (dram_axi_rready [3]), + // + .M00_AXI_ACLK (ddr3_axi_clk ), + .M00_AXI_ARESETN (~ddr3_axi_rst ), + .M00_AXI_AWID (ddr3_axi_awid ), + .M00_AXI_AWADDR (ddr3_axi_awaddr ), + .M00_AXI_AWLEN (ddr3_axi_awlen ), + .M00_AXI_AWSIZE (ddr3_axi_awsize ), + .M00_AXI_AWBURST (ddr3_axi_awburst ), + .M00_AXI_AWLOCK (ddr3_axi_awlock ), + .M00_AXI_AWCACHE (ddr3_axi_awcache ), + .M00_AXI_AWPROT (ddr3_axi_awprot ), + .M00_AXI_AWQOS (ddr3_axi_awqos ), + .M00_AXI_AWREGION ( ), + .M00_AXI_AWVALID (ddr3_axi_awvalid ), + .M00_AXI_AWREADY (ddr3_axi_awready ), + .M00_AXI_WDATA (ddr3_axi_wdata ), + .M00_AXI_WSTRB (ddr3_axi_wstrb ), + .M00_AXI_WLAST (ddr3_axi_wlast ), + .M00_AXI_WVALID (ddr3_axi_wvalid ), + .M00_AXI_WREADY (ddr3_axi_wready ), + .M00_AXI_BID (ddr3_axi_bid ), + .M00_AXI_BRESP (ddr3_axi_bresp ), + .M00_AXI_BVALID (ddr3_axi_bvalid ), + .M00_AXI_BREADY (ddr3_axi_bready ), + .M00_AXI_ARID (ddr3_axi_arid ), + .M00_AXI_ARADDR (ddr3_axi_araddr ), + .M00_AXI_ARLEN (ddr3_axi_arlen ), + .M00_AXI_ARSIZE (ddr3_axi_arsize ), + .M00_AXI_ARBURST (ddr3_axi_arburst ), + .M00_AXI_ARLOCK (ddr3_axi_arlock ), + .M00_AXI_ARCACHE (ddr3_axi_arcache ), + .M00_AXI_ARPROT (ddr3_axi_arprot ), + .M00_AXI_ARQOS (ddr3_axi_arqos ), + .M00_AXI_ARREGION ( ), + .M00_AXI_ARVALID (ddr3_axi_arvalid ), + .M00_AXI_ARREADY (ddr3_axi_arready ), + .M00_AXI_RID (ddr3_axi_rid ), + .M00_AXI_RDATA (ddr3_axi_rdata ), + .M00_AXI_RRESP (ddr3_axi_rresp ), + .M00_AXI_RLAST (ddr3_axi_rlast ), + .M00_AXI_RVALID (ddr3_axi_rvalid ), + .M00_AXI_RREADY (ddr3_axi_rready ) + ); + + + ///////////////////////////////////////////////////////////////////////////// + // + // Radios + // + ///////////////////////////////////////////////////////////////////////////// + + + wire [NUM_SPI_PER_DBOARD-1:0] sen[0:NUM_CHANNELS-1]; + wire sclk[0:NUM_CHANNELS-1], mosi[0:NUM_CHANNELS-1], miso[0:NUM_CHANNELS-1]; + // Data + wire [CHANNEL_WIDTH-1:0] rx_int[0:NUM_CHANNELS-1], tx_int[0:NUM_CHANNELS-1]; + wire [CHANNEL_WIDTH-1:0] rx_data[0:NUM_CHANNELS-1], tx_data[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_set_addr[0:NUM_CHANNELS-1]; + wire [31:0] db_fe_set_data[0:NUM_CHANNELS-1]; + wire db_fe_rb_stb[0:NUM_CHANNELS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_CHANNELS-1]; + wire [63:0] db_fe_rb_data[0:NUM_CHANNELS-1]; + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + + genvar i; + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: gen_gpio_control + assign rx_atr[i] = rx_running[i]; + assign tx_atr[i] = tx_running[i]; + end + endgenerate + + + ///////////////////////////////////////////////////////////////////////////////// + // + // TX/RX FrontEnd + // + ///////////////////////////////////////////////////////////////////////////////// + + wire [15:0] db_gpio_in[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_out[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_ddr[0:NUM_CHANNELS-1]; + wire [15:0] db_gpio_fab[0:NUM_CHANNELS-1]; + + wire [31:0] radio_gpio_out[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_ddr[0:NUM_CHANNELS-1]; + wire [31:0] radio_gpio_in[0:NUM_CHANNELS-1]; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_out; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_out_reg; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_ddr_reg; + reg [FP_GPIO_WIDTH-1:0] radio_gpio_src_in; + wire [FP_GPIO_WIDTH-1:0] radio_gpio_sync; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_in_int; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_out_int; + wire [FP_GPIO_WIDTH-1:0] fp_gpio_ddr_int; + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + // Radio Data + assign rx_int[i] = rx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; + assign tx[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = tx_int[i]; + // GPIO + assign db_gpio_out_flat[16*i+15:16*i] = db_gpio_out[i]; + assign db_gpio_ddr_flat[16*i+15:16*i] = db_gpio_ddr[i]; + assign db_gpio_in[i] = db_gpio_in_flat[16*i+15:16*i]; + assign db_gpio_fab[i] = db_gpio_fab_flat[16*i+15:16*i]; + end + endgenerate + + generate if (NUM_CHANNELS_PER_RADIO == 1) + begin + for (i = 0; i < NUM_DBOARDS; i = i + 1) begin + // SPI + assign miso[i] = miso_flat[i]; + assign sclk_flat[i] = sclk[i]; + assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[i]; + assign mosi_flat[i] = mosi[i]; + end + end else if (NUM_CHANNELS_PER_RADIO == 2) + begin + for (i = 0; i < NUM_DBOARDS; i = i + 1) begin + // SPI + assign miso[2*i] = miso_flat[i]; + assign sclk_flat[i] = sclk[2*i]; + assign sen_flat[NUM_SPI_PER_DBOARD*i +: NUM_SPI_PER_DBOARD] = sen[2*i]; + assign mosi_flat[i] = mosi[2*i]; + end + end + endgenerate + + generate + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin + n3xx_db_fe_core #( + .USE_CORRECTION(USE_CORRECTION), + .NUM_SPI_SEN(NUM_SPI_PER_DBOARD), + .WIDTH(CHANNEL_WIDTH) + ) db_fe_core_i ( + .clk(radio_clk), + .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), + .set_addr(db_fe_set_addr[i]), + .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), + .rb_addr(db_fe_rb_addr[i]), + .rb_data(db_fe_rb_data[i]), + .tx_stb(tx_stb[i]), + .tx_data_in(tx_data[i]), + .tx_data_out(tx_int[i]), + .tx_running(tx_running[i]), + .rx_stb(rx_stb[i]), + .rx_data_in(rx_int[i]), + .rx_data_out(rx_data[i]), + .rx_running(rx_running[i]), + .misc_ins(32'h0), + .misc_outs(), + .fp_gpio_in(radio_gpio_in[i]), + .fp_gpio_out(radio_gpio_out[i]), + .fp_gpio_ddr(radio_gpio_ddr[i]), + .fp_gpio_fab(32'h0), + .db_gpio_in(db_gpio_in[i]), + .db_gpio_out(db_gpio_out[i]), + .db_gpio_ddr(db_gpio_ddr[i]), + .db_gpio_fab(db_gpio_fab[i]), + .leds(), + .spi_clk(radio_clk), + .spi_rst(radio_rst), + .sen(sen[i]), + .sclk(sclk[i]), + .mosi(mosi[i]), + .miso(miso[i]) + ); + end + endgenerate + + // Front panel GPIOs logic + // Double-sync for the GPIO inputs to the PS and to the Radio blocks. + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) ps_gpio_in_sync_i ( + .clk(bus_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(ps_gpio_in) + ); + synchronizer #( + .INITIAL_VAL(1'b0), .WIDTH(FP_GPIO_WIDTH) + ) radio_gpio_in_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(fp_gpio_in_int), .out(radio_gpio_sync) + ); + + generate + for (i=0; i PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .tx_out_clk(gt_tx_out_clk_unbuf) + ); + end else begin + ten_gige_phy ten_gige_phy_i ( + // Clocks and Reset + .areset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .refclk(gt_refclk), // Transciever reference clock: 156.25MHz + .clk156(gb_refclk), // Globally buffered core clock: 156.25MHz + .dclk(misc_clk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(1'b0), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_m2s), // Management Data In + .mdio_out(mdio_s2m), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(MDIO_PHYADDR), // MDIO address + // General IO's + .core_status(phy_status[7:0]), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable) + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + xge_mac_wrapper #( + .PORTNUM(PORTNUM), + .WISHBONE(0) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(gb_refclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(bus_clk), + .sys_rst(bus_rst), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // Other + .phy_ready(xge_phy_resetdone), + .ctrl_tx_enable(mac_ctrl_reg[0]), + .status_crc_error(mac_status[0]), + .status_fragment_error(mac_status[1]), + .status_txdfifo_ovflow(mac_status[2]), + .status_txdfifo_udflow(mac_status[3]), + .status_rxdfifo_ovflow(mac_status[4]), + .status_rxdfifo_udflow(mac_status[5]), + .status_pause_frame_rx(mac_status[6]), + .status_local_fault(mac_status[7]), + .status_remote_fault(mac_status[8]), + .wb_ack_o(), + .wb_dat_o(), + .wb_adr_i(1'b0), + .wb_clk_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_i(1'b0), + .wb_rst_i(1'b0), + .wb_stb_i(1'b0), + .wb_we_i (1'b0), + .wb_int_o() + ); + + assign phy_status[31:8] = 24'h0; + assign mac_status[31:9] = 23'h0; + assign link_up = phy_status_bclk[0]; + + end else if (PROTOCOL == "1GbE") begin + + //----------------------------------------------------------------- + // 1 Gigabit Ethernet + //----------------------------------------------------------------- + wire [7:0] gmii_txd, gmii_rxd; + wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; + wire gmii_clk; + wire gt0_qplloutclk, gt0_qplloutrefclk; //unused in 7-series Zynq + + assign gt0_qplloutclk = 1'b0; + assign gt0_qplloutrefclk = 1'b0; + assign sfpp_tx_disable = 1'b0; // Always on. + + if (GT_COMMON == 1) begin + one_gige_phy one_gige_phy_i ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + .pma_reset_out(/*unused*/), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + end else begin + one_gige_phy one_gige_phy_i ( + .reset(areset | phy_ctrl_reg[0]), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .phyaddr(MDIO_PHYADDR), // MDIO address + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status[15:0]), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i + ( + .clk125(gmii_clk), + .reset(areset), + + .GMII_GTX_CLK(), + .GMII_TX_EN(gmii_tx_en), + .GMII_TX_ER(gmii_tx_er), + .GMII_TXD(gmii_txd), + .GMII_RX_CLK(gmii_clk), + .GMII_RX_DV(gmii_rx_dv), + .GMII_RX_ER(gmii_rx_er), + .GMII_RXD(gmii_rxd), + + .sys_clk(bus_clk), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + + .wb_clk_i(1'b0), + .wb_rst_i(1'b0), + .wb_adr_i(8'h0), + .wb_dat_i(32'h0), + .wb_we_i(1'b0), + .wb_stb_i(1'b0), + .wb_cyc_i(1'b0), + .wb_dat_o(), + .wb_ack_o(), + .wb_int_o(), + .mdc(), + .mdio_out(1'b0), + .mdio_tri(), + .mdio_in(), + .debug_tx(), + .debug_rx() + ); + + assign phy_status[31:16] = 16'h0; + assign mac_status[31:0] = 32'h0; + assign link_up = phy_status_bclk[0]; + + assign gt_tx_out_clk_unbuf = 1'b0; + + end else if (PROTOCOL == "Aurora") begin + + //----------------------------------------------------------------- + // Aurora + //----------------------------------------------------------------- + wire user_rst; + wire [63:0] m2p_tdata, p2m_tdata; + wire m2p_tvalid, m2p_tready, p2m_tvalid; + wire channel_up, hard_err, soft_err, mac_crit_err; + + wire bist_checker_en = mac_ctrl_reg[0]; + wire bist_gen_en = mac_ctrl_reg[1]; + wire bist_loopback_en = mac_ctrl_reg[2]; + wire [5:0] bist_gen_rate = mac_ctrl_reg[8:3]; + wire phy_areset = mac_ctrl_reg[9]; + wire mac_clear = mac_ctrl_reg[10]; + wire bist_checker_locked; + + assign sfpp_tx_disable = 1'b0; // Always on. + + if (GT_COMMON == 1) begin + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + .sync_clk(sync_clk), + .qpllclk(qplloutclk), + .qpllrefclk(qplloutrefclk), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + .qplllock(qplllock), + .qpllreset(qpllreset), + .qpllrefclklost(qpllrefclklost), + .tx_out_clk(gt_tx_out_clk_unbuf), + .gt_pll_lock(gt_pll_lock), + .mmcm_locked(mmcm_locked) + ); + end else begin + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(user_clk), + .user_rst(user_rst), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(m2p_tdata), + .s_axis_tvalid(m2p_tvalid), + .s_axis_tready(m2p_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(p2m_tdata), + .m_axis_tvalid(p2m_tvalid), + // AXI4-Lite Config Interface (unused) + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err) + ); + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + + aurora_axis_mac #( + .PHY_ENDIANNESS ("LITTLE"), + .PACKET_MODE (1), + .MAX_PACKET_SIZE(1024), + .BIST_ENABLED (1) + ) aurora_mac_i ( + // Clocks and resets + .phy_clk(user_clk), .phy_rst(user_rst), + .sys_clk(bus_clk), .sys_rst(bus_rst), + .clear(mac_clear), + // PHY Interface (Synchronous to phy_clk) + .phy_s_axis_tdata(p2m_tdata), + .phy_s_axis_tvalid(p2m_tvalid), + .phy_m_axis_tdata(m2p_tdata), + .phy_m_axis_tvalid(m2p_tvalid), + .phy_m_axis_tready(m2p_tready), + // User Interface (Synchronous to sys_clk) + .s_axis_tdata(c2mac_tdata), + .s_axis_tlast(c2mac_tlast), + .s_axis_tvalid(c2mac_tvalid), + .s_axis_tready(c2mac_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tlast(m_axis_tlast), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + // PHY Status Inputs (Synchronous to phy_clk) + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + // Status and Error Outputs (Synchronous to sys_clk) + .overruns(overruns), + .soft_errors(), + .checksum_errors(checksum_errors), + .critical_err(mac_crit_err), + // BIST Interface (Synchronous to sys_clk) + .bist_gen_en(bist_gen_en), + .bist_gen_rate(bist_gen_rate), + .bist_checker_en(bist_checker_en), + .bist_loopback_en(bist_loopback_en), + .bist_checker_locked(bist_checker_locked), + .bist_checker_samps(bist_checker_samps), + .bist_checker_errors(bist_checker_errors) + ); + + assign m_axis_tuser = 4'd0; + + wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk, gt_pll_lock_bclk; + synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk)); + + if (GT_COMMON == 1) begin + synchronizer #(.INITIAL_VAL(1'b0)) gt_pll_lock_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(gt_pll_lock), .out(gt_pll_lock_bclk)); + end else begin + assign gt_pll_lock_bclk = 1'b0; + end + + reg [19:0] bist_lock_latency; + always @(posedge bus_clk) begin + if (!bist_checker_en && !bist_checker_locked) + bist_lock_latency <= 20'd0; + else if (bist_checker_en && !bist_checker_locked) + bist_lock_latency <= bist_lock_latency + 20'd1; + end + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + assign phy_status = {30'd0, hard_err, channel_up}; + assign mac_status = { + 6'h0, //[31:26] + mac_crit_err_latch, //[25] + 1'b1, //[24] + gt_pll_lock_bclk, //[23] + qpllrefclklost, //[22] + qplllock, //[21] + qpllreset, //[20] + bist_lock_latency[19:4], //[19:4] + bist_checker_locked, //[3] + soft_err_bclk, //[2] + hard_err_bclk, //[1] + channel_up_bclk //[0] + }; + + assign link_up = channel_up_bclk; + + end else begin + + //----------------------------------------------------------------- + // Disabled + //----------------------------------------------------------------- + + assign phy_status = 'h0; + assign mac_status = 'h0; + assign link_up = 1'b0; + + assign sfpp_tx_disable = 1'b0; // Always on. + + assign c2mac_tready = 1'b1; + assign m_axis_tdata = 64'h0; + assign m_axis_tuser = 4'h0; + assign m_axis_tlast = 1'b0; + assign m_axis_tvalid = 1'b0; + + assign qpllreset = 1'b0; + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + + end + endgenerate + + wire identify_enable = mac_led_ctl[0]; + wire identify_value = mac_led_ctl[1]; + + //----------------------------------------------------------------- + // Activity detector + //----------------------------------------------------------------- + + wire activity_int; + + pulse_stretch act_pulse_str_i ( + .clk(bus_clk), + .rst(bus_rst | ~link_up), + .pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)), + .pulse_stretched(activity_int) + ); + + always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int; + +endmodule diff --git a/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v b/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v new file mode 100644 index 000000000..fa1d5fe5d --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_mgt_wrapper.v @@ -0,0 +1,440 @@ +/////////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: n3xx_mgt_wrapper +// Description: +// Provides wrapper for just the pieces specific to an MGT lane +// (for easy use with generate) +// +////////////////////////////////////////////////////////////////////// + +`default_nettype none +module n3xx_mgt_wrapper #( + parameter PROTOCOL = "10GbE", // Must be {10GbE, Aurora, Disabled} + parameter REG_DWIDTH = 32, + parameter REG_AWIDTH = 14, + parameter GT_COMMON = 1, + parameter [7:0] PORTNUM = 8'd0, + parameter MDIO_EN = 0, + parameter [4:0] MDIO_PHYADDR = 5'd0, + parameter REG_BASE = 16'h0000 +)( + // Resets + input wire areset, + input wire bus_rst, + + // Clocks + input wire gt_refclk, + input wire gb_refclk, + input wire misc_clk, + input wire bus_clk, + input wire user_clk, + input wire sync_clk, + + // RegPort interface + input wire reg_wr_req, + input wire [REG_AWIDTH-1:0] reg_wr_addr, + input wire [REG_DWIDTH-1:0] reg_wr_data, + input wire reg_rd_req, + input wire [REG_AWIDTH-1:0] reg_rd_addr, + output wire reg_rd_resp, + output wire [REG_DWIDTH-1:0] reg_rd_data, + + // High-speed IO + output wire txp, + output wire txn, + input wire rxp, + input wire rxn, + + // SFP low-speed IO + input wire mod_present_n, + input wire mod_rxlos, + input wire mod_tx_fault, + output wire mod_tx_disable, + + // GT Common + input wire qpllrefclklost, + input wire qplllock, + input wire qplloutclk, + input wire qplloutrefclk, + output wire qpllreset, + + // Aurora MMCM + input wire mmcm_locked, + output wire gt_pll_lock, + output wire gt_tx_out_clk_unbuf, + + // Vita router interface + output wire [63:0] e2v_tdata, + output wire e2v_tlast, + output wire e2v_tvalid, + input wire e2v_tready, + + input wire [63:0] v2e_tdata, + input wire v2e_tlast, + input wire v2e_tvalid, + output wire v2e_tready, + + // CPU + output wire [63:0] e2c_tdata, + output wire [7:0] e2c_tkeep, + output wire e2c_tlast, + output wire e2c_tvalid, + input wire e2c_tready, + + input wire [63:0] c2e_tdata, + input wire [7:0] c2e_tkeep, + input wire c2e_tlast, + input wire c2e_tvalid, + output wire c2e_tready, + + // MISC + output wire [31:0] port_info, + input wire [15:0] device_id, + + // Timebase Outputs + output wire mod_pps, + output wire mod_refclk, + + // Sideband White Rabbit Control + input wire wr_reset_n, + input wire wr_refclk, + + output wire wr_dac_sclk, + output wire wr_dac_din, + output wire wr_dac_clr_n, + output wire wr_dac_cs_n, + output wire wr_dac_ldac_n, + + output wire wr_eeprom_scl_o, + input wire wr_eeprom_scl_i, + output wire wr_eeprom_sda_o, + input wire wr_eeprom_sda_i, + + input wire wr_uart_rx, + output wire wr_uart_tx, + + // WR AXI Control + output wire wr_axi_aclk, + input wire wr_axi_aresetn, + input wire [31:0] wr_axi_awaddr, + input wire wr_axi_awvalid, + output wire wr_axi_awready, + input wire [REG_DWIDTH-1:0] wr_axi_wdata, + input wire [REG_DWIDTH/8-1:0] wr_axi_wstrb, + input wire wr_axi_wvalid, + output wire wr_axi_wready, + output wire [1:0] wr_axi_bresp, + output wire wr_axi_bvalid, + input wire wr_axi_bready, + input wire [31:0] wr_axi_araddr, + input wire wr_axi_arvalid, + output wire wr_axi_arready, + output wire [REG_DWIDTH-1:0] wr_axi_rdata, + output wire [1:0] wr_axi_rresp, + output wire wr_axi_rvalid, + input wire wr_axi_rready, + output wire wr_axi_rlast, + + output wire link_up, + output wire activity + +); + + localparam [REG_AWIDTH-1:0] REG_BASE_MGT_IO = {REG_AWIDTH{1'b0}} + REG_BASE; + localparam [REG_AWIDTH-1:0] REG_BASE_ETH_SWITCH = {REG_AWIDTH{1'b0}} + 16'h1000 + REG_BASE; + + // AXI4-Lite to RegPort (PS to PL Register Access) + wire reg_rd_resp_io, reg_rd_resp_eth_if; + wire [REG_DWIDTH-1:0] reg_rd_data_io, reg_rd_data_eth_if; + + // Regport Mux for response + regport_resp_mux #( + .WIDTH (REG_DWIDTH), + .NUM_SLAVES (2) + ) reg_resp_mux_i ( + .clk(bus_clk), .reset(bus_rst), + .sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}), + .sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}), + .mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data) + ); + + wire [63:0] mgto_tdata, mgti_tdata; + wire [3:0] mgto_tuser, mgti_tuser; + wire mgto_tlast, mgti_tlast, mgto_tvalid, mgti_tvalid, mgto_tready, mgti_tready; + + generate + if (PROTOCOL != "WhiteRabbit") begin + n3xx_mgt_io_core #( + .PROTOCOL (PROTOCOL), + .REG_BASE (REG_BASE_MGT_IO), + .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) + .REG_AWIDTH (REG_AWIDTH), // Width of the address bus + .GT_COMMON (GT_COMMON), + .MDIO_EN (MDIO_EN), + .MDIO_PHYADDR (MDIO_PHYADDR), + .PORTNUM (PORTNUM) + ) mgt_io_i ( + //must reset all channels on quad when other gtx core is reset + .areset (areset), + .gt_refclk (gt_refclk), + .gb_refclk (gb_refclk), + .misc_clk (misc_clk), + .user_clk (user_clk), + .sync_clk (sync_clk), + .gt_tx_out_clk_unbuf(gt_tx_out_clk_unbuf), + + .bus_rst (bus_rst), + .bus_clk (bus_clk), + .qpllreset (qpllreset), + .qplllock (qplllock), + .qplloutclk (qplloutclk), + .qplloutrefclk (qplloutrefclk), + .qpllrefclklost (qpllrefclklost), + .mmcm_locked (mmcm_locked), + .gt_pll_lock (gt_pll_lock), + + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .sfpp_rxlos (mod_rxlos), + .sfpp_tx_fault (mod_tx_fault), + .sfpp_tx_disable(mod_tx_disable), + + //RegPort + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_io), + .reg_rd_data (reg_rd_data_io), + + // Vita to Ethernet + .s_axis_tdata (mgti_tdata), + .s_axis_tuser (mgti_tuser), + .s_axis_tlast (mgti_tlast), + .s_axis_tvalid (mgti_tvalid), + .s_axis_tready (mgti_tready), + + // Ethernet to Vita + .m_axis_tdata (mgto_tdata), + .m_axis_tuser (mgto_tuser), + .m_axis_tlast (mgto_tlast), + .m_axis_tvalid (mgto_tvalid), + .m_axis_tready (mgto_tready), + + .port_info (port_info), + .link_up (link_up), + .activity (activity) + ); + + end else begin + //--------------------------------------------------------------------------------- + // White Rabbit + //--------------------------------------------------------------------------------- + + wire wr_sfp_scl, wr_sfp_sda_o, wr_sfp_sda_i; + + n3xx_wr_top #( + .g_simulation(1'b0), // in std_logic + .g_dpram_size(131072/4), + .g_dpram_initf("../../../../bin/wrpc/wrc_phy16.bram") + ) wr_inst ( + .areset_n_i (wr_reset_n), // in std_logic; -- active low reset, optional + .wr_refclk_buf_i (wr_refclk), // in std_logic; -- 20MHz VCXO after IBUFGDS + .gige_refclk_buf_i (gt_refclk), // in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + .dac_sclk_o (wr_dac_sclk), // out std_logic; -- N3xx cWB-DAC-SCLK + .dac_din_o (wr_dac_din), // out std_logic; -- N3xx cWB-DAC-DIN + .dac_clr_n_o (wr_dac_clr_n), // out std_logic; -- N3xx cWB-DAC-nCLR + .dac_cs_n_o (wr_dac_cs_n), // out std_logic; -- N3xx cWB-DAC-nSYNC + .dac_ldac_n_o (wr_dac_ldac_n), // out std_logic; -- N3xx cWB-DAC-nLDAC + .LED_ACT (activity), // out std_logic; -- connect to SFP+ ACT + .LED_LINK (link_up), // out std_logic; -- connect to SFP+ LINK + .sfp_txp_o (txp), // out std_logic; + .sfp_txn_o (txn), // out std_logic; + .sfp_rxp_i (rxp), // in std_logic; + .sfp_rxn_i (rxn), // in std_logic; + .sfp_mod_def0_b (mod_present_n), // in std_logic; - sfp detect + .eeprom_scl_o (wr_eeprom_scl_o), + .eeprom_scl_i (wr_eeprom_scl_i), + .eeprom_sda_o (wr_eeprom_sda_o), + .eeprom_sda_i (wr_eeprom_sda_i), + .sfp_scl_o (wr_sfp_scl), + .sfp_scl_i (wr_sfp_scl), + .sfp_sda_o (wr_sfp_sda_o), + .sfp_sda_i (wr_sfp_sda_i), + .sfp_tx_fault_i (mod_tx_fault), // in std_logic; + .sfp_tx_disable_o (mod_tx_disable), // out std_logic; + .sfp_los_i (mod_rxlos), // in std_logic; + .wr_uart_rxd (wr_uart_rx), // in std_logic; + .wr_uart_txd (wr_uart_tx), // out std_logic; + + .s00_axi_aclk_o (wr_axi_aclk), + .s00_axi_aresetn (wr_axi_aresetn), + .s00_axi_awaddr (wr_axi_awaddr), + .s00_axi_awprot (3'b0), + .s00_axi_awvalid (wr_axi_awvalid), + .s00_axi_awready (wr_axi_awready), + .s00_axi_wdata (wr_axi_wdata), + .s00_axi_wstrb (wr_axi_wstrb), + .s00_axi_wvalid (wr_axi_wvalid), + .s00_axi_wready (wr_axi_wready), + .s00_axi_bresp (wr_axi_bresp), + .s00_axi_bvalid (wr_axi_bvalid), + .s00_axi_bready (wr_axi_bready), + .s00_axi_araddr (wr_axi_araddr), + .s00_axi_arprot (3'b0), + .s00_axi_arvalid (wr_axi_arvalid), + .s00_axi_arready (wr_axi_arready), + .s00_axi_rdata (wr_axi_rdata), + .s00_axi_rresp (wr_axi_rresp), + .s00_axi_rvalid (wr_axi_rvalid), + .s00_axi_rready (wr_axi_rready), + .s00_axi_rlast (wr_axi_rlast), + .axi_int_o (), + + .pps_o (mod_pps), // out std_logic; + .clk_pps_o (mod_refclk), // out std_logic; + .link_ok_o (), // out std_logic; + .clk_sys_locked_o (), // out std_logic; + .clk_dmtd_locked_o (), // out std_logic); + .wr_debug0_o (), + .wr_debug1_o () + ); + + // TEMPORARY mimic the AXGE SFP EEROM + sfp_eeprom sfp_eeprom_i ( + .clk_i(bus_clk), + .sfp_scl(wr_sfp_scl), + .sfp_sda_i(wr_sfp_sda_o), + .sfp_sda_o(wr_sfp_sda_i)); + + // Assign the port_info vector similarly to mgt_io_core + localparam [7:0] COMPAT_NUM = 8'd2; + localparam [7:0] MGT_PROTOCOL = 8'd4; + assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM}; + + // Tie off unused outputs. + assign gt_pll_lock = 1'b0; + assign gt_tx_out_clk_unbuf = 1'b0; + end + endgenerate + + generate + // Tie off the Ethernet switch for these protocols that do not use it. + if(PROTOCOL == "Aurora" || PROTOCOL == "Disabled" || PROTOCOL == "WhiteRabbit") begin + + //set unused wires to default value + assign e2c_tdata = 64'h0; + assign e2c_tkeep = 8'h0; + assign e2c_tlast = 1'b0; + assign e2c_tvalid = 1'b0; + assign c2e_tready = 1'b1; + + assign reg_rd_resp_eth_if = 1'b0; + assign reg_rd_data_eth_if = 'h0; + + assign e2v_tdata = mgto_tdata; + assign e2v_tlast = mgto_tlast; + assign e2v_tvalid = mgto_tvalid; + assign mgto_tready = e2v_tready; + + assign mgti_tdata = v2e_tdata; + assign mgti_tlast = v2e_tlast; + assign mgti_tvalid = v2e_tvalid; + assign v2e_tready = mgti_tready; + + end else begin + + wire [3:0] e2c_tuser; + wire [3:0] c2e_tuser; + + // In AXI Stream, tkeep is the byte qualifier that indicates + // whether the content of the associated byte + // of TDATA is processed as part of the data stream. + // tuser as used in eth_switch is the numbier of valid bytes + + // Converting tuser to tkeep for ingress packets + assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111 + : (e2c_tuser == 4'd0) ? 8'b1111_1111 + : (e2c_tuser == 4'd1) ? 8'b0000_0001 + : (e2c_tuser == 4'd2) ? 8'b0000_0011 + : (e2c_tuser == 4'd3) ? 8'b0000_0111 + : (e2c_tuser == 4'd4) ? 8'b0000_1111 + : (e2c_tuser == 4'd5) ? 8'b0001_1111 + : (e2c_tuser == 4'd6) ? 8'b0011_1111 + : 8'b0111_1111; + + // Converting tkeep to tuser for egress packets + assign c2e_tuser = ~c2e_tlast ? 4'd0 + : (c2e_tkeep == 8'b1111_1111) ? 4'd0 + : (c2e_tkeep == 8'b0111_1111) ? 4'd7 + : (c2e_tkeep == 8'b0011_1111) ? 4'd6 + : (c2e_tkeep == 8'b0001_1111) ? 4'd5 + : (c2e_tkeep == 8'b0000_1111) ? 4'd4 + : (c2e_tkeep == 8'b0000_0111) ? 4'd3 + : (c2e_tkeep == 8'b0000_0011) ? 4'd2 + : (c2e_tkeep == 8'b0000_0001) ? 4'd1 + : 4'd0; + + eth_interface #( + .PROTOVER ({8'd1,8'd0}), //FIXME. This should come from outside + .MTU (10), + .NODE_INST (0), + .REG_AWIDTH (REG_AWIDTH), + .BASE (REG_BASE_ETH_SWITCH) + ) eth_interface ( + .clk (bus_clk), + .reset (bus_rst), + .device_id (device_id), + .reg_wr_req (reg_wr_req), + .reg_wr_addr (reg_wr_addr), + .reg_wr_data (reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr (reg_rd_addr), + .reg_rd_resp (reg_rd_resp_eth_if), + .reg_rd_data (reg_rd_data_eth_if), + .my_mac (), + .my_ip (), + .my_udp_port (), + .eth_tx_tdata (mgti_tdata), + .eth_tx_tuser (mgti_tuser), + .eth_tx_tlast (mgti_tlast), + .eth_tx_tvalid (mgti_tvalid), + .eth_tx_tready (mgti_tready), + .eth_rx_tdata (mgto_tdata), + .eth_rx_tuser (mgto_tuser), + .eth_rx_tlast (mgto_tlast), + .eth_rx_tvalid (mgto_tvalid), + .eth_rx_tready (mgto_tready), + .e2v_tdata (e2v_tdata), + .e2v_tlast (e2v_tlast), + .e2v_tvalid (e2v_tvalid), + .e2v_tready (e2v_tready), + .v2e_tdata (v2e_tdata), + .v2e_tlast (v2e_tlast), + .v2e_tvalid (v2e_tvalid), + .v2e_tready (v2e_tready), + .e2c_tdata (e2c_tdata), + .e2c_tuser (e2c_tuser), + .e2c_tlast (e2c_tlast), + .e2c_tvalid (e2c_tvalid), + .e2c_tready (e2c_tready), + .c2e_tdata (c2e_tdata), + .c2e_tuser (c2e_tuser), + .c2e_tlast (c2e_tlast), + .c2e_tvalid (c2e_tvalid), + .c2e_tready (c2e_tready) + ); + + end + endgenerate + +endmodule // n3xx_mgt_wrapper +`default_nettype wire diff --git a/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd b/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd new file mode 100644 index 000000000..148a66185 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_serial_dac.vhd @@ -0,0 +1,218 @@ +------------------------------------------------------------------------------- +-- Title : N3xx Serial DAC interface +-- Project : White Rabbit Switch +------------------------------------------------------------------------------- +-- File : n3xx_serial_dac.vhd +-- Author : paas, slayer, dbaker +-- Company : CERN BE-Co-HT +-- Created : 2010-02-25 +-- Last update: 2011-05-10 +-- Platform : fpga-generic +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- Description: The dac unit provides an interface to a 16 bit serial Digital to +-- Analogue converter (AD5663, SPI?/QSPI?/MICROWIRE? compatible) +-- +------------------------------------------------------------------------------- +-- Copyright (c) 2010 CERN +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- either version 2.1 of the License, or (at your option) any +-- later version. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl-2.1.html +------------------------------------------------------------------------------- +-- Revisions :1 +-- Date Version Author Description +-- 2009-01-24 1.0 paas Created +-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch +-- 2018-02-01 2.0 dbaker Modified for n3xx +------------------------------------------------------------------------------- + + +library IEEE; + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +entity n3xx_serial_dac is + + generic ( + g_num_data_bits : integer := 16; + g_num_extra_bits : integer := 8; + g_num_cs_select : integer := 2 + ); + + port ( +-- clock & reset + clk_i : in std_logic; + rst_n_i : in std_logic; + +-- channel 1 value and value load strobe + value_i : in std_logic_vector(g_num_data_bits-1 downto 0); + cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0); + load_i : in std_logic; + +-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024 + sclk_divsel_i : in std_logic_vector(2 downto 0); + +-- DAC I/F + dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); + dac_sclk_o : out std_logic; + dac_sdata_o : out std_logic; + + xdone_o : out std_logic + ); +end n3xx_serial_dac; + + +architecture syn of n3xx_serial_dac is + + signal divider : unsigned(11 downto 0); + signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0); + signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0); + signal endSendingData : std_logic; + signal sendingData : std_logic; + signal iDacClk : std_logic; + signal iValidValue : std_logic; + + signal divider_muxed : std_logic; + + signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0); + + constant k_cmd_hi : integer := 21; + constant k_cmd_lo : integer := 19; + constant k_addr_hi : integer := 18; + constant k_addr_lo : integer := 16; +begin + + select_divider : process (divider, sclk_divsel_i) + begin -- process + case sclk_divsel_i is + when "000" => divider_muxed <= divider(1); -- sclk = clk_i/8 + when "001" => divider_muxed <= divider(2); -- sclk = clk_i/16 + when "010" => divider_muxed <= divider(3); -- sclk = clk_i/32 + when "011" => divider_muxed <= divider(4); -- sclk = clk_i/64 + when "100" => divider_muxed <= divider(5); -- sclk = clk_i/128 + when "101" => divider_muxed <= divider(6); -- sclk = clk_i/256 + when "110" => divider_muxed <= divider(7); -- sclk = clk_i/512 + when "111" => divider_muxed <= divider(8); -- sclk = clk_i/1024 + when others => null; + end case; + end process; + + + iValidValue <= load_i; + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + sendingData <= '0'; + else + if iValidValue = '1' and sendingData = '0' then + sendingData <= '1'; + elsif endSendingData = '1' then + sendingData <= '0'; + end if; + end if; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if iValidValue = '1' then + divider <= (others => '0'); + elsif sendingData = '1' then + if(divider_muxed = '1') then + divider <= (others => '0'); + else + divider <= divider + 1; + end if; + elsif endSendingData = '1' then + divider <= (others => '0'); + end if; + end if; + end process; + + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + iDacClk <= '1'; -- 0 + else + if iValidValue = '1' then + iDacClk <= '1'; -- 0 + elsif divider_muxed = '1' then + iDacClk <= not(iDacClk); + elsif endSendingData = '1' then + iDacClk <= '1'; -- 0 + end if; + end if; + end if; + end process; + + process(clk_i, rst_n_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + dataSh <= (others => '0'); + else + if iValidValue = '1' and sendingData = '0' then + cs_sel_reg <= cs_sel_i; + dataSh <= (others => '0'); + if cs_sel_i(0) = '1' then + dataSh(k_addr_hi downto k_addr_lo) <= "000"; + elsif cs_sel_i(1) = '1' then + dataSh(k_addr_hi downto k_addr_lo) <= "001"; + end if; + dataSh(k_cmd_hi downto k_cmd_lo) <= "011"; + dataSh(g_num_data_bits-1 downto 0) <= value_i; + elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then + dataSh(0) <= dataSh(dataSh'left); + dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0); + end if; + end if; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if iValidValue = '1' and sendingData = '0' then + bitCounter(0) <= '1'; + bitCounter(bitCounter'left downto 1) <= (others => '0'); + elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then + bitCounter(0) <= '0'; + bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0); + end if; + end if; + end process; + + endSendingData <= bitCounter(bitCounter'left); + + xdone_o <= not SendingData; + + dac_sdata_o <= dataSh(dataSh'left); + + gen_cs_out : for i in 0 to g_num_cs_select-1 generate + dac_cs_n_o(i) <= not(sendingData); + end generate gen_cs_out; + + dac_sclk_o <= iDacClk; + + +end syn; diff --git a/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd new file mode 100644 index 000000000..9049bd845 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_serial_dac_arb.vhd @@ -0,0 +1,187 @@ +------------------------------------------------------------------------------- +-- Title : N3xx serial DAC interface with arbiter +-- Project : White Rabbit +------------------------------------------------------------------------------- +-- File : spec_serial_dac.vhd +-- Author : Tomasz Wlostowski, modifications by dbaker +-- Company : CERN BE-Co-HT +-- Platform : fpga-generic +-- Standard : VHDL'87 +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2011 CERN +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- either version 2.1 of the License, or (at your option) any +-- later version. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl-2.1.html +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity n3xx_serial_dac_arb is + generic( + g_invert_sclk : boolean; + g_num_extra_bits : integer + ); + port( + clk_i : in std_logic; + rst_n_i : in std_logic; + + val1_i : in std_logic_vector(15 downto 0); + load1_i : in std_logic; + val2_i : in std_logic_vector(15 downto 0); + load2_i : in std_logic; + + dac_cs_n_o : out std_logic_vector(1 downto 0); + dac_clr_n_o : out std_logic; + dac_sclk_o : out std_logic; + dac_din_o : out std_logic); + +end n3xx_serial_dac_arb; + +architecture behavioral of n3xx_serial_dac_arb is + + component n3xx_serial_dac + generic ( + g_num_data_bits : integer; + g_num_extra_bits : integer; + g_num_cs_select : integer); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + value_i : in std_logic_vector(g_num_data_bits-1 downto 0); + cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0); + load_i : in std_logic; + sclk_divsel_i : in std_logic_vector(2 downto 0); + dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0); + dac_sclk_o : out std_logic; + dac_sdata_o : out std_logic; + xdone_o : out std_logic); + end component; + + signal d1, d2 : std_logic_vector(15 downto 0) := (others=>'0'); + signal d1_ready, d2_ready : std_logic := '0'; + + + signal dac_data : std_logic_vector(15 downto 0) := (others=>'0'); + signal dac_load : std_logic := '0'; + signal dac_cs_sel : std_logic_vector(1 downto 0) := (others=>'0'); + signal dac_done : std_logic := '0'; + signal dac_sclk_int : std_logic := '0'; + + type t_state is (WAIT_DONE, LOAD_DAC, WAIT_DATA); + + signal state : t_state; + + signal trig0 : std_logic_vector(31 downto 0); + signal trig1 : std_logic_vector(31 downto 0); + signal trig2 : std_logic_vector(31 downto 0); + signal trig3 : std_logic_vector(31 downto 0); + signal CONTROL0 : std_logic_vector(35 downto 0); + +begin -- behavioral + + dac_clr_n_o <= '1'; + + U_DAC : n3xx_serial_dac + generic map ( + g_num_data_bits => 16, + g_num_extra_bits => g_num_extra_bits, + g_num_cs_select => 2) + port map ( + clk_i => clk_i, + rst_n_i => rst_n_i, + value_i => dac_data, + cs_sel_i => dac_cs_sel, + load_i => dac_load, + sclk_divsel_i => "001", + dac_cs_n_o => dac_cs_n_o, + dac_sclk_o => dac_sclk_int, + dac_sdata_o => dac_din_o, + xdone_o => dac_done); + + + p_drive_sclk: process(dac_sclk_int) + begin + if(g_invert_sclk) then + dac_sclk_o <= not dac_sclk_int; + else + dac_sclk_o <= dac_sclk_int; + end if; + end process; + + process(clk_i) + begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + d1 <= (others => '0'); + d1_ready <= '0'; + d2 <= (others => '0'); + d2_ready <= '0'; + dac_load <= '0'; + dac_cs_sel <= (others => '0'); + state <= WAIT_DATA; + else + + if(load1_i = '1' or load2_i = '1') then + + if(load1_i = '1') then + d1_ready <= '1'; + d1 <= val1_i; + end if; + + if(load2_i = '1') then + d2_ready <= '1'; + d2 <= val2_i; + end if; + else + case state is + when WAIT_DATA => + if(d1_ready = '1') then + dac_cs_sel <= "01"; + dac_data <= d1; + dac_load <= '1'; + d1_ready <= '0'; + state <= LOAD_DAC; + elsif(d2_ready = '1') then + dac_cs_sel <= "10"; + dac_data <= d2; + dac_load <= '1'; + d2_ready <= '0'; + state <= LOAD_DAC; + end if; + + when LOAD_DAC=> + dac_load <= '0'; + state <= WAIT_DONE; + + when WAIT_DONE => + if(dac_done = '1') then + state <= WAIT_DATA; + end if; + when others => null; + end case; + end if; + end if; + end if; + end process; + + + + +end behavioral; diff --git a/fpga/usrp3/top/n3xx/n3xx_wr.xdc b/fpga/usrp3/top/n3xx/n3xx_wr.xdc new file mode 100644 index 000000000..2b69c9ead --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_wr.xdc @@ -0,0 +1,78 @@ +# +# Copyright 2018 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +# 20 MHz White Rabbit reference +create_clock -name wr_refclk -period 50.000 [get_ports WB_20MHZ_P] + +# 62.5M TXOUTCLK from the MGT that does most of the heavy lifting +create_clock -name wr_txoutclk -period 16.000 \ + [get_pins -hierarchical -filter \ + {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK}] + +# 62.5M RXOUTCLK from the MGT that doesn't do as much as the TXOUTCLK +create_clock -name wr_rxoutclk -period 16.000 \ + [get_pins -hierarchical -filter \ + {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK}] + +# Rename the WR 62.5M system clock +create_generated_clock -name wr_sysclk \ + [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_sys_clk_pll/CLKOUT0}] + +# Rename the WR ~62.5M DMTD clock +create_generated_clock -name wr_dmtdclk \ + [get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0}] + + + +# Clock Interaction Matrix : ------------------------------------------------------------ +# Everything is basically async to everything else, except for the net_clk group. +# Blanks mean there are no paths there (in the WR v4.2 build). +# +# The wr_sysclk (62.5 MHz) is derived from the 125 MHz MGT Reference clock (NETCLK). +# On the other hand, the wr_dmtdclk, also a 62.5 MHz clock, is derived from the 20 MHz +# WR VCXO. This two clock groups could be considered asynchronous due to its different +# source and different MMCM primitive (which unrelates them even more). +# +# | wr_RXOUTCLK | wr_TXOUTCLK | wr_dmtdclk | wr_sysclk | net_clk +# wr_RXOUTCLK | timed | async | async | async | +# wr_TXOUTCLK | async | timed | async | async | +# wr_dmtdclk | | | timed | async | +# wr_sysclk | async | async | async | timed | timed +# net_clk | async | | | timed | timed + +set_clock_groups -asynchronous -group [get_clocks wr_rxoutclk] \ + -group [get_clocks wr_txoutclk] \ + -group [get_clocks wr_dmtdclk] \ + -group [get_clocks net_clk] + +set_clock_groups -asynchronous -group [get_clocks wr_sysclk] \ + -group [get_clocks wr_txoutclk] \ + -group [get_clocks wr_rxoutclk] \ + -group [get_clocks wr_dmtdclk] + +# Safe paths : -------------------------------------------------------------------------- +# There is a mix of safe and unknown clock interactions between wr_sysclk and wr_dmtdclk. +# The safe crossings refer to those using a synchronizer structure; and to avoid +# failing timing on those paths, we ignore them (i.e. false paths), and allow the tools +# to time the rest. +# +# The WR IP uses easily identifiable single-bit synchronizers to transfer strobes from +# the wr_dmtdclk to the wr_sysclk domain. +# +# Commenting out command since the asynchronous groups were updated and paths ignored. +# set_false_path -from [get_clocks wr_dmtdclk] \ +# -to [get_pins -hierarchical -filter {NAME =~ */sync_posedge.sync0_reg/D}] +# +# +# The tags generated by the DDMTD (wr_dmtdclk domain) are deglitched before being output +# to the upstream logic in the wr_sysclk domain. Thus, a safe multi-bit crossing is +# expected between these two domains, and we tell the tools to ignore those paths. +# See usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/dmtd_with_deglitcher.vhd for +# implementation details. +# +# Commenting out command since the asynchronous groups were updated and paths ignored. +# set_false_path -from [get_clocks wr_dmtdclk] \ +# -to [get_pins -hierarchical -filter {NAME =~ */U_Wrapped_Softpll/tags_masked_reg*/D}] diff --git a/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd b/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd new file mode 100644 index 000000000..277b6684f --- /dev/null +++ b/fpga/usrp3/top/n3xx/n3xx_wr_top.vhd @@ -0,0 +1,496 @@ +------------------------------------------------------------------------------- +-- +-- File: n3xx_wr_top.vhd +-- Author: +-- Original Project: N310 +-- Date: 22 February 2018 +-- +------------------------------------------------------------------------------- +-- Copyright 2018 Ettus Research, A National Instruments Company +-- SPDX-License-Identifier: LGPL-3.0 +------------------------------------------------------------------------------- +-- +-- Purpose: +-- +-- Wrapper file for the White Rabbit cores. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.gencores_pkg.all; +use work.wishbone_pkg.all; +use work.wr_fabric_pkg.all; +use work.wrcore_pkg.all; +use work.etherbone_pkg.all; +use work.endpoint_pkg.all; +use work.streamers_pkg.all; +use work.wr_xilinx_pkg.all; +use work.wr_board_pkg.all; +use work.axi4_pkg.all; + +library unisim; +use unisim.VCOMPONENTS.all; + + +entity n3xx_wr_top is + generic( + g_simulation : integer := 0; + g_dpram_size : integer := 131072/4; + g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram"); + port ( + --------------------------------------------------------------------------- + -- Resets + --------------------------------------------------------------------------- + -- Reset input (active low, can be async) + areset_n_i : in std_logic; + + --------------------------------------------------------------------------- + -- Oscillators and control DACs + --------------------------------------------------------------------------- + wr_refclk_buf_i : in std_logic; -- 20MHz VCXO after IBUFGDS + + gige_refclk_buf_i : in std_logic; -- 125 MHz MGT Ref after IBUFDS_GTE2 + + dac_sclk_o : out std_logic; -- N310 cWB-DAC-SCLK + dac_din_o : out std_logic; -- N310 cWB-DAC-DIN + dac_clr_n_o : out std_logic; -- N310 cWB-DAC-nCLR + dac_cs_n_o : out std_logic; -- N310 cWB-DAC-nSYNC + dac_ldac_n_o : out std_logic; -- N310 cWB-DAC-nLDAC + + eeprom_scl_o : out std_logic; + eeprom_scl_i : in std_logic; + eeprom_sda_o : out std_logic; + eeprom_sda_i : in std_logic; + + --------------------------------------------------------------------------- + -- SFP pins + --------------------------------------------------------------------------- + -- LEDs + LED_ACT : out std_logic; -- connect to SFP+ ACT + LED_LINK : out std_logic; -- connect to SFP+ LINK + + sfp_txp_o : out std_logic; + sfp_txn_o : out std_logic; + + sfp_rxp_i : in std_logic; + sfp_rxn_i : in std_logic; + + sfp_mod_def0_b : in std_logic; -- sfp detect + --sfp_mod_def1_b : inout std_logic; -- scl + --sfp_mod_def2_b : inout std_logic; -- sda + sfp_scl_o : out std_logic; + sfp_scl_i : in std_logic; + sfp_sda_o : out std_logic; + sfp_sda_i : in std_logic; + sfp_tx_fault_i : in std_logic; + sfp_tx_disable_o : out std_logic; + sfp_los_i : in std_logic; + + --------------------------------------------------------------------------- + -- Grandmaster mode inputs, optional + --------------------------------------------------------------------------- + + -- 10MHz clock generated by N310 when using WR in grandmaster mode + --clk_ext_gm_i : in std_logic := '0'; + -- PPS generated by N310 when using WR in grandmaster mode + --pps_ext_gm_i : in std_logic := '0'; + + --------------------------------------------------------------------------- + --UART + --------------------------------------------------------------------------- + wr_uart_rxd : in std_logic; + wr_uart_txd : out std_logic; + + + ------------------------------------------ + -- Axi Slave Bus Interface S00_AXI + ------------------------------------------ + -- aclk provided by this IP, wire to master! + s00_axi_aclk_o : out std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(31 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(31 downto 0); + s00_axi_wstrb : in std_logic_vector(3 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(31 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(31 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic; + s00_axi_rlast : out std_logic; + axi_int_o : out std_logic; -- axi interrupt signal + + + --------------------------------------------------------------------------- + -- PPS and main clock + --------------------------------------------------------------------------- + -- PPS output from WR Core, in 125M domain + pps_o : out std_logic; + clk_pps_o : out std_logic; + link_ok_o : out std_logic; + + --------------------------------------------------------------------------- + -- Debug + --------------------------------------------------------------------------- + clk_sys_locked_o : out std_logic; + clk_dmtd_locked_o : out std_logic; + wr_debug0_o : out std_logic; + wr_debug1_o : out std_logic); +end entity n3xx_wr_top; + +architecture structure of n3xx_wr_top is + + component n3xx_serial_dac_arb + generic( + g_invert_sclk : boolean; + g_num_extra_bits : integer); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + val1_i : in std_logic_vector(15 downto 0); + load1_i : in std_logic; + val2_i : in std_logic_vector(15 downto 0); + load2_i : in std_logic; + dac_cs_n_o : out std_logic_vector(1 downto 0); + dac_clr_n_o : out std_logic; + dac_sclk_o : out std_logic; + dac_din_o : out std_logic); + end component; + + ------------------------------------------------------------------------------ + -- Signals declaration + ------------------------------------------------------------------------------ + + -- PLLs, clocks + signal clk_pll_62m5 : std_logic; + signal clk_pll_125m : std_logic; + signal clk_ref_62m5 : std_logic; + signal clk_pll_dmtd : std_logic; + signal pll_locked : std_logic; + signal clk_10m_ext : std_logic; + + -- Reset logic + signal rst_pll_62m5_n : std_logic; + signal rstlogic_arst_n : std_logic; + signal rstlogic_clk_in : std_logic_vector(1 downto 0); + signal rstlogic_rst_out : std_logic_vector(1 downto 0); + + -- PLL DAC ARB + signal dac_hpll_load_p1 : std_logic; + signal dac_hpll_data : std_logic_vector(15 downto 0); + signal dac_dpll_load_p1 : std_logic; + signal dac_dpll_data : std_logic_vector(15 downto 0); + signal dac_cs_vec_n : std_logic_vector(1 downto 0); + + -- OneWire + signal onewire_in : std_logic_vector(1 downto 0); + signal onewire_en : std_logic_vector(1 downto 0); + + -- PHY + signal phy16_to_wrc : t_phy_16bits_to_wrc; + signal phy16_from_wrc : t_phy_16bits_from_wrc; + + -- External reference + signal ext_ref_mul : std_logic; + signal ext_ref_mul_locked : std_logic; + signal ext_ref_mul_stopped : std_logic; + signal ext_ref_rst : std_logic; + + -- SFP I2C + --signal sfp_scl_o : std_logic; + --signal sfp_scl_i : std_logic; + --signal sfp_sda_o : std_logic; + --signal sfp_sda_i : std_logic; + + -- WRC WB Slave interface + signal wb_slave_out : t_wishbone_slave_out; + signal wb_slave_in : t_wishbone_slave_in; + signal zero : std_logic; + + + signal ref_clk_fb_o, pps, ref_clk_fb_i, clk_ref_125m, clk_ref_125m_bufg : std_logic; + + +begin + + wr_debug0_o <= dac_dpll_load_p1; + wr_debug1_o <= dac_hpll_load_p1; + + ----------------------------------------------------------------------------- + -- Platform-dependent part (PHY, PLLs, buffers, etc) + ----------------------------------------------------------------------------- + + cmp_xwrc_platform : xwrc_platform_xilinx + generic map ( + g_fpga_family => "kintex7", + g_with_external_clock_input => false, + g_use_default_plls => TRUE, + g_simulation => 0, + g_use_ibufgds => false ) + port map ( + areset_n_i => areset_n_i, + clk_10m_ext_i => '0', + clk_20m_vcxo_i => wr_refclk_buf_i, + clk_125m_pllref_i => '0', -- only used for "spartan6" g_fpga_family + clk_125m_gtp_p_i => gige_refclk_buf_i, -- buffered on top level with IBUFDS_GTE2 + clk_125m_gtp_n_i => '0', + sfp_txn_o => sfp_txn_o, + sfp_txp_o => sfp_txp_o, + sfp_rxn_i => sfp_rxn_i, + sfp_rxp_i => sfp_rxp_i, + sfp_tx_fault_i => sfp_tx_fault_i, + sfp_los_i => sfp_los_i, + sfp_tx_disable_o => sfp_tx_disable_o, + clk_62m5_sys_o => clk_pll_62m5, -- gige_refclk_buf_i > BUFG > MMCM > BUFG 62.5M + clk_125m_ref_o => clk_ref_62m5, -- gige_refclk_buf_i > GTX > TXOUTCLK > BUFG 62.5M + clk_62m5_dmtd_o => clk_pll_dmtd, -- wr_refclk_buf_i > BUFG > MMCM > BUFG ~62.5M + pll_locked_o => pll_locked, + clk_10m_ext_o => clk_10m_ext, + phy16_o => phy16_to_wrc, + phy16_i => phy16_from_wrc, + ext_ref_mul_o => ext_ref_mul, + ext_ref_mul_locked_o => ext_ref_mul_locked, + ext_ref_mul_stopped_o => ext_ref_mul_stopped, + ext_ref_rst_i => ext_ref_rst); + + ----------------------------------------------------------------------------- + -- Reset logic + ----------------------------------------------------------------------------- + + -- logic AND of all async reset sources (active low) + rstlogic_arst_n <= pll_locked and areset_n_i; + + -- concatenation of all clocks required to have synced resets + rstlogic_clk_in(0) <= clk_pll_62m5; + rstlogic_clk_in(1) <= clk_ref_62m5; + + cmp_rstlogic_reset : gc_reset + generic map ( + g_clocks => 2, -- 62.5MHz, 125MHz + g_logdelay => 4, -- 16 clock cycles + g_syncdepth => 3) -- length of sync chains + port map ( + free_clk_i => gige_refclk_buf_i, + locked_i => rstlogic_arst_n, + clks_i => rstlogic_clk_in, + rstn_o => rstlogic_rst_out); + + -- distribution of resets (already synchronized to their clock domains) + rst_pll_62m5_n <= rstlogic_rst_out(0); + + -- rst_sys_62m5_n_o <= rst_pll_62m5_n; -- reset in 62.5 MHz domain, if needed + -- rst_ref_125m_n_o <= rstlogic_rst_out(1); -- reset in 125 MHz domain, if needed + + + ----------------------------------------------------------------------------- + -- 2x SPI DAC + ----------------------------------------------------------------------------- + + cmp_dac_arb : n3xx_serial_dac_arb + generic map ( + g_invert_sclk => FALSE, + g_num_extra_bits => 8) + port map ( + clk_i => clk_pll_62m5, + rst_n_i => rst_pll_62m5_n, + val1_i => dac_dpll_data, + load1_i => dac_dpll_load_p1, + val2_i => dac_hpll_data, + load2_i => dac_hpll_load_p1, + dac_cs_n_o => dac_cs_vec_n, + dac_clr_n_o => dac_clr_n_o, -- unused, always '1' + dac_sclk_o => dac_sclk_o, + dac_din_o => dac_din_o); + + -- only need one CS for the AD5663 DAC, channel is selected with data bits + dac_cs_n_o <= dac_cs_vec_n(0); + + -- nLDAC is unused. A command embedded in the DAC SPI transaction is used instead + -- to transfer the write from the input register to the DAC output. + dac_ldac_n_o <= '1'; + + + + ----------------------------------------------------------------------------- + -- The WR PTP core with optional fabric interface attached + ----------------------------------------------------------------------------- + + cmp_board_common : xwrc_board_common + generic map ( + g_simulation => 0, + g_with_external_clock_input => false, -- eventually true ! DJB ! + g_board_name => "NA ", + g_phys_uart => TRUE, + g_virtual_uart => false, + g_aux_clks => 0, + g_ep_rxbuf_size => 1024, + g_tx_runt_padding => TRUE, + g_dpram_initf => g_dpram_initf, + g_dpram_size => 131072/4, + g_interface_mode => PIPELINED, + g_address_granularity => BYTE, + g_aux_sdb => c_wrc_periph3_sdb, + g_softpll_enable_debugger => TRUE, -- was FALSE + g_vuart_fifo_size => 1024, + g_pcs_16bit => TRUE, + g_diag_id => 0, -- guessing about this + g_diag_ver => 185, -- setting the version reg to 0xB9 + g_diag_ro_size => 0, -- not sure if this is needed to enable diag regs + g_diag_rw_size => 16, -- not sure if this is needed to enable diag regs + g_streamers_op_mode => TX_AND_RX, + g_tx_streamer_params => c_tx_streamer_params_defaut, + g_rx_streamer_params => c_rx_streamer_params_defaut, + g_fabric_iface => plain + ) + port map ( + clk_sys_i => clk_pll_62m5, + clk_dmtd_i => clk_pll_dmtd, + clk_ref_i => clk_ref_62m5, + clk_aux_i => (others => '0'), + clk_10m_ext_i => '0', -- ! DJB ! eventually external 10 MHz clock + clk_ext_mul_i => ext_ref_mul, + clk_ext_mul_locked_i => ext_ref_mul_locked, + clk_ext_stopped_i => ext_ref_mul_stopped, + clk_ext_rst_o => ext_ref_rst, + pps_ext_i => '0', -- ! DJB ! eventually external PPS + rst_n_i => rst_pll_62m5_n, + dac_hpll_load_p1_o => dac_hpll_load_p1, + dac_hpll_data_o => dac_hpll_data, + dac_dpll_load_p1_o => dac_dpll_load_p1, + dac_dpll_data_o => dac_dpll_data, + phy16_o => phy16_from_wrc, + phy16_i => phy16_to_wrc, + scl_o => eeprom_scl_o, -- not using the I2C bus because we don't have a + scl_i => eeprom_scl_i, -- dedicated EEPROm for WR Cal. Instead plan + sda_o => eeprom_sda_o, -- to read cal values over the UART and store + sda_i => eeprom_sda_i, -- on the main uSD card. + sfp_scl_o => sfp_scl_o, + sfp_scl_i => sfp_scl_i, + sfp_sda_o => sfp_sda_o, + sfp_sda_i => sfp_sda_i, + sfp_det_i => sfp_mod_def0_b, + spi_sclk_o => open, + spi_ncs_o => open, + spi_mosi_o => open, + spi_miso_i => '0', + uart_rxd_i => wr_uart_rxd, + uart_txd_o => wr_uart_txd, + owr_pwren_o => open, + owr_en_o => open, + owr_i => "11", + wb_slave_i => wb_slave_in, + wb_slave_o => wb_slave_out, + aux_master_o => open, + aux_master_i => cc_dummy_master_in, + wrf_src_o => open, + wrf_src_i => c_dummy_src_in, + wrf_snk_o => open, + wrf_snk_i => c_dummy_snk_in, + wrs_tx_data_i => (others=>'0'), + wrs_tx_valid_i => '0', + wrs_tx_dreq_o => open, + wrs_tx_last_i => '1', + wrs_tx_flush_i => '0', + wrs_tx_cfg_i => c_tx_streamer_cfg_default, + wrs_rx_first_o => open, + wrs_rx_last_o => open, + wrs_rx_data_o => open, + wrs_rx_valid_o => open, + wrs_rx_dreq_i => '0', + wrs_rx_cfg_i => c_rx_streamer_cfg_default, + wb_eth_master_o => open, + wb_eth_master_i => cc_dummy_master_in, + aux_diag_i => (others=>(others=>'0')), + aux_diag_o => open, + tm_dac_value_o => open, + tm_dac_wr_o => open, + tm_clk_aux_lock_en_i => (others=>'0'), + tm_clk_aux_locked_o => open, + timestamps_o => open, + timestamps_ack_i => '1', + abscal_txts_o => open, + abscal_rxts_o => open, + fc_tx_pause_req_i => '0', + fc_tx_pause_delay_i => (others=>'0'), + fc_tx_pause_ready_o => open, + tm_link_up_o => open, + tm_time_valid_o => open, + tm_tai_o => open, + tm_cycles_o => open, + led_act_o => LED_ACT, + led_link_o => LED_LINK, + btn1_i => '1', + btn2_i => '1', + pps_p_o => pps, + pps_led_o => open, + link_ok_o => link_ok_o); + + -- I2C interface for SFP + --sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z'; + --sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z'; + --sfp_scl_i <= sfp_mod_def1_b; + --sfp_sda_i <= sfp_mod_def2_b; + + s00_axi_aclk_o <= clk_pll_62m5; + + zero <= '0'; + cmp_axi4lite_wbm: wb_axi4lite_bridge + port map ( + clk_sys_i => clk_pll_62m5, + rst_n_i => s00_axi_aresetn, + + AWADDR => s00_axi_awaddr, + AWVALID => s00_axi_awvalid, + AWREADY => s00_axi_awready, + WDATA => s00_axi_wdata, + WSTRB => s00_axi_wstrb, + WVALID => s00_axi_wvalid, + WREADY => s00_axi_wready, + WLAST => zero, + BRESP => s00_axi_bresp, + BVALID => s00_axi_bvalid, + BREADY => s00_axi_bready, + ARADDR => s00_axi_araddr, + ARVALID => s00_axi_arvalid, + ARREADY => s00_axi_arready, + RDATA => s00_axi_rdata, + RRESP => s00_axi_rresp, + RVALID => s00_axi_rvalid, + RREADY => s00_axi_rready, + RLAST => s00_axi_rlast, + + wb_adr => wb_slave_in.adr, + wb_dat_m2s => wb_slave_in.dat, + wb_sel => wb_slave_in.sel, + wb_cyc => wb_slave_in.cyc, + wb_stb => wb_slave_in.stb, + wb_we => wb_slave_in.we, + + wb_dat_s2m => wb_slave_out.dat, + wb_err => wb_slave_out.err, + wb_rty => wb_slave_out.rty, + wb_ack => wb_slave_out.ack, + wb_stall => wb_slave_out.stall + ); + + + -- locals to outputs + clk_pps_o <= clk_ref_62m5; -- ref_clk + pps_o <= pps; -- pps + +end architecture structure ; -- of n3xx_wr_top + diff --git a/fpga/usrp3/top/n3xx/setupenv.sh b/fpga/usrp3/top/n3xx/setupenv.sh new file mode 100644 index 000000000..0be100b62 --- /dev/null +++ b/fpga/usrp3/top/n3xx/setupenv.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-N3x0" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["N300"]="zynq/xc7z035/ffg900/-2" +PRODUCT_ID_MAP["N310"]="zynq/xc7z100/ffg900/-2" +PRODUCT_ID_MAP["N320"]="zynq/xc7z100/ffg900/-2" +PRODUCT_ID_MAP["EISCAT"]="zynq/xc7z100/ffg900/-2" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh diff --git a/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile new file mode 100644 index 000000000..1e783b2de --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/Makefile @@ -0,0 +1,84 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs +include $(BASE_DIR)/../lib/xge/Makefile.srcs +include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIGE_PHY_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(PACKET_PROC_SRCS) \ +) +#$(IP_FIFO_SHORT_2CLK_SRCS) \ + + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +#include $(BASE_DIR)/../sim/general/Makefile.srcs +#include $(BASE_DIR)/../sim/control/Makefile.srcs +#include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = arm_to_sfp_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath arm_to_sfp_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv new file mode 100644 index 000000000..46005a13a --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/arm_to_sfp_tb.sv @@ -0,0 +1,528 @@ +// +// Copyright 2017 Ettus Research +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axis_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module arm_to_sfp_tb(); + `TEST_BENCH_INIT("arm_to_sfp_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // ARM to SFP Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire xgige_refclk, xgige_clk156, xgige_dclk; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + + wire [63:0] m_xgmii_txd; + wire [7:0] m_xgmii_txc; + wire [63:0] m_xgmii_rxd; + wire [7:0] m_xgmii_rxc; + wire [63:0] s_xgmii_txd; + wire [7:0] s_xgmii_txc; + wire [63:0] s_xgmii_rxd; + wire [7:0] s_xgmii_rxc; + wire [7:0] m_xgmii_status; + wire [7:0] s_xgmii_status; + wire m_xge_phy_resetdone; + wire s_xge_phy_resetdone; + wire m_mdc, m_mdio_in, m_mdio_out; + wire s_mdc, s_mdio_in, s_mdio_out; + wire sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable; + + + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire [3:0] loop_tuser; + wire loop_tlast, loop_tvalid, loop_tready; + + wire [7:0] wb_adr_i; + wire wb_cyc_i; + wire [31:0] wb_dat_i; + wire wb_stb_i; + wire wb_we_i; + wire wb_ack_o; + wire [31:0] wb_dat_o; + wire wb_int_o; + wire [63:0] c2e_tdata_int; + wire [3:0] c2e_tuser_int; + wire c2e_tlast_int; + wire c2e_tvalid_int; + wire c2e_tready_int; + wire [63:0] c2e_tdata; + wire [3:0] c2e_tuser; + wire c2e_tlast; + wire c2e_tvalid; + wire c2e_tready; + wire m_axis_tvalid; + wire m_axis_tlast; + wire [63:0] m_axis_tdata; + wire m_axis_tready; + wire [3:0] m_axis_tuser; + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = xgige_refclk; + //assign s_user_clk = xgige_refclk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .areset(GSR), + .refclk_p(XG_CLK_P), + .refclk_n(XG_CLK_N), + .refclk(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + axis_master #(.DWIDTH(34)) m_axis (.clk(m_user_clk)); + axis_slave #(.DWIDTH(68)) s_axis (.clk(s_user_clk)); + + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2.5; + independent_clock <= 1'b1; + #2.5; + end + end + + assign sfpp_rxlos = 1'b0; + assign sfpp_tx_fault = 1'b0; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware + ten_gig_eth_pcs_pma_gt_common_block + ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b001 /*3'b101*GTSOUTHREFCLK0*/) + ); + + ten_gige_phy ten_gige_phy_master_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(m_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(m_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(m_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(m_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(m_mdc), // Management Data Clock + .mdio_in(m_mdio_in), // Management Data In + .mdio_out(m_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(m_xgmii_status), // Core status + .resetdone(m_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(m_xgmii_txd), + .xgmii_txc(m_xgmii_txc), + .xgmii_rxd(m_xgmii_rxd), + .xgmii_rxc(m_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(m_user_clk), + .sys_rst(GSR), + .rx_tdata(s_axis.axis.tdata[63:0]), + .rx_tuser(s_axis.axis.tdata[67:64]), + .rx_tlast(s_axis.axis.tlast), + .rx_tvalid(s_axis.axis.tvalid), + .rx_tready(/*s_axis.axis.tready*/1'b1), + .tx_tdata(c2e_tdata), + .tx_tuser(c2e_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2e_tlast), + .tx_tvalid(c2e_tvalid), + .tx_tready(c2e_tready), + // Other + .phy_ready(m_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign m_phy_status = {8'h00, m_xgmii_status}; + + axi_fifo32_to_fifo64 inst_axi_fifo32_to_fifo64 + ( + .clk(m_user_clk), + .reset(GSR), + .i_tdata({m_axis.axis.tdata[31:0]}), // endian swap + .i_tuser(m_axis.axis.tdata[33:32]), + .i_tlast(m_axis.axis.tlast), + .i_tvalid(m_axis.axis.tvalid), + .i_tready(m_axis.axis.tready), + .o_tdata(m_axis_tdata), + .o_tuser(m_axis_tuser), + .o_tlast(m_axis_tlast), + .o_tvalid(m_axis_tvalid), + .o_tready(m_axis_tready) + ); + + arm_framer inst_arm_framer ( + .clk (m_user_clk), + .reset (GSR), + .clear (clear), + .s_axis_tdata (m_axis_tdata), + .s_axis_tuser (m_axis_tuser), + .s_axis_tlast (m_axis_tlast), + .s_axis_tvalid (m_axis_tvalid), + .s_axis_tready (m_axis_tready), + .m_axis_tdata (c2e_tdata_int), + .m_axis_tuser (c2e_tuser_int), + .m_axis_tlast (c2e_tlast_int), + .m_axis_tvalid (c2e_tvalid_int), + .m_axis_tready (c2e_tready_int) + ); + + axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux + (.clk(m_user_clk), .reset(GSR), .clear(clear), + .i0_tdata({c2e_tuser_int,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int), + .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(), + .i2_tdata(), .i2_tlast(), .i2_tvalid(), .i2_tready(), + .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata({c2e_tuser,c2e_tdata}), .o_tlast(c2e_tlast), .o_tvalid(c2e_tvalid), .o_tready(c2e_tready)); + + ten_gige_phy ten_gige_phy_slave_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(s_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(s_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(s_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(s_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(s_mdc), // Management Data Clock + .mdio_in(s_mdio_in), // Management Data In + .mdio_out(s_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(s_xgmii_status), // Core status + .resetdone(s_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset2), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(s_xgmii_txd), + .xgmii_txc(s_xgmii_txc), + .xgmii_rxd(s_xgmii_rxd), + .xgmii_rxc(s_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(s_user_clk), + .sys_rst(GSR), + .rx_tdata(loop_tdata), + .rx_tuser(loop_tuser), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(loop_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Other + .phy_ready(s_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign s_phy_status = {8'h00, s_xgmii_status}; + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + m_axis.reset; + while (GSR) @(posedge XG_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_axis.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'h0000_0000_0000_ffff}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'hffff_ffff_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_0806_0001_0800}, 1'b0); + // m_axis.push_word({4'b0, 64'h0604_0001_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_c0a8_0a64_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_c0a8_0a0a}, 1'b1); + //`TEST_CASE_DONE(1'b1); + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'hffff_ffff_ffff_ce20}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'had1b_c57a_0806_0001}, 1'b0); + // m_axis.push_word({4'b0, 64'h0800_0604_0001_ce20}, 1'b0); + // m_axis.push_word({4'b0, 64'had1b_c57a_c0a8_0a64}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_c0a8}, 1'b0); + // m_axis.push_word({4'd2, 64'h0a0a_1111_1111_1111}, 1'b1); + //`TEST_CASE_DONE(1'b1); + // repeat(2000) @(posedge m_user_clk); + `TEST_CASE_START("Test Ethernet packet"); + s_axis.axis.tready = 0; + m_axis.push_word({2'b0, 32'hffff_ffff}, 1'b0); + s_axis.axis.tready = 1; + m_axis.push_word({2'b0, 32'hffff_9aa9}, 1'b0); + m_axis.push_word({2'b0, 32'h6400_e341}, 1'b0); + m_axis.push_word({2'b0, 32'h0800_4500}, 1'b0); + m_axis.push_word({2'b0, 32'h0148_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_4011}, 1'b0); + m_axis.push_word({2'b0, 32'h79a6_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_ffff}, 1'b0); + m_axis.push_word({2'b0, 32'hffff_0044}, 1'b0); + m_axis.push_word({2'b0, 32'h0043_0134}, 1'b0); + m_axis.push_word({2'b0, 32'h90be_0101}, 1'b0); + m_axis.push_word({2'b0, 32'h0600_d2ab}, 1'b0); + m_axis.push_word({2'b0, 32'h9f01_0007}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_9aa9}, 1'b0); + m_axis.push_word({2'b0, 32'h6400_e341}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_6382}, 1'b0); + m_axis.push_word({2'b0, 32'h5363_3501}, 1'b0); + m_axis.push_word({2'b0, 32'h013d_0701}, 1'b0); + m_axis.push_word({2'b0, 32'h9aa9_6400}, 1'b0); + m_axis.push_word({2'b0, 32'he341_3902}, 1'b0); + m_axis.push_word({2'b0, 32'h0240_3707}, 1'b0); + m_axis.push_word({2'b0, 32'h0103_060c}, 1'b0); + m_axis.push_word({2'b0, 32'h0f1c_2a3c}, 1'b0); + m_axis.push_word({2'b0, 32'h0c75_6468}, 1'b0); + m_axis.push_word({2'b0, 32'h6370_2031}, 1'b0); + m_axis.push_word({2'b0, 32'h2e32_342e}, 1'b0); + m_axis.push_word({2'b0, 32'h31ff_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'b0, 32'h0000_0000}, 1'b0); + m_axis.push_word({2'd2, 32'h0000_0000}, 1'b1); + + `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + `TEST_CASE_START("Test Ethernet packet"); + s_axis.axis.tready = 0; + m_axis.push_word({2'b0, 32'h01005e7f }, 1'b0); + s_axis.axis.tready = 1; + m_axis.push_word({2'b0, 32'hfffa90e2 }, 1'b0); + m_axis.push_word({2'b0, 32'hba3aa7e8 }, 1'b0); + m_axis.push_word({2'b0, 32'h08004500 }, 1'b0); + m_axis.push_word({2'b0, 32'h00c7515e }, 1'b0); + m_axis.push_word({2'b0, 32'h40000111 }, 1'b0); + m_axis.push_word({2'b0, 32'h6d1bc0a8 }, 1'b0); + m_axis.push_word({2'b0, 32'h0a0aefff }, 1'b0); + m_axis.push_word({2'b0, 32'hfffad40f }, 1'b0); + m_axis.push_word({2'b0, 32'h076c00b3 }, 1'b0); + m_axis.push_word({2'b0, 32'hbb714d2d }, 1'b0); + m_axis.push_word({2'b0, 32'h53454152 }, 1'b0); + m_axis.push_word({2'b0, 32'h4348202a }, 1'b0); + m_axis.push_word({2'b0, 32'h20485454 }, 1'b0); + m_axis.push_word({2'b0, 32'h502f312e }, 1'b0); + m_axis.push_word({2'b0, 32'h310d0a48 }, 1'b0); + m_axis.push_word({2'b0, 32'h4f53543a }, 1'b0); + m_axis.push_word({2'b0, 32'h20323339 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323535 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323535 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e323530 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a313930 }, 1'b0); + m_axis.push_word({2'b0, 32'h300d0a4d }, 1'b0); + m_axis.push_word({2'b0, 32'h414e3a20 }, 1'b0); + m_axis.push_word({2'b0, 32'h22737364 }, 1'b0); + m_axis.push_word({2'b0, 32'h703a6469 }, 1'b0); + m_axis.push_word({2'b0, 32'h73636f76 }, 1'b0); + m_axis.push_word({2'b0, 32'h6572220d }, 1'b0); + m_axis.push_word({2'b0, 32'h0a4d583a }, 1'b0); + m_axis.push_word({2'b0, 32'h20310d0a }, 1'b0); + m_axis.push_word({2'b0, 32'h53543a20 }, 1'b0); + m_axis.push_word({2'b0, 32'h75726e3a }, 1'b0); + m_axis.push_word({2'b0, 32'h6469616c }, 1'b0); + m_axis.push_word({2'b0, 32'h2d6d756c }, 1'b0); + m_axis.push_word({2'b0, 32'h74697363 }, 1'b0); + m_axis.push_word({2'b0, 32'h7265656e }, 1'b0); + m_axis.push_word({2'b0, 32'h2d6f7267 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a736572 }, 1'b0); + m_axis.push_word({2'b0, 32'h76696365 }, 1'b0); + m_axis.push_word({2'b0, 32'h3a646961 }, 1'b0); + m_axis.push_word({2'b0, 32'h6c3a310d }, 1'b0); + m_axis.push_word({2'b0, 32'h0a555345 }, 1'b0); + m_axis.push_word({2'b0, 32'h522d4147 }, 1'b0); + m_axis.push_word({2'b0, 32'h454e543a }, 1'b0); + m_axis.push_word({2'b0, 32'h20476f6f }, 1'b0); + m_axis.push_word({2'b0, 32'h676c6520 }, 1'b0); + m_axis.push_word({2'b0, 32'h4368726f }, 1'b0); + m_axis.push_word({2'b0, 32'h6d652f35 }, 1'b0); + m_axis.push_word({2'b0, 32'h342e302e }, 1'b0); + m_axis.push_word({2'b0, 32'h32383430 }, 1'b0); + m_axis.push_word({2'b0, 32'h2e353920 }, 1'b0); + m_axis.push_word({2'b0, 32'h4c696e75 }, 1'b0); + m_axis.push_word({2'b1, 32'h78111111 }, 1'b1); + + `TEST_CASE_DONE(1'b1); + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile new file mode 100644 index 000000000..c4cdf38dd --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/aurora_loopback/Makefile @@ -0,0 +1,80 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(RFNOC_SRCS) \ +../../n3xx_npio_qsfp_wrapper.v \ +../../n3xx_mgt_io_core.v \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(AURORA_PHY_SRCS) \ +$(AURORA_PHY_1_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs +include $(BASE_DIR)/../sim/control/Makefile.srcs +include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = aurora_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 70 + +SIM_SRCS = \ +$(abspath aurora_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv new file mode 100644 index 000000000..ed328f153 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/aurora_loopback/aurora_loopback_tb.sv @@ -0,0 +1,395 @@ +///////////////////////////////////////////////////////////////// +// +// Copyright 2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +///////////////////////////////////////////////////////////////// + + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module aurora_loopback_tb(); + `TEST_BENCH_INIT("aurora_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_CLK(bus_clk, 1000/200, 50) //define 200 MHz bus clk + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + localparam PACKET_MODE = 1; + + // Aurora Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // + // |-------------------------------------| + // | n3xx_npio_qsfp_wrapper | + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // <==== |------------| |----------------| + // |-------------------------------------| + + // Initialize DUT + wire aurora_refclk, aurora_init_clk; + wire aurora_clk156; + wire m_user_rst, s_user_rst; + wire m_channel_up, s_channel_up; + wire m_hard_err, s_hard_err; + wire m_soft_err, s_soft_err; + wire s_link_up; + +(* dont_touch = "true" *) IBUFDS_GTE2 aurora_refclk_ibuf ( + .ODIV2(), + .CEB (1'b0), + .I (XG_CLK_P), + .IB(XG_CLK_N), + .O (aurora_refclk) + ); + + aurora_phy_clk_gen aurora_clk_gen_i ( + .refclk_ibuf(aurora_refclk), + .clk156(aurora_clk156), + .init_clk(aurora_init_clk) + ); + wire qpllreset, qpllreset_slave; + wire qplllock, qplllock_slave; + wire qplloutclk, qplloutclk_slave; + wire qplloutrefclk, qplloutrefclk_slave; + wire qpllrefclklost, qpllrefclklost_slave; + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i, qpll_drpdo_out_s_i; + wire qpll_drprdy_out_i, qpll_drprdy_out_s_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (qplloutclk), //to sfp + .gt_qpllrefclk_quad1_out (qplloutrefclk), // to sfp + .GT0_GTREFCLK0_COMMON_IN (aurora_refclk), +//----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (qplllock), //from 1st sfp + .GT0_QPLLRESET_IN (qpllreset), //from 1st sfp + .GT0_QPLLLOCKDETCLK_IN (aurora_init_clk), + .GT0_QPLLREFCLKLOST_OUT (qpllrefclklost), //from 1st sfp +//---------------------- Common DRP Ports ---------------------- //not really used??? + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (aurora_init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + wire au_master_tx_out_clk, au_slave_tx_out_clk; + wire au_master_gt_pll_lock, au_slave_gt_pll_lock; + wire au_user_clk, au_sync_clk, au_mmcm_locked; + wire au_s_user_clk, au_s_sync_clk, au_s_mmcm_locked; + wire au_master_phy_reset; + + aurora_phy_mmcm aurora_phy_mmcm_0 ( + .aurora_tx_clk_unbuf(au_master_tx_out_clk), + .mmcm_reset(!au_master_gt_pll_lock), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .mmcm_locked(au_mmcm_locked) + ); + + wire [63:0] m_i_tdata, m_o_tdata; + wire m_i_tvalid, m_i_tready, m_o_tvalid; + wire [63:0] s_i_tdata, s_o_tdata; + wire s_i_tvalid, s_i_tready, s_o_tvalid; + wire [63:0] loop_tdata; + wire loop_tlast, loop_tvalid, loop_tready; + wire [31:0] m_overruns; + reg [31:0] s_overruns; + wire [31:0] m_soft_errors, s_soft_errors; + reg m_bist_gen, m_bist_check, s_bist_loopback; + reg [5:0] m_bist_rate; + wire m_bist_locked; + wire [47:0] m_bist_samps, m_bist_errors; + + cvita_master m_tx_chdr (.clk(au_user_clk)); + cvita_slave m_rx_chdr (.clk(au_user_clk)); + + aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_master_i ( + // Resets + .areset(GSR), + // Clocks + .refclk(aurora_refclk), + .qpllclk(qplloutclk), + .qpllrefclk(qplloutrefclk), + .user_clk(au_user_clk), + .sync_clk(au_sync_clk), + .init_clk(aurora_init_clk), + .user_rst(m_user_rst), + // GTX Serial I/O + .tx_p(SFP_LN0_P), .tx_n(SFP_LN0_N), + .rx_p(SFP_LN1_P), .rx_n(SFP_LN1_N), + // AXI4-Stream TX Interface + .s_axis_tdata(m_i_tdata), .s_axis_tvalid(m_i_tvalid), .s_axis_tready(m_i_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(m_o_tdata), .m_axis_tvalid(m_o_tvalid), + // AXI4-Lite Config Interface + .s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(), + .s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(), + .s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1), + .s_axi_arready(), .s_axi_arvalid(1'b0), + .s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err), + .qplllock(qplllock), + .qpllreset(qpllreset), + .qpllrefclklost(qpllrefclklost), + .tx_out_clk(au_master_tx_out_clk), + .gt_pll_lock(au_master_gt_pll_lock), + .mmcm_locked(au_mmcm_locked) + ); + + aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_master_i ( + // Clocks and resets + .phy_clk(au_user_clk), .phy_rst(m_user_rst), + .sys_clk(au_user_clk), .sys_rst(m_user_rst), + .clear(1'b0), + // PHY Interface + .phy_s_axis_tdata(m_o_tdata), .phy_s_axis_tvalid(m_o_tvalid), + .phy_m_axis_tdata(m_i_tdata), .phy_m_axis_tvalid(m_i_tvalid), .phy_m_axis_tready(m_i_tready), + // User Interface + .s_axis_tdata(m_tx_chdr.axis.tdata), .s_axis_tlast(m_tx_chdr.axis.tlast), + .s_axis_tvalid(m_tx_chdr.axis.tvalid), .s_axis_tready(m_tx_chdr.axis.tready), + .m_axis_tdata(m_rx_chdr.axis.tdata), .m_axis_tlast(m_rx_chdr.axis.tlast), + .m_axis_tvalid(m_rx_chdr.axis.tvalid), .m_axis_tready(m_rx_chdr.axis.tready), + // Misc PHY + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err), + .overruns(m_overruns), .soft_errors(m_soft_errors), + //BIST + .bist_gen_en(m_bist_gen), .bist_checker_en(m_bist_check), .bist_loopback_en(1'b0), .bist_gen_rate(m_bist_rate), + .bist_checker_locked(m_bist_locked), .bist_checker_samps(m_bist_samps), .bist_checker_errors(m_bist_errors) + ); + +reg reg_wr_req_s; +reg [13:0] reg_wr_addr_s; +reg [31:0] reg_wr_data_s; +reg reg_rd_req_s; +reg [13:0] reg_rd_addr_s; +wire reg_rd_resp_s; +wire [31:0] reg_rd_data_s; + +n3xx_npio_qsfp_wrapper #( + .LANES(1), // Number of lanes of Aurora to instantiate (Supported = {1,2,3,4}) + .REG_BASE(32'h0), // Base register address + .PORTNUM_BASE(4), // Base port number for discovery + .REG_DWIDTH(32), // Width of regport address bus + .REG_AWIDTH(14) // Width of regport data bus +) qsfp_wrapper_inst ( + // Clocks and Resets + .areset(GSR), + .bus_clk(bus_clk), + .misc_clk(aurora_init_clk), + .bus_rst(GSR), + .gt_refclk(aurora_refclk), + .gt_clk156(aurora_clk156), + // Serial lanes + .txp(SFP_LN1_P), + .txn(SFP_LN1_N), + .rxp(SFP_LN0_P), + .rxn(SFP_LN0_N), + // AXIS input interface + .s_axis_tdata(loop_tdata), + .s_axis_tlast(loop_tlast), + .s_axis_tvalid(~s_bist_loopback & loop_tvalid), + .s_axis_tready(loop_tready), + // AXIS output interface + .m_axis_tdata(loop_tdata), + .m_axis_tlast(loop_tlast), + .m_axis_tvalid(loop_tvalid), + .m_axis_tready(~s_bist_loopback & loop_tready), + // Register ports + .reg_wr_req(reg_wr_req_s), //input reg_wr_req, + .reg_wr_addr(reg_wr_addr_s), //input [REG_AWIDTH-1:0] reg_wr_addr, + .reg_wr_data(reg_wr_data_s), //input [REG_DWIDTH-1:0] reg_wr_data, + .reg_rd_req(reg_rd_req_s), //input reg_rd_req, + .reg_rd_addr(reg_rd_addr_s), //input [REG_AWIDTH-1:0] reg_rd_addr, + .reg_rd_resp(reg_rd_resp_s), //output reg_rd_resp, + .reg_rd_data(reg_rd_data_s), //output [REG_DWIDTH-1:0] reg_rd_data, + + .link_up(s_link_up), + .activity() +); + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + while (GSR) @(posedge aurora_refclk); + `TEST_CASE_DONE((~GSR)); + + m_bist_gen <= 1'b0; + m_bist_rate <= 6'd0; + m_bist_check <= 1'b0; + s_bist_loopback <= 1'b0; + + m_tx_chdr.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge au_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up. Uses QSFP Wrapper"); + while (s_link_up !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Run PRBS BIST"); + s_bist_loopback <= PACKET_MODE; + $display("Need to interact with regport to set s_bist_loopback."); + reg_wr_req_s <= 1; + reg_wr_addr_s <= 4; + reg_wr_data_s <= 4; + @(posedge bus_clk); + repeat (3) @(posedge au_user_clk); + reg_wr_req_s <= 0; + m_bist_rate <= 6'd60; + m_bist_gen <= 1'b1; + m_bist_check <= 1'b1; + @(posedge au_user_clk); + while (m_bist_locked !== 1'b1) @(posedge au_user_clk); + repeat (512) @(posedge au_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge au_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge au_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.src_sid==header_out.src_sid, "Bad packet: Wrong Src SID"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong Dst SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.src_sid==header_out.src_sid, "Bad packet: Wrong Src SID"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong Dst SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + repeat (10) @(posedge au_user_clk); //Wait for clear to go low + m_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(200, 64'd0, 64'h100, header); + end + begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==201, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + m_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==21, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + reg_rd_req_s <= 1; + reg_rd_addr_s <= 'h20; + @(posedge reg_rd_resp_s) + reg_rd_req_s <= 0; + s_overruns <= reg_rd_data_s; + `TEST_CASE_DONE((s_overruns === 32'd0)); + + s_bist_loopback <= 1'b1; + + `TEST_CASE_START("Run PRBS BIST (Loopback Mode)"); + @(posedge au_user_clk); + m_bist_gen <= 1'b1; + m_bist_rate <= 6'd60; + m_bist_check <= 1'b1; + @(posedge au_user_clk); + while (m_bist_locked !== 1'b1) @(posedge au_user_clk); + repeat (512) @(posedge au_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge au_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge au_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + s_bist_loopback <= 1'b0; + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + reg_rd_req_s <= 1; + reg_rd_addr_s <= 'h20; + @(posedge reg_rd_resp_s) + reg_rd_req_s <= 0; + s_overruns <= reg_rd_data_s; + `TEST_CASE_DONE((s_overruns === 32'd0)); + + `TEST_BENCH_DONE; + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile new file mode 100644 index 000000000..738cb12dc --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/Makefile @@ -0,0 +1,70 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_tb + +SIM_SRCS = \ +$(abspath dram_fifo_tb.sv) \ +$(abspath axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv new file mode 100644 index 000000000..63bea218e --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/axis_dram_fifo_single.sv @@ -0,0 +1,493 @@ +// +// Copyright 2015 Ettus Research LLC +// + +`timescale 1ns/1ps + +module axis_dram_fifo_single +#( + parameter DIFF_CLK = 0, + parameter SR_BASE = 0 +) ( + input bus_clk, + input bus_rst, + input sys_clk_p, + input sys_clk_n, + input sys_rst_n, + input dma_engine_clk, + + input [63:0] i_tdata, + input i_tlast, + input i_tvalid, + output i_tready, + + output [63:0] o_tdata, + output o_tlast, + output o_tvalid, + input o_tready, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + output [31:0] rb_data, + + input [63:0] forced_bit_err, + + output init_calib_complete +); + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk + + // Misc declarations + axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(dma_engine_clk)); + axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(dma_engine_clk)); + axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_rd(.clk(ddr3_axi_clk)); + axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(4)) mig_axi_wr(.clk(ddr3_axi_clk)); + + wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_p; + wire [15:0] ddr3_addr; // Address + wire [2:0] ddr3_ba; // Bank Address + wire ddr3_ras_n; // Row Address Strobe. + wire ddr3_cas_n; // Column address select + wire ddr3_we_n; // Write Enable + wire ddr3_reset_n; // SDRAM reset pin. + wire [0:0] ddr3_ck_p; // Differential clock + wire [0:0] ddr3_ck_n; + wire [0:0] ddr3_cke; // Clock Enable + wire [0:0] ddr3_cs_n; // Chip Select + wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ... + wire [0:0] ddr3_odt; // On-Die termination enable. + + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + axi_dma_fifo #( + .DEFAULT_BASE(30'h02000000), + .DEFAULT_MASK(30'hFF000000), + .DEFAULT_TIMEOUT(280), + .SR_BASE(SR_BASE), + .EXT_BIST(1), + .SIMULATION(1) + ) axi_dma_fifo_i0 ( + // + // Clocks and reset + .bus_clk (bus_clk), + .bus_reset (bus_rst), + .dram_clk (dma_engine_clk), + .dram_reset (ddr3_axi_rst), + // + // AXI Write address channel + .m_axi_awid (dma_axi_wr.addr.id), + .m_axi_awaddr (dma_axi_wr.addr.addr), + .m_axi_awlen (dma_axi_wr.addr.len), + .m_axi_awsize (dma_axi_wr.addr.size), + .m_axi_awburst (dma_axi_wr.addr.burst), + .m_axi_awlock (dma_axi_wr.addr.lock), + .m_axi_awcache (dma_axi_wr.addr.cache), + .m_axi_awprot (dma_axi_wr.addr.prot), + .m_axi_awqos (dma_axi_wr.addr.qos), + .m_axi_awregion (dma_axi_wr.addr.region), + .m_axi_awuser (dma_axi_wr.addr.user), + .m_axi_awvalid (dma_axi_wr.addr.valid), + .m_axi_awready (dma_axi_wr.addr.ready), + // + // AXI Write data channel. + .m_axi_wdata (dma_axi_wr.data.data), + .m_axi_wstrb (dma_axi_wr.data.strb), + .m_axi_wlast (dma_axi_wr.data.last), + .m_axi_wuser (dma_axi_wr.data.user), + .m_axi_wvalid (dma_axi_wr.data.valid), + .m_axi_wready (dma_axi_wr.data.ready), + // + // AXI Write response channel signals + .m_axi_bid (dma_axi_wr.resp.id), + .m_axi_bresp (dma_axi_wr.resp.resp), + .m_axi_buser (dma_axi_wr.resp.user), + .m_axi_bvalid (dma_axi_wr.resp.valid), + .m_axi_bready (dma_axi_wr.resp.ready), + // + // AXI Read address channel + .m_axi_arid (dma_axi_rd.addr.id), + .m_axi_araddr (dma_axi_rd.addr.addr), + .m_axi_arlen (dma_axi_rd.addr.len), + .m_axi_arsize (dma_axi_rd.addr.size), + .m_axi_arburst (dma_axi_rd.addr.burst), + .m_axi_arlock (dma_axi_rd.addr.lock), + .m_axi_arcache (dma_axi_rd.addr.cache), + .m_axi_arprot (dma_axi_rd.addr.prot), + .m_axi_arqos (dma_axi_rd.addr.qos), + .m_axi_arregion (dma_axi_rd.addr.region), + .m_axi_aruser (dma_axi_rd.addr.user), + .m_axi_arvalid (dma_axi_rd.addr.valid), + .m_axi_arready (dma_axi_rd.addr.ready), + // + // AXI Read data channel + .m_axi_rid (dma_axi_rd.data.id), + .m_axi_rdata (dma_axi_rd.data.data), + .m_axi_rresp (dma_axi_rd.data.resp), + .m_axi_rlast (dma_axi_rd.data.last), + .m_axi_ruser (dma_axi_rd.data.user), + .m_axi_rvalid (dma_axi_rd.data.valid), + .m_axi_rready (dma_axi_rd.data.ready), + // + // CHDR friendly AXI stream input + .i_tdata (i_tdata), + .i_tlast (i_tlast), + .i_tvalid (i_tvalid), + .i_tready (i_tready), + // + // CHDR friendly AXI Stream output + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .o_tready (o_tready), + // + // Settings + .set_stb (set_stb), + .set_addr (set_addr), + .set_data (set_data), + .rb_data (rb_data), + + .debug() + ); + + //--------------------------------------------------- + // We use an interconnect to connect to FIFOs. + //--------------------------------------------------- + // Attach to third slave just to validate proper ID handling in interconnect + + axi_intercon_4x64_256_bd_wrapper axi_intercon_i ( + // + .S00_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S00_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S00_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S00_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S00_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S00_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S00_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S00_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S00_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S00_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S00_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S00_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S00_AXI_AWREADY (), // output S01_AXI_AWREADY + .S00_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S00_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S00_AXI_WLAST (0), // input S01_AXI_WLAST + .S00_AXI_WVALID (0), // input S01_AXI_WVALID + .S00_AXI_WREADY (), // output S01_AXI_WREADY + .S00_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S00_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S00_AXI_BVALID (), // output S01_AXI_BVALID + .S00_AXI_BREADY (1), // input S01_AXI_BREADY + .S00_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S00_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S00_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S00_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S00_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S00_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S00_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S00_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S00_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S00_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S00_AXI_ARREADY (), // output S01_AXI_ARREADY + .S00_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S00_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S00_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S00_AXI_RLAST (), // output S01_AXI_RLAST + .S00_AXI_RVALID (), // output S01_AXI_RVALID + .S00_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S01_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S01_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S01_AXI_AWREADY (), // output S01_AXI_AWREADY + .S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S01_AXI_WLAST (0), // input S01_AXI_WLAST + .S01_AXI_WVALID (0), // input S01_AXI_WVALID + .S01_AXI_WREADY (), // output S01_AXI_WREADY + .S01_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S01_AXI_BVALID (), // output S01_AXI_BVALID + .S01_AXI_BREADY (1), // input S01_AXI_BREADY + .S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S01_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S01_AXI_ARREADY (), // output S01_AXI_ARREADY + .S01_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S01_AXI_RLAST (), // output S01_AXI_RLAST + .S01_AXI_RVALID (), // output S01_AXI_RVALID + .S01_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S02_AXI_ACLK (dma_engine_clk), // input S01_AXI_ACLK + .S02_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S02_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S02_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S02_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S02_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S02_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S02_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S02_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S02_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S02_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S02_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S02_AXI_AWREADY (), // output S01_AXI_AWREADY + .S02_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S02_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S02_AXI_WLAST (0), // input S01_AXI_WLAST + .S02_AXI_WVALID (0), // input S01_AXI_WVALID + .S02_AXI_WREADY (), // output S01_AXI_WREADY + .S02_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S02_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S02_AXI_BVALID (), // output S01_AXI_BVALID + .S02_AXI_BREADY (1), // input S01_AXI_BREADY + .S02_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S02_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S02_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S02_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S02_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S02_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S02_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S02_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S02_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S02_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S02_AXI_ARREADY (), // output S01_AXI_ARREADY + .S02_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S02_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S02_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S02_AXI_RLAST (), // output S01_AXI_RLAST + .S02_AXI_RVALID (), // output S01_AXI_RVALID + .S02_AXI_RREADY (1), // input S01_AXI_RREADY + // + .S03_AXI_ACLK (dma_engine_clk), // input S00_AXI_ACLK + .S03_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN + .S03_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID + .S03_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR + .S03_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN + .S03_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE + .S03_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST + .S03_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK + .S03_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE + .S03_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT + .S03_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS + .S03_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID + .S03_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY + .S03_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA + .S03_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB + .S03_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST + .S03_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID + .S03_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY + .S03_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID + .S03_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP + .S03_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID + .S03_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY + .S03_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID + .S03_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR + .S03_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN + .S03_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE + .S03_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST + .S03_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK + .S03_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE + .S03_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT + .S03_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS + .S03_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID + .S03_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY + .S03_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID + .S03_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA + .S03_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP + .S03_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST + .S03_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID + .S03_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY + // + .M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK + .M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN + .M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID + .M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR + .M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN + .M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE + .M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST + .M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK + .M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE + .M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT + .M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS + .M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID + .M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY + .M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA + .M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB + .M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST + .M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID + .M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY + .M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID + .M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP + .M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID + .M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY + .M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID + .M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR + .M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN + .M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE + .M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST + .M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK + .M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE + .M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT + .M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS + .M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID + .M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY + .M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID + .M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA + .M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP + .M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST + .M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID + .M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY + ); + + //--------------------------------------------------- + // MIG + //--------------------------------------------------- + ddr3_32bit ddr_mig_i ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (init_calib_complete), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 150MHz clock out + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + + // Slave Interface Write Address Ports + .s_axi_awid (mig_axi_wr.addr.id), + .s_axi_awaddr (mig_axi_wr.addr.addr), + .s_axi_awlen (mig_axi_wr.addr.len), + .s_axi_awsize (mig_axi_wr.addr.size), + .s_axi_awburst (mig_axi_wr.addr.burst), + .s_axi_awlock (mig_axi_wr.addr.lock), + .s_axi_awcache (mig_axi_wr.addr.cache), + .s_axi_awprot (mig_axi_wr.addr.prot), + .s_axi_awqos (mig_axi_wr.addr.qos), + .s_axi_awvalid (mig_axi_wr.addr.valid), + .s_axi_awready (mig_axi_wr.addr.ready), + // Slave Interface Write Data Ports + .s_axi_wdata (mig_axi_wr.data.data), + .s_axi_wstrb (mig_axi_wr.data.strb), + .s_axi_wlast (mig_axi_wr.data.last), + .s_axi_wvalid (mig_axi_wr.data.valid), + .s_axi_wready (mig_axi_wr.data.ready), + // Slave Interface Write Response Ports + .s_axi_bid (mig_axi_wr.resp.id), + .s_axi_bresp (mig_axi_wr.resp.resp), + .s_axi_bvalid (mig_axi_wr.resp.valid), + .s_axi_bready (mig_axi_wr.resp.ready), + // Slave Interface Read Address Ports + .s_axi_arid (mig_axi_rd.addr.id), + .s_axi_araddr (mig_axi_rd.addr.addr), + .s_axi_arlen (mig_axi_rd.addr.len), + .s_axi_arsize (mig_axi_rd.addr.size), + .s_axi_arburst (mig_axi_rd.addr.burst), + .s_axi_arlock (mig_axi_rd.addr.lock), + .s_axi_arcache (mig_axi_rd.addr.cache), + .s_axi_arprot (mig_axi_rd.addr.prot), + .s_axi_arqos (mig_axi_rd.addr.qos), + .s_axi_arvalid (mig_axi_rd.addr.valid), + .s_axi_arready (mig_axi_rd.addr.ready), + // Slave Interface Read Data Ports + .s_axi_rid (mig_axi_rd.data.id), + .s_axi_rdata (mig_axi_rd.data.data), + .s_axi_rresp (mig_axi_rd.data.resp), + .s_axi_rlast (mig_axi_rd.data.last), + .s_axi_rvalid (mig_axi_rd.data.valid), + .s_axi_rready (mig_axi_rd.data.ready), + // System Clock Ports + .sys_clk_p (sys_clk_p), // From external 100MHz source. + .sys_clk_n (sys_clk_n), // From external 100MHz source. + .clk_ref_i (bus_clk), + .sys_rst (sys_rst_n) // IJB. Poorly named active low. Should change RST_ACT_LOW. + ); + + //--------------------------------------------------- + // DDR3 SDRAM Models + //--------------------------------------------------- + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i0 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[1:0]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[15:0]), + .dqs (ddr3_dqs_p[1:0]), + .dqs_n (ddr3_dqs_n[1:0]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i1 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[3:2]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[31:16]), + .dqs (ddr3_dqs_p[3:2]), + .dqs_n (ddr3_dqs_n[3:2]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv new file mode 100644 index 000000000..2979aefb7 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo/dram_fifo_tb.sv @@ -0,0 +1,163 @@ +// +// Copyright 2016 Ettus Research +// + + +`timescale 1ns/1ps +`define SIM_TIMEOUT_US 120 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 7 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module dram_fifo_tb(); + `TEST_BENCH_INIT("dram_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/200, 50) //200MHz bus_clk + `DEFINE_CLK(dma_engine_clk, 1000.0/305.0, 50) //305MHz dma_engine_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET_N(sys_rst_n, 0, 100) //100ns for GSR to deassert + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master chdr_i (.clk(bus_clk)); + cvita_slave chdr_o (.clk(bus_clk)); + + // Initialize DUT + wire calib_complete; + + axis_dram_fifo_single dut_single ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk_p(sys_clk_p),//use differential clock on N310 + .sys_clk_n(sys_clk_n), + .sys_rst_n(sys_rst_n), + .dma_engine_clk(dma_engine_clk), + + .i_tdata(chdr_i.axis.tdata), + .i_tlast(chdr_i.axis.tlast), + .i_tvalid(chdr_i.axis.tvalid), + .i_tready(chdr_i.axis.tready), + + .o_tdata(chdr_o.axis.tdata), + .o_tlast(chdr_o.axis.tlast), + .o_tvalid(chdr_o.axis.tvalid), + .o_tready(chdr_o.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(), + + .forced_bit_err(64'h0), + .init_calib_complete(calib_complete) + ); + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (~sys_rst_n) @(posedge sys_clk_p); + `TEST_CASE_DONE((~bus_rst & sys_rst_n)); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + chdr_i.push_ramp_pkt(16, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",16,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==16, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + chdr_i.push_ramp_pkt(1024, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",1024,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==1024, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + fork + begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + chdr_o.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + i = 0; + repeat (20) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + fork + begin + repeat (10) begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + repeat (30) @(posedge bus_clk); + end + end + begin + repeat (10) begin + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + i = 0; + repeat (20) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + end + end + join + `TEST_CASE_DONE(1); + + `TEST_BENCH_DONE; + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile new file mode 100644 index 000000000..49e673dc4 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/Makefile @@ -0,0 +1,70 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_4x64_256_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_SRCS) \ +$(IP_AXI_INTERCON_4X64_256_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_bist_tb + +SIM_SRCS = \ +$(abspath dram_fifo_bist_tb.sv) \ +$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv new file mode 100644 index 000000000..96a60de6e --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/dram_fifo_bist_tb.sv @@ -0,0 +1,348 @@ +// +// Copyright 2015 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define SIM_RUNTIME_US 3000 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 8 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module dram_fifo_bist_tb(); + `TEST_BENCH_INIT("dram_fifo_bist_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/200, 50) //200MHz bus_clk + `DEFINE_CLK(dma_engine_clk, 1000/300, 50) //300MHz dma_engine_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET_N(sys_rst_n, 0, 100) //100ns for GSR to deassert + + localparam EXTENDED_TEST = 0; + + // Initialize DUT + wire calib_complete; + wire running, done; + wire [1:0] error; + wire [31:0] rb_data; + reg [63:0] forced_bit_err; + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master cvita_fifo_in (.clk(bus_clk)); + cvita_slave cvita_fifo_out (.clk(bus_clk)); + + // AXI DRAM FIFO Topology (Inline production BIST for DRAM FIFO): + // + // User Data ====> |---------| |---------------| |-----------| ====> User Data Out + // | AXI MUX | ====> | AXI DRAM FIFO | ====> | AXI DEMUX | + // BIST Data ====> |---------| |---------------| |-----------| ====> BIST Data Out + // || + // |--------------| + // | MIG (D/S)RAM | + // |--------------| + + localparam SR_FIFO_BASE = 0; + localparam SR_BIST_BASE = SR_FIFO_BASE + 4; + + axis_dram_fifo_single dut_single ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk_p(sys_clk_p),//use differential clock on N310 + .sys_clk_n(sys_clk_n), + .sys_rst_n(sys_rst_n), + .dma_engine_clk(dma_engine_clk), + + .i_tdata(cvita_fifo_in.axis.tdata), + .i_tlast(cvita_fifo_in.axis.tlast), + .i_tvalid(cvita_fifo_in.axis.tvalid), + .i_tready(cvita_fifo_in.axis.tready), + + .o_tdata(cvita_fifo_out.axis.tdata), + .o_tlast(cvita_fifo_out.axis.tlast), + .o_tvalid(cvita_fifo_out.axis.tvalid), + .o_tready(cvita_fifo_out.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(rb_data), + + .forced_bit_err(forced_bit_err), + .init_calib_complete(calib_complete) + ); + + assign {error, done, running} = rb_data[3:0]; + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + integer single_run_time; + integer xfer_cnt, cyc_cnt; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (~sys_rst_n) @(posedge sys_clk_p); + `TEST_CASE_DONE(~bus_rst & sys_rst_n); + + forced_bit_err <= 64'h0; + repeat (200) @(posedge sys_clk_p); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + //Select BIST status as the readback output + tst_set.write(SR_FIFO_BASE + 0, 3'd1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + cvita_fifo_in.push_ramp_pkt(100, 64'd0, 64'h100, header); + cvita_fifo_out.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",100,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==100, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + i = 0; + repeat (100) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 10 x 40byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd40, 18'd10}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... again (should fail)"); + forced_bit_err <= 64'h8000000000000000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + forced_bit_err <= 64'h0; + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... and again (should pass)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + if (EXTENDED_TEST) begin // Extended test mode + `TEST_CASE_START("Setup BIST: 8000 x 40byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd40, 18'd8000}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 256 x 1000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd4, 16'd256}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd1000, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("User Data: Concurrent read and write"); + cvita_fifo_out.axis.tready = 1; + fork + begin + cvita_fifo_in.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + cvita_fifo_out.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 256 x 600byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd600, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 30 x 8000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd8000, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 100 x 8000byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd8000, 18'd100}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 10 x 256byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'hFFFFFFFF); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd256, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous (Early interrupt)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + single_run_time = $time - curr_time; + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #2000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + fork + begin + `TEST_CASE_START("Run BIST Continuous (Force error)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then force error + #10000; + forced_bit_err <= 64'h1; + end + join + //Recover from failure + forced_bit_err <= 64'h0; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + repeat (2000) @(posedge bus_clk); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `ASSERT_ERROR((($time - curr_time) > 2 * single_run_time), "Continuous test most likely stopped early!"); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #100000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + end + + `TEST_BENCH_DONE; + + end +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile new file mode 100644 index 000000000..77c7c58c5 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/Makefile @@ -0,0 +1,78 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/simple_gemac/Makefile.srcs +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(SIMPLE_GEMAC_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +#include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_ONE_GIGE_PHY_XCI_SRCS) \ +$(ONE_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs +include $(BASE_DIR)/../sim/control/Makefile.srcs +include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = one_gig_eth_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath one_gig_eth_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v new file mode 100644 index 000000000..cd24e14a8 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/demo_one_gig_pcs_pma_mdio.v @@ -0,0 +1,489 @@ +//------------------------------------------------------------------------------ +// File : demo_tb.v +// Author : Xilinx Inc. +//------------------------------------------------------------------------------ +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//------------------------------------------------------------------------------ +// Description: This testbench will exercise the ports of the Ethernet +// 1000BASE-X PCS/PMA core's example design to perform the following +// operations: +// +//---------------- +// Configuration +//---------------- +// The core will be reset, then Auto-Negotiation (if present) will +// be disabled and and the core will be taken out of the Isolate +// state. +// +//---------------- +// Transmitter +//---------------- +// Four frames are generated by the Tx Stimulus and pushed into the +// GMII transmitter. +// +// The PHY side transmitter interface data is captured, 8B10B decoded +// and the Tx Monitor checks that the captured data matches that +// injected. +// +//---------------- +// Receiver +//---------------- +// Four frames are generated by the Rx Stimulus, 8B10B encoded and +// pushed into the PHY side receiver interface. +// +// The GMII side receiver interface data is captured and the +// Rx Monitor checks that the captured data matches that injected. +// +// +//---------------------------------------------------------------------- +// Demonstration Test Fixture | +// | +// | +// -------------------------- | +// | Example Design | | +// | (DUT) | | +// | | | +// | | | +// | | | +// Tx | | 8B10B decode, Tx | +// Generate -------> --------> Monitor | +// Frames | | Frames | +// |GMII PHY | | +// | I/F I/F | | +// | | | +// | | | +// | | | +// Rx | | 8B10B encode, Rx | +// Monitor <-------- <-------- Generate | +// Frames | | Frames | +// | | | +// ------------^------------- | +// | | +// | | +// Stimulate | +// MDIO I/F | +// (if present) | +// | +//---------------------------------------------------------------------- + +`timescale 1 ps/1 ps + + +// To use this testbench copy it over the demo_tb.v in the example testbench +// provided by xilinx + +// This module is a modified version of the demonstration testbench provided +// by Xilinx. It has the mdio_master along with the one_gig dut. +// It uses the configuration vector to control the phy +// Can be used to debug mdio_master +module demo_tb; + + + //---------------------------------------------------------------------------- + // Stimulus - Management Frame data + //---------------------------------------------------------------------------- + // Create management frame + reg [0:63] mdio_data; + + initial + begin + + mdio_data[0:31] = 32'hffffffff; // preamble field + mdio_data[32:33] = 2'h1; // start opcode + mdio_data[34:35] = 2'h1; // write opcode + mdio_data[36:40] = 5'd1; // phyad (write to this device) + mdio_data[41:45] = 5'h0; // regad (write to Configuration Register) + mdio_data[46:47] = 2'h2; // Turn-around cycles + + // DATA FIELD + + mdio_data[48] = 1'b0; // Do not assert Reset + mdio_data[49] = 1'b0; // No loopback + mdio_data[50] = 1'b0; // Speed selection + mdio_data[51] = 1'b0; // Disable Auto-Negotiation + mdio_data[52] = 1'b0; // Disable Power Down + mdio_data[53] = 1'b0; // Disable Isolate GMII + mdio_data[54] = 1'b0; // Disable Auto-Negotiation Restart + mdio_data[55] = 1'b1; // Full Duplex Mode + mdio_data[56] = 1'b0; // Disable Collision Test + mdio_data[57] = 1'b0; // Speed selection + mdio_data[58:63] = 6'h0; // Reserved + + end + + + + //---------------------------------------------------------------------------- + // testbench signals + //---------------------------------------------------------------------------- + + // testbench control semaphores + reg configuration_finished; + wire tx_monitor_finished; + wire rx_monitor_finished; + wire simulation_finished; + + + //---------------------------------------------------------------------------- + // DUT signals + //---------------------------------------------------------------------------- + + // An independent clock source used as the reference clock for an + // IDELAYCTRL (if present) and for the main GT transceiver reset logic. + // This example design assumes that this is of frequency 200MHz. + reg independent_clock; + + // System Reset + reg reset; + + // Transceiver Interface + //---------------------- + reg gtrefclk_p; + reg gtrefclk_n; + wire rxuserclk2; + wire txp; + wire txn; + wire rxp; + wire rxn; + + // GMII Interface + //--------------- + wire gmii_tx_clk; + wire gmii_rx_clk; + wire [7:0] gmii_txd; + wire gmii_tx_en; + wire gmii_tx_er; + wire [7:0] gmii_rxd; + wire gmii_rx_dv; + wire gmii_rx_er; + + // Management: MDIO Interface + //--------------------------- + wire mdc; + wire mdio_i; + wire mdio_o; + wire mdio_t; + reg [4:0] configuration_vector; + reg configuration_valid; + wire signal_detect; + wire [15:0] status_vector; + + parameter [13:0] REG_BASE = 14'h0; + parameter REG_DWIDTH = 32; + parameter REG_AWIDTH = 14; + + reg reg_wr_req; + reg [REG_AWIDTH-1:0] reg_wr_addr; + reg [31:0] reg_wr_data; + reg reg_rd_req; + reg [REG_AWIDTH-1:0] reg_rd_addr; + wire reg_rd_resp; + wire [31:0] reg_rd_data; + + //---------------------------------------------------------------------------- + // Create clock sources + //---------------------------------------------------------------------------- + + // An independent clock source used as the reference clock for an + // IDELAYCTRL (if present) and for the main GT transceiver reset logic. + // This testbench uses the frequency of 200MHz. + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2500; + independent_clock <= 1'b1; + #2500; + end + end + + + + // Create the transceiver Reference clock (125 MHz) + initial + begin + gtrefclk_p <= 1'b0; + gtrefclk_n <= 1'b1; + forever + begin + gtrefclk_p <= 1'b0; + gtrefclk_n <= 1'b1; + #4000; + gtrefclk_p <= 1'b1; + gtrefclk_n <= 1'b0; + #4000; + end + end + + // MDIO Master + mdio_master #( + .REG_BASE (REG_BASE + 32'h10), + .REG_AWIDTH (REG_AWIDTH), + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (independent_clock), + .rst (reset), + .mdc (mdc), + .mdio_in (mdio_o), + .mdio_out (mdio_i), + .mdio_tri (mdio_t), + .reg_wr_req (reg_wr_req), + .reg_wr_addr(reg_wr_addr), + .reg_wr_data(reg_wr_data), + .reg_rd_req (reg_rd_req), + .reg_rd_addr(reg_rd_addr), + .reg_rd_data(reg_rd_data), + .reg_rd_resp(reg_rd_resp) + ); + + //---------------------------------------------------------------------------- + // Wire up Device Under Test + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_example_design dut + ( + .independent_clock (independent_clock), + .gtrefclk_p (gtrefclk_p), + .gtrefclk_n (gtrefclk_n), + .rxuserclk2 (rxuserclk2), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .gmii_tx_clk (gmii_tx_clk), + .gmii_rx_clk (gmii_rx_clk), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect) + ); + + + + //---------------------------------------------------------------------------- + // Instantiate a Stimulus module for the core + //---------------------------------------------------------------------------- + stimulus_tb stimulus + ( + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + + .gmii_tx_clk (gmii_tx_clk), + .gmii_rx_clk (gmii_rx_clk), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd), + .gmii_rx_dv (gmii_rx_dv), + .gmii_rx_er (gmii_rx_er), + + .configuration_finished (configuration_finished), + .tx_monitor_finished (tx_monitor_finished), + .rx_monitor_finished (rx_monitor_finished) + ); + + + + //---------------------------------------------------------------------------- + // Simulate that PMD sublayer has detected and optical input. + //---------------------------------------------------------------------------- + assign signal_detect = 1'b1; + + + + + //---------------------------------------------------------------------------- + // Set the PHYAD for the core + //---------------------------------------------------------------------------- + + + //---------------------------------------------------------------------------- + // Configuration process. This process will reset the core, then write + // to configuration register 0 to turn off autonegotiation and take + // the core out of the isolate state. + //---------------------------------------------------------------------------- + + // drives MDC at 2.5 MHz + //initial + //begin + // mdc <= 1'b0; + // forever + // begin + // mdc <= 1'b0; + // #200000; + // mdc <= 1'b1; + // #200000; + // end + //end + + + // Main configuration process + initial + begin : p_configuration + integer MDIO_BIT; // Bit counter within MDIO frame + + $display("** Note: Timing checks are not valid"); + + configuration_finished <= 0; + configuration_vector <= 5'b00000; + // Not doing any MDIO write, so configure the Register 0 using + // Configuration Vector + configuration_valid <= 1'b1; + //mdio_i <= 1'b1; + + // reset the core + $display("Resetting core..."); + reset <= 1'b1; + #1000000 + @(posedge gtrefclk_p) + reset <= 1'b0; + // wait for core to obtain synchronisation + + #2000000000 + #1000000000 + + #250000000 + + // Write to PCS Management configuration register 0. + $display("Writing to Control Register in PCS sublayer...."); + + // Write REG_MDIO_OP to Read MDIO Phy Addr 1, Reg Addr 1 + @(posedge independent_clock) + reg_wr_addr <= 14'h18; + reg_wr_data <= 16'h822; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + + // Write REG_MDIO_CTRL_STATUS to turn on mdio_running + @(posedge independent_clock) + reg_wr_addr <= 14'h1c; + reg_wr_data <= 32'h1; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + + // Write REG_MDIO_OP to Read MDIO Phy Addr 1, Reg Addr 0 + @(posedge independent_clock) + reg_wr_addr <= 14'h18; + reg_wr_data <= 32'h820; + reg_wr_req <= 1'b1; + @(posedge independent_clock) + reg_wr_req <= 1'b0; + #4000000 + //@(negedge mdc) // centre MDIO around MDC rising edge + + //MDIO_BIT = 0; + + //// transmit serial management frame + //while(MDIO_BIT !== 64) + //begin + // @(negedge mdc); + // mdio_i <= mdio_data[MDIO_BIT]; + // MDIO_BIT = MDIO_BIT + 1; + //end + + //@(negedge mdc) + //mdio_i <= 1'b1; // simulate tri-state with pullup + #10000000 + // wait for core to obtain synchronisation + wait (status_vector[1] == 1); + #8000000 + + configuration_finished <= 1; + end // p_configuration + + + + //---------------------------------------------------------------------------- + // End the simulation. + //---------------------------------------------------------------------------- + + assign simulation_finished = tx_monitor_finished & rx_monitor_finished; + + + initial + begin : p_end_simulation + fork: sim_in_progress + @(posedge simulation_finished) disable sim_in_progress; + #2000000000 + #2000000000 + #500000000 + disable sim_in_progress; + + join + if (simulation_finished) begin + #1000000 + $display("Test completed successfully"); + $display("Simulation Complete."); + end + else + $display("** Error: Testbench timed out"); + $stop; + end // p_end_simulation + + +endmodule + diff --git a/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv new file mode 100644 index 000000000..759ea2872 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv @@ -0,0 +1,381 @@ +// +// Copyright 2016 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module one_gig_eth_loopback_tb(); + `TEST_BENCH_INIT("one_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(ETH_CLK_P, 1000/125, 50) //125MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire ETH_CLK_N = ~ETH_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // One_gigE Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | gigE MAC | <===> | gigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | gigE MAC | <===> | gigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire gige_refclk, gige_refclk_bufg; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + wire [7:0] m_gmii_txd, m_gmii_rxd; + wire m_gmii_tx_en, m_gmii_tx_er, m_gmii_rx_dv, m_gmii_rx_er; + wire m_gmii_clk; + wire [7:0] s_gmii_txd, s_gmii_rxd; + wire s_gmii_tx_en, s_gmii_tx_er, s_gmii_rx_dv, s_gmii_rx_er; + wire s_gmii_clk; + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire loop_tlast, loop_tvalid, loop_tready; + + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = gmii_clk; + //assign s_user_clk = gmii_clk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + wire gt0_qplloutclk, gt0_qplloutrefclk, pma_reset; + + one_gige_phy_clk_gen gige_clk_gen_i ( + .areset(GSR), + .refclk_p(ETH_CLK_P), + .refclk_n(ETH_CLK_N), + .refclk(gige_refclk), + .refclk_bufg(gige_refclk_bufg) + ); + + cvita_master m_tx_chdr (.clk(m_user_clk)); + cvita_slave s_rx_chdr (.clk(s_user_clk)); + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #0.5; + independent_clock <= 1'b1; + #0.5; + end + end + + //----------------------------------------------------------------- + // MDIO Master + //----------------------------------------------------------------- + wire mdc, mdio_m2s, mdio_s2m; + + mdio_master #( + .MDC_DIVIDER (8'd200) + ) mdio_master_i ( + .clk (m_user_clk), + .rst (GSR), + .mdc (mdc), + .mdio_in (mdio_s2m), + .mdio_out (mdio_m2s), + .mdio_tri (), + .reg_wr_req (/*reg_wr_req*/), + .reg_wr_addr(/*reg_wr_addr*/), + .reg_wr_data(/*reg_wr_data*/), + .reg_rd_req (/*reg_rd_req*/), + .reg_rd_addr(/*reg_rd_addr*/), + .reg_rd_data(/*reg_rd_data*/), + .reg_rd_resp(/*reg_rd_resp*/) + ); + + //GT COMMON + one_gig_eth_pcs_pma_gt_common core_gt_common_i + ( + .GTREFCLK0_IN (gige_refclk) , + .QPLLLOCK_OUT (), + .QPLLLOCKDETCLK_IN (independent_clock), + .QPLLOUTCLK_OUT (gt0_qplloutclk), + .QPLLOUTREFCLK_OUT (gt0_qplloutrefclk), + .QPLLREFCLKLOST_OUT (), + .QPLLRESET_IN (pma_reset) + ); + + one_gige_phy one_gige_phy_master_i + ( + .reset(GSR), // Asynchronous reset for entire core. + .independent_clock(independent_clock), + .pma_reset_out(pma_reset), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gige_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gige_refclk_bufg), // Reference clock routed through a BUFG + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(m_gmii_clk), // Clock to client MAC. + .gmii_txd(m_gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(m_gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(m_gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(m_gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(m_gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(m_gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(m_phy_status), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_master_i + ( + .clk125(m_gmii_clk), + .reset(GSR), + + .GMII_GTX_CLK(), + .GMII_TX_EN(m_gmii_tx_en), + .GMII_TX_ER(m_gmii_tx_er), + .GMII_TXD(m_gmii_txd), + .GMII_RX_CLK(m_gmii_clk), + .GMII_RX_DV(m_gmii_rx_dv), + .GMII_RX_ER(m_gmii_rx_er), + .GMII_RXD(m_gmii_rxd), + + .sys_clk(m_user_clk), + .rx_tdata(s_rx_chdr.axis.tdata), + .rx_tuser(/*s_rx_chdr.axis.tuser*/), + .rx_tlast(s_rx_chdr.axis.tlast), + .rx_tvalid(s_rx_chdr.axis.tvalid), + .rx_tready(s_rx_chdr.axis.tready), + .tx_tdata(m_tx_chdr.axis.tdata), + .tx_tuser(/*m_tx_chdr.axis_tuser*/), + .tx_tlast(m_tx_chdr.axis.tlast), + .tx_tvalid(m_tx_chdr.axis.tvalid), + .tx_tready(m_tx_chdr.axis.tready), + // Debug + .debug_tx(), .debug_rx() + ); + + one_gige_phy one_gige_phy_slave_i + ( + .reset(GSR), // Asynchronous reset for entire core. + .independent_clock(independent_clock), + .pma_reset_out(), + .gt0_qplloutclk_in(gt0_qplloutclk), + .gt0_qplloutrefclk_in(gt0_qplloutrefclk), + // Tranceiver Interface + .gtrefclk(gige_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gige_refclk_bufg), // Reference clock routed through a BUFG + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(s_gmii_clk), // Clock to client MAC. + .gmii_txd(s_gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(s_gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(s_gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(s_gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(s_gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(s_gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_m2s), // Management Data In + .mdio_o(mdio_s2m), // Management Data Out + .mdio_t(), // Management Data Tristate + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(s_phy_status), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_slave_i + ( + .clk125(s_gmii_clk), + .reset(GSR), + + .GMII_GTX_CLK(), + .GMII_TX_EN(s_gmii_tx_en), + .GMII_TX_ER(s_gmii_tx_er), + .GMII_TXD(s_gmii_txd), + .GMII_RX_CLK(s_gmii_clk), + .GMII_RX_DV(s_gmii_rx_dv), + .GMII_RX_ER(s_gmii_rx_er), + .GMII_RXD(s_gmii_rxd), + + .sys_clk(s_user_clk), + .rx_tdata(loop_tdata), + .rx_tuser(), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(), + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Debug + .debug_tx(), .debug_rx() + ); + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + while (GSR) @(posedge ETH_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_tx_chdr.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + // `TEST_CASE_START("Run PRBS15 BIST"); + // s_bist_loopback <= PACKET_MODE; + // @(posedge m_user_clk); + // m_bist_gen <= 1'b1; + // m_bist_check <= 1'b1; + // @(posedge m_user_clk); + // while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + // repeat (512) @(posedge m_user_clk); + // `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + // `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + // @(posedge m_user_clk); + // m_bist_gen <= 1'b0; + // repeat (256) @(posedge m_user_clk); + // m_bist_check <= 1'b0; + // `TEST_CASE_DONE(1'b1); + + repeat(1000) @(posedge m_user_clk); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + s_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header); + end + begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + s_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + //s_bist_loopback <= 1'b1; + + //`TEST_CASE_START("Run PRBS15 BIST (Loopback Mode)"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b1; + //m_bist_rate <= 5'd4; + //m_bist_check <= 1'b1; + //@(posedge m_user_clk); + //while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + //repeat (512) @(posedge m_user_clk); + //`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + //`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b0; + //repeat (256) @(posedge m_user_clk); + //m_bist_check <= 1'b0; + //`TEST_CASE_DONE(1'b1); + + //s_bist_loopback <= 1'b0; + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + end + +endmodule diff --git a/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile new file mode 100644 index 000000000..c1271a40b --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/Makefile @@ -0,0 +1,84 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynq +PART_ID = xc7z100/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs +include $(BASE_DIR)/../lib/xge/Makefile.srcs +include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(XGE_SRCS) \ +$(XGE_INTERFACE_SRCS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) \ +$(IP_TEN_GIGE_PHY_XCI_SRCS) \ +$(TEN_GIGE_PHY_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(PACKET_PROC_SRCS) \ +) +#$(IP_FIFO_SHORT_2CLK_SRCS) \ + + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +#include $(BASE_DIR)/../sim/general/Makefile.srcs +#include $(BASE_DIR)/../sim/control/Makefile.srcs +#include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = ten_gig_eth_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 30000 + +SIM_SRCS = \ +$(abspath ten_gig_eth_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv new file mode 100644 index 000000000..b0233a339 --- /dev/null +++ b/fpga/usrp3/top/n3xx/sim/ten_gig_eth_loopback/ten_gig_eth_loopback_tb.sv @@ -0,0 +1,527 @@ +// +// Copyright 2016 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axis_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module ten_gig_eth_loopback_tb(); + `TEST_BENCH_INIT("ten_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + //localparam PACKET_MODE = 0; + localparam PORTNUM = 8'd0; + + // Ten_gigE Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | XgigE MAC | <===> | XgigE PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire xgige_refclk, xgige_clk156, xgige_dclk; + wire m_user_clk, s_user_clk; + wire m_channel_up, s_channel_up; + + wire [63:0] m_xgmii_txd; + wire [7:0] m_xgmii_txc; + wire [63:0] m_xgmii_rxd; + wire [7:0] m_xgmii_rxc; + wire [63:0] s_xgmii_txd; + wire [7:0] s_xgmii_txc; + wire [63:0] s_xgmii_rxd; + wire [7:0] s_xgmii_rxc; + wire [7:0] m_xgmii_status; + wire [7:0] s_xgmii_status; + wire m_xge_phy_resetdone; + wire s_xge_phy_resetdone; + wire m_mdc, m_mdio_in, m_mdio_out; + wire s_mdc, s_mdio_in, s_mdio_out; + wire sfpp_rxlos,sfpp_tx_fault,sfpp_tx_disable; + + + wire [15:0] m_phy_status; + wire [15:0] s_phy_status; + wire [63:0] loop_tdata; + wire [3:0] loop_tuser; + wire loop_tlast, loop_tvalid, loop_tready; + + wire [7:0] wb_adr_i; + wire wb_cyc_i; + wire [31:0] wb_dat_i; + wire wb_stb_i; + wire wb_we_i; + wire wb_ack_o; + wire [31:0] wb_dat_o; + wire wb_int_o; + //`ifdef USE_ARM_FRAMER + //wire [63:0] c2e_tdata_int; + //wire [3:0] c2e_tuser_int; + //wire c2e_tlast_int; + //wire c2e_tvalid_int; + //wire c2e_tready_int; + //wire [63:0] c2e_tdata; + //wire [3:0] c2e_tuser; + //wire c2e_tlast; + //wire c2e_tvalid; + //wire c2e_tready; + //`endif + + reg independent_clock; + assign m_channel_up = m_phy_status[0]; + assign s_channel_up = s_phy_status[0]; + //assign m_user_clk = xgige_refclk; + //assign s_user_clk = xgige_refclk; + assign m_user_clk = independent_clock; + assign s_user_clk = independent_clock; + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .areset(GSR), + .refclk_p(XG_CLK_P), + .refclk_n(XG_CLK_N), + .refclk(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + + cvita_master m_tx_chdr (.clk(m_user_clk)); + cvita_slave s_rx_chdr (.clk(s_user_clk)); + // Use this to send axi-stream with arm_framer + //`ifdef USE_ARM_FRAMER + //axis_master #(.DWIDTH(68)) m_axis (.clk(m_user_clk)); + //axis_slave #(.DWIDTH(68)) s_axis (.clk(s_user_clk)); + //`endif + initial + begin + independent_clock <= 1'b0; + forever + begin + independent_clock <= 1'b0; + #2.5; + independent_clock <= 1'b1; + #2.5; + end + end + + assign sfpp_rxlos = 1'b0; + assign sfpp_tx_fault = 1'b0; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware + ten_gig_eth_pcs_pma_gt_common_block + ( + .refclk(xgige_refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .qpllrefclksel(3'b001 /*3'b101*GTSOUTHREFCLK0*/) + ); + + ten_gige_phy ten_gige_phy_master_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(m_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(m_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(m_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(m_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN0_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN0_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN1_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN1_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(m_mdc), // Management Data Clock + .mdio_in(m_mdio_in), // Management Data In + .mdio_out(m_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(m_xgmii_status), // Core status + .resetdone(m_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset1), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_master_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(m_xgmii_txd), + .xgmii_txc(m_xgmii_txc), + .xgmii_rxd(m_xgmii_rxd), + .xgmii_rxc(m_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(m_user_clk), + .sys_rst(GSR), + //`ifdef USE_ARM_FRAMER + //.rx_tdata(s_axis.axis.tdata[63:0]), + //.rx_tuser(s_axis.axis.tdata[67:64]), + //.rx_tlast(s_axis.axis.tlast), + //.rx_tvalid(s_axis.axis.tvalid), + //.rx_tready(/*s_axis.axis.tready*/1'b1), + //.tx_tdata(c2e_tdata), + //.tx_tuser(c2e_tuser), + //.tx_tlast(c2e_tlast), + //.tx_tvalid(c2e_tvalid), + //.tx_tready(c2e_tready), + //`endif + .rx_tdata(s_rx_chdr.axis.tdata), + .rx_tuser(), + .rx_tlast(s_rx_chdr.axis.tlast), + .rx_tvalid(s_rx_chdr.axis.tvalid), + .rx_tready(s_rx_chdr.axis.tready), + .tx_tdata(m_tx_chdr.axis.tdata), + .tx_tuser(4'd4), // Bit[3] (error) is ignored for now. + .tx_tlast(m_tx_chdr.axis.tlast), + .tx_tvalid(m_tx_chdr.axis.tvalid), + .tx_tready(m_tx_chdr.axis.tready), + // Other + .phy_ready(m_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign m_phy_status = {8'h00, m_xgmii_status}; + + //`ifdef USE_ARM_FRAMER + // arm_framer inst_arm_framer ( + // .clk (m_user_clk), + // .reset (GSR), + // .clear (clear), + // .s_axis_tdata (m_axis.axis.tdata[63:0]), + // .s_axis_tuser (m_axis.axis.tdata[67:64]), + // .s_axis_tlast (m_axis.axis.tlast), + // .s_axis_tvalid (m_axis.axis.tvalid), + // .s_axis_tready (m_axis.axis.tready), + // .m_axis_tdata (c2e_tdata_int), + // .m_axis_tuser (c2e_tuser_int), + // .m_axis_tlast (c2e_tlast_int), + // .m_axis_tvalid (c2e_tvalid_int), + // .m_axis_tready (c2e_tready_int) + // ); + + // axi_mux4 #(.PRIO(0), .WIDTH(68)) eth_mux + // (.clk(m_user_clk), .reset(GSR), .clear(clear), + // .i0_tdata({c2e_tuser_int,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int), + // .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(), + // .i2_tdata(), .i2_tlast(), .i2_tvalid(), .i2_tready(), + // .i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), + // .o_tdata({c2e_tuser,c2e_tdata}), .o_tlast(c2e_tlast), .o_tvalid(c2e_tvalid), .o_tready(c2e_tready)); + //`endif + + ten_gige_phy ten_gige_phy_slave_i + ( + // Clocks and Reset + .areset(GSR), // Asynchronous reset for entire core. + .refclk(xgige_refclk), // Transciever reference clock: 156.25MHz + .clk156(xgige_clk156), // Globally buffered core clock: 156.25MHz + .dclk(xgige_dclk), // Management/DRP clock: 78.125MHz + .sim_speedup_control(~GSR), + // GMII Interface (client MAC <=> PCS) + .xgmii_txd(s_xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(s_xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(s_xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(s_xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(SFP_LN1_P), // Differential +ve of serial transmission from PMA to PMD. + .txn(SFP_LN1_N), // Differential -ve of serial transmission from PMA to PMD. + .rxp(SFP_LN0_P), // Differential +ve for serial reception from PMD to PMA. + .rxn(SFP_LN0_N), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(s_mdc), // Management Data Clock + .mdio_in(s_mdio_in), // Management Data In + .mdio_out(s_mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(s_xgmii_status), // Core status + .resetdone(s_xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), //FIXME // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), //FIXME + .tx_disable(/*sfpp_tx_disable*/), //FIXME + .qpllreset(qpllreset2), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + n310_xge_mac_wrapper #(.PORTNUM(PORTNUM)) xge_mac_wrapper_slave_i + ( + // XGMII + .xgmii_clk(xgige_clk156), + .xgmii_txd(s_xgmii_txd), + .xgmii_txc(s_xgmii_txc), + .xgmii_rxd(s_xgmii_rxd), + .xgmii_rxc(s_xgmii_rxc), + // Client FIFO Interfaces + .sys_clk(s_user_clk), + .sys_rst(GSR), + .rx_tdata(loop_tdata), + .rx_tuser(loop_tuser), + .rx_tlast(loop_tlast), + .rx_tvalid(loop_tvalid), + .rx_tready(loop_tready), + .tx_tdata(loop_tdata), + .tx_tuser(loop_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(loop_tlast), + .tx_tvalid(loop_tvalid), + .tx_tready(loop_tready), + // Other + .phy_ready(s_xge_phy_resetdone), + .ctrl_tx_enable (/*mac_ctrl_reg[0]*/1'b1), //FIXME: Remove hardcoded value + .status_crc_error (), + .status_fragment_error (), + .status_txdfifo_ovflow (), + .status_txdfifo_udflow (), + .status_rxdfifo_ovflow (), + .status_rxdfifo_udflow (), + .status_pause_frame_rx (), + .status_local_fault (), + .status_remote_fault () + ); + + assign s_phy_status = {8'h00, s_xgmii_status}; + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + `TEST_CASE_START("Wait for reset"); + // `ifdef USE_ARM_FRAMER + // m_axis.reset; + // `endif + while (GSR) @(posedge XG_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_tx_chdr.push_bubble(); + // `ifdef USE_ARM_FRAMER + //m_axis.push_bubble(); + // `endif + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + // `TEST_CASE_START("Run PRBS15 BIST"); + // s_bist_loopback <= PACKET_MODE; + // @(posedge m_user_clk); + // m_bist_gen <= 1'b1; + // m_bist_check <= 1'b1; + // @(posedge m_user_clk); + // while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + // repeat (512) @(posedge m_user_clk); + // `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + // `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + // @(posedge m_user_clk); + // m_bist_gen <= 1'b0; + // repeat (256) @(posedge m_user_clk); + // m_bist_check <= 1'b0; + // `TEST_CASE_DONE(1'b1); + + repeat(2000) @(posedge m_user_clk); + + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'h0000_0000_0000_ffff}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'hffff_ffff_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_0806_0001_0800}, 1'b0); + // m_axis.push_word({4'b0, 64'h0604_0001_ce20_ad1b}, 1'b0); + // m_axis.push_word({4'b0, 64'hc57a_c0a8_0a64_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_c0a8_0a0a}, 1'b1); + //`TEST_CASE_DONE(1'b1); + + // repeat(2000) @(posedge m_user_clk); + //`TEST_CASE_START("Test Ethernet packet"); + // s_axis.axis.tready = 0; + // m_axis.push_word({4'b0, 64'hffff_ffff_ffff_9aa9}, 1'b0); + // s_axis.axis.tready = 1; + // m_axis.push_word({4'b0, 64'h6400_e341_0800_4500}, 1'b0); + // m_axis.push_word({4'b0, 64'h0148_0000_0000_4011}, 1'b0); + // m_axis.push_word({4'b0, 64'h79a6_0000_0000_ffff}, 1'b0); + // m_axis.push_word({4'b0, 64'hffff_0044_0043_0134}, 1'b0); + // m_axis.push_word({4'b0, 64'h90be_0101_0600_d2ab}, 1'b0); + // m_axis.push_word({4'b0, 64'h9f01_0007_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_9aa9}, 1'b0); + // m_axis.push_word({4'b0, 64'h6400_e341_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'b0, 64'h0000_0000_0000_6382}, 1'b0); + // m_axis.push_word({4'b0, 64'h5363_3501_013d_0701}, 1'b0); + // m_axis.push_word({4'b0, 64'h9aa9_6400_e341_3902}, 1'b0); + // m_axis.push_word({4'b0, 64'h0240_3707_0103_060c}, 1'b0); + // m_axis.push_word({4'b0, 64'h0f1c_2a3c_0c75_6468}, 1'b0); + // m_axis.push_word({4'b0, 64'h6370_2031_2e32_342e}, 1'b0); + // m_axis.push_word({4'b0, 64'h31ff_0000_0000_0000}, 1'b0); + // m_axis.push_word({5'b0, 64'h0000_0000_0000_0000}, 1'b0); + // m_axis.push_word({4'd6, 64'h0000_0000_1234_0000}, 1'b1); + + //`TEST_CASE_DONE(1'b1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + s_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + s_rx_chdr.axis.tready = 1; + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID"); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + s_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header); + end + begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + s_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + s_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + //s_bist_loopback <= 1'b1; + + //`TEST_CASE_START("Run PRBS15 BIST (Loopback Mode)"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b1; + //m_bist_rate <= 5'd4; + //m_bist_check <= 1'b1; + //@(posedge m_user_clk); + //while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + //repeat (512) @(posedge m_user_clk); + //`ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + //`ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + //@(posedge m_user_clk); + //m_bist_gen <= 1'b0; + //repeat (256) @(posedge m_user_clk); + //m_bist_check <= 1'b0; + //`TEST_CASE_DONE(1'b1); + + //s_bist_loopback <= 1'b0; + + //`TEST_CASE_START("Validate no drops (master)"); + //`TEST_CASE_DONE((m_overruns === 32'd0)); + + //`TEST_CASE_START("Validate no drops (slave)"); + //`TEST_CASE_DONE((s_overruns === 32'd0)); + + end + +endmodule diff --git a/fpga/usrp3/top/python/batch-build b/fpga/usrp3/top/python/batch-build new file mode 100755 index 000000000..fcf9ac7f5 --- /dev/null +++ b/fpga/usrp3/top/python/batch-build @@ -0,0 +1,45 @@ +#!/bin/bash + +iterations=1 +directory="." +targets="" +name="" +outdir=${PWD} + +for arg in "$@"; do + if [[ $arg == "--help" ]]; then + echo "Usage: batch-build [options] targets" + echo "Options:" + echo " --runs=N [1] Build the specified targets N times" + echo " --dir= [.] Makefile directory" + echo " --name= [] Name of this batch job. Used as a prefix for build output" + echo " --help Print the message and exit" + echo "" + exit 0 + elif [[ $arg =~ "--runs="([0-9]+) ]]; then + iterations=${BASH_REMATCH[1]} + elif [[ $arg =~ "--dir="(.+) ]]; then + directory=${BASH_REMATCH[1]} + elif [[ $arg =~ "--name="(.+) ]]; then + name=${BASH_REMATCH[1]}"_" + else + targets=$targets$arg" " + fi +done + +cd $directory >/dev/null 2>&1 +if [ $? -ne 0 ]; then + echo "ERROR: Could not cd to $directory" + exit +fi + +for i in $(seq 1 $iterations); do + make $targets + if [ $? -ne 0 ]; then + echo "ERROR: Build Failed!!! Stopping batch build." + exit + fi + cp -rf build ${outdir}/${name}batch-build_$(date +'%Y-%m-%d_%H-%M-%S') + make clean +done + diff --git a/fpga/usrp3/top/python/check_inout.py b/fpga/usrp3/top/python/check_inout.py new file mode 100755 index 000000000..0e53b5c6d --- /dev/null +++ b/fpga/usrp3/top/python/check_inout.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# Description: +# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. +# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes + +import sys +import re + +if __name__=='__main__': + if len(sys.argv) == 2: + print("Usage: %s ") + sys.exit(-1) + + verilog_filename = sys.argv[1] + ucf_filename = sys.argv[2] + + verilog_file = open(verilog_filename, 'r') + ucf_file = open(ucf_filename, 'r') + + verilog_iolist = list() + ucf_iolist = list() + + #read in all input, inout, and output declarations and compile a list + for line in verilog_file: + for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): + verilog_iolist.append(match) + + for line in ucf_file: + m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) + if m is not None: + ucf_iolist.append(m.group(1)) + + #now find corresponding matches and error when you don't find one + #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem + err = False + + for item in verilog_iolist: + if item not in ucf_iolist: + print("Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item) + err = True + + if err: + sys.exit(-1) + + print("No errors found.") + sys.exit(0) diff --git a/fpga/usrp3/top/python/check_timing.py b/fpga/usrp3/top/python/check_timing.py new file mode 100644 index 000000000..4fa981ba6 --- /dev/null +++ b/fpga/usrp3/top/python/check_timing.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python +# +# Copyright 2011-2012 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +import sys +import re + +def print_timing_constraint_summary(twr_file): + output = "" + keep = False + done = False + try: open(twr_file) + except IOError: + print("cannot open or find %s; no timing summary to print!"%twr_file) + exit(-1) + for line in open(twr_file).readlines(): + if 'Derived Constraint Report' in line: keep = True + if 'constraint' in line and 'met' in line: done = True + if not keep and done: keep = True + if keep: output += line + if done: break + print(("\n\n"+output)) + +if __name__=='__main__': list(map(print_timing_constraint_summary, sys.argv[1:])) diff --git a/fpga/usrp3/top/tcl/ise_helper.tcl b/fpga/usrp3/top/tcl/ise_helper.tcl new file mode 100644 index 000000000..608cac10d --- /dev/null +++ b/fpga/usrp3/top/tcl/ise_helper.tcl @@ -0,0 +1,82 @@ +# +# Copyright 2008 Ettus Research LLC +# Copyright 2015 Ettus Research, a National Instruments Company +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +proc set_props {process options} { + if ![string compare $options ""] { + return + } + set state 1 + foreach opt $options { + if $state { + set key $opt + set state 0 + } else { + puts ">>> Setting: $process\[$key\] = $opt" + if ![string compare $process "Project"] { + project set $key $opt + } else { + project set $key $opt -process $process + } + set state 1 + } + } +} + +if [file isfile $env(ISE_FILE)] { + puts ">>> Opening project: $env(ISE_FILE)" + project open $env(ISE_FILE) +} else { + puts ">>> Creating project: $env(ISE_FILE)" + project new $env(ISE_FILE) + + ################################################## + # Set the project properties + ################################################## + set_props "Project" $env(PROJECT_PROPERTIES) + + ################################################## + # Add the sources + ################################################## + foreach source $env(SOURCES) { + puts ">>> Adding source to project: $source" + xfile add $source + } + + ################################################## + # Add the custom sources + ################################################## + foreach source $env(CUSTOM_SRCS) { + puts ">>> Adding custom source to project: $source" + xfile add $source -include_global + } + + ################################################## + # Set the top level module + ################################################## + project set top $env(TOP_MODULE) + + ################################################## + # Set the process properties + ################################################## + set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) + set_props "Translate" $env(TRANSLATE_PROPERTIES) + set_props "Map" $env(MAP_PROPERTIES) + set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) + set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) + set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) + set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) +} + +if [string compare [lindex $argv 0] ""] { + puts ">>> Running Process: [lindex $argv 0]" + process run [lindex $argv 0] +} + +project close +exit + + diff --git a/fpga/usrp3/top/x300/.gitignore b/fpga/usrp3/top/x300/.gitignore new file mode 100644 index 000000000..1b0a8a728 --- /dev/null +++ b/fpga/usrp3/top/x300/.gitignore @@ -0,0 +1,8 @@ +build +build-* +isim* +fuse* +tmp* +*.log +*.jou +*impact* diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile new file mode 100644 index 000000000..2f5e1b924 --- /dev/null +++ b/fpga/usrp3/top/x300/Makefile @@ -0,0 +1,145 @@ +# +# Copyright 2012-2016 Ettus Research LLC +# + +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP X3X0 FPGA Help +##------------------- +##Usage: +## make +## +##Output: +## build/usrp__fpga_.bit: Configuration bitstream with header +## build/usrp__fpga_.bin: Configuration bitstream without header +## build/usrp__fpga_.lvbitx: Configuration bitstream for PCIe (NI-RIO) +## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) + +# Debug Options +# Uncomment the following line to add a debug UART on GPIO 10 & 11 +#OPTIONS += DEBUG_UART=1 + +CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py + +GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) +HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) +XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS) +HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS) +XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) + +# Set build option (check RTL, run synthesis, or do a full build) +ifndef TARGET + ifdef CHECK + TARGET = rtl + else ifdef SYNTH + TARGET = synth + else + TARGET = bin + endif +endif +TOP ?= x300 + +DEFAULT_IMAGE_CORE_FILE_X300=x300_rfnoc_image_core.v +DEFAULT_IMAGE_CORE_FILE_X310=x310_rfnoc_image_core.v +DEFAULT_EDGE_FILE_X300=$(abspath x300_static_router.hex) +DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex) + +# vivado_build($1=Device, $2=Definitions) +vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1) + +# post_build($1=Device, $2=Option) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build; \ + echo "Exporting bitstream files..."; \ + cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \ + cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \ + echo "Generating LVBITX..."; \ + $(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \ + cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \ + echo "Exporting build report..."; \ + cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \ + echo "Build DONE ... $(1)_$(2)"; +else + post_build = @echo "Skipping bitfile export." +endif + +## +##Supported Targets +##----------------- +##all: X300_HG X310_HG X300_XG X310_XG (Default target) +all: X300_HG X310_HG X300_XG X310_XG + +##X310_1G: 1GigE on both SFP+ ports. +X310_1G: + $(call vivado_build,X310,$(GIGE_DEFS) X310=1) + $(call post_build,X310,1G) + +##X300_1G: 1GigE on both SFP+ ports. +X300_1G: + $(call vivado_build,X300,$(GIGE_DEFS) X300=1) + $(call post_build,X300,1G) + +##X310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +X310_HG: + $(call vivado_build,X310,$(HG_DEFS) X310=1) + $(call post_build,X310,HG) + +##X300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1. +X300_HG: + $(call vivado_build,X300,$(HG_DEFS) X300=1) + $(call post_build,X300,HG) + +##X310_XG: 10GigE on both SFP+ ports. +X310_XG: + $(call vivado_build,X310,$(XG_DEFS) X310=1) + $(call post_build,X310,XG) + +##X300_XG: 10GigE on both SFP+ ports. +X300_XG: + $(call vivado_build,X300,$(XG_DEFS) X300=1) + $(call post_build,X300,XG) + +##X310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +X310_HA: + $(call vivado_build,X310,$(HA_DEFS) X310=1) + $(call post_build,X310,HA) + +##X300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1. +X300_HA: + $(call vivado_build,X300,$(HA_DEFS) X300=1) + $(call post_build,X300,HA) + +##X310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +X310_XA: + $(call vivado_build,X310,$(XA_DEFS) X310=1) + $(call post_build,X310,XA) + +##X300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1. +X300_XA: + $(call vivado_build,X300,$(XA_DEFS) X300=1) + $(call post_build,X300,XA) + +clean: ##Clean up all target build outputs. + @echo "Cleaning targets..." + @rm -rf build-X3*_* + @rm -rf build + +cleanall: ##Clean up all target and ip build outputs. + @echo "Cleaning targets and IP..." + @rm -rf build-ip + @rm -rf build-X3*_* + @rm -rf build + +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' + +## +##Supported Options +##----------------- +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) + +.PHONY: all clean cleanall help diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc new file mode 100644 index 000000000..c297e9560 --- /dev/null +++ b/fpga/usrp3/top/x300/Makefile.x300.inc @@ -0,0 +1,133 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +BASE_DIR = $(abspath ..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/viv_design_builder.mak + +include $(IP_DIR)/Makefile.inc +include coregen_dsp/Makefile.srcs +include $(LIB_DIR)/ip/Makefile.inc +include $(LIB_DIR)/hls/Makefile.inc +include $(LIB_DIR)/control/Makefile.srcs +include $(LIB_DIR)/fifo/Makefile.srcs +include $(LIB_DIR)/simple_gemac/Makefile.srcs +include $(LIB_DIR)/timing/Makefile.srcs +include $(LIB_DIR)/zpu/Makefile.srcs +include $(LIB_DIR)/wishbone/Makefile.srcs +include $(LIB_DIR)/packet_proc/Makefile.srcs +include $(LIB_DIR)/xge/Makefile.srcs +include $(LIB_DIR)/xge_interface/Makefile.srcs +include $(LIB_DIR)/dsp/Makefile.srcs +include $(LIB_DIR)/io_port2/Makefile.srcs +include $(LIB_DIR)/axi/Makefile.srcs +include $(LIB_DIR)/io_cap_gen/Makefile.srcs +include $(LIB_DIR)/rfnoc/Makefile.srcs +# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and +# DUC, and of course the radio. Any other block needs to use the +# RFNOC_OOT_MAKEFILE_SRCS variable (see below). +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +# If out-of-tree modules want to be compiled into this image, then they need to +# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files. +# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual +# source files. +-include $(RFNOC_OOT_MAKEFILE_SRCS) + +IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE) +EDGE_FILE ?= $(DEFAULT_EDGE_FILE) + +################################################## +# Sources +################################################## +TOP_SRCS = \ +x300.v \ +x300_pcie_int.v \ +x300_core.v \ +x300_sfpp_io_core.v \ +x300_zpu_config.vhd \ +x300_eth_interface.v \ +nirio_chdr64_adapter.v \ +soft_ctrl.v \ +capture_ddrlvds.v \ +gen_ddrlvds.v \ +bus_int.v \ +x300.xdc \ +timing.xdc \ +$(IMAGE_CORE) + +ifdef BUILD_10G +SFP_SERDES_SRCS += $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.xdc) $(TEN_GIGE_PHY_SRCS) $(IP_TEN_GIGE_PHY_XCI_SRCS) +endif + +ifdef BUILD_1G +SFP_SERDES_SRCS += $(abspath x300_1ge.xdc) $(ONE_GIGE_PHY_SRCS) $(IP_ONE_GIGE_PHY_XCI_SRCS) +endif + +ifdef BUILD_AURORA +SFP_SERDES_SRCS += $(abspath x300_aurora.xdc) $(AURORA_PHY_SRCS) $(IP_AURORA_XCI_SRCS) +endif + +ifdef SFP0_10GBE +SFP_SERDES_SRCS += $(abspath x300_10ge_port0.xdc) +endif + +ifdef SFP1_10GBE +SFP_SERDES_SRCS += $(abspath x300_10ge_port1.xdc) +endif + +ifndef NO_DRAM_FIFOS +DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath x300_dram.xdc) +else +DRAM_SRCS = +endif + +DESIGN_SRCS = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \ +$(UDP_SRCS) $(EXTRAM_SRCS) \ +$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \ +$(SFP_SERDES_SRCS) $(IOPORT2_SRCS) \ +$(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \ +$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \ +$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \ +$(RFNOC_FRAMEWORK_SRCS) \ +$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \ +$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \ +$(RFNOC_OOT_SRCS) + +EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(EDGE_FILE)" + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: + +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) + +# DESIGN_SRCS and VERILOG_DEFS must be defined +bin: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(abspath ./build_x300.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID)) + +synth: .prereqs $$(DESIGN_SRCS) ip + $(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +rtl: .prereqs $$(DESIGN_SRCS) ip + $(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID)) + +.PHONY: bin rtl diff --git a/fpga/usrp3/top/x300/build_x300.tcl b/fpga/usrp3/top/x300/build_x300.tcl new file mode 100644 index 000000000..87517e3b8 --- /dev/null +++ b/fpga/usrp3/top/x300/build_x300.tcl @@ -0,0 +1,45 @@ +# +# Copyright 2014-2015 Ettus Research +# + +source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl +source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl + +# STEP#1: Create project, add sources, refresh IP +vivado_utils::initialize_project + +# STEP#2: Run synthesis +vivado_utils::synthesize_design +vivado_utils::generate_post_synth_reports + +# STEP#3: Run implementation strategy +set x3xx_strategy [dict create] +dict set x3xx_strategy "opt_design.is_enabled" 1 +dict set x3xx_strategy "opt_design.directive" "NoBramPowerOpt" +dict set x3xx_strategy "post_opt_power_opt_design.is_enabled" 0 +dict set x3xx_strategy "place_design.directive" "ExtraNetDelay_high" +dict set x3xx_strategy "post_place_power_opt_design.is_enabled" 0 +dict set x3xx_strategy "post_place_phys_opt_design.is_enabled" 1 +dict set x3xx_strategy "post_place_phys_opt_design.directive" "AggressiveExplore" +dict set x3xx_strategy "route_design.directive" "Explore" +dict set x3xx_strategy "route_design.more_options" "-tns_cleanup" +dict set x3xx_strategy "post_route_phys_opt_design.is_enabled" 1 +dict set x3xx_strategy "post_route_phys_opt_design.directive" "Explore" +vivado_strategies::implement_design $x3xx_strategy + +# STEP#4: Generate reports +vivado_utils::generate_post_route_reports + +# STEP#5: Generate a bitstream, netlist and debug probes + +# STC3 Requirement: Disable waiting for DCI Match +set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [get_designs *] +# STC3 Requirement: No bitstream compression +set_property BITSTREAM.GENERAL.COMPRESS False [get_designs *] +# Use 6MHz clock to configure bitstream +set_property BITSTREAM.CONFIG.CONFIGRATE 6 [get_designs *] + +vivado_utils::write_implementation_outputs + +# Cleanup +vivado_utils::close_batch_project diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v new file mode 100644 index 000000000..faf4f8d82 --- /dev/null +++ b/fpga/usrp3/top/x300/bus_int.v @@ -0,0 +1,901 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// Copyright 2019 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module bus_int #( + parameter NUM_RADIOS = 2, + parameter NUM_CHANNELS_PER_RADIO = 2, + parameter NUM_CHANNELS = 4 +)( + input clk, input clk_div2, input reset, input reset_div2, + output sen, output sclk, output mosi, input miso, + inout scl0, inout sda0, + inout scl1, inout sda1, + inout scl2, inout sda2, + output gps_txd, input gps_rxd, + output debug_txd, input debug_rxd, + output [1:0] leds, + output [3:0] sw_rst, + // Timekeeper + input pps, + // Block connections + input ce_clk, + input ce_rst, + // Radio Connections + input radio_clk, + input radio_rst, + input [ NUM_CHANNELS-1:0] radio_rx_stb, + input [32*NUM_CHANNELS-1:0] radio_rx_data, + output [ NUM_CHANNELS-1:0] radio_rx_running, + input [ NUM_CHANNELS-1:0] radio_tx_stb, + output [32*NUM_CHANNELS-1:0] radio_tx_data, + output [ NUM_CHANNELS-1:0] radio_tx_running, + // Daughter Board Settings Buses + output [ NUM_RADIOS-1:0] db_fe_set_stb, + output [ 8*NUM_RADIOS-1:0] db_fe_set_addr, + output [32*NUM_RADIOS-1:0] db_fe_set_data, + input [ NUM_RADIOS-1:0] db_fe_rb_stb, + output [ 8*NUM_RADIOS-1:0] db_fe_rb_addr, + input [64*NUM_RADIOS-1:0] db_fe_rb_data, + // SFP+ 0 + input SFPP0_ModAbs, input SFPP0_TxFault, input SFPP0_RxLOS, inout SFPP0_RS0, inout SFPP0_RS1, + // SFP+ 1 + input SFPP1_ModAbs, input SFPP1_TxFault, input SFPP1_RxLOS, inout SFPP1_RS0, inout SFPP1_RS1, + // Clock control and status + input [7:0] clock_status, output [7:0] clock_control, output [31:0] ref_freq, output ref_freq_changed, + // SFP+ 0 data stream + output [63:0] sfp0_tx_tdata, output [3:0] sfp0_tx_tuser, output sfp0_tx_tlast, output sfp0_tx_tvalid, input sfp0_tx_tready, + input [63:0] sfp0_rx_tdata, input [3:0] sfp0_rx_tuser, input sfp0_rx_tlast, input sfp0_rx_tvalid, output sfp0_rx_tready, + // SFP+ 1 data stream + output [63:0] sfp1_tx_tdata, output [3:0] sfp1_tx_tuser, output sfp1_tx_tlast, output sfp1_tx_tvalid, input sfp1_tx_tready, + input [63:0] sfp1_rx_tdata, input [3:0] sfp1_rx_tuser, input sfp1_rx_tlast, input sfp1_rx_tvalid, output sfp1_rx_tready, + // PCIe + output [63:0] pcio_tdata, output [2:0] pcio_tuser, output pcio_tlast, output pcio_tvalid, input pcio_tready, + input [63:0] pcii_tdata, input [2:0] pcii_tuser, input pcii_tlast, input pcii_tvalid, output pcii_tready, + //iop2 message fifos + output [63:0] o_iop2_msg_tdata, output o_iop2_msg_tvalid, output o_iop2_msg_tlast, input o_iop2_msg_tready, + input [63:0] i_iop2_msg_tdata, input i_iop2_msg_tvalid, input i_iop2_msg_tlast, output i_iop2_msg_tready, + //------------------------------------------------------------------ + // Wishbone Slave Interface(s) + //------------------------------------------------------------------ + input [31:0] sfp0_wb_dat_i, + output [31:0] sfp0_wb_dat_o, + output [15:0] sfp0_wb_adr, + output [3:0] sfp0_wb_sel, + input sfp0_wb_ack, + output sfp0_wb_stb, + output sfp0_wb_cyc, + output sfp0_wb_we, + input sfp0_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300. + + input [31:0] sfp1_wb_dat_i, + output [31:0] sfp1_wb_dat_o, + output [15:0] sfp1_wb_adr, + output [3:0] sfp1_wb_sel, + input sfp1_wb_ack, + output sfp1_wb_stb, + output sfp1_wb_cyc, + output sfp1_wb_we, + input sfp1_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300. + + input [15:0] sfp0_phy_status, + input [15:0] sfp1_phy_status, + input [31:0] xadc_readback, + + // + // AXI4 (128b@250MHz) interface to DDR3 controller + // + input ddr3_axi_clk_x2, + input ddr3_axi_rst, + // Write Address Ports + output [1*2-1:0] ddr3_axi_awid, + output [32*2-1:0] ddr3_axi_awaddr, + output [8*2-1:0] ddr3_axi_awlen, + output [3*2-1:0] ddr3_axi_awsize, + output [2*2-1:0] ddr3_axi_awburst, + output [1*2-1:0] ddr3_axi_awlock, + output [4*2-1:0] ddr3_axi_awcache, + output [3*2-1:0] ddr3_axi_awprot, + output [4*2-1:0] ddr3_axi_awqos, + output [1*2-1:0] ddr3_axi_awvalid, + input [1*2-1:0] ddr3_axi_awready, + // Write Data Ports + output [64*2-1:0] ddr3_axi_wdata, + output [8*2-1:0] ddr3_axi_wstrb, + output [1*2-1:0] ddr3_axi_wlast, + output [1*2-1:0] ddr3_axi_wvalid, + input [1*2-1:0] ddr3_axi_wready, + // Write Response Ports + output [1*2-1:0] ddr3_axi_bready, + input [1*2-1:0] ddr3_axi_bid, + input [2*2-1:0] ddr3_axi_bresp, + input [1*2-1:0] ddr3_axi_bvalid, + // Read Address Ports + output [1*2-1:0] ddr3_axi_arid, + output [32*2-1:0] ddr3_axi_araddr, + output [8*2-1:0] ddr3_axi_arlen, + output [3*2-1:0] ddr3_axi_arsize, + output [2*2-1:0] ddr3_axi_arburst, + output [1*2-1:0] ddr3_axi_arlock, + output [4*2-1:0] ddr3_axi_arcache, + output [3*2-1:0] ddr3_axi_arprot, + output [4*2-1:0] ddr3_axi_arqos, + output [1*2-1:0] ddr3_axi_arvalid, + input [1*2-1:0] ddr3_axi_arready, + // Read Data Ports + input [1*2-1:0] ddr3_axi_rid, + input [64*2-1:0] ddr3_axi_rdata, + input [2*2-1:0] ddr3_axi_rresp, + input [1*2-1:0] ddr3_axi_rlast, + input [1*2-1:0] ddr3_axi_rvalid, + output [1*2-1:0] ddr3_axi_rready, + + + // Debug + output [31:0] debug0, + output [31:0] debug1, + output [127:0] debug2); + + localparam SR_AWIDTH = 8; + localparam RB_AWIDTH = 8; + + localparam SR_LEDS = 8'd00; + localparam SR_SW_RST = 8'd01; + localparam SR_CLOCK_CTRL = 8'd02; + localparam SR_DEVICE_ID = 8'd03; + localparam SR_REF_FREQ = 8'd04; + localparam SR_SFPP_CTRL0 = 8'd08; + localparam SR_SFPP_CTRL1 = 8'd09; + localparam SR_SPI = 8'd32; + localparam SR_ETHINT0 = 8'd40; + localparam SR_ETHINT1 = 8'd56; + //localparam SR_NEXT_ADDR = 8'd72; + localparam SR_BASE_TIME = 8'd100; + + localparam RB_COUNTER = 8'd00; + localparam RB_SPI_RDY = 8'd01; + localparam RB_SPI_DATA = 8'd02; + localparam RB_CLK_STATUS = 8'd03; + localparam RB_ETH_TYPE0 = 8'd04; + localparam RB_ETH_TYPE1 = 8'd05; + localparam RB_COMPAT_NUM = 8'd06; + localparam RB_RFNOC_INFO = 8'd07; + localparam RB_SFPP_STATUS0 = 8'd08; + localparam RB_SFPP_STATUS1 = 8'd09; + localparam RB_GIT_HASH = 8'd10; + localparam RB_XADC_VALS = 8'd11; + localparam RB_NUM_TIMEKEEPERS = 8'd12; + + localparam COMPAT_MAJOR = 16'h0026; + localparam COMPAT_MINOR = 16'h0000; + localparam NUM_TIMEKEEPERS = 1; + + localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; + + wire [31:0] set_data; + wire [7:0] set_addr; + reg [31:0] rb_data; + wire [RB_AWIDTH-1:0] rb_addr; + wire rb_rd_stb; + wire set_stb; + wire spi_ready; + wire [31:0] rb_spi_data; + wire [15:0] device_id; + + wire m_ctrlport_req_wr_radio0; + wire m_ctrlport_req_rd_radio0; + wire [19:0] m_ctrlport_req_addr_radio0; + wire [31:0] m_ctrlport_req_data_radio0; + wire [3:0] m_ctrlport_req_byte_en_radio0; + wire m_ctrlport_req_has_time_radio0; + wire [63:0] m_ctrlport_req_time_radio0; + wire m_ctrlport_resp_ack_radio0; + wire [1:0] m_ctrlport_resp_status_radio0; + wire [31:0] m_ctrlport_resp_data_radio0; + wire m_ctrlport_req_wr_radio1; + wire m_ctrlport_req_rd_radio1; + wire [19:0] m_ctrlport_req_addr_radio1; + wire [31:0] m_ctrlport_req_data_radio1; + wire [3:0] m_ctrlport_req_byte_en_radio1; + wire m_ctrlport_req_has_time_radio1; + wire [63:0] m_ctrlport_req_time_radio1; + wire m_ctrlport_resp_ack_radio1; + wire [1:0] m_ctrlport_resp_status_radio1; + wire [31:0] m_ctrlport_resp_data_radio1; + + // ZPU in and ZPU out axi streams + wire [63:0] zpui_tdata, zpuo_tdata; + wire [3:0] zpui_tuser, zpuo_tuser; + wire zpui_tlast, zpuo_tlast, zpui_tvalid, zpuo_tvalid, zpui_tready, zpuo_tready; + wire [63:0] zpui0_tdata, zpuo0_tdata; + wire [3:0] zpui0_tuser, zpuo0_tuser; + wire zpui0_tlast, zpuo0_tlast, zpui0_tvalid, zpuo0_tvalid, zpui0_tready, zpuo0_tready; + wire [63:0] zpui1_tdata, zpuo1_tdata; + wire [3:0] zpui1_tuser, zpuo1_tuser; + wire zpui1_tlast, zpuo1_tlast, zpui1_tvalid, zpuo1_tvalid, zpui1_tready, zpuo1_tready; + + // v2e (vita to ethernet) and e2v (eth to vita) + wire [63:0] v2e0_tdata, v2e1_tdata, e2v0_tdata, e2v1_tdata; + wire v2e0_tlast, v2e1_tlast, v2e0_tvalid, v2e1_tvalid, v2e0_tready, v2e1_tready; + wire e2v0_tlast, e2v1_tlast, e2v0_tvalid, e2v1_tvalid, e2v0_tready, e2v1_tready; + + //settings bus for crossbar router + wire [31:0] set_data_xb; + wire [8:0] set_addr_xb; + wire set_stb_xb; + + // SFP+ logic + wire SFPP0_ModAbs_sync, SFPP0_TxFault_sync, SFPP0_RxLOS_sync; + reg SFPP0_ModAbs_reg, SFPP0_TxFault_reg, SFPP0_RxLOS_reg; + reg SFPP0_ModAbs_chgd, SFPP0_TxFault_chgd, SFPP0_RxLOS_chgd; + + wire SFPP1_ModAbs_sync, SFPP1_TxFault_sync, SFPP1_RxLOS_sync; + reg SFPP1_ModAbs_reg, SFPP1_TxFault_reg, SFPP1_RxLOS_reg; + reg SFPP1_ModAbs_chgd, SFPP1_TxFault_chgd, SFPP1_RxLOS_chgd; + + wire [15:0] sfp0_phy_status_sync, sfp1_phy_status_sync; + + //////////////////////////////////////////////////////////////////// + // Soft CPU - drives network setup, soft reset, ICMP, ... + //////////////////////////////////////////////////////////////////// + soft_ctrl #(.SB_ADDRW(SR_AWIDTH), .RB_ADDRW(RB_AWIDTH)) sc + ( + .clk(clk), .rst(reset), + .clk_div2(clk_div2), .rst_div2(reset_div2), + //------------------------------------------------------------------ + // I2C interfaces + //------------------------------------------------------------------ + .scl0(scl0), .sda0(sda0), + .scl1(scl1), .sda1(sda1), + .scl2(scl2), .sda2(sda2), + //------------------------------------------------------------------ + // UARTs for CPU comms + //------------------------------------------------------------------ + .gps_rxd(gps_rxd), .gps_txd(gps_txd), + .debug_rxd(debug_rxd), .debug_txd(debug_txd), + //------------------------------------------------------------------ + // settings bus interface + //------------------------------------------------------------------ + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data), + //------------------------------------------------------------------ + // settings bus interface for crossbar router + //------------------------------------------------------------------ + .set_stb_xb(set_stb_xb), + .set_addr_xb(set_addr_xb), + .set_data_xb(set_data_xb), + //------------------------------------------------------------------ + // readback bus interface + //------------------------------------------------------------------ + .rb_addr(rb_addr), + .rb_data(rb_data), + .rb_rd_stb(rb_rd_stb), + //------------------------------------------------------------------ + // packet interface in + //------------------------------------------------------------------ + .rx_tdata(zpui_tdata), + .rx_tuser(zpui_tuser), + .rx_tlast(zpui_tlast), + .rx_tvalid(zpui_tvalid), + .rx_tready(zpui_tready), + //------------------------------------------------------------------ + // packet interface out + //------------------------------------------------------------------ + .tx_tdata(zpuo_tdata), + .tx_tuser(zpuo_tuser), + .tx_tlast(zpuo_tlast), + .tx_tvalid(zpuo_tvalid), + .tx_tready(zpuo_tready), + //------------------------------------------------------------------ + // Wishbone Slave Interface(s) + //------------------------------------------------------------------ + .s4_dat_i(sfp0_wb_dat_i), + .s4_dat_o(sfp0_wb_dat_o), + .s4_adr(sfp0_wb_adr), + .s4_sel(sfp0_wb_sel), + .s4_ack(sfp0_wb_ack), + .s4_stb(sfp0_wb_stb), + .s4_cyc(sfp0_wb_cyc), + .s4_we(sfp0_wb_we), + .s4_int(sfp0_wb_int), + //------------------------------------------------------------------ + // IoPort2 Msg Interface + //------------------------------------------------------------------ + .o_iop2_msg_tdata(o_iop2_msg_tdata), + .o_iop2_msg_tvalid(o_iop2_msg_tvalid), + .o_iop2_msg_tlast(o_iop2_msg_tlast), + .o_iop2_msg_tready(o_iop2_msg_tready), + .i_iop2_msg_tdata(i_iop2_msg_tdata), + .i_iop2_msg_tvalid(i_iop2_msg_tvalid), + .i_iop2_msg_tlast(i_iop2_msg_tlast), + .i_iop2_msg_tready(i_iop2_msg_tready), + + .s5_dat_i(sfp1_wb_dat_i), + .s5_dat_o(sfp1_wb_dat_o), + .s5_adr(sfp1_wb_adr), + .s5_sel(sfp1_wb_sel), + .s5_ack(sfp1_wb_ack), + .s5_stb(sfp1_wb_stb), + .s5_cyc(sfp1_wb_cyc), + .s5_we(sfp1_wb_we), + .s5_int(sfp1_wb_int), + + //------------------------------------------------------------------ + // Debug + //------------------------------------------------------------------ + .debug0(debug2), + .debug1() + ); + + setting_reg #(.my_addr(SR_LEDS), .awidth(SR_AWIDTH), .width(2)) set_leds + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(leds)); + + // + // SW_RST - Bit allocation: + // [0] - PHY reset + // [1] - Radio clk domain reset + // [2] - Radio Clk PLL reset. + // [3] - ADC IdelayCtrl reset + // + setting_reg #(.my_addr(SR_SW_RST), .awidth(SR_AWIDTH), .width(4)) set_sw_rst + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(sw_rst)); + + setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(8), + .at_reset(7'b1000000) //bit 6 high means GPSDO on by default + ) set_clk_ctrl + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(clock_control)); + + setting_reg #(.my_addr(SR_DEVICE_ID), .awidth(SR_AWIDTH), .width(16), + .at_reset(32'd0) + ) set_dev_id + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(device_id), .changed()); + + setting_reg #(.my_addr(SR_REF_FREQ), .awidth(SR_AWIDTH), .width(32), + .at_reset(32'd10_000_000) //default to 10 MHz reference clock + ) set_ref_freq + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(ref_freq), .changed(ref_freq_changed)); + + simple_spi_core #(.BASE(SR_SPI), .WIDTH(1), .CLK_IDLE(0), .SEN_IDLE(1'b1)) misc_spi + (.clock(clk), .reset(reset), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(rb_spi_data), .ready(spi_ready), + .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso), + .debug()); + + reg [31:0] counter; + wire [31:0] rb_data_crossbar = 32'h0; + wire [63:0] radio_time_tb; + wire [63:0] radio_time_last_pps_tb; + wire [63:0] period_ns_q32_tb; + wire [63:0] radio_time; + wire [63:0] radio_time_last_pps; + reg [31:0] radio_time_hi; + reg [31:0] radio_time_last_pps_hi; + reg radio_time_hi_ld; + reg radio_time_last_pps_hi_ld; + + + always @(posedge clk) counter <= counter + 1; + + always @* begin + radio_time_hi_ld = 1'b0; + radio_time_last_pps_hi_ld = 1'b0; + casex (rb_addr) + RB_RFNOC_INFO: rb_data = {device_id, RFNOC_PROTOVER[15:0]}; + RB_COMPAT_NUM: rb_data = {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]}; + RB_COUNTER: rb_data = counter; + RB_SPI_RDY: rb_data = {31'b0, spi_ready}; + RB_SPI_DATA: rb_data = rb_spi_data; + RB_CLK_STATUS: rb_data = {24'b0, clock_status}; + // SFPP Interface pins. + RB_SFPP_STATUS0: rb_data = { + sfp0_phy_status_sync, 10'b0, + SFPP0_ModAbs_chgd, SFPP0_TxFault_chgd, SFPP0_RxLOS_chgd, + SFPP0_ModAbs_sync, SFPP0_TxFault_sync, SFPP0_RxLOS_sync}; + RB_SFPP_STATUS1: rb_data = { + sfp1_phy_status_sync, 10'b0, + SFPP1_ModAbs_chgd, SFPP1_TxFault_chgd, SFPP1_RxLOS_chgd, + SFPP1_ModAbs_sync, SFPP1_TxFault_sync, SFPP1_RxLOS_sync}; + RB_NUM_TIMEKEEPERS: rb_data = NUM_TIMEKEEPERS; + // Allow readback of configured ethernet interfaces. +`ifdef SFP0_AURORA + RB_ETH_TYPE0: rb_data = {32'h2}; +`else + `ifdef SFP0_10GBE + RB_ETH_TYPE0: rb_data = {32'h1}; + `else + RB_ETH_TYPE0: rb_data = {32'h0}; + `endif +`endif +`ifdef SFP1_AURORA + RB_ETH_TYPE1: rb_data = {32'h2}; +`else + `ifdef SFP1_10GBE + RB_ETH_TYPE1: rb_data = {32'h1}; + `else + RB_ETH_TYPE1: rb_data = {32'h0}; + `endif +`endif + RB_GIT_HASH: rb_data = `GIT_HASH; + RB_XADC_VALS: rb_data = xadc_readback; + SR_BASE_TIME: begin + rb_data = radio_time[31:0]; + radio_time_hi_ld = 1'b1; + end + SR_BASE_TIME + 'h04: rb_data = radio_time_hi; + SR_BASE_TIME + 'h14: begin + rb_data = radio_time_last_pps[31:0]; + radio_time_last_pps_hi_ld = 1'b1; + end + SR_BASE_TIME + 'h18: rb_data = radio_time_last_pps_hi; + SR_BASE_TIME + 'h1C: rb_data = period_ns_q32_tb[31:0]; + SR_BASE_TIME + 'h20: rb_data = period_ns_q32_tb[63:32]; + + default: begin + rb_data = 32'h0; + end + endcase // case (rb_addr) + end + + always @(posedge clk_div2) begin + if (radio_time_hi_ld) + radio_time_hi <= radio_time[63:32]; + if (radio_time_last_pps_hi_ld) + radio_time_last_pps_hi <= radio_time_last_pps[63:32]; + end + + // Timekeeper + + axi_fifo_2clk #( + .WIDTH (64), + .SIZE (3) + ) radio_time_clk_cross_fifo ( + .reset (radio_rst), + .i_aclk (radio_clk), + .i_tdata (radio_time_tb), + .i_tvalid (1'b1), + .i_tready (), + .o_aclk (clk_div2), + .o_tdata (radio_time), + .o_tready (1'b1), + .o_tvalid () + ); + + axi_fifo_2clk #( + .WIDTH (64), + .SIZE (3) + ) radio_time_last_pps_clk_cross_fifo ( + .reset (radio_rst), + .i_aclk (radio_clk), + .i_tdata (radio_time_last_pps_tb), + .i_tvalid (1'b1), + .i_tready (), + .o_aclk (clk_div2), + .o_tdata (radio_time_last_pps), + .o_tready (1'b1), + .o_tvalid () + ); + + timekeeper #( + .BASE_ADDR (SR_BASE_TIME), + .TIME_INCREMENT (1'b1) + ) timekeeper_i ( + .tb_clk (radio_clk), + .tb_rst (radio_rst), + .s_ctrlport_clk (clk_div2), + .s_ctrlport_req_wr (set_stb), + .s_ctrlport_req_rd (), + .s_ctrlport_req_addr (set_addr), + .s_ctrlport_req_data (set_data), + .s_ctrlport_resp_ack (), + .s_ctrlport_resp_data (), + .sample_rx_stb (radio_rx_stb[0]), + .pps (pps), + .tb_timestamp (radio_time_tb), + .tb_timestamp_last_pps (radio_time_last_pps_tb), + .tb_period_ns_q32 (period_ns_q32_tb) + ); + + // Latch state changes to SFP0+ pins. + synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_modabs_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_ModAbs), .out(SFPP0_ModAbs_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_txfault_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_TxFault), .out(SFPP0_TxFault_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) sfpp0_rxlos_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP0_RxLOS), .out(SFPP0_RxLOS_sync)); + + always @(posedge clk) begin + SFPP0_ModAbs_reg <= SFPP0_ModAbs_sync; + SFPP0_TxFault_reg <= SFPP0_TxFault_sync; + SFPP0_RxLOS_reg <= SFPP0_RxLOS_sync; + end + + always @(posedge clk) begin + if (reset || (rb_rd_stb && (rb_addr == RB_SFPP_STATUS0))) begin + SFPP0_ModAbs_chgd <= 1'b0; + SFPP0_TxFault_chgd <= 1'b0; + SFPP0_RxLOS_chgd <= 1'b0; + end else begin + if (SFPP0_ModAbs_sync != SFPP0_ModAbs_reg) + SFPP0_ModAbs_chgd <= 1'b1; + if (SFPP0_TxFault_sync != SFPP0_TxFault_reg) + SFPP0_TxFault_chgd <= 1'b1; + if (SFPP0_RxLOS_sync != SFPP0_RxLOS_reg) + SFPP0_RxLOS_chgd <= 1'b1; + end + end + + // Latch state changes to SFP1+ pins. + synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_modabs_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_ModAbs), .out(SFPP1_ModAbs_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_txfault_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_TxFault), .out(SFPP1_TxFault_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) sfpp1_rxlos_sync ( + .clk(clk), .rst(1'b0 /* no reset */), .in(SFPP1_RxLOS), .out(SFPP1_RxLOS_sync)); + + always @(posedge clk) begin + SFPP1_ModAbs_reg <= SFPP1_ModAbs_sync; + SFPP1_TxFault_reg <= SFPP1_TxFault_sync; + SFPP1_RxLOS_reg <= SFPP1_RxLOS_sync; + end + + always @(posedge clk) begin + if (reset || (rb_rd_stb && (rb_addr == RB_SFPP_STATUS1))) begin + SFPP1_ModAbs_chgd <= 1'b0; + SFPP1_TxFault_chgd <= 1'b0; + SFPP1_RxLOS_chgd <= 1'b0; + end else begin + if (SFPP1_ModAbs_sync != SFPP1_ModAbs_reg) + SFPP1_ModAbs_chgd <= 1'b1; + if (SFPP1_TxFault_sync != SFPP1_TxFault_reg) + SFPP1_TxFault_chgd <= 1'b1; + if (SFPP1_RxLOS_sync != SFPP1_RxLOS_reg) + SFPP1_RxLOS_chgd <= 1'b1; + end + end + + //Synchronize ethernet PHY status bits to bus_clk + //All bits in the bus can be treated as asynchronous + genvar i; + generate + for (i=0; i<16; i=i+1) begin: eth_status_synchronizer_gen + synchronizer #(.INITIAL_VAL(1'b0)) sfp0_status ( + .clk(clk), .rst(1'b0 /* no reset */), .in(sfp0_phy_status[i]), .out(sfp0_phy_status_sync[i])); + synchronizer #(.INITIAL_VAL(1'b0)) sfp1_status ( + .clk(clk), .rst(1'b0 /* no reset */), .in(sfp1_phy_status[i]), .out(sfp1_phy_status_sync[i])); + end + endgenerate + + + wire [1:0] sfpp0_ctrl; + + // SFPP_RS0/1 pins are open drain. + setting_reg #(.my_addr(SR_SFPP_CTRL0), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp0_ctrl + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(sfpp0_ctrl)); + + assign SFPP0_RS0 = sfpp0_ctrl[0] ? 1'b0 : 1'bz; + assign SFPP0_RS1 = sfpp0_ctrl[1] ? 1'b0 : 1'bz; + + wire [1:0] sfpp1_ctrl; + + // SFPP1_RS0/1 pins are open drain. + setting_reg #(.my_addr(SR_SFPP_CTRL1), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp1_ctrl + (.clk(clk), .rst(reset), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(sfpp1_ctrl)); + + assign SFPP1_RS0 = sfpp1_ctrl[0] ? 1'b0 : 1'bz; + assign SFPP1_RS1 = sfpp1_ctrl[1] ? 1'b0 : 1'bz; + + // //////////////////////////////////////////////////////////////// + // ETH interfaces + +`ifdef SFP0_AURORA + // The packet format over Aurora is CHDR so we don't need any special framing/deframing + assign {e2v0_tdata, e2v0_tlast, e2v0_tvalid, sfp0_rx_tready} = {sfp0_rx_tdata, sfp0_rx_tlast, sfp0_rx_tvalid, e2v0_tready}; + assign {sfp0_tx_tdata, sfp0_tx_tlast, sfp0_tx_tvalid, v2e0_tready} = {v2e0_tdata, v2e0_tlast, v2e0_tvalid, sfp0_tx_tready}; + assign {zpui0_tdata, zpui0_tlast, zpui0_tvalid, zpuo0_tready} = {64'h0, 1'b0, 1'b0, 1'b1}; +`else + x300_eth_interface #( + .PROTOVER(RFNOC_PROTOVER), .MTU(10), .NODE_INST(0), .BASE(SR_ETHINT0) + ) eth_interface0 ( + .clk(clk), .reset(reset), + .device_id(device_id), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .eth_tx_tdata(sfp0_tx_tdata), .eth_tx_tuser(sfp0_tx_tuser), .eth_tx_tlast(sfp0_tx_tlast), + .eth_tx_tvalid(sfp0_tx_tvalid), .eth_tx_tready(sfp0_tx_tready), + .eth_rx_tdata(sfp0_rx_tdata), .eth_rx_tuser(sfp0_rx_tuser), .eth_rx_tlast(sfp0_rx_tlast), + .eth_rx_tvalid(sfp0_rx_tvalid), .eth_rx_tready(sfp0_rx_tready), + .e2v_tdata(e2v0_tdata), .e2v_tlast(e2v0_tlast), .e2v_tvalid(e2v0_tvalid), .e2v_tready(e2v0_tready), + .v2e_tdata(v2e0_tdata), .v2e_tlast(v2e0_tlast), .v2e_tvalid(v2e0_tvalid), .v2e_tready(v2e0_tready), + .e2z_tdata(zpui0_tdata), .e2z_tuser(zpui0_tuser), .e2z_tlast(zpui0_tlast), .e2z_tvalid(zpui0_tvalid), .e2z_tready(zpui0_tready), + .z2e_tdata(zpuo0_tdata), .z2e_tuser(zpuo0_tuser), .z2e_tlast(zpuo0_tlast), .z2e_tvalid(zpuo0_tvalid), .z2e_tready(zpuo0_tready) + ); +`endif + +`ifdef SFP1_AURORA + // The packet format over Aurora is CHDR so we don't need any special framing/deframing + assign {e2v1_tdata, e2v1_tlast, e2v1_tvalid, sfp1_rx_tready} = {sfp1_rx_tdata, sfp1_rx_tlast, sfp1_rx_tvalid, e2v1_tready}; + assign {sfp1_tx_tdata, sfp1_tx_tlast, sfp1_tx_tvalid, v2e1_tready} = {v2e1_tdata, v2e1_tlast, v2e1_tvalid, sfp1_tx_tready}; + assign {zpui1_tdata, zpui1_tlast, zpui1_tvalid, zpuo1_tready} = {64'h0, 1'b0, 1'b0, 1'b1}; +`else + x300_eth_interface #( + .PROTOVER(RFNOC_PROTOVER), .MTU(10), .NODE_INST(1), .BASE(SR_ETHINT1) + ) eth_interface1 ( + .clk(clk), .reset(reset), + .device_id(device_id), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .eth_tx_tdata(sfp1_tx_tdata), .eth_tx_tuser(sfp1_tx_tuser), .eth_tx_tlast(sfp1_tx_tlast), + .eth_tx_tvalid(sfp1_tx_tvalid), .eth_tx_tready(sfp1_tx_tready), + .eth_rx_tdata(sfp1_rx_tdata), .eth_rx_tuser(sfp1_rx_tuser), .eth_rx_tlast(sfp1_rx_tlast), + .eth_rx_tvalid(sfp1_rx_tvalid), .eth_rx_tready(sfp1_rx_tready), + .e2v_tdata(e2v1_tdata), .e2v_tlast(e2v1_tlast), .e2v_tvalid(e2v1_tvalid), .e2v_tready(e2v1_tready), + .v2e_tdata(v2e1_tdata), .v2e_tlast(v2e1_tlast), .v2e_tvalid(v2e1_tvalid), .v2e_tready(v2e1_tready), + .e2z_tdata(zpui1_tdata), .e2z_tuser(zpui1_tuser), .e2z_tlast(zpui1_tlast), .e2z_tvalid(zpui1_tvalid), .e2z_tready(zpui1_tready), + .z2e_tdata(zpuo1_tdata), .z2e_tuser(zpuo1_tuser), .z2e_tlast(zpuo1_tlast), .z2e_tvalid(zpuo1_tvalid), .z2e_tready(zpuo1_tready) + ); +`endif + + axi_mux4 #(.PRIO(0), .WIDTH(68)) zpui_mux + (.clk(clk), .reset(reset), .clear(1'b0), + .i0_tdata({zpui0_tuser,zpui0_tdata}), .i0_tlast(zpui0_tlast), .i0_tvalid(zpui0_tvalid), .i0_tready(zpui0_tready), + .i1_tdata({zpui1_tuser,zpui1_tdata}), .i1_tlast(zpui1_tlast), .i1_tvalid(zpui1_tvalid), .i1_tready(zpui1_tready), + .i2_tdata(68'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), + .i3_tdata(68'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), + .o_tdata({zpui_tuser,zpui_tdata}), .o_tlast(zpui_tlast), .o_tvalid(zpui_tvalid), .o_tready(zpui_tready)); + + // Demux ZPU to Eth output by the port number in top 8 bits of data on first line + wire [67:0] zpuo_eth_header; + wire [1:0] zpuo_eth_dest = (zpuo_eth_header[63:56] == 8'd0) ? 2'b00 : 2'b01; + + axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(68)) zpuo_demux + (.clk(clk), .reset(reset), .clear(1'b0), + .header(zpuo_eth_header), .dest(zpuo_eth_dest), + .i_tdata({zpuo_tuser,zpuo_tdata}), .i_tlast(zpuo_tlast), .i_tvalid(zpuo_tvalid), .i_tready(zpuo_tready), + .o0_tdata({zpuo0_tuser,zpuo0_tdata}), .o0_tlast(zpuo0_tlast), .o0_tvalid(zpuo0_tvalid), .o0_tready(zpuo0_tready), + .o1_tdata({zpuo1_tuser,zpuo1_tdata}), .o1_tlast(zpuo1_tlast), .o1_tvalid(zpuo1_tvalid), .o1_tready(zpuo1_tready), + .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1), + .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)); + // + // End ETH interfaces + //////////////////////////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////////////////////////// + // PCIe Interface + // + localparam DMA_RX_DEST_WIDTH = 3; + // PCIe to CHDR (p2c) and CHDR to PCIe (c2p) + wire [63:0] p2c_tdata; + wire p2c_tlast, p2c_tvalid, p2c_tready; + wire [63:0] c2p_tdata; + wire c2p_tlast, c2p_tvalid, c2p_tready; + // Transport adapter with the management interface + nirio_chdr64_adapter #( + .PROTOVER(RFNOC_PROTOVER), + .DMA_ID_WIDTH(DMA_RX_DEST_WIDTH) + ) nirio_xport_adapter + ( + .clk(clk), .rst(reset), + .device_id(device_id), + // From x300_pcie_int + .s_dma_tdata(pcii_tdata), + .s_dma_tuser(pcii_tuser), + .s_dma_tlast(pcii_tlast), + .s_dma_tvalid(pcii_tvalid), + .s_dma_tready(pcii_tready), + // To x300_pcie_int + .m_dma_tdata(pcio_tdata), + .m_dma_tuser(pcio_tuser), + .m_dma_tlast(pcio_tlast), + .m_dma_tvalid(pcio_tvalid), + .m_dma_tready(pcio_tready), + // From xport adapter into the image core + .m_chdr_tdata(p2c_tdata), + .m_chdr_tlast(p2c_tlast), + .m_chdr_tvalid(p2c_tvalid), + .m_chdr_tready(p2c_tready), + // From image core into the xport adapter + .s_chdr_tdata(c2p_tdata), + .s_chdr_tlast(c2p_tlast), + .s_chdr_tvalid(c2p_tvalid), + .s_chdr_tready(c2p_tready) + ); + // + // End PCIe Interface + /////////////////////////////////////////////////////////////////////////// + + rfnoc_image_core #( + .PROTOVER(RFNOC_PROTOVER) + ) rfnoc_sandbox_i ( + .chdr_aclk (clk ), + .ctrl_aclk (clk_div2 ), + .core_arst (reset ), + .device_id (device_id ), + .radio_clk (radio_clk ), + .ce_clk (ce_clk ), + .dram_clk (ddr3_axi_clk_x2), + .m_ctrlport_radio1_req_wr (m_ctrlport_req_wr_radio1 ), + .m_ctrlport_radio1_req_rd (m_ctrlport_req_rd_radio1 ), + .m_ctrlport_radio1_req_addr (m_ctrlport_req_addr_radio1 ), + .m_ctrlport_radio1_req_data (m_ctrlport_req_data_radio1 ), + .m_ctrlport_radio1_req_byte_en (m_ctrlport_req_byte_en_radio1 ), + .m_ctrlport_radio1_req_has_time (m_ctrlport_req_has_time_radio1), + .m_ctrlport_radio1_req_time (m_ctrlport_req_time_radio1 ), + .m_ctrlport_radio1_resp_ack (m_ctrlport_resp_ack_radio1 ), + .m_ctrlport_radio1_resp_status (m_ctrlport_resp_status_radio1 ), + .m_ctrlport_radio1_resp_data (m_ctrlport_resp_data_radio1 ), + .m_ctrlport_radio0_req_wr (m_ctrlport_req_wr_radio0 ), + .m_ctrlport_radio0_req_rd (m_ctrlport_req_rd_radio0 ), + .m_ctrlport_radio0_req_addr (m_ctrlport_req_addr_radio0 ), + .m_ctrlport_radio0_req_data (m_ctrlport_req_data_radio0 ), + .m_ctrlport_radio0_req_byte_en (m_ctrlport_req_byte_en_radio0 ), + .m_ctrlport_radio0_req_has_time (m_ctrlport_req_has_time_radio0), + .m_ctrlport_radio0_req_time (m_ctrlport_req_time_radio0 ), + .m_ctrlport_radio0_resp_ack (m_ctrlport_resp_ack_radio0 ), + .m_ctrlport_radio0_resp_status (m_ctrlport_resp_status_radio0 ), + .m_ctrlport_radio0_resp_data (m_ctrlport_resp_data_radio0 ), + .radio_time (radio_time_tb ), + .radio_rx_stb_radio0 (radio_rx_stb[1:0] ), + .radio_rx_data_radio0 (radio_rx_data[63:0] ), + .radio_rx_running_radio0 (radio_rx_running[1:0] ), + .radio_tx_stb_radio0 (radio_tx_stb[1:0] ), + .radio_tx_data_radio0 (radio_tx_data[63:0] ), + .radio_tx_running_radio0 (radio_tx_running[1:0] ), + .radio_rx_stb_radio1 (radio_rx_stb[3:2] ), + .radio_rx_data_radio1 (radio_rx_data[127:64] ), + .radio_rx_running_radio1 (radio_rx_running[3:2] ), + .radio_tx_stb_radio1 (radio_tx_stb[3:2] ), + .radio_tx_data_radio1 (radio_tx_data[127:64] ), + .radio_tx_running_radio1 (radio_tx_running[3:2] ), + // DRAM interface + .axi_rst (ddr3_axi_rst), + // Slave Interface Write Address Ports + .m_axi_awid (ddr3_axi_awid ), + .m_axi_awaddr (ddr3_axi_awaddr ), + .m_axi_awlen (ddr3_axi_awlen ), + .m_axi_awsize (ddr3_axi_awsize ), + .m_axi_awburst (ddr3_axi_awburst), + .m_axi_awlock (ddr3_axi_awlock ), + .m_axi_awcache (ddr3_axi_awcache), + .m_axi_awprot (ddr3_axi_awprot ), + .m_axi_awqos (ddr3_axi_awqos ), + .m_axi_awregion (), + .m_axi_awuser (), + .m_axi_awvalid (ddr3_axi_awvalid), + .m_axi_awready (ddr3_axi_awready), + // Slave Interface Write Data Ports + .m_axi_wdata (ddr3_axi_wdata ), + .m_axi_wstrb (ddr3_axi_wstrb ), + .m_axi_wlast (ddr3_axi_wlast ), + .m_axi_wuser (), + .m_axi_wvalid (ddr3_axi_wvalid), + .m_axi_wready (ddr3_axi_wready), + // Slave Interface Write Response Ports + .m_axi_bid (ddr3_axi_bid ), + .m_axi_bresp (ddr3_axi_bresp ), + .m_axi_buser (), + .m_axi_bvalid (ddr3_axi_bvalid), + .m_axi_bready (ddr3_axi_bready), + // Slave Interface Read Address Ports + .m_axi_arid (ddr3_axi_arid ), + .m_axi_araddr (ddr3_axi_araddr ), + .m_axi_arlen (ddr3_axi_arlen ), + .m_axi_arsize (ddr3_axi_arsize ), + .m_axi_arburst (ddr3_axi_arburst), + .m_axi_arlock (ddr3_axi_arlock ), + .m_axi_arcache (ddr3_axi_arcache), + .m_axi_arprot (ddr3_axi_arprot ), + .m_axi_arqos (ddr3_axi_arqos ), + .m_axi_arregion (), + .m_axi_aruser (), + .m_axi_arvalid (ddr3_axi_arvalid), + .m_axi_arready (ddr3_axi_arready), + // Slave Interface Read Data Ports + .m_axi_rid (ddr3_axi_rid ), + .m_axi_rdata (ddr3_axi_rdata ), + .m_axi_rresp (ddr3_axi_rresp ), + .m_axi_rlast (ddr3_axi_rlast ), + .m_axi_ruser (), + .m_axi_rvalid (ddr3_axi_rvalid), + .m_axi_rready (ddr3_axi_rready), + .s_eth0_tdata (e2v0_tdata ), + .s_eth0_tlast (e2v0_tlast ), + .s_eth0_tvalid (e2v0_tvalid), + .s_eth0_tready (e2v0_tready), + .m_eth0_tdata (v2e0_tdata ), + .m_eth0_tlast (v2e0_tlast ), + .m_eth0_tvalid (v2e0_tvalid), + .m_eth0_tready (v2e0_tready), + .s_eth1_tdata (e2v1_tdata ), + .s_eth1_tlast (e2v1_tlast ), + .s_eth1_tvalid (e2v1_tvalid), + .s_eth1_tready (e2v1_tready), + .m_eth1_tdata (v2e1_tdata ), + .m_eth1_tlast (v2e1_tlast ), + .m_eth1_tvalid (v2e1_tvalid), + .m_eth1_tready (v2e1_tready), + + .s_pcie_tdata (p2c_tdata ), + .s_pcie_tlast (p2c_tlast ), + .s_pcie_tvalid (p2c_tvalid), + .s_pcie_tready (p2c_tready), + .m_pcie_tdata (c2p_tdata ), + .m_pcie_tlast (c2p_tlast ), + .m_pcie_tvalid (c2p_tvalid), + .m_pcie_tready (c2p_tready) + ); + + //--------------------------------------------------------------------------- + // Convert Control Port to Settings Bus + //--------------------------------------------------------------------------- + + localparam NUM_CTRLPORTS_PER_DBOARD = 1; + + ctrlport_to_settings_bus # ( + .NUM_PORTS (NUM_CTRLPORTS_PER_DBOARD), + .USE_TIME (1) + ) ctrlport0_to_settings_bus_i ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (m_ctrlport_req_wr_radio0), + .s_ctrlport_req_rd (m_ctrlport_req_rd_radio0), + .s_ctrlport_req_addr (m_ctrlport_req_addr_radio0), + .s_ctrlport_req_data (m_ctrlport_req_data_radio0), + .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio0), + .s_ctrlport_req_time (m_ctrlport_req_time_radio0), + .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio0), + .s_ctrlport_resp_data (m_ctrlport_resp_data_radio0), + .set_data (db_fe_set_data[31:0]), + .set_addr (db_fe_set_addr[7:0]), + .set_stb (db_fe_set_stb[0]), + .set_time (), + .set_has_time (), + .rb_stb (db_fe_rb_stb[0]), + .rb_addr (db_fe_rb_addr[7:0]), + .rb_data (db_fe_rb_data[63:0]), + .timestamp (radio_time_tb) + ); + + ctrlport_to_settings_bus # ( + .NUM_PORTS (NUM_CTRLPORTS_PER_DBOARD), + .USE_TIME (1) + ) ctrlport1_to_settings_bus_i ( + .ctrlport_clk (radio_clk), + .ctrlport_rst (radio_rst), + .s_ctrlport_req_wr (m_ctrlport_req_wr_radio1), + .s_ctrlport_req_rd (m_ctrlport_req_rd_radio1), + .s_ctrlport_req_addr (m_ctrlport_req_addr_radio1), + .s_ctrlport_req_data (m_ctrlport_req_data_radio1), + .s_ctrlport_req_has_time (m_ctrlport_req_has_time_radio1), + .s_ctrlport_req_time (m_ctrlport_req_time_radio1), + .s_ctrlport_resp_ack (m_ctrlport_resp_ack_radio1), + .s_ctrlport_resp_data (m_ctrlport_resp_data_radio1), + .set_data (db_fe_set_data[63:32]), + .set_addr (db_fe_set_addr[15:8]), + .set_stb (db_fe_set_stb[1]), + .set_time (), + .set_has_time (), + .rb_stb (db_fe_rb_stb[1]), + .rb_addr (db_fe_rb_addr[15:8]), + .rb_data (db_fe_rb_data[127:64]), + .timestamp (radio_time_tb) + ); + +endmodule // bus_int diff --git a/fpga/usrp3/top/x300/capture_ddrlvds.v b/fpga/usrp3/top/x300/capture_ddrlvds.v new file mode 100644 index 000000000..f5bd5a4a0 --- /dev/null +++ b/fpga/usrp3/top/x300/capture_ddrlvds.v @@ -0,0 +1,200 @@ +// +// Copyright 2011-2014 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// The two clocks are aligned externally in order to eliminate the need for a FIFO. +// A FIFO cannot be used to transition between clock domains because it can cause +// alignment issues between the output of multiple modules. + +module capture_ddrlvds #( + parameter WIDTH = 14, //Width of the SS data bus + parameter PATT_CHECKER = "FALSE", //{TRUE, FALSE}: Is the integrated ramp pattern checker + parameter DATA_IDELAY_MODE = "BYPASSED", //{BYPASSED, FIXED, DYNAMIC} + parameter DATA_IDELAY_VAL = 16, //IDELAY value for FIXED mode. In DYNAMIC mode, this value is used by the timing analyzer + parameter DATA_IDELAY_FREF = 200.0 //Reference clock frequency for the IDELAYCTRL +) ( + // ADC IO Pins + input adc_clk_p, + input adc_clk_n, + input [WIDTH-1:0] adc_data_p, + input [WIDTH-1:0] adc_data_n, + + //System synchronous clock + input radio_clk, + + //IDELAY settings + input data_delay_stb, + input [4:0] data_delay_val, + + //Capture clock and output data + output adc_cap_clk, + output [(2*WIDTH)-1:0] data_out, + + //Pattern checker options (sync to radio_clk) + input checker_en, + output [3:0] checker_locked, + output [3:0] checker_failed +); + + //------------------------------------------------------------------- + // Clock Path + + wire adc_buf_clk; + + // Route source synchronous clock to differential input clock buffer + // then to a global clock buffer. We route to a global buffer because + // the data bus being capture spans multiple banks. + IBUFGDS ss_clk_ibufgds_i ( + .I(adc_clk_p), .IB(adc_clk_n), + .O(adc_buf_clk) + ); + + BUFG ss_clk_bufg_i ( + .I(adc_buf_clk), + .O(adc_cap_clk) + ); + + //------------------------------------------------------------------- + // Data Path + + wire [WIDTH-1:0] adc_data_buf, adc_data_del; + wire [(2*WIDTH)-1:0] adc_data_aclk; + reg [(2*WIDTH)-1:0] adc_data_rclk, adc_data_rclk_sync; + + genvar i; + generate for(i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins + + // Use a differential IO buffer to get the data into the IOB + IBUFDS ibufds_i ( + .I(adc_data_p[i]), .IB(adc_data_n[i]), + .O(adc_data_buf[i]) + ); + + // Use an optional IDELAY to tune the capture interface from + // software. This is a clock to data delay calibration so all + // data bits are delayed by the same amount. + if (DATA_IDELAY_MODE != "BYPASSED") begin + // Pipeline IDELAY control signals to ease routing + reg data_delay_stb_reg; + reg [4:0] data_delay_val_reg; + always @(posedge radio_clk) + {data_delay_stb_reg, data_delay_val_reg} <= {data_delay_stb, data_delay_val}; + + IDELAYE2 #( + .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) + .IDELAY_TYPE(DATA_IDELAY_MODE=="FIXED"?"FIXED":"VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + .SIGNAL_PATTERN("DATA"), // DATA, CLOCK input signal + .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") + .PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE + .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE) + .IDELAY_VALUE(DATA_IDELAY_VAL), // Input delay tap setting (0-31) + .REFCLK_FREQUENCY(DATA_IDELAY_FREF) // IDELAYCTRL clock input frequency in MHz (190.0-210.0). + ) idelay_i ( + .DATAIN(1'b0), // Internal delay data input + .IDATAIN(adc_data_buf[i]), // Data input from the I/O + .DATAOUT(adc_data_del[i]), // Delayed data output + .C(radio_clk), // Clock input + .LD(data_delay_stb_reg), // Load IDELAY_VALUE input + .CE(1'b0), // Active high enable increment/decrement input + .INC(1'b0), // Increment / Decrement tap delay input + .CINVCTRL(1'b0), // Dynamic clock inversion input + .CNTVALUEIN(data_delay_val_reg), // Counter value input + .CNTVALUEOUT(), // Counter value output + .LDPIPEEN(1'b0), // Enable PIPELINE register to load data input + .REGRST(1'b0) // Reset for the pipeline register.Only used in VAR_LOAD_PIPE mode. + ); + end else begin + assign adc_data_del[i] = adc_data_buf[i]; + end + + // Use the global ADC clock to capture delayed data into an IDDR. + // Each IQ sample is transferred in QDR mode i.e. odd and even on + // a rising and falling edge of the clock + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) iddr_i ( + .C(adc_cap_clk), .CE(1'b1), + .D(adc_data_del[i]), .R(1'b0), .S(1'b0), + .Q1(adc_data_aclk[2*i]), .Q2(adc_data_aclk[(2*i)+1]) + ); + end endgenerate + + // Transfer data from the source-synchronous ADC clock domian to the + // system synchronous radio clock domain. We assume that adc_cap_clk + // and radio_clk are generated from the same source and have the same + // frequency however, they have an unknown but constant phase offset. + // In order to cross domains, we use a simple synchronizer to avoid any + // sample-sample delay uncertainty introduced by FIFOs. + // NOTE: The path between adc_data_aclk and adc_data_rclk must be + // constrained to prevent build to build variations. Also, the + // phase of the two clocks must be aligned ensure that the data + // capture is safe + always @(posedge radio_clk) + {adc_data_rclk_sync, adc_data_rclk} <= {adc_data_rclk, adc_data_aclk}; + + // The synchronized output is the output of this module + assign data_out = adc_data_rclk_sync; + + //------------------------------------------------------------------- + // Checkers + + generate if (PATT_CHECKER == "TRUE") begin + wire checker_en_aclk; + wire [1:0] checker_locked_aclk, checker_failed_aclk; + + synchronizer #(.INITIAL_VAL(1'b0)) checker_en_aclk_sync_i ( + .clk(adc_cap_clk), .rst(1'b0), .in(checker_en), .out(checker_en_aclk)); + synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_0_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[0]), .out(checker_locked[0])); + synchronizer #(.INITIAL_VAL(1'b0)) checker_locked_aclk_1_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(checker_locked_aclk[1]), .out(checker_locked[1])); + synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_0_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[0]), .out(checker_failed[0])); + synchronizer #(.INITIAL_VAL(1'b0)) checker_failed_aclk_1_sync_i ( + .clk(radio_clk), .rst(1'b0), .in(checker_failed_aclk[1]), .out(checker_failed[1])); + + cap_pattern_verifier #( // Q Channel : Synchronous to SSCLK + .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1), + .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1) + ) aclk_q_checker_i ( + .clk(adc_cap_clk), .rst(~checker_en_aclk), + .valid(1'b1), .data(~adc_data_aclk[WIDTH-1:0]), + .count(), .errors(), + .locked(checker_locked_aclk[0]), .failed(checker_failed_aclk[0]) + ); + + cap_pattern_verifier #( // I Channel : Synchronous to SSCLK + .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1), + .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1) + ) aclk_i_checker_i ( + .clk(adc_cap_clk), .rst(~checker_en_aclk), + .valid(1'b1), .data(~adc_data_aclk[(2*WIDTH)-1:WIDTH]), + .count(), .errors(), + .locked(checker_locked_aclk[1]), .failed(checker_failed_aclk[1]) + ); + + cap_pattern_verifier #( // Q Channel : Synchronous to Radio CLK + .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1), + .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1) + ) rclk_q_checker_i ( + .clk(radio_clk), .rst(~checker_en), + .valid(1'b1), .data(~adc_data_rclk_sync[WIDTH-1:0]), + .count(), .errors(), + .locked(checker_locked[2]), .failed(checker_failed[2]) + ); + + cap_pattern_verifier #( // I Channel : Synchronous to Radio CLK + .WIDTH(WIDTH), .PATTERN("RAMP"), .HOLD_CYCLES(1), + .RAMP_START(0), .RAMP_STOP({WIDTH{1'b1}}), .RAMP_INCR(1) + ) rclk_i_checker_i ( + .clk(radio_clk), .rst(~checker_en), + .valid(1'b1), .data(~adc_data_rclk_sync[(2*WIDTH)-1:WIDTH]), + .count(), .errors(), + .locked(checker_locked[3]), .failed(checker_failed[3]) + ); + end endgenerate + +endmodule // capture_ddrlvds diff --git a/fpga/usrp3/top/x300/coregen_dsp/.gitignore b/fpga/usrp3/top/x300/coregen_dsp/.gitignore new file mode 100644 index 000000000..dbc4e5588 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/.gitignore @@ -0,0 +1,4 @@ +_xmsgs +*.log +*.ncf + diff --git a/fpga/usrp3/top/x300/coregen_dsp/.lso b/fpga/usrp3/top/x300/coregen_dsp/.lso new file mode 100644 index 000000000..9d9a4a3aa --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/.lso @@ -0,0 +1 @@ +fir_compiler_v5_0 diff --git a/fpga/usrp3/top/x300/coregen_dsp/Makefile.srcs b/fpga/usrp3/top/x300/coregen_dsp/Makefile.srcs new file mode 100644 index 000000000..cc199b39c --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/Makefile.srcs @@ -0,0 +1,17 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## + +COREGEN_DSP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x300/coregen_dsp/, \ +hbdec1.v \ +hbdec1.ngc \ +hbdec2.v \ +hbdec2.ngc \ +hbdec3.v \ +hbdec3.ngc \ +)) + diff --git a/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp new file mode 100644 index 000000000..593e2f179 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = Verilog +SET device = xc7k410t +SET devicefamily = kintex7 +SET flowvendor = Other +SET package = ffg900 +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false diff --git a/fpga/usrp3/top/x300/coregen_dsp/filt2.coe b/fpga/usrp3/top/x300/coregen_dsp/filt2.coe new file mode 100644 index 000000000..e18b5daa7 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/filt2.coe @@ -0,0 +1,36 @@ + Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb31.coe b/fpga/usrp3/top/x300/coregen_dsp/hb31.coe new file mode 100644 index 000000000..37f5a180e --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb31.coe @@ -0,0 +1,32 @@ +Radix=10; +CoefData = -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb35.coe b/fpga/usrp3/top/x300/coregen_dsp/hb35.coe new file mode 100644 index 000000000..18078085d --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb35.coe @@ -0,0 +1,36 @@ +Radix=10; +CoefData = 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb39.coe b/fpga/usrp3/top/x300/coregen_dsp/hb39.coe new file mode 100644 index 000000000..1d99fa946 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb39.coe @@ -0,0 +1,40 @@ +Radix=10; +CoefData = -102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb43.coe b/fpga/usrp3/top/x300/coregen_dsp/hb43.coe new file mode 100644 index 000000000..c56c4c928 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb43.coe @@ -0,0 +1,44 @@ +Radix=10; +CoefData = 100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb47.coe b/fpga/usrp3/top/x300/coregen_dsp/hb47.coe new file mode 100644 index 000000000..85b9a0f3d --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb47.coe @@ -0,0 +1,51 @@ +; Generated with round((2^18-2)*halfgen_test(.21,12,1)) +; 83% effective BW, 64dB to 85dB rolloff +Radix=10; +CoefData = +-62, + 0, + 194, + 0, +-440, + 0, + 855, + 0, +-1505, + 0, + 2478, + 0, +-3900, + 0, + 5990, + 0, +-9187, + 0, + 14632, + 0, +-26536, + 0, + 83009, + 131071, + 83009, + 0, +-26536, + 0, + 14632, + 0, +-9187, + 0, + 5990, + 0, +-3900, + 0, + 2478, + 0, +-1505, + 0, + 855, + 0, +-440, + 0, + 194, + 0, +-62; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb51.coe b/fpga/usrp3/top/x300/coregen_dsp/hb51.coe new file mode 100644 index 000000000..ebfddb7fb --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb51.coe @@ -0,0 +1,52 @@ +Radix=10; +CoefData = 300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb55.coe b/fpga/usrp3/top/x300/coregen_dsp/hb55.coe new file mode 100644 index 000000000..07f861818 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb55.coe @@ -0,0 +1,56 @@ +Radix=10; +CoefData = -400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb59.coe b/fpga/usrp3/top/x300/coregen_dsp/hb59.coe new file mode 100644 index 000000000..79f1e362b --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb59.coe @@ -0,0 +1,60 @@ +Radix=10; +CoefData = 500, +0, +-400, +0, +300, +0, +-200, +0, +100, +0, +-102, + 0, + 282, + -0, + -581, + 0, + 1053, + -0, + -1759, + 0, + 2814, + -0, + -4434, + 0, + 7193, + -0, + -13190, + 0, + 41478, + 65536, + 41478, + 0, + -13190, + -0, + 7193, + 0, + -4434, + -0, + 2814, + 0, + -1759, + -0, + 1053, + 0, + -581, + -0, + 282, + 0, + -102, +0, +100, +0, +-200, +0, +300, +0, +-400, +0 +500; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hb63.coe b/fpga/usrp3/top/x300/coregen_dsp/hb63.coe new file mode 100644 index 000000000..3b312036d --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hb63.coe @@ -0,0 +1,67 @@ +; Generated with round((2^18-2)*halfgen_test(.22,16,1)) +; 88% effective BW, 64dB to 87dB rolloff +Radix=10; +CoefData = +-35, + 0, + 95, + 0, +-195, + 0, + 352, + 0, +-582, + 0, + 907, + 0, +-1354, + 0, + 1953, + 0, +-2751, + 0, + 3813, + 0, +-5249, + 0, + 7264, + 0, +-10296, + 0, + 15494, + 0, +-27083, + 0, + 83196, + 131071, + 83196, + 0, +-27083, + 0, + 15494, + 0, +-10296, + 0, + 7264, + 0, +-5249, + 0, + 3813, + 0, +-2751, + 0, + 1953, + 0, +-1354, + 0, + 907, + 0, +-582, + 0, + 352, + 0, + -195, + 0 + 95, + 0 +-35; diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.asy b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.asy new file mode 100644 index 000000000..7644e7bbe --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec1 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ngc b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ngc new file mode 100644 index 000000000..5c09a6253 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$22g6~753-Xnzd}foo8#5+421).97 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174289io6`;138b?>i6;hk1<7*;12827geh39;0n76a>3`494?"39:0:?om4n531>c=5$530>45ek2d?=?4>0:9l56g4290/8<=512``?k26:3;:76a>3`094?"39:0:?om4n531>44<3f;8m<4?:%627?74jj1e8<<51298k45f83:1(9?<:01ag>h39;0:865`12;e>5<#<891=>ll;o626?7232e:?4k50;&756<6;ki0b9?=:048?j741m0;6):>3;30ff=i<881=:54o01:g?6=,=;86<=mc:l757<6021d=>7m:18'045=9:hh7c:>2;3:?>i6;0k1<7*;12827ge:?7?=h9:3=6=4+401956dd3g>:>7?k;:m27<3=83.?=>4>3ca8j17528o07b?<9583>!26;3;8nn5a40095c=5$530>45ek2d?=?4=0:9l56?5290/8<=512``?k26:38:76a>38394?"39:0:?om4n531>74<3f;85=4?:%627?74jj1e8<<52298k45?n3:1(9?<:01ag>h39;09865`12`a>5<#<891=>ll;o626?4232e:?oo50;&756<6;ki0b9?=:348?j74j00;6):>3;30ff=i<881>:54o01al8:18'045=9:hh7c:>2;0:?>i6;hl1<7*;12827ge:?7?=h9:2n6=4+401956dd3g>:>74>3ca8j1752;o07b?!26;3;8in5a40094>=h9:o>6=4+401956cd3g>:>7?4;n30a1<72->:?7?k<:18'045=9:oh7c:>2;18?j74m;0;6):>3;30af=i<881865`12g2>5<#<891=>kl;o626?3<3f;8i=4?:%627?74mj1e8<<56:9l56bb290/8<=512g`?k26:3=07b?!26;3;8in5a4009<>=h9:nh6=4+401956cd3g>:>774;n30`g<72->:?7?jn:18'045=9:oh7c:>2;`8?j74l00;6):>3;30af=i<881o65`12f;>5<#<891=>kl;o626?b<3f;8h:4?:%627?74mj1e8<<5e:9l56b1290/8<=512g`?k26:3l07b?!26;3;8in5a400955=5$530>45bk2d?=?4>1:9l56b5290/8<=512g`?k26:3;976a>3e394?"39:0:?hm4n531>45<3f;8h=4?:%627?74mj1e8<<51598k45dn3:1(9?<:01fg>h39;0:965`12af>5<#<891=>kl;o626?7132e:?nj50;&756<6;li0b9?=:058?j74kj0;6):>3;30af=i<881=554o01`f?6=,=;86<=jc:l757<6121d=>mn:18'045=9:oh7c:>2;3b?>i6;j21<7*;12827`e:?7?=h9:i>6=4+401956cd3g>:>7?j;:m27f2=83.?=>4>3da8j17528l07b?!26;3;8in5a400965=7>5$530>45bk2d?=?4=1:9l56e6290/8<=512g`?k26:38976a>3b294?"39:0:?hm4n531>75<3f;8nk4?:%627?74mj1e8<<52598k45bj3:1(9?<:01fg>h39;09965`12gb>5<#<891=>kl;o626?4132e:?h750;&756<6;li0b9?=:358?j74m10;6):>3;30af=i<881>554o01f3?6=,=;86<=jc:l757<5121d=>ji:18'045=9:oh7c:>2;0b?>i6;m>1<7*;12827`e:?7?=h9:ho6=4+401956cd3g>:>74>40a8j1752910c<:>5;29 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1742:n27c:>2;00?>o4j;0;6):>3;1g=>h39;09865f3c394?"39:08h45a400960=j6;o626?4032c8hh4?:%627?5c12d?=?4=8:9j7ab=83.?=>4jl:18'045=;m30b9?=:3c8?l5cj3:1(9?<:2f:?k26:38i76g!26;39o56`;1381g>=n;j<1<7*;1280`<=i<881>i54i2`a>5<#<891?i74n531>7c<3`9i<7>5$530>6b>3g>:>75=h39;0:76gic;29 1742oo0b9?=:398mcd=83.?=>4ie:l757<432c::n4?:%627?71j2d?=?4?;:k22d<72->:?7?9b:l757<632c::44?:%627?71j2d?=?4=;:k22=<72->:?7?9b:l757<432c:::4?:%627?71j2d?=?4;;:k223<72->:?7?9b:l757<232c::84?:%627?71j2d?=?49;:k221<72->:?7?9b:l757<032c::?4?:%627?71j2d?=?47;:k224<72->:?7?9b:l757<>32c::=4?:%627?71j2d?=?4n;:k21c<72->:?7?9b:l757:?7?9b:l757:?7?9b:l7570:9j50?=83.?=>4>6c9m044=9810e<;8:18'045=9?h0b9?=:008?l72>3:1(9?<:04a?k26:3;876g>5483>!26;3;=n6`;13820>=n9<>1<7*;12822g=i<881=854i070>5<#<891=;l4n531>40<3`;>>7>5$530>40e3g>:>7?8;:k214<72->:?7?9b:l757<6021b=8>50;&756<6>k1e8<<51898m42a290/8<=517`8j17528k07d?;e;29 174282;3a?>o63;35f>h39;0:o65f15`94?"39:0::o5a40095a=j6=4+401953d4>6c9m044=:810e<:9:18'045=9?h0b9?=:308?l73=3:1(9?<:04a?k26:38876g>4583>!26;3;=n6`;13810>=n9=91<7*;12822g=i<881>854i051>5<#<891=;l4n531>70<3`;<=7>5$530>40e3g>:>7<8;:k235<72->:?7?9b:l757<5021b=;h50;&756<6>k1e8<<52898m40b290/8<=517`8j1752;k07d?9d;29 174282;0a?>o6>:0;6):>3;35f>h39;09o65f14:94?"39:0::o5a40096a=o6=4+401953d:?7?8f:l757<632e:;i4?:%627?70n2d?=?4=;:m23f<72->:?7?8f:l757<432c9m:4?:%627?4f>2d?=?4?;:k1e0<72->:?72d?=?4=;:k1e6<72->:?72d?=?4;;:k264<72->:?7?=0:l757<732c:=k4?:%627?7582d?=?4>;:k25`<72->:?7?=0:l757<532c:=i4?:%627?7582d?=?4<;:k25f<72->:?7?=0:l757<332c:=o4?:%627?7582d?=?4:;:k25d<72->:?7?=0:l757<132c:=44?:%627?7582d?=?48;:k26d<72->:?7?=0:l75744?:%627?7582d?=?46;:k26=<72->:?7?=0:l757:4?:%627?7582d?=?4m;:k263<72->:?7?=0:l75784?:%627?7582d?=?4k;:k261<72->:?7?=0:l757>4?:%627?7582d?=?4i;:k267<72->:?7?=0:l757<6821b=<650;&756<6:91e8<<51098m46c290/8<=511a8j1752910e<>m:18'045=99i0b9?=:098m46f290/8<=511a8j1752;10e<>6:18'045=99i0b9?=:298m46?290/8<=511a8j1752=10e<>8:18'045=99i0b9?=:498m461290/8<=511a8j1752?10e<>::18'045=99i0b9?=:698m471290/8<=511a8j1752110e:18'045=99i0b9?=:e98m477290/8<=511a8j1752l10e<>i:18'045=99i0b9?=:g98m46b290/8<=511a8j17528:07d??4;29 17428:h7c:>2;32?>i6;=0;6):>3;307>h39;0;76a>3383>!26;3;8?6`;1382?>i6;80;6):>3;307>h39;0976a>3183>!26;3;8?6`;1380?>i6:o0;6):>3;307>h39;0?76a>2d83>!26;3;8?6`;1386?>i6:m0;6):>3;307>h39;0=76a>2b83>!26;3;8?6`;1384?>i6;m0;6):>3;307>h39;0376a>3b83>!26;3;8?6`;138:?>i6;k0;6):>3;307>h39;0j76a>3`83>!26;3;8?6`;138a?>i6;00;6):>3;307>h39;0h76a>3983>!26;3;8?6`;138g?>i6;>0;6):>3;307>h39;0n76a>3783>!26;3;8?6`;138e?>i6;<0;6):>3;307>h39;0:<65`13`94?"39:0:?>5a400954=5<#<891=l74n531>4=5<#<891=l74n531>6=6=4+40195d?5<#<891=l74n531>0=5<#<891=l74n531>2=5<#<891=l74n531><=5<#<891=l74n531>g=5<#<891=l74n531>a=5<#<891=l74n531>c=4;h3a4?6=,=;862:9j5dc=83.?=>4>a89m044=9:10e76g>ac83>!26;3;j56`;13822>=n9h>1<7*;1282e<=i<881=:54i0;:>5<#<891=l74n531>4><3f9j97>5$530>6g33g>:>7>4;n1b7?6=,=;86>o;;o626?7<3f9j>7>5$530>6g33g>:>7<4;n1b5?6=,=;86>o;;o626?5<3f9j<7>5$530>6g33g>:>7:4;n1:b?6=,=;86>o;;o626?3<3f92i7>5$530>6g33g>:>784;n1:`?6=,=;86>o;;o626?1<3f92n7>5$530>6g33g>:>764;n1:e?6=,=;86>o;;o626??<3f9257>5$530>6g33g>:>7o4;n1:o;;o626?d<3f92;7>5$530>6g33g>:>7m4;n1:2?6=,=;86>o;;o626?b<3f9297>5$530>6g33g>:>7k4;n1:0?6=,=;86>o;;o626?`<3f92?7>5$530>6g33g>:>7??;:m0=7<72->:?7=n4:l757<6921d?4>50;&756<4i=1e8<<51398k6>a290/8<=53`68j17528907b=7e;29 1742:k?7c:>2;37?>i40m0;6):>3;1b0>h39;0:965`39a94?"39:08m95a400953=o;;o626?7?32e8444?:%627?5f<2d?=?4>9:9l7=>=83.?=>468:18'045=;h>0b9?=:0`8?j5?=3:1(9?<:2c7?k26:3;h76a<8583>!26;39j86`;1382`>=h;191<7*;1280e1=i<881=h54o2:1>5<#<891?l:4n531>4`<3f93=7>5$530>6g33g>:>7:?7=n4:l757<5921d?:h50;&756<4i=1e8<<52398k61b290/8<=53`68j1752;907b=8d;29 1742:k?7c:>2;07?>i4?j0;6):>3;1b0>h39;09965`3``94?"39:08m95a400963=o;;o626?4?32e8m54?:%627?5f<2d?=?4=9:9l7d1=83.?=>4o9:18'045=;h>0b9?=:3`8?j5>k3:1(9?<:2c7?k26:38h76a<9083>!26;39j86`;1381`>=h;1<1<7*;1280e1=i<881>h54o25a>5<#<891?l:4n531>7`<3`k?6=4+4019e6=i<881<65fa383>!26;3k87c:>2;38?lg6290/8<=5a29m044=:21bm=4?:%627?g43g>:>7=4;h;e>5<#<891m>5a40090>=n1l0;6):>3;c0?k26:3?07d7k:18'045=i:1e8<<56:9j=f<72->:?7o<;o626?1<3`3i6=4+4019e6=i<881465f9`83>!26;3k87c:>2;;8?l??290/8<=5a29m044=i21b5:4?:%627?g43g>:>7l4;h;5>5<#<891m>5a4009g>=n1<0;6):>3;c0?k26:3n07d7;:18'045=i:1e8<<5e:9j=6<72->:?7o<;o626?`<3`396=4+4019e6=i<881==54i8394?"39:0j?6`;13825>=n190;6):>3;c0?k26:3;976g7f;29 1742h90b9?=:018?lgd290/8<=5a29m044=9=10ell50;&7565:9jed<72->:?7o<;o626?7132cj57>5$530>d55<#<891m>5a40095==h39;0:565fa783>!26;3k87c:>2;3b?>of=3:1(9?<:`18j17528h07d76:18'045=i:1e8<<51b98m=c=83.?=>4n3:l757<6l21d8=l50;&756<38h1e8<<50:9l05?=83.?=>4;0`9m044=921d8=650;&756<38h1e8<<52:9l051=83.?=>4;0`9m044=;21d8=850;&756<38h1e8<<54:9l053=83.?=>4;0`9m044==21d8=:50;&756<38h1e8<<56:9l055=83.?=>4;0`9m044=?21d8=?50;&756<38h1e8<<58:9l056=83.?=>4;0`9m044=121d?kh50;&756<38h1e8<<5a:9l7cc=83.?=>4;0`9m044=j21d?kj50;&756<38h1e8<<5c:9l7ce=83.?=>4;0`9m044=l21d?kl50;&756<38h1e8<<5e:9l7cg=83.?=>4;0`9m044=n21d?k750;&756<38h1e8<<51198k6`?290/8<=541c8j17528;07b=i6;29 1742=:j7c:>2;31?>i4n<0;6):>3;63e>h39;0:?65`3g694?"39:0?n;o626?7132e8j<4?:%627?27i2d?=?4>7:9l7c6=83.?=>4;0`9m044=9110c>ki:18'045=<9k0b9?=:0;8?j5bm3:1(9?<:52b?k26:3;j76a!26;3>;m6`;1382f>=h;lh1<7*;12874d=i<881=n54o2gb>5<#<8918=o4n531>4b<3f9n57>5$530>16f3g>:>7?j;:m0a=<72->:?7:?a:l757<6n21d?h950;&756<38h1e8<<52198k6c1290/8<=541c8j1752;;07b=j5;29 1742=:j7c:>2;01?>i4m=0;6):>3;63e>h39;09?65`3d194?"39:0?n;o626?4132e?==4?:%627?27i2d?=?4=7:9l05`=83.?=>4;0`9m044=:110c9>j:18'045=<9k0b9?=:3;8?j27l3:1(9?<:52b?k26:38j76a;0b83>!26;3>;m6`;1381f>=h<981<7*;12874d=i<881>n54o2d4>5<#<8918=o4n531>7b<3f9no7>5$530>16f3g>:>7:?7:?a:l757<5n21bo94?:%627?e43g>:>7>4;ha1>5<#<891o>5a40095>=nk80;6):>3;a0?k26:3807dm?:18'045=k:1e8<<53:9jfc<72->:?7m<;o626?2<3`hn6=4+4019g6=i<881965fbe83>!26;3i87c:>2;48?ldd290/8<=5c29m044=?21bno4?:%627?e43g>:>764;h`b>5<#<891o>5a4009=>=nj10;6):>3;a0?k26:3k07dl8:18'045=k:1e8<<5b:9jf3<72->:?7m<;o626?e<3`h>6=4+4019g6=i<881h65fb583>!26;3i87c:>2;g8?ld4290/8<=5c29m044=n21bn?4?:%627?e43g>:>7??;:ka5?6=,=;86n=4n531>47<3`h;6=4+4019g6=i<881=?54i`d94?"39:0h?6`;13827>=nkj0;6):>3;a0?k26:3;?76glb;29 1742j90b9?=:078?lef290/8<=5c29m044=9?10en750;&7567:9jg=<72->:?7m<;o626?7?32ch;7>5$530>f55<#<891o>5a40095d=h39;0:n65fb883>!26;3i87c:>2;3`?>ofm3:1(9?<:b18j17528n07d?8a;29 17428=27c:>2;28?l7003:1(9?<:05:?k26:3;07d?87;29 17428=27c:>2;08?xd3>10;684?:1y'07c=:k30D9=k;I605>"4?>0:mh94i0;2>5<5<5<=57>55;294~"3:l09585G42f8L1563-9<;7?ne69'6d7=k2c:8<4?::k2<4<722c:5:4?::k761<722e?=;4?::a03g=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:9b;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e6g>4083>>o6080;66g>9683>>i39?0;66sm47f94?3=83:p(95<5<5<=i7>55;294~"3:l09595G42f8L1563-9<;7?ne69'6d7=:2c:8<4?::k2<4<722c:5:4?::k75=<722e?=;4?::a03`=83?1<7>t$50f>7?33A>8h6F;309'721=9ho<7):188m4?02900e9?7:188k1712900qo:80;291?6=8r.?>h4=959K06b<@=9:7)=87;3ba2=#:h;1>6g>4083>>o6080;66g>9683>>o3910;66a;1783>>{e<>;1<7;50;2x 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1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=n:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 1742j90b9?=:058?le?290/8<=5c29m044=9110en950;&7569:9jg3<72->:?7m<;o626?7f32ch97>5$530>f55<#<891o>5a40095f=h39;0:h65f16c94?"39:0:;45a40094>=n9>21<7*;12823<=i<881=65f16594?"39:0:;45a40096>=zj<9i6=4>a083>5}#<;o1>594H51g?M2492P:?k4>0z6g>2>=?>03?79l:5c951<0>3=964n022>4=#9981?;o4$020>71a3g;:;7?4n01f>4=#9=:1>:h4n055>4=i9>h1=6`>9782?k4?>3;0b?o7:09'6g5=:020b?l;:09m720=82.8mi4:;o621?7<,=8=6?l<;%613?5fl2.???4;2e9'065=:k?0(9=;:24:?!24=39=h6a>o39l0;66g>8783>>o60=0;66a=b683>>o6010;66g;2383>>o5j?0;66g>8683>>o39o0;66g>8g83>>i6?=0;66g;1`83>>o6000;66a;2g83>>i4io0;66g;1b83>>o39k0;66g>8c83>>o3:90;66g>8483>>o60:0;66g>9383>>o60;0;66g;1e83>>i4?10;66g>8`83>>o60l0;66g>7483>>o6?:0;66g;2083>>o60m0;66g;2283>>ib;3:1(9?<:d08j1752910ch?50;&756;:mf4?6=,=;86h<4n531>7=h39;0876ake;29 1742l80b9?=:598kab=83.?=>4j2:l757<232eoo7>5$530>`46`;1384?>ici3:1(9?<:d08j1752110ci750;&756d=h39;0i76ak5;29 1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 1742h90b9?=:038?l?7290/8<=5a29m044=9;10e5h50;&7563:9jef<72->:?7o<;o626?7332cjn7>5$530>d55<#<891m>5a400953=h39;0:;65fa983>!26;3k87c:>2;3;?>of?3:1(9?<:`18j17528307do9:18'045=i:1e8<<51`98md3=83.?=>4n3:l757<6j21b544?:%627?g43g>:>7?l;:k;a?6=,=;86l=4n531>4b<3f>;n7>5$530>16f3g>:>7>4;n63=?6=,=;869>n;o626?7<3f>;47>5$530>16f3g>:>7<4;n633?6=,=;869>n;o626?5<3f>;:7>5$530>16f3g>:>7:4;n631?6=,=;869>n;o626?3<3f>;87>5$530>16f3g>:>784;n637?6=,=;869>n;o626?1<3f>;=7>5$530>16f3g>:>764;n634?6=,=;869>n;o626??<3f9mj7>5$530>16f3g>:>7o4;n1ea?6=,=;869>n;o626?d<3f9mh7>5$530>16f3g>:>7m4;n1eg?6=,=;869>n;o626?b<3f9mn7>5$530>16f3g>:>7k4;n1ee?6=,=;869>n;o626?`<3f9m57>5$530>16f3g>:>7??;:m0b=<72->:?7:?a:l757<6921d?k850;&756<38h1e8<<51398k6`2290/8<=541c8j17528907b=i4;29 1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 1742j90b9?=:018?led290/8<=5c29m044=9=10enl50;&7565:9jgd<72->:?7m<;o626?7132ch57>5$530>f55<#<891o>5a40095==h39;0:565fc783>!26;3i87c:>2;3b?>od=3:1(9?<:b18j17528h07dl6:18'045=k:1e8<<51b98mdc=83.?=>4l3:l757<6l21b=:o50;&756<6?01e8<<50:9j52>=83.?=>4>789m044=921b=:950;&756<6?01e8<<52:9~f05d290:m<4?:1y'07c=:1=0D9=k;I605>\6;o0:13=?<0?47s+36595dc03gko6<5af`82?k7783:0b<>>:09'554=;?k0(<><:35e?k76?3;0b<=j:09'516=:>l0b<99:09m52d=92d:5;4>;o0;2?7"4im0>7c:>5;38 1412;h87):=7;1b`>"3;;0?>i5+42196g3<,=9?6>86;%601?51l2e8mh4?::k75`<722c:4;4?::k2<1<722e9n:4?::k2<=<722c?>?4?::k1f3<722c:4:4?::k75c<722c:4k4?::m231<722c?=l4?::k2<<<722e?>k4?::m0ec<722c?=n4?::k75g<722c:4o4?::k765<722c:484?::k2<6<722c:5?4?::k2<7<722c?=i4?::m03=<722c:4l4?::k2<`<722c:;84?::k236<722c?><4?::k2>4?::mf7?6=,=;86h<4n531>5=h39;0:76aj0;29 1742l80b9?=:398ka`=83.?=>4j2:l757<432eoi7>5$530>`46`;1386?>ick3:1(9?<:d08j1752?10cil50;&756==h39;0276ak7;29 1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 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17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 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1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8=j:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 174288;7c:>2;32?>o68m0;6):>3;33g>h39;0;76g>0c83>!26;3;;o6`;1382?>o68h0;6):>3;33g>h39;0976g>0883>!26;3;;o6`;1380?>o6810;6):>3;33g>h39;0?76g>0683>!26;3;;o6`;1386?>o68?0;6):>3;33g>h39;0=76g>0483>!26;3;;o6`;1384?>o69?0;6):>3;33g>h39;0376g>1483>!26;3;;o6`;138:?>o69=0;6):>3;33g>h39;0j76g>1283>!26;3;;o6`;138a?>o69;0;6):>3;33g>h39;0h76g>1083>!26;3;;o6`;138g?>o6990;6):>3;33g>h39;0n76g>0g83>!26;3;;o6`;138e?>o68l0;6):>3;33g>h39;0:<65f11694?"39:0:5<#<891=>=4n531>4=5<#<891=>=4n531>6=5<#<891=>=4n531>0=5<#<891=>=4n531>2=5<#<891=>=4n531><=5<#<891=>=4n531>g=5<#<891=>=4n531>a=5<#<891=>=4n531>c=6=4+40195654;n31f?6=,=;86<=<;o626?7632c:ml4?:%627?7f12d?=?4?;:k2e=<72->:?7?n9:l757<632c:m:4?:%627?7f12d?=?4=;:k2e3<72->:?7?n9:l757<432c:m84?:%627?7f12d?=?4;;:k2e6<72->:?7?n9:l757<232c:m?4?:%627?7f12d?=?49;:k2e4<72->:?7?n9:l757<032c:m=4?:%627?7f12d?=?47;:k2=c<72->:?7?n9:l757<>32c:5h4?:%627?7f12d?=?4n;:k2=a<72->:?7?n9:l757:?7?n9:l757:?7?n9:l7570:9j5g6=83.?=>4>a89m044=9810eae83>!26;3;j56`;13820>=n9hi1<7*;1282e<=i<881=854i0ca>5<#<891=l74n531>40<3`;j87>5$530>4g>3g>:>7?8;:k2=<<72->:?7?n9:l757<6021d?l;50;&756<4i=1e8<<50:9l7d5=83.?=>4450;&756<4i=1e8<<54:9l7<`=83.?=>444=83.?=>4442;31?>i40o0;6):>3;1b0>h39;0:?65`39g94?"39:08m95a400951=o;;o626?7132e84o4?:%627?5f<2d?=?4>7:9l7=g=83.?=>466:18'045=;h>0b9?=:0;8?j5?03:1(9?<:2c7?k26:3;j76a<8683>!26;39j86`;1382f>=h;1?1<7*;1280e1=i<881=n54o2:7>5<#<891?l:4n531>4b<3f93?7>5$530>6g33g>:>7?j;:m0<7<72->:?7=n4:l757<6n21d?5?50;&756<4i=1e8<<52198k6>7290/8<=53`68j1752;;07b=8f;29 1742:k?7c:>2;01?>i4?l0;6):>3;1b0>h39;09?65`36f94?"39:08m95a400961=o;;o626?4132e8ml4?:%627?5f<2d?=?4=7:9l7d?=83.?=>4o7:18'045=;h>0b9?=:3;8?j5f?3:1(9?<:2c7?k26:38j76a!26;39j86`;1381f>=h;0i1<7*;1280e1=i<881>n54o2;2>5<#<891?l:4n531>7b<3f93:7>5$530>6g33g>:>7:?7=n4:l757<5n21bm94?:%627?g43g>:>7>4;hc1>5<#<891m>5a40095>=ni80;6):>3;c0?k26:3807do?:18'045=i:1e8<<53:9j=c<72->:?7o<;o626?2<3`3n6=4+4019e6=i<881965f9e83>!26;3k87c:>2;48?l?d290/8<=5a29m044=?21b5o4?:%627?g43g>:>764;h;b>5<#<891m>5a4009=>=n110;6):>3;c0?k26:3k07d78:18'045=i:1e8<<5b:9j=3<72->:?7o<;o626?e<3`3>6=4+4019e6=i<881h65f9583>!26;3k87c:>2;g8?l?4290/8<=5a29m044=n21b5?4?:%627?g43g>:>7??;:k:5?6=,=;86l=4n531>47<3`3;6=4+4019e6=i<881=?54i9d94?"39:0j?6`;13827>=nij0;6):>3;c0?k26:3;?76gnb;29 1742h90b9?=:078?lgf290/8<=5a29m044=9?10el750;&7567:9je=<72->:?7o<;o626?7?32cj;7>5$530>d55<#<891m>5a40095d=h39;0:n65f9883>!26;3k87c:>2;3`?>o?m3:1(9?<:`18j17528n07b:?b;29 1742=:j7c:>2;28?j2713:1(9?<:52b?k26:3;07b:?8;29 1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 174282;0g?>o63;35f>h39;09i65f15094?"39:0::o5a40096c=5<#<891=:h4n531>4=5<#<891=:h4n531>6=5<#<891>l84n531>4=5<#<891>l84n531>6=5<#<891=?>4n531>5=5<#<891=?>4n531>7=54i03`>5<#<891=?>4n531>1=5<#<891=?>4n531>3=5<#<891=?>4n531>==5<#<891=?>4n531>d=5<#<891=?>4n531>f=6=4+40195765<#<891=?>4n531>`=5<#<891=?>4n531>46<3`;:47>5$530>4473g>:>7?>;:k24a<72->:?7??c:l757<732c:;:k24d<72->:?7??c:l757<532c:<44?:%627?77k2d?=?4<;:k24=<72->:?7??c:l757<332c:<:4?:%627?77k2d?=?4:;:k243<72->:?7??c:l757<132c:<84?:%627?77k2d?=?48;:k253<72->:?7??c:l757:?7??c:l7574?:%627?77k2d?=?4m;:k257<72->:?7??c:l757:?7??c:l757:?7??c:l757<6821b==:50;&756<68j1e8<<51098k453290/8<=51218j1752910c<==:18'045=9:90b9?=:098k456290/8<=51218j1752;10c<=?:18'045=9:90b9?=:298k44a290/8<=51218j1752=10c<290/8<=51218j1752j10c<=7:18'045=9:90b9?=:e98k450290/8<=51218j1752l10c<=9:18'045=9:90b9?=:g98k452290/8<=51218j17528:07b?=b;29 17428987c:>2;32?>o6ih0;6):>3;3b=>h39;0;76g>a983>!26;3;j56`;1382?>o6i>0;6):>3;3b=>h39;0976g>a783>!26;3;j56`;1380?>o6i<0;6):>3;3b=>h39;0?76g>a283>!26;3;j56`;1386?>o6i;0;6):>3;3b=>h39;0=76g>a083>!26;3;j56`;1384?>o6i90;6):>3;3b=>h39;0376g>9g83>!26;3;j56`;138:?>o61l0;6):>3;3b=>h39;0j76g>9e83>!26;3;j56`;138a?>o61j0;6):>3;3b=>h39;0h76g>9c83>!26;3;j56`;138g?>o61h0;6):>3;3b=>h39;0n76g>b383>!26;3;j56`;138e?>o6j80;6):>3;3b=>h39;0:<65f1c294?"39:0:m45a400954=4:9j5de=83.?=>4>a89m044=9<10e9883>!26;3;j56`;1382<>=h;h?1<7*;1280e1=i<881<65`3`194?"39:08m95a40095>=h;h81<7*;1280e1=i<881>65`3`394?"39:08m95a40097>=h;h:1<7*;1280e1=i<881865`38d94?"39:08m95a40091>=h;0o1<7*;1280e1=i<881:65`38f94?"39:08m95a40093>=h;0h1<7*;1280e1=i<881465`38c94?"39:08m95a4009=>=h;031<7*;1280e1=i<881m65`38:94?"39:08m95a4009f>=h;0=1<7*;1280e1=i<881o65`38494?"39:08m95a4009`>=h;0?1<7*;1280e1=i<881i65`38694?"39:08m95a4009b>=h;091<7*;1280e1=i<881==54o2;1>5<#<891?l:4n531>47<3f92<7>5$530>6g33g>:>7?=;:m0:?7=n4:l757<6;21d?5k50;&756<4i=1e8<<51598k6>c290/8<=53`68j17528?07b=7c;29 1742:k?7c:>2;35?>i40k0;6):>3;1b0>h39;0:;65`39c94?"39:08m95a40095==o;;o626?7f32e84:4?:%627?5f<2d?=?4>b:9l7=3=83.?=>46;:18'045=;h>0b9?=:0f8?j5?;3:1(9?<:2c7?k26:3;n76a<8383>!26;39j86`;1382b>=h;1;1<7*;1280e1=i<881>=54o2:3>5<#<891?l:4n531>77<3f95$530>6g33g>:>7<=;:m03`<72->:?7=n4:l757<5;21d?:j50;&756<4i=1e8<<52598k61d290/8<=53`68j1752;?07b=nb;29 1742:k?7c:>2;05?>i4ih0;6):>3;1b0>h39;09;65`3`;94?"39:08m95a40096==o;;o626?4f32e8m;4?:%627?5f<2d?=?4=b:9l747>:18'045=;h>0b9?=:3f8?j5?>3:1(9?<:2c7?k26:38n76a<7c83>!26;39j86`;1381b>=ni=0;6):>3;c0?k26:3:07do=:18'045=i:1e8<<51:9je4<72->:?7o<;o626?4<3`k;6=4+4019e6=i<881?65f9g83>!26;3k87c:>2;68?l?b290/8<=5a29m044==21b5i4?:%627?g43g>:>784;h;`>5<#<891m>5a40093>=n1k0;6):>3;c0?k26:3207d7n:18'045=i:1e8<<59:9j==<72->:?7o<;o626?g<3`3<6=4+4019e6=i<881n65f9783>!26;3k87c:>2;a8?l?2290/8<=5a29m044=l21b594?:%627?g43g>:>7k4;h;0>5<#<891m>5a4009b>=n1;0;6):>3;c0?k26:3;;76g61;29 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1742=:j7c:>2;37?>i4n:0;6):>3;63e>h39;0:965`3g094?"39:0?n;o626?7?32e8ik4?:%627?27i2d?=?4>9:9l7`c=83.?=>4;0`9m044=9h10c>kk:18'045=<9k0b9?=:0`8?j5bj3:1(9?<:52b?k26:3;h76a!26;3>;m6`;1382`>=h;l31<7*;12874d=i<881=h54o2g;>5<#<8918=o4n531>4`<3f9n;7>5$530>16f3g>:>7:?7:?a:l757<5921d?h;50;&756<38h1e8<<52398k6c3290/8<=541c8j1752;907b=j3;29 1742=:j7c:>2;07?>i4m;0;6):>3;63e>h39;09965`40394?"39:0?n;o626?4?32e?4;0`9m044=:h10c9>l:18'045=<9k0b9?=:3`8?j27:3:1(9?<:52b?k26:38h76a!26;3>;m6`;1381`>=h;li1<7*;12874d=i<881>h54o2g2>5<#<8918=o4n531>7`<3`i?6=4+4019g6=i<881<65fc383>!26;3i87c:>2;38?le6290/8<=5c29m044=:21bo=4?:%627?e43g>:>7=4;h`e>5<#<891o>5a40090>=njl0;6):>3;a0?k26:3?07dlk:18'045=k:1e8<<56:9jff<72->:?7m<;o626?1<3`hi6=4+4019g6=i<881465fb`83>!26;3i87c:>2;;8?ld?290/8<=5c29m044=i21bn:4?:%627?e43g>:>7l4;h`5>5<#<891o>5a4009g>=nj<0;6):>3;a0?k26:3n07dl;:18'045=k:1e8<<5e:9jf6<72->:?7m<;o626?`<3`h96=4+4019g6=i<881==54ic394?"39:0h?6`;13825>=nj90;6):>3;a0?k26:3;976gnf;29 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1742l80b9?=:`98ka0=83.?=>4j2:l7575$530>`46`;138g?>ic;3:1(9?<:d08j1752l10ci<50;&75646<3fn;6=4+4019a7=i<881=<54obd94?"39:0n>6`;13826>=hkl0;6):>3;g1?k26:3;876ajb;29 1742l80b9?=:068?jcf290/8<=5e39m044=9<10ch750;&7566:9la=<72->:?7k=;o626?7032en;7>5$530>`45<#<891i?5a40095<=h39;0:m65`e583>!26;3o97c:>2;3a?>ic03:1(9?<:d08j17528i07bmk:18'045=m;1e8<<51e98m612290/8<=53668j1752910e>9<:18'045=;>>0b9?=:098m615290/8<=53668j1752;10e>9>:18'045=;>>0b9?=:298m617290/8<=53668j1752=10e>8i:18'045=;>>0b9?=:498m60b290/8<=53668j1752?10e>jn:18'045=;m30b9?=:198m6b?290/8<=53e;8j1752810e>j8:18'045=;m30b9?=:398m6b1290/8<=53e;8j1752:10e>j::18'045=;m30b9?=:598m6b3290/8<=53e;8j1752<10e>j<:18'045=;m30b9?=:798m6b5290/8<=53e;8j1752>10e>j?:18'045=;m30b9?=:998m6ea290/8<=53e;8j1752010e>mj:18'045=;m30b9?=:`98m6ec290/8<=53e;8j1752k10e>ml:18'045=;m30b9?=:b98m6ee290/8<=53e;8j1752m10e>mn:18'045=;m30b9?=:d98m6e>290/8<=53e;8j1752o10e>m7:18'045=;m30b9?=:028?l5d?3:1(9?<:2f:?k26:3;:76g!26;39o56`;13826>=n;j>1<7*;1280`<=i<881=>54i2a0>5<#<891?i74n531>42<3`9h>7>5$530>6b>3g>:>7?:;:k0g4<72->:?7=k9:l757<6>21b?n>50;&756<4l01e8<<51698m6da290/8<=53e;8j17528207d=me;29 1742:n27c:>2;3:?>o4jm0;6):>3;1g=>h39;0:m65f3ca94?"39:08h45a40095g=j6;o626?7c32c8n54?:%627?5c12d?=?4>e:9j7g1=83.?=>4l9:18'045=;m30b9?=:328?l5e=3:1(9?<:2f:?k26:38:76g!26;39o56`;13816>=n;k91<7*;1280`<=i<881>>54i2`1>5<#<891?i74n531>72<3`9i=7>5$530>6b>3g>:>7<:;:k0a5<72->:?7=k9:l757<5>21b?ih50;&756<4l01e8<<52698m6bb290/8<=53e;8j1752;207d=kd;29 1742:n27c:>2;0:?>o4lj0;6):>3;1g=>h39;09m65f3e`94?"39:08h45a40096g=j6;o626?4c32c8no4?:%627?5c12d?=?4=e:9j7g6=83.?=>44=h39;0976gib;29 1742oo0b9?=:298m40d290/8<=517`8j1752910e<8n:18'045=9?h0b9?=:098m40>290/8<=517`8j1752;10e<87:18'045=9?h0b9?=:298m400290/8<=517`8j1752=10e<89:18'045=9?h0b9?=:498m402290/8<=517`8j1752?10e<8;:18'045=9?h0b9?=:698m405290/8<=517`8j1752110e<8>:18'045=9?h0b9?=:898m407290/8<=517`8j1752h10e<;i:18'045=9?h0b9?=:c98m43b290/8<=517`8j1752j10e<;k:18'045=9?h0b9?=:e98m43d290/8<=517`8j1752l10e<;m:18'045=9?h0b9?=:g98m43f290/8<=517`8j17528:07d?:9;29 174282;32?>o6=>0;6):>3;35f>h39;0:>65f14494?"39:0::o5a400956=6=4+401953d4?:%627?71j2d?=?4>6:9j504=83.?=>4>6c9m044=9>10e<;>:18'045=9?h0b9?=:0:8?l7283:1(9?<:04a?k26:3;276g>4g83>!26;3;=n6`;1382e>=n9=o1<7*;12822g=i<881=o54i06`>5<#<891=;l4n531>4e<3`;?n7>5$530>40e3g>:>7?k;:k20d<72->:?7?9b:l757<6m21b=9750;&756<6>k1e8<<51g98m42?290/8<=517`8j1752;:07d?;7;29 174282;02?>o63;35f>h39;09>65f15794?"39:0::o5a400966=?6=4+401953d4>6c9m044=:>10e<9?:18'045=9?h0b9?=:3:8?l71n3:1(9?<:04a?k26:38276g>6d83>!26;3;=n6`;1381e>=n9?n1<7*;12822g=i<881>o54i040>5<#<891=;l4n531>7e<3`;>47>5$530>40e3g>:>7:?7?9b:l757<5m21b=9<50;&756<6>k1e8<<52g98k4>7290/8<=516d8j1752910c<9j:18'045=9>l0b9?=:098k41c290/8<=516d8j1752;10c<9l:18'045=9>l0b9?=:298m7g0290/8<=52`48j1752910e?o::18'045=:h<0b9?=:098m7g3290/8<=52`48j1752;10e?o<:18'045=:h<0b9?=:298m7g5290/8<=52`48j1752=10e<<>:18'045=9;:0b9?=:198m47a290/8<=51328j1752810e290/8<=51328j1752>10e<290/8<=51328j1752010e<<7:18'045=9;:0b9?=:`98m440290/8<=51328j1752k10e<<9:18'045=9;:0b9?=:b98m442290/8<=51328j1752m10e<<;:18'045=9;:0b9?=:d98m444290/8<=51328j1752o10e<<=:18'045=9;:0b9?=:028?l7603:1(9?<:003?k26:3;:76g>0e83>!26;3;;o6`;1383?>o68k0;6):>3;33g>h39;0:76g>0`83>!26;3;;o6`;1381?>o6800;6):>3;33g>h39;0876g>0983>!26;3;;o6`;1387?>o68>0;6):>3;33g>h39;0>76g>0783>!26;3;;o6`;1385?>o68<0;6):>3;33g>h39;0<76g>1783>!26;3;;o6`;138;?>o69<0;6):>3;33g>h39;0276g>1583>!26;3;;o6`;138b?>o69:0;6):>3;33g>h39;0i76g>1383>!26;3;;o6`;138`?>o6980;6):>3;33g>h39;0o76g>1183>!26;3;;o6`;138f?>o68o0;6):>3;33g>h39;0m76g>0d83>!26;3;;o6`;13824>=n99>1<7*;12824f=i<881=<54o017>5<#<891=>=4n531>5=5<#<891=>=4n531>7=54o00e>5<#<891=>=4n531>1=5<#<891=>=4n531>3=5<#<891=>=4n531>==5<#<891=>=4n531>d=5<#<891=>=4n531>f=5<#<891=>=4n531>`=5<#<891=>=4n531>46<3f;9n7>5$530>4543g>:>7?>;:k2ed<72->:?7?n9:l757<732c:m54?:%627?7f12d?=?4>;:k2e2<72->:?7?n9:l757<532c:m;4?:%627?7f12d?=?4<;:k2e0<72->:?7?n9:l757<332c:m>4?:%627?7f12d?=?4:;:k2e7<72->:?7?n9:l757<132c:m<4?:%627?7f12d?=?48;:k2e5<72->:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757:?7?n9:l757<6821b=o>50;&756<6i01e8<<51098m4ga290/8<=51`;8j17528807d?ne;29 17428k27c:>2;30?>o6im0;6):>3;3b=>h39;0:865f1`a94?"39:0:m45a400950=8:9l7d3=83.?=>444421d?4j50;&756<4i=1e8<<57:9l7444447=:18'045=;h>0b9?=:038?j5>83:1(9?<:2c7?k26:3;976a<8g83>!26;39j86`;13827>=h;1o1<7*;1280e1=i<881=954o2:g>5<#<891?l:4n531>43<3f93o7>5$530>6g33g>:>7?9;:m0:?7=n4:l757<6?21d?5o50;&756<4i=1e8<<51998k6>>290/8<=53`68j17528307b=78;29 1742:k?7c:>2;3b?>i40>0;6):>3;1b0>h39;0:n65`39794?"39:08m95a40095f=o;;o626?7b32e84?4?:%627?5f<2d?=?4>f:9l7=7=83.?=>46?:18'045=;h>0b9?=:338?j50n3:1(9?<:2c7?k26:38976a<7d83>!26;39j86`;13817>=h;>n1<7*;1280e1=i<881>954o25`>5<#<891?l:4n531>73<3f9jn7>5$530>6g33g>:>7<9;:m0ed<72->:?7=n4:l757<5?21d?l750;&756<4i=1e8<<52998k6g?290/8<=53`68j1752;307b=n7;29 1742:k?7c:>2;0b?>i4i?0;6):>3;1b0>h39;09n65`38a94?"39:08m95a40096f=o;;o626?4b32e8;o4?:%627?5f<2d?=?4=f:9je1<72->:?7o<;o626?6<3`k96=4+4019e6=i<881=65fa083>!26;3k87c:>2;08?lg7290/8<=5a29m044=;21b5k4?:%627?g43g>:>7:4;h;f>5<#<891m>5a40091>=n1m0;6):>3;c0?k26:3<07d7l:18'045=i:1e8<<57:9j=g<72->:?7o<;o626?><3`3j6=4+4019e6=i<881565f9983>!26;3k87c:>2;c8?l?0290/8<=5a29m044=j21b5;4?:%627?g43g>:>7m4;h;6>5<#<891m>5a4009`>=n1=0;6):>3;c0?k26:3o07d7<:18'045=i:1e8<<5f:9j=7<72->:?7o<;o626?7732c2=7>5$530>d55<#<891m>5a400957=h39;0:?65fab83>!26;3k87c:>2;37?>ofj3:1(9?<:`18j17528?07don:18'045=i:1e8<<51798md?=83.?=>4n3:l757<6?21bm54?:%627?g43g>:>7?7;:kb3?6=,=;86l=4n531>4?<3`k=6=4+4019e6=i<881=l54i`794?"39:0j?6`;1382f>=n100;6):>3;c0?k26:3;h76g7e;29 1742h90b9?=:0f8?j27j3:1(9?<:52b?k26:3:07b:?9;29 1742=:j7c:>2;38?j2703:1(9?<:52b?k26:3807b:?7;29 1742=:j7c:>2;18?j27>3:1(9?<:52b?k26:3>07b:?5;29 1742=:j7c:>2;78?j27<3:1(9?<:52b?k26:3<07b:?3;29 1742=:j7c:>2;58?j2793:1(9?<:52b?k26:3207b:?0;29 1742=:j7c:>2;;8?j5an3:1(9?<:52b?k26:3k07b=ie;29 1742=:j7c:>2;`8?j5al3:1(9?<:52b?k26:3i07b=ic;29 1742=:j7c:>2;f8?j5aj3:1(9?<:52b?k26:3o07b=ia;29 1742=:j7c:>2;d8?j5a13:1(9?<:52b?k26:3;;76a!26;3>;m6`;13825>=h;o<1<7*;12874d=i<881=?54o2d6>5<#<8918=o4n531>45<3f9m87>5$530>16f3g>:>7?;;:m0b6<72->:?7:?a:l757<6=21d?k<50;&756<38h1e8<<51798k6`6290/8<=541c8j17528=07b=i0;29 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1742:n27c:>2;3g?>o4j10;6):>3;1g=>h39;0:i65f3c594?"39:08h45a40095c=4;h1a1?6=,=;86>j6;o626?4632c8n94?:%627?5c12d?=?4=2:9j7g5=83.?=>4l=:18'045=;m30b9?=:368?l5e93:1(9?<:2f:?k26:38>76g!26;39o56`;13812>=n;ml1<7*;1280`<=i<881>:54i2ff>5<#<891?i74n531>7><3`9oh7>5$530>6b>3g>:>7<6;:k0`f<72->:?7=k9:l757<5i21b?il50;&756<4l01e8<<52c98m6b6290/8<=53e;8j1752;i07d=l6;29 1742:n27c:>2;0g?>o4jk0;6):>3;1g=>h39;09i65f3c294?"39:08h45a40096c=h39;0;76gid;29 1742oo0b9?=:098mce=83.?=>4ie:l757<532cmn7>5$530>cc54i04`>5<#<891=;l4n531>5=5<#<891=;l4n531>7=54i044>5<#<891=;l4n531>1=5<#<891=;l4n531>3=5<#<891=;l4n531>==5<#<891=;l4n531>d=5<#<891=;l4n531>f=5<#<891=;l4n531>`=5<#<891=;l4n531>46<3`;>57>5$530>40e3g>:>7?>;:k212<72->:?7?9b:l757<6:21b=8850;&756<6>k1e8<<51298m432290/8<=517`8j17528>07d?:4;29 174282;36?>o6=:0;6):>3;35f>h39;0::65f14094?"39:0::o5a400952=32c:8k4?:%627?71j2d?=?4>a:9j51c=83.?=>4>6c9m044=9k10e<:l:18'045=9?h0b9?=:0a8?l73j3:1(9?<:04a?k26:3;o76g>4`83>!26;3;=n6`;1382a>=n9=31<7*;12822g=i<881=k54i06;>5<#<891=;l4n531>76<3`;?;7>5$530>40e3g>:>7<>;:k203<72->:?7?9b:l757<5:21b=9;50;&756<6>k1e8<<52298m423290/8<=517`8j1752;>07d?;3;29 174282;06?>o6?;0;6):>3;35f>h39;09:65f16394?"39:0::o5a400962=32c::h4?:%627?71j2d?=?4=a:9j53b=83.?=>4>6c9m044=:k10e<8<:18'045=9?h0b9?=:3a8?l7203:1(9?<:04a?k26:38o76g>4e83>!26;3;=n6`;1381a>=n9=81<7*;12822g=i<881>k54o0:3>5<#<891=:h4n531>5=5<#<891=:h4n531>7=54i3c4>5<#<891>l84n531>5=6=4+40196d05<#<891>l84n531>7=54i3c1>5<#<891>l84n531>1=5<#<891=?>4n531>4=5<#<891=?>4n531>6=5<#<891=?>4n531>0=5<#<891=?>4n531>2=5<#<891=?>4n531><=5<#<891=?>4n531>g=5<#<891=?>4n531>a=5<#<891=?>4n531>c=4;h32:?7??c:l757<632c::?7??c:l757<432c:<54?:%627?77k2d?=?4;;:k242<72->:?7??c:l757<232c:<;4?:%627?77k2d?=?49;:k240<72->:?7??c:l757<032c:=;4?:%627?77k2d?=?47;:k250<72->:?7??c:l757<>32c:=94?:%627?77k2d?=?4n;:k256<72->:?7??c:l757:?7??c:l757:?7??c:l7570:9j552=83.?=>4>0b9m044=9810c<=;:18'045=9:90b9?=:198k455290/8<=51218j1752810c<=>:18'045=9:90b9?=:398k457290/8<=51218j1752:10c<10c<=k:18'045=9:90b9?=:998k45d290/8<=51218j1752010c<=m:18'045=9:90b9?=:`98k45f290/8<=51218j1752k10c<=6:18'045=9:90b9?=:b98k45?290/8<=51218j1752m10c<=8:18'045=9:90b9?=:d98k451290/8<=51218j1752o10c<=::18'045=9:90b9?=:028?j75j3:1(9?<:010?k26:3;:76g>a`83>!26;3;j56`;1383?>o6i10;6):>3;3b=>h39;0:76g>a683>!26;3;j56`;1381?>o6i?0;6):>3;3b=>h39;0876g>a483>!26;3;j56`;1387?>o6i:0;6):>3;3b=>h39;0>76g>a383>!26;3;j56`;1385?>o6i80;6):>3;3b=>h39;0<76g>a183>!26;3;j56`;138;?>o61o0;6):>3;3b=>h39;0276g>9d83>!26;3;j56`;138b?>o61m0;6):>3;3b=>h39;0i76g>9b83>!26;3;j56`;138`?>o61k0;6):>3;3b=>h39;0o76g>9`83>!26;3;j56`;138f?>o6j;0;6):>3;3b=>h39;0m76g>b083>!26;3;j56`;13824>=n9k:1<7*;1282e<=i<881=<54i0ce>5<#<891=l74n531>44<3`;ji7>5$530>4g>3g>:>7?<;:k2ea<72->:?7?n9:l757<6<21b=lm50;&756<6i01e8<<51498m4ge290/8<=51`;8j17528<07d?n4;29 17428k27c:>2;34?>o6100;6):>3;3b=>h39;0:465`3`794?"39:08m95a40094>=h;h91<7*;1280e1=i<881=65`3`094?"39:08m95a40096>=h;h;1<7*;1280e1=i<881?65`3`294?"39:08m95a40090>=h;0l1<7*;1280e1=i<881965`38g94?"39:08m95a40092>=h;0n1<7*;1280e1=i<881;65`38`94?"39:08m95a4009<>=h;0k1<7*;1280e1=i<881565`38;94?"39:08m95a4009e>=h;021<7*;1280e1=i<881n65`38594?"39:08m95a4009g>=h;0<1<7*;1280e1=i<881h65`38794?"39:08m95a4009a>=h;0>1<7*;1280e1=i<881j65`38194?"39:08m95a400955=o;;o626?7532e84k4?:%627?5f<2d?=?4>3:9l7=c=83.?=>46k:18'045=;h>0b9?=:078?j5?k3:1(9?<:2c7?k26:3;=76a<8c83>!26;39j86`;13823>=h;1k1<7*;1280e1=i<881=554o2::>5<#<891?l:4n531>4?<3f9347>5$530>6g33g>:>7?n;:m0<2<72->:?7=n4:l757<6j21d?5;50;&756<4i=1e8<<51b98k6>3290/8<=53`68j17528n07b=73;29 1742:k?7c:>2;3f?>i40;0;6):>3;1b0>h39;0:j65`39394?"39:08m95a400965=o;;o626?4532e8;h4?:%627?5f<2d?=?4=3:9l72b=83.?=>49l:18'045=;h>0b9?=:378?j5fj3:1(9?<:2c7?k26:38=76a!26;39j86`;13813>=h;h31<7*;1280e1=i<881>554o2c;>5<#<891?l:4n531>7?<3f9j;7>5$530>6g33g>:>7:?7=n4:l757<5j21d?4m50;&756<4i=1e8<<52b98k6?6290/8<=53`68j1752;n07b=76;29 1742:k?7c:>2;0f?>i4?k0;6):>3;1b0>h39;09j65fa583>!26;3k87c:>2;28?lg5290/8<=5a29m044=921bm<4?:%627?g43g>:>7<4;hc3>5<#<891m>5a40097>=n1o0;6):>3;c0?k26:3>07d7j:18'045=i:1e8<<55:9j=a<72->:?7o<;o626?0<3`3h6=4+4019e6=i<881;65f9c83>!26;3k87c:>2;:8?l?f290/8<=5a29m044=121b554?:%627?g43g>:>7o4;h;4>5<#<891m>5a4009f>=n1?0;6):>3;c0?k26:3i07d7::18'045=i:1e8<<5d:9j=1<72->:?7o<;o626?c<3`386=4+4019e6=i<881j65f9383>!26;3k87c:>2;33?>o>93:1(9?<:`18j17528;07d7?:18'045=i:1e8<<51398m=`=83.?=>4n3:l757<6;21bmn4?:%627?g43g>:>7?;;:kbf?6=,=;86l=4n531>43<3`kj6=4+4019e6=i<881=;54i`;94?"39:0j?6`;13823>=ni10;6):>3;c0?k26:3;376gn7;29 1742h90b9?=:0;8?lg1290/8<=5a29m044=9h10el;50;&756b:9j=<<72->:?7o<;o626?7d32c3i7>5$530>d5n;o626?6<3f>;57>5$530>16f3g>:>7?4;n63n;o626?4<3f>;;7>5$530>16f3g>:>7=4;n632?6=,=;869>n;o626?2<3f>;97>5$530>16f3g>:>7;4;n630?6=,=;869>n;o626?0<3f>;?7>5$530>16f3g>:>794;n635?6=,=;869>n;o626?><3f>;<7>5$530>16f3g>:>774;n1eb?6=,=;869>n;o626?g<3f9mi7>5$530>16f3g>:>7l4;n1e`?6=,=;869>n;o626?e<3f9mo7>5$530>16f3g>:>7j4;n1ef?6=,=;869>n;o626?c<3f9mm7>5$530>16f3g>:>7h4;n1e=?6=,=;869>n;o626?7732e8j54?:%627?27i2d?=?4>1:9l7c0=83.?=>4;0`9m044=9;10c>h::18'045=<9k0b9?=:018?j5a<3:1(9?<:52b?k26:3;?76a!26;3>;m6`;13821>=h;o81<7*;12874d=i<881=;54o2d2>5<#<8918=o4n531>41<3f9m<7>5$530>16f3g>:>7?7;:m0ac<72->:?7:?a:l757<6121d?hk50;&756<38h1e8<<51`98k6cc290/8<=541c8j17528h07b=jb;29 1742=:j7c:>2;3`?>i4mh0;6):>3;63e>h39;0:h65`3d;94?"39:0?n;o626?4732e8i;4?:%627?27i2d?=?4=1:9l7`3=83.?=>4;0`9m044=:;10c>k;:18'045=<9k0b9?=:318?j5b;3:1(9?<:52b?k26:38?76a!26;3>;m6`;13811>=h<8;1<7*;12874d=i<881>;54o533>5<#<8918=o4n531>71<3f>;j7>5$530>16f3g>:>7<7;:m74`<72->:?7:?a:l757<5121d8=j50;&756<38h1e8<<52`98k16d290/8<=541c8j1752;h07b:?2;29 1742=:j7c:>2;0`?>i4n>0;6):>3;63e>h39;09h65`3da94?"39:0?5<#<891o>5a40094>=nk;0;6):>3;a0?k26:3;07dm>:18'045=k:1e8<<52:9jg5<72->:?7m<;o626?5<3`hm6=4+4019g6=i<881865fbd83>!26;3i87c:>2;78?ldc290/8<=5c29m044=>21bnn4?:%627?e43g>:>794;h`a>5<#<891o>5a4009<>=njh0;6):>3;a0?k26:3307dl7:18'045=k:1e8<<5a:9jf2<72->:?7m<;o626?d<3`h=6=4+4019g6=i<881o65fb483>!26;3i87c:>2;f8?ld3290/8<=5c29m044=m21bn>4?:%627?e43g>:>7h4;h`1>5<#<891o>5a400955=h39;0:=65fb183>!26;3i87c:>2;31?>ofn3:1(9?<:b18j17528907dml:18'045=k:1e8<<51598mfd=83.?=>4l3:l757<6=21bol4?:%627?e43g>:>7?9;:k`=?6=,=;86n=4n531>41<3`i36=4+4019g6=i<881=554ib594?"39:0h?6`;1382=>=nk?0;6):>3;a0?k26:3;j76gl5;29 1742j90b9?=:0`8?ld>290/8<=5c29m044=9j10elk50;&756d:9j52g=83.?=>4>789m044=821b=:650;&756<6?01e8<<51:9j521=83.?=>4>789m044=:21vn8:=:182e4<729q/8?k52958L15c3A>8=6T>3g824~2c2>21;:473;5`>1g=9=0<:79=:0390<<083;;69;57487=1=lk8;ocg>4=inh0:7c??0;28j466281/==<537c8 4642;=m7c?>7;38j45b281/=9>526d8j411281e=:l51:l2=3<63g83:7?4n3c;>4=#:k91>464n3`7>4=i;><1<6*o;4$517>60>3->897=9d:m0e`<722c?=h4?::k2<3<722c:494?::m1f2<722c:454?::k767<722c9n;4?::k2<2<722c?=k4?::k2=4?::k2<0<722c:4>4?::k2=7<722c:4?4?::k75a<722e8;54?::k24?::k764<722c:4i4?::k766<722en?7>5$530>`46`;1382?>ib83:1(9?<:d08j1752;10cih50;&7561=h39;0>76akc;29 1742l80b9?=:798kad=83.?=>4j2:l757<032eom7>5$530>`46`;138:?>ic?3:1(9?<:d08j1752h10ci850;&756f=1<7*;128f6>h39;0o76ak3;29 1742l80b9?=:d98ka4=83.?=>4j2:l7575$530>`44;nf3>5<#<891i?5a400954=h39;0:>65`cd83>!26;3o97c:>2;30?>ibj3:1(9?<:d08j17528>07bkn:18'045=m;1e8<<51498k`?=83.?=>4j2:l757<6>21di54?:%627?c53g>:>7?8;:mf3?6=,=;86h<4n531>4><3fo=6=4+4019a7=i<881=454od794?"39:0n>6`;1382e>=hm=0;6):>3;g1?k26:3;i76ak8;29 1742l80b9?=:0a8?jec290/8<=5e39m044=9m10e>9::18'045=;>>0b9?=:198m614290/8<=53668j1752810e>9=:18'045=;>>0b9?=:398m616290/8<=53668j1752:10e>9?:18'045=;>>0b9?=:598m60a290/8<=53668j1752<10e>8j:18'045=;>>0b9?=:798m6bf290/8<=53e;8j1752910e>j7:18'045=;m30b9?=:098m6b0290/8<=53e;8j1752;10e>j9:18'045=;m30b9?=:298m6b2290/8<=53e;8j1752=10e>j;:18'045=;m30b9?=:498m6b4290/8<=53e;8j1752?10e>j=:18'045=;m30b9?=:698m6b7290/8<=53e;8j1752110e>mi:18'045=;m30b9?=:898m6eb290/8<=53e;8j1752h10e>mk:18'045=;m30b9?=:c98m6ed290/8<=53e;8j1752j10e>mm:18'045=;m30b9?=:e98m6ef290/8<=53e;8j1752l10e>m6:18'045=;m30b9?=:g98m6e?290/8<=53e;8j17528:07d=l7;29 1742:n27c:>2;32?>o4k<0;6):>3;1g=>h39;0:>65f3b694?"39:08h45a400956=j6;o626?7232c8o<4?:%627?5c12d?=?4>6:9j7f6=83.?=>410e>li:18'045=;m30b9?=:0:8?l5em3:1(9?<:2f:?k26:3;276g!26;39o56`;1382e>=n;ki1<7*;1280`<=i<881=o54i2`b>5<#<891?i74n531>4e<3`9i57>5$530>6b>3g>:>7?k;:k0f=<72->:?7=k9:l757<6m21b?o950;&756<4l01e8<<51g98m6d1290/8<=53e;8j1752;:07d=m5;29 1742:n27c:>2;02?>o4j=0;6):>3;1g=>h39;09>65f3c194?"39:08h45a400966=j6;o626?4232c8i=4?:%627?5c12d?=?4=6:9j7a`=83.?=>410e>jj:18'045=;m30b9?=:3:8?l5cl3:1(9?<:2f:?k26:38276g!26;39o56`;1381e>=n;mh1<7*;1280`<=i<881>o54i2f2>5<#<891?i74n531>7e<3`9h:7>5$530>6b>3g>:>7:?7=k9:l757<5m21b?o>50;&756<4l01e8<<52g98mc`=83.?=>4ie:l757<732cmh7>5$530>ccoaj3:1(9?<:gg8j1752:10e<8l:18'045=9?h0b9?=:198m40f290/8<=517`8j1752810e<86:18'045=9?h0b9?=:398m40?290/8<=517`8j1752:10e<88:18'045=9?h0b9?=:598m401290/8<=517`8j1752<10e<8::18'045=9?h0b9?=:798m403290/8<=517`8j1752>10e<8=:18'045=9?h0b9?=:998m406290/8<=517`8j1752010e<8?:18'045=9?h0b9?=:`98m43a290/8<=517`8j1752k10e<;j:18'045=9?h0b9?=:b98m43c290/8<=517`8j1752m10e<;l:18'045=9?h0b9?=:d98m43e290/8<=517`8j1752o10e<;n:18'045=9?h0b9?=:028?l7213:1(9?<:04a?k26:3;:76g>5683>!26;3;=n6`;13826>=n9<<1<7*;12822g=i<881=>54i076>5<#<891=;l4n531>42<3`;>87>5$530>40e3g>:>7?:;:k216<72->:?7?9b:l757<6>21b=8<50;&756<6>k1e8<<51698m436290/8<=517`8j17528207d?:0;29 174282;3:?>o63;35f>h39;0:m65f15g94?"39:0::o5a40095g=h6=4+401953de:9j51?=83.?=>4>6c9m044=9o10e<:7:18'045=9?h0b9?=:328?l73?3:1(9?<:04a?k26:38:76g>4783>!26;3;=n6`;13816>=n9=?1<7*;12822g=i<881>>54i067>5<#<891=;l4n531>72<3`;??7>5$530>40e3g>:>7<:;:k237<72->:?7?9b:l757<5>21b=:?50;&756<6>k1e8<<52698m417290/8<=517`8j1752;207d?9f;29 174282;0:?>o6>l0;6):>3;35f>h39;09m65f17f94?"39:0::o5a40096g=4>6c9m044=:o10c<6?:18'045=9>l0b9?=:198k41b290/8<=516d8j1752810c<9k:18'045=9>l0b9?=:398k41d290/8<=516d8j1752:10e?o8:18'045=:h<0b9?=:198m7g2290/8<=52`48j1752810e?o;:18'045=:h<0b9?=:398m7g4290/8<=52`48j1752:10e?o=:18'045=:h<0b9?=:598m446290/8<=51328j1752910e8;29 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1742=:j7c:>2;08?j27?3:1(9?<:52b?k26:3907b:?6;29 1742=:j7c:>2;68?j27=3:1(9?<:52b?k26:3?07b:?4;29 1742=:j7c:>2;48?j27;3:1(9?<:52b?k26:3=07b:?1;29 1742=:j7c:>2;:8?j2783:1(9?<:52b?k26:3307b=if;29 1742=:j7c:>2;c8?j5am3:1(9?<:52b?k26:3h07b=id;29 1742=:j7c:>2;a8?j5ak3:1(9?<:52b?k26:3n07b=ib;29 1742=:j7c:>2;g8?j5ai3:1(9?<:52b?k26:3l07b=i9;29 1742=:j7c:>2;33?>i4n10;6):>3;63e>h39;0:=65`3g494?"39:0?6=4+401905gn;o626?7332e8j>4?:%627?27i2d?=?4>5:9l7c4=83.?=>4;0`9m044=9?10c>h>:18'045=<9k0b9?=:058?j5a83:1(9?<:52b?k26:3;376a!26;3>;m6`;1382=>=h;lo1<7*;12874d=i<881=l54o2gg>5<#<8918=o4n531>4d<3f9nn7>5$530>16f3g>:>7?l;:m0ad<72->:?7:?a:l757<6l21d?h750;&756<38h1e8<<51d98k6c?290/8<=541c8j17528l07b=j7;29 1742=:j7c:>2;03?>i4m?0;6):>3;63e>h39;09=65`3d794?"39:0?n;o626?4332e8i?4?:%627?27i2d?=?4=5:9l047=83.?=>4;0`9m044=:?10c9??:18'045=<9k0b9?=:358?j27n3:1(9?<:52b?k26:38376a;0d83>!26;3>;m6`;1381=>=h<9n1<7*;12874d=i<881>l54o52`>5<#<8918=o4n531>7d<3f>;>7>5$530>16f3g>:>7:?7:?a:l757<5l21d?hm50;&756<38h1e8<<52d98k6c6290/8<=541c8j1752;l07dm;:18'045=k:1e8<<50:9jg7<72->:?7m<;o626?7<3`i:6=4+4019g6=i<881>65fc183>!26;3i87c:>2;18?lda290/8<=5c29m044=<21bnh4?:%627?e43g>:>7;4;h`g>5<#<891o>5a40092>=njj0;6):>3;a0?k26:3=07dlm:18'045=k:1e8<<58:9jfd<72->:?7m<;o626??<3`h36=4+4019g6=i<881m65fb683>!26;3i87c:>2;`8?ld1290/8<=5c29m044=k21bn84?:%627?e43g>:>7j4;h`7>5<#<891o>5a4009a>=nj:0;6):>3;a0?k26:3l07dl=:18'045=k:1e8<<51198mg7=83.?=>4l3:l757<6921bn=4?:%627?e43g>:>7?=;:kbb?6=,=;86n=4n531>45<3`ih6=4+4019g6=i<881=954ib`94?"39:0h?6`;13821>=nkh0;6):>3;a0?k26:3;=76gl9;29 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1742l80b9?=:b98ka2=83.?=>4j2:l7575$530>`46`;138e?>ic93:1(9?<:d08j17528:07bj?:18'045=m;1e8<<51098kf`=83.?=>4j2:l757<6:21doh4?:%627?c53g>:>7?<;:mff?6=,=;86h<4n531>42<3foj6=4+4019a7=i<881=854od;94?"39:0n>6`;13822>=hm10;6):>3;g1?k26:3;<76aj7;29 1742l80b9?=:0:8?jc1290/8<=5e39m044=9010ch;50;&756a:9la1<72->:?7k=;o626?7e32eo47>5$530>`45<#<891i?5a40095a=6=4+40197225<#<891?::4n531>4=5<#<891?::4n531>6=5<#<891?::4n531>0=5<#<891?i74n531>5=5<#<891?i74n531>7=54i2f6>5<#<891?i74n531>1=5<#<891?i74n531>3=5<#<891?i74n531>==5<#<891?i74n531>d=5<#<891?i74n531>f=5<#<891?i74n531>`=5<#<891?i74n531>46<3`9h;7>5$530>6b>3g>:>7?>;:k0g0<72->:?7=k9:l757<6:21b?n:50;&756<4l01e8<<51298m6e4290/8<=53e;8j17528>07d=l2;29 1742:n27c:>2;36?>o4k80;6):>3;1g=>h39;0::65f3b294?"39:08h45a400952=j6;o626?7>32c8ni4?:%627?5c12d?=?4>a:9j7ge=83.?=>4ln:18'045=;m30b9?=:0a8?l5e13:1(9?<:2f:?k26:3;o76g!26;39o56`;1382a>=n;k=1<7*;1280`<=i<881=k54i2`5>5<#<891?i74n531>76<3`9i97>5$530>6b>3g>:>7<>;:k0f1<72->:?7=k9:l757<5:21b?o=50;&756<4l01e8<<52298m6d5290/8<=53e;8j1752;>07d=m1;29 1742:n27c:>2;06?>o4m90;6):>3;1g=>h39;09:65f3ed94?"39:08h45a400962=j6;o626?4>32c8hn4?:%627?5c12d?=?4=a:9j7ad=83.?=>4j>:18'045=;m30b9?=:3a8?l5d>3:1(9?<:2f:?k26:38o76g!26;39o56`;1381a>=n;k:1<7*;1280`<=i<881>k54igd94?"39:0mi6`;1383?>oal3:1(9?<:gg8j1752810ekm50;&7566=5<#<891=;l4n531>4=5<#<891=;l4n531>6=5<#<891=;l4n531>0=6=4+401953d5<#<891=;l4n531>2=5<#<891=;l4n531><=5<#<891=;l4n531>g=5<#<891=;l4n531>a=5<#<891=;l4n531>c=4;h36=?6=,=;86<8m;o626?7632c:9:4?:%627?71j2d?=?4>2:9j500=83.?=>4>6c9m044=9:10e<;::18'045=9?h0b9?=:068?l72<3:1(9?<:04a?k26:3;>76g>5283>!26;3;=n6`;13822>=n9<81<7*;12822g=i<881=:54i072>5<#<891=;l4n531>4><3`;><7>5$530>40e3g>:>7?6;:k20c<72->:?7?9b:l757<6i21b=9k50;&756<6>k1e8<<51c98m42d290/8<=517`8j17528i07d?;b;29 174282;3g?>o63;35f>h39;0:i65f15;94?"39:0::o5a40095c=36=4+401953d4;h373?6=,=;86<8m;o626?4632c:8;4?:%627?71j2d?=?4=2:9j513=83.?=>4>6c9m044=::10e<:;:18'045=9?h0b9?=:368?l73;3:1(9?<:04a?k26:38>76g>7383>!26;3;=n6`;13812>=n9>;1<7*;12822g=i<881>:54i053>5<#<891=;l4n531>7><3`;=j7>5$530>40e3g>:>7<6;:k22`<72->:?7?9b:l757<5i21b=;j50;&756<6>k1e8<<52c98m404290/8<=517`8j1752;i07d?:8;29 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78a;295~N3;81vb>78b;295~N3;81vb>78c;295~N3;81vb>78d;295~N3;81vb>78e;295~N3;81vb>78f;295~N3;81vb>770;295~N3;81vb>771;295~N3;81vb>772;295~N3;81vb>773;295~N3;81vb>774;295~N3;81vb>775;295~N3;81vb>776;295~N3;81vb>777;295~N3;81vb>778;295~N3;81vb>779;295~N3;81vb>77a;295~N3;81vb>77b;295~N3;81vb>77c;295~N3;81vb>77d;295~N3;81vb>77e;295~N3;81vb>77f;295~N3;81vb>760;295~N3;81vb>761;295~N3;81vb>762;295~N3;81vb>763;295~N3;81vb>l9c;295~N3;81vb>l9d;295~N3;81vb>l9e;295~N3;81vb>l9f;295~N3;81vb>l80;295~N3;81vb>l81;295~N3;81vb>l82;295~N3;81vb>l83;295~N3;81vb>l84;295~N3;81vb>l85;295~N3;81vb>l86;295~N3;81vb>l87;295~N3;81vb>l88;295~N3;81vb>l89;295~N3;81vb>l8a;295~N3;81vb>l8b;295~N3;81vb>l8c;295~N3;81vb>l8d;295~N3;81vb>l8e;295~N3;81vb>l8f;295~N3;81vb>l70;295~N3;81vb>l71;295~N3;81vb>l72;295~N3;81vb>l73;295~N3;81vb>l74;295~N3;81vb>l75;295~N3;81vb>j:e;295~N3;81vb>j:f;295~N3;81vb>j90;295~N3;81vb>j91;295~N3;81vb>j92;295~N3;81vb>j93;295~N3;81vb>j94;295~N3;81vb>j95;295~N3;81vb>j96;295~N3;81vb>j97;295~N3;81vb>j98;295~N3;81vb>j99;295~N3;81vb>j9a;295~N3;81vb>j9b;295~N3;81vb>j9c;295~N3;81vb>j9d;295~N3;81vb>j9e;295~N3;81vb>j9f;295~N3;81vb>j80;295~N3;81vb>j81;295~N3;81vb>j82;295~N3;81vb>j83;295~N3;81vb>j84;295~N3;81vb>j85;295~N3;81vb>j86;295~N3;81vb>j87;295~N3;81vb>h:0;295~N3;81vb>h:1;295~N3;81vb>h:2;295~N3;81vb>h:3;295~N3;81vb>h:4;295~N3;81vb>h:5;295~N3;81vb>h:6;295~N3;81vb>h:7;295~N3;81vb>h:8;295~N3;81vb>h:9;295~N3;81vb>h:a;295~N3;81vb>h:b;295~N3;81vb>h:c;295~N3;81vb>h:d;295~N3;81vb>h:e;295~N3;81vb>h:f;295~N3;81vb>h90;295~N3;81vb>h91;295~N3;81vb>h92;295~N3;81vb>h93;295~N3;81vb>h94;295~N3;81vb>h95;295~N3;81vb>h96;295~N3;81vb>h97;295~N3;81vb>h98;295~N3;81vb>h99;295~N3;81vb9?;2;295~N3;81vb9?;3;295~N3;81vb9?;4;295~N3;81vb9?;5;295~N3;81vb9?;6;295~N3;81vb9?;7;295~N3;81vb9?;8;295~N3;81vb9?;9;295~N3;81vb9?;a;295~N3;81vb9?;b;295~N3;81vb9?;c;295~N3;81vb9?;d;295~N3;81vb9?;e;295~N3;81vb9?;f;295~N3;81vb9?:0;295~N3;81vb9?:1;295~N3;81vb9?:2;295~N3;81vb9?:3;295~N3;81vb9?:4;295~N3;81vb9?:5;295~N3;81vb9?:6;295~N3;81vb9?:7;295~N3;81vb9?:8;295~N3;81vb9?:9;295~N3;81vb9?:a;295~N3;81vb9?:b;295~N3;81vb9=<4;295~N3;81vb9=<5;295~N3;81vb9=<6;295~N3;81vb9=<7;295~N3;81vb9=<8;295~N3;81vb9=<9;295~N3;81vb9=8;295~N3;81vb99>9;295~N3;81vb99>a;295~N3;81vb99>b;295~N3;81vb99>c;295~N3;81vb99>d;295~N3;81vb99>e;295~N3;81vb99>f;295~N3;81vb99=0;295~N3;81vb99=1;295~N3;81vb99=2;295~N3;81vb99=3;295~N3;81vb99=4;295~N3;81vb99=5;295~N3;81vb99=6;295~N3;81vb99=7;295~N3;81vb99=8;295~N3;81vb99=9;295~N3;81vb99=a;295~N3;81vb99=b;295~N3;81vb99=c;295~N3;81vb99=d;295~N3;81vb99=e;295~N3;81vb99=f;295~N3;81vb99<0;295~N3;81vb99<1;295~N3;81vb97?a;295~N3;81vb97?b;295~N3;81vb97?c;295~N3;81vb97?d;295~N3;81vb97?e;295~N3;81vb97?f;295~N3;81vb97>0;295~N3;81vb97>1;295~N3;81vb97>2;295~N3;81vb97>3;295~N3;81vb97>4;295~N3;81vb97>5;295~N3;81vb97>6;295~N3;81vb97>7;295~N3;81vb97>8;295~N3;81vb97>9;295~N3;81vb97>a;295~N3;81vb97>b;295~N3;81vb97>c;295~N3;81vb97>d;295~N3;81vb97>e;295~N3;81vb97>f;295~N3;81vb97=0;295~N3;81vb97=1;295~N3;81vb97=2;295~N3;81vb97=3;295~N3;81vb9oic;295~N3;81vb9oid;295~N3;81vb9oie;295~N3;81vb9oif;295~N3;81vb9l?0;295~N3;81vb9l?1;295~N3;81vb9l?2;295~N3;81vb9l?3;295~N3;81vb9l?4;295~N3;81vb9l?5;295~N3;81vb9l?6;295~N3;81vb9l?7;295~N3;81vb9l?8;295~N3;81vb9l?9;295~N3;81vb9l?a;295~N3;81vb9l?b;295~N3;81vb9l?c;295~N3;81vb9l?d;295~N3;81vb9l?e;295~N3;81vb9l?f;295~N3;81vb9l>0;295~N3;81vb9l>1;295~N3;81vb9l>2;295~N3;81vb9l>3;295~N3;81vb9l>4;295~N3;81vb9l>5;295~N3;81vb9mje;295~N3;81vb9mjf;295~N3;81vb9mi0;295~N3;81vb9mi1;295~N3;81vb9mi2;295~N3;81vb9mi3;295~N3;81vb9mi4;295~N3;81vb9mi5;295~N3;81vb9mi6;295~N3;81vb9mi7;295~N3;81vb9mi8;295~N3;81vb9mi9;295~N3;81vb9mia;295~N3;81vb9mib;295~N3;81vb9mic;295~N3;81vb9mid;295~N3;81vb9mie;295~N3;81vb9mif;295~N3;81vb9j?0;295~N3;81vb9j?1;295~N3;81vb9j?2;295~N3;81vb9j?3;295~N3;81vb9j?4;295~N3;81vb9j?5;295~N3;81vb9j?6;295~N3;81vb9j?7;295~N3;81vb9kj0;295~N3;81vb9kj1;295~N3;81vb9kj2;295~N3;81vb9kj3;295~N3;81vb9kj4;295~N3;81vb9kj5;295~N3;81vb9kj6;295~N3;81vb9kj7;295~N3;81vb9kj8;295~N3;81vb9kj9;295~N3;81vb9kja;295~N3;81vb9kjb;295~N3;81vb9kjc;295~N3;81vb9kjd;295~N3;81vb9kje;295~N3;81vb9kjf;295~N3;81vb9ki0;295~N3;81vb9ki1;295~N3;81vb9ki2;295~N3;81vb9ki3;295~N3;81vb9ki4;295~N3;81vb9ki5;295~N3;81vb9ki6;295~N3;81vb9ki7;295~N3;81vb9ki8;295~N3;81vb9ki9;295~N3;81vb8>k2;295~N3;81vb8>k3;295~N3;81vb8>k4;295~N3;81vb8>k5;295~N3;81vb8>k6;295~N3;81vb8>k7;295~N3;81vb8>k8;295~N3;81vb8>k9;295~N3;81vb8>ka;295~N3;81vb8>kb;295~N3;81vb8>kc;295~N3;81vb8>kd;295~N3;81vb8>ke;295~N3;81vb8>kf;295~N3;81vb8>j0;295~N3;81vb8>j1;295~N3;81vb8>j2;295~N3;81vb8>j3;295~N3;81vb8>j4;295~N3;81vb8>j5;295~N3;81vb8>j6;295~N3;81vb8>j7;295~N3;81vb8>j8;295~N3;81vb8>j9;295~N3;81vb8>ja;295~N3;81vb8>jb;295~N3;81vb80;295~N3;81vb8l>1;295~N3;81vb8l>2;295~N3;81vb8l>3;295~N3;81vb8l>4;295~N3;81vb8l>5;295~N3;81vb8l>6;295~N3;81vb8l>7;295~N3;81vb8l>8;295~N3;81vb8l>9;295~N3;81vb8l>a;295~N3;81vb8l>b;295~N3;81vb8l>c;295~N3;81vb8l>d;295~N3;81vb8l>e;295~N3;81vb8l>f;295~N3;81vb8l=0;295~N3;81vb8l=1;295~N3;81vb8l=2;295~N3;81vb8l=3;295~N3;81vb8l=4;295~N3;81vb8l=5;295~N3;81vb8l=6;295~N3;81vb8l=7;295~N3;81vb8l=8;295~N3;81vb8l=9;295~N3;81vb8l=a;295~N3;81vb8l=b;295~N3;81vb8l=c;295~N3;81vb8l=d;295~N3;81vb8l=e;295~N3;81vb8l=f;295~N3;81vb8j76;295~N3;81vb8j77;295~N3;81vb8j78;295~N3;81vb8j79;295~N3;81vb8j7a;295~N3;81vb8j7b;295~N3;81vb8j7c;295~N3;81vb8j7d;295~N3;81vb8j7e;295~N3;81vb8j7f;295~N3;81vb8j60;295~N3;81vb8j61;295~N3;81vb8j62;295~N3;81vb8j63;295~N3;81vb8j64;295~N3;81vb8j65;295~N3;81vb8j66;295~N3;81vb8j67;295~N3;81vb8j68;295~N3;81vb8j69;295~N3;81vb8j6a;295~N3;81vb8j6b;295~N3;81vb8j6c;295~N3;81vb8j6d;295~N3;81vb8j6e;295~N3;81vb8j6f;295~N3;81vb8jn0;295~N3;81vb8jn1;295~N3;81vb8jn2;295~N3;81vb8jn3;295~N3;81vb8jn4;295~N3;81vb8jn5;295~N3;81vb8jn6;295~N3;81vb8jn7;295~N3;81vb8jn8;295~N3;81vb8jn9;295~N3;81vb8jna;295~N3;81vb8jnb;295~N3;81vb;>?2;295~N3;81vb;>?3;295~N3;81vb;>?4;295~N3;81vb;>?5;295~N3;81vb;>?6;295~N3;81vb;>?7;295~N3;81vb;>?8;295~N3;81vb;>?9;295~N3;81vb;>?a;295~N3;81vb;>?b;295~N3;81vb;>?c;295~N3;81vb;>?d;295~N3;81vb;>?e;295~N3;81vb;>?f;295~N3;81vb;>>0;295~N3;81vb;>>1;295~N3;81vb;>>2;295~N3;81vb;>>3;295~N3;81vb;>>4;295~N3;81vb;>>5;295~N3;81vb;>>6;295~N3;81vb;>>7;295~N3;81vb;>>8;295~N3;81vb;>>9;295~N3;81vb;>>a;295~N3;81vb;>>b;295~N3;81vb;>>c;295~N3;81vb;>>d;295~N3;81vb;>>e;295~N3;81vb;>>f;295~N3;81vb;>=0;295~N3;81vb;>=1;295~N3;81vb;>=2;295~N3;81vb;>=3;295~N3;81vb;>=4;295~N3;81vb;>=5;295~N3;81vb;>=6;295~N3;81vb;>=7;295~N3;81vb;<8e;295~N3;81vb;<8f;295~N3;81vb;<70;295~N3;81vb;<71;295~N3;81vb;<72;295~N3;81vb;<73;295~N3;81vb;<74;295~N3;81vb;<75;295~N3;81vb;<76;295~N3;81vb;<77;295~N3;81vb;<78;295~N3;81vb;<79;295~N3;81vb;<7a;295~N3;81vb;<7b;295~N3;81vb;<7c;295~N3;81vb;<7d;295~N3;81vb;<7e;295~N3;81vb;<7f;295~N3;81vb;<60;295~N3;81vb;<61;295~N3;81vb;<62;295~N3;81vb;<63;295~N3;81vb;<64;295~N3;81vb;<65;295~N3;81vb;<66;295~N3;81vb;<67;295~N3;81vb;<68;295~N3;81vb;<69;295~N3;81vb;<6a;295~N3;81vb;<6b;295~N3;81vb;<6c;295~N3;81vb;<6d;295~N3;81vb;<6e;295~N3;81vb;<6f;295~N3;81vb;0;295~N3;81vb;;>1;295~N3;81vb;;>2;295~N3;81vb;;>3;295~N3;81vb;;>4;295~N3;81vb;;>5;295~N3;81vb;;>6;295~N3;81vb;;>7;295~N3;81vb;;>8;295~N3;81vb;;>9;295~N3;81vb;;>a;295~N3;81vb;;>b;295~N3;81vb;;>c;295~N3;81vb;;>d;295~N3;81vb;;>e;295~N3;81vb;;>f;295~N3;81vb;9?a;295~N3;81vb;9?b;295~N3;81vb;9?c;295~N3;81vb;9?d;295~N3;81vb;9?e;295~N3;81vb;9?f;295~N3;81vb;9>0;295~N3;81vb;9>1;295~N3;81vb;9>2;295~N3;81vb;9>3;295~N3;81vb;9>4;295~N3;81vb;9>5;295~N3;81vb;9>6;295~N3;81vb;9>7;295~N3;81vb;9>8;295~N3;81vb;9>9;295~N3;81vb;9>a;295~N3;81vb;9>b;295~N3;81vb;9>c;295~N3;81vb;9>d;295~N3;81vb;o=4;295~N3;81vb;o=5;295~N3;81vb;o=6;295~N3;81vb;o=7;295~N3;81vb;o=8;295~N3;81vb;o=9;295~N3;81vb;o=a;295~N3;81vb;o=b;295~N3;81vb;o=c;295~N3;81vb;o=d;295~N3;81vb;o=e;295~N3;81vb;o=f;295~N3;81vb;o<0;295~N3;81vb;o<1;295~N3;81vb;o<2;295~N3;81vb;o<3;295~N3;81vb;o<4;295~N3;81vb;o<5;295~N3;81vb;o<6;295~N3;81vb;o<7;295~N3;81vqpsO@Byb0cb===_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000df_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a4_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000099_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000097_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000017_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c13 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8e ), + .Q(\blk00000003/sig00000881 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/sig00000b8e ), + .Q15(\NLW_blk00000003/blk00000c12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c11 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8d ), + .Q(\blk00000003/sig00000880 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/sig00000b8d ), + .Q15(\NLW_blk00000003/blk00000c10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0f ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8c ), + .Q(\blk00000003/sig0000087f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/sig00000b8c ), + .Q15(\NLW_blk00000003/blk00000c0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0d ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8b ), + .Q(\blk00000003/sig0000087e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/sig00000b8b ), + .Q15(\NLW_blk00000003/blk00000c0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c0b ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b8a ), + .Q(\blk00000003/sig0000087c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/sig00000b8a ), + .Q15(\NLW_blk00000003/blk00000c0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c09 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b89 ), + .Q(\blk00000003/sig0000087b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/sig00000b89 ), + .Q15(\NLW_blk00000003/blk00000c08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c07 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b88 ), + .Q(\blk00000003/sig0000087d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/sig00000b88 ), + .Q15(\NLW_blk00000003/blk00000c06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c05 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b87 ), + .Q(\blk00000003/sig00000879 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/sig00000b87 ), + .Q15(\NLW_blk00000003/blk00000c04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c03 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b86 ), + .Q(\blk00000003/sig00000878 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/sig00000b86 ), + .Q15(\NLW_blk00000003/blk00000c02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c01 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b85 ), + .Q(\blk00000003/sig0000087a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/sig00000b85 ), + .Q15(\NLW_blk00000003/blk00000c00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bff ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b84 ), + .Q(\blk00000003/sig00000876 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/sig00000b84 ), + .Q15(\NLW_blk00000003/blk00000bfe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b83 ), + .Q(\blk00000003/sig00000875 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/sig00000b83 ), + .Q15(\NLW_blk00000003/blk00000bfc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b82 ), + .Q(\blk00000003/sig00000877 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bfa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/sig00000b82 ), + .Q15(\NLW_blk00000003/blk00000bfa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b81 ), + .Q(\blk00000003/sig00000873 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/sig00000b81 ), + .Q15(\NLW_blk00000003/blk00000bf8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b80 ), + .Q(\blk00000003/sig00000872 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/sig00000b80 ), + .Q15(\NLW_blk00000003/blk00000bf6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/sig00000874 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/sig00000b7f ), + .Q15(\NLW_blk00000003/blk00000bf4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/sig00000870 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/sig00000b7e ), + .Q15(\NLW_blk00000003/blk00000bf2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/sig0000086f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bf0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/sig00000b7d ), + .Q15(\NLW_blk00000003/blk00000bf0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bef ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/sig00000871 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/sig00000b7c ), + .Q15(\NLW_blk00000003/blk00000bee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bed ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7b ), + .Q(\blk00000003/sig0000086d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/sig00000b7b ), + .Q15(\NLW_blk00000003/blk00000bec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000beb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b7a ), + .Q(\blk00000003/sig0000086c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/sig00000b7a ), + .Q15(\NLW_blk00000003/blk00000bea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b79 ), + .Q(\blk00000003/sig0000086e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/sig00000b79 ), + .Q15(\NLW_blk00000003/blk00000be8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b78 ), + .Q(\blk00000003/sig0000086a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/sig00000b78 ), + .Q15(\NLW_blk00000003/blk00000be6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b77 ), + .Q(\blk00000003/sig0000086b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/sig00000b77 ), + .Q15(\NLW_blk00000003/blk00000be4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b76 ), + .Q(\blk00000003/sig000008b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/sig00000b76 ), + .Q15(\NLW_blk00000003/blk00000be2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b75 ), + .Q(\blk00000003/sig000008b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000be0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/sig00000b75 ), + .Q15(\NLW_blk00000003/blk00000be0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b74 ), + .Q(\blk00000003/sig000008ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bde ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/sig00000b74 ), + .Q15(\NLW_blk00000003/blk00000bde_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b73 ), + .Q(\blk00000003/sig000008ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bdc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/sig00000b73 ), + .Q15(\NLW_blk00000003/blk00000bdc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b72 ), + .Q(\blk00000003/sig000008af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bda ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/sig00000b72 ), + .Q15(\NLW_blk00000003/blk00000bda_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b71 ), + .Q(\blk00000003/sig000008ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/sig00000b71 ), + .Q15(\NLW_blk00000003/blk00000bd8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b70 ), + .Q(\blk00000003/sig000008aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/sig00000b70 ), + .Q15(\NLW_blk00000003/blk00000bd6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6f ), + .Q(\blk00000003/sig000008ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/sig00000b6f ), + .Q15(\NLW_blk00000003/blk00000bd4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6e ), + .Q(\blk00000003/sig000008a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/sig00000b6e ), + .Q15(\NLW_blk00000003/blk00000bd2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6d ), + .Q(\blk00000003/sig000008a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bd0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/sig00000b6d ), + .Q15(\NLW_blk00000003/blk00000bd0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6c ), + .Q(\blk00000003/sig000008a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/sig00000b6c ), + .Q15(\NLW_blk00000003/blk00000bce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig000008a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bcc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/sig00000b6b ), + .Q15(\NLW_blk00000003/blk00000bcc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b6a ), + .Q(\blk00000003/sig000008a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/sig00000b6a ), + .Q15(\NLW_blk00000003/blk00000bca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b69 ), + .Q(\blk00000003/sig000008a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/sig00000b69 ), + .Q15(\NLW_blk00000003/blk00000bc8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig000008a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/sig00000b68 ), + .Q15(\NLW_blk00000003/blk00000bc6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b67 ), + .Q(\blk00000003/sig000008a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/sig00000b67 ), + .Q15(\NLW_blk00000003/blk00000bc4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc3 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b66 ), + .Q(\blk00000003/sig000008a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/sig00000b66 ), + .Q15(\NLW_blk00000003/blk00000bc2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc1 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig000008a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bc0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/sig00000b65 ), + .Q15(\NLW_blk00000003/blk00000bc0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbf ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b64 ), + .Q(\blk00000003/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000bbe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbd ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig0000089d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bbc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000bbc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbb ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b62 ), + .Q(\blk00000003/sig0000089f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000bba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb9 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b61 ), + .Q(\blk00000003/sig0000089c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000bb8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb7 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b60 ), + .Q(\blk00000003/sig0000089b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000bb6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb5 ( + .C(clk), + .CE(\blk00000003/sig000009b7 ), + .D(\blk00000003/sig00000b5f ), + .Q(\blk00000003/sig0000089a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b7 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000bb4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5e ), + .Q(\blk00000003/sig00000839 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000bb2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5d ), + .Q(\blk00000003/sig00000838 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bb0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000bb0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000baf ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5c ), + .Q(\blk00000003/sig00000837 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000bae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bad ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5b ), + .Q(\blk00000003/sig00000836 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000bac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000bac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bab ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b5a ), + .Q(\blk00000003/sig00000835 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000baa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000baa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba9 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b59 ), + .Q(\blk00000003/sig00000833 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000ba8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba7 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b58 ), + .Q(\blk00000003/sig00000832 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000ba6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba5 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b57 ), + .Q(\blk00000003/sig00000834 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000ba4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba3 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b56 ), + .Q(\blk00000003/sig00000830 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000ba2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ba1 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b55 ), + .Q(\blk00000003/sig0000082f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ba0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000ba0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b54 ), + .Q(\blk00000003/sig00000831 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000b9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b53 ), + .Q(\blk00000003/sig0000082d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000b9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b9b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b52 ), + .Q(\blk00000003/sig0000082c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b9a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000b9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b99 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b51 ), + .Q(\blk00000003/sig0000082e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b98 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000b98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b97 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b50 ), + .Q(\blk00000003/sig0000082b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b96 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000b96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b95 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4f ), + .Q(\blk00000003/sig0000082a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b94 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000b94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b93 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4e ), + .Q(\blk00000003/sig00000829 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b92 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000b92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b91 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4d ), + .Q(\blk00000003/sig00000828 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b90 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000b90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4c ), + .Q(\blk00000003/sig00000826 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/sig00000b4c ), + .Q15(\NLW_blk00000003/blk00000b8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4b ), + .Q(\blk00000003/sig00000825 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/sig00000b4b ), + .Q15(\NLW_blk00000003/blk00000b8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b8b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b4a ), + .Q(\blk00000003/sig00000827 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/sig00000b4a ), + .Q15(\NLW_blk00000003/blk00000b8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b89 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b49 ), + .Q(\blk00000003/sig00000823 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/sig00000b49 ), + .Q15(\NLW_blk00000003/blk00000b88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b87 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b48 ), + .Q(\blk00000003/sig00000822 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/sig00000b48 ), + .Q15(\NLW_blk00000003/blk00000b86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b85 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b47 ), + .Q(\blk00000003/sig00000824 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/sig00000b47 ), + .Q15(\NLW_blk00000003/blk00000b84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b83 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b46 ), + .Q(\blk00000003/sig00000851 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/sig00000b46 ), + .Q15(\NLW_blk00000003/blk00000b82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b81 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b45 ), + .Q(\blk00000003/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/sig00000b45 ), + .Q15(\NLW_blk00000003/blk00000b80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b44 ), + .Q(\blk00000003/sig0000084e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/sig00000b44 ), + .Q15(\NLW_blk00000003/blk00000b7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b43 ), + .Q(\blk00000003/sig00000850 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/sig00000b43 ), + .Q15(\NLW_blk00000003/blk00000b7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b7b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b42 ), + .Q(\blk00000003/sig0000084c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/sig00000b42 ), + .Q15(\NLW_blk00000003/blk00000b7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b79 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b41 ), + .Q(\blk00000003/sig0000084b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/sig00000b41 ), + .Q15(\NLW_blk00000003/blk00000b78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b77 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b40 ), + .Q(\blk00000003/sig0000084d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/sig00000b40 ), + .Q15(\NLW_blk00000003/blk00000b76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b75 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3f ), + .Q(\blk00000003/sig00000849 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/sig00000b3f ), + .Q15(\NLW_blk00000003/blk00000b74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b73 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3e ), + .Q(\blk00000003/sig00000848 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/sig00000b3e ), + .Q15(\NLW_blk00000003/blk00000b72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b71 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3d ), + .Q(\blk00000003/sig0000084a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/sig00000b3d ), + .Q15(\NLW_blk00000003/blk00000b70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3c ), + .Q(\blk00000003/sig00000847 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/sig00000b3c ), + .Q15(\NLW_blk00000003/blk00000b6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3b ), + .Q(\blk00000003/sig00000846 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/sig00000b3b ), + .Q15(\NLW_blk00000003/blk00000b6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b6b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b3a ), + .Q(\blk00000003/sig00000845 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/sig00000b3a ), + .Q15(\NLW_blk00000003/blk00000b6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b69 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b39 ), + .Q(\blk00000003/sig00000844 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/sig00000b39 ), + .Q15(\NLW_blk00000003/blk00000b68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b67 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b38 ), + .Q(\blk00000003/sig00000842 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/sig00000b38 ), + .Q15(\NLW_blk00000003/blk00000b66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b65 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b37 ), + .Q(\blk00000003/sig00000841 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/sig00000b37 ), + .Q15(\NLW_blk00000003/blk00000b64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b63 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b36 ), + .Q(\blk00000003/sig00000843 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/sig00000b36 ), + .Q15(\NLW_blk00000003/blk00000b62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b61 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b35 ), + .Q(\blk00000003/sig0000083f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/sig00000b35 ), + .Q15(\NLW_blk00000003/blk00000b60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5f ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b34 ), + .Q(\blk00000003/sig0000083e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/sig00000b34 ), + .Q15(\NLW_blk00000003/blk00000b5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5d ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b33 ), + .Q(\blk00000003/sig00000840 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/sig00000b33 ), + .Q15(\NLW_blk00000003/blk00000b5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b5b ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b32 ), + .Q(\blk00000003/sig0000083c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/sig00000b32 ), + .Q15(\NLW_blk00000003/blk00000b5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b59 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b31 ), + .Q(\blk00000003/sig0000083b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/sig00000b31 ), + .Q15(\NLW_blk00000003/blk00000b58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b57 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b30 ), + .Q(\blk00000003/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/sig00000b30 ), + .Q15(\NLW_blk00000003/blk00000b56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b55 ( + .C(clk), + .CE(\blk00000003/sig000009b6 ), + .D(\blk00000003/sig00000b2f ), + .Q(\blk00000003/sig0000083a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b6 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/sig00000b2f ), + .Q15(\NLW_blk00000003/blk00000b54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b53 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000b2e ), + .Q(\blk00000003/sig000009ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b52 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig00000b2e ), + .Q15(\NLW_blk00000003/blk00000b52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b51 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2d ), + .Q(\blk00000003/sig00000808 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/sig00000b2d ), + .Q15(\NLW_blk00000003/blk00000b50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2c ), + .Q(\blk00000003/sig00000807 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/sig00000b2c ), + .Q15(\NLW_blk00000003/blk00000b4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2b ), + .Q(\blk00000003/sig00000809 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/sig00000b2b ), + .Q15(\NLW_blk00000003/blk00000b4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b4b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b2a ), + .Q(\blk00000003/sig00000806 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/sig00000b2a ), + .Q15(\NLW_blk00000003/blk00000b4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b49 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b29 ), + .Q(\blk00000003/sig00000805 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/sig00000b29 ), + .Q15(\NLW_blk00000003/blk00000b48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b47 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b28 ), + .Q(\blk00000003/sig00000804 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/sig00000b28 ), + .Q15(\NLW_blk00000003/blk00000b46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b45 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b27 ), + .Q(\blk00000003/sig00000803 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/sig00000b27 ), + .Q15(\NLW_blk00000003/blk00000b44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b43 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b26 ), + .Q(\blk00000003/sig00000801 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/sig00000b26 ), + .Q15(\NLW_blk00000003/blk00000b42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b41 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b25 ), + .Q(\blk00000003/sig00000800 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/sig00000b25 ), + .Q15(\NLW_blk00000003/blk00000b40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b24 ), + .Q(\blk00000003/sig00000802 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/sig00000b24 ), + .Q15(\NLW_blk00000003/blk00000b3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b23 ), + .Q(\blk00000003/sig000007fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/sig00000b23 ), + .Q15(\NLW_blk00000003/blk00000b3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b3b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b22 ), + .Q(\blk00000003/sig000007fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/sig00000b22 ), + .Q15(\NLW_blk00000003/blk00000b3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b39 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b21 ), + .Q(\blk00000003/sig000007ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/sig00000b21 ), + .Q15(\NLW_blk00000003/blk00000b38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b37 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b20 ), + .Q(\blk00000003/sig000007fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/sig00000b20 ), + .Q15(\NLW_blk00000003/blk00000b36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b35 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1f ), + .Q(\blk00000003/sig000007fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/sig00000b1f ), + .Q15(\NLW_blk00000003/blk00000b34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b33 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1e ), + .Q(\blk00000003/sig000007fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/sig00000b1e ), + .Q15(\NLW_blk00000003/blk00000b32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b31 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1d ), + .Q(\blk00000003/sig000007f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/sig00000b1d ), + .Q15(\NLW_blk00000003/blk00000b30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1c ), + .Q(\blk00000003/sig000007f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/sig00000b1c ), + .Q15(\NLW_blk00000003/blk00000b2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1b ), + .Q(\blk00000003/sig000007f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/sig00000b1b ), + .Q15(\NLW_blk00000003/blk00000b2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b2b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b1a ), + .Q(\blk00000003/sig000007f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b2a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/sig00000b1a ), + .Q15(\NLW_blk00000003/blk00000b2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b29 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b19 ), + .Q(\blk00000003/sig000007f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b28 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/sig00000b19 ), + .Q15(\NLW_blk00000003/blk00000b28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b27 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b18 ), + .Q(\blk00000003/sig000007f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b26 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/sig00000b18 ), + .Q15(\NLW_blk00000003/blk00000b26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b25 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b17 ), + .Q(\blk00000003/sig000007f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b24 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/sig00000b17 ), + .Q15(\NLW_blk00000003/blk00000b24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b23 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b16 ), + .Q(\blk00000003/sig000007f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b22 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/sig00000b16 ), + .Q15(\NLW_blk00000003/blk00000b22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b21 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b15 ), + .Q(\blk00000003/sig00000821 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b20 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/sig00000b15 ), + .Q15(\NLW_blk00000003/blk00000b20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b14 ), + .Q(\blk00000003/sig00000820 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/sig00000b14 ), + .Q15(\NLW_blk00000003/blk00000b1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b13 ), + .Q(\blk00000003/sig0000081f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/sig00000b13 ), + .Q15(\NLW_blk00000003/blk00000b1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b1b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b12 ), + .Q(\blk00000003/sig0000081d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b1a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/sig00000b12 ), + .Q15(\NLW_blk00000003/blk00000b1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b19 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b11 ), + .Q(\blk00000003/sig0000081c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b18 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/sig00000b11 ), + .Q15(\NLW_blk00000003/blk00000b18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b17 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b10 ), + .Q(\blk00000003/sig0000081e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b16 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/sig00000b10 ), + .Q15(\NLW_blk00000003/blk00000b16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b15 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0f ), + .Q(\blk00000003/sig0000081a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b14 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/sig00000b0f ), + .Q15(\NLW_blk00000003/blk00000b14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b13 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0e ), + .Q(\blk00000003/sig00000819 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b12 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/sig00000b0e ), + .Q15(\NLW_blk00000003/blk00000b12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b11 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0d ), + .Q(\blk00000003/sig0000081b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b10 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/sig00000b0d ), + .Q15(\NLW_blk00000003/blk00000b10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0f ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0c ), + .Q(\blk00000003/sig00000817 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/sig00000b0c ), + .Q15(\NLW_blk00000003/blk00000b0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0d ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0b ), + .Q(\blk00000003/sig00000816 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/sig00000b0b ), + .Q15(\NLW_blk00000003/blk00000b0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b0b ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b0a ), + .Q(\blk00000003/sig00000818 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b0a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/sig00000b0a ), + .Q15(\NLW_blk00000003/blk00000b0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b09 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b09 ), + .Q(\blk00000003/sig00000815 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b08 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/sig00000b09 ), + .Q15(\NLW_blk00000003/blk00000b08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b07 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b08 ), + .Q(\blk00000003/sig00000814 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b06 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/sig00000b08 ), + .Q15(\NLW_blk00000003/blk00000b06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b05 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b07 ), + .Q(\blk00000003/sig00000813 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b04 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/sig00000b07 ), + .Q15(\NLW_blk00000003/blk00000b04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b03 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b06 ), + .Q(\blk00000003/sig00000812 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b02 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/sig00000b06 ), + .Q15(\NLW_blk00000003/blk00000b02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000b01 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b05 ), + .Q(\blk00000003/sig00000810 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000b00 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/sig00000b05 ), + .Q15(\NLW_blk00000003/blk00000b00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aff ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b04 ), + .Q(\blk00000003/sig0000080f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/sig00000b04 ), + .Q15(\NLW_blk00000003/blk00000afe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afd ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b03 ), + .Q(\blk00000003/sig00000811 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/sig00000b03 ), + .Q15(\NLW_blk00000003/blk00000afc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000afb ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b02 ), + .Q(\blk00000003/sig0000080d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000afa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/sig00000b02 ), + .Q15(\NLW_blk00000003/blk00000afa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af9 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b01 ), + .Q(\blk00000003/sig0000080c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/sig00000b01 ), + .Q15(\NLW_blk00000003/blk00000af8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af7 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000b00 ), + .Q(\blk00000003/sig0000080e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/sig00000b00 ), + .Q15(\NLW_blk00000003/blk00000af6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af5 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000aff ), + .Q(\blk00000003/sig0000080a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/sig00000aff ), + .Q15(\NLW_blk00000003/blk00000af4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af3 ( + .C(clk), + .CE(\blk00000003/sig000009b5 ), + .D(\blk00000003/sig00000afe ), + .Q(\blk00000003/sig0000080b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b5 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/sig00000afe ), + .Q15(\NLW_blk00000003/blk00000af2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000af1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afd ), + .Q(\blk00000003/sig00000937 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000af0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig00000afd ), + .Q15(\NLW_blk00000003/blk00000af0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afc ), + .Q(\blk00000003/sig000001c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aee ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a9a ), + .Q(\blk00000003/sig00000afc ), + .Q15(\NLW_blk00000003/blk00000aee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afb ), + .Q(\blk00000003/sig000001c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aec ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a98 ), + .Q(\blk00000003/sig00000afb ), + .Q15(\NLW_blk00000003/blk00000aec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aeb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000afa ), + .Q(\blk00000003/sig000001c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aea ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a96 ), + .Q(\blk00000003/sig00000afa ), + .Q15(\NLW_blk00000003/blk00000aea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af9 ), + .Q(\blk00000003/sig000001c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a94 ), + .Q(\blk00000003/sig00000af9 ), + .Q15(\NLW_blk00000003/blk00000ae8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af8 ), + .Q(\blk00000003/sig000001c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a92 ), + .Q(\blk00000003/sig00000af8 ), + .Q15(\NLW_blk00000003/blk00000ae6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af7 ), + .Q(\blk00000003/sig000001c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a90 ), + .Q(\blk00000003/sig00000af7 ), + .Q15(\NLW_blk00000003/blk00000ae4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8e ), + .Q(\blk00000003/sig00000af6 ), + .Q15(\NLW_blk00000003/blk00000ae2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ae1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af5 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ae0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8c ), + .Q(\blk00000003/sig00000af5 ), + .Q15(\NLW_blk00000003/blk00000ae0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af4 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ade ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a8a ), + .Q(\blk00000003/sig00000af4 ), + .Q15(\NLW_blk00000003/blk00000ade_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000add ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000adc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/sig00000af3 ), + .Q15(\NLW_blk00000003/blk00000adc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000adb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af2 ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ada ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/sig00000af2 ), + .Q15(\NLW_blk00000003/blk00000ada_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af1 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a88 ), + .Q(\blk00000003/sig00000af1 ), + .Q15(\NLW_blk00000003/blk00000ad8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/sig00000af0 ), + .Q15(\NLW_blk00000003/blk00000ad6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aef ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/sig00000aef ), + .Q15(\NLW_blk00000003/blk00000ad4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aee ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/sig00000aee ), + .Q15(\NLW_blk00000003/blk00000ad2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ad1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ad0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/sig00000aed ), + .Q15(\NLW_blk00000003/blk00000ad0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aec ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ace ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/sig00000aec ), + .Q15(\NLW_blk00000003/blk00000ace_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aeb ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000acc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/sig00000aeb ), + .Q15(\NLW_blk00000003/blk00000acc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000acb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aca ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/sig00000aea ), + .Q15(\NLW_blk00000003/blk00000aca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae9 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000ae9 ), + .Q15(\NLW_blk00000003/blk00000ac8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae8 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/sig00000ae8 ), + .Q15(\NLW_blk00000003/blk00000ac6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000ae7 ), + .Q15(\NLW_blk00000003/blk00000ac4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae6 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000ae6 ), + .Q15(\NLW_blk00000003/blk00000ac2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ac1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae5 ), + .Q(\blk00000003/sig00000152 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ac0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000ae5 ), + .Q15(\NLW_blk00000003/blk00000ac0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abe ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000ae4 ), + .Q15(\NLW_blk00000003/blk00000abe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae3 ), + .Q(\blk00000003/sig00000150 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000ae3 ), + .Q15(\NLW_blk00000003/blk00000abc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae2 ), + .Q(\blk00000003/sig0000014f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aba ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000ae2 ), + .Q15(\NLW_blk00000003/blk00000aba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/sig00000151 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000ae1 ), + .Q15(\NLW_blk00000003/blk00000ab8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ae0 ), + .Q(\blk00000003/sig0000014d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/sig00000ae0 ), + .Q15(\NLW_blk00000003/blk00000ab6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adf ), + .Q(\blk00000003/sig0000014c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000adf ), + .Q15(\NLW_blk00000003/blk00000ab4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/sig0000014e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000ade ), + .Q15(\NLW_blk00000003/blk00000ab2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ab1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000add ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000ab0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000add ), + .Q15(\NLW_blk00000003/blk00000ab0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aaf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adc ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aae ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/sig00000adc ), + .Q15(\NLW_blk00000003/blk00000aae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aac ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/sig00000adb ), + .Q15(\NLW_blk00000003/blk00000aac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ada ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aaa ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/sig00000ada ), + .Q15(\NLW_blk00000003/blk00000aaa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad9 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa8 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/sig00000ad9 ), + .Q15(\NLW_blk00000003/blk00000aa8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa6 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/sig00000ad8 ), + .Q15(\NLW_blk00000003/blk00000aa6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad7 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa4 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/sig00000ad7 ), + .Q15(\NLW_blk00000003/blk00000aa4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad6 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa2 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a48 ), + .Q(\blk00000003/sig00000ad6 ), + .Q15(\NLW_blk00000003/blk00000aa2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000aa0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/sig00000ad5 ), + .Q15(\NLW_blk00000003/blk00000aa0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad4 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/sig00000ad4 ), + .Q15(\NLW_blk00000003/blk00000a9e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad3 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a42 ), + .Q(\blk00000003/sig00000ad3 ), + .Q15(\NLW_blk00000003/blk00000a9c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a46 ), + .Q(\blk00000003/sig00000ad2 ), + .Q15(\NLW_blk00000003/blk00000a9a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a99 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad1 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a98 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/sig00000ad1 ), + .Q15(\NLW_blk00000003/blk00000a98_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a97 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ad0 ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a96 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a44 ), + .Q(\blk00000003/sig00000ad0 ), + .Q15(\NLW_blk00000003/blk00000a96_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a95 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a94 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3c ), + .Q(\blk00000003/sig00000acf ), + .Q15(\NLW_blk00000003/blk00000a94_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a93 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000ace ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a92 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a40 ), + .Q(\blk00000003/sig00000ace ), + .Q15(\NLW_blk00000003/blk00000a92_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000acd ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a90 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000a3e ), + .Q(\blk00000003/sig00000acd ), + .Q15(\NLW_blk00000003/blk00000a90_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/sig000007d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/sig00000acc ), + .Q15(\NLW_blk00000003/blk00000a8e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000acb ), + .Q(\blk00000003/sig000007d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/sig00000acb ), + .Q15(\NLW_blk00000003/blk00000a8c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aca ), + .Q(\blk00000003/sig000007d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a8a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/sig00000aca ), + .Q15(\NLW_blk00000003/blk00000a8a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a89 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/sig000007d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a88 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/sig00000ac9 ), + .Q15(\NLW_blk00000003/blk00000a88_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a87 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac8 ), + .Q(\blk00000003/sig000007d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a86 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/sig00000ac8 ), + .Q15(\NLW_blk00000003/blk00000a86_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a85 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac7 ), + .Q(\blk00000003/sig000007d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a84 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/sig00000ac7 ), + .Q15(\NLW_blk00000003/blk00000a84_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a83 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac6 ), + .Q(\blk00000003/sig000007d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a82 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk00000a82_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a81 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac5 ), + .Q(\blk00000003/sig000007d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a80 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk00000a80_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac4 ), + .Q(\blk00000003/sig000007d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk00000a7e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac3 ), + .Q(\blk00000003/sig000007cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk00000a7c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac2 ), + .Q(\blk00000003/sig000007ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a7a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk00000a7a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a79 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac1 ), + .Q(\blk00000003/sig000007d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a78 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk00000a78_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a77 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ac0 ), + .Q(\blk00000003/sig000007cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a76 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk00000a76_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a75 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abf ), + .Q(\blk00000003/sig000007cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a74 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/sig00000abf ), + .Q15(\NLW_blk00000003/blk00000a74_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a73 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abe ), + .Q(\blk00000003/sig000007cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a72 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/sig00000abe ), + .Q15(\NLW_blk00000003/blk00000a72_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a71 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abd ), + .Q(\blk00000003/sig000007c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a70 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/sig00000abd ), + .Q15(\NLW_blk00000003/blk00000a70_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abc ), + .Q(\blk00000003/sig000007c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/sig00000abc ), + .Q15(\NLW_blk00000003/blk00000a6e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000abb ), + .Q(\blk00000003/sig000007ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/sig00000abb ), + .Q15(\NLW_blk00000003/blk00000a6c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aba ), + .Q(\blk00000003/sig000007c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a6a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/sig00000aba ), + .Q15(\NLW_blk00000003/blk00000a6a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a69 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab9 ), + .Q(\blk00000003/sig000007c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a68 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk00000a68_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a67 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab8 ), + .Q(\blk00000003/sig000007c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a66 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk00000a66_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a65 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab7 ), + .Q(\blk00000003/sig000007c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a64 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk00000a64_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a63 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab6 ), + .Q(\blk00000003/sig000007c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a62 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk00000a62_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a61 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab5 ), + .Q(\blk00000003/sig000007c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a60 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk00000a60_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab4 ), + .Q(\blk00000003/sig000007f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk00000a5e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab3 ), + .Q(\blk00000003/sig000007f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk00000a5c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a5b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab2 ), + .Q(\blk00000003/sig000007ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a5a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk00000a5a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a59 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab1 ), + .Q(\blk00000003/sig000007ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a58 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk00000a58_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a57 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000ab0 ), + .Q(\blk00000003/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a56 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk00000a56_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a55 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaf ), + .Q(\blk00000003/sig000007eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a54 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/sig00000aaf ), + .Q15(\NLW_blk00000003/blk00000a54_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a53 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aae ), + .Q(\blk00000003/sig000007ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a52 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/sig00000aae ), + .Q15(\NLW_blk00000003/blk00000a52_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a51 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aad ), + .Q(\blk00000003/sig000007ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a50 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/sig00000aad ), + .Q15(\NLW_blk00000003/blk00000a50_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aac ), + .Q(\blk00000003/sig000007e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/sig00000aac ), + .Q15(\NLW_blk00000003/blk00000a4e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aab ), + .Q(\blk00000003/sig000007e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/sig00000aab ), + .Q15(\NLW_blk00000003/blk00000a4c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a4b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aaa ), + .Q(\blk00000003/sig000007e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a4a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/sig00000aaa ), + .Q15(\NLW_blk00000003/blk00000a4a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a49 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa9 ), + .Q(\blk00000003/sig000007e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a48 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/sig00000aa9 ), + .Q15(\NLW_blk00000003/blk00000a48_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a47 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa8 ), + .Q(\blk00000003/sig000007e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a46 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/sig00000aa8 ), + .Q15(\NLW_blk00000003/blk00000a46_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a45 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa7 ), + .Q(\blk00000003/sig000007e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a44 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/sig00000aa7 ), + .Q15(\NLW_blk00000003/blk00000a44_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a43 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa6 ), + .Q(\blk00000003/sig000007e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a42 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/sig00000aa6 ), + .Q15(\NLW_blk00000003/blk00000a42_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a41 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa5 ), + .Q(\blk00000003/sig000007e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a40 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/sig00000aa5 ), + .Q15(\NLW_blk00000003/blk00000a40_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3f ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa4 ), + .Q(\blk00000003/sig000007e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/sig00000aa4 ), + .Q15(\NLW_blk00000003/blk00000a3e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3d ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa3 ), + .Q(\blk00000003/sig000007e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/sig00000aa3 ), + .Q15(\NLW_blk00000003/blk00000a3c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a3b ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa2 ), + .Q(\blk00000003/sig000007de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a3a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/sig00000aa2 ), + .Q15(\NLW_blk00000003/blk00000a3a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a39 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa1 ), + .Q(\blk00000003/sig000007dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a38 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/sig00000aa1 ), + .Q15(\NLW_blk00000003/blk00000a38_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a37 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000aa0 ), + .Q(\blk00000003/sig000007df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a36 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/sig00000aa0 ), + .Q15(\NLW_blk00000003/blk00000a36_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a35 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9f ), + .Q(\blk00000003/sig000007db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a34 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/sig00000a9f ), + .Q15(\NLW_blk00000003/blk00000a34_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a33 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9e ), + .Q(\blk00000003/sig000007da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a32 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/sig00000a9e ), + .Q15(\NLW_blk00000003/blk00000a32_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a31 ( + .C(clk), + .CE(\blk00000003/sig000009b4 ), + .D(\blk00000003/sig00000a9d ), + .Q(\blk00000003/sig000007dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a30 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig000009b4 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/sig00000a9d ), + .Q15(\NLW_blk00000003/blk00000a30_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9c ), + .Q(\blk00000003/sig00000761 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001de ), + .Q(\blk00000003/sig00000a9c ), + .Q15(\NLW_blk00000003/blk00000a2e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a9b ), + .Q(\blk00000003/sig000009ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ca ), + .Q(\blk00000003/sig00000a9b ), + .Q15(\NLW_blk00000003/blk00000a2c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a2b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a99 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a2a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a99 ), + .Q15(\NLW_blk00000003/blk00000a2a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a29 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a97 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a28 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a97 ), + .Q15(\NLW_blk00000003/blk00000a28_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a27 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a95 ), + .Q(\blk00000003/sig00000a96 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a26 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a95 ), + .Q15(\NLW_blk00000003/blk00000a26_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a25 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a93 ), + .Q(\blk00000003/sig00000a94 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a24 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a93 ), + .Q15(\NLW_blk00000003/blk00000a24_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a23 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a91 ), + .Q(\blk00000003/sig00000a92 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a22 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a91 ), + .Q15(\NLW_blk00000003/blk00000a22_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a21 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8f ), + .Q(\blk00000003/sig00000a90 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a20 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a8f ), + .Q15(\NLW_blk00000003/blk00000a20_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8d ), + .Q(\blk00000003/sig00000a8e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a8d ), + .Q15(\NLW_blk00000003/blk00000a1e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a8b ), + .Q(\blk00000003/sig00000a8c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a8b ), + .Q15(\NLW_blk00000003/blk00000a1c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a1b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a89 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a1a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a89 ), + .Q15(\NLW_blk00000003/blk00000a1a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a19 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a18 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a87 ), + .Q15(\NLW_blk00000003/blk00000a18_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a17 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/sig00000a86 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a16 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a85 ), + .Q15(\NLW_blk00000003/blk00000a16_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a15 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/sig00000a84 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a14 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000a83 ), + .Q15(\NLW_blk00000003/blk00000a14_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a13 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/sig00000a82 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a12 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000a81 ), + .Q15(\NLW_blk00000003/blk00000a12_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a11 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/sig00000a80 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a10 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000a7f ), + .Q15(\NLW_blk00000003/blk00000a10_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0f ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/sig00000a7e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0e ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig00000a7d ), + .Q15(\NLW_blk00000003/blk00000a0e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0d ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/sig00000a7c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0c ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000a7b ), + .Q15(\NLW_blk00000003/blk00000a0c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a0b ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/sig00000a7a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a0a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000a79 ), + .Q15(\NLW_blk00000003/blk00000a0a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a09 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a08 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000a77 ), + .Q15(\NLW_blk00000003/blk00000a08_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a07 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/sig00000a76 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a06 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000a75 ), + .Q15(\NLW_blk00000003/blk00000a06_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a05 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/sig00000a74 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a04 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000a73 ), + .Q15(\NLW_blk00000003/blk00000a04_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a03 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a02 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000a71 ), + .Q15(\NLW_blk00000003/blk00000a02_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a01 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000a70 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a00 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000a6f ), + .Q15(\NLW_blk00000003/blk00000a00_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ff ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000a6e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fe ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000a6d ), + .Q15(\NLW_blk00000003/blk000009fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000a6c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000a6b ), + .Q15(\NLW_blk00000003/blk000009fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009fb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009fa ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000a69 ), + .Q15(\NLW_blk00000003/blk000009fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000a68 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000a67 ), + .Q15(\NLW_blk00000003/blk000009f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000a66 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000a65 ), + .Q15(\NLW_blk00000003/blk000009f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000a64 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig00000a63 ), + .Q15(\NLW_blk00000003/blk000009f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000a61 ), + .Q15(\NLW_blk00000003/blk000009f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009f1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000a60 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig00000a5f ), + .Q15(\NLW_blk00000003/blk000009f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ef ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/sig00000a5e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ee ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig00000a5d ), + .Q15(\NLW_blk00000003/blk000009ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ed ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/sig00000a5c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ec ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig00000a5b ), + .Q15(\NLW_blk00000003/blk000009ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009eb ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/sig00000a5a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ea ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig00000a59 ), + .Q15(\NLW_blk00000003/blk000009ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/sig00000a58 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig00000a57 ), + .Q15(\NLW_blk00000003/blk000009e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/sig00000a56 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig00000a55 ), + .Q15(\NLW_blk00000003/blk000009e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/sig00000a54 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig00000a53 ), + .Q15(\NLW_blk00000003/blk000009e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/sig00000a52 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig00000a51 ), + .Q15(\NLW_blk00000003/blk000009e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/sig00000a50 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig00000a4f ), + .Q15(\NLW_blk00000003/blk000009e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009df ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/sig00000a4e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009de ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig00000a4d ), + .Q15(\NLW_blk00000003/blk000009de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009dd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/sig00000a4c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009dc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig00000a4b ), + .Q15(\NLW_blk00000003/blk000009dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009db ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/sig00000a4a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009da ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig00000a49 ), + .Q15(\NLW_blk00000003/blk000009da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d9 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a47 ), + .Q(\blk00000003/sig00000a48 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig00000a47 ), + .Q15(\NLW_blk00000003/blk000009d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d7 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a45 ), + .Q(\blk00000003/sig00000a46 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig00000a45 ), + .Q15(\NLW_blk00000003/blk000009d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d5 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a43 ), + .Q(\blk00000003/sig00000a44 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig00000a43 ), + .Q15(\NLW_blk00000003/blk000009d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d3 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a41 ), + .Q(\blk00000003/sig00000a42 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig00000a41 ), + .Q15(\NLW_blk00000003/blk000009d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009d1 ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3f ), + .Q(\blk00000003/sig00000a40 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig00000a3f ), + .Q15(\NLW_blk00000003/blk000009d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cf ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3d ), + .Q(\blk00000003/sig00000a3e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ce ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig00000a3d ), + .Q15(\NLW_blk00000003/blk000009ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cd ( + .C(clk), + .CE(\blk00000003/sig000009b8 ), + .D(\blk00000003/sig00000a3b ), + .Q(\blk00000003/sig00000a3c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009cc ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(NlwRenamedSig_OI_rfd), + .CE(\blk00000003/sig000009b8 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig00000a3b ), + .Q15(\NLW_blk00000003/blk000009cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009cb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a3a ), + .Q(\blk00000003/sig000007a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/sig00000a3a ), + .Q15(\NLW_blk00000003/blk000009ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a39 ), + .Q(\blk00000003/sig000007a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/sig00000a39 ), + .Q15(\NLW_blk00000003/blk000009c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a38 ), + .Q(\blk00000003/sig000007a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/sig00000a38 ), + .Q15(\NLW_blk00000003/blk000009c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a37 ), + .Q(\blk00000003/sig000007a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/sig00000a37 ), + .Q15(\NLW_blk00000003/blk000009c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a36 ), + .Q(\blk00000003/sig000007a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/sig00000a36 ), + .Q15(\NLW_blk00000003/blk000009c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009c1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a35 ), + .Q(\blk00000003/sig000007a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/sig00000a35 ), + .Q15(\NLW_blk00000003/blk000009c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bf ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a34 ), + .Q(\blk00000003/sig000007a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/sig00000a34 ), + .Q15(\NLW_blk00000003/blk000009be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bd ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a33 ), + .Q(\blk00000003/sig000007a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/sig00000a33 ), + .Q15(\NLW_blk00000003/blk000009bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a32 ), + .Q(\blk00000003/sig000007a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/sig00000a32 ), + .Q15(\NLW_blk00000003/blk000009ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a31 ), + .Q(\blk00000003/sig000007a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/sig00000a31 ), + .Q15(\NLW_blk00000003/blk000009b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a30 ), + .Q(\blk00000003/sig0000079f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/sig00000a30 ), + .Q15(\NLW_blk00000003/blk000009b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2f ), + .Q(\blk00000003/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/sig00000a2f ), + .Q15(\NLW_blk00000003/blk000009b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2e ), + .Q(\blk00000003/sig0000079c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/sig00000a2e ), + .Q15(\NLW_blk00000003/blk000009b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009b1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2d ), + .Q(\blk00000003/sig0000079e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/sig00000a2d ), + .Q15(\NLW_blk00000003/blk000009b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009af ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2c ), + .Q(\blk00000003/sig0000079a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/sig00000a2c ), + .Q15(\NLW_blk00000003/blk000009ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ad ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2b ), + .Q(\blk00000003/sig00000799 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/sig00000a2b ), + .Q15(\NLW_blk00000003/blk000009ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009ab ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a2a ), + .Q(\blk00000003/sig0000079b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/sig00000a2a ), + .Q15(\NLW_blk00000003/blk000009aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a9 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a29 ), + .Q(\blk00000003/sig00000797 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000a29 ), + .Q15(\NLW_blk00000003/blk000009a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a7 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a28 ), + .Q(\blk00000003/sig00000796 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000a28 ), + .Q15(\NLW_blk00000003/blk000009a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a5 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a27 ), + .Q(\blk00000003/sig00000798 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/sig00000a27 ), + .Q15(\NLW_blk00000003/blk000009a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a3 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a26 ), + .Q(\blk00000003/sig00000794 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig00000a26 ), + .Q15(\NLW_blk00000003/blk000009a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009a1 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a25 ), + .Q(\blk00000003/sig00000793 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig00000a25 ), + .Q15(\NLW_blk00000003/blk000009a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a24 ), + .Q(\blk00000003/sig00000795 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig00000a24 ), + .Q15(\NLW_blk00000003/blk0000099e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a23 ), + .Q(\blk00000003/sig00000792 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig00000a23 ), + .Q15(\NLW_blk00000003/blk0000099c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000099b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a22 ), + .Q(\blk00000003/sig000007c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000099a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/sig00000a22 ), + .Q15(\NLW_blk00000003/blk0000099a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000999 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a21 ), + .Q(\blk00000003/sig000007bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000998 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000998_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000997 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a20 ), + .Q(\blk00000003/sig000007c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000996 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000996_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000995 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1f ), + .Q(\blk00000003/sig000007bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000994 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000994_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000993 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1e ), + .Q(\blk00000003/sig000007bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000992 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000992_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000991 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1d ), + .Q(\blk00000003/sig000007be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000990 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000990_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1c ), + .Q(\blk00000003/sig000007ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/sig00000a1c ), + .Q15(\NLW_blk00000003/blk0000098e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1b ), + .Q(\blk00000003/sig000007b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/sig00000a1b ), + .Q15(\NLW_blk00000003/blk0000098c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a1a ), + .Q(\blk00000003/sig000007bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/sig00000a1a ), + .Q15(\NLW_blk00000003/blk0000098a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000989 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a19 ), + .Q(\blk00000003/sig000007b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000988 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000988_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000987 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a18 ), + .Q(\blk00000003/sig000007b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000986 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000986_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000985 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a17 ), + .Q(\blk00000003/sig000007b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000984 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000984_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000983 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a16 ), + .Q(\blk00000003/sig000007b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000982 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000982_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000981 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a15 ), + .Q(\blk00000003/sig000007b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000980 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000980_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a14 ), + .Q(\blk00000003/sig000007b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/sig00000a14 ), + .Q15(\NLW_blk00000003/blk0000097e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a13 ), + .Q(\blk00000003/sig000007b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/sig00000a13 ), + .Q15(\NLW_blk00000003/blk0000097c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000097b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a12 ), + .Q(\blk00000003/sig000007b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000097a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/sig00000a12 ), + .Q15(\NLW_blk00000003/blk0000097a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000979 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a11 ), + .Q(\blk00000003/sig000007b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000978 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000978_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000977 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a10 ), + .Q(\blk00000003/sig000007af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000976 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/sig00000a10 ), + .Q15(\NLW_blk00000003/blk00000976_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000975 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0f ), + .Q(\blk00000003/sig000007ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000974 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/sig00000a0f ), + .Q15(\NLW_blk00000003/blk00000974_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000973 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0e ), + .Q(\blk00000003/sig000007ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000972 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/sig00000a0e ), + .Q15(\NLW_blk00000003/blk00000972_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000971 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0d ), + .Q(\blk00000003/sig000007ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000970 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/sig00000a0d ), + .Q15(\NLW_blk00000003/blk00000970_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0c ), + .Q(\blk00000003/sig000007aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/sig00000a0c ), + .Q15(\NLW_blk00000003/blk0000096e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a0b ), + .Q(\blk00000003/sig00000869 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig00000a0b ), + .Q15(\NLW_blk00000003/blk0000096c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000096b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000a0a ), + .Q(\blk00000003/sig000007ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000096a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(\blk00000003/sig0000091e ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/sig00000a0a ), + .Q15(\NLW_blk00000003/blk0000096a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000969 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a09 ), + .Q(\blk00000003/sig00000867 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000968 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig00000a09 ), + .Q15(\NLW_blk00000003/blk00000968_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000967 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a08 ), + .Q(\blk00000003/sig00000866 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000966 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000a08 ), + .Q15(\NLW_blk00000003/blk00000966_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000965 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a07 ), + .Q(\blk00000003/sig00000868 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000964 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig00000a07 ), + .Q15(\NLW_blk00000003/blk00000964_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000963 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a06 ), + .Q(\blk00000003/sig00000865 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000962 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000a06 ), + .Q15(\NLW_blk00000003/blk00000962_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a05 ), + .Q(\blk00000003/sig00000864 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000960 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000a05 ), + .Q15(\NLW_blk00000003/blk00000960_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a04 ), + .Q(\blk00000003/sig00000863 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000a04 ), + .Q15(\NLW_blk00000003/blk0000095e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a03 ), + .Q(\blk00000003/sig00000862 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000a03 ), + .Q15(\NLW_blk00000003/blk0000095c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000095b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a02 ), + .Q(\blk00000003/sig00000860 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000095a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000a02 ), + .Q15(\NLW_blk00000003/blk0000095a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000959 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a01 ), + .Q(\blk00000003/sig0000085f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000958 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000a01 ), + .Q15(\NLW_blk00000003/blk00000958_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000957 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000a00 ), + .Q(\blk00000003/sig00000861 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000956 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000a00 ), + .Q15(\NLW_blk00000003/blk00000956_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000955 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ff ), + .Q(\blk00000003/sig0000085d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000954 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000009ff ), + .Q15(\NLW_blk00000003/blk00000954_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000953 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fe ), + .Q(\blk00000003/sig0000085c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000952 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000009fe ), + .Q15(\NLW_blk00000003/blk00000952_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000951 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fd ), + .Q(\blk00000003/sig0000085e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000950 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000009fd ), + .Q15(\NLW_blk00000003/blk00000950_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fc ), + .Q(\blk00000003/sig0000085a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000009fc ), + .Q15(\NLW_blk00000003/blk0000094e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fb ), + .Q(\blk00000003/sig00000859 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000009fb ), + .Q15(\NLW_blk00000003/blk0000094c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000094b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009fa ), + .Q(\blk00000003/sig0000085b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000094a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000009fa ), + .Q15(\NLW_blk00000003/blk0000094a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000949 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f9 ), + .Q(\blk00000003/sig00000858 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000948 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000009f9 ), + .Q15(\NLW_blk00000003/blk00000948_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000947 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f8 ), + .Q(\blk00000003/sig00000857 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000946 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000009f8 ), + .Q15(\NLW_blk00000003/blk00000946_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000945 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f7 ), + .Q(\blk00000003/sig00000856 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000944 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000009f7 ), + .Q15(\NLW_blk00000003/blk00000944_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000943 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f6 ), + .Q(\blk00000003/sig00000855 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000942 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000009f6 ), + .Q15(\NLW_blk00000003/blk00000942_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000941 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f5 ), + .Q(\blk00000003/sig00000853 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000940 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000009f5 ), + .Q15(\NLW_blk00000003/blk00000940_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f4 ), + .Q(\blk00000003/sig00000852 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000009f4 ), + .Q15(\NLW_blk00000003/blk0000093e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f3 ), + .Q(\blk00000003/sig00000854 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000009f3 ), + .Q15(\NLW_blk00000003/blk0000093c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000093b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f2 ), + .Q(\blk00000003/sig00000898 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000093a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000009f2 ), + .Q15(\NLW_blk00000003/blk0000093a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000939 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f1 ), + .Q(\blk00000003/sig00000897 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000938 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000009f1 ), + .Q15(\NLW_blk00000003/blk00000938_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000937 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009f0 ), + .Q(\blk00000003/sig00000899 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000936 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000009f0 ), + .Q15(\NLW_blk00000003/blk00000936_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000935 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ef ), + .Q(\blk00000003/sig00000895 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000934 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000009ef ), + .Q15(\NLW_blk00000003/blk00000934_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000933 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ee ), + .Q(\blk00000003/sig00000894 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000932 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000009ee ), + .Q15(\NLW_blk00000003/blk00000932_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000931 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ed ), + .Q(\blk00000003/sig00000896 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000930 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000009ed ), + .Q15(\NLW_blk00000003/blk00000930_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ec ), + .Q(\blk00000003/sig00000893 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000009ec ), + .Q15(\NLW_blk00000003/blk0000092e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009eb ), + .Q(\blk00000003/sig00000892 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000009eb ), + .Q15(\NLW_blk00000003/blk0000092c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000092b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ea ), + .Q(\blk00000003/sig00000891 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000092a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000009ea ), + .Q15(\NLW_blk00000003/blk0000092a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000929 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e9 ), + .Q(\blk00000003/sig00000890 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000928 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000009e9 ), + .Q15(\NLW_blk00000003/blk00000928_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000927 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e8 ), + .Q(\blk00000003/sig0000088e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000926 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000009e8 ), + .Q15(\NLW_blk00000003/blk00000926_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000925 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e7 ), + .Q(\blk00000003/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000924 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000009e7 ), + .Q15(\NLW_blk00000003/blk00000924_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000923 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/sig0000088f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000922 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000009e6 ), + .Q15(\NLW_blk00000003/blk00000922_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e5 ), + .Q(\blk00000003/sig0000088b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000920 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000009e5 ), + .Q15(\NLW_blk00000003/blk00000920_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/sig0000088a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000009e4 ), + .Q15(\NLW_blk00000003/blk0000091e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e3 ), + .Q(\blk00000003/sig0000088c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000009e3 ), + .Q15(\NLW_blk00000003/blk0000091c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/sig00000888 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000091a ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000009e2 ), + .Q15(\NLW_blk00000003/blk0000091a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000919 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e1 ), + .Q(\blk00000003/sig00000887 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000918 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000009e1 ), + .Q15(\NLW_blk00000003/blk00000918_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000917 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/sig00000889 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000916 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000009e0 ), + .Q15(\NLW_blk00000003/blk00000916_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000915 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009df ), + .Q(\blk00000003/sig00000886 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000914 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000009df ), + .Q15(\NLW_blk00000003/blk00000914_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/sig00000885 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000912 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000009de ), + .Q15(\NLW_blk00000003/blk00000912_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dd ), + .Q(\blk00000003/sig00000884 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000910 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000009dd ), + .Q15(\NLW_blk00000003/blk00000910_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/sig00000883 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090e ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000009dc ), + .Q15(\NLW_blk00000003/blk0000090e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009db ), + .Q(\blk00000003/sig000002a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090c ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d5 ), + .Q(\blk00000003/sig000009db ), + .Q15(\NLW_blk00000003/blk0000090c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/sig000002a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000090a ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000029e ), + .Q(\blk00000003/sig000009da ), + .Q15(\NLW_blk00000003/blk0000090a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d9 ), + .Q(\blk00000003/sig00000882 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000908 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000908_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000907 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/sig000008c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000906 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000906_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d7 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000904 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000904_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d6 ), + .Q(\blk00000003/sig000009b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000902 ( + .A0(\blk00000003/sig00000049 ), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d1 ), + .Q(\blk00000003/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000902_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d5 ), + .Q(\blk00000003/sig000008c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000900 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000900_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d4 ), + .Q(\blk00000003/sig000008bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig000009d4 ), + .Q15(\NLW_blk00000003/blk000008fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d3 ), + .Q(\blk00000003/sig000008c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig000009d3 ), + .Q15(\NLW_blk00000003/blk000008fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d2 ), + .Q(\blk00000003/sig000008be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig000009d2 ), + .Q15(\NLW_blk00000003/blk000008fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d1 ), + .Q(\blk00000003/sig000008bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig000009d1 ), + .Q15(\NLW_blk00000003/blk000008f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009d0 ), + .Q(\blk00000003/sig000008bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig000009d0 ), + .Q15(\NLW_blk00000003/blk000008f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cf ), + .Q(\blk00000003/sig000008bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig000009cf ), + .Q15(\NLW_blk00000003/blk000008f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ce ), + .Q(\blk00000003/sig000008b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig000009ce ), + .Q15(\NLW_blk00000003/blk000008f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cd ), + .Q(\blk00000003/sig000008b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig000009cd ), + .Q15(\NLW_blk00000003/blk000008f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cc ), + .Q(\blk00000003/sig000008ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig000009cc ), + .Q15(\NLW_blk00000003/blk000008ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009cb ), + .Q(\blk00000003/sig000008b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig000009cb ), + .Q15(\NLW_blk00000003/blk000008ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009ca ), + .Q(\blk00000003/sig000008b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig000009ca ), + .Q15(\NLW_blk00000003/blk000008ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c9 ), + .Q(\blk00000003/sig000008b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig000009c9 ), + .Q15(\NLW_blk00000003/blk000008e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c8 ), + .Q(\blk00000003/sig000008b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig000009c8 ), + .Q15(\NLW_blk00000003/blk000008e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c7 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig000009c7 ), + .Q15(\NLW_blk00000003/blk000008e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c6 ), + .Q(\blk00000003/sig000008b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig000009c6 ), + .Q15(\NLW_blk00000003/blk000008e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c5 ), + .Q(\blk00000003/sig000001de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008e0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig000009c5 ), + .Q15(\NLW_blk00000003/blk000008e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c4 ), + .Q(\blk00000003/sig00000760 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(NlwRenamedSig_OI_rfd), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d7 ), + .Q(\blk00000003/sig000009c4 ), + .Q15(\NLW_blk00000003/blk000008de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009c3 ), + .Q(\blk00000003/sig0000091f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000008dc ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000009c3 ), + .Q15(\NLW_blk00000003/blk000008dc_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk000008db ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000275 ) + ); + INV \blk00000003/blk000008da ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000232 ) + ); + INV \blk00000003/blk000008d9 ( + .I(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000026e ) + ); + INV \blk00000003/blk000008d8 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000283 ) + ); + INV \blk00000003/blk000008d7 ( + .I(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000274 ) + ); + INV \blk00000003/blk000008d6 ( + .I(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009ab ) + ); + INV \blk00000003/blk000008d5 ( + .I(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000286 ) + ); + INV \blk00000003/blk000008d4 ( + .I(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026f ) + ); + INV \blk00000003/blk000008d3 ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000248 ) + ); + INV \blk00000003/blk000008d2 ( + .I(\blk00000003/sig00000223 ), + .O(\blk00000003/sig00000231 ) + ); + INV \blk00000003/blk000008d1 ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c1 ) + ); + INV \blk00000003/blk000008d0 ( + .I(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000001cb ) + ); + INV \blk00000003/blk000008cf ( + .I(\blk00000003/sig000000be ), + .O(\blk00000003/sig000000bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000009b0 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk000008cd ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig00000250 ), + .I2(coef_ld), + .O(\blk00000003/sig0000024c ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000008cc ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig00000241 ), + .I2(\blk00000003/sig00000250 ), + .I3(coef_ld), + .I4(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000244 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000008cb ( + .I0(coef_ld), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000024b ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk000008ca ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig00000227 ), + .I2(coef_we), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000255 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000008c9 ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(\blk00000003/sig00000250 ), + .I4(coef_ld), + .O(\blk00000003/sig0000024a ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c8 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig000009ba ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c7 ( + .I0(\blk00000003/sig0000027e ), + .I1(ce), + .I2(\blk00000003/sig00000241 ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig000009c2 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c6 ( + .I0(\blk00000003/sig00000285 ), + .I1(ce), + .I2(\blk00000003/sig0000023f ), + .I3(\blk00000003/sig00000276 ), + .O(\blk00000003/sig000009c1 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000008c5 ( + .I0(\blk00000003/sig000009af ), + .I1(ce), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig000009bc ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000008c4 ( + .I0(ce), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig000009b9 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000008c3 ( + .I0(\blk00000003/sig000001e7 ), + .I1(\blk00000003/sig000009ae ), + .I2(\blk00000003/sig000000ad ), + .I3(ce), + .I4(nd), + .O(\blk00000003/sig000009c0 ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c2 ( + .I0(\blk00000003/sig000001e2 ), + .I1(\blk00000003/sig000001d7 ), + .I2(\blk00000003/sig000009be ), + .I3(ce), + .O(\blk00000003/sig000009bf ) + ); + LUT3 #( + .INIT ( 8'h6C )) + \blk00000003/blk000008c1 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000009be ), + .I2(ce), + .O(\blk00000003/sig000009bd ) + ); + LUT4 #( + .INIT ( 16'h6AAA )) + \blk00000003/blk000008c0 ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000000ad ), + .I2(ce), + .I3(nd), + .O(\blk00000003/sig000009bb ) + ); + LUT4 #( + .INIT ( 16'hECCC )) + \blk00000003/blk000008bf ( + .I0(coef_we), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000258 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008be ( + .C(clk), + .D(\blk00000003/sig000009c2 ), + .Q(\blk00000003/sig0000027e ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000008bd ( + .C(clk), + .D(\blk00000003/sig000009c1 ), + .Q(\blk00000003/sig00000285 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bc ( + .C(clk), + .D(\blk00000003/sig000009c0 ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008bb ( + .C(clk), + .D(\blk00000003/sig000009bf ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ba ( + .C(clk), + .D(\blk00000003/sig000009bd ), + .R(sclr), + .Q(\blk00000003/sig000009be ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b9 ( + .C(clk), + .D(\blk00000003/sig000009bc ), + .R(sclr), + .Q(\blk00000003/sig000009af ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000008b8 ( + .C(clk), + .D(\blk00000003/sig000009bb ), + .R(sclr), + .Q(\blk00000003/sig000009ae ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b7 ( + .I0(\blk00000003/sig00000935 ), + .O(\blk00000003/sig0000092f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b6 ( + .I0(\blk00000003/sig00000934 ), + .O(\blk00000003/sig0000092c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b5 ( + .I0(\blk00000003/sig00000933 ), + .O(\blk00000003/sig00000929 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b4 ( + .I0(\blk00000003/sig00000932 ), + .O(\blk00000003/sig00000926 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b3 ( + .I0(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000923 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b2 ( + .I0(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b1 ( + .I0(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000028e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008b0 ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig00000260 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008af ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000c2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000008ae ( + .I0(\blk00000003/sig000009ae ), + .O(\blk00000003/sig000000b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a5 ), + .R(sclr), + .Q(\blk00000003/sig000009aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000009a2 ), + .R(sclr), + .Q(\blk00000003/sig000009a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099f ), + .R(sclr), + .Q(\blk00000003/sig000009a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000099c ), + .R(sclr), + .Q(\blk00000003/sig000009a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000999 ), + .R(sclr), + .Q(\blk00000003/sig000009a6 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000921 ), + .S(sclr), + .Q(\blk00000003/sig00000936 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000930 ), + .S(sclr), + .Q(\blk00000003/sig00000935 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092d ), + .S(sclr), + .Q(\blk00000003/sig00000934 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000092a ), + .S(sclr), + .Q(\blk00000003/sig00000933 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000927 ), + .R(sclr), + .Q(\blk00000003/sig00000932 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000008a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000924 ), + .S(sclr), + .Q(\blk00000003/sig00000931 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a2 ), + .R(\blk00000003/sig000002a5 ), + .Q(\blk00000003/sig000002a0 ) + ); + FDR \blk00000003/blk000008a1 ( + .C(clk), + .D(\blk00000003/sig000009ba ), + .R(ce), + .Q(\blk00000003/sig000009b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029c ), + .R(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig0000029a ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .S(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig00000295 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000089e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028f ), + .S(sclr), + .Q(\blk00000003/sig00000294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000292 ), + .R(sclr), + .Q(\blk00000003/sig00000293 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000289 ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000089b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028c ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDR \blk00000003/blk0000089a ( + .C(clk), + .D(\blk00000003/sig000009b9 ), + .R(ce), + .Q(\blk00000003/sig000009b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000899 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000261 ), + .R(\blk00000003/sig00000264 ), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000898 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000897 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000259 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000896 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000256 ), + .R(coef_ld), + .Q(\blk00000003/sig0000025b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000895 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000225 ), + .R(coef_ld), + .Q(\blk00000003/sig00000223 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000894 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b4 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000893 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000998 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000892 ( + .I0(\blk00000003/sig000009a7 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000891 ( + .I0(\blk00000003/sig000009a8 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig0000099e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000890 ( + .I0(\blk00000003/sig000009a9 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000009a1 ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk0000088f ( + .I0(\blk00000003/sig000009aa ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000009a4 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000088e ( + .I0(\blk00000003/sig000001dc ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000996 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000994 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000995 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000993 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000088a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig00000991 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000889 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig00000992 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000888 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig00000990 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000887 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000098e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000886 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000098f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000885 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000098d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000884 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig0000098b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000883 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig0000098c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000882 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig0000098a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000881 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000988 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000880 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000989 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000987 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000985 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000986 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000984 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig00000982 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000087a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000983 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000879 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig00000981 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000878 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000097f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000877 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig00000980 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000876 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000097e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000875 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig0000097c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000874 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000097d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000873 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig0000097b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000872 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000979 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000871 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig0000097a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000870 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000978 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000976 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000977 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000975 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000973 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000974 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000086a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig00000972 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000869 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig00000970 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000868 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig00000971 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000867 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000096f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000866 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000134 ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000096d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000865 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000096e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000864 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000135 ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig0000096c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000863 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000137 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig0000096a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000862 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000136 ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig0000096b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000861 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000138 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000969 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000860 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000139 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000968 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000966 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000013a ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000967 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000965 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000963 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000964 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000085a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig00000962 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000859 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig00000960 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000858 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig00000961 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000857 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000095f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000856 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000095d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000855 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000095e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000854 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig0000095c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000853 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig0000095a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000852 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig0000095b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000851 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000959 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000850 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000957 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000958 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000956 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000954 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000955 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000953 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000084a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig00000951 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000849 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig00000952 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000848 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig00000950 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000847 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000094e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000846 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000094f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000845 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000094d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000844 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig0000094b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000843 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig0000094c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000842 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig0000094a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000841 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000948 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000840 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000949 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000947 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000945 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000946 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000944 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig00000942 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000083a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000943 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000839 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig00000941 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000838 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000093f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000837 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig00000940 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000836 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000093e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000835 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ad ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig0000093c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000834 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ac ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000093d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000833 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001ae ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig0000093b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000832 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b0 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000939 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000831 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001af ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig0000093a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000830 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001dc ), + .I2(\blk00000003/sig000001b1 ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000938 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000082f ( + .I0(\blk00000003/sig00000936 ), + .I1(\blk00000003/sig00000931 ), + .O(\blk00000003/sig00000920 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082e ( + .I0(ce), + .I1(\blk00000003/sig000001de ), + .O(\blk00000003/sig000009b8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082d ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/sig000009b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082c ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/sig000009b6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082b ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/sig000009b5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000082a ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/sig000009b4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000829 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/sig0000091e ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000828 ( + .I0(sclr), + .I1(\blk00000003/sig000009b3 ), + .O(\blk00000003/sig0000029d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000827 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .O(\blk00000003/sig00000298 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000826 ( + .I0(\blk00000003/sig00000295 ), + .I1(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig00000296 ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000825 ( + .I0(\blk00000003/sig000002a3 ), + .I1(\blk00000003/sig000009b2 ), + .I2(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000824 ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig000001d7 ), + .O(\blk00000003/sig00000291 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000823 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000822 ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig0000028b ) + ); + LUT3 #( + .INIT ( 8'hDA )) + \blk00000003/blk00000821 ( + .I0(nd), + .I1(\blk00000003/sig000000b2 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig00000288 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000820 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000247 ), + .O(\blk00000003/sig00000284 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081f ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig0000023f ), + .O(\blk00000003/sig00000281 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081e ( + .I0(\blk00000003/sig00000247 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000027f ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081d ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000081c ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081b ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000081a ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000819 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000247 ), + .I2(\blk00000003/sig00000243 ), + .O(\blk00000003/sig0000026c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000818 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000243 ), + .O(\blk00000003/sig00000268 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000817 ( + .I0(\blk00000003/sig00000241 ), + .I1(\blk00000003/sig00000243 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000026a ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000816 ( + .I0(\blk00000003/sig00000250 ), + .I1(\blk00000003/sig000009b1 ), + .O(\blk00000003/sig00000263 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000815 ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .I2(\blk00000003/sig0000022f ), + .O(\blk00000003/sig0000025a ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk00000814 ( + .I0(coef_we), + .I1(\blk00000003/sig0000025d ), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000252 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000813 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000246 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000812 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000811 ( + .I0(coef_we), + .I1(coef_ld), + .I2(\blk00000003/sig0000023b ), + .O(\blk00000003/sig0000024e ) + ); + LUT3 #( + .INIT ( 8'h20 )) + \blk00000003/blk00000810 ( + .I0(\blk00000003/sig0000025b ), + .I1(\blk00000003/sig0000025c ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022c ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk0000080f ( + .I0(\blk00000003/sig0000025c ), + .I1(\blk00000003/sig0000025b ), + .I2(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000022a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080e ( + .I0(coef_ld), + .I1(\blk00000003/sig00000250 ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk0000080d ( + .I0(coef_we), + .I1(\blk00000003/sig0000023b ), + .I2(\blk00000003/sig00000239 ), + .O(\blk00000003/sig0000021f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000080c ( + .I0(\blk00000003/sig00000223 ), + .I1(coef_we), + .O(\blk00000003/sig00000224 ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk0000080b ( + .I0(\blk00000003/sig0000023b ), + .I1(coef_we), + .I2(\blk00000003/sig0000022f ), + .I3(\blk00000003/sig00000227 ), + .I4(coef_ld), + .O(\blk00000003/sig0000023a ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk0000080a ( + .I0(\blk00000003/sig00000239 ), + .I1(\blk00000003/sig0000023b ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000238 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000809 ( + .I0(\blk00000003/sig000000ad ), + .I1(nd), + .O(\blk00000003/sig000001e6 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000808 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig000001dc ), + .O(\blk00000003/sig000001e4 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk00000807 ( + .I0(\blk00000003/sig000000c6 ), + .I1(\blk00000003/sig00000931 ), + .I2(\blk00000003/sig000009b0 ), + .O(\blk00000003/sig000000c7 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000806 ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig00000931 ), + .O(\blk00000003/sig000001dd ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk00000805 ( + .I0(\blk00000003/sig000009a6 ), + .I1(\blk00000003/sig000009a7 ), + .I2(\blk00000003/sig000009a8 ), + .I3(\blk00000003/sig000009a9 ), + .I4(\blk00000003/sig000009aa ), + .O(\blk00000003/sig000000c9 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000804 ( + .I0(\blk00000003/sig000001d7 ), + .I1(\blk00000003/sig000001ca ), + .I2(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000803 ( + .I0(\blk00000003/sig00000294 ), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001d8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000802 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000bc ), + .O(\blk00000003/sig000000bb ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000801 ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000000ba ), + .O(\blk00000003/sig000000b9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000800 ( + .I0(\blk00000003/sig000000b4 ), + .I1(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000000b5 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk000007ff ( + .I0(\blk00000003/sig000001ca ), + .I1(\blk00000003/sig000001e5 ), + .I2(\blk00000003/sig000001d5 ), + .I3(\blk00000003/sig000001d7 ), + .I4(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d4 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk000007fe ( + .I0(\blk00000003/sig000001d5 ), + .I1(\blk00000003/sig000009af ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001e5 ), + .O(\blk00000003/sig000001d0 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk000007fd ( + .I0(\blk00000003/sig000009ae ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000000b0 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk000007fc ( + .I0(\blk00000003/sig000001e5 ), + .I1(\blk00000003/sig000001d5 ), + .I2(\blk00000003/sig000001d7 ), + .I3(\blk00000003/sig000001d3 ), + .O(\blk00000003/sig000001d2 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk000007fb ( + .I0(\blk00000003/sig00000293 ), + .I1(\blk00000003/sig00000294 ), + .I2(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig000001da ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk000007fa ( + .I0(ce), + .I1(\blk00000003/sig000009ac ), + .I2(\blk00000003/sig000009ad ), + .I3(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b7 ) + ); + MUXCY \blk00000003/blk000007f9 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig000009ab ), + .O(\blk00000003/sig000009a3 ) + ); + MUXCY_L \blk00000003/blk000007f8 ( + .CI(\blk00000003/sig000009a3 ), + .DI(\blk00000003/sig000009aa ), + .S(\blk00000003/sig000009a4 ), + .LO(\blk00000003/sig000009a0 ) + ); + MUXCY_L \blk00000003/blk000007f7 ( + .CI(\blk00000003/sig000009a0 ), + .DI(\blk00000003/sig000009a9 ), + .S(\blk00000003/sig000009a1 ), + .LO(\blk00000003/sig0000099d ) + ); + MUXCY_L \blk00000003/blk000007f6 ( + .CI(\blk00000003/sig0000099d ), + .DI(\blk00000003/sig000009a8 ), + .S(\blk00000003/sig0000099e ), + .LO(\blk00000003/sig0000099a ) + ); + MUXCY_L \blk00000003/blk000007f5 ( + .CI(\blk00000003/sig0000099a ), + .DI(\blk00000003/sig000009a7 ), + .S(\blk00000003/sig0000099b ), + .LO(\blk00000003/sig00000997 ) + ); + MUXCY_D \blk00000003/blk000007f4 ( + .CI(\blk00000003/sig00000997 ), + .DI(\blk00000003/sig000009a6 ), + .S(\blk00000003/sig00000998 ), + .O(\NLW_blk00000003/blk000007f4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000007f4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000007f3 ( + .CI(\blk00000003/sig000009a3 ), + .LI(\blk00000003/sig000009a4 ), + .O(\blk00000003/sig000009a5 ) + ); + XORCY \blk00000003/blk000007f2 ( + .CI(\blk00000003/sig000009a0 ), + .LI(\blk00000003/sig000009a1 ), + .O(\blk00000003/sig000009a2 ) + ); + XORCY \blk00000003/blk000007f1 ( + .CI(\blk00000003/sig0000099d ), + .LI(\blk00000003/sig0000099e ), + .O(\blk00000003/sig0000099f ) + ); + XORCY \blk00000003/blk000007f0 ( + .CI(\blk00000003/sig0000099a ), + .LI(\blk00000003/sig0000099b ), + .O(\blk00000003/sig0000099c ) + ); + XORCY \blk00000003/blk000007ef ( + .CI(\blk00000003/sig00000997 ), + .LI(\blk00000003/sig00000998 ), + .O(\blk00000003/sig00000999 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000996 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000995 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000994 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000993 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000992 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000991 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000990 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000098a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000989 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000988 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000987 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000986 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000985 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000984 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000983 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000982 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000981 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000980 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000097a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000979 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000978 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000977 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000976 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000975 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000974 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000973 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000972 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000971 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000970 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000096a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000969 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000968 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000967 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000966 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000965 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000964 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000963 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000962 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000961 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000960 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000095a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000959 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000958 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000957 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000956 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000955 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000954 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000953 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000952 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000951 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000950 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000094a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000949 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000948 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000947 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000946 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000945 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000944 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000943 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000079a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000942 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000799 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000941 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000798 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000940 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000797 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000796 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000795 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000794 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000793 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000792 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000093a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000791 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000939 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000790 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000938 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000078f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig000001dc ) + ); + MUXCY_L \blk00000003/blk0000078e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000936 ), + .S(\blk00000003/sig00000920 ), + .LO(\blk00000003/sig0000092e ) + ); + MUXCY_L \blk00000003/blk0000078d ( + .CI(\blk00000003/sig0000092e ), + .DI(\blk00000003/sig00000935 ), + .S(\blk00000003/sig0000092f ), + .LO(\blk00000003/sig0000092b ) + ); + MUXCY_L \blk00000003/blk0000078c ( + .CI(\blk00000003/sig0000092b ), + .DI(\blk00000003/sig00000934 ), + .S(\blk00000003/sig0000092c ), + .LO(\blk00000003/sig00000928 ) + ); + MUXCY_L \blk00000003/blk0000078b ( + .CI(\blk00000003/sig00000928 ), + .DI(\blk00000003/sig00000933 ), + .S(\blk00000003/sig00000929 ), + .LO(\blk00000003/sig00000925 ) + ); + MUXCY_L \blk00000003/blk0000078a ( + .CI(\blk00000003/sig00000925 ), + .DI(\blk00000003/sig00000932 ), + .S(\blk00000003/sig00000926 ), + .LO(\blk00000003/sig00000922 ) + ); + MUXCY_D \blk00000003/blk00000789 ( + .CI(\blk00000003/sig00000922 ), + .DI(\blk00000003/sig00000931 ), + .S(\blk00000003/sig00000923 ), + .O(\NLW_blk00000003/blk00000789_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000789_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000788 ( + .CI(\blk00000003/sig0000092e ), + .LI(\blk00000003/sig0000092f ), + .O(\blk00000003/sig00000930 ) + ); + XORCY \blk00000003/blk00000787 ( + .CI(\blk00000003/sig0000092b ), + .LI(\blk00000003/sig0000092c ), + .O(\blk00000003/sig0000092d ) + ); + XORCY \blk00000003/blk00000786 ( + .CI(\blk00000003/sig00000928 ), + .LI(\blk00000003/sig00000929 ), + .O(\blk00000003/sig0000092a ) + ); + XORCY \blk00000003/blk00000785 ( + .CI(\blk00000003/sig00000925 ), + .LI(\blk00000003/sig00000926 ), + .O(\blk00000003/sig00000927 ) + ); + XORCY \blk00000003/blk00000784 ( + .CI(\blk00000003/sig00000922 ), + .LI(\blk00000003/sig00000923 ), + .O(\blk00000003/sig00000924 ) + ); + XORCY \blk00000003/blk00000783 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000920 ), + .O(\blk00000003/sig00000921 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000779 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000778 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000777 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000776 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000775 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000774 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig00000772 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig00000770 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000076e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c5 ), + .R(sclr), + .Q(\blk00000003/sig0000076c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c4 ), + .R(sclr), + .Q(\blk00000003/sig0000076b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c3 ), + .R(sclr), + .Q(\blk00000003/sig0000076a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c2 ), + .R(sclr), + .Q(\blk00000003/sig00000769 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c1 ), + .R(sclr), + .Q(\blk00000003/sig00000768 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003c0 ), + .R(sclr), + .Q(\blk00000003/sig00000767 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bf ), + .R(sclr), + .Q(\blk00000003/sig00000766 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003be ), + .R(sclr), + .Q(\blk00000003/sig00000765 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bd ), + .R(sclr), + .Q(\blk00000003/sig00000764 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bc ), + .R(sclr), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig000003bb ), + .R(sclr), + .Q(\blk00000003/sig00000762 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000432 ), + .R(sclr), + .Q(\blk00000003/sig00000791 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000431 ), + .R(sclr), + .Q(\blk00000003/sig00000790 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000430 ), + .R(sclr), + .Q(\blk00000003/sig0000078f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042f ), + .R(sclr), + .Q(\blk00000003/sig0000078e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000078d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042d ), + .R(sclr), + .Q(\blk00000003/sig0000078c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042c ), + .R(sclr), + .Q(\blk00000003/sig0000078b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042b ), + .R(sclr), + .Q(\blk00000003/sig0000078a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000042a ), + .R(sclr), + .Q(\blk00000003/sig00000789 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073a ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000429 ), + .R(sclr), + .Q(\blk00000003/sig00000788 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000428 ), + .R(sclr), + .Q(\blk00000003/sig00000787 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000427 ), + .R(sclr), + .Q(\blk00000003/sig00000786 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000426 ), + .R(sclr), + .Q(\blk00000003/sig00000785 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000736 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig00000784 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000734 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig00000782 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000732 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig00000780 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000730 ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig0000077e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072e ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig0000077c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig0000077b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072c ( + .C(clk), + .CE(\blk00000003/sig0000091e ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig0000077a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000295 ), + .R(sclr), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a0 ), + .R(sclr), + .Q(\blk00000003/sig0000075c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a6 ), + .R(sclr), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .R(sclr), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .R(sclr), + .Q(\blk00000003/sig0000075a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029a ), + .R(sclr), + .Q(\blk00000003/sig0000075e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .R(sclr), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .R(sclr), + .Q(\blk00000003/sig00000758 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .R(sclr), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .R(sclr), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .R(sclr), + .Q(\blk00000003/sig00000756 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .R(sclr), + .Q(\blk00000003/sig00000754 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .R(sclr), + .Q(\blk00000003/sig00000750 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .R(sclr), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .R(sclr), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .R(sclr), + .Q(\blk00000003/sig00000752 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .R(sclr), + .Q(\blk00000003/sig0000074e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .R(sclr), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .R(sclr), + .Q(\blk00000003/sig0000074c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .R(sclr), + .Q(\blk00000003/sig0000074a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .R(sclr), + .Q(\blk00000003/sig00000748 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .R(sclr), + .Q(\blk00000003/sig00000746 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .R(sclr), + .Q(\blk00000003/sig00000744 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .R(sclr), + .Q(\blk00000003/sig00000742 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .R(sclr), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .R(sclr), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .R(sclr), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .R(sclr), + .Q(\blk00000003/sig00000747 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .R(sclr), + .Q(\blk00000003/sig00000745 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .R(sclr), + .Q(\blk00000003/sig00000743 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000741 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000740 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000073a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000739 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000738 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000737 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000736 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000733 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000735 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000734 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000733 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f2 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f2_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f2_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f2_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f2_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f2_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f2_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f2_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f2_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000f2_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f2_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000703 , \blk00000003/sig00000703 , \blk00000003/sig00000704 , \blk00000003/sig00000705 , \blk00000003/sig00000706 , +\blk00000003/sig00000707 , \blk00000003/sig00000708 , \blk00000003/sig00000709 , \blk00000003/sig0000070a , \blk00000003/sig0000070b , +\blk00000003/sig0000070c , \blk00000003/sig0000070d , \blk00000003/sig0000070e , \blk00000003/sig0000070f , \blk00000003/sig00000710 , +\blk00000003/sig00000711 , \blk00000003/sig00000712 , \blk00000003/sig00000713 , \blk00000003/sig00000714 , \blk00000003/sig00000715 , +\blk00000003/sig00000716 , \blk00000003/sig00000717 , \blk00000003/sig00000718 , \blk00000003/sig00000719 , \blk00000003/sig0000071a }), + .P({\NLW_blk00000003/blk000000f2_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f2_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f2_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071b , +\blk00000003/sig0000071b , \blk00000003/sig0000071b , \blk00000003/sig0000071c , \blk00000003/sig0000071d , \blk00000003/sig0000071e , +\blk00000003/sig0000071f , \blk00000003/sig00000720 , \blk00000003/sig00000721 , \blk00000003/sig00000722 , \blk00000003/sig00000723 , +\blk00000003/sig00000724 , \blk00000003/sig00000725 , \blk00000003/sig00000726 , \blk00000003/sig00000727 , \blk00000003/sig00000728 , +\blk00000003/sig00000729 , \blk00000003/sig0000072a , \blk00000003/sig0000072b , \blk00000003/sig0000072c , \blk00000003/sig0000072d , +\blk00000003/sig0000072e , \blk00000003/sig0000072f , \blk00000003/sig00000730 , \blk00000003/sig00000731 , \blk00000003/sig00000732 }), + .PCOUT({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f1 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f1_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f1_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f1_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f1_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f1_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f1_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f1_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f1_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000f1_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f1_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000006a3 , \blk00000003/sig000006a3 , \blk00000003/sig000006a4 , \blk00000003/sig000006a5 , \blk00000003/sig000006a6 , +\blk00000003/sig000006a7 , \blk00000003/sig000006a8 , \blk00000003/sig000006a9 , \blk00000003/sig000006aa , \blk00000003/sig000006ab , +\blk00000003/sig000006ac , \blk00000003/sig000006ad , \blk00000003/sig000006ae , \blk00000003/sig000006af , \blk00000003/sig000006b0 , +\blk00000003/sig000006b1 , \blk00000003/sig000006b2 , \blk00000003/sig000006b3 , \blk00000003/sig000006b4 , \blk00000003/sig000006b5 , +\blk00000003/sig000006b6 , \blk00000003/sig000006b7 , \blk00000003/sig000006b8 , \blk00000003/sig000006b9 , \blk00000003/sig000006ba }), + .P({\NLW_blk00000003/blk000000f1_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f1_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f1_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bb , +\blk00000003/sig000006bb , \blk00000003/sig000006bb , \blk00000003/sig000006bc , \blk00000003/sig000006bd , \blk00000003/sig000006be , +\blk00000003/sig000006bf , \blk00000003/sig000006c0 , \blk00000003/sig000006c1 , \blk00000003/sig000006c2 , \blk00000003/sig000006c3 , +\blk00000003/sig000006c4 , \blk00000003/sig000006c5 , \blk00000003/sig000006c6 , \blk00000003/sig000006c7 , \blk00000003/sig000006c8 , +\blk00000003/sig000006c9 , \blk00000003/sig000006ca , \blk00000003/sig000006cb , \blk00000003/sig000006cc , \blk00000003/sig000006cd , +\blk00000003/sig000006ce , \blk00000003/sig000006cf , \blk00000003/sig000006d0 , \blk00000003/sig000006d1 , \blk00000003/sig000006d2 }), + .PCOUT({\blk00000003/sig000006d3 , \blk00000003/sig000006d4 , \blk00000003/sig000006d5 , \blk00000003/sig000006d6 , \blk00000003/sig000006d7 , +\blk00000003/sig000006d8 , \blk00000003/sig000006d9 , \blk00000003/sig000006da , \blk00000003/sig000006db , \blk00000003/sig000006dc , +\blk00000003/sig000006dd , \blk00000003/sig000006de , \blk00000003/sig000006df , \blk00000003/sig000006e0 , \blk00000003/sig000006e1 , +\blk00000003/sig000006e2 , \blk00000003/sig000006e3 , \blk00000003/sig000006e4 , \blk00000003/sig000006e5 , \blk00000003/sig000006e6 , +\blk00000003/sig000006e7 , \blk00000003/sig000006e8 , \blk00000003/sig000006e9 , \blk00000003/sig000006ea , \blk00000003/sig000006eb , +\blk00000003/sig000006ec , \blk00000003/sig000006ed , \blk00000003/sig000006ee , \blk00000003/sig000006ef , \blk00000003/sig000006f0 , +\blk00000003/sig000006f1 , \blk00000003/sig000006f2 , \blk00000003/sig000006f3 , \blk00000003/sig000006f4 , \blk00000003/sig000006f5 , +\blk00000003/sig000006f6 , \blk00000003/sig000006f7 , \blk00000003/sig000006f8 , \blk00000003/sig000006f9 , \blk00000003/sig000006fa , +\blk00000003/sig000006fb , \blk00000003/sig000006fc , \blk00000003/sig000006fd , \blk00000003/sig000006fe , \blk00000003/sig000006ff , +\blk00000003/sig00000700 , \blk00000003/sig00000701 , \blk00000003/sig00000702 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f0 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f0_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f0_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f0_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f0_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f0_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f0_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f0_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f0_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000f0_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f0_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000643 , \blk00000003/sig00000643 , \blk00000003/sig00000644 , \blk00000003/sig00000645 , \blk00000003/sig00000646 , +\blk00000003/sig00000647 , \blk00000003/sig00000648 , \blk00000003/sig00000649 , \blk00000003/sig0000064a , \blk00000003/sig0000064b , +\blk00000003/sig0000064c , \blk00000003/sig0000064d , \blk00000003/sig0000064e , \blk00000003/sig0000064f , \blk00000003/sig00000650 , +\blk00000003/sig00000651 , \blk00000003/sig00000652 , \blk00000003/sig00000653 , \blk00000003/sig00000654 , \blk00000003/sig00000655 , +\blk00000003/sig00000656 , \blk00000003/sig00000657 , \blk00000003/sig00000658 , \blk00000003/sig00000659 , \blk00000003/sig0000065a }), + .P({\NLW_blk00000003/blk000000f0_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f0_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f0_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065b , +\blk00000003/sig0000065b , \blk00000003/sig0000065b , \blk00000003/sig0000065c , \blk00000003/sig0000065d , \blk00000003/sig0000065e , +\blk00000003/sig0000065f , \blk00000003/sig00000660 , \blk00000003/sig00000661 , \blk00000003/sig00000662 , \blk00000003/sig00000663 , +\blk00000003/sig00000664 , \blk00000003/sig00000665 , \blk00000003/sig00000666 , \blk00000003/sig00000667 , \blk00000003/sig00000668 , +\blk00000003/sig00000669 , \blk00000003/sig0000066a , \blk00000003/sig0000066b , \blk00000003/sig0000066c , \blk00000003/sig0000066d , +\blk00000003/sig0000066e , \blk00000003/sig0000066f , \blk00000003/sig00000670 , \blk00000003/sig00000671 , \blk00000003/sig00000672 }), + .PCOUT({\blk00000003/sig00000673 , \blk00000003/sig00000674 , \blk00000003/sig00000675 , \blk00000003/sig00000676 , \blk00000003/sig00000677 , +\blk00000003/sig00000678 , \blk00000003/sig00000679 , \blk00000003/sig0000067a , \blk00000003/sig0000067b , \blk00000003/sig0000067c , +\blk00000003/sig0000067d , \blk00000003/sig0000067e , \blk00000003/sig0000067f , \blk00000003/sig00000680 , \blk00000003/sig00000681 , +\blk00000003/sig00000682 , \blk00000003/sig00000683 , \blk00000003/sig00000684 , \blk00000003/sig00000685 , \blk00000003/sig00000686 , +\blk00000003/sig00000687 , \blk00000003/sig00000688 , \blk00000003/sig00000689 , \blk00000003/sig0000068a , \blk00000003/sig0000068b , +\blk00000003/sig0000068c , \blk00000003/sig0000068d , \blk00000003/sig0000068e , \blk00000003/sig0000068f , \blk00000003/sig00000690 , +\blk00000003/sig00000691 , \blk00000003/sig00000692 , \blk00000003/sig00000693 , \blk00000003/sig00000694 , \blk00000003/sig00000695 , +\blk00000003/sig00000696 , \blk00000003/sig00000697 , \blk00000003/sig00000698 , \blk00000003/sig00000699 , \blk00000003/sig0000069a , +\blk00000003/sig0000069b , \blk00000003/sig0000069c , \blk00000003/sig0000069d , \blk00000003/sig0000069e , \blk00000003/sig0000069f , +\blk00000003/sig000006a0 , \blk00000003/sig000006a1 , \blk00000003/sig000006a2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ef ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ef_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ef_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ef_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ef_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ef_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ef_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ef_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ef_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000ef_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ef_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e4 , \blk00000003/sig000005e5 , \blk00000003/sig000005e6 , +\blk00000003/sig000005e7 , \blk00000003/sig000005e8 , \blk00000003/sig000005e9 , \blk00000003/sig000005ea , \blk00000003/sig000005eb , +\blk00000003/sig000005ec , \blk00000003/sig000005ed , \blk00000003/sig000005ee , \blk00000003/sig000005ef , \blk00000003/sig000005f0 , +\blk00000003/sig000005f1 , \blk00000003/sig000005f2 , \blk00000003/sig000005f3 , \blk00000003/sig000005f4 , \blk00000003/sig000005f5 , +\blk00000003/sig000005f6 , \blk00000003/sig000005f7 , \blk00000003/sig000005f8 , \blk00000003/sig000005f9 , \blk00000003/sig000005fa }), + .P({\NLW_blk00000003/blk000000ef_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ef_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ef_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fb , +\blk00000003/sig000005fb , \blk00000003/sig000005fb , \blk00000003/sig000005fc , \blk00000003/sig000005fd , \blk00000003/sig000005fe , +\blk00000003/sig000005ff , \blk00000003/sig00000600 , \blk00000003/sig00000601 , \blk00000003/sig00000602 , \blk00000003/sig00000603 , +\blk00000003/sig00000604 , \blk00000003/sig00000605 , \blk00000003/sig00000606 , \blk00000003/sig00000607 , \blk00000003/sig00000608 , +\blk00000003/sig00000609 , \blk00000003/sig0000060a , \blk00000003/sig0000060b , \blk00000003/sig0000060c , \blk00000003/sig0000060d , +\blk00000003/sig0000060e , \blk00000003/sig0000060f , \blk00000003/sig00000610 , \blk00000003/sig00000611 , \blk00000003/sig00000612 }), + .PCOUT({\blk00000003/sig00000613 , \blk00000003/sig00000614 , \blk00000003/sig00000615 , \blk00000003/sig00000616 , \blk00000003/sig00000617 , +\blk00000003/sig00000618 , \blk00000003/sig00000619 , \blk00000003/sig0000061a , \blk00000003/sig0000061b , \blk00000003/sig0000061c , +\blk00000003/sig0000061d , \blk00000003/sig0000061e , \blk00000003/sig0000061f , \blk00000003/sig00000620 , \blk00000003/sig00000621 , +\blk00000003/sig00000622 , \blk00000003/sig00000623 , \blk00000003/sig00000624 , \blk00000003/sig00000625 , \blk00000003/sig00000626 , +\blk00000003/sig00000627 , \blk00000003/sig00000628 , \blk00000003/sig00000629 , \blk00000003/sig0000062a , \blk00000003/sig0000062b , +\blk00000003/sig0000062c , \blk00000003/sig0000062d , \blk00000003/sig0000062e , \blk00000003/sig0000062f , \blk00000003/sig00000630 , +\blk00000003/sig00000631 , \blk00000003/sig00000632 , \blk00000003/sig00000633 , \blk00000003/sig00000634 , \blk00000003/sig00000635 , +\blk00000003/sig00000636 , \blk00000003/sig00000637 , \blk00000003/sig00000638 , \blk00000003/sig00000639 , \blk00000003/sig0000063a , +\blk00000003/sig0000063b , \blk00000003/sig0000063c , \blk00000003/sig0000063d , \blk00000003/sig0000063e , \blk00000003/sig0000063f , +\blk00000003/sig00000640 , \blk00000003/sig00000641 , \blk00000003/sig00000642 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ee ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ee_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ee_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ee_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ee_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ee_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ee_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ee_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ee_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000005a1 , \blk00000003/sig000005a2 , \blk00000003/sig000005a3 , \blk00000003/sig000005a4 , \blk00000003/sig000005a5 , +\blk00000003/sig000005a6 , \blk00000003/sig000005a7 , \blk00000003/sig000005a8 , \blk00000003/sig000005a9 , \blk00000003/sig000005aa , +\blk00000003/sig000005ab , \blk00000003/sig000005ac , \blk00000003/sig000005ad , \blk00000003/sig000005ae , \blk00000003/sig000005af , +\blk00000003/sig000005b0 , \blk00000003/sig000005b1 , \blk00000003/sig000005b2 }), + .BCOUT({\NLW_blk00000003/blk000000ee_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ee_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000005b3 , \blk00000003/sig000005b3 , \blk00000003/sig000005b4 , \blk00000003/sig000005b5 , \blk00000003/sig000005b6 , +\blk00000003/sig000005b7 , \blk00000003/sig000005b8 , \blk00000003/sig000005b9 , \blk00000003/sig000005ba , \blk00000003/sig000005bb , +\blk00000003/sig000005bc , \blk00000003/sig000005bd , \blk00000003/sig000005be , \blk00000003/sig000005bf , \blk00000003/sig000005c0 , +\blk00000003/sig000005c1 , \blk00000003/sig000005c2 , \blk00000003/sig000005c3 , \blk00000003/sig000005c4 , \blk00000003/sig000005c5 , +\blk00000003/sig000005c6 , \blk00000003/sig000005c7 , \blk00000003/sig000005c8 , \blk00000003/sig000005c9 , \blk00000003/sig000005ca }), + .P({\NLW_blk00000003/blk000000ee_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ee_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ee_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cb , +\blk00000003/sig000005cb , \blk00000003/sig000005cb , \blk00000003/sig000005cc , \blk00000003/sig000005cd , \blk00000003/sig000005ce , +\blk00000003/sig000005cf , \blk00000003/sig000005d0 , \blk00000003/sig000005d1 , \blk00000003/sig000005d2 , \blk00000003/sig000005d3 , +\blk00000003/sig000005d4 , \blk00000003/sig000005d5 , \blk00000003/sig000005d6 , \blk00000003/sig000005d7 , \blk00000003/sig000005d8 , +\blk00000003/sig000005d9 , \blk00000003/sig000005da , \blk00000003/sig000005db , \blk00000003/sig000005dc , \blk00000003/sig000005dd , +\blk00000003/sig000005de , \blk00000003/sig000005df , \blk00000003/sig000005e0 , \blk00000003/sig000005e1 , \blk00000003/sig000005e2 }), + .PCOUT({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ed ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ed_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ed_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ed_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ed_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ed_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ed_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ed_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ed_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000052f , \blk00000003/sig00000530 , \blk00000003/sig00000531 , \blk00000003/sig00000532 , \blk00000003/sig00000533 , +\blk00000003/sig00000534 , \blk00000003/sig00000535 , \blk00000003/sig00000536 , \blk00000003/sig00000537 , \blk00000003/sig00000538 , +\blk00000003/sig00000539 , \blk00000003/sig0000053a , \blk00000003/sig0000053b , \blk00000003/sig0000053c , \blk00000003/sig0000053d , +\blk00000003/sig0000053e , \blk00000003/sig0000053f , \blk00000003/sig00000540 }), + .BCOUT({\NLW_blk00000003/blk000000ed_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ed_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000541 , \blk00000003/sig00000541 , \blk00000003/sig00000542 , \blk00000003/sig00000543 , \blk00000003/sig00000544 , +\blk00000003/sig00000545 , \blk00000003/sig00000546 , \blk00000003/sig00000547 , \blk00000003/sig00000548 , \blk00000003/sig00000549 , +\blk00000003/sig0000054a , \blk00000003/sig0000054b , \blk00000003/sig0000054c , \blk00000003/sig0000054d , \blk00000003/sig0000054e , +\blk00000003/sig0000054f , \blk00000003/sig00000550 , \blk00000003/sig00000551 , \blk00000003/sig00000552 , \blk00000003/sig00000553 , +\blk00000003/sig00000554 , \blk00000003/sig00000555 , \blk00000003/sig00000556 , \blk00000003/sig00000557 , \blk00000003/sig00000558 }), + .P({\NLW_blk00000003/blk000000ed_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ed_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ed_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig00000559 , +\blk00000003/sig00000559 , \blk00000003/sig00000559 , \blk00000003/sig0000055a , \blk00000003/sig0000055b , \blk00000003/sig0000055c , +\blk00000003/sig0000055d , \blk00000003/sig0000055e , \blk00000003/sig0000055f , \blk00000003/sig00000560 , \blk00000003/sig00000561 , +\blk00000003/sig00000562 , \blk00000003/sig00000563 , \blk00000003/sig00000564 , \blk00000003/sig00000565 , \blk00000003/sig00000566 , +\blk00000003/sig00000567 , \blk00000003/sig00000568 , \blk00000003/sig00000569 , \blk00000003/sig0000056a , \blk00000003/sig0000056b , +\blk00000003/sig0000056c , \blk00000003/sig0000056d , \blk00000003/sig0000056e , \blk00000003/sig0000056f , \blk00000003/sig00000570 }), + .PCOUT({\blk00000003/sig00000571 , \blk00000003/sig00000572 , \blk00000003/sig00000573 , \blk00000003/sig00000574 , \blk00000003/sig00000575 , +\blk00000003/sig00000576 , \blk00000003/sig00000577 , \blk00000003/sig00000578 , \blk00000003/sig00000579 , \blk00000003/sig0000057a , +\blk00000003/sig0000057b , \blk00000003/sig0000057c , \blk00000003/sig0000057d , \blk00000003/sig0000057e , \blk00000003/sig0000057f , +\blk00000003/sig00000580 , \blk00000003/sig00000581 , \blk00000003/sig00000582 , \blk00000003/sig00000583 , \blk00000003/sig00000584 , +\blk00000003/sig00000585 , \blk00000003/sig00000586 , \blk00000003/sig00000587 , \blk00000003/sig00000588 , \blk00000003/sig00000589 , +\blk00000003/sig0000058a , \blk00000003/sig0000058b , \blk00000003/sig0000058c , \blk00000003/sig0000058d , \blk00000003/sig0000058e , +\blk00000003/sig0000058f , \blk00000003/sig00000590 , \blk00000003/sig00000591 , \blk00000003/sig00000592 , \blk00000003/sig00000593 , +\blk00000003/sig00000594 , \blk00000003/sig00000595 , \blk00000003/sig00000596 , \blk00000003/sig00000597 , \blk00000003/sig00000598 , +\blk00000003/sig00000599 , \blk00000003/sig0000059a , \blk00000003/sig0000059b , \blk00000003/sig0000059c , \blk00000003/sig0000059d , +\blk00000003/sig0000059e , \blk00000003/sig0000059f , \blk00000003/sig000005a0 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ec ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ec_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ec_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ec_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ec_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ec_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ec_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ec_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ec_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000004bd , \blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , +\blk00000003/sig000004c2 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce }), + .BCOUT({\NLW_blk00000003/blk000000ec_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ec_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004cf , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , \blk00000003/sig000004d1 , \blk00000003/sig000004d2 , +\blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , \blk00000003/sig000004d6 , \blk00000003/sig000004d7 , +\blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da , \blk00000003/sig000004db , \blk00000003/sig000004dc , +\blk00000003/sig000004dd , \blk00000003/sig000004de , \blk00000003/sig000004df , \blk00000003/sig000004e0 , \blk00000003/sig000004e1 , +\blk00000003/sig000004e2 , \blk00000003/sig000004e3 , \blk00000003/sig000004e4 , \blk00000003/sig000004e5 , \blk00000003/sig000004e6 }), + .P({\NLW_blk00000003/blk000000ec_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ec_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ec_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e7 , +\blk00000003/sig000004e7 , \blk00000003/sig000004e7 , \blk00000003/sig000004e8 , \blk00000003/sig000004e9 , \blk00000003/sig000004ea , +\blk00000003/sig000004eb , \blk00000003/sig000004ec , \blk00000003/sig000004ed , \blk00000003/sig000004ee , \blk00000003/sig000004ef , +\blk00000003/sig000004f0 , \blk00000003/sig000004f1 , \blk00000003/sig000004f2 , \blk00000003/sig000004f3 , \blk00000003/sig000004f4 , +\blk00000003/sig000004f5 , \blk00000003/sig000004f6 , \blk00000003/sig000004f7 , \blk00000003/sig000004f8 , \blk00000003/sig000004f9 , +\blk00000003/sig000004fa , \blk00000003/sig000004fb , \blk00000003/sig000004fc , \blk00000003/sig000004fd , \blk00000003/sig000004fe }), + .PCOUT({\blk00000003/sig000004ff , \blk00000003/sig00000500 , \blk00000003/sig00000501 , \blk00000003/sig00000502 , \blk00000003/sig00000503 , +\blk00000003/sig00000504 , \blk00000003/sig00000505 , \blk00000003/sig00000506 , \blk00000003/sig00000507 , \blk00000003/sig00000508 , +\blk00000003/sig00000509 , \blk00000003/sig0000050a , \blk00000003/sig0000050b , \blk00000003/sig0000050c , \blk00000003/sig0000050d , +\blk00000003/sig0000050e , \blk00000003/sig0000050f , \blk00000003/sig00000510 , \blk00000003/sig00000511 , \blk00000003/sig00000512 , +\blk00000003/sig00000513 , \blk00000003/sig00000514 , \blk00000003/sig00000515 , \blk00000003/sig00000516 , \blk00000003/sig00000517 , +\blk00000003/sig00000518 , \blk00000003/sig00000519 , \blk00000003/sig0000051a , \blk00000003/sig0000051b , \blk00000003/sig0000051c , +\blk00000003/sig0000051d , \blk00000003/sig0000051e , \blk00000003/sig0000051f , \blk00000003/sig00000520 , \blk00000003/sig00000521 , +\blk00000003/sig00000522 , \blk00000003/sig00000523 , \blk00000003/sig00000524 , \blk00000003/sig00000525 , \blk00000003/sig00000526 , +\blk00000003/sig00000527 , \blk00000003/sig00000528 , \blk00000003/sig00000529 , \blk00000003/sig0000052a , \blk00000003/sig0000052b , +\blk00000003/sig0000052c , \blk00000003/sig0000052d , \blk00000003/sig0000052e }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000eb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000eb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000eb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000eb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000eb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000eb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000eb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000eb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000eb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig0000044b , \blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , +\blk00000003/sig00000450 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c }), + .BCOUT({\NLW_blk00000003/blk000000eb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000eb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000045d , \blk00000003/sig0000045d , \blk00000003/sig0000045e , \blk00000003/sig0000045f , \blk00000003/sig00000460 , +\blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , \blk00000003/sig00000464 , \blk00000003/sig00000465 , +\blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 , \blk00000003/sig00000469 , \blk00000003/sig0000046a , +\blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , \blk00000003/sig0000046e , \blk00000003/sig0000046f , +\blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , \blk00000003/sig00000473 , \blk00000003/sig00000474 }), + .P({\NLW_blk00000003/blk000000eb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000eb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000eb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000475 , +\blk00000003/sig00000475 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , \blk00000003/sig00000478 , +\blk00000003/sig00000479 , \blk00000003/sig0000047a , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , +\blk00000003/sig0000047e , \blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , +\blk00000003/sig00000483 , \blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , +\blk00000003/sig00000488 , \blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c }), + .PCOUT({\blk00000003/sig0000048d , \blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , +\blk00000003/sig00000492 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa , +\blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , \blk00000003/sig000004af , +\blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , \blk00000003/sig000004b4 , +\blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , \blk00000003/sig000004b9 , +\blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000ea ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000ea_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000ea_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000ea_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000ea_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000ea_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000ea_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000ea_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig000003eb , \blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , +\blk00000003/sig000003f0 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000ea_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000ea_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000ea_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000041b , \blk00000003/sig0000041b , \blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , +\blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , +\blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , \blk00000003/sig00000427 , \blk00000003/sig00000428 , +\blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , \blk00000003/sig0000042c , \blk00000003/sig0000042d , +\blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , \blk00000003/sig00000431 , \blk00000003/sig00000432 }), + .P({\NLW_blk00000003/blk000000ea_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000ea_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000ea_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000433 , +\blk00000003/sig00000433 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , \blk00000003/sig00000436 , +\blk00000003/sig00000437 , \blk00000003/sig00000438 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , +\blk00000003/sig0000043c , \blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , +\blk00000003/sig00000441 , \blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , +\blk00000003/sig00000446 , \blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a }), + .PCOUT({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000379 , \blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , +\blk00000003/sig0000037e , \blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , +\blk00000003/sig00000383 , \blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , +\blk00000003/sig00000388 , \blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , +\blk00000003/sig0000038d , \blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , +\blk00000003/sig00000392 , \blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , +\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , +\blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , +\blk00000003/sig000003b3 , \blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , +\blk00000003/sig000003b8 , \blk00000003/sig000003b9 , \blk00000003/sig000003ba }), + .BCOUT({\NLW_blk00000003/blk000000e9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003bb , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , +\blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , +\blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 }), + .P({\NLW_blk00000003/blk000000e9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d3 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , +\blk00000003/sig000003d7 , \blk00000003/sig000003d8 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , +\blk00000003/sig000003dc , \blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , +\blk00000003/sig000003e1 , \blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , +\blk00000003/sig000003e6 , \blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea }), + .PCOUT({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000319 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , +\blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , +\blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , +\blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , +\blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 }), + .P({\NLW_blk00000003/blk000000e8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000331 , +\blk00000003/sig00000331 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , \blk00000003/sig00000334 , +\blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , +\blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , +\blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , +\blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 }), + .PCOUT({\blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , +\blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000e7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000e7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000e7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000e7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000e7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000e7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000e7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000e7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, +\blk00000003/sig00000049 , NlwRenamedSig_OI_rfd}), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000e7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002a7 , \blk00000003/sig000002a8 , \blk00000003/sig000002a9 , \blk00000003/sig000002aa , \blk00000003/sig000002ab , +\blk00000003/sig000002ac , \blk00000003/sig000002ad , \blk00000003/sig000002ae , \blk00000003/sig000002af , \blk00000003/sig000002b0 , +\blk00000003/sig000002b1 , \blk00000003/sig000002b2 , \blk00000003/sig000002b3 , \blk00000003/sig000002b4 , \blk00000003/sig000002b5 , +\blk00000003/sig000002b6 , \blk00000003/sig000002b7 , \blk00000003/sig000002b8 }), + .BCOUT({\NLW_blk00000003/blk000000e7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000e7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002b9 , \blk00000003/sig000002b9 , \blk00000003/sig000002ba , \blk00000003/sig000002bb , \blk00000003/sig000002bc , +\blk00000003/sig000002bd , \blk00000003/sig000002be , \blk00000003/sig000002bf , \blk00000003/sig000002c0 , \blk00000003/sig000002c1 , +\blk00000003/sig000002c2 , \blk00000003/sig000002c3 , \blk00000003/sig000002c4 , \blk00000003/sig000002c5 , \blk00000003/sig000002c6 , +\blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , \blk00000003/sig000002ca , \blk00000003/sig000002cb , +\blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , \blk00000003/sig000002cf , \blk00000003/sig000002d0 }), + .P({\NLW_blk00000003/blk000000e7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000e7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000e7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d1 , +\blk00000003/sig000002d1 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , \blk00000003/sig000002d4 , +\blk00000003/sig000002d5 , \blk00000003/sig000002d6 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , +\blk00000003/sig000002da , \blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , +\blk00000003/sig000002df , \blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , +\blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 }), + .PCOUT({\blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , +\blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .Q(\blk00000003/sig000002a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a3 ), + .Q(\blk00000003/sig0000029f ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000029f ), + .LI(\blk00000003/sig000002a1 ), + .O(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig0000029f ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig000002a1 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e2_LO_UNCONNECTED ) + ); + FDE \blk00000003/blk000000e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029d ), + .Q(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029b ), + .O(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig0000029a ), + .S(\blk00000003/sig0000029b ), + .O(\NLW_blk00000003/blk000000df_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000df_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000296 ), + .O(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000295 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000dc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dc_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000294 ), + .S(\blk00000003/sig0000028e ), + .LO(\blk00000003/sig00000290 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000293 ), + .S(\blk00000003/sig00000291 ), + .O(\NLW_blk00000003/blk000000da_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000290 ), + .LI(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000292 ) + ); + XORCY \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000028f ) + ); + MUXCY_L \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000287 ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig00000288 ), + .LO(\blk00000003/sig0000028a ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig0000028a ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig0000028b ), + .O(\NLW_blk00000003/blk000000d6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000287 ) + ); + XORCY \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig0000028b ), + .O(\blk00000003/sig0000028c ) + ); + XORCY \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000287 ), + .LI(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000289 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000277 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000285 ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d0_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000283 ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000276 ), + .S(\blk00000003/sig00000281 ), + .O(\blk00000003/sig0000027d ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig0000027d ), + .DI(\blk00000003/sig0000027e ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig00000249 ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000027a ), + .O(\NLW_blk00000003/blk000000cb_O_UNCONNECTED ), + .LO(\blk00000003/sig00000277 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000277 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000278 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000276 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000265 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000274 ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000273 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig0000026d ), + .LO(\NLW_blk00000003/blk000000c5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig0000026d ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .O(\blk00000003/sig0000026b ), + .LO(\NLW_blk00000003/blk000000c4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026b ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026c ), + .O(\blk00000003/sig00000267 ), + .LO(\NLW_blk00000003/blk000000c3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000026a ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\blk00000003/sig00000265 ) + ); + MUXCY_D \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000267 ), + .DI(\blk00000003/sig0000023e ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ), + .LO(\NLW_blk00000003/blk000000c1_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000265 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000266 ) + ); + FDE \blk00000003/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000263 ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024f ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025e ), + .LI(\blk00000003/sig00000260 ), + .O(\blk00000003/sig00000261 ) + ); + MUXCY_D \blk00000003/blk000000bb ( + .CI(\blk00000003/sig0000025e ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig00000260 ), + .O(\NLW_blk00000003/blk000000bb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bb_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig0000025d ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig00000257 ), + .DI(\blk00000003/sig0000025c ), + .S(\blk00000003/sig00000258 ), + .LO(\blk00000003/sig00000254 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000254 ), + .DI(\blk00000003/sig0000025b ), + .S(\blk00000003/sig00000255 ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .DI(NlwRenamedSig_OI_rfd), + .S(\blk00000003/sig0000025a ), + .O(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000257 ), + .LI(\blk00000003/sig00000258 ), + .O(\blk00000003/sig00000259 ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000254 ), + .LI(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000256 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b3 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b2 ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000243 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .Q(\blk00000003/sig00000236 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .Q(\blk00000003/sig00000241 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000249 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig00000247 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000244 ), + .Q(\blk00000003/sig00000245 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000239 ), + .Q(\blk00000003/sig0000023d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a4_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\blk00000003/sig0000022f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a2_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000229 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000023b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000238 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig00000237 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000235 ) + ); + MUXCY_D \blk00000003/blk0000009b ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000232 ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig00000233 ) + ); + MUXCY_D \blk00000003/blk0000009a ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000231 ), + .O(\blk00000003/sig0000022e ), + .LO(\NLW_blk00000003/blk0000009a_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000099 ( + .CI(\blk00000003/sig0000022e ), + .DI(\blk00000003/sig0000022f ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000099_O_UNCONNECTED ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022c ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000097_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(\blk00000003/sig00000228 ), + .O(\NLW_blk00000003/blk00000096_O_UNCONNECTED ), + .LO(\blk00000003/sig00000229 ) + ); + XORCY \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000224 ), + .O(\blk00000003/sig00000225 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000223 ), + .S(\blk00000003/sig00000224 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000093 ( + .CI(\blk00000003/sig0000021c ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk00000091_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000090 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk0000002b ( + .C(clk), + .D(\blk00000003/sig000000be ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(\blk00000003/sig000001dd ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001de ), + .R(sclr), + .Q(\blk00000003/sig000001df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dc ), + .R(\blk00000003/sig000001dd ), + .Q(rdy) + ); + FDRE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001da ), + .R(sclr), + .Q(\blk00000003/sig000001db ) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d8 ), + .S(sclr), + .Q(\blk00000003/sig000001d9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .R(sclr), + .Q(\blk00000003/sig000001d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d6 ), + .R(sclr), + .Q(\blk00000003/sig000001ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d4 ), + .R(sclr), + .Q(\blk00000003/sig000001d5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d2 ), + .R(sclr), + .Q(\blk00000003/sig000001d3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001d_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d0 ), + .R(sclr), + .Q(\blk00000003/sig000001d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c8 ), + .R(sclr), + .Q(\blk00000003/sig000000c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c3 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c4 ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk00000017 ( + .CI(\blk00000003/sig000001ca ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001cb ), + .O(\NLW_blk00000003/blk00000017_O_UNCONNECTED ), + .LO(\blk00000003/sig000001cc ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000016 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000016_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000016_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000016_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000016_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000016_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000016_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000016_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , \blk00000003/sig00000156 , \blk00000003/sig00000157 , +\blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , \blk00000003/sig0000015b , \blk00000003/sig0000015c , +\blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , \blk00000003/sig00000160 , \blk00000003/sig00000161 , +\blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , \blk00000003/sig00000165 , \blk00000003/sig00000166 , +\blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , \blk00000003/sig0000016a , \blk00000003/sig0000016b , +\blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , \blk00000003/sig0000016f , \blk00000003/sig00000170 , +\blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , \blk00000003/sig00000174 , \blk00000003/sig00000175 , +\blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , \blk00000003/sig00000179 , \blk00000003/sig0000017a , +\blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , +\blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000016_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000016_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000016_P<47>_UNCONNECTED , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , +\blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 }), + .A({\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b2 , +\blk00000003/sig000001b2 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , +\blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , \blk00000003/sig000001ba , +\blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , +\blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 , \blk00000003/sig000001c4 , +\blk00000003/sig000001c5 , \blk00000003/sig000001c6 , \blk00000003/sig000001c7 , \blk00000003/sig000001c8 , \blk00000003/sig000001c9 }), + .PCOUT({\NLW_blk00000003/blk00000016_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000016_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000016_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000015 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000015_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000015_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000015_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000015_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000015_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000015_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000015_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b8 , \blk00000003/sig00000049 , \blk00000003/sig000000bc , +\blk00000003/sig000000ba , \blk00000003/sig000000bc }), + .PCIN({\blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , +\blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , +\blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , +\blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , +\blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , +\blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , +\blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , +\blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 , +\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000015_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , NlwRenamedSig_OI_rfd, \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , +\blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 , +\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b }), + .BCOUT({\NLW_blk00000003/blk00000015_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000015_P<47>_UNCONNECTED , \blk00000003/sig0000010c , \blk00000003/sig0000010d , \blk00000003/sig0000010e , +\blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , \blk00000003/sig00000113 , +\blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , \blk00000003/sig00000118 , +\blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , \blk00000003/sig0000011d , +\blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , \blk00000003/sig00000122 , +\blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , \blk00000003/sig00000127 , +\blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , \blk00000003/sig0000012c , +\blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , \blk00000003/sig00000131 , +\blk00000003/sig00000132 , \blk00000003/sig00000133 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , +\blk00000003/sig00000137 , \blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a }), + .A({\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013b , +\blk00000003/sig0000013b , \blk00000003/sig0000013b , \blk00000003/sig0000013c , \blk00000003/sig0000013d , \blk00000003/sig0000013e , +\blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , \blk00000003/sig00000142 , \blk00000003/sig00000143 , +\blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , \blk00000003/sig00000147 , \blk00000003/sig00000148 , +\blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b , \blk00000003/sig0000014c , \blk00000003/sig0000014d , +\blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , \blk00000003/sig00000151 , \blk00000003/sig00000152 }), + .PCOUT({\NLW_blk00000003/blk00000015_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000015_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000015_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk00000014 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c9 ), + .O(\blk00000003/sig000000c5 ), + .LO(\NLW_blk00000003/blk00000014_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000000c5 ), + .DI(\blk00000003/sig000000c6 ), + .S(\blk00000003/sig000000c7 ), + .O(\blk00000003/sig000000bd ), + .LO(\blk00000003/sig000000c8 ) + ); + XORCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000000c3 ), + .LI(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000000c4 ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000000c0 ), + .DI(\blk00000003/sig000000c1 ), + .S(\blk00000003/sig000000c2 ), + .O(\NLW_blk00000003/blk00000011_O_UNCONNECTED ), + .LO(\blk00000003/sig000000c3 ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000c0 ), + .LO(\NLW_blk00000003/blk00000010_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000f ( + .C(clk), + .D(\blk00000003/sig000000bb ), + .Q(\blk00000003/sig000000bc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000e ( + .C(clk), + .D(\blk00000003/sig000000b9 ), + .Q(\blk00000003/sig000000ba ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000d ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .Q(\blk00000003/sig000000b8 ) + ); + XORCY \blk00000003/blk0000000c ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b6 ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000b4 ), + .S(\blk00000003/sig000000b5 ), + .O(\NLW_blk00000003/blk0000000b_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000af ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b3 ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000b1 ), + .R(sclr), + .Q(\blk00000003/sig000000b2 ) + ); + MUXCY_D \blk00000003/blk00000008 ( + .CI(NlwRenamedSig_OI_rfd), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000ae ), + .LO(\NLW_blk00000003/blk00000008_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000007 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig000000ad ), + .S(nd), + .O(\blk00000003/sig000000af ), + .LO(\blk00000003/sig000000ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000ac ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + VCC \blk00000003/blk00000005 ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002c/blk0000008e ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002c/sig00000c29 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c26 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c28 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c21 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c1c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c09 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c06 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c05 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c03 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c02 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c04 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c00 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000c01 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002c/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/sig000001e7 ), + .A3(\blk00000003/blk0000002c/sig00000bf8 ), + .A4(\blk00000003/blk0000002c/sig00000bf8 ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001d9 ), + .DPRA1(\blk00000003/sig000001db ), + .DPRA2(\blk00000003/sig000001e3 ), + .DPRA3(\blk00000003/blk0000002c/sig00000bf8 ), + .DPRA4(\blk00000003/blk0000002c/sig00000bf8 ), + .WCLK(clk), + .WE(\blk00000003/blk0000002c/sig00000c29 ), + .SPO(\NLW_blk00000003/blk0000002c/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002c/sig00000bfb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c28 ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c27 ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c26 ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c25 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c24 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c23 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c22 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c21 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c20 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1f ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1e ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1d ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1c ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1b ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c1a ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c19 ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c18 ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c17 ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c16 ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c15 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c14 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c13 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c12 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c11 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c10 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0f ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0e ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0d ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0c ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0b ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c0a ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c09 ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c08 ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c07 ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c06 ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c05 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c04 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c03 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c02 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c01 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000c00 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bff ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfe ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfd ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfc ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfb ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bfa ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002c/sig00000bf9 ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002c/blk0000002d ( + .G(\blk00000003/blk0000002c/sig00000bf8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000120/blk00000152 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000120/sig00000c77 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000151 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000120/sig00000c75 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000151_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000150 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000120/sig00000c74 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000150_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000120/sig00000c76 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/blk00000120/sig00000c72 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/blk00000120/sig00000c71 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000120/sig00000c73 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/blk00000120/sig00000c6f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000014a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/blk00000120/sig00000c6e ), + .Q15(\NLW_blk00000003/blk00000120/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000149 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/blk00000120/sig00000c70 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000148 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/blk00000120/sig00000c6c ), + .Q15(\NLW_blk00000003/blk00000120/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000147 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/blk00000120/sig00000c6b ), + .Q15(\NLW_blk00000003/blk00000120/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000146 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/blk00000120/sig00000c6d ), + .Q15(\NLW_blk00000003/blk00000120/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000145 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/blk00000120/sig00000c69 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000144 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/blk00000120/sig00000c68 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000143 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/blk00000120/sig00000c6a ), + .Q15(\NLW_blk00000003/blk00000120/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000142 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/blk00000120/sig00000c66 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000141 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/blk00000120/sig00000c65 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk00000140 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/blk00000120/sig00000c67 ), + .Q15(\NLW_blk00000003/blk00000120/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013f ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/blk00000120/sig00000c63 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013e ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/blk00000120/sig00000c62 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013d ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/blk00000120/sig00000c64 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013c ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/blk00000120/sig00000c60 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013b ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/blk00000120/sig00000c5f ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000120/blk0000013a ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000120/sig00000c5e ), + .A2(\blk00000003/blk00000120/sig00000c5e ), + .A3(\blk00000003/blk00000120/sig00000c5e ), + .CE(\blk00000003/blk00000120/sig00000c77 ), + .CLK(clk), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/blk00000120/sig00000c61 ), + .Q15(\NLW_blk00000003/blk00000120/blk0000013a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c76 ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c75 ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000137 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c74 ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000136 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c73 ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000135 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c72 ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000134 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c71 ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000133 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c70 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6f ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6e ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6d ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6c ), + .Q(\blk00000003/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6b ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c6a ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c69 ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c68 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c67 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c66 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c65 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c64 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c63 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c62 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c61 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c60 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000120/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000120/sig00000c5f ), + .Q(\blk00000003/sig000003d2 ) + ); + GND \blk00000003/blk00000120/blk00000121 ( + .G(\blk00000003/blk00000120/sig00000c5e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000153/blk00000185 ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk00000153/sig00000cc5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000184 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk00000153/sig00000cc3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000184_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000183 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/blk00000153/sig00000cc2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000183_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000182 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/blk00000153/sig00000cc4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000182_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000181 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/blk00000153/sig00000cc0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000181_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000180 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk00000153/sig00000cbf ), + .Q15(\NLW_blk00000003/blk00000153/blk00000180_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk00000153/sig00000cc1 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk00000153/sig00000cbd ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076a ), + .Q(\blk00000003/blk00000153/sig00000cbc ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017c ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000768 ), + .Q(\blk00000003/blk00000153/sig00000cbe ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017b ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076c ), + .Q(\blk00000003/blk00000153/sig00000cba ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000017a ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk00000153/sig00000cb9 ), + .Q15(\NLW_blk00000003/blk00000153/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000179 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk00000153/sig00000cbb ), + .Q15(\NLW_blk00000003/blk00000153/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000178 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk00000153/sig00000cb7 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000177 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000770 ), + .Q(\blk00000003/blk00000153/sig00000cb6 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000176 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig0000076e ), + .Q(\blk00000003/blk00000153/sig00000cb8 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000175 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000772 ), + .Q(\blk00000003/blk00000153/sig00000cb4 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000174 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000773 ), + .Q(\blk00000003/blk00000153/sig00000cb3 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000173 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk00000153/sig00000cb5 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000172 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000775 ), + .Q(\blk00000003/blk00000153/sig00000cb1 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000171 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000776 ), + .Q(\blk00000003/blk00000153/sig00000cb0 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk00000170 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000774 ), + .Q(\blk00000003/blk00000153/sig00000cb2 ), + .Q15(\NLW_blk00000003/blk00000153/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016f ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000778 ), + .Q(\blk00000003/blk00000153/sig00000cae ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016e ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000779 ), + .Q(\blk00000003/blk00000153/sig00000cad ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000153/blk0000016d ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk00000153/sig00000cac ), + .A2(\blk00000003/blk00000153/sig00000cac ), + .A3(\blk00000003/blk00000153/sig00000cac ), + .CE(\blk00000003/blk00000153/sig00000cc5 ), + .CLK(clk), + .D(\blk00000003/sig00000777 ), + .Q(\blk00000003/blk00000153/sig00000caf ), + .Q15(\NLW_blk00000003/blk00000153/blk0000016d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc4 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc3 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000016a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc2 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000169 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc1 ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000168 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cc0 ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000167 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbf ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000166 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbe ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbd ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbc ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cbb ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cba ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb9 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb8 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb7 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb6 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb5 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb4 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb3 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb2 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb1 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cb0 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000caf ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cae ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000153/sig00000cad ), + .Q(\blk00000003/sig000003ea ) + ); + GND \blk00000003/blk00000153/blk00000154 ( + .G(\blk00000003/blk00000153/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000186/blk000001b8 ( + .I0(ce), + .I1(\blk00000003/sig00000743 ), + .O(\blk00000003/blk00000186/sig00000d13 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/blk00000186/sig00000d11 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/blk00000186/sig00000d10 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/blk00000186/sig00000d12 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/blk00000186/sig00000d0e ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/blk00000186/sig00000d0d ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/blk00000186/sig00000d0f ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/blk00000186/sig00000d0b ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001b0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/blk00000186/sig00000d0a ), + .Q15(\NLW_blk00000003/blk00000186/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001af ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/blk00000186/sig00000d0c ), + .Q15(\NLW_blk00000003/blk00000186/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ae ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/blk00000186/sig00000d08 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ad ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/blk00000186/sig00000d07 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ac ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/blk00000186/sig00000d09 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001ab ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/blk00000186/sig00000d05 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001aa ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/blk00000186/sig00000d04 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a9 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/blk00000186/sig00000d06 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a8 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/blk00000186/sig00000d02 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a7 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/blk00000186/sig00000d01 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a6 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/blk00000186/sig00000d03 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a5 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/blk00000186/sig00000cff ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a4 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/blk00000186/sig00000cfe ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a3 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/blk00000186/sig00000d00 ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a2 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/blk00000186/sig00000cfc ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a1 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/blk00000186/sig00000cfb ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000186/blk000001a0 ( + .A0(\blk00000003/sig00000749 ), + .A1(\blk00000003/blk00000186/sig00000cfa ), + .A2(\blk00000003/blk00000186/sig00000cfa ), + .A3(\blk00000003/blk00000186/sig00000cfa ), + .CE(\blk00000003/blk00000186/sig00000d13 ), + .CLK(clk), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/blk00000186/sig00000cfd ), + .Q15(\NLW_blk00000003/blk00000186/blk000001a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d12 ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d11 ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d10 ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0f ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0e ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000019a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0d ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000199 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0c ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0b ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d0a ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d09 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d08 ), + .Q(\blk00000003/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d07 ), + .Q(\blk00000003/sig00000426 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d06 ), + .Q(\blk00000003/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d05 ), + .Q(\blk00000003/sig00000428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d04 ), + .Q(\blk00000003/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d03 ), + .Q(\blk00000003/sig0000042a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d02 ), + .Q(\blk00000003/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d01 ), + .Q(\blk00000003/sig0000042c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000d00 ), + .Q(\blk00000003/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cff ), + .Q(\blk00000003/sig0000042e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfe ), + .Q(\blk00000003/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfd ), + .Q(\blk00000003/sig00000430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfc ), + .Q(\blk00000003/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000186/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000186/sig00000cfb ), + .Q(\blk00000003/sig00000432 ) + ); + GND \blk00000003/blk00000186/blk00000187 ( + .G(\blk00000003/blk00000186/sig00000cfa ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b9/blk000001eb ( + .I0(ce), + .I1(\blk00000003/sig00000745 ), + .O(\blk00000003/blk000001b9/sig00000d61 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001ea ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077b ), + .Q(\blk00000003/blk000001b9/sig00000d5f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001ea_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077c ), + .Q(\blk00000003/blk000001b9/sig00000d5e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077a ), + .Q(\blk00000003/blk000001b9/sig00000d60 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077e ), + .Q(\blk00000003/blk000001b9/sig00000d5c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077f ), + .Q(\blk00000003/blk000001b9/sig00000d5b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000077d ), + .Q(\blk00000003/blk000001b9/sig00000d5d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000781 ), + .Q(\blk00000003/blk000001b9/sig00000d59 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000782 ), + .Q(\blk00000003/blk000001b9/sig00000d58 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e2 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000780 ), + .Q(\blk00000003/blk000001b9/sig00000d5a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e1 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000784 ), + .Q(\blk00000003/blk000001b9/sig00000d56 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001e0 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000785 ), + .Q(\blk00000003/blk000001b9/sig00000d55 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001df ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000783 ), + .Q(\blk00000003/blk000001b9/sig00000d57 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001de ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000787 ), + .Q(\blk00000003/blk000001b9/sig00000d53 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dd ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000788 ), + .Q(\blk00000003/blk000001b9/sig00000d52 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001dc ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000786 ), + .Q(\blk00000003/blk000001b9/sig00000d54 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001db ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078a ), + .Q(\blk00000003/blk000001b9/sig00000d50 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001da ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078b ), + .Q(\blk00000003/blk000001b9/sig00000d4f ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d9 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000789 ), + .Q(\blk00000003/blk000001b9/sig00000d51 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d8 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078d ), + .Q(\blk00000003/blk000001b9/sig00000d4d ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d7 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078e ), + .Q(\blk00000003/blk000001b9/sig00000d4c ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d6 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078c ), + .Q(\blk00000003/blk000001b9/sig00000d4e ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d5 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000790 ), + .Q(\blk00000003/blk000001b9/sig00000d4a ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d4 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig00000791 ), + .Q(\blk00000003/blk000001b9/sig00000d49 ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b9/blk000001d3 ( + .A0(\blk00000003/sig00000747 ), + .A1(\blk00000003/blk000001b9/sig00000d48 ), + .A2(\blk00000003/blk000001b9/sig00000d48 ), + .A3(\blk00000003/blk000001b9/sig00000d48 ), + .CE(\blk00000003/blk000001b9/sig00000d61 ), + .CLK(clk), + .D(\blk00000003/sig0000078f ), + .Q(\blk00000003/blk000001b9/sig00000d4b ), + .Q15(\NLW_blk00000003/blk000001b9/blk000001d3_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d60 ), + .Q(\blk00000003/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5f ), + .Q(\blk00000003/sig00000434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5e ), + .Q(\blk00000003/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5d ), + .Q(\blk00000003/sig00000436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5c ), + .Q(\blk00000003/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5b ), + .Q(\blk00000003/sig00000438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d5a ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d59 ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d58 ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d57 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d56 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d55 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d54 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d53 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d52 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d51 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d50 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4f ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4e ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4d ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4c ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4b ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d4a ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b9/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b9/sig00000d49 ), + .Q(\blk00000003/sig0000044a ) + ); + GND \blk00000003/blk000001b9/blk000001ba ( + .G(\blk00000003/blk000001b9/sig00000d48 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001ec/blk0000021e ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk000001ec/sig00000daf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk000001ec/sig00000dad ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk000001ec/sig00000dac ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk000001ec/sig00000dae ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000021a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk000001ec/sig00000daa ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000021a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000219 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk000001ec/sig00000da9 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000219_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000218 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk000001ec/sig00000dab ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000218_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000217 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk000001ec/sig00000da7 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000217_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000216 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk000001ec/sig00000da6 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000215 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk000001ec/sig00000da8 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000214 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk000001ec/sig00000da4 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000213 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk000001ec/sig00000da3 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000212 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk000001ec/sig00000da5 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000211 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk000001ec/sig00000da1 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000210 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk000001ec/sig00000da0 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk000001ec/sig00000da2 ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk000001ec/sig00000d9e ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk000001ec/sig00000d9d ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk000001ec/sig00000d9f ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk000001ec/sig00000d9b ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk0000020a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk000001ec/sig00000d9a ), + .Q15(\NLW_blk00000003/blk000001ec/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000209 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk000001ec/sig00000d9c ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000208 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000001ec/sig00000d98 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000207 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000001ec/sig00000d97 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ec/blk00000206 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk000001ec/sig00000d96 ), + .A2(\blk00000003/blk000001ec/sig00000d96 ), + .A3(\blk00000003/blk000001ec/sig00000d96 ), + .CE(\blk00000003/blk000001ec/sig00000daf ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk000001ec/sig00000d99 ), + .Q15(\NLW_blk00000003/blk000001ec/blk00000206_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dae ), + .Q(\blk00000003/sig000005b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dad ), + .Q(\blk00000003/sig000005b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000203 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dac ), + .Q(\blk00000003/sig000005b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000202 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000dab ), + .Q(\blk00000003/sig000005b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000201 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000daa ), + .Q(\blk00000003/sig000005b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk00000200 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da9 ), + .Q(\blk00000003/sig000005b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da8 ), + .Q(\blk00000003/sig000005b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da7 ), + .Q(\blk00000003/sig000005ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da6 ), + .Q(\blk00000003/sig000005bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da5 ), + .Q(\blk00000003/sig000005bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da4 ), + .Q(\blk00000003/sig000005bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da3 ), + .Q(\blk00000003/sig000005be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da2 ), + .Q(\blk00000003/sig000005bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da1 ), + .Q(\blk00000003/sig000005c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000da0 ), + .Q(\blk00000003/sig000005c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9f ), + .Q(\blk00000003/sig000005c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9e ), + .Q(\blk00000003/sig000005c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9d ), + .Q(\blk00000003/sig000005c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9c ), + .Q(\blk00000003/sig000005c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9b ), + .Q(\blk00000003/sig000005c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d9a ), + .Q(\blk00000003/sig000005c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d99 ), + .Q(\blk00000003/sig000005c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d98 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001ec/sig00000d97 ), + .Q(\blk00000003/sig000005ca ) + ); + GND \blk00000003/blk000001ec/blk000001ed ( + .G(\blk00000003/blk000001ec/sig00000d96 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000021f/blk00000251 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk0000021f/sig00000dfd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000250 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000793 ), + .Q(\blk00000003/blk0000021f/sig00000dfb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000250_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000794 ), + .Q(\blk00000003/blk0000021f/sig00000dfa ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000792 ), + .Q(\blk00000003/blk0000021f/sig00000dfc ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000796 ), + .Q(\blk00000003/blk0000021f/sig00000df8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000797 ), + .Q(\blk00000003/blk0000021f/sig00000df7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000795 ), + .Q(\blk00000003/blk0000021f/sig00000df9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000024a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000799 ), + .Q(\blk00000003/blk0000021f/sig00000df5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000024a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000249 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079a ), + .Q(\blk00000003/blk0000021f/sig00000df4 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000248 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig00000798 ), + .Q(\blk00000003/blk0000021f/sig00000df6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000247 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079c ), + .Q(\blk00000003/blk0000021f/sig00000df2 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000246 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/blk0000021f/sig00000df1 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000245 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/blk0000021f/sig00000df3 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000244 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/blk0000021f/sig00000def ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000243 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a0 ), + .Q(\blk00000003/blk0000021f/sig00000dee ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000242 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig0000079e ), + .Q(\blk00000003/blk0000021f/sig00000df0 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000241 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a2 ), + .Q(\blk00000003/blk0000021f/sig00000dec ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000240 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/blk0000021f/sig00000deb ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/blk0000021f/sig00000ded ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023e ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/blk0000021f/sig00000de9 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023d ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a6 ), + .Q(\blk00000003/blk0000021f/sig00000de8 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023c ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a4 ), + .Q(\blk00000003/blk0000021f/sig00000dea ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023b ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a8 ), + .Q(\blk00000003/blk0000021f/sig00000de6 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk0000023a ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/blk0000021f/sig00000de5 ), + .Q15(\NLW_blk00000003/blk0000021f/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000021f/blk00000239 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk0000021f/sig00000de4 ), + .A2(\blk00000003/blk0000021f/sig00000de4 ), + .A3(\blk00000003/blk0000021f/sig00000de4 ), + .CE(\blk00000003/blk0000021f/sig00000dfd ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/blk0000021f/sig00000de7 ), + .Q15(\NLW_blk00000003/blk0000021f/blk00000239_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfc ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfb ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dfa ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df9 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df8 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df7 ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df6 ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df5 ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df4 ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df3 ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df2 ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df1 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000df0 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000def ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dee ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000ded ), + .Q(\blk00000003/sig000005da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dec ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000deb ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000dea ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de9 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de8 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de7 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de6 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000021f/sig00000de5 ), + .Q(\blk00000003/sig000005e2 ) + ); + GND \blk00000003/blk0000021f/blk00000220 ( + .G(\blk00000003/blk0000021f/sig00000de4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000252/blk00000284 ( + .I0(ce), + .I1(\blk00000003/sig00000742 ), + .O(\blk00000003/blk00000252/sig00000e4b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000283 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/blk00000252/sig00000e49 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000283_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000282 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/blk00000252/sig00000e48 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000282_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000281 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/blk00000252/sig00000e4a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000281_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000280 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/blk00000252/sig00000e46 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000280_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/blk00000252/sig00000e45 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/blk00000252/sig00000e47 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/blk00000252/sig00000e43 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/blk00000252/sig00000e42 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027b ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/blk00000252/sig00000e44 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000027a ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/blk00000252/sig00000e40 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000279 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/blk00000252/sig00000e3f ), + .Q15(\NLW_blk00000003/blk00000252/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000278 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/blk00000252/sig00000e41 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000277 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk00000252/sig00000e3d ), + .Q15(\NLW_blk00000003/blk00000252/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000276 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/blk00000252/sig00000e3c ), + .Q15(\NLW_blk00000003/blk00000252/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000275 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/blk00000252/sig00000e3e ), + .Q15(\NLW_blk00000003/blk00000252/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000274 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/blk00000252/sig00000e3a ), + .Q15(\NLW_blk00000003/blk00000252/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000273 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/blk00000252/sig00000e39 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000272 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/blk00000252/sig00000e3b ), + .Q15(\NLW_blk00000003/blk00000252/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000271 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/blk00000252/sig00000e37 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk00000270 ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/blk00000252/sig00000e36 ), + .Q15(\NLW_blk00000003/blk00000252/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026f ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/blk00000252/sig00000e38 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026e ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/blk00000252/sig00000e34 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026d ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/blk00000252/sig00000e33 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000252/blk0000026c ( + .A0(\blk00000003/sig00000748 ), + .A1(\blk00000003/blk00000252/sig00000e32 ), + .A2(\blk00000003/blk00000252/sig00000e32 ), + .A3(\blk00000003/blk00000252/sig00000e32 ), + .CE(\blk00000003/blk00000252/sig00000e4b ), + .CLK(clk), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/blk00000252/sig00000e35 ), + .Q15(\NLW_blk00000003/blk00000252/blk0000026c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e4a ), + .Q(\blk00000003/sig00000703 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000026a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e49 ), + .Q(\blk00000003/sig00000704 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000269 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e48 ), + .Q(\blk00000003/sig00000705 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000268 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e47 ), + .Q(\blk00000003/sig00000706 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000267 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e46 ), + .Q(\blk00000003/sig00000707 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e45 ), + .Q(\blk00000003/sig00000708 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e44 ), + .Q(\blk00000003/sig00000709 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e43 ), + .Q(\blk00000003/sig0000070a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e42 ), + .Q(\blk00000003/sig0000070b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e41 ), + .Q(\blk00000003/sig0000070c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e40 ), + .Q(\blk00000003/sig0000070d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3f ), + .Q(\blk00000003/sig0000070e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3e ), + .Q(\blk00000003/sig0000070f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3d ), + .Q(\blk00000003/sig00000710 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3c ), + .Q(\blk00000003/sig00000711 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3b ), + .Q(\blk00000003/sig00000712 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e3a ), + .Q(\blk00000003/sig00000713 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e39 ), + .Q(\blk00000003/sig00000714 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e38 ), + .Q(\blk00000003/sig00000715 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e37 ), + .Q(\blk00000003/sig00000716 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e36 ), + .Q(\blk00000003/sig00000717 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e35 ), + .Q(\blk00000003/sig00000718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e34 ), + .Q(\blk00000003/sig00000719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000252/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000252/sig00000e33 ), + .Q(\blk00000003/sig0000071a ) + ); + GND \blk00000003/blk00000252/blk00000253 ( + .G(\blk00000003/blk00000252/sig00000e32 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000285/blk000002b7 ( + .I0(ce), + .I1(\blk00000003/sig00000744 ), + .O(\blk00000003/blk00000285/sig00000e99 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/blk00000285/sig00000e97 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ac ), + .Q(\blk00000003/blk00000285/sig00000e96 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007aa ), + .Q(\blk00000003/blk00000285/sig00000e98 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ae ), + .Q(\blk00000003/blk00000285/sig00000e94 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/blk00000285/sig00000e93 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/blk00000285/sig00000e95 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002b0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/blk00000285/sig00000e91 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002af ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b2 ), + .Q(\blk00000003/blk00000285/sig00000e90 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ae ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b0 ), + .Q(\blk00000003/blk00000285/sig00000e92 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ad ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b4 ), + .Q(\blk00000003/blk00000285/sig00000e8e ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ac ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/blk00000285/sig00000e8d ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002ab ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/blk00000285/sig00000e8f ), + .Q15(\NLW_blk00000003/blk00000285/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002aa ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/blk00000285/sig00000e8b ), + .Q15(\NLW_blk00000003/blk00000285/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a9 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b8 ), + .Q(\blk00000003/blk00000285/sig00000e8a ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a8 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b6 ), + .Q(\blk00000003/blk00000285/sig00000e8c ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a7 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007ba ), + .Q(\blk00000003/blk00000285/sig00000e88 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a6 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/blk00000285/sig00000e87 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a5 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/blk00000285/sig00000e89 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a4 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/blk00000285/sig00000e85 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a3 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007be ), + .Q(\blk00000003/blk00000285/sig00000e84 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a2 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bc ), + .Q(\blk00000003/blk00000285/sig00000e86 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a1 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c0 ), + .Q(\blk00000003/blk00000285/sig00000e82 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk000002a0 ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007c1 ), + .Q(\blk00000003/blk00000285/sig00000e81 ), + .Q15(\NLW_blk00000003/blk00000285/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000285/blk0000029f ( + .A0(\blk00000003/sig00000746 ), + .A1(\blk00000003/blk00000285/sig00000e80 ), + .A2(\blk00000003/blk00000285/sig00000e80 ), + .A3(\blk00000003/blk00000285/sig00000e80 ), + .CE(\blk00000003/blk00000285/sig00000e99 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/blk00000285/sig00000e83 ), + .Q15(\NLW_blk00000003/blk00000285/blk0000029f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e98 ), + .Q(\blk00000003/sig0000071b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e97 ), + .Q(\blk00000003/sig0000071c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e96 ), + .Q(\blk00000003/sig0000071d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e95 ), + .Q(\blk00000003/sig0000071e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e94 ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e93 ), + .Q(\blk00000003/sig00000720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e92 ), + .Q(\blk00000003/sig00000721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e91 ), + .Q(\blk00000003/sig00000722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e90 ), + .Q(\blk00000003/sig00000723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8f ), + .Q(\blk00000003/sig00000724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8e ), + .Q(\blk00000003/sig00000725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8d ), + .Q(\blk00000003/sig00000726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8c ), + .Q(\blk00000003/sig00000727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8b ), + .Q(\blk00000003/sig00000728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e8a ), + .Q(\blk00000003/sig00000729 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e89 ), + .Q(\blk00000003/sig0000072a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e88 ), + .Q(\blk00000003/sig0000072b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e87 ), + .Q(\blk00000003/sig0000072c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e86 ), + .Q(\blk00000003/sig0000072d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e85 ), + .Q(\blk00000003/sig0000072e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e84 ), + .Q(\blk00000003/sig0000072f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e83 ), + .Q(\blk00000003/sig00000730 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e82 ), + .Q(\blk00000003/sig00000731 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000285/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000285/sig00000e81 ), + .Q(\blk00000003/sig00000732 ) + ); + GND \blk00000003/blk00000285/blk00000286 ( + .G(\blk00000003/blk00000285/sig00000e80 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b8/blk000002ea ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk000002b8/sig00000ee7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d0 ), + .Q(\blk00000003/blk000002b8/sig00000ee5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d1 ), + .Q(\blk00000003/blk000002b8/sig00000ee4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004cf ), + .Q(\blk00000003/blk000002b8/sig00000ee6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d3 ), + .Q(\blk00000003/blk000002b8/sig00000ee2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d4 ), + .Q(\blk00000003/blk000002b8/sig00000ee1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d2 ), + .Q(\blk00000003/blk000002b8/sig00000ee3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d6 ), + .Q(\blk00000003/blk000002b8/sig00000edf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d7 ), + .Q(\blk00000003/blk000002b8/sig00000ede ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e1 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d5 ), + .Q(\blk00000003/blk000002b8/sig00000ee0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002e0 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d9 ), + .Q(\blk00000003/blk000002b8/sig00000edc ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002df ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004da ), + .Q(\blk00000003/blk000002b8/sig00000edb ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002de ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004d8 ), + .Q(\blk00000003/blk000002b8/sig00000edd ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dd ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dc ), + .Q(\blk00000003/blk000002b8/sig00000ed9 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002dc ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004dd ), + .Q(\blk00000003/blk000002b8/sig00000ed8 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002db ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004db ), + .Q(\blk00000003/blk000002b8/sig00000eda ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002da ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004df ), + .Q(\blk00000003/blk000002b8/sig00000ed6 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d9 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e0 ), + .Q(\blk00000003/blk000002b8/sig00000ed5 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d8 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004de ), + .Q(\blk00000003/blk000002b8/sig00000ed7 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d7 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e2 ), + .Q(\blk00000003/blk000002b8/sig00000ed3 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d6 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e3 ), + .Q(\blk00000003/blk000002b8/sig00000ed2 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d5 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e1 ), + .Q(\blk00000003/blk000002b8/sig00000ed4 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d4 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/blk000002b8/sig00000ed0 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d3 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/blk000002b8/sig00000ecf ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002b8/blk000002d2 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk000002b8/sig00000ece ), + .A2(\blk00000003/blk000002b8/sig00000ece ), + .A3(\blk00000003/blk000002b8/sig00000ece ), + .CE(\blk00000003/blk000002b8/sig00000ee7 ), + .CLK(clk), + .D(\blk00000003/sig000004e4 ), + .Q(\blk00000003/blk000002b8/sig00000ed1 ), + .Q15(\NLW_blk00000003/blk000002b8/blk000002d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee6 ), + .Q(\blk00000003/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee5 ), + .Q(\blk00000003/sig00000542 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee4 ), + .Q(\blk00000003/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee3 ), + .Q(\blk00000003/sig00000544 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee2 ), + .Q(\blk00000003/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee1 ), + .Q(\blk00000003/sig00000546 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ee0 ), + .Q(\blk00000003/sig00000547 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edf ), + .Q(\blk00000003/sig00000548 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ede ), + .Q(\blk00000003/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edd ), + .Q(\blk00000003/sig0000054a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edc ), + .Q(\blk00000003/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000edb ), + .Q(\blk00000003/sig0000054c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000eda ), + .Q(\blk00000003/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed9 ), + .Q(\blk00000003/sig0000054e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed8 ), + .Q(\blk00000003/sig0000054f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed7 ), + .Q(\blk00000003/sig00000550 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed6 ), + .Q(\blk00000003/sig00000551 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed5 ), + .Q(\blk00000003/sig00000552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed4 ), + .Q(\blk00000003/sig00000553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed3 ), + .Q(\blk00000003/sig00000554 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed2 ), + .Q(\blk00000003/sig00000555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed1 ), + .Q(\blk00000003/sig00000556 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ed0 ), + .Q(\blk00000003/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b8/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b8/sig00000ecf ), + .Q(\blk00000003/sig00000558 ) + ); + GND \blk00000003/blk000002b8/blk000002b9 ( + .G(\blk00000003/blk000002b8/sig00000ece ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002eb/blk0000031d ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk000002eb/sig00000f35 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c3 ), + .Q(\blk00000003/blk000002eb/sig00000f33 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c4 ), + .Q(\blk00000003/blk000002eb/sig00000f32 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000031a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c2 ), + .Q(\blk00000003/blk000002eb/sig00000f34 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000031a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000319 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c6 ), + .Q(\blk00000003/blk000002eb/sig00000f30 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000319_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000318 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c7 ), + .Q(\blk00000003/blk000002eb/sig00000f2f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000318_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000317 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c5 ), + .Q(\blk00000003/blk000002eb/sig00000f31 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000317_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000316 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c9 ), + .Q(\blk00000003/blk000002eb/sig00000f2d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000316_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000315 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ca ), + .Q(\blk00000003/blk000002eb/sig00000f2c ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000315_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000314 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007c8 ), + .Q(\blk00000003/blk000002eb/sig00000f2e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000314_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000313 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cc ), + .Q(\blk00000003/blk000002eb/sig00000f2a ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000312 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cd ), + .Q(\blk00000003/blk000002eb/sig00000f29 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000311 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cb ), + .Q(\blk00000003/blk000002eb/sig00000f2b ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000310 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007cf ), + .Q(\blk00000003/blk000002eb/sig00000f27 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d0 ), + .Q(\blk00000003/blk000002eb/sig00000f26 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007ce ), + .Q(\blk00000003/blk000002eb/sig00000f28 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d2 ), + .Q(\blk00000003/blk000002eb/sig00000f24 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d3 ), + .Q(\blk00000003/blk000002eb/sig00000f23 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d1 ), + .Q(\blk00000003/blk000002eb/sig00000f25 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk0000030a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d5 ), + .Q(\blk00000003/blk000002eb/sig00000f21 ), + .Q15(\NLW_blk00000003/blk000002eb/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000309 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d6 ), + .Q(\blk00000003/blk000002eb/sig00000f20 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000308 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d4 ), + .Q(\blk00000003/blk000002eb/sig00000f22 ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000307 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d8 ), + .Q(\blk00000003/blk000002eb/sig00000f1e ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000306 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d9 ), + .Q(\blk00000003/blk000002eb/sig00000f1d ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002eb/blk00000305 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk000002eb/sig00000f1c ), + .A2(\blk00000003/blk000002eb/sig00000f1c ), + .A3(\blk00000003/blk000002eb/sig00000f1c ), + .CE(\blk00000003/blk000002eb/sig00000f35 ), + .CLK(clk), + .D(\blk00000003/sig000007d7 ), + .Q(\blk00000003/blk000002eb/sig00000f1f ), + .Q15(\NLW_blk00000003/blk000002eb/blk00000305_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000304 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f34 ), + .Q(\blk00000003/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000303 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f33 ), + .Q(\blk00000003/sig0000055a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000302 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f32 ), + .Q(\blk00000003/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000301 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f31 ), + .Q(\blk00000003/sig0000055c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk00000300 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f30 ), + .Q(\blk00000003/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2f ), + .Q(\blk00000003/sig0000055e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2e ), + .Q(\blk00000003/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2d ), + .Q(\blk00000003/sig00000560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2c ), + .Q(\blk00000003/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2b ), + .Q(\blk00000003/sig00000562 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f2a ), + .Q(\blk00000003/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f29 ), + .Q(\blk00000003/sig00000564 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f28 ), + .Q(\blk00000003/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f27 ), + .Q(\blk00000003/sig00000566 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f26 ), + .Q(\blk00000003/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f25 ), + .Q(\blk00000003/sig00000568 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f24 ), + .Q(\blk00000003/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f23 ), + .Q(\blk00000003/sig0000056a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f22 ), + .Q(\blk00000003/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f21 ), + .Q(\blk00000003/sig0000056c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f20 ), + .Q(\blk00000003/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1f ), + .Q(\blk00000003/sig0000056e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1e ), + .Q(\blk00000003/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002eb/sig00000f1d ), + .Q(\blk00000003/sig00000570 ) + ); + GND \blk00000003/blk000002eb/blk000002ec ( + .G(\blk00000003/blk000002eb/sig00000f1c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000031e/blk00000350 ( + .I0(ce), + .I1(\blk00000003/sig0000074e ), + .O(\blk00000003/blk0000031e/sig00000f83 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/blk0000031e/sig00000f81 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/blk0000031e/sig00000f80 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/blk0000031e/sig00000f82 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/blk0000031e/sig00000f7e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/blk0000031e/sig00000f7d ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000034a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/blk0000031e/sig00000f7f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000034a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000349 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/blk0000031e/sig00000f7b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000349_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000348 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/blk0000031e/sig00000f7a ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000348_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000347 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/blk0000031e/sig00000f7c ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000347_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000346 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/blk0000031e/sig00000f78 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000345 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/blk0000031e/sig00000f77 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000344 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/blk0000031e/sig00000f79 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000343 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/blk0000031e/sig00000f75 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000342 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/blk0000031e/sig00000f74 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000341 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/blk0000031e/sig00000f76 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000340 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/blk0000031e/sig00000f72 ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033f ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/blk0000031e/sig00000f71 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033e ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/blk0000031e/sig00000f73 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033d ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/blk0000031e/sig00000f6f ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033c ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/blk0000031e/sig00000f6e ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033b ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/blk0000031e/sig00000f70 ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk0000033a ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/blk0000031e/sig00000f6c ), + .Q15(\NLW_blk00000003/blk0000031e/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000339 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/blk0000031e/sig00000f6b ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000031e/blk00000338 ( + .A0(\blk00000003/sig00000751 ), + .A1(\blk00000003/blk0000031e/sig00000f6a ), + .A2(\blk00000003/blk0000031e/sig00000f6a ), + .A3(\blk00000003/blk0000031e/sig00000f6a ), + .CE(\blk00000003/blk0000031e/sig00000f83 ), + .CLK(clk), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/blk0000031e/sig00000f6d ), + .Q15(\NLW_blk00000003/blk0000031e/blk00000338_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f82 ), + .Q(\blk00000003/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f81 ), + .Q(\blk00000003/sig000006a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f80 ), + .Q(\blk00000003/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7f ), + .Q(\blk00000003/sig000006a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7e ), + .Q(\blk00000003/sig000006a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7d ), + .Q(\blk00000003/sig000006a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7c ), + .Q(\blk00000003/sig000006a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7b ), + .Q(\blk00000003/sig000006aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f7a ), + .Q(\blk00000003/sig000006ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f79 ), + .Q(\blk00000003/sig000006ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f78 ), + .Q(\blk00000003/sig000006ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f77 ), + .Q(\blk00000003/sig000006ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f76 ), + .Q(\blk00000003/sig000006af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f75 ), + .Q(\blk00000003/sig000006b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f74 ), + .Q(\blk00000003/sig000006b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f73 ), + .Q(\blk00000003/sig000006b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f72 ), + .Q(\blk00000003/sig000006b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f71 ), + .Q(\blk00000003/sig000006b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f70 ), + .Q(\blk00000003/sig000006b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6f ), + .Q(\blk00000003/sig000006b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6e ), + .Q(\blk00000003/sig000006b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6d ), + .Q(\blk00000003/sig000006b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6c ), + .Q(\blk00000003/sig000006b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000031e/sig00000f6b ), + .Q(\blk00000003/sig000006ba ) + ); + GND \blk00000003/blk0000031e/blk0000031f ( + .G(\blk00000003/blk0000031e/sig00000f6a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000351/blk00000383 ( + .I0(ce), + .I1(\blk00000003/sig0000074f ), + .O(\blk00000003/blk00000351/sig00000fd1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000382 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007db ), + .Q(\blk00000003/blk00000351/sig00000fcf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000382_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000381 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dc ), + .Q(\blk00000003/blk00000351/sig00000fce ), + .Q15(\NLW_blk00000003/blk00000351/blk00000381_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000380 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007da ), + .Q(\blk00000003/blk00000351/sig00000fd0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000380_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007de ), + .Q(\blk00000003/blk00000351/sig00000fcc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007df ), + .Q(\blk00000003/blk00000351/sig00000fcb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007dd ), + .Q(\blk00000003/blk00000351/sig00000fcd ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e1 ), + .Q(\blk00000003/blk00000351/sig00000fc9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e2 ), + .Q(\blk00000003/blk00000351/sig00000fc8 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000037a ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e0 ), + .Q(\blk00000003/blk00000351/sig00000fca ), + .Q15(\NLW_blk00000003/blk00000351/blk0000037a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000379 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e4 ), + .Q(\blk00000003/blk00000351/sig00000fc6 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000378 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e5 ), + .Q(\blk00000003/blk00000351/sig00000fc5 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000377 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e3 ), + .Q(\blk00000003/blk00000351/sig00000fc7 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000376 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk00000351/sig00000fc3 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000375 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e8 ), + .Q(\blk00000003/blk00000351/sig00000fc2 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000374 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/blk00000351/sig00000fc4 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000373 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ea ), + .Q(\blk00000003/blk00000351/sig00000fc0 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000372 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007eb ), + .Q(\blk00000003/blk00000351/sig00000fbf ), + .Q15(\NLW_blk00000003/blk00000351/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000371 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007e9 ), + .Q(\blk00000003/blk00000351/sig00000fc1 ), + .Q15(\NLW_blk00000003/blk00000351/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk00000370 ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ed ), + .Q(\blk00000003/blk00000351/sig00000fbd ), + .Q15(\NLW_blk00000003/blk00000351/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036f ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ee ), + .Q(\blk00000003/blk00000351/sig00000fbc ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036e ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ec ), + .Q(\blk00000003/blk00000351/sig00000fbe ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036d ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f0 ), + .Q(\blk00000003/blk00000351/sig00000fba ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036c ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007f1 ), + .Q(\blk00000003/blk00000351/sig00000fb9 ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000351/blk0000036b ( + .A0(\blk00000003/sig00000750 ), + .A1(\blk00000003/blk00000351/sig00000fb8 ), + .A2(\blk00000003/blk00000351/sig00000fb8 ), + .A3(\blk00000003/blk00000351/sig00000fb8 ), + .CE(\blk00000003/blk00000351/sig00000fd1 ), + .CLK(clk), + .D(\blk00000003/sig000007ef ), + .Q(\blk00000003/blk00000351/sig00000fbb ), + .Q15(\NLW_blk00000003/blk00000351/blk0000036b_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000036a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fd0 ), + .Q(\blk00000003/sig000006bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000369 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcf ), + .Q(\blk00000003/sig000006bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000368 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fce ), + .Q(\blk00000003/sig000006bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000367 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcd ), + .Q(\blk00000003/sig000006be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000366 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcc ), + .Q(\blk00000003/sig000006bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000365 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fcb ), + .Q(\blk00000003/sig000006c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000364 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fca ), + .Q(\blk00000003/sig000006c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000363 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc9 ), + .Q(\blk00000003/sig000006c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000362 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc8 ), + .Q(\blk00000003/sig000006c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc7 ), + .Q(\blk00000003/sig000006c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc6 ), + .Q(\blk00000003/sig000006c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc5 ), + .Q(\blk00000003/sig000006c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc4 ), + .Q(\blk00000003/sig000006c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc3 ), + .Q(\blk00000003/sig000006c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc2 ), + .Q(\blk00000003/sig000006c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc1 ), + .Q(\blk00000003/sig000006ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fc0 ), + .Q(\blk00000003/sig000006cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbf ), + .Q(\blk00000003/sig000006cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbe ), + .Q(\blk00000003/sig000006cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbd ), + .Q(\blk00000003/sig000006ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbc ), + .Q(\blk00000003/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fbb ), + .Q(\blk00000003/sig000006d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fba ), + .Q(\blk00000003/sig000006d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000351/sig00000fb9 ), + .Q(\blk00000003/sig000006d2 ) + ); + GND \blk00000003/blk00000351/blk00000352 ( + .G(\blk00000003/blk00000351/sig00000fb8 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000384/blk000003b6 ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk00000384/sig0000101f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk00000384/sig0000101d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk00000384/sig0000101c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk00000384/sig0000101e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk00000384/sig0000101a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk00000384/sig00001019 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003b0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk00000384/sig0000101b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003af ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk00000384/sig00001017 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ae ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk00000384/sig00001016 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ad ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk00000384/sig00001018 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ac ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk00000384/sig00001014 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003ab ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk00000384/sig00001013 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003aa ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk00000384/sig00001015 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a9 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk00000384/sig00001011 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a8 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk00000384/sig00001010 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a7 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk00000384/sig00001012 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a6 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk00000384/sig0000100e ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a5 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk00000384/sig0000100d ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a4 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk00000384/sig0000100f ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a3 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk00000384/sig0000100b ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a2 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk00000384/sig0000100a ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a1 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk00000384/sig0000100c ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk000003a0 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk00000384/sig00001008 ), + .Q15(\NLW_blk00000003/blk00000384/blk000003a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk00000384/sig00001007 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000384/blk0000039e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk00000384/sig00001006 ), + .A2(\blk00000003/blk00000384/sig00001006 ), + .A3(\blk00000003/blk00000384/sig00001006 ), + .CE(\blk00000003/blk00000384/sig0000101f ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk00000384/sig00001009 ), + .Q15(\NLW_blk00000003/blk00000384/blk0000039e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101e ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101d ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101c ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101b ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000101a ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001019 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001018 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001017 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001016 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001015 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001014 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001013 ), + .Q(\blk00000003/sig000004da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001012 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001011 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001010 ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100f ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100e ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100d ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100c ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100b ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig0000100a ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001009 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001008 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000384/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000384/sig00001007 ), + .Q(\blk00000003/sig000004e6 ) + ); + GND \blk00000003/blk00000384/blk00000385 ( + .G(\blk00000003/blk00000384/sig00001006 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b7/blk000003e9 ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk000003b7/sig0000106d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f3 ), + .Q(\blk00000003/blk000003b7/sig0000106b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f4 ), + .Q(\blk00000003/blk000003b7/sig0000106a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f2 ), + .Q(\blk00000003/blk000003b7/sig0000106c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f6 ), + .Q(\blk00000003/blk000003b7/sig00001068 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f7 ), + .Q(\blk00000003/blk000003b7/sig00001067 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f5 ), + .Q(\blk00000003/blk000003b7/sig00001069 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f9 ), + .Q(\blk00000003/blk000003b7/sig00001065 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fa ), + .Q(\blk00000003/blk000003b7/sig00001064 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003e0 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007f8 ), + .Q(\blk00000003/blk000003b7/sig00001066 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003df ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fc ), + .Q(\blk00000003/blk000003b7/sig00001062 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003de ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fd ), + .Q(\blk00000003/blk000003b7/sig00001061 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dd ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fb ), + .Q(\blk00000003/blk000003b7/sig00001063 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003dc ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007ff ), + .Q(\blk00000003/blk000003b7/sig0000105f ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003db ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000800 ), + .Q(\blk00000003/blk000003b7/sig0000105e ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003da ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig000007fe ), + .Q(\blk00000003/blk000003b7/sig00001060 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d9 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000802 ), + .Q(\blk00000003/blk000003b7/sig0000105c ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d8 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000803 ), + .Q(\blk00000003/blk000003b7/sig0000105b ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d7 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000801 ), + .Q(\blk00000003/blk000003b7/sig0000105d ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d6 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000805 ), + .Q(\blk00000003/blk000003b7/sig00001059 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d5 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000806 ), + .Q(\blk00000003/blk000003b7/sig00001058 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d4 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000804 ), + .Q(\blk00000003/blk000003b7/sig0000105a ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d3 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000808 ), + .Q(\blk00000003/blk000003b7/sig00001056 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d2 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000809 ), + .Q(\blk00000003/blk000003b7/sig00001055 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003b7/blk000003d1 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk000003b7/sig00001054 ), + .A2(\blk00000003/blk000003b7/sig00001054 ), + .A3(\blk00000003/blk000003b7/sig00001054 ), + .CE(\blk00000003/blk000003b7/sig0000106d ), + .CLK(clk), + .D(\blk00000003/sig00000807 ), + .Q(\blk00000003/blk000003b7/sig00001057 ), + .Q15(\NLW_blk00000003/blk000003b7/blk000003d1_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106c ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106b ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000106a ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001069 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001068 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001067 ), + .Q(\blk00000003/sig000004ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001066 ), + .Q(\blk00000003/sig000004ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001065 ), + .Q(\blk00000003/sig000004ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001064 ), + .Q(\blk00000003/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001063 ), + .Q(\blk00000003/sig000004f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001062 ), + .Q(\blk00000003/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001061 ), + .Q(\blk00000003/sig000004f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001060 ), + .Q(\blk00000003/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105f ), + .Q(\blk00000003/sig000004f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105e ), + .Q(\blk00000003/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105d ), + .Q(\blk00000003/sig000004f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105c ), + .Q(\blk00000003/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105b ), + .Q(\blk00000003/sig000004f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig0000105a ), + .Q(\blk00000003/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001059 ), + .Q(\blk00000003/sig000004fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001058 ), + .Q(\blk00000003/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001057 ), + .Q(\blk00000003/sig000004fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001056 ), + .Q(\blk00000003/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b7/sig00001055 ), + .Q(\blk00000003/sig000004fe ) + ); + GND \blk00000003/blk000003b7/blk000003b8 ( + .G(\blk00000003/blk000003b7/sig00001054 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003ea/blk0000041c ( + .I0(ce), + .I1(\blk00000003/sig00000755 ), + .O(\blk00000003/blk000003ea/sig000010bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/blk000003ea/sig000010b9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000041a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/blk000003ea/sig000010b8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000041a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000419 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/blk000003ea/sig000010ba ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000419_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000418 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/blk000003ea/sig000010b6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000418_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000417 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/blk000003ea/sig000010b5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000417_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000416 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/blk000003ea/sig000010b7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000416_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000415 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/blk000003ea/sig000010b3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000415_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000414 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/blk000003ea/sig000010b2 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000414_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000413 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/blk000003ea/sig000010b4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000413_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000412 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk000003ea/sig000010b0 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000412_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000411 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk000003ea/sig000010af ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000411_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000410 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk000003ea/sig000010b1 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000410_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040f ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk000003ea/sig000010ad ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040e ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk000003ea/sig000010ac ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040d ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk000003ea/sig000010ae ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040c ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk000003ea/sig000010aa ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040b ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/blk000003ea/sig000010a9 ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk0000040a ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk000003ea/sig000010ab ), + .Q15(\NLW_blk00000003/blk000003ea/blk0000040a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000409 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/blk000003ea/sig000010a7 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000409_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000408 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/blk000003ea/sig000010a6 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000408_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000407 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/blk000003ea/sig000010a8 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000407_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000406 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/blk000003ea/sig000010a4 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000406_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000405 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/blk000003ea/sig000010a3 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000405_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000003ea/blk00000404 ( + .A0(\blk00000003/sig00000758 ), + .A1(\blk00000003/blk000003ea/sig000010a2 ), + .A2(\blk00000003/blk000003ea/sig000010a2 ), + .A3(\blk00000003/blk000003ea/sig000010a2 ), + .CE(\blk00000003/blk000003ea/sig000010bb ), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/blk000003ea/sig000010a5 ), + .Q15(\NLW_blk00000003/blk000003ea/blk00000404_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ba ), + .Q(\blk00000003/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b9 ), + .Q(\blk00000003/sig00000644 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b8 ), + .Q(\blk00000003/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b7 ), + .Q(\blk00000003/sig00000646 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b6 ), + .Q(\blk00000003/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b5 ), + .Q(\blk00000003/sig00000648 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b4 ), + .Q(\blk00000003/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b3 ), + .Q(\blk00000003/sig0000064a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b2 ), + .Q(\blk00000003/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b1 ), + .Q(\blk00000003/sig0000064c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010b0 ), + .Q(\blk00000003/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010af ), + .Q(\blk00000003/sig0000064e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ae ), + .Q(\blk00000003/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ad ), + .Q(\blk00000003/sig00000650 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ac ), + .Q(\blk00000003/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010ab ), + .Q(\blk00000003/sig00000652 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010aa ), + .Q(\blk00000003/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a9 ), + .Q(\blk00000003/sig00000654 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a8 ), + .Q(\blk00000003/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a7 ), + .Q(\blk00000003/sig00000656 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a6 ), + .Q(\blk00000003/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a5 ), + .Q(\blk00000003/sig00000658 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a4 ), + .Q(\blk00000003/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003ea/sig000010a3 ), + .Q(\blk00000003/sig0000065a ) + ); + GND \blk00000003/blk000003ea/blk000003eb ( + .G(\blk00000003/blk000003ea/sig000010a2 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041d/blk0000044f ( + .I0(ce), + .I1(\blk00000003/sig00000754 ), + .O(\blk00000003/blk0000041d/sig00001109 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080b ), + .Q(\blk00000003/blk0000041d/sig00001107 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080c ), + .Q(\blk00000003/blk0000041d/sig00001106 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080a ), + .Q(\blk00000003/blk0000041d/sig00001108 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080e ), + .Q(\blk00000003/blk0000041d/sig00001104 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000044a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080f ), + .Q(\blk00000003/blk0000041d/sig00001103 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000044a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000449 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000080d ), + .Q(\blk00000003/blk0000041d/sig00001105 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000449_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000448 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000811 ), + .Q(\blk00000003/blk0000041d/sig00001101 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000448_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000447 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000812 ), + .Q(\blk00000003/blk0000041d/sig00001100 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000447_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000446 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000810 ), + .Q(\blk00000003/blk0000041d/sig00001102 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000446_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000445 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000814 ), + .Q(\blk00000003/blk0000041d/sig000010fe ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000445_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000444 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000815 ), + .Q(\blk00000003/blk0000041d/sig000010fd ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000444_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000443 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000813 ), + .Q(\blk00000003/blk0000041d/sig000010ff ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000443_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000442 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000817 ), + .Q(\blk00000003/blk0000041d/sig000010fb ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000442_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000441 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000818 ), + .Q(\blk00000003/blk0000041d/sig000010fa ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000441_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000440 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000816 ), + .Q(\blk00000003/blk0000041d/sig000010fc ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000440_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043f ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081a ), + .Q(\blk00000003/blk0000041d/sig000010f8 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043e ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081b ), + .Q(\blk00000003/blk0000041d/sig000010f7 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043d ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000819 ), + .Q(\blk00000003/blk0000041d/sig000010f9 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043c ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081d ), + .Q(\blk00000003/blk0000041d/sig000010f5 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043b ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081e ), + .Q(\blk00000003/blk0000041d/sig000010f4 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk0000043a ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081c ), + .Q(\blk00000003/blk0000041d/sig000010f6 ), + .Q15(\NLW_blk00000003/blk0000041d/blk0000043a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000439 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000820 ), + .Q(\blk00000003/blk0000041d/sig000010f2 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000439_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000438 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig00000821 ), + .Q(\blk00000003/blk0000041d/sig000010f1 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000438_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000041d/blk00000437 ( + .A0(\blk00000003/sig00000759 ), + .A1(\blk00000003/blk0000041d/sig000010f0 ), + .A2(\blk00000003/blk0000041d/sig000010f0 ), + .A3(\blk00000003/blk0000041d/sig000010f0 ), + .CE(\blk00000003/blk0000041d/sig00001109 ), + .CLK(clk), + .D(\blk00000003/sig0000081f ), + .Q(\blk00000003/blk0000041d/sig000010f3 ), + .Q15(\NLW_blk00000003/blk0000041d/blk00000437_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000436 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001108 ), + .Q(\blk00000003/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000435 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001107 ), + .Q(\blk00000003/sig0000065c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000434 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001106 ), + .Q(\blk00000003/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000433 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001105 ), + .Q(\blk00000003/sig0000065e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000432 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001104 ), + .Q(\blk00000003/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000431 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001103 ), + .Q(\blk00000003/sig00000660 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000430 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001102 ), + .Q(\blk00000003/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001101 ), + .Q(\blk00000003/sig00000662 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig00001100 ), + .Q(\blk00000003/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010ff ), + .Q(\blk00000003/sig00000664 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fe ), + .Q(\blk00000003/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fd ), + .Q(\blk00000003/sig00000666 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000042a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fc ), + .Q(\blk00000003/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000429 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fb ), + .Q(\blk00000003/sig00000668 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000428 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010fa ), + .Q(\blk00000003/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000427 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f9 ), + .Q(\blk00000003/sig0000066a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000426 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f8 ), + .Q(\blk00000003/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000425 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f7 ), + .Q(\blk00000003/sig0000066c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000424 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f6 ), + .Q(\blk00000003/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000423 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f5 ), + .Q(\blk00000003/sig0000066e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000422 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f4 ), + .Q(\blk00000003/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000421 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f3 ), + .Q(\blk00000003/sig00000670 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk00000420 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f2 ), + .Q(\blk00000003/sig00000671 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d/blk0000041f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000041d/sig000010f1 ), + .Q(\blk00000003/sig00000672 ) + ); + GND \blk00000003/blk0000041d/blk0000041e ( + .G(\blk00000003/blk0000041d/sig000010f0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000450/blk00000482 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk00000450/sig00001157 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000481 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ba ), + .Q(\blk00000003/blk00000450/sig00001155 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000481_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000480 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bb ), + .Q(\blk00000003/blk00000450/sig00001154 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000480_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/blk00000450/sig00001156 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bd ), + .Q(\blk00000003/blk00000450/sig00001152 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002be ), + .Q(\blk00000003/blk00000450/sig00001151 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bc ), + .Q(\blk00000003/blk00000450/sig00001153 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c0 ), + .Q(\blk00000003/blk00000450/sig0000114f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000047a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/blk00000450/sig0000114e ), + .Q15(\NLW_blk00000003/blk00000450/blk0000047a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000479 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002bf ), + .Q(\blk00000003/blk00000450/sig00001150 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000479_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000478 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c3 ), + .Q(\blk00000003/blk00000450/sig0000114c ), + .Q15(\NLW_blk00000003/blk00000450/blk00000478_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000477 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c4 ), + .Q(\blk00000003/blk00000450/sig0000114b ), + .Q15(\NLW_blk00000003/blk00000450/blk00000477_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000476 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/blk00000450/sig0000114d ), + .Q15(\NLW_blk00000003/blk00000450/blk00000476_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000475 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c6 ), + .Q(\blk00000003/blk00000450/sig00001149 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000475_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000474 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c7 ), + .Q(\blk00000003/blk00000450/sig00001148 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000474_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000473 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c5 ), + .Q(\blk00000003/blk00000450/sig0000114a ), + .Q15(\NLW_blk00000003/blk00000450/blk00000473_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000472 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c9 ), + .Q(\blk00000003/blk00000450/sig00001146 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000472_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000471 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ca ), + .Q(\blk00000003/blk00000450/sig00001145 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000471_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk00000470 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002c8 ), + .Q(\blk00000003/blk00000450/sig00001147 ), + .Q15(\NLW_blk00000003/blk00000450/blk00000470_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046f ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cc ), + .Q(\blk00000003/blk00000450/sig00001143 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046e ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cd ), + .Q(\blk00000003/blk00000450/sig00001142 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046d ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cb ), + .Q(\blk00000003/blk00000450/sig00001144 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046c ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002cf ), + .Q(\blk00000003/blk00000450/sig00001140 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046b ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/blk00000450/sig0000113f ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000450/blk0000046a ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk00000450/sig0000113e ), + .A2(\blk00000003/blk00000450/sig0000113e ), + .A3(\blk00000003/blk00000450/sig0000113e ), + .CE(\blk00000003/blk00000450/sig00001157 ), + .CLK(clk), + .D(\blk00000003/sig000002ce ), + .Q(\blk00000003/blk00000450/sig00001141 ), + .Q15(\NLW_blk00000003/blk00000450/blk0000046a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000469 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001156 ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000468 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001155 ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000467 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001154 ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000466 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001153 ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000465 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001152 ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000464 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001151 ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000463 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001150 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000462 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114f ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000461 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114e ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114d ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114c ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114b ), + .Q(\blk00000003/sig00000468 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000114a ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001149 ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001148 ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001147 ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001146 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001145 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001144 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001143 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001142 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001141 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig00001140 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000450/sig0000113f ), + .Q(\blk00000003/sig00000474 ) + ); + GND \blk00000003/blk00000450/blk00000451 ( + .G(\blk00000003/blk00000450/sig0000113e ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000483/blk000004b5 ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk00000483/sig000011a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000823 ), + .Q(\blk00000003/blk00000483/sig000011a3 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000824 ), + .Q(\blk00000003/blk00000483/sig000011a2 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000822 ), + .Q(\blk00000003/blk00000483/sig000011a4 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000826 ), + .Q(\blk00000003/blk00000483/sig000011a0 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004b0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000827 ), + .Q(\blk00000003/blk00000483/sig0000119f ), + .Q15(\NLW_blk00000003/blk00000483/blk000004b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004af ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000825 ), + .Q(\blk00000003/blk00000483/sig000011a1 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ae ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000829 ), + .Q(\blk00000003/blk00000483/sig0000119d ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ad ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082a ), + .Q(\blk00000003/blk00000483/sig0000119c ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ac ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000828 ), + .Q(\blk00000003/blk00000483/sig0000119e ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004ab ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082c ), + .Q(\blk00000003/blk00000483/sig0000119a ), + .Q15(\NLW_blk00000003/blk00000483/blk000004ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004aa ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082d ), + .Q(\blk00000003/blk00000483/sig00001199 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a9 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082b ), + .Q(\blk00000003/blk00000483/sig0000119b ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a8 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082f ), + .Q(\blk00000003/blk00000483/sig00001197 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a7 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000830 ), + .Q(\blk00000003/blk00000483/sig00001196 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a6 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig0000082e ), + .Q(\blk00000003/blk00000483/sig00001198 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a5 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000832 ), + .Q(\blk00000003/blk00000483/sig00001194 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a4 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000833 ), + .Q(\blk00000003/blk00000483/sig00001193 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a3 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000831 ), + .Q(\blk00000003/blk00000483/sig00001195 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a2 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000835 ), + .Q(\blk00000003/blk00000483/sig00001191 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a1 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000836 ), + .Q(\blk00000003/blk00000483/sig00001190 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk000004a0 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000834 ), + .Q(\blk00000003/blk00000483/sig00001192 ), + .Q15(\NLW_blk00000003/blk00000483/blk000004a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000838 ), + .Q(\blk00000003/blk00000483/sig0000118e ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000839 ), + .Q(\blk00000003/blk00000483/sig0000118d ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000483/blk0000049d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk00000483/sig0000118c ), + .A2(\blk00000003/blk00000483/sig0000118c ), + .A3(\blk00000003/blk00000483/sig0000118c ), + .CE(\blk00000003/blk00000483/sig000011a5 ), + .CLK(clk), + .D(\blk00000003/sig00000837 ), + .Q(\blk00000003/blk00000483/sig0000118f ), + .Q15(\NLW_blk00000003/blk00000483/blk0000049d_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a4 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a3 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000049a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a2 ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000499 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a1 ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000498 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig000011a0 ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000497 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119f ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000496 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119e ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000495 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119d ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000494 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119c ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000493 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119b ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000492 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000119a ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000491 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001199 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000490 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001198 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001197 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001196 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001195 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001194 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001193 ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk0000048a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001192 ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000489 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001191 ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000488 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig00001190 ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000487 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118f ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000486 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118e ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483/blk00000485 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000483/sig0000118d ), + .Q(\blk00000003/sig0000048c ) + ); + GND \blk00000003/blk00000483/blk00000484 ( + .G(\blk00000003/blk00000483/sig0000118c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004b6/blk000004e8 ( + .I0(ce), + .I1(\blk00000003/sig0000075d ), + .O(\blk00000003/blk000004b6/sig000011f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031a ), + .Q(\blk00000003/blk000004b6/sig000011f1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031b ), + .Q(\blk00000003/blk000004b6/sig000011f0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000319 ), + .Q(\blk00000003/blk000004b6/sig000011f2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031d ), + .Q(\blk00000003/blk000004b6/sig000011ee ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/blk000004b6/sig000011ed ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/blk000004b6/sig000011ef ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/blk000004b6/sig000011eb ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004e0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000321 ), + .Q(\blk00000003/blk000004b6/sig000011ea ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004df ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000031f ), + .Q(\blk00000003/blk000004b6/sig000011ec ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004de ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000323 ), + .Q(\blk00000003/blk000004b6/sig000011e8 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dd ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000324 ), + .Q(\blk00000003/blk000004b6/sig000011e7 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004dc ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000322 ), + .Q(\blk00000003/blk000004b6/sig000011e9 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004db ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000326 ), + .Q(\blk00000003/blk000004b6/sig000011e5 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004da ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000327 ), + .Q(\blk00000003/blk000004b6/sig000011e4 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d9 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000325 ), + .Q(\blk00000003/blk000004b6/sig000011e6 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d8 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000329 ), + .Q(\blk00000003/blk000004b6/sig000011e2 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d7 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032a ), + .Q(\blk00000003/blk000004b6/sig000011e1 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d6 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000328 ), + .Q(\blk00000003/blk000004b6/sig000011e3 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d5 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032c ), + .Q(\blk00000003/blk000004b6/sig000011df ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d4 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032d ), + .Q(\blk00000003/blk000004b6/sig000011de ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d3 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032b ), + .Q(\blk00000003/blk000004b6/sig000011e0 ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d2 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032f ), + .Q(\blk00000003/blk000004b6/sig000011dc ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d1 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig00000330 ), + .Q(\blk00000003/blk000004b6/sig000011db ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004b6/blk000004d0 ( + .A0(\blk00000003/sig0000075e ), + .A1(\blk00000003/blk000004b6/sig000011da ), + .A2(\blk00000003/blk000004b6/sig000011da ), + .A3(\blk00000003/blk000004b6/sig000011da ), + .CE(\blk00000003/blk000004b6/sig000011f3 ), + .CLK(clk), + .D(\blk00000003/sig0000032e ), + .Q(\blk00000003/blk000004b6/sig000011dd ), + .Q15(\NLW_blk00000003/blk000004b6/blk000004d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f2 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f1 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011f0 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ef ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ee ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ed ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ec ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011eb ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011ea ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e9 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e8 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e7 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e6 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e5 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e4 ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e3 ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e2 ), + .Q(\blk00000003/sig000005f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e1 ), + .Q(\blk00000003/sig000005f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011e0 ), + .Q(\blk00000003/sig000005f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011df ), + .Q(\blk00000003/sig000005f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011de ), + .Q(\blk00000003/sig000005f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dd ), + .Q(\blk00000003/sig000005f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011dc ), + .Q(\blk00000003/sig000005f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004b6/sig000011db ), + .Q(\blk00000003/sig000005fa ) + ); + GND \blk00000003/blk000004b6/blk000004b7 ( + .G(\blk00000003/blk000004b6/sig000011da ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004e9/blk0000051b ( + .I0(ce), + .I1(\blk00000003/sig0000075a ), + .O(\blk00000003/blk000004e9/sig00001241 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000051a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083b ), + .Q(\blk00000003/blk000004e9/sig0000123f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000051a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000519 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083c ), + .Q(\blk00000003/blk000004e9/sig0000123e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000519_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000518 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083a ), + .Q(\blk00000003/blk000004e9/sig00001240 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000518_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000517 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083e ), + .Q(\blk00000003/blk000004e9/sig0000123c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000517_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000516 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083f ), + .Q(\blk00000003/blk000004e9/sig0000123b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000516_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000515 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000083d ), + .Q(\blk00000003/blk000004e9/sig0000123d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000515_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000514 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000841 ), + .Q(\blk00000003/blk000004e9/sig00001239 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000514_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000513 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000842 ), + .Q(\blk00000003/blk000004e9/sig00001238 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000513_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000512 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000840 ), + .Q(\blk00000003/blk000004e9/sig0000123a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000512_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000511 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000844 ), + .Q(\blk00000003/blk000004e9/sig00001236 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000511_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000510 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000845 ), + .Q(\blk00000003/blk000004e9/sig00001235 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000510_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050f ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000843 ), + .Q(\blk00000003/blk000004e9/sig00001237 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050e ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000847 ), + .Q(\blk00000003/blk000004e9/sig00001233 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050d ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000848 ), + .Q(\blk00000003/blk000004e9/sig00001232 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050c ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000846 ), + .Q(\blk00000003/blk000004e9/sig00001234 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050b ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084a ), + .Q(\blk00000003/blk000004e9/sig00001230 ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk0000050a ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084b ), + .Q(\blk00000003/blk000004e9/sig0000122f ), + .Q15(\NLW_blk00000003/blk000004e9/blk0000050a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000509 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000849 ), + .Q(\blk00000003/blk000004e9/sig00001231 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000509_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000508 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084d ), + .Q(\blk00000003/blk000004e9/sig0000122d ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000508_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000507 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084e ), + .Q(\blk00000003/blk000004e9/sig0000122c ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000507_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000506 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084c ), + .Q(\blk00000003/blk000004e9/sig0000122e ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000506_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000505 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000850 ), + .Q(\blk00000003/blk000004e9/sig0000122a ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000505_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000504 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig00000851 ), + .Q(\blk00000003/blk000004e9/sig00001229 ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000504_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e9/blk00000503 ( + .A0(\blk00000003/sig0000075f ), + .A1(\blk00000003/blk000004e9/sig00001228 ), + .A2(\blk00000003/blk000004e9/sig00001228 ), + .A3(\blk00000003/blk000004e9/sig00001228 ), + .CE(\blk00000003/blk000004e9/sig00001241 ), + .CLK(clk), + .D(\blk00000003/sig0000084f ), + .Q(\blk00000003/blk000004e9/sig0000122b ), + .Q15(\NLW_blk00000003/blk000004e9/blk00000503_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001240 ), + .Q(\blk00000003/sig000005fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123f ), + .Q(\blk00000003/sig000005fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123e ), + .Q(\blk00000003/sig000005fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123d ), + .Q(\blk00000003/sig000005fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123c ), + .Q(\blk00000003/sig000005ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123b ), + .Q(\blk00000003/sig00000600 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000123a ), + .Q(\blk00000003/sig00000601 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001239 ), + .Q(\blk00000003/sig00000602 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001238 ), + .Q(\blk00000003/sig00000603 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001237 ), + .Q(\blk00000003/sig00000604 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001236 ), + .Q(\blk00000003/sig00000605 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001235 ), + .Q(\blk00000003/sig00000606 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001234 ), + .Q(\blk00000003/sig00000607 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001233 ), + .Q(\blk00000003/sig00000608 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001232 ), + .Q(\blk00000003/sig00000609 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001231 ), + .Q(\blk00000003/sig0000060a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001230 ), + .Q(\blk00000003/sig0000060b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122f ), + .Q(\blk00000003/sig0000060c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122e ), + .Q(\blk00000003/sig0000060d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122d ), + .Q(\blk00000003/sig0000060e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122c ), + .Q(\blk00000003/sig0000060f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122b ), + .Q(\blk00000003/sig00000610 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig0000122a ), + .Q(\blk00000003/sig00000611 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004e9/sig00001229 ), + .Q(\blk00000003/sig00000612 ) + ); + GND \blk00000003/blk000004e9/blk000004ea ( + .G(\blk00000003/blk000004e9/sig00001228 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000051c/blk0000054e ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk0000051c/sig0000128f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000853 ), + .Q(\blk00000003/blk0000051c/sig0000128d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000854 ), + .Q(\blk00000003/blk0000051c/sig0000128c ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000852 ), + .Q(\blk00000003/blk0000051c/sig0000128e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000054a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000856 ), + .Q(\blk00000003/blk0000051c/sig0000128a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000054a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000549 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000857 ), + .Q(\blk00000003/blk0000051c/sig00001289 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000549_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000548 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000855 ), + .Q(\blk00000003/blk0000051c/sig0000128b ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000548_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000547 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000859 ), + .Q(\blk00000003/blk0000051c/sig00001287 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000547_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000546 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085a ), + .Q(\blk00000003/blk0000051c/sig00001286 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000546_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000545 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000858 ), + .Q(\blk00000003/blk0000051c/sig00001288 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000545_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000544 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085c ), + .Q(\blk00000003/blk0000051c/sig00001284 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000544_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000543 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085d ), + .Q(\blk00000003/blk0000051c/sig00001283 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000543_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000542 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085b ), + .Q(\blk00000003/blk0000051c/sig00001285 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000542_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000541 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085f ), + .Q(\blk00000003/blk0000051c/sig00001281 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000541_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000540 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000860 ), + .Q(\blk00000003/blk0000051c/sig00001280 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000540_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig0000085e ), + .Q(\blk00000003/blk0000051c/sig00001282 ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000862 ), + .Q(\blk00000003/blk0000051c/sig0000127e ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000863 ), + .Q(\blk00000003/blk0000051c/sig0000127d ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000861 ), + .Q(\blk00000003/blk0000051c/sig0000127f ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053b ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000865 ), + .Q(\blk00000003/blk0000051c/sig0000127b ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk0000053a ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000866 ), + .Q(\blk00000003/blk0000051c/sig0000127a ), + .Q15(\NLW_blk00000003/blk0000051c/blk0000053a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000539 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000864 ), + .Q(\blk00000003/blk0000051c/sig0000127c ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000539_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000538 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000868 ), + .Q(\blk00000003/blk0000051c/sig00001278 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000538_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000537 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000869 ), + .Q(\blk00000003/blk0000051c/sig00001277 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000537_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c/blk00000536 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk0000051c/sig00001276 ), + .A2(\blk00000003/blk0000051c/sig00001276 ), + .A3(\blk00000003/blk0000051c/sig00001276 ), + .CE(\blk00000003/blk0000051c/sig0000128f ), + .CLK(clk), + .D(\blk00000003/sig00000867 ), + .Q(\blk00000003/blk0000051c/sig00001279 ), + .Q15(\NLW_blk00000003/blk0000051c/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128e ), + .Q(\blk00000003/sig000002b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128d ), + .Q(\blk00000003/sig000002ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128c ), + .Q(\blk00000003/sig000002bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128b ), + .Q(\blk00000003/sig000002bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000128a ), + .Q(\blk00000003/sig000002bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001289 ), + .Q(\blk00000003/sig000002be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001288 ), + .Q(\blk00000003/sig000002bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001287 ), + .Q(\blk00000003/sig000002c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001286 ), + .Q(\blk00000003/sig000002c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001285 ), + .Q(\blk00000003/sig000002c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001284 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001283 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001282 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001281 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001280 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127f ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127e ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127d ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127c ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127b ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig0000127a ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001279 ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001278 ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000051c/sig00001277 ), + .Q(\blk00000003/sig000002d0 ) + ); + GND \blk00000003/blk0000051c/blk0000051d ( + .G(\blk00000003/blk0000051c/sig00001276 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000054f/blk00000581 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk0000054f/sig000012dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000580 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086b ), + .Q(\blk00000003/blk0000054f/sig000012db ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000580_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086c ), + .Q(\blk00000003/blk0000054f/sig000012da ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086a ), + .Q(\blk00000003/blk0000054f/sig000012dc ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086e ), + .Q(\blk00000003/blk0000054f/sig000012d8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086f ), + .Q(\blk00000003/blk0000054f/sig000012d7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000086d ), + .Q(\blk00000003/blk0000054f/sig000012d9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000057a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000871 ), + .Q(\blk00000003/blk0000054f/sig000012d5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000057a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000579 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000872 ), + .Q(\blk00000003/blk0000054f/sig000012d4 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000579_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000578 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000870 ), + .Q(\blk00000003/blk0000054f/sig000012d6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000578_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000577 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000874 ), + .Q(\blk00000003/blk0000054f/sig000012d2 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000577_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000576 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000875 ), + .Q(\blk00000003/blk0000054f/sig000012d1 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000576_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000575 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000873 ), + .Q(\blk00000003/blk0000054f/sig000012d3 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000575_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000574 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000877 ), + .Q(\blk00000003/blk0000054f/sig000012cf ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000574_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000573 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000878 ), + .Q(\blk00000003/blk0000054f/sig000012ce ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000573_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000572 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000876 ), + .Q(\blk00000003/blk0000054f/sig000012d0 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000572_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000571 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087a ), + .Q(\blk00000003/blk0000054f/sig000012cc ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000571_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000570 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087b ), + .Q(\blk00000003/blk0000054f/sig000012cb ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000570_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056f ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000879 ), + .Q(\blk00000003/blk0000054f/sig000012cd ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056e ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087d ), + .Q(\blk00000003/blk0000054f/sig000012c9 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056d ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087e ), + .Q(\blk00000003/blk0000054f/sig000012c8 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056c ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087c ), + .Q(\blk00000003/blk0000054f/sig000012ca ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056b ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000880 ), + .Q(\blk00000003/blk0000054f/sig000012c6 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk0000056a ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig00000881 ), + .Q(\blk00000003/blk0000054f/sig000012c5 ), + .Q15(\NLW_blk00000003/blk0000054f/blk0000056a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054f/blk00000569 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk0000054f/sig000012c4 ), + .A2(\blk00000003/blk0000054f/sig000012c4 ), + .A3(\blk00000003/blk0000054f/sig000012c4 ), + .CE(\blk00000003/blk0000054f/sig000012dd ), + .CLK(clk), + .D(\blk00000003/sig0000087f ), + .Q(\blk00000003/blk0000054f/sig000012c7 ), + .Q15(\NLW_blk00000003/blk0000054f/blk00000569_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000568 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012dc ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012db ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000566 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012da ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d9 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000564 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d8 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d7 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000562 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000560 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012d0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk0000055a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ce ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000558 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012cb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000556 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012ca ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000554 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000552 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000054f/sig000012c5 ), + .Q(\blk00000003/sig000002e8 ) + ); + GND \blk00000003/blk0000054f/blk00000550 ( + .G(\blk00000003/blk0000054f/sig000012c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000582/blk000005b4 ( + .I0(ce), + .I1(\blk00000003/sig00000761 ), + .O(\blk00000003/blk00000582/sig0000132b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000883 ), + .Q(\blk00000003/blk00000582/sig00001329 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000884 ), + .Q(\blk00000003/blk00000582/sig00001328 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000882 ), + .Q(\blk00000003/blk00000582/sig0000132a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005b0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000886 ), + .Q(\blk00000003/blk00000582/sig00001326 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005af ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000887 ), + .Q(\blk00000003/blk00000582/sig00001325 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ae ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000885 ), + .Q(\blk00000003/blk00000582/sig00001327 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ad ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000889 ), + .Q(\blk00000003/blk00000582/sig00001323 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ac ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088a ), + .Q(\blk00000003/blk00000582/sig00001322 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005ab ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000888 ), + .Q(\blk00000003/blk00000582/sig00001324 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005aa ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088c ), + .Q(\blk00000003/blk00000582/sig00001320 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a9 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088d ), + .Q(\blk00000003/blk00000582/sig0000131f ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a8 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088b ), + .Q(\blk00000003/blk00000582/sig00001321 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a7 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088f ), + .Q(\blk00000003/blk00000582/sig0000131d ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a6 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000890 ), + .Q(\blk00000003/blk00000582/sig0000131c ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a5 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig0000088e ), + .Q(\blk00000003/blk00000582/sig0000131e ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a4 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000892 ), + .Q(\blk00000003/blk00000582/sig0000131a ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a3 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000893 ), + .Q(\blk00000003/blk00000582/sig00001319 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a2 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000891 ), + .Q(\blk00000003/blk00000582/sig0000131b ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a1 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000895 ), + .Q(\blk00000003/blk00000582/sig00001317 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk000005a0 ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000896 ), + .Q(\blk00000003/blk00000582/sig00001316 ), + .Q15(\NLW_blk00000003/blk00000582/blk000005a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059f ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000894 ), + .Q(\blk00000003/blk00000582/sig00001318 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059e ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000898 ), + .Q(\blk00000003/blk00000582/sig00001314 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059d ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/blk00000582/sig00001313 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582/blk0000059c ( + .A0(\blk00000003/sig0000029a ), + .A1(\blk00000003/blk00000582/sig00001312 ), + .A2(\blk00000003/blk00000582/sig00001312 ), + .A3(\blk00000003/blk00000582/sig00001312 ), + .CE(\blk00000003/blk00000582/sig0000132b ), + .CLK(clk), + .D(\blk00000003/sig00000897 ), + .Q(\blk00000003/blk00000582/sig00001315 ), + .Q15(\NLW_blk00000003/blk00000582/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000132a ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000059a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001329 ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000599 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001328 ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000598 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001327 ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000597 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001326 ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000596 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001325 ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001324 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000594 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001323 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001322 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000592 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001321 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000591 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001320 ), + .Q(\blk00000003/sig00000323 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000590 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131f ), + .Q(\blk00000003/sig00000324 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131e ), + .Q(\blk00000003/sig00000325 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131d ), + .Q(\blk00000003/sig00000326 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131c ), + .Q(\blk00000003/sig00000327 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131b ), + .Q(\blk00000003/sig00000328 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig0000131a ), + .Q(\blk00000003/sig00000329 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk0000058a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001319 ), + .Q(\blk00000003/sig0000032a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001318 ), + .Q(\blk00000003/sig0000032b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000588 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001317 ), + .Q(\blk00000003/sig0000032c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001316 ), + .Q(\blk00000003/sig0000032d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000586 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001315 ), + .Q(\blk00000003/sig0000032e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001314 ), + .Q(\blk00000003/sig0000032f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000582/blk00000584 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000582/sig00001313 ), + .Q(\blk00000003/sig00000330 ) + ); + GND \blk00000003/blk00000582/blk00000583 ( + .G(\blk00000003/blk00000582/sig00001312 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005b5/blk000005e7 ( + .I0(ce), + .I1(\blk00000003/sig00000760 ), + .O(\blk00000003/blk000005b5/sig00001379 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/blk000005b5/sig00001377 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/blk000005b5/sig00001376 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/blk000005b5/sig00001378 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/blk000005b5/sig00001374 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/blk000005b5/sig00001373 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/blk000005b5/sig00001375 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005e0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/blk000005b5/sig00001371 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005df ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/blk000005b5/sig00001370 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005de ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/blk000005b5/sig00001372 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dd ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/blk000005b5/sig0000136e ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005dc ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/blk000005b5/sig0000136d ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005db ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/blk000005b5/sig0000136f ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005da ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/blk000005b5/sig0000136b ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d9 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/blk000005b5/sig0000136a ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d8 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/blk000005b5/sig0000136c ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d7 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/blk000005b5/sig00001368 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d6 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/blk000005b5/sig00001367 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d5 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/blk000005b5/sig00001369 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d4 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ad ), + .Q(\blk00000003/blk000005b5/sig00001365 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d3 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ae ), + .Q(\blk00000003/blk000005b5/sig00001364 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d2 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/blk000005b5/sig00001366 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d1 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b0 ), + .Q(\blk00000003/blk000005b5/sig00001362 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005d0 ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008b1 ), + .Q(\blk00000003/blk000005b5/sig00001361 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b5/blk000005cf ( + .A0(\blk00000003/sig00000295 ), + .A1(\blk00000003/blk000005b5/sig00001360 ), + .A2(\blk00000003/blk000005b5/sig00001360 ), + .A3(\blk00000003/blk000005b5/sig00001360 ), + .CE(\blk00000003/blk000005b5/sig00001379 ), + .CLK(clk), + .D(\blk00000003/sig000008af ), + .Q(\blk00000003/blk000005b5/sig00001363 ), + .Q15(\NLW_blk00000003/blk000005b5/blk000005cf_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001378 ), + .Q(\blk00000003/sig00000331 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001377 ), + .Q(\blk00000003/sig00000332 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001376 ), + .Q(\blk00000003/sig00000333 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001375 ), + .Q(\blk00000003/sig00000334 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001374 ), + .Q(\blk00000003/sig00000335 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001373 ), + .Q(\blk00000003/sig00000336 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001372 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001371 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001370 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136f ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136e ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136d ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136c ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136b ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig0000136a ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001369 ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001368 ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001367 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001366 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001365 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001364 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001363 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001362 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5/blk000005b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005b5/sig00001361 ), + .Q(\blk00000003/sig00000348 ) + ); + GND \blk00000003/blk000005b5/blk000005b6 ( + .G(\blk00000003/blk000005b5/sig00001360 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005e8/blk00000620 ( + .I0(ce), + .I1(\blk00000003/sig00000237 ), + .O(\blk00000003/blk000005e8/sig000013dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c9 ), + .DPO(\blk00000003/blk000005e8/sig000013db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c8 ), + .DPO(\blk00000003/blk000005e8/sig000013da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061d ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c7 ), + .DPO(\blk00000003/blk000005e8/sig000013d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061c ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c6 ), + .DPO(\blk00000003/blk000005e8/sig000013d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061b ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c5 ), + .DPO(\blk00000003/blk000005e8/sig000013d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk0000061a ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c4 ), + .DPO(\blk00000003/blk000005e8/sig000013d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000619 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c2 ), + .DPO(\blk00000003/blk000005e8/sig000013d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000618 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c1 ), + .DPO(\blk00000003/blk000005e8/sig000013d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000617 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c3 ), + .DPO(\blk00000003/blk000005e8/sig000013d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000005e8/blk00000616 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013c0 ), + .DPO(\blk00000003/blk000005e8/sig000013d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000615 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bf ), + .DPO(\blk00000003/blk000005e8/sig000013d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000614 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013be ), + .DPO(\blk00000003/blk000005e8/sig000013d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000613 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bd ), + .DPO(\blk00000003/blk000005e8/sig000013cf ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000612 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bc ), + .DPO(\blk00000003/blk000005e8/sig000013ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk00000611 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013bb ), + .DPO(\blk00000003/blk000005e8/sig000013cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000005e8/blk00000610 ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b9 ), + .DPO(\blk00000003/blk000005e8/sig000013cb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060f ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013b8 ), + .DPO(\blk00000003/blk000005e8/sig000013ca ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000005e8/blk0000060e ( + .A0(\blk00000003/sig0000025f ), + .A1(\blk00000003/sig00000262 ), + .A2(\blk00000003/blk000005e8/sig000013b7 ), + .A3(\blk00000003/blk000005e8/sig000013b7 ), + .A4(\blk00000003/blk000005e8/sig000013b7 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig000002a0 ), + .DPRA1(\blk00000003/sig000002a6 ), + .DPRA2(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA3(\blk00000003/blk000005e8/sig000013b7 ), + .DPRA4(\blk00000003/blk000005e8/sig000013b7 ), + .WCLK(clk), + .WE(\blk00000003/blk000005e8/sig000013dc ), + .SPO(\blk00000003/blk000005e8/sig000013ba ), + .DPO(\blk00000003/blk000005e8/sig000013cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013db ), + .Q(\blk00000003/sig000002a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013da ), + .Q(\blk00000003/sig000002a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d9 ), + .Q(\blk00000003/sig000002a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk0000060a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d8 ), + .Q(\blk00000003/sig000002aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d7 ), + .Q(\blk00000003/sig000002ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000608 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d6 ), + .Q(\blk00000003/sig000002ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d5 ), + .Q(\blk00000003/sig000002ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000606 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d4 ), + .Q(\blk00000003/sig000002ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d3 ), + .Q(\blk00000003/sig000002af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000604 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d1 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000602 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013d0 ), + .Q(\blk00000003/sig000002b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cf ), + .Q(\blk00000003/sig000002b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk00000600 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ce ), + .Q(\blk00000003/sig000002b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cd ), + .Q(\blk00000003/sig000002b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cc ), + .Q(\blk00000003/sig000002b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013cb ), + .Q(\blk00000003/sig000002b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ca ), + .Q(\blk00000003/sig000002b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c9 ), + .Q(\blk00000003/sig000008c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c8 ), + .Q(\blk00000003/sig000008c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c7 ), + .Q(\blk00000003/sig000008c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c6 ), + .Q(\blk00000003/sig000008c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c5 ), + .Q(\blk00000003/sig000008c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c4 ), + .Q(\blk00000003/sig000008c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c3 ), + .Q(\blk00000003/sig000008ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c2 ), + .Q(\blk00000003/sig000008cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c1 ), + .Q(\blk00000003/sig000008cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013c0 ), + .Q(\blk00000003/sig000008cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bf ), + .Q(\blk00000003/sig000008ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013be ), + .Q(\blk00000003/sig000008cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bd ), + .Q(\blk00000003/sig000008d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bc ), + .Q(\blk00000003/sig000008d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013bb ), + .Q(\blk00000003/sig000008d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013ba ), + .Q(\blk00000003/sig000008d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b9 ), + .Q(\blk00000003/sig000008d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8/blk000005ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000005e8/sig000013b8 ), + .Q(\blk00000003/sig000008d5 ) + ); + GND \blk00000003/blk000005e8/blk000005e9 ( + .G(\blk00000003/blk000005e8/sig000013b7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000621/blk00000659 ( + .I0(ce), + .I1(\blk00000003/sig0000073d ), + .O(\blk00000003/blk00000621/sig0000143f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000658 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142c ), + .DPO(\blk00000003/blk00000621/sig0000143e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000657 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142b ), + .DPO(\blk00000003/blk00000621/sig0000143d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000656 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c6 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000142a ), + .DPO(\blk00000003/blk00000621/sig0000143c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000655 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c7 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001429 ), + .DPO(\blk00000003/blk00000621/sig0000143b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000654 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c8 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001428 ), + .DPO(\blk00000003/blk00000621/sig0000143a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000653 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008c9 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001427 ), + .DPO(\blk00000003/blk00000621/sig00001439 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000652 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cb ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001425 ), + .DPO(\blk00000003/blk00000621/sig00001437 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk00000651 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cc ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001424 ), + .DPO(\blk00000003/blk00000621/sig00001436 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk00000650 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ca ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001426 ), + .DPO(\blk00000003/blk00000621/sig00001438 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064f ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cd ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001423 ), + .DPO(\blk00000003/blk00000621/sig00001435 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064e ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008ce ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001422 ), + .DPO(\blk00000003/blk00000621/sig00001434 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000621/blk0000064d ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008cf ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001421 ), + .DPO(\blk00000003/blk00000621/sig00001433 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000621/blk0000064c ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d0 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig00001420 ), + .DPO(\blk00000003/blk00000621/sig00001432 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk0000064b ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d1 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141f ), + .DPO(\blk00000003/blk00000621/sig00001431 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000621/blk0000064a ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d2 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141e ), + .DPO(\blk00000003/blk00000621/sig00001430 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000649 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d4 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141c ), + .DPO(\blk00000003/blk00000621/sig0000142e ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000648 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d5 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141b ), + .DPO(\blk00000003/blk00000621/sig0000142d ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000621/blk00000647 ( + .A0(\blk00000003/sig00000733 ), + .A1(\blk00000003/sig00000734 ), + .A2(\blk00000003/blk00000621/sig0000141a ), + .A3(\blk00000003/blk00000621/sig0000141a ), + .A4(\blk00000003/blk00000621/sig0000141a ), + .D(\blk00000003/sig000008d3 ), + .DPRA0(\blk00000003/sig0000075c ), + .DPRA1(\blk00000003/sig0000075b ), + .DPRA2(\blk00000003/blk00000621/sig0000141a ), + .DPRA3(\blk00000003/blk00000621/sig0000141a ), + .DPRA4(\blk00000003/blk00000621/sig0000141a ), + .WCLK(clk), + .WE(\blk00000003/blk00000621/sig0000143f ), + .SPO(\blk00000003/blk00000621/sig0000141d ), + .DPO(\blk00000003/blk00000621/sig0000142f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000646 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143e ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143d ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000644 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143c ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143b ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000642 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000143a ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001439 ), + .Q(\blk00000003/sig00000450 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000640 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001438 ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001437 ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001436 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001435 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001434 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001433 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000063a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001432 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001431 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000638 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001430 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142f ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000636 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142e ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142d ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000634 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142c ), + .Q(\blk00000003/sig000008d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142b ), + .Q(\blk00000003/sig000008d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000632 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000142a ), + .Q(\blk00000003/sig000008d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001429 ), + .Q(\blk00000003/sig000008d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000630 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001428 ), + .Q(\blk00000003/sig000008da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001427 ), + .Q(\blk00000003/sig000008db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001426 ), + .Q(\blk00000003/sig000008dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001425 ), + .Q(\blk00000003/sig000008dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001424 ), + .Q(\blk00000003/sig000008de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001423 ), + .Q(\blk00000003/sig000008df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk0000062a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001422 ), + .Q(\blk00000003/sig000008e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001421 ), + .Q(\blk00000003/sig000008e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000628 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig00001420 ), + .Q(\blk00000003/sig000008e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141f ), + .Q(\blk00000003/sig000008e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000626 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141e ), + .Q(\blk00000003/sig000008e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141d ), + .Q(\blk00000003/sig000008e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000624 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141c ), + .Q(\blk00000003/sig000008e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000621/sig0000141b ), + .Q(\blk00000003/sig000008e7 ) + ); + GND \blk00000003/blk00000621/blk00000622 ( + .G(\blk00000003/blk00000621/sig0000141a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000065a/blk00000692 ( + .I0(ce), + .I1(\blk00000003/sig0000073e ), + .O(\blk00000003/blk0000065a/sig000014a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000691 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148f ), + .DPO(\blk00000003/blk0000065a/sig000014a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000690 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148e ), + .DPO(\blk00000003/blk0000065a/sig000014a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068f ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d8 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148d ), + .DPO(\blk00000003/blk0000065a/sig0000149f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068e ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008d9 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148c ), + .DPO(\blk00000003/blk0000065a/sig0000149e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068d ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008da ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148b ), + .DPO(\blk00000003/blk0000065a/sig0000149d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068c ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008db ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000148a ), + .DPO(\blk00000003/blk0000065a/sig0000149c ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk0000068b ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dd ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001488 ), + .DPO(\blk00000003/blk0000065a/sig0000149a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk0000068a ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008de ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001487 ), + .DPO(\blk00000003/blk0000065a/sig00001499 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000689 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008dc ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001489 ), + .DPO(\blk00000003/blk0000065a/sig0000149b ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000688 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008df ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001486 ), + .DPO(\blk00000003/blk0000065a/sig00001498 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000687 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e0 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001485 ), + .DPO(\blk00000003/blk0000065a/sig00001497 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000065a/blk00000686 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e1 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001484 ), + .DPO(\blk00000003/blk0000065a/sig00001496 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000065a/blk00000685 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e2 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001483 ), + .DPO(\blk00000003/blk0000065a/sig00001495 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000684 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e3 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001482 ), + .DPO(\blk00000003/blk0000065a/sig00001494 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000683 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e4 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001481 ), + .DPO(\blk00000003/blk0000065a/sig00001493 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000682 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e6 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147f ), + .DPO(\blk00000003/blk0000065a/sig00001491 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000065a/blk00000681 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e7 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig0000147e ), + .DPO(\blk00000003/blk0000065a/sig00001490 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000065a/blk00000680 ( + .A0(\blk00000003/sig00000735 ), + .A1(\blk00000003/sig00000736 ), + .A2(\blk00000003/blk0000065a/sig0000147d ), + .A3(\blk00000003/blk0000065a/sig0000147d ), + .A4(\blk00000003/blk0000065a/sig0000147d ), + .D(\blk00000003/sig000008e5 ), + .DPRA0(\blk00000003/sig00000757 ), + .DPRA1(\blk00000003/sig00000756 ), + .DPRA2(\blk00000003/blk0000065a/sig0000147d ), + .DPRA3(\blk00000003/blk0000065a/sig0000147d ), + .DPRA4(\blk00000003/blk0000065a/sig0000147d ), + .WCLK(clk), + .WE(\blk00000003/blk0000065a/sig000014a2 ), + .SPO(\blk00000003/blk0000065a/sig00001480 ), + .DPO(\blk00000003/blk0000065a/sig00001492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a1 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig000014a0 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149f ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149e ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149d ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000067a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149c ), + .Q(\blk00000003/sig000004c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149b ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000678 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000149a ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001499 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000676 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001498 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001497 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000674 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001496 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001495 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000672 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001494 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001493 ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000670 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001492 ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001491 ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001490 ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148f ), + .Q(\blk00000003/sig000008e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148e ), + .Q(\blk00000003/sig000008e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148d ), + .Q(\blk00000003/sig000008ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000066a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148c ), + .Q(\blk00000003/sig000008eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148b ), + .Q(\blk00000003/sig000008ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000668 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000148a ), + .Q(\blk00000003/sig000008ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001489 ), + .Q(\blk00000003/sig000008ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000666 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001488 ), + .Q(\blk00000003/sig000008ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001487 ), + .Q(\blk00000003/sig000008f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000664 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001486 ), + .Q(\blk00000003/sig000008f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001485 ), + .Q(\blk00000003/sig000008f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000662 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001484 ), + .Q(\blk00000003/sig000008f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001483 ), + .Q(\blk00000003/sig000008f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk00000660 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001482 ), + .Q(\blk00000003/sig000008f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001481 ), + .Q(\blk00000003/sig000008f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig00001480 ), + .Q(\blk00000003/sig000008f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147f ), + .Q(\blk00000003/sig000008f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065a/blk0000065c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000065a/sig0000147e ), + .Q(\blk00000003/sig000008f9 ) + ); + GND \blk00000003/blk0000065a/blk0000065b ( + .G(\blk00000003/blk0000065a/sig0000147d ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000693/blk000006cb ( + .I0(ce), + .I1(\blk00000003/sig0000073f ), + .O(\blk00000003/blk00000693/sig00001505 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006ca ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f2 ), + .DPO(\blk00000003/blk00000693/sig00001504 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008e9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f1 ), + .DPO(\blk00000003/blk00000693/sig00001503 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c8 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ea ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014f0 ), + .DPO(\blk00000003/blk00000693/sig00001502 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c7 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008eb ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ef ), + .DPO(\blk00000003/blk00000693/sig00001501 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c6 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ec ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ee ), + .DPO(\blk00000003/blk00000693/sig00001500 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006c5 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ed ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ed ), + .DPO(\blk00000003/blk00000693/sig000014ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c4 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ef ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014eb ), + .DPO(\blk00000003/blk00000693/sig000014fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c3 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f0 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ea ), + .DPO(\blk00000003/blk00000693/sig000014fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006c2 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008ee ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014ec ), + .DPO(\blk00000003/blk00000693/sig000014fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006c1 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f1 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e9 ), + .DPO(\blk00000003/blk00000693/sig000014fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000693/blk000006c0 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f2 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e8 ), + .DPO(\blk00000003/blk00000693/sig000014fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006bf ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f3 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e7 ), + .DPO(\blk00000003/blk00000693/sig000014f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006be ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f4 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e6 ), + .DPO(\blk00000003/blk00000693/sig000014f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bd ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f5 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e5 ), + .DPO(\blk00000003/blk00000693/sig000014f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006bc ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f6 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e4 ), + .DPO(\blk00000003/blk00000693/sig000014f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000693/blk000006bb ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f8 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e2 ), + .DPO(\blk00000003/blk00000693/sig000014f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000693/blk000006ba ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f9 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e1 ), + .DPO(\blk00000003/blk00000693/sig000014f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000693/blk000006b9 ( + .A0(\blk00000003/sig00000737 ), + .A1(\blk00000003/sig00000738 ), + .A2(\blk00000003/blk00000693/sig000014e0 ), + .A3(\blk00000003/blk00000693/sig000014e0 ), + .A4(\blk00000003/blk00000693/sig000014e0 ), + .D(\blk00000003/sig000008f7 ), + .DPRA0(\blk00000003/sig00000753 ), + .DPRA1(\blk00000003/sig00000752 ), + .DPRA2(\blk00000003/blk00000693/sig000014e0 ), + .DPRA3(\blk00000003/blk00000693/sig000014e0 ), + .DPRA4(\blk00000003/blk00000693/sig000014e0 ), + .WCLK(clk), + .WE(\blk00000003/blk00000693/sig00001505 ), + .SPO(\blk00000003/blk00000693/sig000014e3 ), + .DPO(\blk00000003/blk00000693/sig000014f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001504 ), + .Q(\blk00000003/sig0000052f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001503 ), + .Q(\blk00000003/sig00000530 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001502 ), + .Q(\blk00000003/sig00000531 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001501 ), + .Q(\blk00000003/sig00000532 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig00001500 ), + .Q(\blk00000003/sig00000533 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ff ), + .Q(\blk00000003/sig00000534 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fe ), + .Q(\blk00000003/sig00000535 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fd ), + .Q(\blk00000003/sig00000536 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fc ), + .Q(\blk00000003/sig00000537 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fb ), + .Q(\blk00000003/sig00000538 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014fa ), + .Q(\blk00000003/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f9 ), + .Q(\blk00000003/sig0000053a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f8 ), + .Q(\blk00000003/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f7 ), + .Q(\blk00000003/sig0000053c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f6 ), + .Q(\blk00000003/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f5 ), + .Q(\blk00000003/sig0000053e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f4 ), + .Q(\blk00000003/sig0000053f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f3 ), + .Q(\blk00000003/sig00000540 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f2 ), + .Q(\blk00000003/sig000008fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f1 ), + .Q(\blk00000003/sig000008fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014f0 ), + .Q(\blk00000003/sig000008fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ef ), + .Q(\blk00000003/sig000008fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ee ), + .Q(\blk00000003/sig000008fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ed ), + .Q(\blk00000003/sig000008ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk000006a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ec ), + .Q(\blk00000003/sig00000900 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014eb ), + .Q(\blk00000003/sig00000901 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014ea ), + .Q(\blk00000003/sig00000902 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e9 ), + .Q(\blk00000003/sig00000903 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e8 ), + .Q(\blk00000003/sig00000904 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e7 ), + .Q(\blk00000003/sig00000905 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk0000069a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e6 ), + .Q(\blk00000003/sig00000906 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e5 ), + .Q(\blk00000003/sig00000907 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000698 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e4 ), + .Q(\blk00000003/sig00000908 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e3 ), + .Q(\blk00000003/sig00000909 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000696 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e2 ), + .Q(\blk00000003/sig0000090a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000693/sig000014e1 ), + .Q(\blk00000003/sig0000090b ) + ); + GND \blk00000003/blk00000693/blk00000694 ( + .G(\blk00000003/blk00000693/sig000014e0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000006cc/blk00000704 ( + .I0(ce), + .I1(\blk00000003/sig00000740 ), + .O(\blk00000003/blk000006cc/sig00001568 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000703 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fa ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001555 ), + .DPO(\blk00000003/blk000006cc/sig00001567 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000702 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fb ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001554 ), + .DPO(\blk00000003/blk000006cc/sig00001566 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000701 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fc ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001553 ), + .DPO(\blk00000003/blk000006cc/sig00001565 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk00000700 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fd ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001552 ), + .DPO(\blk00000003/blk000006cc/sig00001564 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006ff ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008fe ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001551 ), + .DPO(\blk00000003/blk000006cc/sig00001563 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fe ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig000008ff ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001550 ), + .DPO(\blk00000003/blk000006cc/sig00001562 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006fd ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000901 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154e ), + .DPO(\blk00000003/blk000006cc/sig00001560 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006fc ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000902 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154d ), + .DPO(\blk00000003/blk000006cc/sig0000155f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006fb ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000900 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154f ), + .DPO(\blk00000003/blk000006cc/sig00001561 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006fa ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000903 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154c ), + .DPO(\blk00000003/blk000006cc/sig0000155e ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f9 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000904 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154b ), + .DPO(\blk00000003/blk000006cc/sig0000155d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f8 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000905 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig0000154a ), + .DPO(\blk00000003/blk000006cc/sig0000155c ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk000006cc/blk000006f7 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000906 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001549 ), + .DPO(\blk00000003/blk000006cc/sig0000155b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f6 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000907 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001548 ), + .DPO(\blk00000003/blk000006cc/sig0000155a ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000006cc/blk000006f5 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000908 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001547 ), + .DPO(\blk00000003/blk000006cc/sig00001559 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000006cc/blk000006f4 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090a ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001545 ), + .DPO(\blk00000003/blk000006cc/sig00001557 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f3 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig0000090b ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001544 ), + .DPO(\blk00000003/blk000006cc/sig00001556 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000006cc/blk000006f2 ( + .A0(\blk00000003/sig00000739 ), + .A1(\blk00000003/sig0000073a ), + .A2(\blk00000003/blk000006cc/sig00001543 ), + .A3(\blk00000003/blk000006cc/sig00001543 ), + .A4(\blk00000003/blk000006cc/sig00001543 ), + .D(\blk00000003/sig00000909 ), + .DPRA0(\blk00000003/sig0000074c ), + .DPRA1(\blk00000003/sig0000074a ), + .DPRA2(\blk00000003/blk000006cc/sig00001543 ), + .DPRA3(\blk00000003/blk000006cc/sig00001543 ), + .DPRA4(\blk00000003/blk000006cc/sig00001543 ), + .WCLK(clk), + .WE(\blk00000003/blk000006cc/sig00001568 ), + .SPO(\blk00000003/blk000006cc/sig00001546 ), + .DPO(\blk00000003/blk000006cc/sig00001558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001567 ), + .Q(\blk00000003/sig000005a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001566 ), + .Q(\blk00000003/sig000005a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001565 ), + .Q(\blk00000003/sig000005a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001564 ), + .Q(\blk00000003/sig000005a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001563 ), + .Q(\blk00000003/sig000005a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001562 ), + .Q(\blk00000003/sig000005a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001561 ), + .Q(\blk00000003/sig000005a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001560 ), + .Q(\blk00000003/sig000005a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155f ), + .Q(\blk00000003/sig000005a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155e ), + .Q(\blk00000003/sig000005aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155d ), + .Q(\blk00000003/sig000005ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155c ), + .Q(\blk00000003/sig000005ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155b ), + .Q(\blk00000003/sig000005ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000155a ), + .Q(\blk00000003/sig000005ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001559 ), + .Q(\blk00000003/sig000005af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001558 ), + .Q(\blk00000003/sig000005b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001557 ), + .Q(\blk00000003/sig000005b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001556 ), + .Q(\blk00000003/sig000005b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001555 ), + .Q(\blk00000003/sig0000090c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001554 ), + .Q(\blk00000003/sig0000090d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001553 ), + .Q(\blk00000003/sig0000090e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001552 ), + .Q(\blk00000003/sig0000090f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001551 ), + .Q(\blk00000003/sig00000910 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001550 ), + .Q(\blk00000003/sig00000911 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154f ), + .Q(\blk00000003/sig00000912 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154e ), + .Q(\blk00000003/sig00000913 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154d ), + .Q(\blk00000003/sig00000914 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154c ), + .Q(\blk00000003/sig00000915 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154b ), + .Q(\blk00000003/sig00000916 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig0000154a ), + .Q(\blk00000003/sig00000917 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001549 ), + .Q(\blk00000003/sig00000918 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001548 ), + .Q(\blk00000003/sig00000919 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001547 ), + .Q(\blk00000003/sig0000091a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001546 ), + .Q(\blk00000003/sig0000091b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001545 ), + .Q(\blk00000003/sig0000091c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc/blk000006ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000006cc/sig00001544 ), + .Q(\blk00000003/sig0000091d ) + ); + GND \blk00000003/blk000006cc/blk000006cd ( + .G(\blk00000003/blk000006cc/sig00001543 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000705/blk0000072b ( + .I0(ce), + .I1(\blk00000003/sig00000741 ), + .O(\blk00000003/blk00000705/sig000015a7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000072a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000072a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk00000729 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000729_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000728 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090e ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000728_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000727 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000090f ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000727_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000726 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000910 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000726_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000725 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000911 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000725_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk00000724 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000913 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000724_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159f ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000723 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000914 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000723_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk00000722 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000912 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000722_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig000015a0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000721 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000915 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000721_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000720 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000916 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000720_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159c ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk00000705/blk0000071f ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000917 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159b ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071e ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000918 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig0000159a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071d ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig00000919 ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001599 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000705/blk0000071c ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091a ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001598 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk0000071b ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091c ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001596 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk00000705/blk0000071a ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091d ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk0000071a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001595 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000705/blk00000719 ( + .A0(\blk00000003/sig0000073b ), + .A1(\blk00000003/sig0000073c ), + .A2(\blk00000003/blk00000705/sig00001594 ), + .A3(\blk00000003/blk00000705/sig00001594 ), + .A4(\blk00000003/blk00000705/sig00001594 ), + .D(\blk00000003/sig0000091b ), + .DPRA0(\blk00000003/sig0000074d ), + .DPRA1(\blk00000003/sig0000074b ), + .DPRA2(\blk00000003/blk00000705/sig00001594 ), + .DPRA3(\blk00000003/blk00000705/sig00001594 ), + .DPRA4(\blk00000003/blk00000705/sig00001594 ), + .WCLK(clk), + .WE(\blk00000003/blk00000705/sig000015a7 ), + .SPO(\NLW_blk00000003/blk00000705/blk00000719_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000705/sig00001597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000718 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a6 ), + .Q(\blk00000003/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000717 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a5 ), + .Q(\blk00000003/sig000003aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000716 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a4 ), + .Q(\blk00000003/sig000003ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000715 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a3 ), + .Q(\blk00000003/sig000003ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000714 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a2 ), + .Q(\blk00000003/sig000003ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000713 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a1 ), + .Q(\blk00000003/sig000003ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000712 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig000015a0 ), + .Q(\blk00000003/sig000003af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000711 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159f ), + .Q(\blk00000003/sig000003b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000710 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159e ), + .Q(\blk00000003/sig000003b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159d ), + .Q(\blk00000003/sig000003b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159c ), + .Q(\blk00000003/sig000003b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159b ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig0000159a ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001599 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk0000070a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001598 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000709 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001597 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000708 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001596 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705/blk00000707 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000705/sig00001595 ), + .Q(\blk00000003/sig000003ba ) + ); + GND \blk00000003/blk00000705/blk00000706 ( + .G(\blk00000003/blk00000705/sig00001594 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000075c/blk00000782 ( + .I0(ce), + .I1(\blk00000003/sig00000235 ), + .O(\blk00000003/blk0000075c/sig000015e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000075c/blk00000781 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000781_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000780 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000780_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077f ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b4 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077e ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b5 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077d ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b6 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015df ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077c ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b7 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015de ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077b ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b9 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk0000077a ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008ba ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk0000077a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015db ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000779 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008b8 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000779_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000778 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bb ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000778_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015da ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000777 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bc ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000777_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000776 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bd ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000776_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000775 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008be ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000775_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000774 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008bf ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000774_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000773 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c0 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000773_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000772 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c2 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000772_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000771 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c3 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000771_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000075c/blk00000770 ( + .A0(\blk00000003/sig0000023c ), + .A1(\blk00000003/blk0000075c/sig000015d1 ), + .A2(\blk00000003/blk0000075c/sig000015d1 ), + .A3(\blk00000003/blk0000075c/sig000015d1 ), + .A4(\blk00000003/blk0000075c/sig000015d1 ), + .D(\blk00000003/sig000008c1 ), + .DPRA0(\blk00000003/sig0000091f ), + .DPRA1(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA2(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA3(\blk00000003/blk0000075c/sig000015d1 ), + .DPRA4(\blk00000003/blk0000075c/sig000015d1 ), + .WCLK(clk), + .WE(\blk00000003/blk0000075c/sig000015e4 ), + .SPO(\NLW_blk00000003/blk0000075c/blk00000770_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000075c/sig000015d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e3 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e2 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e1 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015e0 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015df ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000076a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015de ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dd ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000768 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015dc ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015db ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000766 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015da ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d9 ), + .Q(\blk00000003/sig00000104 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000764 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d8 ), + .Q(\blk00000003/sig00000105 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d7 ), + .Q(\blk00000003/sig00000106 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000762 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d6 ), + .Q(\blk00000003/sig00000107 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d5 ), + .Q(\blk00000003/sig00000108 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk00000760 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d4 ), + .Q(\blk00000003/sig00000109 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d3 ), + .Q(\blk00000003/sig0000010a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075c/blk0000075e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000075c/sig000015d2 ), + .Q(\blk00000003/sig0000010b ) + ); + GND \blk00000003/blk0000075c/blk0000075d ( + .G(\blk00000003/blk0000075c/sig000015d1 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.veo b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.veo new file mode 100644 index 000000000..eb615e1ee --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec1 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec1.v when simulating +// the core, hbdec1. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xco b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xco new file mode 100644 index 000000000..efcc206f5 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Dec 4 21:34:29 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc7k325t +SET devicefamily = kintex7 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ffg900 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=200.0 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=7 +CSET component_name=hbdec1 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=200 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 8b63d7c7 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_0.mif new file mode 100644 index 000000000..f19636daf --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_0.mif @@ -0,0 +1,5 @@ +111111111111000010 +000000000011000010 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_1.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_1.mif new file mode 100644 index 000000000..07e316dd3 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_1.mif @@ -0,0 +1,5 @@ +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_2.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_2.mif new file mode 100644 index 000000000..da84300d6 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_2.mif @@ -0,0 +1,5 @@ +111111101000011111 +000000100110101110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_3.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_3.mif new file mode 100644 index 000000000..ea92ca6c2 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_3.mif @@ -0,0 +1,5 @@ +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_4.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_4.mif new file mode 100644 index 000000000..9e9303211 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_4.mif @@ -0,0 +1,5 @@ +111101110000011101 +000011100100101000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_5.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_5.mif new file mode 100644 index 000000000..e0c3f05fe --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto0_5.mif @@ -0,0 +1,5 @@ +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1_flist.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_flist.txt new file mode 100644 index 000000000..2bd535f92 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_flist.txt @@ -0,0 +1,22 @@ +# Output products list for +hbdec1.asy +hbdec1.gise +hbdec1.mif +hbdec1.ngc +hbdec1.v +hbdec1.veo +hbdec1.xco +hbdec1.xise +hbdec1COEFF_auto0_0.mif +hbdec1COEFF_auto0_1.mif +hbdec1COEFF_auto0_2.mif +hbdec1COEFF_auto0_3.mif +hbdec1COEFF_auto0_4.mif +hbdec1COEFF_auto0_5.mif +hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +hbdec1_flist.txt +hbdec1_readme.txt +hbdec1_reload_addrfilt_decode_rom.mif +hbdec1_reload_order.txt +hbdec1_xmdf.tcl +hbdec1filt_decode_rom.mif diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1_readme.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_readme.txt new file mode 100644 index 000000000..3ca791f11 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_readme.txt @@ -0,0 +1,67 @@ +The following files were generated for 'hbdec1' in directory +/home/matt/fpgadev/usrp3/top/x300/coregen_dsp/ + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec1.mif + * hbdec1_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec1.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec1.ngc + * hbdec1.v + * hbdec1.veo + * hbdec1COEFF_auto0_0.mif + * hbdec1COEFF_auto0_1.mif + * hbdec1COEFF_auto0_2.mif + * hbdec1COEFF_auto0_3.mif + * hbdec1COEFF_auto0_4.mif + * hbdec1COEFF_auto0_5.mif + * hbdec1COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec1_reload_addrfilt_decode_rom.mif + * hbdec1filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec1.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec1.asy + * hbdec1.mif + * hbdec1_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec1_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec1.gise + * hbdec1.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec1_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec1_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_order.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_order.txt new file mode 100644 index 000000000..11f12084f --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 20 +Reload index 1 = Index 22 +Reload index 2 = Index 16 +Reload index 3 = Index 18 +Reload index 4 = Index 12 +Reload index 5 = Index 14 +Reload index 6 = Index 8 +Reload index 7 = Index 10 +Reload index 8 = Index 4 +Reload index 9 = Index 6 +Reload index 10 = Index 0 +Reload index 11 = Index 2 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1_xmdf.tcl b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_xmdf.tcl new file mode 100644 index 000000000..7aa8f91c3 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1_xmdf.tcl @@ -0,0 +1,111 @@ +# The package naming convention is _xmdf +package provide hbdec1_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec1_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec1_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec1 +} +# ::hbdec1_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec1_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_3.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_4.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto0_5.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec1filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec1 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec1filt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec1filt_decode_rom.mif new file mode 100644 index 000000000..32d689cd7 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec1filt_decode_rom.mif @@ -0,0 +1,17 @@ +00 +10 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.asy b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.asy new file mode 100644 index 000000000..e9bd5ec37 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec2 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[46:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[46:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.mif new file mode 100644 index 000000000..78d2dd901 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.mif @@ -0,0 +1,47 @@ +111111111111000010 +000000000000000000 +000000000011000010 +000000000000000000 +111111111001001000 +000000000000000000 +000000001101010111 +000000000000000000 +111111101000011111 +000000000000000000 +000000100110101110 +000000000000000000 +111111000011000100 +000000000000000000 +000001011101100110 +000000000000000000 +111101110000011101 +000000000000000000 +000011100100101000 +000000000000000000 +111001100001011000 +000000000000000000 +010100010001000001 +011111111111111111 +010100010001000001 +000000000000000000 +111001100001011000 +000000000000000000 +000011100100101000 +000000000000000000 +111101110000011101 +000000000000000000 +000001011101100110 +000000000000000000 +111111000011000100 +000000000000000000 +000000100110101110 +000000000000000000 +111111101000011111 +000000000000000000 +000000001101010111 +000000000000000000 +111111111001001000 +000000000000000000 +000000000011000010 +000000000000000000 +111111111111000010 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ngc b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ngc new file mode 100644 index 000000000..e01cbfd43 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$3155~753-Xnzd}foo8#5+421).97 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17a2;2;7c:>e;d8?j41n3:1(9?i:3:3?k26m3;;76a=6d83>!26n383<6`;1d825>=h:?i1<7*;1g81<5=i<8o1=?54o34a>5<#<8l1>5>4n53f>45<3f8=m7>5$53e>7>73g>:i7?;;:m12<<72->:j7<70:l75`<6=21d>;650;&75c<5091e8e;3;?>i5><0;6):>f;0;4>h39l0:565`27694?"39o094=5a40g95d=d:9l60`=83.?=k4=819m04c=9l10c?;k:18'04`=:1:0b9?j:0d8?j42k3:1(9?i:3:3?k26m38;76a=5c83>!26n383<6`;1d815>=h:?54o37:>5<#<8l1>5>4n53f>75<3f8>47>5$53e>7>73g>:i7<;;:m112<72->:j7<70:l75`<5=21d>5950;&75c<5091e81290/8e;0;?>i50=0;6):>f;0;4>h39l09565`29194?"39o094=5a40g96d=50z&77d<5i?1C8974H51g?j4f=3:17pl;8983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3000;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;8d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd30o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3180;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3100;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31k0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9b83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31m0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;9d83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd31o0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a983>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3i00;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;a`83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3ik0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ab83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3im0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;ad83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3io0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b183>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j80;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b383>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j:0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b583>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j<0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b783>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd3j>0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl;b983>c<729q/8>o54378L12>3A>8h6*=ae87?l?32900e4;50;9j=3<722c2;7>5;h;;>5<5<5<5<?6=44i566>5<5<i57>5f;294~"3;h0?>85G45;8L15c3-8jh7:4i8694?=n1<0;66g66;29?l?02900e4650;9j5d2=831b>5k50;9j6=`=831b>4>50;9j6<7=831b>4<50;9j012=831b89;50;9l061=831d>5j50;9~f1df290m6=4?{%60e?25=2B?845G42f8 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17a28o37c:>e;33?>i6ml0;6):>f;3f<>h39l0:=65`1df94?"39o0:i55a40g957=5:9l5`2=83.?=k4>e99m04c=9?10c50z&77d<5i?1C8974H51g?j4f=3:17pl83g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0<10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84c83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84e83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl84g83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0==0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd0=?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl85683><<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<954?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<9n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0=m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`41`<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:=4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>80;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`427<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:94?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0><0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`423<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:54?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>00;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42d<7200;6=u+42c906><@=>27E:<<729q/8>o542:8L12>3A>8h6*=ae80?l?32900e4;50;9j=3<722c2;7>5;h3;a?6=3`;2j7>5;h3b0?6=3f>9>7>5;n617?6=3th<:n4?:883>5}#<:k18>64H56:?M24l2.9mi4<;h;7>5<>o>?3:17d?7e;29?l7>n3:17d?n4;29?j25:3:17b:=3;29?xd0>m0;644?:1y'06g=<:20D9:6;I60`>"5im087d7;:188m<3=831b5;4?::k:3?6=3`;3i7>5;h3:b?6=3`;j87>5;n616?6=3f>9?7>5;|`42`<7200;6=u+42c906><@=>27E:6<729q/8>o52c`8L12>3A>8h6*=ae8;b>o5i10;66g=a883>>i4?>0;66s|200:>5<61rTm5638568:1>;0=1029638588:1>;0=h0296385c8:1>;0=j0296385e8:1>;0=l0296385g8:1>;0>9029638608:1>;0>;029638628:1>;0>=029638648:1>;0>?029638668:1>;0>1029638688:1>;0>h0296386c8:1>;0>j0296386e8:1>;0>l0296s|200b>5<61rTm;638568:0>;0=1028638588:0>;0=h0286385c8:0>;0=j0286385e8:0>;0=l0286385g8:0>;0>9028638608:0>;0>;028638628:0>;0>=028638648:0>;0>?028638668:0>;0>1028638688:0>;0>h0286386c8:0>;0>j0286386e8:0>;0>l0286s|200a>5<5sW;o<6386b82e1=z{;;9o7>52z\2g`=:??o1=l:4}r026a<72;qU=nj4=64g>4g33ty9=?k50;0xZ4ed34==57?n4:p644a2909wS?la:?42g<6i=1v??<0;296~X6k016;;o51`68yv46;80;6?uQ1b:8920128k?7p}=12094?4|V8i<70998;3b0>{t:8986=4={_3`2>;0>>0:m95rs3300?6=:rT:o85277195d2<>6<=8:181[7d:27<:=4>a59~w77403:1>vP>c09>334=9h>0q~<>3883>7}Y9m201:8>:0c7?xu59:k1<75<5sW;o:6385g82e1=z{;;8o7>52z\2`0=:?4g33ty9=>k50;0xZ4b434=>o7?n4:p645a2909wS?k2:?41g<6i=1v??;0;296~X6l816;8951`68yv46<80;6?uQ1b`8923>28k?7p}=15094?4|V8i;709:8;3b0>{t:8>86=4={_671>;0>o09m45rs3370?6=9hqU=5k4=61e>4>b34=?<7?7e:?404<60l16;9<519g89224282n709;4;3;a>;0<<0:4h5275495=c<5>><6<6j;<578d9>31g=91o01::m:0:f?813k3;3i6384e82<`=:?=o1=5k4=66e>4>b34=><7?7e:?414<60l16;8<519g89234282n709:4;3;a>;0=<0:4h5274495=c<5>515g8922628>n709;2;37a>;0<:0:8h52756951c<5>>>6<:j;<57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15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0=l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0<31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e06g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0??1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0?l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0><1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>21<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>31<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0>l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0181<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0191<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0121<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0131<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e01l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0081<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0091<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0021<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0031<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00k1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00h1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00i1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00n1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00o1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e00l1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h:1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h;1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h81<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h91<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h>1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h?1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h<1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h=1<7;50;2x 15f2;k;7E:;9:J77a=#:hn1>6g>4d83>>o60l0;66g>a583>>o3:=0;66a;2383>>{e0h21<7:?:34904}O<:n0(9=n:0466>\6w8;51e862?472;;1qdhi:18'04`=nl1e8:j7hj;o62a?7<3`li6=4+40d9b`=i<8o1>65f1g`94?"39o0:jl5a40g94>=n9o31<7*;1g82bd=i<8o1=65f1g:94?"39o0:jl5a40g96>=n9o=1<7*;1g82bd=i<8o1?65f1g494?"39o0:jl5a40g90>=n9o?1<7*;1g82bd=i<8o1965f1g694?"39o0:jl5a40g92>=n9o91<7*;1g82bd=i<8o1;65f23194?"39o0:jl5a40g9<>=n:;81<7*;1g82bd=i<8o1565f23394?"39o0:jl5a40g9e>=n:;:1<7*;1g82bd=i<8o1n65f20d94?"39o0:jl5a40g9g>=n:8o1<7*;1g82bd=i<8o1h65f20694?"39o0:jl5a40g9a>=n:931<7*;1g82bd=i<8o1j65f1gg94?"39o0:jl5a40g955=;;o62a?6<3`;;?7>5$53e>4633g>:i7?4;h335?6=,=;m6<>;;o62a?4<3`>?:7>5;h3;a?6=3`>8=7>5;h3:b?6=3f89h7>5$53e>74d3g>:i7>4;n01f?6=,=;m6?5$53e>74d3g>:i7<4;n01=?6=,=;m6?5$53e>74d3g>:i7:4;n013?6=,=;m6?5$53e>74d3g>:i784;n011?6=,=;m6?97>5$53e>74d3g>:i764;n060?6=,=;m6??7>5$53e>74d3g>:i7o4;n066?6=,=;m6?=7>5$53e>74d3g>:i7m4;n064?6=,=;m6?5$53e>74d3g>:i7k4;n00f?6=,=;m6?5$53e>74d3g>:i7??;:m161<72->:j7<=c:l75`<6921d>8h50;&75c<5=l1e88m50;&75c<5=l1e88o50;&75c<5=l1e88650;&75c<5=l1e85950;&75c<5=l1e85;50;&75c<5=l1e85=50;&75c<5=l1e8:650;&75c<5=l1e8;<50;&75c<5=l1e8"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ac83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?ij0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ae83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?il0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7ag83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j90;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b083>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j;0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b283>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j=0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b483>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j?0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b683>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?j10;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7b883>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jh0;694?:1y'06g=:0o0D9:6;I60`>"5im097d?;e;29?l7?m3:17d?n4;29?j25:3:17pl7bc83>1<729q/8>o528g8L12>3A>8h6*=ae81?l73m3:17d?7e;29?l7f<3:17b:=2;29?xd?jj0;6k4?:1y'06g=<;?0D9:6;I60`>"5im0=7d7;:188m<3=831b5;4?::k:3?6=3`336=44i0c7>5<5<5<5<>6=44o514>5<1<75f9483>>o>>3:17d78:188m<>=831b=l:50;9j6=c=831b>5h50;9j6<6=831b>4?50;9j6<4=831b89:50;9j013=831d8>950;9l6=b=831vn5lj:18e>5<7s->8m7:=5:J70<=O<:n0(?ok:59j=1<722c297>5;h;5>5<>o6i=0;66g=8d83>>o50o0;66g=9183>>o5180;66g=9383>>o3<=0;66g;4483>>i3;>0;66a=8e83>>{e0kl1<7h50;2x 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7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc37>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg71290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno?n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg7e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc3`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk;o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg7b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno?i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno<=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc07>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg41290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno<8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg4e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc0`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk8o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg4b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno==:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc17>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg51290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno=n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg5e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc1`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk9o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg5b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno=i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<;6=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc62>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc67>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg21290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<36=4;:183!24i382i6F;489K06b<,;ko6?5f15g94?=n91o1<75f1`694?=h<;81<75rbc6:>5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno:n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg2e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc6`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk>o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg2b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno:i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc77>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg31290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;8:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno;n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg3e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc7`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk?o6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg3b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno;i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0429026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc47>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk<>6=46:183!24i3>846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg01290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno88:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno8n:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg0e29026=4?{%60e?2402B?845G42f8 7gc2:1b594?::k:1?6=3`3=6=44i8594?=n91o1<75f18d94?=n9h>1<75`43094?=h<;91<75rbc4`>5<3290;w):N3<01C8>j4$3cg>7=n9=o1<75f19g94?=n9h>1<75`43094?=zjk846F;489K06b<,;ko6>5f9583>>o>=3:17d79:188m<1=831b=5k50;9j5<`=831b=l:50;9l074=831d8?=50;9~fg0b290?6=4?{%60e?4>m2B?845G42f8 7gc2;1b=9k50;9j5=c=831b=l:50;9l074=831vno8i:18:>5<7s->8m7:<8:J70<=O<:n0(?ok:29j=1<722c297>5;h;5>5<5<>290;w):N3<01C8>j4$3cg>6=n1=0;66g65;29?l?12900e4950;9j5=c=831b=4h50;9j5d2=831d8?<50;9l075=831vno9=:187>5<7s->8m7<6e:J70<=O<:n0(?ok:39j51c=831b=5k50;9j5d2=831d8?<50;9~fg1429026=4?{%60e?2402B?845G42f8 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.v b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.v new file mode 100644 index 000000000..e5423434c --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.v @@ -0,0 +1,24109 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec2.v +// /___/ /\ Timestamp: Wed Dec 4 13:33:47 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec2.ngc ./tmp/_cg/hbdec2.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec2.ngc +// Output file : ./tmp/_cg/hbdec2.v +// # of Modules : 1 +// Design Name : hbdec2 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec2 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [46 : 0] dout_1; + output [46 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000767 ; + wire \blk00000003/sig00000766 ; + wire \blk00000003/sig00000765 ; + wire \blk00000003/sig00000764 ; + wire \blk00000003/sig00000763 ; + wire \blk00000003/sig00000762 ; + wire \blk00000003/sig00000761 ; + wire \blk00000003/sig00000760 ; + wire \blk00000003/sig0000075f ; + wire \blk00000003/sig0000075e ; + wire \blk00000003/sig0000075d ; + wire \blk00000003/sig0000075c ; + wire \blk00000003/sig0000075b ; + wire \blk00000003/sig0000075a ; + wire \blk00000003/sig00000759 ; + wire \blk00000003/sig00000758 ; + wire \blk00000003/sig00000757 ; + wire \blk00000003/sig00000756 ; + wire \blk00000003/sig00000755 ; + wire \blk00000003/sig00000754 ; + wire \blk00000003/sig00000753 ; + wire \blk00000003/sig00000752 ; + wire \blk00000003/sig00000751 ; + wire \blk00000003/sig00000750 ; + wire \blk00000003/sig0000074f ; + wire \blk00000003/sig0000074e ; + wire \blk00000003/sig0000074d ; + wire \blk00000003/sig0000074c ; + wire \blk00000003/sig0000074b ; + wire \blk00000003/sig0000074a ; + wire \blk00000003/sig00000749 ; + wire \blk00000003/sig00000748 ; + wire \blk00000003/sig00000747 ; + wire \blk00000003/sig00000746 ; + wire \blk00000003/sig00000745 ; + wire \blk00000003/sig00000744 ; + wire \blk00000003/sig00000743 ; + wire \blk00000003/sig00000742 ; + wire \blk00000003/sig00000741 ; + wire \blk00000003/sig00000740 ; + wire \blk00000003/sig0000073f ; + wire \blk00000003/sig0000073e ; + wire \blk00000003/sig0000073d ; + wire \blk00000003/sig0000073c ; + wire \blk00000003/sig0000073b ; + wire \blk00000003/sig0000073a ; + wire \blk00000003/sig00000739 ; + wire \blk00000003/sig00000738 ; + wire \blk00000003/sig00000737 ; + wire \blk00000003/sig00000736 ; + wire \blk00000003/sig00000735 ; + wire \blk00000003/sig00000734 ; + wire \blk00000003/sig00000733 ; + wire \blk00000003/sig00000732 ; + wire \blk00000003/sig00000731 ; + wire \blk00000003/sig00000730 ; + wire \blk00000003/sig0000072f ; + wire \blk00000003/sig0000072e ; + wire \blk00000003/sig0000072d ; + wire \blk00000003/sig0000072c ; + wire \blk00000003/sig0000072b ; + wire \blk00000003/sig0000072a ; + wire \blk00000003/sig00000729 ; + wire \blk00000003/sig00000728 ; + wire \blk00000003/sig00000727 ; + wire \blk00000003/sig00000726 ; + wire \blk00000003/sig00000725 ; + wire \blk00000003/sig00000724 ; + wire \blk00000003/sig00000723 ; + wire \blk00000003/sig00000722 ; + wire \blk00000003/sig00000721 ; + wire \blk00000003/sig00000720 ; + wire \blk00000003/sig0000071f ; + wire \blk00000003/sig0000071e ; + wire \blk00000003/sig0000071d ; + wire \blk00000003/sig0000071c ; + wire \blk00000003/sig0000071b ; + wire \blk00000003/sig0000071a ; + wire \blk00000003/sig00000719 ; + wire \blk00000003/sig00000718 ; + wire \blk00000003/sig00000717 ; + wire \blk00000003/sig00000716 ; + wire \blk00000003/sig00000715 ; + wire \blk00000003/sig00000714 ; + wire \blk00000003/sig00000713 ; + wire \blk00000003/sig00000712 ; + wire \blk00000003/sig00000711 ; + wire \blk00000003/sig00000710 ; + wire \blk00000003/sig0000070f ; + wire \blk00000003/sig0000070e ; + wire \blk00000003/sig0000070d ; + wire \blk00000003/sig0000070c ; + wire \blk00000003/sig0000070b ; + wire \blk00000003/sig0000070a ; + wire \blk00000003/sig00000709 ; + wire \blk00000003/sig00000708 ; + wire \blk00000003/sig00000707 ; + wire \blk00000003/sig00000706 ; + wire \blk00000003/sig00000705 ; + wire \blk00000003/sig00000704 ; + wire \blk00000003/sig00000703 ; + wire \blk00000003/sig00000702 ; + wire \blk00000003/sig00000701 ; + wire \blk00000003/sig00000700 ; + wire \blk00000003/sig000006ff ; + wire \blk00000003/sig000006fe ; + wire \blk00000003/sig000006fd ; + wire \blk00000003/sig000006fc ; + wire \blk00000003/sig000006fb ; + wire \blk00000003/sig000006fa ; + wire \blk00000003/sig000006f9 ; + wire \blk00000003/sig000006f8 ; + wire \blk00000003/sig000006f7 ; + wire \blk00000003/sig000006f6 ; + wire \blk00000003/sig000006f5 ; + wire \blk00000003/sig000006f4 ; + wire \blk00000003/sig000006f3 ; + wire \blk00000003/sig000006f2 ; + wire \blk00000003/sig000006f1 ; + wire \blk00000003/sig000006f0 ; + wire \blk00000003/sig000006ef ; + wire \blk00000003/sig000006ee ; + wire \blk00000003/sig000006ed ; + wire \blk00000003/sig000006ec ; + wire \blk00000003/sig000006eb ; + wire \blk00000003/sig000006ea ; + wire \blk00000003/sig000006e9 ; + wire \blk00000003/sig000006e8 ; + wire \blk00000003/sig000006e7 ; + wire \blk00000003/sig000006e6 ; + wire \blk00000003/sig000006e5 ; + wire \blk00000003/sig000006e4 ; + wire \blk00000003/sig000006e3 ; + wire \blk00000003/sig000006e2 ; + wire \blk00000003/sig000006e1 ; + wire \blk00000003/sig000006e0 ; + wire \blk00000003/sig000006df ; + wire \blk00000003/sig000006de ; + wire \blk00000003/sig000006dd ; + wire \blk00000003/sig000006dc ; + wire \blk00000003/sig000006db ; + wire \blk00000003/sig000006da ; + wire \blk00000003/sig000006d9 ; + wire \blk00000003/sig000006d8 ; + wire \blk00000003/sig000006d7 ; + wire \blk00000003/sig000006d6 ; + wire \blk00000003/sig000006d5 ; + wire \blk00000003/sig000006d4 ; + wire \blk00000003/sig000006d3 ; + wire \blk00000003/sig000006d2 ; + wire \blk00000003/sig000006d1 ; + wire \blk00000003/sig000006d0 ; + wire \blk00000003/sig000006cf ; + wire \blk00000003/sig000006ce ; + wire \blk00000003/sig000006cd ; + wire \blk00000003/sig000006cc ; + wire \blk00000003/sig000006cb ; + wire \blk00000003/sig000006ca ; + wire \blk00000003/sig000006c9 ; + wire \blk00000003/sig000006c8 ; + wire \blk00000003/sig000006c7 ; + wire \blk00000003/sig000006c6 ; + wire \blk00000003/sig000006c5 ; + wire \blk00000003/sig000006c4 ; + wire \blk00000003/sig000006c3 ; + wire \blk00000003/sig000006c2 ; + wire \blk00000003/sig000006c1 ; + wire \blk00000003/sig000006c0 ; + wire \blk00000003/sig000006bf ; + wire \blk00000003/sig000006be ; + wire \blk00000003/sig000006bd ; + wire \blk00000003/sig000006bc ; + wire \blk00000003/sig000006bb ; + wire \blk00000003/sig000006ba ; + wire \blk00000003/sig000006b9 ; + wire \blk00000003/sig000006b8 ; + wire \blk00000003/sig000006b7 ; + wire \blk00000003/sig000006b6 ; + wire \blk00000003/sig000006b5 ; + wire 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\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000698_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000696_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000694_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000692_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000690_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000688_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000686_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000684_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000682_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000680_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000678_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000676_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000674_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000672_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000670_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000668_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000666_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000664_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000662_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000660_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000004d0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ee_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ea_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000db_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000da_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c0_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000098_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000091_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000001a_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000016_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000012_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000c_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000b_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [46 : 0] NlwRenamedSig_OI_dout_1; + wire [46 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000783 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/sig00000679 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000782 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f6 ), + .Q(\blk00000003/sig00000767 ), + .Q15(\NLW_blk00000003/blk00000782_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000781 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000766 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000780 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004f5 ), + .Q(\blk00000003/sig00000766 ), + .Q15(\NLW_blk00000003/blk00000780_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072f ), + .Q(\blk00000003/sig00000765 ), + .Q15(\NLW_blk00000003/blk0000077e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000764 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000733 ), + .Q(\blk00000003/sig00000764 ), + .Q15(\NLW_blk00000003/blk0000077c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000077b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000077a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000731 ), + .Q(\blk00000003/sig00000763 ), + .Q15(\NLW_blk00000003/blk0000077a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000779 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000762 ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000778 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072d ), + .Q(\blk00000003/sig00000762 ), + .Q15(\NLW_blk00000003/blk00000778_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000777 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000776 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/sig00000761 ), + .Q15(\NLW_blk00000003/blk00000776_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000775 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000760 ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000774 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000729 ), + .Q(\blk00000003/sig00000760 ), + .Q15(\NLW_blk00000003/blk00000774_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000773 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000772 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000072b ), + .Q(\blk00000003/sig0000075f ), + .Q15(\NLW_blk00000003/blk00000772_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000771 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075e ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000770 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000727 ), + .Q(\blk00000003/sig0000075e ), + .Q15(\NLW_blk00000003/blk00000770_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071f ), + .Q(\blk00000003/sig0000075d ), + .Q15(\NLW_blk00000003/blk0000076e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075c ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000721 ), + .Q(\blk00000003/sig0000075c ), + .Q15(\NLW_blk00000003/blk0000076c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000076b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000076a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\blk00000003/sig0000075b ), + .Q15(\NLW_blk00000003/blk0000076a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000769 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000075a ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000768 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/sig0000075a ), + .Q15(\NLW_blk00000003/blk00000768_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000767 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000766 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071b ), + .Q(\blk00000003/sig00000759 ), + .Q15(\NLW_blk00000003/blk00000766_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000765 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000758 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000764 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000717 ), + .Q(\blk00000003/sig00000758 ), + .Q15(\NLW_blk00000003/blk00000764_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000763 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000762 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000071d ), + .Q(\blk00000003/sig00000757 ), + .Q15(\NLW_blk00000003/blk00000762_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000761 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000756 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000760 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070f ), + .Q(\blk00000003/sig00000756 ), + .Q15(\NLW_blk00000003/blk00000760_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000713 ), + .Q(\blk00000003/sig00000755 ), + .Q15(\NLW_blk00000003/blk0000075e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000754 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000715 ), + .Q(\blk00000003/sig00000754 ), + .Q15(\NLW_blk00000003/blk0000075c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000075b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000075a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000711 ), + .Q(\blk00000003/sig00000753 ), + .Q15(\NLW_blk00000003/blk0000075a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000759 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000752 ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000758 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000709 ), + .Q(\blk00000003/sig00000752 ), + .Q15(\NLW_blk00000003/blk00000758_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000757 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000756 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070b ), + .Q(\blk00000003/sig00000751 ), + .Q15(\NLW_blk00000003/blk00000756_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000755 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000750 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000754 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000703 ), + .Q(\blk00000003/sig00000750 ), + .Q15(\NLW_blk00000003/blk00000754_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000753 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000752 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000070d ), + .Q(\blk00000003/sig0000074f ), + .Q15(\NLW_blk00000003/blk00000752_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000751 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074e ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000750 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000705 ), + .Q(\blk00000003/sig0000074e ), + .Q15(\NLW_blk00000003/blk00000750_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000701 ), + .Q(\blk00000003/sig0000074d ), + .Q15(\NLW_blk00000003/blk0000074e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074c ), + .Q(\blk00000003/sig000001ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000707 ), + .Q(\blk00000003/sig0000074c ), + .Q15(\NLW_blk00000003/blk0000074c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000074b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000074a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f9 ), + .Q(\blk00000003/sig0000074b ), + .Q15(\NLW_blk00000003/blk0000074a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000749 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000074a ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000748 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fd ), + .Q(\blk00000003/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000748_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000747 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000749 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000746 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ff ), + .Q(\blk00000003/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000746_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000745 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000748 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000744 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006fb ), + .Q(\blk00000003/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000744_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000743 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000747 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000742 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f3 ), + .Q(\blk00000003/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000742_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000741 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000746 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000740 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f5 ), + .Q(\blk00000003/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000740_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000745 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ed ), + .Q(\blk00000003/sig00000745 ), + .Q15(\NLW_blk00000003/blk0000073e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000744 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f7 ), + .Q(\blk00000003/sig00000744 ), + .Q15(\NLW_blk00000003/blk0000073c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000073b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000743 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000073a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006ef ), + .Q(\blk00000003/sig00000743 ), + .Q15(\NLW_blk00000003/blk0000073a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000739 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000742 ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006eb ), + .Q(\blk00000003/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000738_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000737 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000741 ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000736 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006f1 ), + .Q(\blk00000003/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000736_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000735 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000740 ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000734 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e3 ), + .Q(\blk00000003/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000734_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000733 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073f ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000732 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e7 ), + .Q(\blk00000003/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000732_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000731 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073e ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000730 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000730_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073d ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/sig0000073d ), + .Q15(\NLW_blk00000003/blk0000072e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073c ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006e1 ), + .Q(\blk00000003/sig0000073c ), + .Q15(\NLW_blk00000003/blk0000072c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000072b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073b ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000072a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d9 ), + .Q(\blk00000003/sig0000073b ), + .Q15(\NLW_blk00000003/blk0000072a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000729 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000073a ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000728 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006dd ), + .Q(\blk00000003/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000728_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000727 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000739 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000726 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006df ), + .Q(\blk00000003/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000726_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000725 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000738 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000724 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d7 ), + .Q(\blk00000003/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000724_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000723 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000737 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000722 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006d5 ), + .Q(\blk00000003/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000722_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000721 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000736 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000720 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000006db ), + .Q(\blk00000003/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000720_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000735 ), + .Q(\blk00000003/sig000004f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001df ), + .Q(\blk00000003/sig00000735 ), + .Q15(\NLW_blk00000003/blk0000071e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000734 ), + .Q(\blk00000003/sig0000067a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c3 ), + .Q(\blk00000003/sig00000734 ), + .Q15(\NLW_blk00000003/blk0000071c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000071b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000732 ), + .Q(\blk00000003/sig00000733 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000071a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000732 ), + .Q15(\NLW_blk00000003/blk0000071a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000719 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000730 ), + .Q(\blk00000003/sig00000731 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000718 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000730 ), + .Q15(\NLW_blk00000003/blk00000718_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000717 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072e ), + .Q(\blk00000003/sig0000072f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000716 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000072e ), + .Q15(\NLW_blk00000003/blk00000716_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000715 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072c ), + .Q(\blk00000003/sig0000072d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000714 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig0000072c ), + .Q15(\NLW_blk00000003/blk00000714_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000713 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000072a ), + .Q(\blk00000003/sig0000072b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000712 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig0000072a ), + .Q15(\NLW_blk00000003/blk00000712_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000711 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000728 ), + .Q(\blk00000003/sig00000729 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000710 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000728 ), + .Q15(\NLW_blk00000003/blk00000710_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000726 ), + .Q(\blk00000003/sig00000727 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig00000726 ), + .Q15(\NLW_blk00000003/blk0000070e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070d ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000724 ), + .Q(\blk00000003/sig00000725 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig00000724 ), + .Q15(\NLW_blk00000003/blk0000070c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070b ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000722 ), + .Q(\blk00000003/sig00000723 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig00000722 ), + .Q15(\NLW_blk00000003/blk0000070a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000709 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000720 ), + .Q(\blk00000003/sig00000721 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000708 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000720 ), + .Q15(\NLW_blk00000003/blk00000708_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000707 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071e ), + .Q(\blk00000003/sig0000071f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000706 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig0000071e ), + .Q15(\NLW_blk00000003/blk00000706_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071c ), + .Q(\blk00000003/sig0000071d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000704 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig0000071c ), + .Q15(\NLW_blk00000003/blk00000704_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000703 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000071a ), + .Q(\blk00000003/sig0000071b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000702 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000071a ), + .Q15(\NLW_blk00000003/blk00000702_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000701 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/sig00000719 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000700 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000718 ), + .Q15(\NLW_blk00000003/blk00000700_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ff ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000716 ), + .Q(\blk00000003/sig00000717 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fe ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000716 ), + .Q15(\NLW_blk00000003/blk000006fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000714 ), + .Q(\blk00000003/sig00000715 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig00000714 ), + .Q15(\NLW_blk00000003/blk000006fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000712 ), + .Q(\blk00000003/sig00000713 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006fa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig00000712 ), + .Q15(\NLW_blk00000003/blk000006fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000710 ), + .Q(\blk00000003/sig00000711 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000710 ), + .Q15(\NLW_blk00000003/blk000006f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070e ), + .Q(\blk00000003/sig0000070f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig0000070e ), + .Q15(\NLW_blk00000003/blk000006f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070c ), + .Q(\blk00000003/sig0000070d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig0000070c ), + .Q15(\NLW_blk00000003/blk000006f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig0000070a ), + .Q(\blk00000003/sig0000070b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig0000070a ), + .Q15(\NLW_blk00000003/blk000006f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000708 ), + .Q(\blk00000003/sig00000709 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000708 ), + .Q15(\NLW_blk00000003/blk000006f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ef ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000706 ), + .Q(\blk00000003/sig00000707 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig00000706 ), + .Q15(\NLW_blk00000003/blk000006ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ed ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000704 ), + .Q(\blk00000003/sig00000705 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig00000704 ), + .Q15(\NLW_blk00000003/blk000006ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006eb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000702 ), + .Q(\blk00000003/sig00000703 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig00000702 ), + .Q15(\NLW_blk00000003/blk000006ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig00000700 ), + .Q(\blk00000003/sig00000701 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig00000700 ), + .Q15(\NLW_blk00000003/blk000006e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fe ), + .Q(\blk00000003/sig000006ff ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006fe ), + .Q15(\NLW_blk00000003/blk000006e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fc ), + .Q(\blk00000003/sig000006fd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006fc ), + .Q15(\NLW_blk00000003/blk000006e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006fa ), + .Q(\blk00000003/sig000006fb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006fa ), + .Q15(\NLW_blk00000003/blk000006e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f8 ), + .Q(\blk00000003/sig000006f9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006f8 ), + .Q15(\NLW_blk00000003/blk000006e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006df ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/sig000006f7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006f6 ), + .Q15(\NLW_blk00000003/blk000006de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/sig000006f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006f4 ), + .Q15(\NLW_blk00000003/blk000006dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006db ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/sig000006f3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006f2 ), + .Q15(\NLW_blk00000003/blk000006da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/sig000006f1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006f0 ), + .Q15(\NLW_blk00000003/blk000006d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ee ), + .Q(\blk00000003/sig000006ef ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006ee ), + .Q15(\NLW_blk00000003/blk000006d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ec ), + .Q(\blk00000003/sig000006ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006ec ), + .Q15(\NLW_blk00000003/blk000006d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006ea ), + .Q(\blk00000003/sig000006eb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ea ), + .Q15(\NLW_blk00000003/blk000006d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/sig000006e9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006e8 ), + .Q15(\NLW_blk00000003/blk000006d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e6 ), + .Q(\blk00000003/sig000006e7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006e6 ), + .Q15(\NLW_blk00000003/blk000006ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/sig000006e5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006e4 ), + .Q15(\NLW_blk00000003/blk000006cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cb ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e2 ), + .Q(\blk00000003/sig000006e3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006e2 ), + .Q15(\NLW_blk00000003/blk000006ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c9 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006e0 ), + .Q(\blk00000003/sig000006e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006e0 ), + .Q15(\NLW_blk00000003/blk000006c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c7 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006de ), + .Q(\blk00000003/sig000006df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006de ), + .Q15(\NLW_blk00000003/blk000006c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c5 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006dc ), + .Q(\blk00000003/sig000006dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006dc ), + .Q15(\NLW_blk00000003/blk000006c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c3 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006da ), + .Q(\blk00000003/sig000006db ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006da ), + .Q15(\NLW_blk00000003/blk000006c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c1 ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d8 ), + .Q(\blk00000003/sig000006d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006d8 ), + .Q15(\NLW_blk00000003/blk000006c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bf ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d6 ), + .Q(\blk00000003/sig000006d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006d6 ), + .Q15(\NLW_blk00000003/blk000006be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bd ( + .C(clk), + .CE(\blk00000003/sig00000683 ), + .D(\blk00000003/sig000006d4 ), + .Q(\blk00000003/sig000006d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ac ), + .CE(\blk00000003/sig00000683 ), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006d4 ), + .Q15(\NLW_blk00000003/blk000006bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d3 ), + .Q(\blk00000003/sig00000682 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e5 ), + .Q(\blk00000003/sig000006d3 ), + .Q15(\NLW_blk00000003/blk000006ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d2 ), + .Q(\blk00000003/sig0000056e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000006d2 ), + .Q15(\NLW_blk00000003/blk000006b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d1 ), + .Q(\blk00000003/sig00000681 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/sig000006d1 ), + .Q15(\NLW_blk00000003/blk000006b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006d0 ), + .Q(\blk00000003/sig0000056c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000006d0 ), + .Q15(\NLW_blk00000003/blk000006b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cf ), + .Q(\blk00000003/sig0000056b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000006cf ), + .Q15(\NLW_blk00000003/blk000006b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ce ), + .Q(\blk00000003/sig0000056d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006b0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000006ce ), + .Q15(\NLW_blk00000003/blk000006b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cd ), + .Q(\blk00000003/sig00000569 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ae ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000006cd ), + .Q15(\NLW_blk00000003/blk000006ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cc ), + .Q(\blk00000003/sig00000568 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006ac ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000006cc ), + .Q15(\NLW_blk00000003/blk000006ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006cb ), + .Q(\blk00000003/sig0000056a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006aa ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000006cb ), + .Q15(\NLW_blk00000003/blk000006aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ca ), + .Q(\blk00000003/sig00000567 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a8 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000006ca ), + .Q15(\NLW_blk00000003/blk000006a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c9 ), + .Q(\blk00000003/sig00000566 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a6 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000006c9 ), + .Q15(\NLW_blk00000003/blk000006a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c8 ), + .Q(\blk00000003/sig00000564 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a4 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000006c8 ), + .Q15(\NLW_blk00000003/blk000006a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c7 ), + .Q(\blk00000003/sig00000563 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a2 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000006c7 ), + .Q15(\NLW_blk00000003/blk000006a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c6 ), + .Q(\blk00000003/sig00000565 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000006a0 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000006c6 ), + .Q15(\NLW_blk00000003/blk000006a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c5 ), + .Q(\blk00000003/sig00000561 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000006c5 ), + .Q15(\NLW_blk00000003/blk0000069e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c4 ), + .Q(\blk00000003/sig00000560 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000006c4 ), + .Q15(\NLW_blk00000003/blk0000069c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c3 ), + .Q(\blk00000003/sig00000562 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000069a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000006c3 ), + .Q15(\NLW_blk00000003/blk0000069a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000699 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c2 ), + .Q(\blk00000003/sig0000055e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000698 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000006c2 ), + .Q15(\NLW_blk00000003/blk00000698_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000697 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c1 ), + .Q(\blk00000003/sig0000055d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000696 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000006c1 ), + .Q15(\NLW_blk00000003/blk00000696_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000695 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006c0 ), + .Q(\blk00000003/sig0000055f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000694 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000006c0 ), + .Q15(\NLW_blk00000003/blk00000694_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bf ), + .Q(\blk00000003/sig0000055c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000692 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000006bf ), + .Q15(\NLW_blk00000003/blk00000692_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000691 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006be ), + .Q(\blk00000003/sig0000055b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000690 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000006be ), + .Q15(\NLW_blk00000003/blk00000690_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bd ), + .Q(\blk00000003/sig00000559 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000006bd ), + .Q15(\NLW_blk00000003/blk0000068e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bc ), + .Q(\blk00000003/sig00000558 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000006bc ), + .Q15(\NLW_blk00000003/blk0000068c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000068b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006bb ), + .Q(\blk00000003/sig0000055a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000068a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000006bb ), + .Q15(\NLW_blk00000003/blk0000068a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000689 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ba ), + .Q(\blk00000003/sig0000059e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000688 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000006ba ), + .Q15(\NLW_blk00000003/blk00000688_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000687 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b9 ), + .Q(\blk00000003/sig0000059d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000686 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000006b9 ), + .Q15(\NLW_blk00000003/blk00000686_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000685 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b8 ), + .Q(\blk00000003/sig00000557 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000684 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000006b8 ), + .Q15(\NLW_blk00000003/blk00000684_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000683 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b7 ), + .Q(\blk00000003/sig0000059b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000682 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000006b7 ), + .Q15(\NLW_blk00000003/blk00000682_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000681 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b6 ), + .Q(\blk00000003/sig0000059a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000680 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000006b6 ), + .Q15(\NLW_blk00000003/blk00000680_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b5 ), + .Q(\blk00000003/sig0000059c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000006b5 ), + .Q15(\NLW_blk00000003/blk0000067e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b4 ), + .Q(\blk00000003/sig00000599 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000006b4 ), + .Q15(\NLW_blk00000003/blk0000067c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000067b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b3 ), + .Q(\blk00000003/sig00000598 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000067a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000006b3 ), + .Q15(\NLW_blk00000003/blk0000067a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000679 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b2 ), + .Q(\blk00000003/sig00000596 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000678 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000006b2 ), + .Q15(\NLW_blk00000003/blk00000678_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000677 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b1 ), + .Q(\blk00000003/sig00000595 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000676 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000006b1 ), + .Q15(\NLW_blk00000003/blk00000676_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000675 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/sig00000597 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000674 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000006b0 ), + .Q15(\NLW_blk00000003/blk00000674_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000673 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/sig00000593 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000672 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000006af ), + .Q15(\NLW_blk00000003/blk00000672_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000671 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ae ), + .Q(\blk00000003/sig00000592 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000670 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000006ae ), + .Q15(\NLW_blk00000003/blk00000670_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ad ), + .Q(\blk00000003/sig00000594 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000006ad ), + .Q15(\NLW_blk00000003/blk0000066e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ac ), + .Q(\blk00000003/sig00000590 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000006ac ), + .Q15(\NLW_blk00000003/blk0000066c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006ab ), + .Q(\blk00000003/sig0000058f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000006ab ), + .Q15(\NLW_blk00000003/blk0000066a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000669 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006aa ), + .Q(\blk00000003/sig00000591 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000668 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000006aa ), + .Q15(\NLW_blk00000003/blk00000668_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000667 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a9 ), + .Q(\blk00000003/sig0000058e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000666 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000006a9 ), + .Q15(\NLW_blk00000003/blk00000666_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000665 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a8 ), + .Q(\blk00000003/sig0000058d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000664 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000006a8 ), + .Q15(\NLW_blk00000003/blk00000664_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000663 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a7 ), + .Q(\blk00000003/sig0000058b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000662 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000006a7 ), + .Q15(\NLW_blk00000003/blk00000662_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000661 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a6 ), + .Q(\blk00000003/sig0000058a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000660 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000006a6 ), + .Q15(\NLW_blk00000003/blk00000660_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a5 ), + .Q(\blk00000003/sig0000058c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065e ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000006a5 ), + .Q15(\NLW_blk00000003/blk0000065e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a4 ), + .Q(\blk00000003/sig00000588 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065c ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/sig000006a4 ), + .Q15(\NLW_blk00000003/blk0000065c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a3 ), + .Q(\blk00000003/sig00000587 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/sig000006a3 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a2 ), + .Q(\blk00000003/sig00000589 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000006a2 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a1 ), + .Q(\blk00000003/sig000002c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002a8 ), + .Q(\blk00000003/sig000006a1 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000006a0 ), + .Q(\blk00000003/sig00000680 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d0 ), + .Q(\blk00000003/sig000006a0 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069f ), + .Q(\blk00000003/sig000002c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig000000ac ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d4 ), + .Q(\blk00000003/sig0000069f ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069e ), + .Q(\blk00000003/sig000005c8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000069e ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069d ), + .Q(\blk00000003/sig000005c7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig0000069d ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069c ), + .Q(\blk00000003/sig000005c5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000069c ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069b ), + .Q(\blk00000003/sig000005c4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig0000069b ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000069a ), + .Q(\blk00000003/sig000005c6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000069a ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000699 ), + .Q(\blk00000003/sig000005c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000699 ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000698 ), + .Q(\blk00000003/sig000005c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000698 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000697 ), + .Q(\blk00000003/sig000005c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000697 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000696 ), + .Q(\blk00000003/sig000005bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000696 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000695 ), + .Q(\blk00000003/sig000005be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000695 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000694 ), + .Q(\blk00000003/sig000005c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000694 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000693 ), + .Q(\blk00000003/sig000005bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000693 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000692 ), + .Q(\blk00000003/sig000005bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig00000692 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000691 ), + .Q(\blk00000003/sig000005ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig00000691 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000690 ), + .Q(\blk00000003/sig000005b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig00000690 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068f ), + .Q(\blk00000003/sig000005bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig0000068f ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068e ), + .Q(\blk00000003/sig000005b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000068e ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068d ), + .Q(\blk00000003/sig000005b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000068d ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068c ), + .Q(\blk00000003/sig000004f5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ac ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig0000068c ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068b ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig0000068b ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000068a ), + .Q(\blk00000003/sig000001df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ac ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig0000068a ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000627 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027e ) + ); + INV \blk00000003/blk00000626 ( + .I(\blk00000003/sig00000287 ), + .O(\blk00000003/sig00000277 ) + ); + INV \blk00000003/blk00000625 ( + .I(\blk00000003/sig000001ce ), + .O(\blk00000003/sig0000028c ) + ); + INV \blk00000003/blk00000624 ( + .I(\blk00000003/sig0000028e ), + .O(\blk00000003/sig0000027d ) + ); + INV \blk00000003/blk00000623 ( + .I(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000678 ) + ); + INV \blk00000003/blk00000622 ( + .I(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028f ) + ); + INV \blk00000003/blk00000621 ( + .I(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000278 ) + ); + INV \blk00000003/blk00000620 ( + .I(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000243 ) + ); + INV \blk00000003/blk0000061f ( + .I(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000ba ) + ); + INV \blk00000003/blk0000061e ( + .I(\blk00000003/sig000000ad ), + .O(\blk00000003/sig000001c7 ) + ); + INV \blk00000003/blk0000061d ( + .I(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig0000067c ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk0000061b ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig00000234 ), + .I2(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk0000061a ( + .I0(\blk00000003/sig00000248 ), + .I1(\blk00000003/sig0000023c ), + .I2(\blk00000003/sig0000024b ), + .I3(coef_ld), + .I4(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000023f ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk00000619 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000246 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk00000618 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024b ), + .I4(coef_ld), + .O(\blk00000003/sig00000245 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000617 ( + .I0(\blk00000003/sig00000287 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000219 ), + .O(\blk00000003/sig00000689 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000616 ( + .I0(\blk00000003/sig0000028e ), + .I1(ce), + .I2(\blk00000003/sig0000023a ), + .I3(\blk00000003/sig0000027f ), + .O(\blk00000003/sig00000688 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk00000615 ( + .I0(\blk00000003/sig0000067b ), + .I1(ce), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig00000686 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000614 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000067f ), + .O(\blk00000003/sig00000685 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000613 ( + .I0(ce), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig0000067d ), + .O(\blk00000003/sig00000684 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk00000612 ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig00000291 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000687 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000611 ( + .C(clk), + .D(\blk00000003/sig00000689 ), + .Q(\blk00000003/sig00000287 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk00000610 ( + .C(clk), + .D(\blk00000003/sig00000688 ), + .Q(\blk00000003/sig0000028e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .D(\blk00000003/sig00000687 ), + .R(sclr), + .Q(\blk00000003/sig0000067e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060e ( + .C(clk), + .D(\blk00000003/sig00000686 ), + .R(sclr), + .Q(\blk00000003/sig0000067b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060d ( + .I0(\blk00000003/sig00000602 ), + .O(\blk00000003/sig000005fd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060c ( + .I0(\blk00000003/sig00000601 ), + .O(\blk00000003/sig000005fa ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060b ( + .I0(\blk00000003/sig00000600 ), + .O(\blk00000003/sig000005f7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000060a ( + .I0(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000609 ( + .I0(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000608 ( + .I0(\blk00000003/sig000002ba ), + .O(\blk00000003/sig000002bb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000607 ( + .I0(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a0 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000606 ( + .I0(\blk00000003/sig0000067e ), + .O(\blk00000003/sig00000296 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000605 ( + .I0(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000269 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000604 ( + .I0(\blk00000003/sig00000264 ), + .O(\blk00000003/sig00000265 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000603 ( + .I0(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000254 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000602 ( + .I0(\blk00000003/sig0000024f ), + .O(\blk00000003/sig0000024d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000601 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig0000022a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000600 ( + .I0(\blk00000003/sig000001cc ), + .O(\blk00000003/sig000000bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000672 ), + .R(sclr), + .Q(\blk00000003/sig00000677 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066f ), + .R(sclr), + .Q(\blk00000003/sig00000676 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000066c ), + .R(sclr), + .Q(\blk00000003/sig00000675 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000669 ), + .R(sclr), + .Q(\blk00000003/sig00000674 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000666 ), + .R(sclr), + .Q(\blk00000003/sig00000673 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f2 ), + .R(sclr), + .Q(\blk00000003/sig00000603 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fe ), + .S(sclr), + .Q(\blk00000003/sig00000602 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005fb ), + .R(sclr), + .Q(\blk00000003/sig00000601 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f8 ), + .R(sclr), + .Q(\blk00000003/sig00000600 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005f5 ), + .S(sclr), + .Q(\blk00000003/sig000005ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c0 ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bd ), + .R(\blk00000003/sig000002c3 ), + .Q(\blk00000003/sig000002ba ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b3 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b8 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ab ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ae ), + .R(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002b0 ) + ); + FDR \blk00000003/blk000005ef ( + .C(clk), + .D(\blk00000003/sig00000685 ), + .R(ce), + .Q(\blk00000003/sig0000067f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000005ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .S(sclr), + .Q(\blk00000003/sig000002a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a4 ), + .R(sclr), + .Q(\blk00000003/sig000002a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000001e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR \blk00000003/blk000005ea ( + .C(clk), + .D(\blk00000003/sig00000684 ), + .R(ce), + .Q(\blk00000003/sig0000067d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000268 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000267 ), + .R(\blk00000003/sig0000026d ), + .Q(\blk00000003/sig00000264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025c ), + .R(coef_ld), + .Q(\blk00000003/sig00000262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025f ), + .R(coef_ld), + .Q(\blk00000003/sig00000261 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000258 ), + .R(sclr), + .Q(\blk00000003/sig00000259 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000255 ), + .R(sclr), + .Q(\blk00000003/sig00000256 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000251 ), + .R(coef_ld), + .Q(\blk00000003/sig00000252 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024e ), + .R(coef_ld), + .Q(\blk00000003/sig0000024f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000af ), + .R(sclr), + .Q(\blk00000003/sig000000ad ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000665 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig00000674 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000668 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig00000675 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000005dd ( + .I0(\blk00000003/sig00000676 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig0000066e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000005dc ( + .I0(\blk00000003/sig00000677 ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig000001dd ), + .O(\blk00000003/sig00000671 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000005db ( + .I0(\blk00000003/sig000001dd ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig00000663 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005da ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000661 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000662 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig00000660 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000065e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000065f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000065d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000065b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000065c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig0000065a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000658 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005d0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000659 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000657 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ce ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000655 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000656 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000654 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005cb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000652 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ca ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000653 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000651 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000064f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig00000650 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000064e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000064c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000064d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000064b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000649 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig0000064a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005c0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000648 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bf ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000646 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005be ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000647 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bd ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000645 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bc ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000643 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005bb ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000644 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ba ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000642 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig00000640 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000641 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000063f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000063d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000063e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000063c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig0000063a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000063b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000639 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005b0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000637 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005af ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000638 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ae ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000636 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ad ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000635 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ac ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000633 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005ab ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000634 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005aa ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000632 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a9 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig00000630 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a8 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig00000631 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a7 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000062f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a6 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000062d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a5 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000062e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a4 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000062c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a3 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig0000062a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a2 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig0000062b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a1 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000629 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000005a0 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000627 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000628 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000626 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000624 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000625 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000623 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000059a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig00000621 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000599 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000622 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000598 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig00000620 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000597 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000061e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000596 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000061f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000595 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000061d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000594 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig0000061b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000593 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000061c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000592 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig0000061a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000591 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000618 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000590 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000619 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000617 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000615 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000616 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058c ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000614 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058b ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000612 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000058a ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000613 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000589 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig00000611 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000588 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000060f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000587 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig00000610 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000586 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000060e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000585 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000060c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000584 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000060d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000583 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig0000060b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000582 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000609 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000581 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig0000060a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000580 ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000608 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057f ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000606 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057e ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000607 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000057d ( + .I0(\blk00000003/sig000001cc ), + .I1(\blk00000003/sig000001dd ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000605 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000057c ( + .I0(\blk00000003/sig00000603 ), + .I1(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000005f1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057b ( + .I0(ce), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000683 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000057a ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/sig000005ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000579 ( + .I0(ce), + .I1(\blk00000003/sig00000682 ), + .O(\blk00000003/sig000005ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000578 ( + .I0(ce), + .I1(\blk00000003/sig00000681 ), + .O(\blk00000003/sig000005ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000577 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002b5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000576 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig000002b8 ), + .O(\blk00000003/sig000002b2 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000575 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002af ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000574 ( + .I0(\blk00000003/sig000002b0 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig00000680 ), + .O(\blk00000003/sig000002ad ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000573 ( + .I0(\blk00000003/sig00000680 ), + .I1(\blk00000003/sig000002c1 ), + .I2(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002aa ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000572 ( + .I0(sclr), + .I1(\blk00000003/sig0000067f ), + .O(\blk00000003/sig000002a7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000571 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000001d6 ), + .O(\blk00000003/sig000002a3 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000570 ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig0000029f ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000056f ( + .I0(\blk00000003/sig000001e6 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig00000298 ), + .O(\blk00000003/sig0000029d ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000056e ( + .I0(nd), + .I1(\blk00000003/sig00000298 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000056d ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000293 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk0000056c ( + .I0(\blk00000003/sig0000067e ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001e7 ), + .O(\blk00000003/sig00000295 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056b ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig00000242 ), + .O(\blk00000003/sig0000028d ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000056a ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023a ), + .O(\blk00000003/sig0000028a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000569 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000288 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000568 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig00000248 ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000283 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000567 ( + .I0(\blk00000003/sig00000240 ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000242 ), + .O(\blk00000003/sig00000285 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000566 ( + .I0(\blk00000003/sig0000023b ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000565 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig0000027a ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000564 ( + .I0(\blk00000003/sig00000238 ), + .I1(\blk00000003/sig00000242 ), + .I2(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000275 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000563 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig0000023e ), + .O(\blk00000003/sig00000271 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000562 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig00000248 ), + .O(\blk00000003/sig00000273 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000561 ( + .I0(\blk00000003/sig0000024b ), + .I1(\blk00000003/sig0000067d ), + .O(\blk00000003/sig0000026c ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000560 ( + .I0(coef_we), + .I1(\blk00000003/sig00000222 ), + .I2(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000260 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000055f ( + .I0(\blk00000003/sig00000261 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .O(\blk00000003/sig0000025e ) + ); + LUT4 #( + .INIT ( 16'hE6CC )) + \blk00000003/blk0000055e ( + .I0(coef_we), + .I1(\blk00000003/sig00000262 ), + .I2(\blk00000003/sig00000222 ), + .I3(\blk00000003/sig00000227 ), + .O(\blk00000003/sig0000025b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055d ( + .I0(\blk00000003/sig00000259 ), + .I1(\blk00000003/sig000001c3 ), + .O(\blk00000003/sig00000257 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000055c ( + .I0(\blk00000003/sig00000252 ), + .I1(coef_we), + .O(\blk00000003/sig00000250 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000055b ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .O(\blk00000003/sig00000241 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000055a ( + .I0(coef_we), + .I1(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ) + ); + LUT3 #( + .INIT ( 8'h40 )) + \blk00000003/blk00000559 ( + .I0(coef_ld), + .I1(coef_we), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000249 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000558 ( + .I0(\blk00000003/sig00000261 ), + .I1(\blk00000003/sig00000262 ), + .O(\blk00000003/sig0000022d ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000557 ( + .I0(\blk00000003/sig0000024f ), + .I1(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000229 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000556 ( + .I0(\blk00000003/sig00000262 ), + .I1(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000555 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024b ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig00000220 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000554 ( + .I0(coef_we), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig00000234 ), + .O(\blk00000003/sig0000021d ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000553 ( + .I0(\blk00000003/sig00000236 ), + .I1(coef_we), + .I2(\blk00000003/sig00000227 ), + .I3(\blk00000003/sig00000222 ), + .I4(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000552 ( + .I0(\blk00000003/sig00000234 ), + .I1(\blk00000003/sig00000236 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000233 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000551 ( + .I0(nd), + .I1(\blk00000003/sig00000291 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e5 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000550 ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000001dd ), + .O(\blk00000003/sig000001e3 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000054f ( + .I0(\blk00000003/sig000000bf ), + .I1(\blk00000003/sig000005ff ), + .I2(\blk00000003/sig0000067c ), + .O(\blk00000003/sig000000c0 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000054e ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000005ff ), + .O(\blk00000003/sig000001de ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000054d ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001ca ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000054c ( + .I0(\blk00000003/sig00000256 ), + .I1(\blk00000003/sig00000259 ), + .O(\blk00000003/sig000001c4 ) + ); + LUT5 #( + .INIT ( 32'h00002000 )) + \blk00000003/blk0000054b ( + .I0(\blk00000003/sig00000673 ), + .I1(\blk00000003/sig00000674 ), + .I2(\blk00000003/sig00000675 ), + .I3(\blk00000003/sig00000676 ), + .I4(\blk00000003/sig00000677 ), + .O(\blk00000003/sig000000c2 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk0000054a ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig000001c3 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000549 ( + .I0(\blk00000003/sig000002a6 ), + .I1(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001db ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000548 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b5 ), + .O(\blk00000003/sig000000b4 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000547 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig000000b3 ), + .O(\blk00000003/sig000000b2 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000546 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000545 ( + .I0(\blk00000003/sig000000ad ), + .I1(\blk00000003/sig000001c6 ), + .O(\blk00000003/sig000000ae ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000544 ( + .I0(\blk00000003/sig000001c3 ), + .I1(\blk00000003/sig000001e4 ), + .I2(\blk00000003/sig000001d4 ), + .I3(\blk00000003/sig000001d6 ), + .I4(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000543 ( + .I0(\blk00000003/sig000001d4 ), + .I1(\blk00000003/sig0000067b ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001cf ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000542 ( + .I0(\blk00000003/sig000001e4 ), + .I1(\blk00000003/sig000001d4 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d2 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000541 ( + .I0(\blk00000003/sig000002a5 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig000001e2 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk00000540 ( + .I0(ce), + .I1(\blk00000003/sig00000679 ), + .I2(\blk00000003/sig0000067a ), + .I3(\blk00000003/sig000000b1 ), + .O(\blk00000003/sig000000b0 ) + ); + MUXCY \blk00000003/blk0000053f ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000678 ), + .O(\blk00000003/sig00000670 ) + ); + MUXCY_L \blk00000003/blk0000053e ( + .CI(\blk00000003/sig00000670 ), + .DI(\blk00000003/sig00000677 ), + .S(\blk00000003/sig00000671 ), + .LO(\blk00000003/sig0000066d ) + ); + MUXCY_L \blk00000003/blk0000053d ( + .CI(\blk00000003/sig0000066d ), + .DI(\blk00000003/sig00000676 ), + .S(\blk00000003/sig0000066e ), + .LO(\blk00000003/sig0000066a ) + ); + MUXCY_L \blk00000003/blk0000053c ( + .CI(\blk00000003/sig0000066a ), + .DI(\blk00000003/sig00000675 ), + .S(\blk00000003/sig0000066b ), + .LO(\blk00000003/sig00000667 ) + ); + MUXCY_L \blk00000003/blk0000053b ( + .CI(\blk00000003/sig00000667 ), + .DI(\blk00000003/sig00000674 ), + .S(\blk00000003/sig00000668 ), + .LO(\blk00000003/sig00000664 ) + ); + MUXCY_D \blk00000003/blk0000053a ( + .CI(\blk00000003/sig00000664 ), + .DI(\blk00000003/sig00000673 ), + .S(\blk00000003/sig00000665 ), + .O(\NLW_blk00000003/blk0000053a_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000053a_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000539 ( + .CI(\blk00000003/sig00000670 ), + .LI(\blk00000003/sig00000671 ), + .O(\blk00000003/sig00000672 ) + ); + XORCY \blk00000003/blk00000538 ( + .CI(\blk00000003/sig0000066d ), + .LI(\blk00000003/sig0000066e ), + .O(\blk00000003/sig0000066f ) + ); + XORCY \blk00000003/blk00000537 ( + .CI(\blk00000003/sig0000066a ), + .LI(\blk00000003/sig0000066b ), + .O(\blk00000003/sig0000066c ) + ); + XORCY \blk00000003/blk00000536 ( + .CI(\blk00000003/sig00000667 ), + .LI(\blk00000003/sig00000668 ), + .O(\blk00000003/sig00000669 ) + ); + XORCY \blk00000003/blk00000535 ( + .CI(\blk00000003/sig00000664 ), + .LI(\blk00000003/sig00000665 ), + .O(\blk00000003/sig00000666 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000528 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000526 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000524 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000522 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000520 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000518 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000516 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000514 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000512 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000510 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000506 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000504 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000503 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000502 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000501 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000630 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000500 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000062a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000629 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000628 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000627 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000626 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000625 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000624 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000623 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000622 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000621 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000620 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000061a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000619 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000618 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000617 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000616 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000615 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000614 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000613 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000612 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000611 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000610 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000060a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000609 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000608 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000607 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000606 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000605 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig000001dd ) + ); + MUXCY_L \blk00000003/blk000004d4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000603 ), + .S(\blk00000003/sig000005f1 ), + .LO(\blk00000003/sig000005fc ) + ); + MUXCY_L \blk00000003/blk000004d3 ( + .CI(\blk00000003/sig000005fc ), + .DI(\blk00000003/sig00000602 ), + .S(\blk00000003/sig000005fd ), + .LO(\blk00000003/sig000005f9 ) + ); + MUXCY_L \blk00000003/blk000004d2 ( + .CI(\blk00000003/sig000005f9 ), + .DI(\blk00000003/sig00000601 ), + .S(\blk00000003/sig000005fa ), + .LO(\blk00000003/sig000005f6 ) + ); + MUXCY_L \blk00000003/blk000004d1 ( + .CI(\blk00000003/sig000005f6 ), + .DI(\blk00000003/sig00000600 ), + .S(\blk00000003/sig000005f7 ), + .LO(\blk00000003/sig000005f3 ) + ); + MUXCY_D \blk00000003/blk000004d0 ( + .CI(\blk00000003/sig000005f3 ), + .DI(\blk00000003/sig000005ff ), + .S(\blk00000003/sig000005f4 ), + .O(\NLW_blk00000003/blk000004d0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000004d0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000004cf ( + .CI(\blk00000003/sig000005fc ), + .LI(\blk00000003/sig000005fd ), + .O(\blk00000003/sig000005fe ) + ); + XORCY \blk00000003/blk000004ce ( + .CI(\blk00000003/sig000005f9 ), + .LI(\blk00000003/sig000005fa ), + .O(\blk00000003/sig000005fb ) + ); + XORCY \blk00000003/blk000004cd ( + .CI(\blk00000003/sig000005f6 ), + .LI(\blk00000003/sig000005f7 ), + .O(\blk00000003/sig000005f8 ) + ); + XORCY \blk00000003/blk000004cc ( + .CI(\blk00000003/sig000005f3 ), + .LI(\blk00000003/sig000005f4 ), + .O(\blk00000003/sig000005f5 ) + ); + XORCY \blk00000003/blk000004cb ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000005f1 ), + .O(\blk00000003/sig000005f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig0000050e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a2 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig0000050d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig0000050c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a0 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig0000050b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000050a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig00000509 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig00000508 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig00000507 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig00000506 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000049a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig00000505 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000504 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000498 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000503 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000502 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000496 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000495 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000494 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000491 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig000004fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000490 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig000004fb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig000004fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig000004f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig000004f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig000004f7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000450 ), + .R(sclr), + .Q(\blk00000003/sig00000526 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044f ), + .R(sclr), + .Q(\blk00000003/sig00000525 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000489 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044e ), + .R(sclr), + .Q(\blk00000003/sig00000524 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000488 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044d ), + .R(sclr), + .Q(\blk00000003/sig00000523 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000487 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044c ), + .R(sclr), + .Q(\blk00000003/sig00000522 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000486 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044b ), + .R(sclr), + .Q(\blk00000003/sig00000521 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000485 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000044a ), + .R(sclr), + .Q(\blk00000003/sig00000520 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000484 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000449 ), + .R(sclr), + .Q(\blk00000003/sig0000051f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000483 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000448 ), + .R(sclr), + .Q(\blk00000003/sig0000051e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000482 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000447 ), + .R(sclr), + .Q(\blk00000003/sig0000051d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000481 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000446 ), + .R(sclr), + .Q(\blk00000003/sig0000051c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000480 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000445 ), + .R(sclr), + .Q(\blk00000003/sig0000051b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047f ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000444 ), + .R(sclr), + .Q(\blk00000003/sig0000051a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000443 ), + .R(sclr), + .Q(\blk00000003/sig00000519 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047d ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000442 ), + .R(sclr), + .Q(\blk00000003/sig00000518 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047c ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000441 ), + .R(sclr), + .Q(\blk00000003/sig00000517 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047b ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000440 ), + .R(sclr), + .Q(\blk00000003/sig00000516 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047a ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043f ), + .R(sclr), + .Q(\blk00000003/sig00000515 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000479 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043e ), + .R(sclr), + .Q(\blk00000003/sig00000514 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000478 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043d ), + .R(sclr), + .Q(\blk00000003/sig00000513 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000477 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043c ), + .R(sclr), + .Q(\blk00000003/sig00000512 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000476 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043b ), + .R(sclr), + .Q(\blk00000003/sig00000511 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000475 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig0000043a ), + .R(sclr), + .Q(\blk00000003/sig00000510 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000474 ( + .C(clk), + .CE(\blk00000003/sig000005ef ), + .D(\blk00000003/sig00000439 ), + .R(sclr), + .Q(\blk00000003/sig0000050f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004aa ), + .R(sclr), + .Q(\blk00000003/sig00000586 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a9 ), + .R(sclr), + .Q(\blk00000003/sig00000585 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a8 ), + .R(sclr), + .Q(\blk00000003/sig00000584 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000449 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a7 ), + .R(sclr), + .Q(\blk00000003/sig00000583 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000448 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a6 ), + .R(sclr), + .Q(\blk00000003/sig00000582 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000447 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a5 ), + .R(sclr), + .Q(\blk00000003/sig00000581 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000446 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a4 ), + .R(sclr), + .Q(\blk00000003/sig00000580 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a3 ), + .R(sclr), + .Q(\blk00000003/sig0000057f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000444 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a2 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000443 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a1 ), + .R(sclr), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000442 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004a0 ), + .R(sclr), + .Q(\blk00000003/sig0000057c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000441 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049f ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000440 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049e ), + .R(sclr), + .Q(\blk00000003/sig0000057a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049d ), + .R(sclr), + .Q(\blk00000003/sig00000579 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049c ), + .R(sclr), + .Q(\blk00000003/sig00000578 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049b ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig0000049a ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000499 ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000498 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000439 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000497 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000438 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000496 ), + .R(sclr), + .Q(\blk00000003/sig00000572 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000437 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000495 ), + .R(sclr), + .Q(\blk00000003/sig00000571 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000436 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000494 ), + .R(sclr), + .Q(\blk00000003/sig00000570 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000435 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig00000493 ), + .R(sclr), + .Q(\blk00000003/sig0000056f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000434 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig0000053e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000433 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig0000053d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig0000053c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000431 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig0000053b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000430 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000053a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig00000539 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig00000538 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig00000537 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042c ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig00000536 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042b ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig00000535 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042a ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000534 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000429 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000533 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000428 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000532 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000427 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000531 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000426 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000530 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000425 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig0000052f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000424 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig0000052e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000423 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig0000052d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000422 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig0000052c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000421 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig0000052b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000420 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig0000052a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000529 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041e ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000528 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000527 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004da ), + .R(sclr), + .Q(\blk00000003/sig000005b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d9 ), + .R(sclr), + .Q(\blk00000003/sig000005b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d8 ), + .R(sclr), + .Q(\blk00000003/sig000005b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000419 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d7 ), + .R(sclr), + .Q(\blk00000003/sig000005b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000418 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d6 ), + .R(sclr), + .Q(\blk00000003/sig000005b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000417 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d5 ), + .R(sclr), + .Q(\blk00000003/sig000005b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000416 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d4 ), + .R(sclr), + .Q(\blk00000003/sig000005b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000415 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d3 ), + .R(sclr), + .Q(\blk00000003/sig000005af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000414 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d2 ), + .R(sclr), + .Q(\blk00000003/sig000005ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000413 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d1 ), + .R(sclr), + .Q(\blk00000003/sig000005ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000412 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004d0 ), + .R(sclr), + .Q(\blk00000003/sig000005ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000411 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cf ), + .R(sclr), + .Q(\blk00000003/sig000005ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000410 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ce ), + .R(sclr), + .Q(\blk00000003/sig000005aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040f ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cd ), + .R(sclr), + .Q(\blk00000003/sig000005a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040e ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cc ), + .R(sclr), + .Q(\blk00000003/sig000005a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040d ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004cb ), + .R(sclr), + .Q(\blk00000003/sig000005a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004ca ), + .R(sclr), + .Q(\blk00000003/sig000005a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040b ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c9 ), + .R(sclr), + .Q(\blk00000003/sig000005a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040a ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c8 ), + .R(sclr), + .Q(\blk00000003/sig000005a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000409 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c7 ), + .R(sclr), + .Q(\blk00000003/sig000005a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000408 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c6 ), + .R(sclr), + .Q(\blk00000003/sig000005a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000407 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c5 ), + .R(sclr), + .Q(\blk00000003/sig000005a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000406 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c4 ), + .R(sclr), + .Q(\blk00000003/sig000005a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000405 ( + .C(clk), + .CE(\blk00000003/sig000005ee ), + .D(\blk00000003/sig000004c3 ), + .R(sclr), + .Q(\blk00000003/sig0000059f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000404 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000468 ), + .R(sclr), + .Q(\blk00000003/sig00000556 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000467 ), + .R(sclr), + .Q(\blk00000003/sig00000555 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000466 ), + .R(sclr), + .Q(\blk00000003/sig00000554 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000465 ), + .R(sclr), + .Q(\blk00000003/sig00000553 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000464 ), + .R(sclr), + .Q(\blk00000003/sig00000552 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000463 ), + .R(sclr), + .Q(\blk00000003/sig00000551 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000462 ), + .R(sclr), + .Q(\blk00000003/sig00000550 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000461 ), + .R(sclr), + .Q(\blk00000003/sig0000054f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000460 ), + .R(sclr), + .Q(\blk00000003/sig0000054e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045f ), + .R(sclr), + .Q(\blk00000003/sig0000054d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045e ), + .R(sclr), + .Q(\blk00000003/sig0000054c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045d ), + .R(sclr), + .Q(\blk00000003/sig0000054b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045c ), + .R(sclr), + .Q(\blk00000003/sig0000054a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045b ), + .R(sclr), + .Q(\blk00000003/sig00000549 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig0000045a ), + .R(sclr), + .Q(\blk00000003/sig00000548 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000459 ), + .R(sclr), + .Q(\blk00000003/sig00000547 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000458 ), + .R(sclr), + .Q(\blk00000003/sig00000546 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000457 ), + .R(sclr), + .Q(\blk00000003/sig00000545 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000456 ), + .R(sclr), + .Q(\blk00000003/sig00000544 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000455 ), + .R(sclr), + .Q(\blk00000003/sig00000543 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000454 ), + .R(sclr), + .Q(\blk00000003/sig00000542 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000453 ), + .R(sclr), + .Q(\blk00000003/sig00000541 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000452 ), + .R(sclr), + .Q(\blk00000003/sig00000540 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(\blk00000003/sig000005ed ), + .D(\blk00000003/sig00000451 ), + .R(sclr), + .Q(\blk00000003/sig0000053f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .R(sclr), + .Q(\blk00000003/sig000004ef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b7 ), + .R(sclr), + .Q(\blk00000003/sig000004ed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ba ), + .R(sclr), + .Q(\blk00000003/sig000004eb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002be ), + .R(sclr), + .Q(\blk00000003/sig000004e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig000004e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f5 ), + .R(sclr), + .Q(\blk00000003/sig000004e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b1 ), + .R(sclr), + .Q(\blk00000003/sig000004f3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b0 ), + .R(sclr), + .Q(\blk00000003/sig000004f1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .R(sclr), + .Q(\blk00000003/sig000004f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f1 ), + .R(sclr), + .Q(\blk00000003/sig000004f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ef ), + .R(sclr), + .Q(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004ed ), + .R(sclr), + .Q(\blk00000003/sig000004ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004eb ), + .R(sclr), + .Q(\blk00000003/sig000004ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e9 ), + .R(sclr), + .Q(\blk00000003/sig000004ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e7 ), + .R(sclr), + .Q(\blk00000003/sig000004e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000106 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e5 ), + .R(sclr), + .Q(\blk00000003/sig000004e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000105 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e3 ), + .R(sclr), + .Q(\blk00000003/sig000004e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000104 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004e1 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000232 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004dc ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004db ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026b ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000268 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004dc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000264 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000004db ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fc ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fc_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fc_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fc_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fc_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fc_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fc_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fc_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fc_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fc_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000004ab , \blk00000003/sig000004ab , \blk00000003/sig000004ac , \blk00000003/sig000004ad , \blk00000003/sig000004ae , +\blk00000003/sig000004af , \blk00000003/sig000004b0 , \blk00000003/sig000004b1 , \blk00000003/sig000004b2 , \blk00000003/sig000004b3 , +\blk00000003/sig000004b4 , \blk00000003/sig000004b5 , \blk00000003/sig000004b6 , \blk00000003/sig000004b7 , \blk00000003/sig000004b8 , +\blk00000003/sig000004b9 , \blk00000003/sig000004ba , \blk00000003/sig000004bb , \blk00000003/sig000004bc , \blk00000003/sig000004bd , +\blk00000003/sig000004be , \blk00000003/sig000004bf , \blk00000003/sig000004c0 , \blk00000003/sig000004c1 , \blk00000003/sig000004c2 }), + .P({\NLW_blk00000003/blk000000fc_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fc_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fc_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c3 , +\blk00000003/sig000004c3 , \blk00000003/sig000004c3 , \blk00000003/sig000004c4 , \blk00000003/sig000004c5 , \blk00000003/sig000004c6 , +\blk00000003/sig000004c7 , \blk00000003/sig000004c8 , \blk00000003/sig000004c9 , \blk00000003/sig000004ca , \blk00000003/sig000004cb , +\blk00000003/sig000004cc , \blk00000003/sig000004cd , \blk00000003/sig000004ce , \blk00000003/sig000004cf , \blk00000003/sig000004d0 , +\blk00000003/sig000004d1 , \blk00000003/sig000004d2 , \blk00000003/sig000004d3 , \blk00000003/sig000004d4 , \blk00000003/sig000004d5 , +\blk00000003/sig000004d6 , \blk00000003/sig000004d7 , \blk00000003/sig000004d8 , \blk00000003/sig000004d9 , \blk00000003/sig000004da }), + .PCOUT({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fb ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fb_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fb_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fb_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fb_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fb_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fb_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fb_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fb_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig00000469 , \blk00000003/sig0000046a , \blk00000003/sig0000046b , \blk00000003/sig0000046c , \blk00000003/sig0000046d , +\blk00000003/sig0000046e , \blk00000003/sig0000046f , \blk00000003/sig00000470 , \blk00000003/sig00000471 , \blk00000003/sig00000472 , +\blk00000003/sig00000473 , \blk00000003/sig00000474 , \blk00000003/sig00000475 , \blk00000003/sig00000476 , \blk00000003/sig00000477 , +\blk00000003/sig00000478 , \blk00000003/sig00000479 , \blk00000003/sig0000047a }), + .BCOUT({\NLW_blk00000003/blk000000fb_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fb_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig0000047b , \blk00000003/sig0000047b , \blk00000003/sig0000047c , \blk00000003/sig0000047d , \blk00000003/sig0000047e , +\blk00000003/sig0000047f , \blk00000003/sig00000480 , \blk00000003/sig00000481 , \blk00000003/sig00000482 , \blk00000003/sig00000483 , +\blk00000003/sig00000484 , \blk00000003/sig00000485 , \blk00000003/sig00000486 , \blk00000003/sig00000487 , \blk00000003/sig00000488 , +\blk00000003/sig00000489 , \blk00000003/sig0000048a , \blk00000003/sig0000048b , \blk00000003/sig0000048c , \blk00000003/sig0000048d , +\blk00000003/sig0000048e , \blk00000003/sig0000048f , \blk00000003/sig00000490 , \blk00000003/sig00000491 , \blk00000003/sig00000492 }), + .P({\NLW_blk00000003/blk000000fb_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fb_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fb_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000493 , +\blk00000003/sig00000493 , \blk00000003/sig00000493 , \blk00000003/sig00000494 , \blk00000003/sig00000495 , \blk00000003/sig00000496 , +\blk00000003/sig00000497 , \blk00000003/sig00000498 , \blk00000003/sig00000499 , \blk00000003/sig0000049a , \blk00000003/sig0000049b , +\blk00000003/sig0000049c , \blk00000003/sig0000049d , \blk00000003/sig0000049e , \blk00000003/sig0000049f , \blk00000003/sig000004a0 , +\blk00000003/sig000004a1 , \blk00000003/sig000004a2 , \blk00000003/sig000004a3 , \blk00000003/sig000004a4 , \blk00000003/sig000004a5 , +\blk00000003/sig000004a6 , \blk00000003/sig000004a7 , \blk00000003/sig000004a8 , \blk00000003/sig000004a9 , \blk00000003/sig000004aa }), + .PCOUT({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000fa ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000fa_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000fa_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000fa_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000fa_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000fa_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000fa_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000fa_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d , +\blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , \blk00000003/sig00000412 , +\blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , \blk00000003/sig00000417 , +\blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , \blk00000003/sig0000041c , +\blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , \blk00000003/sig00000421 , +\blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 , \blk00000003/sig00000426 , +\blk00000003/sig00000427 , \blk00000003/sig00000428 , \blk00000003/sig00000429 , \blk00000003/sig0000042a , \blk00000003/sig0000042b , +\blk00000003/sig0000042c , \blk00000003/sig0000042d , \blk00000003/sig0000042e , \blk00000003/sig0000042f , \blk00000003/sig00000430 , +\blk00000003/sig00000431 , \blk00000003/sig00000432 , \blk00000003/sig00000433 , \blk00000003/sig00000434 , \blk00000003/sig00000435 , +\blk00000003/sig00000436 , \blk00000003/sig00000437 , \blk00000003/sig00000438 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000fa_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000fa_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000fa_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000439 , \blk00000003/sig00000439 , \blk00000003/sig0000043a , \blk00000003/sig0000043b , \blk00000003/sig0000043c , +\blk00000003/sig0000043d , \blk00000003/sig0000043e , \blk00000003/sig0000043f , \blk00000003/sig00000440 , \blk00000003/sig00000441 , +\blk00000003/sig00000442 , \blk00000003/sig00000443 , \blk00000003/sig00000444 , \blk00000003/sig00000445 , \blk00000003/sig00000446 , +\blk00000003/sig00000447 , \blk00000003/sig00000448 , \blk00000003/sig00000449 , \blk00000003/sig0000044a , \blk00000003/sig0000044b , +\blk00000003/sig0000044c , \blk00000003/sig0000044d , \blk00000003/sig0000044e , \blk00000003/sig0000044f , \blk00000003/sig00000450 }), + .P({\NLW_blk00000003/blk000000fa_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000fa_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000fa_P<0>_UNCONNECTED }), + .A({\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000451 , +\blk00000003/sig00000451 , \blk00000003/sig00000451 , \blk00000003/sig00000452 , \blk00000003/sig00000453 , \blk00000003/sig00000454 , +\blk00000003/sig00000455 , \blk00000003/sig00000456 , \blk00000003/sig00000457 , \blk00000003/sig00000458 , \blk00000003/sig00000459 , +\blk00000003/sig0000045a , \blk00000003/sig0000045b , \blk00000003/sig0000045c , \blk00000003/sig0000045d , \blk00000003/sig0000045e , +\blk00000003/sig0000045f , \blk00000003/sig00000460 , \blk00000003/sig00000461 , \blk00000003/sig00000462 , \blk00000003/sig00000463 , +\blk00000003/sig00000464 , \blk00000003/sig00000465 , \blk00000003/sig00000466 , \blk00000003/sig00000467 , \blk00000003/sig00000468 }), + .PCOUT({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f9 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f9_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f9_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f9_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f9_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f9_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f9_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f9_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000397 , \blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , +\blk00000003/sig0000039c , \blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , +\blk00000003/sig000003a1 , \blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , +\blk00000003/sig000003a6 , \blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , +\blk00000003/sig000003ab , \blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , +\blk00000003/sig000003b0 , \blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 , \blk00000003/sig000003b4 , +\blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , \blk00000003/sig000003b9 , +\blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , \blk00000003/sig000003be , +\blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , \blk00000003/sig000003c3 , +\blk00000003/sig000003c4 , \blk00000003/sig000003c5 , \blk00000003/sig000003c6 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f9_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , \blk00000003/sig000003ca , \blk00000003/sig000003cb , +\blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , \blk00000003/sig000003cf , \blk00000003/sig000003d0 , +\blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , \blk00000003/sig000003d4 , \blk00000003/sig000003d5 , +\blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 }), + .BCOUT({\NLW_blk00000003/blk000000f9_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f9_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003d9 , \blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , +\blk00000003/sig000003dd , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 }), + .P({\NLW_blk00000003/blk000000f9_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f9_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f9_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f1 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , +\blk00000003/sig000003f5 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f8 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f8_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f8_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f8_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f8_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f8_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f8_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f8_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f8_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f8_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f8_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000337 , \blk00000003/sig00000337 , \blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , +\blk00000003/sig0000033b , \blk00000003/sig0000033c , \blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , +\blk00000003/sig00000340 , \blk00000003/sig00000341 , \blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , +\blk00000003/sig00000345 , \blk00000003/sig00000346 , \blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , +\blk00000003/sig0000034a , \blk00000003/sig0000034b , \blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e }), + .P({\NLW_blk00000003/blk000000f8_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f8_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f8_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig0000034f , +\blk00000003/sig0000034f , \blk00000003/sig0000034f , \blk00000003/sig00000350 , \blk00000003/sig00000351 , \blk00000003/sig00000352 , +\blk00000003/sig00000353 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 }), + .PCOUT({\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b , +\blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , \blk00000003/sig00000370 , +\blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , \blk00000003/sig00000375 , +\blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , \blk00000003/sig0000037a , +\blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , \blk00000003/sig0000037f , +\blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 , \blk00000003/sig00000384 , +\blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , \blk00000003/sig00000389 , +\blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , \blk00000003/sig0000038e , +\blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , \blk00000003/sig00000393 , +\blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk000000f7 ( + .PATTERNBDETECT(\NLW_blk00000003/blk000000f7_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk000000f7_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk000000f7_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk000000f7_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk000000f7_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk000000f7_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk000000f7_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig000000ac , +\blk00000003/sig00000049 , \blk00000003/sig000000ac }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk000000f7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002c5 , \blk00000003/sig000002c6 , \blk00000003/sig000002c7 , \blk00000003/sig000002c8 , \blk00000003/sig000002c9 , +\blk00000003/sig000002ca , \blk00000003/sig000002cb , \blk00000003/sig000002cc , \blk00000003/sig000002cd , \blk00000003/sig000002ce , +\blk00000003/sig000002cf , \blk00000003/sig000002d0 , \blk00000003/sig000002d1 , \blk00000003/sig000002d2 , \blk00000003/sig000002d3 , +\blk00000003/sig000002d4 , \blk00000003/sig000002d5 , \blk00000003/sig000002d6 }), + .BCOUT({\NLW_blk00000003/blk000000f7_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk000000f7_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002d7 , \blk00000003/sig000002d7 , \blk00000003/sig000002d8 , \blk00000003/sig000002d9 , \blk00000003/sig000002da , +\blk00000003/sig000002db , \blk00000003/sig000002dc , \blk00000003/sig000002dd , \blk00000003/sig000002de , \blk00000003/sig000002df , +\blk00000003/sig000002e0 , \blk00000003/sig000002e1 , \blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , +\blk00000003/sig000002e5 , \blk00000003/sig000002e6 , \blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , +\blk00000003/sig000002ea , \blk00000003/sig000002eb , \blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee }), + .P({\NLW_blk00000003/blk000000f7_P<47>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<46>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<45>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<44>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<43>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<42>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<41>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<40>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<39>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<38>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<37>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<36>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<35>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<34>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<33>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<32>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<31>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<30>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<29>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<28>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<27>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<26>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<25>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<24>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<23>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<22>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<21>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<20>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<19>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<18>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<17>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<16>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<15>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<14>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<13>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<12>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<11>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<10>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<9>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<8>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<7>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<6>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<5>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<4>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<3>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<2>_UNCONNECTED , \NLW_blk00000003/blk000000f7_P<1>_UNCONNECTED , +\NLW_blk00000003/blk000000f7_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002ef , +\blk00000003/sig000002ef , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , \blk00000003/sig000002f1 , \blk00000003/sig000002f2 , +\blk00000003/sig000002f3 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 }), + .PCOUT({\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b , +\blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , \blk00000003/sig00000310 , +\blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , \blk00000003/sig00000315 , +\blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , \blk00000003/sig0000031a , +\blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , \blk00000003/sig0000031f , +\blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 , \blk00000003/sig00000324 , +\blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , \blk00000003/sig00000329 , +\blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , \blk00000003/sig0000032e , +\blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , \blk00000003/sig00000333 , +\blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .Q(\blk00000003/sig000002c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c1 ), + .Q(\blk00000003/sig000002b9 ) + ); + XORCY \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002bc ), + .LI(\blk00000003/sig000002bf ), + .O(\blk00000003/sig000002c0 ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bc ), + .DI(\blk00000003/sig000002be ), + .S(\blk00000003/sig000002bf ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig000002b9 ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bd ) + ); + MUXCY_L \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002b9 ), + .DI(\blk00000003/sig000002ba ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002bc ) + ); + MUXCY_L \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b8 ), + .S(\blk00000003/sig000002b2 ), + .LO(\blk00000003/sig000002b4 ) + ); + MUXCY_D \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002b4 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b5 ), + .O(\NLW_blk00000003/blk000000ee_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ee_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ed ( + .CI(\blk00000003/sig000002b4 ), + .LI(\blk00000003/sig000002b5 ), + .O(\blk00000003/sig000002b6 ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b2 ), + .O(\blk00000003/sig000002b3 ) + ); + MUXCY_L \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002a9 ), + .DI(\blk00000003/sig000002b1 ), + .S(\blk00000003/sig000002aa ), + .LO(\blk00000003/sig000002ac ) + ); + MUXCY_D \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002ac ), + .DI(\blk00000003/sig000002b0 ), + .S(\blk00000003/sig000002ad ), + .O(\NLW_blk00000003/blk000000ea_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000ea_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000002af ), + .O(\blk00000003/sig000002a9 ) + ); + XORCY \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002ac ), + .LI(\blk00000003/sig000002ad ), + .O(\blk00000003/sig000002ae ) + ); + XORCY \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002a9 ), + .LI(\blk00000003/sig000002aa ), + .O(\blk00000003/sig000002ab ) + ); + FDE \blk00000003/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a7 ), + .Q(\blk00000003/sig000002a8 ) + ); + MUXCY_L \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a6 ), + .S(\blk00000003/sig000002a0 ), + .LO(\blk00000003/sig000002a2 ) + ); + MUXCY_D \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002a2 ), + .DI(\blk00000003/sig000002a5 ), + .S(\blk00000003/sig000002a3 ), + .O(\NLW_blk00000003/blk000000e4_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e4_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig000002a2 ), + .LI(\blk00000003/sig000002a3 ), + .O(\blk00000003/sig000002a4 ) + ); + XORCY \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000002a1 ) + ); + MUXCY_L \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig00000299 ), + .DI(\blk00000003/sig000001e7 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig000001e6 ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000e0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e0_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig0000029f ), + .O(\blk00000003/sig00000299 ) + ); + XORCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig00000299 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000297 ), + .R(sclr), + .Q(\blk00000003/sig00000298 ) + ); + MUXCY_D \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000294 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000296 ), + .O(\NLW_blk00000003/blk000000db_O_UNCONNECTED ), + .LO(\blk00000003/sig00000297 ) + ); + MUXCY_D \blk00000003/blk000000da ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000295 ), + .O(\blk00000003/sig00000292 ), + .LO(\NLW_blk00000003/blk000000da_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d9 ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000293 ), + .O(\blk00000003/sig00000294 ), + .LO(\blk00000003/sig00000290 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000290 ), + .R(sclr), + .Q(\blk00000003/sig00000291 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000280 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig0000021c ), + .DI(\blk00000003/sig0000028e ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028b ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028b ), + .DI(\blk00000003/sig0000028c ), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000289 ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig00000289 ), + .DI(\blk00000003/sig0000027f ), + .S(\blk00000003/sig0000028a ), + .O(\blk00000003/sig00000286 ), + .LO(\NLW_blk00000003/blk000000d3_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig00000286 ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000284 ), + .LO(\NLW_blk00000003/blk000000d2_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig00000284 ), + .DI(\blk00000003/sig00000244 ), + .S(\blk00000003/sig00000285 ), + .O(\blk00000003/sig00000282 ), + .LO(\NLW_blk00000003/blk000000d1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000282 ), + .DI(\blk00000003/sig00000219 ), + .S(\blk00000003/sig00000283 ), + .O(\NLW_blk00000003/blk000000d0_O_UNCONNECTED ), + .LO(\blk00000003/sig00000280 ) + ); + XORCY \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000280 ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000281 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026f ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000027f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig000001cd ), + .DI(\blk00000003/sig0000027d ), + .S(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000027b ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig00000279 ), + .DI(\blk00000003/sig000001cd ), + .S(\blk00000003/sig0000027a ), + .O(\blk00000003/sig00000276 ), + .LO(\NLW_blk00000003/blk000000ca_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000276 ), + .DI(\blk00000003/sig00000277 ), + .S(\blk00000003/sig00000278 ), + .O(\blk00000003/sig00000274 ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000274 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000275 ), + .O(\blk00000003/sig00000270 ), + .LO(\NLW_blk00000003/blk000000c8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig00000272 ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000273 ), + .O(\NLW_blk00000003/blk000000c7_O_UNCONNECTED ), + .LO(\blk00000003/sig0000026e ) + ); + MUXCY_D \blk00000003/blk000000c6 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000239 ), + .S(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ), + .LO(\NLW_blk00000003/blk000000c6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c5 ( + .CI(\blk00000003/sig0000026e ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig0000026f ) + ); + FDE \blk00000003/blk000000c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026c ), + .Q(\blk00000003/sig0000026d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000026b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000263 ) + ); + XORCY \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig00000266 ), + .LI(\blk00000003/sig00000269 ), + .O(\blk00000003/sig0000026a ) + ); + MUXCY_D \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000266 ), + .DI(\blk00000003/sig00000268 ), + .S(\blk00000003/sig00000269 ), + .O(\NLW_blk00000003/blk000000c0_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c0_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000263 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000267 ) + ); + MUXCY_L \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000263 ), + .DI(\blk00000003/sig00000264 ), + .S(\blk00000003/sig00000265 ), + .LO(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bd ( + .CI(\blk00000003/sig0000025a ), + .DI(\blk00000003/sig00000262 ), + .S(\blk00000003/sig0000025b ), + .LO(\blk00000003/sig0000025d ) + ); + MUXCY_D \blk00000003/blk000000bc ( + .CI(\blk00000003/sig0000025d ), + .DI(\blk00000003/sig00000261 ), + .S(\blk00000003/sig0000025e ), + .O(\NLW_blk00000003/blk000000bc_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bc_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025a ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig0000025d ), + .LI(\blk00000003/sig0000025e ), + .O(\blk00000003/sig0000025f ) + ); + XORCY \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025a ), + .LI(\blk00000003/sig0000025b ), + .O(\blk00000003/sig0000025c ) + ); + MUXCY_L \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000259 ), + .S(\blk00000003/sig00000257 ), + .LO(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000257 ), + .O(\blk00000003/sig00000258 ) + ); + MUXCY_D \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000253 ), + .DI(\blk00000003/sig00000256 ), + .S(\blk00000003/sig00000254 ), + .O(\NLW_blk00000003/blk000000b6_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b6_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000253 ), + .LI(\blk00000003/sig00000254 ), + .O(\blk00000003/sig00000255 ) + ); + MUXCY_L \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000252 ), + .S(\blk00000003/sig00000250 ), + .LO(\blk00000003/sig0000024c ) + ); + XORCY \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000250 ), + .O(\blk00000003/sig00000251 ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024c ), + .DI(\blk00000003/sig0000024f ), + .S(\blk00000003/sig0000024d ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig0000024c ), + .LI(\blk00000003/sig0000024d ), + .O(\blk00000003/sig0000024e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000b0 ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e0 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig00000248 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000246 ), + .Q(\blk00000003/sig0000022f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023a ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021b ), + .Q(\blk00000003/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022e ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a1_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022c ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000228 ), + .R(coef_ld), + .Q(\blk00000003/sig00000227 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000224 ), + .R(coef_ld), + .Q(\blk00000003/sig00000222 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000237 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .Q(\blk00000003/sig00000232 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022f ), + .Q(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000098 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022d ), + .O(\NLW_blk00000003/blk00000098_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022e ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022a ), + .O(\blk00000003/sig0000022b ), + .LO(\blk00000003/sig0000022c ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\blk00000003/sig00000226 ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig00000226 ), + .DI(\blk00000003/sig00000227 ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig00000228 ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000225 ), + .O(\blk00000003/sig00000221 ), + .LO(\NLW_blk00000003/blk00000094_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig00000221 ), + .DI(\blk00000003/sig00000222 ), + .S(\blk00000003/sig00000223 ), + .O(\NLW_blk00000003/blk00000093_O_UNCONNECTED ), + .LO(\blk00000003/sig00000224 ) + ); + XORCY \blk00000003/blk00000092 ( + .CI(\blk00000003/sig0000021a ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig00000218 ) + ); + MUXCY_D \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig0000021f ), + .S(\blk00000003/sig00000220 ), + .O(\NLW_blk00000003/blk00000091_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig0000021b ), + .DI(\blk00000003/sig0000021c ), + .S(\blk00000003/sig0000021d ), + .O(\blk00000003/sig0000021e ), + .LO(\NLW_blk00000003/blk00000090_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000218 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000219 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000029 ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .R(sclr), + .Q(\blk00000003/sig000000b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e4 ), + .R(sclr), + .Q(\blk00000003/sig000001e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(\blk00000003/sig000001de ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(sclr), + .Q(\blk00000003/sig000001e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .R(\blk00000003/sig000001de ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .S(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDRE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cb ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c9 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\NLW_blk00000003/blk0000001a_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .R(sclr), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cd ), + .Q(\blk00000003/sig000001ce ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c1 ), + .R(sclr), + .Q(\blk00000003/sig000000bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000016_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bd ), + .S(sclr), + .Q(\blk00000003/sig000001cc ) + ); + MUXCY \blk00000003/blk00000014 ( + .CI(\blk00000003/sig000001c8 ), + .DI(\blk00000003/sig000000ac ), + .S(\blk00000003/sig000001ca ), + .O(\blk00000003/sig000001cb ) + ); + MUXCY_D \blk00000003/blk00000013 ( + .CI(\blk00000003/sig000001c6 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001c8 ), + .LO(\blk00000003/sig000001c9 ) + ); + MUXCY_D \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c3 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c4 ), + .O(\NLW_blk00000003/blk00000012_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c5 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000011 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000011_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000011_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000011_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000011_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000011_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000011_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000011_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000011_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000011_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000011_P<47>_UNCONNECTED , \blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , +\blk00000003/sig0000017f , \blk00000003/sig00000180 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , +\blk00000003/sig00000184 , \blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , +\blk00000003/sig00000189 , \blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , +\blk00000003/sig0000018e , \blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , +\blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , +\blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , +\blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , +\blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , +\blk00000003/sig000001a7 , \blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa }), + .A({\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ab , +\blk00000003/sig000001ab , \blk00000003/sig000001ab , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , +\blk00000003/sig000001af , \blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , +\blk00000003/sig000001b4 , \blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , +\blk00000003/sig000001b9 , \blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , +\blk00000003/sig000001be , \blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 }), + .PCOUT({\NLW_blk00000003/blk00000011_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000011_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000011_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000010 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000010_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk00000010_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000010_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000010_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000010_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000010_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000010_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b1 , \blk00000003/sig00000049 , \blk00000003/sig000000b5 , +\blk00000003/sig000000b3 , \blk00000003/sig000000b5 }), + .PCIN({\blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , \blk00000003/sig000000c7 , +\blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , \blk00000003/sig000000cc , +\blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , \blk00000003/sig000000db , +\blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , \blk00000003/sig000000e0 , +\blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , \blk00000003/sig000000e5 , +\blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , \blk00000003/sig000000ea , +\blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , \blk00000003/sig000000ef , +\blk00000003/sig000000f0 , \blk00000003/sig000000f1 , \blk00000003/sig000000f2 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000010_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ac , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , \blk00000003/sig000000f7 , +\blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , \blk00000003/sig000000fc , +\blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , \blk00000003/sig00000101 , +\blk00000003/sig00000102 , \blk00000003/sig00000103 , \blk00000003/sig00000104 }), + .BCOUT({\NLW_blk00000003/blk00000010_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\NLW_blk00000003/blk00000010_P<47>_UNCONNECTED , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , +\blk00000003/sig00000108 , \blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , +\blk00000003/sig0000010d , \blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , +\blk00000003/sig00000112 , \blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , +\blk00000003/sig00000117 , \blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , +\blk00000003/sig0000011c , \blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , +\blk00000003/sig00000121 , \blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , +\blk00000003/sig00000126 , \blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , +\blk00000003/sig0000012b , \blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , +\blk00000003/sig00000130 , \blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk00000010_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000010_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000010_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000f ( + .CI(\blk00000003/sig000000ac ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c2 ), + .O(\blk00000003/sig000000be ), + .LO(\NLW_blk00000003/blk0000000f_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000e ( + .CI(\blk00000003/sig000000be ), + .DI(\blk00000003/sig000000bf ), + .S(\blk00000003/sig000000c0 ), + .O(\blk00000003/sig000000b6 ), + .LO(\blk00000003/sig000000c1 ) + ); + XORCY \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000bc ), + .LI(\blk00000003/sig000000ac ), + .O(\blk00000003/sig000000bd ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000b9 ), + .DI(\blk00000003/sig000000ba ), + .S(\blk00000003/sig000000bb ), + .O(\NLW_blk00000003/blk0000000c_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000b6 ), + .DI(\blk00000003/sig000000b7 ), + .S(\blk00000003/sig000000b8 ), + .O(\blk00000003/sig000000b9 ), + .LO(\NLW_blk00000003/blk0000000b_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000000a ( + .C(clk), + .D(\blk00000003/sig000000b4 ), + .Q(\blk00000003/sig000000b5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000009 ( + .C(clk), + .D(\blk00000003/sig000000b2 ), + .Q(\blk00000003/sig000000b3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b0 ), + .Q(\blk00000003/sig000000b1 ) + ); + XORCY \blk00000003/blk00000007 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000af ) + ); + MUXCY_D \blk00000003/blk00000006 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ad ), + .S(\blk00000003/sig000000ae ), + .O(\NLW_blk00000003/blk00000006_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000006_LO_UNCONNECTED ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ac ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002b/blk0000008d ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002b/sig00000800 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fe ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000008a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ff ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000089 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000088 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000087 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000086 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000085 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000084 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000083 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000082 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000081 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000080 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000007a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000079 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000078 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000077 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000076 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000075 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000074 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000073 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000072 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000071 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000070 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006c ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006b ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000006a ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000069 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000068 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000067 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000066 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000065 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000064 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000063 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000062 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000061 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk00000060 ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005f ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005e ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002b/blk0000005d ( + .A0(\blk00000003/sig000001e7 ), + .A1(\blk00000003/sig000001e6 ), + .A2(\blk00000003/blk0000002b/sig000007cf ), + .A3(\blk00000003/blk0000002b/sig000007cf ), + .A4(\blk00000003/blk0000002b/sig000007cf ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001dc ), + .DPRA1(\blk00000003/sig000001da ), + .DPRA2(\blk00000003/blk0000002b/sig000007cf ), + .DPRA3(\blk00000003/blk0000002b/sig000007cf ), + .DPRA4(\blk00000003/blk0000002b/sig000007cf ), + .WCLK(clk), + .WE(\blk00000003/blk0000002b/sig00000800 ), + .SPO(\NLW_blk00000003/blk0000002b/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002b/sig000007d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ff ), + .Q(\blk00000003/sig000001e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fe ), + .Q(\blk00000003/sig000001e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fd ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fc ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fb ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007fa ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f9 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f8 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f7 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f6 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f5 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f4 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f3 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f2 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f1 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007f0 ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ef ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ee ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ed ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ec ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007eb ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007ea ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e9 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e8 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e7 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e6 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e5 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e4 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e3 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e2 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e1 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007e0 ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007df ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007de ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dd ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007dc ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007db ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007da ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d9 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d8 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d7 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d6 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d5 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d4 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d3 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d2 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d1 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002b/sig000007d0 ), + .Q(\blk00000003/sig00000217 ) + ); + GND \blk00000003/blk0000002b/blk0000002c ( + .G(\blk00000003/blk0000002b/sig000007cf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000117/blk00000149 ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk00000117/sig0000084f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000148 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk00000117/sig0000084d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000147 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk00000117/sig0000084c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000146 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk00000117/sig0000084e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000145 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk00000117/sig0000084a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000144 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk00000117/sig00000849 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000143 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk00000117/sig0000084b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000142 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000117/sig00000847 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000141 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000117/sig00000846 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000140 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000117/sig00000848 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000117/sig00000844 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000117/sig00000843 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000117/sig00000845 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000117/sig00000841 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000117/sig00000840 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000013a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000117/sig00000842 ), + .Q15(\NLW_blk00000003/blk00000117/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000139 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000117/sig0000083e ), + .Q15(\NLW_blk00000003/blk00000117/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000138 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000117/sig0000083d ), + .Q15(\NLW_blk00000003/blk00000117/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000137 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000117/sig0000083f ), + .Q15(\NLW_blk00000003/blk00000117/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000136 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000117/sig0000083b ), + .Q15(\NLW_blk00000003/blk00000117/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000135 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000117/sig0000083a ), + .Q15(\NLW_blk00000003/blk00000117/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000134 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000117/sig0000083c ), + .Q15(\NLW_blk00000003/blk00000117/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000133 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000117/sig00000838 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000133_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000132 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000117/sig00000837 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000132_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk00000131 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk00000117/sig00000836 ), + .A3(\blk00000003/blk00000117/sig00000836 ), + .CE(\blk00000003/blk00000117/sig0000084f ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000117/sig00000839 ), + .Q15(\NLW_blk00000003/blk00000117/blk00000131_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084e ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084d ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084c ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084b ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000084a ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000849 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000848 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000847 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000846 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000845 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000844 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000843 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000842 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000841 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000840 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083f ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083e ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083d ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083c ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083b ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig0000083a ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000839 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000838 ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000117/sig00000837 ), + .Q(\blk00000003/sig000003f0 ) + ); + GND \blk00000003/blk00000117/blk00000118 ( + .G(\blk00000003/blk00000117/sig00000836 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014a/blk0000017c ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk0000014a/sig0000089e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f8 ), + .Q(\blk00000003/blk0000014a/sig0000089c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000017a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f9 ), + .Q(\blk00000003/blk0000014a/sig0000089b ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000179 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004f7 ), + .Q(\blk00000003/blk0000014a/sig0000089d ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000178 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fb ), + .Q(\blk00000003/blk0000014a/sig00000899 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000177 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fc ), + .Q(\blk00000003/blk0000014a/sig00000898 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000176 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fa ), + .Q(\blk00000003/blk0000014a/sig0000089a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000175 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fe ), + .Q(\blk00000003/blk0000014a/sig00000896 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000174 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004ff ), + .Q(\blk00000003/blk0000014a/sig00000895 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000173 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig000004fd ), + .Q(\blk00000003/blk0000014a/sig00000897 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000172 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000501 ), + .Q(\blk00000003/blk0000014a/sig00000893 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000171 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/blk0000014a/sig00000892 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000170 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000500 ), + .Q(\blk00000003/blk0000014a/sig00000894 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016f ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000504 ), + .Q(\blk00000003/blk0000014a/sig00000890 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016e ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000505 ), + .Q(\blk00000003/blk0000014a/sig0000088f ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016d ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000503 ), + .Q(\blk00000003/blk0000014a/sig00000891 ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016c ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000507 ), + .Q(\blk00000003/blk0000014a/sig0000088d ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016b ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000508 ), + .Q(\blk00000003/blk0000014a/sig0000088c ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk0000016a ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000506 ), + .Q(\blk00000003/blk0000014a/sig0000088e ), + .Q15(\NLW_blk00000003/blk0000014a/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000169 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050a ), + .Q(\blk00000003/blk0000014a/sig0000088a ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000168 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050b ), + .Q(\blk00000003/blk0000014a/sig00000889 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000167 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig00000509 ), + .Q(\blk00000003/blk0000014a/sig0000088b ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000166 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050d ), + .Q(\blk00000003/blk0000014a/sig00000887 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000166_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000165 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050e ), + .Q(\blk00000003/blk0000014a/sig00000886 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000165_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014a/blk00000164 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk0000014a/sig00000885 ), + .A3(\blk00000003/blk0000014a/sig00000885 ), + .CE(\blk00000003/blk0000014a/sig0000089e ), + .CLK(clk), + .D(\blk00000003/sig0000050c ), + .Q(\blk00000003/blk0000014a/sig00000888 ), + .Q15(\NLW_blk00000003/blk0000014a/blk00000164_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089d ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089c ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089b ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000089a ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000899 ), + .Q(\blk00000003/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000898 ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000897 ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000896 ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000895 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000894 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000893 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000892 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000891 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000890 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088f ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088e ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088d ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088c ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088b ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig0000088a ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000889 ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000888 ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000887 ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014a/blk0000014c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014a/sig00000886 ), + .Q(\blk00000003/sig00000408 ) + ); + GND \blk00000003/blk0000014a/blk0000014b ( + .G(\blk00000003/blk0000014a/sig00000885 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017d/blk000001af ( + .I0(ce), + .I1(\blk00000003/sig000004e6 ), + .O(\blk00000003/blk0000017d/sig000008ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ae ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000017d/sig000008eb ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ad ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000017d/sig000008ea ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ac ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000017d/sig000008ec ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001ab ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000017d/sig000008e8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001aa ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000017d/sig000008e7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a9 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000017d/sig000008e9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a8 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000017d/sig000008e5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a7 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000017d/sig000008e4 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a6 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000017d/sig000008e6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a5 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000017d/sig000008e2 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a4 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000017d/sig000008e1 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a3 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000017d/sig000008e3 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a2 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000017d/sig000008df ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a1 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000017d/sig000008de ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk000001a0 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000017d/sig000008e0 ), + .Q15(\NLW_blk00000003/blk0000017d/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019f ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000017d/sig000008dc ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019e ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000017d/sig000008db ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019d ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000017d/sig000008dd ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019c ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000017d/sig000008d9 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019b ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000017d/sig000008d8 ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk0000019a ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000017d/sig000008da ), + .Q15(\NLW_blk00000003/blk0000017d/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000199 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000017d/sig000008d6 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000199_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000198 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000017d/sig000008d5 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000198_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017d/blk00000197 ( + .A0(\blk00000003/sig000004f4 ), + .A1(\blk00000003/sig000004f2 ), + .A2(\blk00000003/blk0000017d/sig000008d4 ), + .A3(\blk00000003/blk0000017d/sig000008d4 ), + .CE(\blk00000003/blk0000017d/sig000008ed ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000017d/sig000008d7 ), + .Q15(\NLW_blk00000003/blk0000017d/blk00000197_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ec ), + .Q(\blk00000003/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008eb ), + .Q(\blk00000003/sig0000043a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008ea ), + .Q(\blk00000003/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e9 ), + .Q(\blk00000003/sig0000043c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e8 ), + .Q(\blk00000003/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e7 ), + .Q(\blk00000003/sig0000043e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e6 ), + .Q(\blk00000003/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e5 ), + .Q(\blk00000003/sig00000440 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e4 ), + .Q(\blk00000003/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e3 ), + .Q(\blk00000003/sig00000442 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e2 ), + .Q(\blk00000003/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e1 ), + .Q(\blk00000003/sig00000444 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008e0 ), + .Q(\blk00000003/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008df ), + .Q(\blk00000003/sig00000446 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008de ), + .Q(\blk00000003/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dd ), + .Q(\blk00000003/sig00000448 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008dc ), + .Q(\blk00000003/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008db ), + .Q(\blk00000003/sig0000044a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008da ), + .Q(\blk00000003/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d9 ), + .Q(\blk00000003/sig0000044c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d8 ), + .Q(\blk00000003/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d7 ), + .Q(\blk00000003/sig0000044e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk00000180 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d6 ), + .Q(\blk00000003/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017d/blk0000017f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017d/sig000008d5 ), + .Q(\blk00000003/sig00000450 ) + ); + GND \blk00000003/blk0000017d/blk0000017e ( + .G(\blk00000003/blk0000017d/sig000008d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b0/blk000001e2 ( + .I0(ce), + .I1(\blk00000003/sig000004e4 ), + .O(\blk00000003/blk000001b0/sig0000093c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000510 ), + .Q(\blk00000003/blk000001b0/sig0000093a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001e0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000511 ), + .Q(\blk00000003/blk000001b0/sig00000939 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001df ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000050f ), + .Q(\blk00000003/blk000001b0/sig0000093b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001de ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000513 ), + .Q(\blk00000003/blk000001b0/sig00000937 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000514 ), + .Q(\blk00000003/blk000001b0/sig00000936 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001dc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000512 ), + .Q(\blk00000003/blk000001b0/sig00000938 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001db ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000516 ), + .Q(\blk00000003/blk000001b0/sig00000934 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001da ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000517 ), + .Q(\blk00000003/blk000001b0/sig00000933 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d9 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000515 ), + .Q(\blk00000003/blk000001b0/sig00000935 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d8 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000519 ), + .Q(\blk00000003/blk000001b0/sig00000931 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d7 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051a ), + .Q(\blk00000003/blk000001b0/sig00000930 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d6 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000518 ), + .Q(\blk00000003/blk000001b0/sig00000932 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d5 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051c ), + .Q(\blk00000003/blk000001b0/sig0000092e ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d4 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051d ), + .Q(\blk00000003/blk000001b0/sig0000092d ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d3 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051b ), + .Q(\blk00000003/blk000001b0/sig0000092f ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d2 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051f ), + .Q(\blk00000003/blk000001b0/sig0000092b ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d1 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000520 ), + .Q(\blk00000003/blk000001b0/sig0000092a ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001d0 ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig0000051e ), + .Q(\blk00000003/blk000001b0/sig0000092c ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cf ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000522 ), + .Q(\blk00000003/blk000001b0/sig00000928 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ce ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000523 ), + .Q(\blk00000003/blk000001b0/sig00000927 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cd ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000521 ), + .Q(\blk00000003/blk000001b0/sig00000929 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cc ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000525 ), + .Q(\blk00000003/blk000001b0/sig00000925 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001cb ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000526 ), + .Q(\blk00000003/blk000001b0/sig00000924 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b0/blk000001ca ( + .A0(\blk00000003/sig000004f0 ), + .A1(\blk00000003/sig000004ee ), + .A2(\blk00000003/blk000001b0/sig00000923 ), + .A3(\blk00000003/blk000001b0/sig00000923 ), + .CE(\blk00000003/blk000001b0/sig0000093c ), + .CLK(clk), + .D(\blk00000003/sig00000524 ), + .Q(\blk00000003/blk000001b0/sig00000926 ), + .Q15(\NLW_blk00000003/blk000001b0/blk000001ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093b ), + .Q(\blk00000003/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000093a ), + .Q(\blk00000003/sig00000452 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000939 ), + .Q(\blk00000003/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000938 ), + .Q(\blk00000003/sig00000454 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000937 ), + .Q(\blk00000003/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000936 ), + .Q(\blk00000003/sig00000456 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000935 ), + .Q(\blk00000003/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000934 ), + .Q(\blk00000003/sig00000458 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000933 ), + .Q(\blk00000003/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000932 ), + .Q(\blk00000003/sig0000045a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000931 ), + .Q(\blk00000003/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000930 ), + .Q(\blk00000003/sig0000045c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092f ), + .Q(\blk00000003/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092e ), + .Q(\blk00000003/sig0000045e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092d ), + .Q(\blk00000003/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092c ), + .Q(\blk00000003/sig00000460 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092b ), + .Q(\blk00000003/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig0000092a ), + .Q(\blk00000003/sig00000462 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000929 ), + .Q(\blk00000003/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000928 ), + .Q(\blk00000003/sig00000464 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000927 ), + .Q(\blk00000003/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000926 ), + .Q(\blk00000003/sig00000466 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000925 ), + .Q(\blk00000003/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b0/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b0/sig00000924 ), + .Q(\blk00000003/sig00000468 ) + ); + GND \blk00000003/blk000001b0/blk000001b1 ( + .G(\blk00000003/blk000001b0/sig00000923 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e3/blk00000215 ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk000001e3/sig0000098b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000214 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/blk000001e3/sig00000989 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000213 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d9 ), + .Q(\blk00000003/blk000001e3/sig00000988 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000212 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002d7 ), + .Q(\blk00000003/blk000001e3/sig0000098a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000211 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002db ), + .Q(\blk00000003/blk000001e3/sig00000986 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000210 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/blk000001e3/sig00000985 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/blk000001e3/sig00000987 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/blk000001e3/sig00000983 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/blk000001e3/sig00000982 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002dd ), + .Q(\blk00000003/blk000001e3/sig00000984 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e1 ), + .Q(\blk00000003/blk000001e3/sig00000980 ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk0000020a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/blk000001e3/sig0000097f ), + .Q15(\NLW_blk00000003/blk000001e3/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000209 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/blk000001e3/sig00000981 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000208 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/blk000001e3/sig0000097d ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000207 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e5 ), + .Q(\blk00000003/blk000001e3/sig0000097c ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000206 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e3 ), + .Q(\blk00000003/blk000001e3/sig0000097e ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000205 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e7 ), + .Q(\blk00000003/blk000001e3/sig0000097a ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000204 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/blk000001e3/sig00000979 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000203 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/blk000001e3/sig0000097b ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000202 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/blk000001e3/sig00000977 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000201 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002eb ), + .Q(\blk00000003/blk000001e3/sig00000976 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk00000200 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002e9 ), + .Q(\blk00000003/blk000001e3/sig00000978 ), + .Q15(\NLW_blk00000003/blk000001e3/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001ff ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ed ), + .Q(\blk00000003/blk000001e3/sig00000974 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fe ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/blk000001e3/sig00000973 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e3/blk000001fd ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk000001e3/sig00000972 ), + .A3(\blk00000003/blk000001e3/sig00000972 ), + .CE(\blk00000003/blk000001e3/sig0000098b ), + .CLK(clk), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/blk000001e3/sig00000975 ), + .Q15(\NLW_blk00000003/blk000001e3/blk000001fd_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000098a ), + .Q(\blk00000003/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000989 ), + .Q(\blk00000003/sig0000047c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000988 ), + .Q(\blk00000003/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000987 ), + .Q(\blk00000003/sig0000047e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000986 ), + .Q(\blk00000003/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000985 ), + .Q(\blk00000003/sig00000480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000984 ), + .Q(\blk00000003/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000983 ), + .Q(\blk00000003/sig00000482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000982 ), + .Q(\blk00000003/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000981 ), + .Q(\blk00000003/sig00000484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000980 ), + .Q(\blk00000003/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097f ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097e ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097c ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097b ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig0000097a ), + .Q(\blk00000003/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000979 ), + .Q(\blk00000003/sig0000048c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000978 ), + .Q(\blk00000003/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000977 ), + .Q(\blk00000003/sig0000048e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000976 ), + .Q(\blk00000003/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000975 ), + .Q(\blk00000003/sig00000490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000974 ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e3/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e3/sig00000973 ), + .Q(\blk00000003/sig00000492 ) + ); + GND \blk00000003/blk000001e3/blk000001e4 ( + .G(\blk00000003/blk000001e3/sig00000972 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000216/blk00000248 ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk00000216/sig000009da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000247 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000528 ), + .Q(\blk00000003/blk00000216/sig000009d8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000246 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000529 ), + .Q(\blk00000003/blk00000216/sig000009d7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000245 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000527 ), + .Q(\blk00000003/blk00000216/sig000009d9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000244 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052b ), + .Q(\blk00000003/blk00000216/sig000009d5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000243 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052c ), + .Q(\blk00000003/blk00000216/sig000009d4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000242 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052a ), + .Q(\blk00000003/blk00000216/sig000009d6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000241 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052e ), + .Q(\blk00000003/blk00000216/sig000009d2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000240 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052f ), + .Q(\blk00000003/blk00000216/sig000009d1 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000052d ), + .Q(\blk00000003/blk00000216/sig000009d3 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000531 ), + .Q(\blk00000003/blk00000216/sig000009cf ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000532 ), + .Q(\blk00000003/blk00000216/sig000009ce ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000530 ), + .Q(\blk00000003/blk00000216/sig000009d0 ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000534 ), + .Q(\blk00000003/blk00000216/sig000009cc ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk0000023a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000535 ), + .Q(\blk00000003/blk00000216/sig000009cb ), + .Q15(\NLW_blk00000003/blk00000216/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000239 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000533 ), + .Q(\blk00000003/blk00000216/sig000009cd ), + .Q15(\NLW_blk00000003/blk00000216/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000238 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000537 ), + .Q(\blk00000003/blk00000216/sig000009c9 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000237 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000538 ), + .Q(\blk00000003/blk00000216/sig000009c8 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000236 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000536 ), + .Q(\blk00000003/blk00000216/sig000009ca ), + .Q15(\NLW_blk00000003/blk00000216/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000235 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053a ), + .Q(\blk00000003/blk00000216/sig000009c6 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000234 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053b ), + .Q(\blk00000003/blk00000216/sig000009c5 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000233 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig00000539 ), + .Q(\blk00000003/blk00000216/sig000009c7 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000232 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053d ), + .Q(\blk00000003/blk00000216/sig000009c3 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000232_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000231 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053e ), + .Q(\blk00000003/blk00000216/sig000009c2 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000231_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000216/blk00000230 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk00000216/sig000009c1 ), + .A3(\blk00000003/blk00000216/sig000009c1 ), + .CE(\blk00000003/blk00000216/sig000009da ), + .CLK(clk), + .D(\blk00000003/sig0000053c ), + .Q(\blk00000003/blk00000216/sig000009c4 ), + .Q15(\NLW_blk00000003/blk00000216/blk00000230_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d9 ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d8 ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d7 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d6 ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d5 ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d4 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d3 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d2 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d1 ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009d0 ), + .Q(\blk00000003/sig0000049c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cf ), + .Q(\blk00000003/sig0000049d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ce ), + .Q(\blk00000003/sig0000049e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cd ), + .Q(\blk00000003/sig0000049f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cc ), + .Q(\blk00000003/sig000004a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009cb ), + .Q(\blk00000003/sig000004a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009ca ), + .Q(\blk00000003/sig000004a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c9 ), + .Q(\blk00000003/sig000004a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c8 ), + .Q(\blk00000003/sig000004a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c7 ), + .Q(\blk00000003/sig000004a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c6 ), + .Q(\blk00000003/sig000004a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c5 ), + .Q(\blk00000003/sig000004a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c4 ), + .Q(\blk00000003/sig000004a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c3 ), + .Q(\blk00000003/sig000004a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000216/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000216/sig000009c2 ), + .Q(\blk00000003/sig000004aa ) + ); + GND \blk00000003/blk00000216/blk00000217 ( + .G(\blk00000003/blk00000216/sig000009c1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000249/blk0000027b ( + .I0(ce), + .I1(\blk00000003/sig000004e5 ), + .O(\blk00000003/blk00000249/sig00000a29 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000027a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000338 ), + .Q(\blk00000003/blk00000249/sig00000a27 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000279 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000339 ), + .Q(\blk00000003/blk00000249/sig00000a26 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000278 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000337 ), + .Q(\blk00000003/blk00000249/sig00000a28 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000277 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033b ), + .Q(\blk00000003/blk00000249/sig00000a24 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000276 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033c ), + .Q(\blk00000003/blk00000249/sig00000a23 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000275 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033a ), + .Q(\blk00000003/blk00000249/sig00000a25 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000274 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033e ), + .Q(\blk00000003/blk00000249/sig00000a21 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000273 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033f ), + .Q(\blk00000003/blk00000249/sig00000a20 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000272 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000033d ), + .Q(\blk00000003/blk00000249/sig00000a22 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000271 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000341 ), + .Q(\blk00000003/blk00000249/sig00000a1e ), + .Q15(\NLW_blk00000003/blk00000249/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000270 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000342 ), + .Q(\blk00000003/blk00000249/sig00000a1d ), + .Q15(\NLW_blk00000003/blk00000249/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026f ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000340 ), + .Q(\blk00000003/blk00000249/sig00000a1f ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026e ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000344 ), + .Q(\blk00000003/blk00000249/sig00000a1b ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026d ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000345 ), + .Q(\blk00000003/blk00000249/sig00000a1a ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026c ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000343 ), + .Q(\blk00000003/blk00000249/sig00000a1c ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026b ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000347 ), + .Q(\blk00000003/blk00000249/sig00000a18 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk0000026a ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000348 ), + .Q(\blk00000003/blk00000249/sig00000a17 ), + .Q15(\NLW_blk00000003/blk00000249/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000269 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000346 ), + .Q(\blk00000003/blk00000249/sig00000a19 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000268 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034a ), + .Q(\blk00000003/blk00000249/sig00000a15 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000267 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034b ), + .Q(\blk00000003/blk00000249/sig00000a14 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000266 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig00000349 ), + .Q(\blk00000003/blk00000249/sig00000a16 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000265 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034d ), + .Q(\blk00000003/blk00000249/sig00000a12 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000265_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000264 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034e ), + .Q(\blk00000003/blk00000249/sig00000a11 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000264_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000249/blk00000263 ( + .A0(\blk00000003/sig000004f3 ), + .A1(\blk00000003/sig000004f1 ), + .A2(\blk00000003/blk00000249/sig00000a10 ), + .A3(\blk00000003/blk00000249/sig00000a10 ), + .CE(\blk00000003/blk00000249/sig00000a29 ), + .CLK(clk), + .D(\blk00000003/sig0000034c ), + .Q(\blk00000003/blk00000249/sig00000a13 ), + .Q15(\NLW_blk00000003/blk00000249/blk00000263_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a28 ), + .Q(\blk00000003/sig000004ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a27 ), + .Q(\blk00000003/sig000004ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a26 ), + .Q(\blk00000003/sig000004ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a25 ), + .Q(\blk00000003/sig000004ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a24 ), + .Q(\blk00000003/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a23 ), + .Q(\blk00000003/sig000004b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a22 ), + .Q(\blk00000003/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a21 ), + .Q(\blk00000003/sig000004b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a20 ), + .Q(\blk00000003/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1f ), + .Q(\blk00000003/sig000004b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1e ), + .Q(\blk00000003/sig000004b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1d ), + .Q(\blk00000003/sig000004b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1c ), + .Q(\blk00000003/sig000004b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1b ), + .Q(\blk00000003/sig000004b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a1a ), + .Q(\blk00000003/sig000004b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a19 ), + .Q(\blk00000003/sig000004ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a18 ), + .Q(\blk00000003/sig000004bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a17 ), + .Q(\blk00000003/sig000004bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a16 ), + .Q(\blk00000003/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a15 ), + .Q(\blk00000003/sig000004be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a14 ), + .Q(\blk00000003/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a13 ), + .Q(\blk00000003/sig000004c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a12 ), + .Q(\blk00000003/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000249/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000249/sig00000a11 ), + .Q(\blk00000003/sig000004c2 ) + ); + GND \blk00000003/blk00000249/blk0000024a ( + .G(\blk00000003/blk00000249/sig00000a10 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027c/blk000002ae ( + .I0(ce), + .I1(\blk00000003/sig000004e3 ), + .O(\blk00000003/blk0000027c/sig00000a78 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ad ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000540 ), + .Q(\blk00000003/blk0000027c/sig00000a76 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ac ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000541 ), + .Q(\blk00000003/blk0000027c/sig00000a75 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002ab ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000053f ), + .Q(\blk00000003/blk0000027c/sig00000a77 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002aa ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000543 ), + .Q(\blk00000003/blk0000027c/sig00000a73 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a9 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000544 ), + .Q(\blk00000003/blk0000027c/sig00000a72 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a8 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000542 ), + .Q(\blk00000003/blk0000027c/sig00000a74 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a7 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000546 ), + .Q(\blk00000003/blk0000027c/sig00000a70 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a6 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000547 ), + .Q(\blk00000003/blk0000027c/sig00000a6f ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a5 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000545 ), + .Q(\blk00000003/blk0000027c/sig00000a71 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a4 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000549 ), + .Q(\blk00000003/blk0000027c/sig00000a6d ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a3 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054a ), + .Q(\blk00000003/blk0000027c/sig00000a6c ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a2 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000548 ), + .Q(\blk00000003/blk0000027c/sig00000a6e ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a1 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054c ), + .Q(\blk00000003/blk0000027c/sig00000a6a ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk000002a0 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054d ), + .Q(\blk00000003/blk0000027c/sig00000a69 ), + .Q15(\NLW_blk00000003/blk0000027c/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029f ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054b ), + .Q(\blk00000003/blk0000027c/sig00000a6b ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029e ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054f ), + .Q(\blk00000003/blk0000027c/sig00000a67 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029d ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000550 ), + .Q(\blk00000003/blk0000027c/sig00000a66 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029c ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig0000054e ), + .Q(\blk00000003/blk0000027c/sig00000a68 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029b ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000552 ), + .Q(\blk00000003/blk0000027c/sig00000a64 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk0000029a ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000553 ), + .Q(\blk00000003/blk0000027c/sig00000a63 ), + .Q15(\NLW_blk00000003/blk0000027c/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000299 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000551 ), + .Q(\blk00000003/blk0000027c/sig00000a65 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000298 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000555 ), + .Q(\blk00000003/blk0000027c/sig00000a61 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000298_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000297 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000556 ), + .Q(\blk00000003/blk0000027c/sig00000a60 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000297_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027c/blk00000296 ( + .A0(\blk00000003/sig000004ef ), + .A1(\blk00000003/sig000004ed ), + .A2(\blk00000003/blk0000027c/sig00000a5f ), + .A3(\blk00000003/blk0000027c/sig00000a5f ), + .CE(\blk00000003/blk0000027c/sig00000a78 ), + .CLK(clk), + .D(\blk00000003/sig00000554 ), + .Q(\blk00000003/blk0000027c/sig00000a62 ), + .Q15(\NLW_blk00000003/blk0000027c/blk00000296_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a77 ), + .Q(\blk00000003/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a76 ), + .Q(\blk00000003/sig000004c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a75 ), + .Q(\blk00000003/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a74 ), + .Q(\blk00000003/sig000004c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a73 ), + .Q(\blk00000003/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a72 ), + .Q(\blk00000003/sig000004c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a71 ), + .Q(\blk00000003/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a70 ), + .Q(\blk00000003/sig000004ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6f ), + .Q(\blk00000003/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6e ), + .Q(\blk00000003/sig000004cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6d ), + .Q(\blk00000003/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6c ), + .Q(\blk00000003/sig000004ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6b ), + .Q(\blk00000003/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a6a ), + .Q(\blk00000003/sig000004d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a69 ), + .Q(\blk00000003/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a68 ), + .Q(\blk00000003/sig000004d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a67 ), + .Q(\blk00000003/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a66 ), + .Q(\blk00000003/sig000004d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a65 ), + .Q(\blk00000003/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a64 ), + .Q(\blk00000003/sig000004d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a63 ), + .Q(\blk00000003/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a62 ), + .Q(\blk00000003/sig000004d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a61 ), + .Q(\blk00000003/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027c/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027c/sig00000a60 ), + .Q(\blk00000003/sig000004da ) + ); + GND \blk00000003/blk0000027c/blk0000027d ( + .G(\blk00000003/blk0000027c/sig00000a5f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002af/blk000002e1 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk000002af/sig00000ac7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002e0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000558 ), + .Q(\blk00000003/blk000002af/sig00000ac5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002df ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000559 ), + .Q(\blk00000003/blk000002af/sig00000ac4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002de ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000557 ), + .Q(\blk00000003/blk000002af/sig00000ac6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055b ), + .Q(\blk00000003/blk000002af/sig00000ac2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002dc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055c ), + .Q(\blk00000003/blk000002af/sig00000ac1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002db ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055a ), + .Q(\blk00000003/blk000002af/sig00000ac3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002da ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055e ), + .Q(\blk00000003/blk000002af/sig00000abf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055f ), + .Q(\blk00000003/blk000002af/sig00000abe ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d8 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000055d ), + .Q(\blk00000003/blk000002af/sig00000ac0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d7 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000561 ), + .Q(\blk00000003/blk000002af/sig00000abc ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d6 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000562 ), + .Q(\blk00000003/blk000002af/sig00000abb ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d5 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000560 ), + .Q(\blk00000003/blk000002af/sig00000abd ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d4 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000564 ), + .Q(\blk00000003/blk000002af/sig00000ab9 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d3 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000565 ), + .Q(\blk00000003/blk000002af/sig00000ab8 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d2 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000563 ), + .Q(\blk00000003/blk000002af/sig00000aba ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d1 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000567 ), + .Q(\blk00000003/blk000002af/sig00000ab6 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002d0 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk000002af/sig00000ab5 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cf ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000566 ), + .Q(\blk00000003/blk000002af/sig00000ab7 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ce ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk000002af/sig00000ab3 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cd ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056b ), + .Q(\blk00000003/blk000002af/sig00000ab2 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cc ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig00000569 ), + .Q(\blk00000003/blk000002af/sig00000ab4 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002cb ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056d ), + .Q(\blk00000003/blk000002af/sig00000ab0 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002cb_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002ca ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk000002af/sig00000aaf ), + .Q15(\NLW_blk00000003/blk000002af/blk000002ca_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002af/blk000002c9 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk000002af/sig00000aae ), + .A3(\blk00000003/blk000002af/sig00000aae ), + .CE(\blk00000003/blk000002af/sig00000ac7 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk000002af/sig00000ab1 ), + .Q15(\NLW_blk00000003/blk000002af/blk000002c9_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac6 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac5 ), + .Q(\blk00000003/sig000002d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac4 ), + .Q(\blk00000003/sig000002d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac3 ), + .Q(\blk00000003/sig000002da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac2 ), + .Q(\blk00000003/sig000002db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac1 ), + .Q(\blk00000003/sig000002dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ac0 ), + .Q(\blk00000003/sig000002dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abf ), + .Q(\blk00000003/sig000002de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abe ), + .Q(\blk00000003/sig000002df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abd ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abc ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000abb ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aba ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab9 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab8 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab7 ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab6 ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab5 ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab4 ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab3 ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab2 ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab1 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000ab0 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002af/blk000002b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002af/sig00000aaf ), + .Q(\blk00000003/sig000002ee ) + ); + GND \blk00000003/blk000002af/blk000002b0 ( + .G(\blk00000003/blk000002af/sig00000aae ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002e2/blk00000314 ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk000002e2/sig00000b16 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000313 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000570 ), + .Q(\blk00000003/blk000002e2/sig00000b14 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000313_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000312 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000571 ), + .Q(\blk00000003/blk000002e2/sig00000b13 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000312_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000311 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000056f ), + .Q(\blk00000003/blk000002e2/sig00000b15 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000311_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000310 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000573 ), + .Q(\blk00000003/blk000002e2/sig00000b11 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000310_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000574 ), + .Q(\blk00000003/blk000002e2/sig00000b10 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000572 ), + .Q(\blk00000003/blk000002e2/sig00000b12 ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000576 ), + .Q(\blk00000003/blk000002e2/sig00000b0e ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000577 ), + .Q(\blk00000003/blk000002e2/sig00000b0d ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000575 ), + .Q(\blk00000003/blk000002e2/sig00000b0f ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk0000030a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000579 ), + .Q(\blk00000003/blk000002e2/sig00000b0b ), + .Q15(\NLW_blk00000003/blk000002e2/blk0000030a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000309 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057a ), + .Q(\blk00000003/blk000002e2/sig00000b0a ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000309_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000308 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000578 ), + .Q(\blk00000003/blk000002e2/sig00000b0c ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000308_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000307 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057c ), + .Q(\blk00000003/blk000002e2/sig00000b08 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000307_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000306 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057d ), + .Q(\blk00000003/blk000002e2/sig00000b07 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000306_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000305 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057b ), + .Q(\blk00000003/blk000002e2/sig00000b09 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000305_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000304 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057f ), + .Q(\blk00000003/blk000002e2/sig00000b05 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000304_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000303 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000580 ), + .Q(\blk00000003/blk000002e2/sig00000b04 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000303_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000302 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig0000057e ), + .Q(\blk00000003/blk000002e2/sig00000b06 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000302_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000301 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000582 ), + .Q(\blk00000003/blk000002e2/sig00000b02 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000301_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk00000300 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000583 ), + .Q(\blk00000003/blk000002e2/sig00000b01 ), + .Q15(\NLW_blk00000003/blk000002e2/blk00000300_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002ff ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000581 ), + .Q(\blk00000003/blk000002e2/sig00000b03 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002ff_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fe ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000585 ), + .Q(\blk00000003/blk000002e2/sig00000aff ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fe_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fd ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000586 ), + .Q(\blk00000003/blk000002e2/sig00000afe ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000002e2/blk000002fc ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk000002e2/sig00000afd ), + .A3(\blk00000003/blk000002e2/sig00000afd ), + .CE(\blk00000003/blk000002e2/sig00000b16 ), + .CLK(clk), + .D(\blk00000003/sig00000584 ), + .Q(\blk00000003/blk000002e2/sig00000b00 ), + .Q15(\NLW_blk00000003/blk000002e2/blk000002fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b15 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b14 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b13 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b12 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b11 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b10 ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0f ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0e ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0d ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0c ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0b ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b0a ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b09 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b08 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b07 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b06 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b05 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b04 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b03 ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b02 ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b01 ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000b00 ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000aff ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002e2/sig00000afe ), + .Q(\blk00000003/sig00000306 ) + ); + GND \blk00000003/blk000002e2/blk000002e3 ( + .G(\blk00000003/blk000002e2/sig00000afd ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000315/blk00000347 ( + .I0(ce), + .I1(\blk00000003/sig000004f6 ), + .O(\blk00000003/blk00000315/sig00000b65 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000346 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/blk00000315/sig00000b63 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000346_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000345 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/blk00000315/sig00000b62 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000345_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000344 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/blk00000315/sig00000b64 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000344_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000343 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/blk00000315/sig00000b60 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000343_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000342 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/blk00000315/sig00000b5f ), + .Q15(\NLW_blk00000003/blk00000315/blk00000342_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000341 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/blk00000315/sig00000b61 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000341_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000340 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/blk00000315/sig00000b5d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000340_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/blk00000315/sig00000b5c ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033e ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/blk00000315/sig00000b5e ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033d ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/blk00000315/sig00000b5a ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033c ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/blk00000315/sig00000b59 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033b ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/blk00000315/sig00000b5b ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000033a ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/blk00000315/sig00000b57 ), + .Q15(\NLW_blk00000003/blk00000315/blk0000033a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000339 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/blk00000315/sig00000b56 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000339_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000338 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/blk00000315/sig00000b58 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000338_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000337 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/blk00000315/sig00000b54 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000337_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000336 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/blk00000315/sig00000b53 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000336_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000335 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/blk00000315/sig00000b55 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000335_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000334 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/blk00000315/sig00000b51 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000334_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000333 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/blk00000315/sig00000b50 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000333_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000332 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/blk00000315/sig00000b52 ), + .Q15(\NLW_blk00000003/blk00000315/blk00000332_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000331 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/blk00000315/sig00000b4e ), + .Q15(\NLW_blk00000003/blk00000315/blk00000331_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk00000330 ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/blk00000315/sig00000b4d ), + .Q15(\NLW_blk00000003/blk00000315/blk00000330_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000315/blk0000032f ( + .A0(\blk00000003/sig000002b1 ), + .A1(\blk00000003/sig000002b0 ), + .A2(\blk00000003/blk00000315/sig00000b4c ), + .A3(\blk00000003/blk00000315/sig00000b4c ), + .CE(\blk00000003/blk00000315/sig00000b65 ), + .CLK(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/blk00000315/sig00000b4f ), + .Q15(\NLW_blk00000003/blk00000315/blk0000032f_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b64 ), + .Q(\blk00000003/sig00000337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b63 ), + .Q(\blk00000003/sig00000338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b62 ), + .Q(\blk00000003/sig00000339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b61 ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b60 ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5f ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5e ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5d ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5c ), + .Q(\blk00000003/sig0000033f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5b ), + .Q(\blk00000003/sig00000340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b5a ), + .Q(\blk00000003/sig00000341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b59 ), + .Q(\blk00000003/sig00000342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b58 ), + .Q(\blk00000003/sig00000343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b57 ), + .Q(\blk00000003/sig00000344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b56 ), + .Q(\blk00000003/sig00000345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b55 ), + .Q(\blk00000003/sig00000346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b54 ), + .Q(\blk00000003/sig00000347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b53 ), + .Q(\blk00000003/sig00000348 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b52 ), + .Q(\blk00000003/sig00000349 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b51 ), + .Q(\blk00000003/sig0000034a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b50 ), + .Q(\blk00000003/sig0000034b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4f ), + .Q(\blk00000003/sig0000034c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4e ), + .Q(\blk00000003/sig0000034d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000315/sig00000b4d ), + .Q(\blk00000003/sig0000034e ) + ); + GND \blk00000003/blk00000315/blk00000316 ( + .G(\blk00000003/blk00000315/sig00000b4c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000348/blk0000037a ( + .I0(ce), + .I1(\blk00000003/sig000004f5 ), + .O(\blk00000003/blk00000348/sig00000bb4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000379 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/blk00000348/sig00000bb2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000379_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000378 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/blk00000348/sig00000bb1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000378_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000377 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/blk00000348/sig00000bb3 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000377_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000376 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/blk00000348/sig00000baf ), + .Q15(\NLW_blk00000003/blk00000348/blk00000376_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000375 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/blk00000348/sig00000bae ), + .Q15(\NLW_blk00000003/blk00000348/blk00000375_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000374 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/blk00000348/sig00000bb0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000374_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000373 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/blk00000348/sig00000bac ), + .Q15(\NLW_blk00000003/blk00000348/blk00000373_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000372 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/blk00000348/sig00000bab ), + .Q15(\NLW_blk00000003/blk00000348/blk00000372_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000371 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/blk00000348/sig00000bad ), + .Q15(\NLW_blk00000003/blk00000348/blk00000371_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000370 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/blk00000348/sig00000ba9 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000370_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036f ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/blk00000348/sig00000ba8 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036e ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/blk00000348/sig00000baa ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036d ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/blk00000348/sig00000ba6 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036c ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/blk00000348/sig00000ba5 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036b ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/blk00000348/sig00000ba7 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk0000036a ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/blk00000348/sig00000ba3 ), + .Q15(\NLW_blk00000003/blk00000348/blk0000036a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000369 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/blk00000348/sig00000ba2 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000369_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000368 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/blk00000348/sig00000ba4 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000368_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000367 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/blk00000348/sig00000ba0 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000367_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000366 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/blk00000348/sig00000b9f ), + .Q15(\NLW_blk00000003/blk00000348/blk00000366_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000365 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/blk00000348/sig00000ba1 ), + .Q15(\NLW_blk00000003/blk00000348/blk00000365_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000364 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/blk00000348/sig00000b9d ), + .Q15(\NLW_blk00000003/blk00000348/blk00000364_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000363 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/blk00000348/sig00000b9c ), + .Q15(\NLW_blk00000003/blk00000348/blk00000363_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000348/blk00000362 ( + .A0(\blk00000003/sig000002b8 ), + .A1(\blk00000003/sig000002b7 ), + .A2(\blk00000003/blk00000348/sig00000b9b ), + .A3(\blk00000003/blk00000348/sig00000b9b ), + .CE(\blk00000003/blk00000348/sig00000bb4 ), + .CLK(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/blk00000348/sig00000b9e ), + .Q15(\NLW_blk00000003/blk00000348/blk00000362_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000361 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb3 ), + .Q(\blk00000003/sig0000034f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000360 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb2 ), + .Q(\blk00000003/sig00000350 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb1 ), + .Q(\blk00000003/sig00000351 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bb0 ), + .Q(\blk00000003/sig00000352 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baf ), + .Q(\blk00000003/sig00000353 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bae ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bad ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000035a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bac ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000359 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000bab ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000358 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000baa ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000357 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba9 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000356 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba8 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000355 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba7 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000354 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba6 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000353 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba5 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000352 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba4 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000351 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba3 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk00000350 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba2 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba1 ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000ba0 ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9f ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9e ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9d ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348/blk0000034a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000348/sig00000b9c ), + .Q(\blk00000003/sig00000366 ) + ); + GND \blk00000003/blk00000348/blk00000349 ( + .G(\blk00000003/blk00000348/sig00000b9b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000037b/blk000003b3 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk0000037b/sig00000c19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c06 ), + .DPO(\blk00000003/blk0000037b/sig00000c18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c05 ), + .DPO(\blk00000003/blk0000037b/sig00000c17 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003b0 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c04 ), + .DPO(\blk00000003/blk0000037b/sig00000c16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003af ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c03 ), + .DPO(\blk00000003/blk0000037b/sig00000c15 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ae ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c02 ), + .DPO(\blk00000003/blk0000037b/sig00000c14 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ad ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c01 ), + .DPO(\blk00000003/blk0000037b/sig00000c13 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003ac ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bff ), + .DPO(\blk00000003/blk0000037b/sig00000c11 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000037b/blk000003ab ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfe ), + .DPO(\blk00000003/blk0000037b/sig00000c10 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000037b/blk000003aa ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000c00 ), + .DPO(\blk00000003/blk0000037b/sig00000c12 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000037b/blk000003a9 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfd ), + .DPO(\blk00000003/blk0000037b/sig00000c0f ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk0000037b/blk000003a8 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfc ), + .DPO(\blk00000003/blk0000037b/sig00000c0e ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk0000037b/blk000003a7 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfb ), + .DPO(\blk00000003/blk0000037b/sig00000c0d ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000037b/blk000003a6 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bfa ), + .DPO(\blk00000003/blk0000037b/sig00000c0c ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a5 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf9 ), + .DPO(\blk00000003/blk0000037b/sig00000c0b ) + ); + RAM32X1D #( + .INIT ( 32'h00000004 )) + \blk00000003/blk0000037b/blk000003a4 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf8 ), + .DPO(\blk00000003/blk0000037b/sig00000c0a ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk0000037b/blk000003a3 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf6 ), + .DPO(\blk00000003/blk0000037b/sig00000c08 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a2 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf5 ), + .DPO(\blk00000003/blk0000037b/sig00000c07 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk0000037b/blk000003a1 ( + .A0(\blk00000003/sig00000264 ), + .A1(\blk00000003/sig00000268 ), + .A2(\blk00000003/sig0000026b ), + .A3(\blk00000003/blk0000037b/sig00000bf4 ), + .A4(\blk00000003/blk0000037b/sig00000bf4 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000002ba ), + .DPRA1(\blk00000003/sig000002be ), + .DPRA2(\blk00000003/sig000002c4 ), + .DPRA3(\blk00000003/blk0000037b/sig00000bf4 ), + .DPRA4(\blk00000003/blk0000037b/sig00000bf4 ), + .WCLK(clk), + .WE(\blk00000003/blk0000037b/sig00000c19 ), + .SPO(\blk00000003/blk0000037b/sig00000bf7 ), + .DPO(\blk00000003/blk0000037b/sig00000c09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk000003a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c18 ), + .Q(\blk00000003/sig000002c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c17 ), + .Q(\blk00000003/sig000002c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c16 ), + .Q(\blk00000003/sig000002c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c15 ), + .Q(\blk00000003/sig000002c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c14 ), + .Q(\blk00000003/sig000002c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c13 ), + .Q(\blk00000003/sig000002ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000039a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c12 ), + .Q(\blk00000003/sig000002cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000399 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c11 ), + .Q(\blk00000003/sig000002cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000398 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c10 ), + .Q(\blk00000003/sig000002cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000397 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0f ), + .Q(\blk00000003/sig000002ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000396 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0e ), + .Q(\blk00000003/sig000002cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000395 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0d ), + .Q(\blk00000003/sig000002d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000394 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0c ), + .Q(\blk00000003/sig000002d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000393 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0b ), + .Q(\blk00000003/sig000002d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000392 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c0a ), + .Q(\blk00000003/sig000002d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000391 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c09 ), + .Q(\blk00000003/sig000002d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000390 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c08 ), + .Q(\blk00000003/sig000002d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c07 ), + .Q(\blk00000003/sig000002d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c06 ), + .Q(\blk00000003/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c05 ), + .Q(\blk00000003/sig000005ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c04 ), + .Q(\blk00000003/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c03 ), + .Q(\blk00000003/sig000005cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000038a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c02 ), + .Q(\blk00000003/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000389 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c01 ), + .Q(\blk00000003/sig000005ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000388 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000c00 ), + .Q(\blk00000003/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000387 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bff ), + .Q(\blk00000003/sig000005d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000386 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfe ), + .Q(\blk00000003/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000385 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfd ), + .Q(\blk00000003/sig000005d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfc ), + .Q(\blk00000003/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfb ), + .Q(\blk00000003/sig000005d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bfa ), + .Q(\blk00000003/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf9 ), + .Q(\blk00000003/sig000005d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf8 ), + .Q(\blk00000003/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf7 ), + .Q(\blk00000003/sig000005d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf6 ), + .Q(\blk00000003/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000037b/sig00000bf5 ), + .Q(\blk00000003/sig000005da ) + ); + GND \blk00000003/blk0000037b/blk0000037c ( + .G(\blk00000003/blk0000037b/sig00000bf4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000003b4/blk000003ec ( + .I0(ce), + .I1(\blk00000003/sig000004e1 ), + .O(\blk00000003/blk000003b4/sig00000c7e ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003eb ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005c9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6b ), + .DPO(\blk00000003/blk000003b4/sig00000c7d ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003ea ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ca ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c6a ), + .DPO(\blk00000003/blk000003b4/sig00000c7c ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e9 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cb ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c69 ), + .DPO(\blk00000003/blk000003b4/sig00000c7b ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e8 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cc ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c68 ), + .DPO(\blk00000003/blk000003b4/sig00000c7a ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk000003b4/blk000003e7 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cd ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c67 ), + .DPO(\blk00000003/blk000003b4/sig00000c79 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk000003b4/blk000003e6 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005ce ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c66 ), + .DPO(\blk00000003/blk000003b4/sig00000c78 ) + ); + RAM32X1D #( + .INIT ( 32'h00000008 )) + \blk00000003/blk000003b4/blk000003e5 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d0 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c64 ), + .DPO(\blk00000003/blk000003b4/sig00000c76 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk000003b4/blk000003e4 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d1 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c63 ), + .DPO(\blk00000003/blk000003b4/sig00000c75 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003e3 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005cf ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c65 ), + .DPO(\blk00000003/blk000003b4/sig00000c77 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003e2 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d2 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c62 ), + .DPO(\blk00000003/blk000003b4/sig00000c74 ) + ); + RAM32X1D #( + .INIT ( 32'h00000006 )) + \blk00000003/blk000003b4/blk000003e1 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d3 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c61 ), + .DPO(\blk00000003/blk000003b4/sig00000c73 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk000003b4/blk000003e0 ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d4 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c60 ), + .DPO(\blk00000003/blk000003b4/sig00000c72 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000A )) + \blk00000003/blk000003b4/blk000003df ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d5 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5f ), + .DPO(\blk00000003/blk000003b4/sig00000c71 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003de ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d6 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5e ), + .DPO(\blk00000003/blk000003b4/sig00000c70 ) + ); + RAM32X1D #( + .INIT ( 32'h00000003 )) + \blk00000003/blk000003b4/blk000003dd ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d7 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5d ), + .DPO(\blk00000003/blk000003b4/sig00000c6f ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000003b4/blk000003dc ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d9 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5b ), + .DPO(\blk00000003/blk000003b4/sig00000c6d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000003b4/blk000003db ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005da ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5a ), + .DPO(\blk00000003/blk000003b4/sig00000c6c ) + ); + RAM32X1D #( + .INIT ( 32'h0000000F )) + \blk00000003/blk000003b4/blk000003da ( + .A0(\blk00000003/sig000004db ), + .A1(\blk00000003/sig000004dc ), + .A2(\blk00000003/sig000004dd ), + .A3(\blk00000003/blk000003b4/sig00000c59 ), + .A4(\blk00000003/blk000003b4/sig00000c59 ), + .D(\blk00000003/sig000005d8 ), + .DPRA0(\blk00000003/sig000004eb ), + .DPRA1(\blk00000003/sig000004e9 ), + .DPRA2(\blk00000003/sig000004e7 ), + .DPRA3(\blk00000003/blk000003b4/sig00000c59 ), + .DPRA4(\blk00000003/blk000003b4/sig00000c59 ), + .WCLK(clk), + .WE(\blk00000003/blk000003b4/sig00000c7e ), + .SPO(\blk00000003/blk000003b4/sig00000c5c ), + .DPO(\blk00000003/blk000003b4/sig00000c6e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7d ), + .Q(\blk00000003/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7c ), + .Q(\blk00000003/sig0000046a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7b ), + .Q(\blk00000003/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c7a ), + .Q(\blk00000003/sig0000046c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c79 ), + .Q(\blk00000003/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c78 ), + .Q(\blk00000003/sig0000046e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c77 ), + .Q(\blk00000003/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c76 ), + .Q(\blk00000003/sig00000470 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c75 ), + .Q(\blk00000003/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c74 ), + .Q(\blk00000003/sig00000472 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c73 ), + .Q(\blk00000003/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c72 ), + .Q(\blk00000003/sig00000474 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c71 ), + .Q(\blk00000003/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c70 ), + .Q(\blk00000003/sig00000476 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6f ), + .Q(\blk00000003/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6e ), + .Q(\blk00000003/sig00000478 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6d ), + .Q(\blk00000003/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6c ), + .Q(\blk00000003/sig0000047a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6b ), + .Q(\blk00000003/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c6a ), + .Q(\blk00000003/sig000005dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c69 ), + .Q(\blk00000003/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c68 ), + .Q(\blk00000003/sig000005de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c67 ), + .Q(\blk00000003/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c66 ), + .Q(\blk00000003/sig000005e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c65 ), + .Q(\blk00000003/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c64 ), + .Q(\blk00000003/sig000005e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c63 ), + .Q(\blk00000003/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c62 ), + .Q(\blk00000003/sig000005e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c61 ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c60 ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5f ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5e ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5d ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5c ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5b ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000003b4/sig00000c5a ), + .Q(\blk00000003/sig000005ec ) + ); + GND \blk00000003/blk000003b4/blk000003b5 ( + .G(\blk00000003/blk000003b4/sig00000c59 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000044d/blk00000473 ( + .I0(ce), + .I1(\blk00000003/sig000004e2 ), + .O(\blk00000003/blk0000044d/sig00000cbf ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000472 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005db ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000472_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbe ) + ); + RAM32X1D #( + .INIT ( 32'h0000000D )) + \blk00000003/blk0000044d/blk00000471 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dc ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000471_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbd ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000470 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005dd ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000470_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbc ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046f ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005de ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cbb ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk0000046e ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005df ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cba ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046d ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e0 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk0000046c ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e2 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk0000046b ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e3 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk0000046a ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e1 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk0000046a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000469 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e4 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000469_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000468 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e5 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000468_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb4 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000C )) + \blk00000003/blk0000044d/blk00000467 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e6 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000467_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000002 )) + \blk00000003/blk0000044d/blk00000466 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e7 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000466_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000005 )) + \blk00000003/blk0000044d/blk00000465 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e8 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000465_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000007 )) + \blk00000003/blk0000044d/blk00000464 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005e9 ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000464_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cb0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000044d/blk00000463 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005eb ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000463_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cae ) + ); + RAM32X1D #( + .INIT ( 32'h00000009 )) + \blk00000003/blk0000044d/blk00000462 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ec ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000462_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000cad ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk0000044d/blk00000461 ( + .A0(\blk00000003/sig000004de ), + .A1(\blk00000003/sig000004df ), + .A2(\blk00000003/sig000004e0 ), + .A3(\blk00000003/blk0000044d/sig00000cac ), + .A4(\blk00000003/blk0000044d/sig00000cac ), + .D(\blk00000003/sig000005ea ), + .DPRA0(\blk00000003/sig000004ec ), + .DPRA1(\blk00000003/sig000004ea ), + .DPRA2(\blk00000003/sig000004e8 ), + .DPRA3(\blk00000003/blk0000044d/sig00000cac ), + .DPRA4(\blk00000003/blk0000044d/sig00000cac ), + .WCLK(clk), + .WE(\blk00000003/blk0000044d/sig00000cbf ), + .SPO(\NLW_blk00000003/blk0000044d/blk00000461_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000044d/sig00000caf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000460 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbe ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbd ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbc ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cbb ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cba ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb9 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000045a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb8 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000459 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb7 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000458 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb6 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000457 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb5 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000456 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb4 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000455 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb3 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000454 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb2 ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000453 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb1 ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000452 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cb0 ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000451 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000caf ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk00000450 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cae ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d/blk0000044f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000044d/sig00000cad ), + .Q(\blk00000003/sig000003d8 ) + ); + GND \blk00000003/blk0000044d/blk0000044e ( + .G(\blk00000003/blk0000044d/sig00000cac ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000004a4/blk000004ca ( + .I0(ce), + .I1(\blk00000003/sig00000230 ), + .O(\blk00000003/blk000004a4/sig00000cfc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk000004a4/blk000004c9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cfa ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c7 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005b9 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c7_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c6 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005ba ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c6_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c5 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bb ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c5_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c4 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bc ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c4_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c3 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005be ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c3_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c2 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bf ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c2_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c1 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005bd ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c1_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004c0 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c0 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004c0_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bf ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c1 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bf_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004be ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c2 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004be_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cf0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bd ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c3 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bd_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cef ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bc ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c4 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bc_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cee ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004bb ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c5 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004bb_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ced ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004ba ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c7 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004ba_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000ceb ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b9 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c8 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b9_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cea ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk000004a4/blk000004b8 ( + .A0(\blk00000003/sig00000237 ), + .A1(\blk00000003/blk000004a4/sig00000ce9 ), + .A2(\blk00000003/blk000004a4/sig00000ce9 ), + .A3(\blk00000003/blk000004a4/sig00000ce9 ), + .A4(\blk00000003/blk000004a4/sig00000ce9 ), + .D(\blk00000003/sig000005c6 ), + .DPRA0(\blk00000003/sig000005f0 ), + .DPRA1(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA2(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA3(\blk00000003/blk000004a4/sig00000ce9 ), + .DPRA4(\blk00000003/blk000004a4/sig00000ce9 ), + .WCLK(clk), + .WE(\blk00000003/blk000004a4/sig00000cfc ), + .SPO(\NLW_blk00000003/blk000004a4/blk000004b8_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000004a4/sig00000cec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfb ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cfa ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf9 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf8 ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf7 ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf6 ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf5 ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf4 ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf3 ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf2 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf1 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cf0 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cef ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cee ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ced ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cec ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000ceb ), + .Q(\blk00000003/sig00000103 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004a4/blk000004a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000004a4/sig00000cea ), + .Q(\blk00000003/sig00000104 ) + ); + GND \blk00000003/blk000004a4/blk000004a5 ( + .G(\blk00000003/blk000004a4/sig00000ce9 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.veo b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.veo new file mode 100644 index 000000000..ce561daa2 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec2 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [46 : 0] dout_1 + .dout_2(dout_2)); // output [46 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec2.v when simulating +// the core, hbdec2. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xco b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xco new file mode 100644 index 000000000..47574a352 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Dec 4 21:33:01 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc7k325t +SET devicefamily = kintex7 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ffg900 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=200 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb47.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=4 +CSET component_name=hbdec2 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=47 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=100 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: b27c3487 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_0.mif new file mode 100644 index 000000000..079623297 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_0.mif @@ -0,0 +1,9 @@ +111111111111000010 +000000000011000010 +111111111001001000 +000000001101010111 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_1.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_1.mif new file mode 100644 index 000000000..d4a0b357e --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_1.mif @@ -0,0 +1,9 @@ +111111101000011111 +000000100110101110 +111111000011000100 +000001011101100110 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_2.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_2.mif new file mode 100644 index 000000000..6d9d6044f --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto0_2.mif @@ -0,0 +1,9 @@ +111101110000011101 +000011100100101000 +111001100001011000 +010100010001000001 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2_flist.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_flist.txt new file mode 100644 index 000000000..d0a6a5443 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_flist.txt @@ -0,0 +1,19 @@ +# Output products list for +hbdec2.asy +hbdec2.gise +hbdec2.mif +hbdec2.ngc +hbdec2.v +hbdec2.veo +hbdec2.xco +hbdec2.xise +hbdec2COEFF_auto0_0.mif +hbdec2COEFF_auto0_1.mif +hbdec2COEFF_auto0_2.mif +hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +hbdec2_flist.txt +hbdec2_readme.txt +hbdec2_reload_addrfilt_decode_rom.mif +hbdec2_reload_order.txt +hbdec2_xmdf.tcl +hbdec2filt_decode_rom.mif diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2_readme.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_readme.txt new file mode 100644 index 000000000..b65eaf925 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_readme.txt @@ -0,0 +1,64 @@ +The following files were generated for 'hbdec2' in directory +/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/ + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec2.mif + * hbdec2_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec2.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec2.ngc + * hbdec2.v + * hbdec2.veo + * hbdec2COEFF_auto0_0.mif + * hbdec2COEFF_auto0_1.mif + * hbdec2COEFF_auto0_2.mif + * hbdec2COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec2_reload_addrfilt_decode_rom.mif + * hbdec2filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec2.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec2.asy + * hbdec2.mif + * hbdec2_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec2_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec2.gise + * hbdec2.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec2_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec2_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_order.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_order.txt new file mode 100644 index 000000000..071b84e5b --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_reload_order.txt @@ -0,0 +1,25 @@ +Reload index 0 = Index 16 +Reload index 1 = Index 18 +Reload index 2 = Index 20 +Reload index 3 = Index 22 +Reload index 4 = Index 8 +Reload index 5 = Index 10 +Reload index 6 = Index 12 +Reload index 7 = Index 14 +Reload index 8 = Index 0 +Reload index 9 = Index 2 +Reload index 10 = Index 4 +Reload index 11 = Index 6 +Reload index 12 = Index 23 +Reload index 13 = Index 0 +Reload index 14 = Index 0 +Reload index 15 = Index 0 +Reload index 16 = Index 0 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2_xmdf.tcl b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_xmdf.tcl new file mode 100644 index 000000000..efebbe070 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2_xmdf.tcl @@ -0,0 +1,99 @@ +# The package naming convention is _xmdf +package provide hbdec2_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec2_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec2_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec2 +} +# ::hbdec2_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec2_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto0_2.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec2filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec2 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec2filt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec2filt_decode_rom.mif new file mode 100644 index 000000000..92e61d005 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec2filt_decode_rom.mif @@ -0,0 +1,17 @@ +000 +100 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.asy b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.asy new file mode 100644 index 000000000..693fa2b1e --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.asy @@ -0,0 +1,61 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 hbdec3 +RECTANGLE Normal 32 32 544 2048 +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName nd +PINATTR Polarity IN +LINE Wide 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName din_1[23:0] +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din_2[23:0] +PINATTR Polarity IN +LINE Normal 0 848 32 848 +PIN 0 848 LEFT 36 +PINATTR PinName coef_ld +PINATTR Polarity IN +LINE Normal 0 880 32 880 +PIN 0 880 LEFT 36 +PINATTR PinName coef_we +PINATTR Polarity IN +LINE Wide 0 912 32 912 +PIN 0 912 LEFT 36 +PINATTR PinName coef_din[17:0] +PINATTR Polarity IN +LINE Normal 0 1008 32 1008 +PIN 0 1008 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 1040 32 1040 +PIN 0 1040 LEFT 36 +PINATTR PinName ce +PINATTR Polarity IN +LINE Normal 0 1072 32 1072 +PIN 0 1072 LEFT 36 +PINATTR PinName sclr +PINATTR Polarity IN +LINE Wide 576 240 544 240 +PIN 576 240 RIGHT 36 +PINATTR PinName dout_1[47:0] +PINATTR Polarity OUT +LINE Wide 576 272 544 272 +PIN 576 272 RIGHT 36 +PINATTR PinName dout_2[47:0] +PINATTR Polarity OUT +LINE Normal 576 1840 544 1840 +PIN 576 1840 RIGHT 36 +PINATTR PinName rfd +PINATTR Polarity OUT +LINE Normal 576 1872 544 1872 +PIN 576 1872 RIGHT 36 +PINATTR PinName rdy +PINATTR Polarity OUT +LINE Normal 576 1904 544 1904 +PIN 576 1904 RIGHT 36 +PINATTR PinName data_valid +PINATTR Polarity OUT + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.mif new file mode 100644 index 000000000..e26979353 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.mif @@ -0,0 +1,63 @@ +111111111111011101 +000000000000000000 +000000000001011111 +000000000000000000 +111111111100111101 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+000000000000000000 +000000000101100000 +000000000000000000 +111111111100111101 +000000000000000000 +000000000001011111 +000000000000000000 +111111111111011101 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ngc b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ngc new file mode 100644 index 000000000..5eaff1030 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0dg2~753-Xnzd}foo8#5+421).97 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155289;j6`;3081<>=h9::i6=4+4209566a3g>8=7<6;:m275g=83.???4>31d8j1562;k07b?<0083>!24:3;85$511>457n2d??<4=c:9l57ce290/8><5122e?k24938o76a>2d294?"3;;0:?=h4n512>7c<3f;9hk4?:%606?748o1e8>?52g98k454i3:1(9==:0174>h3;80;76a>32;94?"3;;0:?9>4n512>4=5$511>45382d??<4=;:m2761=83.???4>3528j1562:10c<=<6;29 155289?<6`;3087?>i6;:?1<7*;3382716=50;&777<6;=:0b9=>:698k45493:1(9==:0174>h3;80376a>32294?"3;;0:?9>4n512><=5$511>45382d??<4n;:m277c=83.???4>3528j1562k10c<==d;29 155289?<6`;308`?>i6;;i1<7*;3382716:g98k45513:1(9==:0174>h3;80:<65`120;>5<#<:81=>:?;o605?7632e:??850;&777<6;=:0b9=>:008?j74:<0;6):<2;3005=i<:;1=>54o0110?6=,=996<=;0:l774<6<21d=><<:18'064=9:>;7c:<1;36?>i6;;81<7*;33827168>7?<419m067=9>10c<==0;29 155289?<6`;3082<>=h9:;m6=4+420956273g>8=7?6;:m274c=83.???4>3528j15628k07b?<1e83>!24:3;88=5a42395g=5$511>45382d??<4>c:9l567f290/8><51263?k2493;o76a>30;94?"3;;0:?9>4n512>4c<3f;8=54?:%606?74<91e8>?51g98k456?3:1(9==:0174>h3;809<65`1235>5<#<:81=>:?;o605?4632e:?<;50;&777<6;=:0b9=>:308?j749=0;6):<2;3005=i<:;1>>54o0127?6=,=996<=;0:l774<5<21d=>?=:18'064=9:>;7c:<1;06?>i6;:l1<7*;33827168>7?<419m067=:>10c<==h9:9h6=4+420956273g>8=7<6;:m276d=83.???4>3528j1562;k07b?<3383>!24:3;88=5a42396g=5$511>45382d??<4=c:9l567d290/8><51263?k24938o76a>30394?"3;;0:?9>4n512>7c<3f;8==4?:%606?74<91e8>?52g98k451j3:1(9==:0145>h3;80;76a>37c94?"3;;0:?:?4n512>4=5$511>45092d??<4=;:m273>=83.???4>3638j1562:10c<=97;29 155289<=6`;3087?>i6;?<1<7*;3382727;0b9=>:698k451:3:1(9==:0145>h3;80376a>37394?"3;;0:?:?4n512><=5$511>45092d??<4n;:m270`=83.???4>3638j1562k10c<=:e;29 155289<=6`;308`?>i6;;0b9=>:g98k452i3:1(9==:0145>h3;80:<65`127:>5<#<:81=>9>;o605?7632e:?8950;&777<6;>;0b9=>:008?j74=?0;6):<2;3034=i<:;1=>54o0161?6=,=996<=81:l774<6<21d=>;;:18'064=9:=:7c:<1;36?>i6;<91<7*;33827278>7?<709m067=9>10c<=:1;29 155289<=6`;3082<>=h9:?;6=4+420956163g>8=7?6;:m271`=83.???4>3638j15628k07b?<4d83>!24:3;8;<5a42395g=5$511>45092d??<4>c:9l562e290/8><51252?k2493;o76a>35c94?"3;;0:?:?4n512>4c<3f;8844?:%606?74?81e8>?51g98k45303:1(9==:0145>h3;809<65`1264>5<#<:81=>9>;o605?4632e:?9850;&777<6;>;0b9=>:308?j74<<0;6):<2;3034=i<:;1>>54o0170?6=,=996<=81:l774<5<21d=>:<:18'064=9:=:7c:<1;06?>i6;>:1<7*;33827278>7?<709m067=:>10c<=9e;29 155289<=6`;3081<>=h9:8=7<6;:m273e=83.???4>3638j1562;k07b?<6283>!24:3;8;<5a42396g=47>5$511>45092d??<4=c:9l562c290/8><51252?k24938o76a>35094?"3;;0:?:?4n512>7c<3f;88<4?:%606?74?81e8>?52g98md`02900c<=6c;29 155289j>6`;3083?>i6;0h1<7*;33827d4:298k45>03:1(9==:01b6>h3;80?76a>38594?"3;;0:?l<4n512>0=5$511>45f:2d??<49;:m27<3=83.???4>3`08j1562>10c<=63;29 155289j>6`;308;?>i6;081<7*;33827d450;&777<6;h80b9=>:c98k45?n3:1(9==:01b6>h3;80h76a>39g94?"3;;0:?l<4n512>a=5$511>45f:2d??<4j;:m27=e=83.???4>3`08j1562o10c<=7b;29 155289j>6`;30824>=h9:2j6=4+420956g53g>8=7?>;:m27=>=83.???4>3`08j15628807b?<8683>!24:3;8m?5a423956=5$511>45f:2d??<4>4:9l56>2290/8><512c1?k2493;>76a>39694?"3;;0:?l<4n512>40<3f;84>4?:%606?74i;1e8>?51698k45?:3:1(9==:01b6>h3;80:465`12:2>5<#<:81=>o=;o605?7>32e:?5>50;&777<6;h80b9=>:0c8?j74?o0;6):<2;30e7=i<:;1=o54o014`?6=,=996<=n2:l774<6k21d=>9l:18'064=9:k97c:<1;3g?>i6;>h1<7*;33827d48>7?6`;30814>=h9:=36=4+420956g53g>8=7<>;:m2721=83.???4>3`08j1562;807b?<7783>!24:3;8m?5a423966=5$511>45f:2d??<4=4:9l5613290/8><512c1?k24938>76a>3`394?"3;;0:?l<4n512>70<3f;8m=4?:%606?74i;1e8>?52698k45>n3:1(9==:01b6>h3;809465`12;f>5<#<:81=>o=;o605?4>32e:?4j50;&777<6;h80b9=>:3c8?j741=0;6):<2;30e7=i<:;1>o54o01;=?6=,=996<=n2:l774<5k21d=>9j:18'064=9:k97c:<1;0g?>i6;>91<7*;33827d48>7?i6;ji1<7*;33827a5:298k45d13:1(9==:01g7>h3;80?76a>3b:94?"3;;0:?i=4n512>0=5$511>45c;2d??<49;:m27f0=83.???4>3e18j1562>10c<=l4;29 155289o?6`;308;?>i6;j91<7*;33827a5:c98k45d83:1(9==:01g7>h3;80h76a>3cd94?"3;;0:?i=4n512>a=5$511>45c;2d??<4j;:m27gb=83.???4>3e18j1562o10c<=mc;29 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h<5>4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<594?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<584?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5;4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5:4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<554?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<544?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5l4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5o4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5n4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5i4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5h4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th<5k4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th4?:483>5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3th5}#<=n1>o?4H57`?M2282.9nh4=;h36a?6=3`;2i7>5;h3a0?6=3`>8;7>5;n601?6=3tho7;t3181f?562;o1>k4ri02:>5<#<:81==64n512>5=5<#<:81>=l4n512>4=5<#<:81>=l4n512>6=5<#<:81>=l4n512>0=6=4+420965d5<#<:81>=l4n512>2=5<#<:81>=l4n512><=5<#<:81>=l4n512>g=5<#<:81>=l4n512>a=6=4+420965d5<#<:81>=l4n512>c=4;h037?6=,=996?>m;o605?7632c:==4?:%606?77n2d??<4?;:k71<<722c:5h4?::k701<722c:mk4?::m17`<72->8>7<;:m17g<72->8>7<8>7<8>7<8>7<8>7<4?:%606?44l2d??<4m;:m127<72->8>7<8>7<8>7<>;50;&777<5;m1e8>?51098k717290/8><527d8j1562910c?8j:18'064=:?l0b9=>:098k70c290/8><527d8j1562;10c?8l:18'064=:?l0b9=>:298k70e290/8><527d8j1562=10c?8n:18'064=:?l0b9=>:498k70>290/8><527d8j1562?10c?87:18'064=:?l0b9=>:698k7??290/8><527d8j1562110c?78:18'064=:?l0b9=>:898k7?1290/8><527d8j1562h10c?7::18'064=:?l0b9=>:c98k7?3290/8><527d8j1562j10c?7<:18'064=:?l0b9=>:e98k7>>290/8><527d8j1562l10c?9j:18'064=:?l0b9=>:g98k714290/8><527d8j15628:07b<97;29 1552;d0lo0;6<4?:1y'01b=:k=0D9;l;I664>i5j?0;66sm7d294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l;1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d094?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l91<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d694?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l?1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d494?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l=1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7d:94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?l31<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dc94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?lh1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7da94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ln1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7dg94?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?ll1<7:50;2x 12c2;km7E::c:J715=#:ko1>6g>5d83>>o61l0;66g>b583>>i3;<0;66sm7g294?2=83:p(9:k:3ce?M22k2B?9=5+2cg96>o6=l0;66g>9d83>>o6j=0;66a;3483>>{e?o;1<7:50;2x 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\ No newline at end of file diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.v b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.v new file mode 100644 index 000000000..cd6e39d9f --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.v @@ -0,0 +1,20014 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: P.49d +// \ \ Application: netgen +// / / Filename: hbdec3.v +// /___/ /\ Timestamp: Wed Dec 4 13:32:32 2013 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/hbdec3.ngc ./tmp/_cg/hbdec3.v +// Device : 7k325tffg900-2 +// Input file : ./tmp/_cg/hbdec3.ngc +// Output file : ./tmp/_cg/hbdec3.v +// # of Modules : 1 +// Design Name : hbdec3 +// Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module hbdec3 ( + sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk, coef_ld, dout_1, dout_2, din_1, din_2, coef_din +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rfd; + output rdy; + output data_valid; + input coef_we; + input nd; + input clk; + input coef_ld; + output [47 : 0] dout_1; + output [47 : 0] dout_2; + input [23 : 0] din_1; + input [23 : 0] din_2; + input [17 : 0] coef_din; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \blk00000003/sig00000664 ; + wire \blk00000003/sig00000663 ; + wire \blk00000003/sig00000662 ; + wire \blk00000003/sig00000661 ; + wire \blk00000003/sig00000660 ; + wire \blk00000003/sig0000065f ; + wire \blk00000003/sig0000065e ; + wire \blk00000003/sig0000065d ; + wire \blk00000003/sig0000065c ; + wire \blk00000003/sig0000065b ; + wire \blk00000003/sig0000065a ; + wire \blk00000003/sig00000659 ; + wire \blk00000003/sig00000658 ; + wire \blk00000003/sig00000657 ; + wire \blk00000003/sig00000656 ; + wire \blk00000003/sig00000655 ; + wire \blk00000003/sig00000654 ; + wire \blk00000003/sig00000653 ; + wire \blk00000003/sig00000652 ; + wire \blk00000003/sig00000651 ; + wire \blk00000003/sig00000650 ; + wire \blk00000003/sig0000064f ; + wire \blk00000003/sig0000064e ; + wire \blk00000003/sig0000064d ; + wire \blk00000003/sig0000064c ; + wire \blk00000003/sig0000064b ; + wire \blk00000003/sig0000064a ; + wire \blk00000003/sig00000649 ; + wire \blk00000003/sig00000648 ; + wire \blk00000003/sig00000647 ; + wire \blk00000003/sig00000646 ; + wire \blk00000003/sig00000645 ; + wire \blk00000003/sig00000644 ; + wire \blk00000003/sig00000643 ; + wire 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\blk00000003/blk000002b1/sig000009c7 ; + wire \blk00000003/blk000002b1/sig000009c6 ; + wire \blk00000003/blk000002b1/sig000009c5 ; + wire \blk00000003/blk000002b1/sig000009c4 ; + wire \blk00000003/blk000002b1/sig000009c3 ; + wire \blk00000003/blk000002b1/sig000009c2 ; + wire \blk00000003/blk000002b1/sig000009c1 ; + wire \blk00000003/blk000002b1/sig000009c0 ; + wire \blk00000003/blk000002b1/sig000009bf ; + wire \blk00000003/blk000002ea/sig00000a27 ; + wire \blk00000003/blk000002ea/sig00000a26 ; + wire \blk00000003/blk000002ea/sig00000a25 ; + wire \blk00000003/blk000002ea/sig00000a24 ; + wire \blk00000003/blk000002ea/sig00000a23 ; + wire \blk00000003/blk000002ea/sig00000a22 ; + wire \blk00000003/blk000002ea/sig00000a21 ; + wire \blk00000003/blk000002ea/sig00000a20 ; + wire \blk00000003/blk000002ea/sig00000a1f ; + wire \blk00000003/blk000002ea/sig00000a1e ; + wire \blk00000003/blk000002ea/sig00000a1d ; + wire \blk00000003/blk000002ea/sig00000a1c ; + wire \blk00000003/blk000002ea/sig00000a1b ; + wire \blk00000003/blk000002ea/sig00000a1a ; + wire \blk00000003/blk000002ea/sig00000a19 ; + wire \blk00000003/blk000002ea/sig00000a18 ; + wire \blk00000003/blk000002ea/sig00000a17 ; + wire \blk00000003/blk000002ea/sig00000a16 ; + wire \blk00000003/blk000002ea/sig00000a15 ; + wire \blk00000003/blk000002ea/sig00000a14 ; + wire \blk00000003/blk00000371/sig00000a64 ; + wire \blk00000003/blk00000371/sig00000a63 ; + wire \blk00000003/blk00000371/sig00000a62 ; + wire \blk00000003/blk00000371/sig00000a61 ; + wire \blk00000003/blk00000371/sig00000a60 ; + wire \blk00000003/blk00000371/sig00000a5f ; + wire \blk00000003/blk00000371/sig00000a5e ; + wire \blk00000003/blk00000371/sig00000a5d ; + wire \blk00000003/blk00000371/sig00000a5c ; + wire \blk00000003/blk00000371/sig00000a5b ; + wire \blk00000003/blk00000371/sig00000a5a ; + wire \blk00000003/blk00000371/sig00000a59 ; + wire \blk00000003/blk00000371/sig00000a58 ; + wire \blk00000003/blk00000371/sig00000a57 ; + wire \blk00000003/blk00000371/sig00000a56 ; + wire \blk00000003/blk00000371/sig00000a55 ; + wire \blk00000003/blk00000371/sig00000a54 ; + wire \blk00000003/blk00000371/sig00000a53 ; + wire \blk00000003/blk00000371/sig00000a52 ; + wire \blk00000003/blk00000371/sig00000a51 ; + wire NLW_blk00000001_P_UNCONNECTED; + wire NLW_blk00000002_G_UNCONNECTED; + wire \NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000658_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000656_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000654_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000652_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000650_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000648_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000646_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000644_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000642_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000640_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000638_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000636_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000634_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000632_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000630_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000628_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000626_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000624_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000622_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000620_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000618_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000616_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000614_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000612_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000610_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000608_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000606_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000604_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000602_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000600_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005be_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000598_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000596_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000594_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000592_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000590_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000588_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000586_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000584_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000582_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000580_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000578_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000576_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000574_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000572_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000570_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000568_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000566_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000564_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000562_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000560_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000558_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000556_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000554_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000552_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000550_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000548_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000546_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000544_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000542_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000540_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000538_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000536_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000534_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000532_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000530_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000528_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000526_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000524_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000522_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000520_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000518_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000516_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000514_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000512_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000510_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000508_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000506_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000504_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000409_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000107_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000106_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000105_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000104_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000fe_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000f2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000eb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000e1_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000dd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d7_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d6_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d5_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d4_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000d3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cf_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ce_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cc_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000cb_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000ca_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c9_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000c2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000bd_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b8_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000000b2_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk000000a0_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000009e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000096_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000095_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000094_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000093_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000092_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000090_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000008f_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000019_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000014_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000010_O_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000d_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000000a_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000009_LO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ; + wire \NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ; + wire [17 : 0] coef_din_0; + wire [23 : 0] din_1_1; + wire [23 : 0] din_2_2; + wire [47 : 0] NlwRenamedSig_OI_dout_1; + wire [47 : 0] NlwRenamedSig_OI_dout_2; + assign + rfd = NlwRenamedSig_OI_rfd, + dout_1[47] = NlwRenamedSig_OI_dout_1[47], + dout_1[46] = NlwRenamedSig_OI_dout_1[46], + dout_1[45] = NlwRenamedSig_OI_dout_1[45], + dout_1[44] = NlwRenamedSig_OI_dout_1[44], + dout_1[43] = NlwRenamedSig_OI_dout_1[43], + dout_1[42] = NlwRenamedSig_OI_dout_1[42], + dout_1[41] = NlwRenamedSig_OI_dout_1[41], + dout_1[40] = NlwRenamedSig_OI_dout_1[40], + dout_1[39] = NlwRenamedSig_OI_dout_1[39], + dout_1[38] = NlwRenamedSig_OI_dout_1[38], + dout_1[37] = NlwRenamedSig_OI_dout_1[37], + dout_1[36] = NlwRenamedSig_OI_dout_1[36], + dout_1[35] = NlwRenamedSig_OI_dout_1[35], + dout_1[34] = NlwRenamedSig_OI_dout_1[34], + dout_1[33] = NlwRenamedSig_OI_dout_1[33], + dout_1[32] = NlwRenamedSig_OI_dout_1[32], + dout_1[31] = NlwRenamedSig_OI_dout_1[31], + dout_1[30] = NlwRenamedSig_OI_dout_1[30], + dout_1[29] = NlwRenamedSig_OI_dout_1[29], + dout_1[28] = NlwRenamedSig_OI_dout_1[28], + dout_1[27] = NlwRenamedSig_OI_dout_1[27], + dout_1[26] = NlwRenamedSig_OI_dout_1[26], + dout_1[25] = NlwRenamedSig_OI_dout_1[25], + dout_1[24] = NlwRenamedSig_OI_dout_1[24], + dout_1[23] = NlwRenamedSig_OI_dout_1[23], + dout_1[22] = NlwRenamedSig_OI_dout_1[22], + dout_1[21] = NlwRenamedSig_OI_dout_1[21], + dout_1[20] = NlwRenamedSig_OI_dout_1[20], + dout_1[19] = NlwRenamedSig_OI_dout_1[19], + dout_1[18] = NlwRenamedSig_OI_dout_1[18], + dout_1[17] = NlwRenamedSig_OI_dout_1[17], + dout_1[16] = NlwRenamedSig_OI_dout_1[16], + dout_1[15] = NlwRenamedSig_OI_dout_1[15], + dout_1[14] = NlwRenamedSig_OI_dout_1[14], + dout_1[13] = NlwRenamedSig_OI_dout_1[13], + dout_1[12] = NlwRenamedSig_OI_dout_1[12], + dout_1[11] = NlwRenamedSig_OI_dout_1[11], + dout_1[10] = NlwRenamedSig_OI_dout_1[10], + dout_1[9] = NlwRenamedSig_OI_dout_1[9], + dout_1[8] = NlwRenamedSig_OI_dout_1[8], + dout_1[7] = NlwRenamedSig_OI_dout_1[7], + dout_1[6] = NlwRenamedSig_OI_dout_1[6], + dout_1[5] = NlwRenamedSig_OI_dout_1[5], + dout_1[4] = NlwRenamedSig_OI_dout_1[4], + dout_1[3] = NlwRenamedSig_OI_dout_1[3], + dout_1[2] = NlwRenamedSig_OI_dout_1[2], + dout_1[1] = NlwRenamedSig_OI_dout_1[1], + dout_1[0] = NlwRenamedSig_OI_dout_1[0], + dout_2[47] = NlwRenamedSig_OI_dout_2[47], + dout_2[46] = NlwRenamedSig_OI_dout_2[46], + dout_2[45] = NlwRenamedSig_OI_dout_2[45], + dout_2[44] = NlwRenamedSig_OI_dout_2[44], + dout_2[43] = NlwRenamedSig_OI_dout_2[43], + dout_2[42] = NlwRenamedSig_OI_dout_2[42], + dout_2[41] = NlwRenamedSig_OI_dout_2[41], + dout_2[40] = NlwRenamedSig_OI_dout_2[40], + dout_2[39] = NlwRenamedSig_OI_dout_2[39], + dout_2[38] = NlwRenamedSig_OI_dout_2[38], + dout_2[37] = NlwRenamedSig_OI_dout_2[37], + dout_2[36] = NlwRenamedSig_OI_dout_2[36], + dout_2[35] = NlwRenamedSig_OI_dout_2[35], + dout_2[34] = NlwRenamedSig_OI_dout_2[34], + dout_2[33] = NlwRenamedSig_OI_dout_2[33], + dout_2[32] = NlwRenamedSig_OI_dout_2[32], + dout_2[31] = NlwRenamedSig_OI_dout_2[31], + dout_2[30] = NlwRenamedSig_OI_dout_2[30], + dout_2[29] = NlwRenamedSig_OI_dout_2[29], + dout_2[28] = NlwRenamedSig_OI_dout_2[28], + dout_2[27] = NlwRenamedSig_OI_dout_2[27], + dout_2[26] = NlwRenamedSig_OI_dout_2[26], + dout_2[25] = NlwRenamedSig_OI_dout_2[25], + dout_2[24] = NlwRenamedSig_OI_dout_2[24], + dout_2[23] = NlwRenamedSig_OI_dout_2[23], + dout_2[22] = NlwRenamedSig_OI_dout_2[22], + dout_2[21] = NlwRenamedSig_OI_dout_2[21], + dout_2[20] = NlwRenamedSig_OI_dout_2[20], + dout_2[19] = NlwRenamedSig_OI_dout_2[19], + dout_2[18] = NlwRenamedSig_OI_dout_2[18], + dout_2[17] = NlwRenamedSig_OI_dout_2[17], + dout_2[16] = NlwRenamedSig_OI_dout_2[16], + dout_2[15] = NlwRenamedSig_OI_dout_2[15], + dout_2[14] = NlwRenamedSig_OI_dout_2[14], + dout_2[13] = NlwRenamedSig_OI_dout_2[13], + dout_2[12] = NlwRenamedSig_OI_dout_2[12], + dout_2[11] = NlwRenamedSig_OI_dout_2[11], + dout_2[10] = NlwRenamedSig_OI_dout_2[10], + dout_2[9] = NlwRenamedSig_OI_dout_2[9], + dout_2[8] = NlwRenamedSig_OI_dout_2[8], + dout_2[7] = NlwRenamedSig_OI_dout_2[7], + dout_2[6] = NlwRenamedSig_OI_dout_2[6], + dout_2[5] = NlwRenamedSig_OI_dout_2[5], + dout_2[4] = NlwRenamedSig_OI_dout_2[4], + dout_2[3] = NlwRenamedSig_OI_dout_2[3], + dout_2[2] = NlwRenamedSig_OI_dout_2[2], + dout_2[1] = NlwRenamedSig_OI_dout_2[1], + dout_2[0] = NlwRenamedSig_OI_dout_2[0], + din_1_1[23] = din_1[23], + din_1_1[22] = din_1[22], + din_1_1[21] = din_1[21], + din_1_1[20] = din_1[20], + din_1_1[19] = din_1[19], + din_1_1[18] = din_1[18], + din_1_1[17] = din_1[17], + din_1_1[16] = din_1[16], + din_1_1[15] = din_1[15], + din_1_1[14] = din_1[14], + din_1_1[13] = din_1[13], + din_1_1[12] = din_1[12], + din_1_1[11] = din_1[11], + din_1_1[10] = din_1[10], + din_1_1[9] = din_1[9], + din_1_1[8] = din_1[8], + din_1_1[7] = din_1[7], + din_1_1[6] = din_1[6], + din_1_1[5] = din_1[5], + din_1_1[4] = din_1[4], + din_1_1[3] = din_1[3], + din_1_1[2] = din_1[2], + din_1_1[1] = din_1[1], + din_1_1[0] = din_1[0], + din_2_2[23] = din_2[23], + din_2_2[22] = din_2[22], + din_2_2[21] = din_2[21], + din_2_2[20] = din_2[20], + din_2_2[19] = din_2[19], + din_2_2[18] = din_2[18], + din_2_2[17] = din_2[17], + din_2_2[16] = din_2[16], + din_2_2[15] = din_2[15], + din_2_2[14] = din_2[14], + din_2_2[13] = din_2[13], + din_2_2[12] = din_2[12], + din_2_2[11] = din_2[11], + din_2_2[10] = din_2[10], + din_2_2[9] = din_2[9], + din_2_2[8] = din_2[8], + din_2_2[7] = din_2[7], + din_2_2[6] = din_2[6], + din_2_2[5] = din_2[5], + din_2_2[4] = din_2[4], + din_2_2[3] = din_2[3], + din_2_2[2] = din_2[2], + din_2_2[1] = din_2[1], + din_2_2[0] = din_2[0], + coef_din_0[17] = coef_din[17], + coef_din_0[16] = coef_din[16], + coef_din_0[15] = coef_din[15], + coef_din_0[14] = coef_din[14], + coef_din_0[13] = coef_din[13], + coef_din_0[12] = coef_din[12], + coef_din_0[11] = coef_din[11], + coef_din_0[10] = coef_din[10], + coef_din_0[9] = coef_din[9], + coef_din_0[8] = coef_din[8], + coef_din_0[7] = coef_din[7], + coef_din_0[6] = coef_din[6], + coef_din_0[5] = coef_din[5], + coef_din_0[4] = coef_din[4], + coef_din_0[3] = coef_din[3], + coef_din_0[2] = coef_din[2], + coef_din_0[1] = coef_din[1], + coef_din_0[0] = coef_din[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000065b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000664 ), + .Q(\blk00000003/sig00000579 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000065a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000434 ), + .Q(\blk00000003/sig00000664 ), + .Q15(\NLW_blk00000003/blk0000065a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000659 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000663 ), + .Q(\blk00000003/sig00000502 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000658 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000042e ), + .Q(\blk00000003/sig00000663 ), + .Q15(\NLW_blk00000003/blk00000658_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000657 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000662 ), + .Q(\blk00000003/sig000001c3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000656 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000630 ), + .Q(\blk00000003/sig00000662 ), + .Q15(\NLW_blk00000003/blk00000656_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000655 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000661 ), + .Q(\blk00000003/sig000001c2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000654 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062e ), + .Q(\blk00000003/sig00000661 ), + .Q15(\NLW_blk00000003/blk00000654_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000653 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000660 ), + .Q(\blk00000003/sig000001c1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000652 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062c ), + .Q(\blk00000003/sig00000660 ), + .Q15(\NLW_blk00000003/blk00000652_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000651 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065f ), + .Q(\blk00000003/sig000001c0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000650 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000062a ), + .Q(\blk00000003/sig0000065f ), + .Q15(\NLW_blk00000003/blk00000650_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065e ), + .Q(\blk00000003/sig000001be ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000628 ), + .Q(\blk00000003/sig0000065e ), + .Q15(\NLW_blk00000003/blk0000064e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065d ), + .Q(\blk00000003/sig000001bd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000626 ), + .Q(\blk00000003/sig0000065d ), + .Q15(\NLW_blk00000003/blk0000064c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000064b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065c ), + .Q(\blk00000003/sig000001bf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000064a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000624 ), + .Q(\blk00000003/sig0000065c ), + .Q15(\NLW_blk00000003/blk0000064a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000649 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065b ), + .Q(\blk00000003/sig000001bc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000648 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061e ), + .Q(\blk00000003/sig0000065b ), + .Q15(\NLW_blk00000003/blk00000648_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000647 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000065a ), + .Q(\blk00000003/sig000001bb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000646 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000622 ), + .Q(\blk00000003/sig0000065a ), + .Q15(\NLW_blk00000003/blk00000646_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000645 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000659 ), + .Q(\blk00000003/sig000001b9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000644 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000618 ), + .Q(\blk00000003/sig00000659 ), + .Q15(\NLW_blk00000003/blk00000644_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000643 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000658 ), + .Q(\blk00000003/sig000001b8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000642 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061c ), + .Q(\blk00000003/sig00000658 ), + .Q15(\NLW_blk00000003/blk00000642_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000641 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000657 ), + .Q(\blk00000003/sig000001ba ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000640 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000620 ), + .Q(\blk00000003/sig00000657 ), + .Q15(\NLW_blk00000003/blk00000640_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000656 ), + .Q(\blk00000003/sig000001b6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000616 ), + .Q(\blk00000003/sig00000656 ), + .Q15(\NLW_blk00000003/blk0000063e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000655 ), + .Q(\blk00000003/sig000001b5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000614 ), + .Q(\blk00000003/sig00000655 ), + .Q15(\NLW_blk00000003/blk0000063c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000063b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000654 ), + .Q(\blk00000003/sig000001b7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000063a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000061a ), + .Q(\blk00000003/sig00000654 ), + .Q15(\NLW_blk00000003/blk0000063a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000639 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000653 ), + .Q(\blk00000003/sig000001b3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000638 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000612 ), + .Q(\blk00000003/sig00000653 ), + .Q15(\NLW_blk00000003/blk00000638_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000637 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000652 ), + .Q(\blk00000003/sig000001b2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000636 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000610 ), + .Q(\blk00000003/sig00000652 ), + .Q15(\NLW_blk00000003/blk00000636_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000635 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000651 ), + .Q(\blk00000003/sig000001b4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000634 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060e ), + .Q(\blk00000003/sig00000651 ), + .Q15(\NLW_blk00000003/blk00000634_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000633 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000650 ), + .Q(\blk00000003/sig000001b1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000632 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000608 ), + .Q(\blk00000003/sig00000650 ), + .Q15(\NLW_blk00000003/blk00000632_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000631 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064f ), + .Q(\blk00000003/sig000001b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000630 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060c ), + .Q(\blk00000003/sig0000064f ), + .Q15(\NLW_blk00000003/blk00000630_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064e ), + .Q(\blk00000003/sig000001ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000602 ), + .Q(\blk00000003/sig0000064e ), + .Q15(\NLW_blk00000003/blk0000062e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064d ), + .Q(\blk00000003/sig000001ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000606 ), + .Q(\blk00000003/sig0000064d ), + .Q15(\NLW_blk00000003/blk0000062c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000062b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064c ), + .Q(\blk00000003/sig000001af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000062a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000060a ), + .Q(\blk00000003/sig0000064c ), + .Q15(\NLW_blk00000003/blk0000062a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000629 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064b ), + .Q(\blk00000003/sig0000014b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000628 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000600 ), + .Q(\blk00000003/sig0000064b ), + .Q15(\NLW_blk00000003/blk00000628_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000627 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000064a ), + .Q(\blk00000003/sig0000014a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000626 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fe ), + .Q(\blk00000003/sig0000064a ), + .Q15(\NLW_blk00000003/blk00000626_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000625 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000649 ), + .Q(\blk00000003/sig000001ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000624 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000604 ), + .Q(\blk00000003/sig00000649 ), + .Q15(\NLW_blk00000003/blk00000624_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000623 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000648 ), + .Q(\blk00000003/sig00000148 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000622 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fc ), + .Q(\blk00000003/sig00000648 ), + .Q15(\NLW_blk00000003/blk00000622_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000621 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000647 ), + .Q(\blk00000003/sig00000147 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000620 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005fa ), + .Q(\blk00000003/sig00000647 ), + .Q15(\NLW_blk00000003/blk00000620_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000646 ), + .Q(\blk00000003/sig00000149 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f8 ), + .Q(\blk00000003/sig00000646 ), + .Q15(\NLW_blk00000003/blk0000061e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000645 ), + .Q(\blk00000003/sig00000146 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/sig00000645 ), + .Q15(\NLW_blk00000003/blk0000061c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000061b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000644 ), + .Q(\blk00000003/sig00000145 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000061a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/sig00000644 ), + .Q15(\NLW_blk00000003/blk0000061a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000619 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000643 ), + .Q(\blk00000003/sig00000143 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000618 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/sig00000643 ), + .Q15(\NLW_blk00000003/blk00000618_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000617 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000642 ), + .Q(\blk00000003/sig00000142 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000616 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/sig00000642 ), + .Q15(\NLW_blk00000003/blk00000616_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000615 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000641 ), + .Q(\blk00000003/sig00000144 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000614 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/sig00000641 ), + .Q15(\NLW_blk00000003/blk00000614_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000613 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000640 ), + .Q(\blk00000003/sig00000140 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000612 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/sig00000640 ), + .Q15(\NLW_blk00000003/blk00000612_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000611 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063f ), + .Q(\blk00000003/sig0000013f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000610 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/sig0000063f ), + .Q15(\NLW_blk00000003/blk00000610_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/sig00000141 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/sig0000063e ), + .Q15(\NLW_blk00000003/blk0000060e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063d ), + .Q(\blk00000003/sig0000013d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/sig0000063d ), + .Q15(\NLW_blk00000003/blk0000060c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000060b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063c ), + .Q(\blk00000003/sig0000013c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000060a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e4 ), + .Q(\blk00000003/sig0000063c ), + .Q15(\NLW_blk00000003/blk0000060a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000609 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063b ), + .Q(\blk00000003/sig0000013e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000608 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e2 ), + .Q(\blk00000003/sig0000063b ), + .Q15(\NLW_blk00000003/blk00000608_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000607 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000063a ), + .Q(\blk00000003/sig0000013b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000606 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005e0 ), + .Q(\blk00000003/sig0000063a ), + .Q15(\NLW_blk00000003/blk00000606_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000605 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000639 ), + .Q(\blk00000003/sig0000013a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000604 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005de ), + .Q(\blk00000003/sig00000639 ), + .Q15(\NLW_blk00000003/blk00000604_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000603 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000638 ), + .Q(\blk00000003/sig00000138 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000602 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005dc ), + .Q(\blk00000003/sig00000638 ), + .Q15(\NLW_blk00000003/blk00000602_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000601 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000637 ), + .Q(\blk00000003/sig00000137 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000600 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005da ), + .Q(\blk00000003/sig00000637 ), + .Q15(\NLW_blk00000003/blk00000600_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000636 ), + .Q(\blk00000003/sig00000139 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fe ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d8 ), + .Q(\blk00000003/sig00000636 ), + .Q15(\NLW_blk00000003/blk000005fe_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000635 ), + .Q(\blk00000003/sig00000136 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fc ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d6 ), + .Q(\blk00000003/sig00000635 ), + .Q15(\NLW_blk00000003/blk000005fc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000634 ), + .Q(\blk00000003/sig00000135 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005fa ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d4 ), + .Q(\blk00000003/sig00000634 ), + .Q15(\NLW_blk00000003/blk000005fa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000633 ), + .Q(\blk00000003/sig00000134 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f8 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000005d0 ), + .Q(\blk00000003/sig00000633 ), + .Q15(\NLW_blk00000003/blk000005f8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000632 ), + .Q(\blk00000003/sig00000434 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e1 ), + .Q(\blk00000003/sig00000632 ), + .Q15(\NLW_blk00000003/blk000005f6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000631 ), + .Q(\blk00000003/sig0000057a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig000000ae ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001c4 ), + .Q(\blk00000003/sig00000631 ), + .Q15(\NLW_blk00000003/blk000005f4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062f ), + .Q(\blk00000003/sig00000630 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig0000062f ), + .Q15(\NLW_blk00000003/blk000005f2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005f1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062d ), + .Q(\blk00000003/sig0000062e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005f0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig0000062d ), + .Q15(\NLW_blk00000003/blk000005f0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ef ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000062b ), + .Q(\blk00000003/sig0000062c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ee ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig0000062b ), + .Q15(\NLW_blk00000003/blk000005ee_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ed ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000629 ), + .Q(\blk00000003/sig0000062a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ec ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig00000629 ), + .Q15(\NLW_blk00000003/blk000005ec_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005eb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000627 ), + .Q(\blk00000003/sig00000628 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ea ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig00000627 ), + .Q15(\NLW_blk00000003/blk000005ea_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000625 ), + .Q(\blk00000003/sig00000626 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig00000625 ), + .Q15(\NLW_blk00000003/blk000005e8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000623 ), + .Q(\blk00000003/sig00000624 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig00000623 ), + .Q15(\NLW_blk00000003/blk000005e6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000621 ), + .Q(\blk00000003/sig00000622 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig00000621 ), + .Q15(\NLW_blk00000003/blk000005e4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061f ), + .Q(\blk00000003/sig00000620 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig0000061f ), + .Q15(\NLW_blk00000003/blk000005e2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061d ), + .Q(\blk00000003/sig0000061e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig0000061d ), + .Q15(\NLW_blk00000003/blk000005e0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005df ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000061b ), + .Q(\blk00000003/sig0000061c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005de ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig0000061b ), + .Q15(\NLW_blk00000003/blk000005de_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005dd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000619 ), + .Q(\blk00000003/sig0000061a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005dc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig00000619 ), + .Q15(\NLW_blk00000003/blk000005dc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005db ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000617 ), + .Q(\blk00000003/sig00000618 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005da ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig00000617 ), + .Q15(\NLW_blk00000003/blk000005da_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000615 ), + .Q(\blk00000003/sig00000616 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig00000615 ), + .Q15(\NLW_blk00000003/blk000005d8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000613 ), + .Q(\blk00000003/sig00000614 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig00000613 ), + .Q15(\NLW_blk00000003/blk000005d6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000611 ), + .Q(\blk00000003/sig00000612 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig00000611 ), + .Q15(\NLW_blk00000003/blk000005d4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060f ), + .Q(\blk00000003/sig00000610 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig0000060f ), + .Q15(\NLW_blk00000003/blk000005d2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005d1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060d ), + .Q(\blk00000003/sig0000060e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005d0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig0000060d ), + .Q15(\NLW_blk00000003/blk000005d0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig0000060b ), + .Q(\blk00000003/sig0000060c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ce ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig0000060b ), + .Q15(\NLW_blk00000003/blk000005ce_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000609 ), + .Q(\blk00000003/sig0000060a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005cc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig00000609 ), + .Q15(\NLW_blk00000003/blk000005cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005cb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000607 ), + .Q(\blk00000003/sig00000608 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ca ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig00000607 ), + .Q15(\NLW_blk00000003/blk000005ca_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000605 ), + .Q(\blk00000003/sig00000606 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig00000605 ), + .Q15(\NLW_blk00000003/blk000005c8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000603 ), + .Q(\blk00000003/sig00000604 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig00000603 ), + .Q15(\NLW_blk00000003/blk000005c6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig00000601 ), + .Q(\blk00000003/sig00000602 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig00000601 ), + .Q15(\NLW_blk00000003/blk000005c4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ff ), + .Q(\blk00000003/sig00000600 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005ff ), + .Q15(\NLW_blk00000003/blk000005c2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005c1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fd ), + .Q(\blk00000003/sig000005fe ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005c0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005fd ), + .Q15(\NLW_blk00000003/blk000005c0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bf ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005fb ), + .Q(\blk00000003/sig000005fc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005be ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005fb ), + .Q15(\NLW_blk00000003/blk000005be_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bd ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f9 ), + .Q(\blk00000003/sig000005fa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005bc ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005f9 ), + .Q15(\NLW_blk00000003/blk000005bc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005bb ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f7 ), + .Q(\blk00000003/sig000005f8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ba ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005f7 ), + .Q15(\NLW_blk00000003/blk000005ba_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/sig000005f6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005f5 ), + .Q15(\NLW_blk00000003/blk000005b8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/sig000005f4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005f3 ), + .Q15(\NLW_blk00000003/blk000005b6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/sig000005f2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005f1 ), + .Q15(\NLW_blk00000003/blk000005b4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/sig000005f0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005ef ), + .Q15(\NLW_blk00000003/blk000005b2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/sig000005ee ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ed ), + .Q15(\NLW_blk00000003/blk000005b0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005af ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/sig000005ec ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ae ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005eb ), + .Q15(\NLW_blk00000003/blk000005ae_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ad ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/sig000005ea ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ac ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005e9 ), + .Q15(\NLW_blk00000003/blk000005ac_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ab ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/sig000005e8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005aa ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005e7 ), + .Q15(\NLW_blk00000003/blk000005aa_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a9 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/sig000005e6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a8 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005e5 ), + .Q15(\NLW_blk00000003/blk000005a8_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a7 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e3 ), + .Q(\blk00000003/sig000005e4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a6 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005e3 ), + .Q15(\NLW_blk00000003/blk000005a6_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a5 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005e1 ), + .Q(\blk00000003/sig000005e2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a4 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005e1 ), + .Q15(\NLW_blk00000003/blk000005a4_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a3 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005df ), + .Q(\blk00000003/sig000005e0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a2 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005df ), + .Q15(\NLW_blk00000003/blk000005a2_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005a1 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005dd ), + .Q(\blk00000003/sig000005de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005a0 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005dd ), + .Q15(\NLW_blk00000003/blk000005a0_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059f ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005db ), + .Q(\blk00000003/sig000005dc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005db ), + .Q15(\NLW_blk00000003/blk0000059e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059d ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d9 ), + .Q(\blk00000003/sig000005da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005d9 ), + .Q15(\NLW_blk00000003/blk0000059c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000059b ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d7 ), + .Q(\blk00000003/sig000005d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000059a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005d7 ), + .Q15(\NLW_blk00000003/blk0000059a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d5 ), + .Q(\blk00000003/sig000005d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000598 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005d5 ), + .Q15(\NLW_blk00000003/blk00000598_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000597 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005d3 ), + .Q(\blk00000003/sig000005d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000596 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005d3 ), + .Q15(\NLW_blk00000003/blk00000596_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000595 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d2 ), + .Q(\blk00000003/sig00000581 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000594 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000435 ), + .Q(\blk00000003/sig000005d2 ), + .Q15(\NLW_blk00000003/blk00000594_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000593 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005d1 ), + .Q(\blk00000003/sig00000480 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000592 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000219 ), + .Q(\blk00000003/sig000005d1 ), + .Q15(\NLW_blk00000003/blk00000592_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000591 ( + .C(clk), + .CE(\blk00000003/sig00000582 ), + .D(\blk00000003/sig000005cf ), + .Q(\blk00000003/sig000005d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000590 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig000000ae ), + .CE(\blk00000003/sig00000582 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig000005cf ), + .Q15(\NLW_blk00000003/blk00000590_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ce ), + .Q(\blk00000003/sig0000047e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000217 ), + .Q(\blk00000003/sig000005ce ), + .Q15(\NLW_blk00000003/blk0000058e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cd ), + .Q(\blk00000003/sig0000047d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000216 ), + .Q(\blk00000003/sig000005cd ), + .Q15(\NLW_blk00000003/blk0000058c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000058b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cc ), + .Q(\blk00000003/sig0000047f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000058a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000218 ), + .Q(\blk00000003/sig000005cc ), + .Q15(\NLW_blk00000003/blk0000058a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000589 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005cb ), + .Q(\blk00000003/sig0000047b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000588 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000214 ), + .Q(\blk00000003/sig000005cb ), + .Q15(\NLW_blk00000003/blk00000588_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000587 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ca ), + .Q(\blk00000003/sig0000047a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000586 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000213 ), + .Q(\blk00000003/sig000005ca ), + .Q15(\NLW_blk00000003/blk00000586_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000585 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c9 ), + .Q(\blk00000003/sig0000047c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000584 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000215 ), + .Q(\blk00000003/sig000005c9 ), + .Q15(\NLW_blk00000003/blk00000584_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000583 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c8 ), + .Q(\blk00000003/sig00000479 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000582 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000212 ), + .Q(\blk00000003/sig000005c8 ), + .Q15(\NLW_blk00000003/blk00000582_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000581 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c7 ), + .Q(\blk00000003/sig00000478 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000580 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000211 ), + .Q(\blk00000003/sig000005c7 ), + .Q15(\NLW_blk00000003/blk00000580_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c6 ), + .Q(\blk00000003/sig00000476 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020f ), + .Q(\blk00000003/sig000005c6 ), + .Q15(\NLW_blk00000003/blk0000057e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c5 ), + .Q(\blk00000003/sig00000475 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020e ), + .Q(\blk00000003/sig000005c5 ), + .Q15(\NLW_blk00000003/blk0000057c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000057b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c4 ), + .Q(\blk00000003/sig00000477 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000057a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000210 ), + .Q(\blk00000003/sig000005c4 ), + .Q15(\NLW_blk00000003/blk0000057a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000579 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c3 ), + .Q(\blk00000003/sig00000473 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000578 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020c ), + .Q(\blk00000003/sig000005c3 ), + .Q15(\NLW_blk00000003/blk00000578_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000577 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c2 ), + .Q(\blk00000003/sig00000472 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000576 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020b ), + .Q(\blk00000003/sig000005c2 ), + .Q15(\NLW_blk00000003/blk00000576_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000575 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c1 ), + .Q(\blk00000003/sig00000474 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000574 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020d ), + .Q(\blk00000003/sig000005c1 ), + .Q15(\NLW_blk00000003/blk00000574_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000573 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005c0 ), + .Q(\blk00000003/sig00000470 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000572 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000209 ), + .Q(\blk00000003/sig000005c0 ), + .Q15(\NLW_blk00000003/blk00000572_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000571 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bf ), + .Q(\blk00000003/sig0000046f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000570 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000208 ), + .Q(\blk00000003/sig000005bf ), + .Q15(\NLW_blk00000003/blk00000570_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005be ), + .Q(\blk00000003/sig00000471 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig0000020a ), + .Q(\blk00000003/sig000005be ), + .Q15(\NLW_blk00000003/blk0000056e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bd ), + .Q(\blk00000003/sig0000046e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000207 ), + .Q(\blk00000003/sig000005bd ), + .Q15(\NLW_blk00000003/blk0000056c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000056b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/sig0000046d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000056a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000206 ), + .Q(\blk00000003/sig000005bc ), + .Q15(\NLW_blk00000003/blk0000056a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000569 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005bb ), + .Q(\blk00000003/sig0000046b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000568 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000204 ), + .Q(\blk00000003/sig000005bb ), + .Q15(\NLW_blk00000003/blk00000568_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000567 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/sig0000046a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000566 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000203 ), + .Q(\blk00000003/sig000005ba ), + .Q15(\NLW_blk00000003/blk00000566_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000565 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b9 ), + .Q(\blk00000003/sig0000046c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000564 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000205 ), + .Q(\blk00000003/sig000005b9 ), + .Q15(\NLW_blk00000003/blk00000564_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000563 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/sig000004b0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000562 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000201 ), + .Q(\blk00000003/sig000005b8 ), + .Q15(\NLW_blk00000003/blk00000562_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000561 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/sig000004af ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000560 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000200 ), + .Q(\blk00000003/sig000005b7 ), + .Q15(\NLW_blk00000003/blk00000560_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/sig00000469 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig00000202 ), + .Q(\blk00000003/sig000005b6 ), + .Q15(\NLW_blk00000003/blk0000055e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/sig000004ad ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fe ), + .Q(\blk00000003/sig000005b5 ), + .Q15(\NLW_blk00000003/blk0000055c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000055b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/sig000004ac ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000055a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fd ), + .Q(\blk00000003/sig000005b4 ), + .Q15(\NLW_blk00000003/blk0000055a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000559 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/sig000004ae ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000558 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ff ), + .Q(\blk00000003/sig000005b3 ), + .Q15(\NLW_blk00000003/blk00000558_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000557 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/sig000004ab ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000556 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fc ), + .Q(\blk00000003/sig000005b2 ), + .Q15(\NLW_blk00000003/blk00000556_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000555 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/sig000004aa ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000554 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fb ), + .Q(\blk00000003/sig000005b1 ), + .Q15(\NLW_blk00000003/blk00000554_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000553 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/sig000004a8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000552 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f9 ), + .Q(\blk00000003/sig000005b0 ), + .Q15(\NLW_blk00000003/blk00000552_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000551 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/sig000004a7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000550 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/sig000005af ), + .Q15(\NLW_blk00000003/blk00000550_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/sig000004a9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001fa ), + .Q(\blk00000003/sig000005ae ), + .Q15(\NLW_blk00000003/blk0000054e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/sig000004a6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/sig000005ad ), + .Q15(\NLW_blk00000003/blk0000054c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000054b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/sig000004a5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000054a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/sig000005ac ), + .Q15(\NLW_blk00000003/blk0000054a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000549 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/sig000004a3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000548 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/sig000005ab ), + .Q15(\NLW_blk00000003/blk00000548_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000547 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/sig000004a2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000546 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/sig000005aa ), + .Q15(\NLW_blk00000003/blk00000546_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000545 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/sig000004a4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000544 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/sig000005a9 ), + .Q15(\NLW_blk00000003/blk00000544_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000543 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/sig000004a1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000542 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/sig000005a8 ), + .Q15(\NLW_blk00000003/blk00000542_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000541 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/sig000004a0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000540 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/sig000005a7 ), + .Q15(\NLW_blk00000003/blk00000540_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/sig0000049e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/sig000005a6 ), + .Q15(\NLW_blk00000003/blk0000053e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/sig0000049d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053c ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/sig000005a5 ), + .Q15(\NLW_blk00000003/blk0000053c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/sig0000049f ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000053a ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/sig000005a4 ), + .Q15(\NLW_blk00000003/blk0000053a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/sig0000049b ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000538 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/sig000005a3 ), + .Q15(\NLW_blk00000003/blk00000538_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/sig0000049a ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000536 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/sig000005a2 ), + .Q15(\NLW_blk00000003/blk00000536_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/sig0000049c ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000534 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/sig000005a1 ), + .Q15(\NLW_blk00000003/blk00000534_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/sig000002de ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000532 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d6 ), + .Q(\blk00000003/sig000005a0 ), + .Q15(\NLW_blk00000003/blk00000532_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/sig000002df ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000530 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000002b9 ), + .Q(\blk00000003/sig0000059f ), + .Q15(\NLW_blk00000003/blk00000530_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/sig00000499 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052e ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/sig0000059e ), + .Q15(\NLW_blk00000003/blk0000052e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/sig00000580 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig000000ae ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d2 ), + .Q(\blk00000003/sig0000059d ), + .Q15(\NLW_blk00000003/blk0000052c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/sig000004da ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000052a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[0]), + .Q(\blk00000003/sig0000059c ), + .Q15(\NLW_blk00000003/blk0000052a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000529 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/sig000004d8 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000528 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[2]), + .Q(\blk00000003/sig0000059b ), + .Q15(\NLW_blk00000003/blk00000528_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000527 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/sig000004d7 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000526 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[3]), + .Q(\blk00000003/sig0000059a ), + .Q15(\NLW_blk00000003/blk00000526_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000525 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/sig000004d9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000524 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[1]), + .Q(\blk00000003/sig00000599 ), + .Q15(\NLW_blk00000003/blk00000524_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000523 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/sig000004d5 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000522 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[5]), + .Q(\blk00000003/sig00000598 ), + .Q15(\NLW_blk00000003/blk00000522_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000521 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/sig000004d4 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000520 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[6]), + .Q(\blk00000003/sig00000597 ), + .Q15(\NLW_blk00000003/blk00000520_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/sig000004d6 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[4]), + .Q(\blk00000003/sig00000596 ), + .Q15(\NLW_blk00000003/blk0000051e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/sig000004d2 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[8]), + .Q(\blk00000003/sig00000595 ), + .Q15(\NLW_blk00000003/blk0000051c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000051b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000594 ), + .Q(\blk00000003/sig000004d1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000051a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[9]), + .Q(\blk00000003/sig00000594 ), + .Q15(\NLW_blk00000003/blk0000051a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000519 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000593 ), + .Q(\blk00000003/sig000004d3 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000518 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[7]), + .Q(\blk00000003/sig00000593 ), + .Q15(\NLW_blk00000003/blk00000518_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000517 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000592 ), + .Q(\blk00000003/sig000004d0 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000516 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[10]), + .Q(\blk00000003/sig00000592 ), + .Q15(\NLW_blk00000003/blk00000516_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000515 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000591 ), + .Q(\blk00000003/sig000004cf ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000514 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[11]), + .Q(\blk00000003/sig00000591 ), + .Q15(\NLW_blk00000003/blk00000514_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000513 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000590 ), + .Q(\blk00000003/sig000004cd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000512 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[13]), + .Q(\blk00000003/sig00000590 ), + .Q15(\NLW_blk00000003/blk00000512_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000511 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058f ), + .Q(\blk00000003/sig000004cc ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000510 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[14]), + .Q(\blk00000003/sig0000058f ), + .Q15(\NLW_blk00000003/blk00000510_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058e ), + .Q(\blk00000003/sig000004ce ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050e ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[12]), + .Q(\blk00000003/sig0000058e ), + .Q15(\NLW_blk00000003/blk0000050e_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058d ), + .Q(\blk00000003/sig000004ca ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050c ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[16]), + .Q(\blk00000003/sig0000058d ), + .Q15(\NLW_blk00000003/blk0000050c_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000050b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058c ), + .Q(\blk00000003/sig000004c9 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000050a ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[17]), + .Q(\blk00000003/sig0000058c ), + .Q15(\NLW_blk00000003/blk0000050a_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000509 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058b ), + .Q(\blk00000003/sig000004cb ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(coef_din_0[15]), + .Q(\blk00000003/sig0000058b ), + .Q15(\NLW_blk00000003/blk00000508_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000507 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000058a ), + .Q(\blk00000003/sig000001e1 ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000506 ( + .A0(\blk00000003/sig000000ae ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig00000049 ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001e3 ), + .Q(\blk00000003/sig0000058a ), + .Q15(\NLW_blk00000003/blk00000506_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000505 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000589 ), + .Q(\blk00000003/sig0000042e ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000504 ( + .A0(\blk00000003/sig00000049 ), + .A1(\blk00000003/sig00000049 ), + .A2(\blk00000003/sig000000ae ), + .A3(\blk00000003/sig00000049 ), + .CE(ce), + .CLK(clk), + .D(\blk00000003/sig000001d8 ), + .Q(\blk00000003/sig00000589 ), + .Q15(\NLW_blk00000003/blk00000504_Q15_UNCONNECTED ) + ); + INV \blk00000003/blk00000503 ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000288 ) + ); + INV \blk00000003/blk00000502 ( + .I(\blk00000003/sig00000291 ), + .O(\blk00000003/sig00000281 ) + ); + INV \blk00000003/blk00000501 ( + .I(\blk00000003/sig000001cf ), + .O(\blk00000003/sig00000296 ) + ); + INV \blk00000003/blk00000500 ( + .I(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000287 ) + ); + INV \blk00000003/blk000004ff ( + .I(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000578 ) + ); + INV \blk00000003/blk000004fe ( + .I(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000299 ) + ); + INV \blk00000003/blk000004fd ( + .I(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000282 ) + ); + INV \blk00000003/blk000004fc ( + .I(\blk00000003/sig0000021d ), + .O(\blk00000003/sig00000245 ) + ); + INV \blk00000003/blk000004fb ( + .I(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000227 ) + ); + INV \blk00000003/blk000004fa ( + .I(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000b9 ) + ); + INV \blk00000003/blk000004f9 ( + .I(\blk00000003/sig000000b6 ), + .O(\blk00000003/sig000000b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig0000057c ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004f7 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000236 ), + .I2(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000249 ) + ); + LUT5 #( + .INIT ( 32'h4F444444 )) + \blk00000003/blk000004f6 ( + .I0(\blk00000003/sig0000024a ), + .I1(\blk00000003/sig0000023e ), + .I2(\blk00000003/sig0000024d ), + .I3(coef_ld), + .I4(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000241 ) + ); + LUT4 #( + .INIT ( 16'h1000 )) + \blk00000003/blk000004f5 ( + .I0(coef_ld), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000248 ) + ); + LUT5 #( + .INIT ( 32'h20AA2020 )) + \blk00000003/blk000004f4 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(\blk00000003/sig0000024d ), + .I4(coef_ld), + .O(\blk00000003/sig00000247 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f3 ( + .I0(\blk00000003/sig00000291 ), + .I1(ce), + .I2(\blk00000003/sig0000023e ), + .I3(\blk00000003/sig0000021b ), + .O(\blk00000003/sig00000588 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f2 ( + .I0(\blk00000003/sig00000298 ), + .I1(ce), + .I2(\blk00000003/sig0000023c ), + .I3(\blk00000003/sig00000289 ), + .O(\blk00000003/sig00000587 ) + ); + LUT4 #( + .INIT ( 16'hEA2A )) + \blk00000003/blk000004f1 ( + .I0(\blk00000003/sig0000057b ), + .I1(ce), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig00000585 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004f0 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/sig0000057f ), + .O(\blk00000003/sig00000584 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk000004ef ( + .I0(ce), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000583 ) + ); + LUT5 #( + .INIT ( 32'h6AAAAAAA )) + \blk00000003/blk000004ee ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000002a2 ), + .I2(ce), + .I3(nd), + .I4(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig00000586 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ed ( + .C(clk), + .D(\blk00000003/sig00000588 ), + .Q(\blk00000003/sig00000291 ) + ); + FD #( + .INIT ( 1'b1 )) + \blk00000003/blk000004ec ( + .C(clk), + .D(\blk00000003/sig00000587 ), + .Q(\blk00000003/sig00000298 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004eb ( + .C(clk), + .D(\blk00000003/sig00000586 ), + .R(sclr), + .Q(\blk00000003/sig0000057e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ea ( + .C(clk), + .D(\blk00000003/sig00000585 ), + .R(sclr), + .Q(\blk00000003/sig0000057b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e9 ( + .I0(\blk00000003/sig00000500 ), + .O(\blk00000003/sig000004fb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e8 ( + .I0(\blk00000003/sig000004ff ), + .O(\blk00000003/sig000004f8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e7 ( + .I0(\blk00000003/sig000004fe ), + .O(\blk00000003/sig000004f5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e6 ( + .I0(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004f2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e5 ( + .I0(\blk00000003/sig000002da ), + .O(\blk00000003/sig000002db ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e4 ( + .I0(\blk00000003/sig000002d7 ), + .O(\blk00000003/sig000002d8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e3 ( + .I0(\blk00000003/sig000002d3 ), + .O(\blk00000003/sig000002d4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e2 ( + .I0(\blk00000003/sig000002b7 ), + .O(\blk00000003/sig000002b1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e1 ( + .I0(\blk00000003/sig0000057e ), + .O(\blk00000003/sig000002a7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004e0 ( + .I0(\blk00000003/sig0000029f ), + .O(\blk00000003/sig0000029d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004df ( + .I0(\blk00000003/sig00000271 ), + .O(\blk00000003/sig00000272 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004de ( + .I0(\blk00000003/sig0000026e ), + .O(\blk00000003/sig0000026f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dd ( + .I0(\blk00000003/sig0000026a ), + .O(\blk00000003/sig0000026b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004dc ( + .I0(\blk00000003/sig00000260 ), + .O(\blk00000003/sig0000025d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004db ( + .I0(\blk00000003/sig0000025f ), + .O(\blk00000003/sig0000025a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004da ( + .I0(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000252 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d9 ( + .I0(\blk00000003/sig00000254 ), + .O(\blk00000003/sig0000024f ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk000004d8 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d7 ( + .I0(\blk00000003/sig00000267 ), + .O(\blk00000003/sig00000229 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000004d6 ( + .I0(\blk00000003/sig000001cd ), + .O(\blk00000003/sig000000ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000572 ), + .R(sclr), + .Q(\blk00000003/sig00000577 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056f ), + .R(sclr), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000056c ), + .R(sclr), + .Q(\blk00000003/sig00000575 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000569 ), + .R(sclr), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000566 ), + .R(sclr), + .Q(\blk00000003/sig00000573 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f0 ), + .S(sclr), + .Q(\blk00000003/sig00000501 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004fc ), + .S(sclr), + .Q(\blk00000003/sig00000500 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f9 ), + .R(sclr), + .Q(\blk00000003/sig000004ff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f6 ), + .R(sclr), + .Q(\blk00000003/sig000004fe ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000004f3 ), + .S(sclr), + .Q(\blk00000003/sig000004fd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dd ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002dc ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d6 ), + .R(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002d3 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c8 ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d1 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ce ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002d0 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cb ), + .S(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bc ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c2 ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002bf ), + .R(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002c4 ) + ); + FDR \blk00000003/blk000004c2 ( + .C(clk), + .D(\blk00000003/sig00000584 ), + .R(ce), + .Q(\blk00000003/sig0000057f ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000004c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b2 ), + .S(sclr), + .Q(\blk00000003/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b5 ), + .R(sclr), + .Q(\blk00000003/sig000002b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002ac ), + .R(sclr), + .Q(\blk00000003/sig000001e9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002af ), + .R(sclr), + .Q(\blk00000003/sig000001e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029b ), + .R(sclr), + .Q(\blk00000003/sig000002a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000029e ), + .R(sclr), + .Q(\blk00000003/sig0000029f ) + ); + FDR \blk00000003/blk000004bb ( + .C(clk), + .D(\blk00000003/sig00000583 ), + .R(ce), + .Q(\blk00000003/sig0000057d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000274 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig00000271 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000273 ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026d ), + .R(\blk00000003/sig00000277 ), + .Q(\blk00000003/sig0000026a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000266 ), + .R(coef_ld), + .Q(\blk00000003/sig00000267 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000262 ), + .R(sclr), + .Q(\blk00000003/sig00000263 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025e ), + .R(sclr), + .Q(\blk00000003/sig00000260 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000025b ), + .R(sclr), + .Q(\blk00000003/sig0000025f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000257 ), + .R(coef_ld), + .Q(\blk00000003/sig00000258 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000253 ), + .R(coef_ld), + .Q(\blk00000003/sig00000255 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000250 ), + .R(coef_ld), + .Q(\blk00000003/sig00000254 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004b0 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000565 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004af ( + .I0(\blk00000003/sig00000574 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000568 ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ae ( + .I0(\blk00000003/sig00000575 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056b ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk000004ad ( + .I0(\blk00000003/sig00000576 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig0000056e ) + ); + LUT3 #( + .INIT ( 8'hDE )) + \blk00000003/blk000004ac ( + .I0(\blk00000003/sig00000577 ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig000001df ), + .O(\blk00000003/sig00000571 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk000004ab ( + .I0(\blk00000003/sig000001df ), + .I1(\blk00000003/sig0000004a ), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig00000563 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004aa ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000104 ), + .I3(NlwRenamedSig_OI_dout_2[47]), + .O(\blk00000003/sig00000562 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a9 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000105 ), + .I3(NlwRenamedSig_OI_dout_2[46]), + .O(\blk00000003/sig00000561 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a8 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000107 ), + .I3(NlwRenamedSig_OI_dout_2[44]), + .O(\blk00000003/sig0000055f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a7 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000106 ), + .I3(NlwRenamedSig_OI_dout_2[45]), + .O(\blk00000003/sig00000560 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a6 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000108 ), + .I3(NlwRenamedSig_OI_dout_2[43]), + .O(\blk00000003/sig0000055e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a5 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010a ), + .I3(NlwRenamedSig_OI_dout_2[41]), + .O(\blk00000003/sig0000055c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a4 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000109 ), + .I3(NlwRenamedSig_OI_dout_2[42]), + .O(\blk00000003/sig0000055d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a3 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010b ), + .I3(NlwRenamedSig_OI_dout_2[40]), + .O(\blk00000003/sig0000055b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a2 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010d ), + .I3(NlwRenamedSig_OI_dout_2[38]), + .O(\blk00000003/sig00000559 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a1 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010c ), + .I3(NlwRenamedSig_OI_dout_2[39]), + .O(\blk00000003/sig0000055a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk000004a0 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010e ), + .I3(NlwRenamedSig_OI_dout_2[37]), + .O(\blk00000003/sig00000558 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000110 ), + .I3(NlwRenamedSig_OI_dout_2[35]), + .O(\blk00000003/sig00000556 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000010f ), + .I3(NlwRenamedSig_OI_dout_2[36]), + .O(\blk00000003/sig00000557 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000111 ), + .I3(NlwRenamedSig_OI_dout_2[34]), + .O(\blk00000003/sig00000555 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000113 ), + .I3(NlwRenamedSig_OI_dout_2[32]), + .O(\blk00000003/sig00000553 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000112 ), + .I3(NlwRenamedSig_OI_dout_2[33]), + .O(\blk00000003/sig00000554 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000049a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000114 ), + .I3(NlwRenamedSig_OI_dout_2[31]), + .O(\blk00000003/sig00000552 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000499 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000116 ), + .I3(NlwRenamedSig_OI_dout_2[29]), + .O(\blk00000003/sig00000550 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000498 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000115 ), + .I3(NlwRenamedSig_OI_dout_2[30]), + .O(\blk00000003/sig00000551 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000497 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000117 ), + .I3(NlwRenamedSig_OI_dout_2[28]), + .O(\blk00000003/sig0000054f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000496 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000119 ), + .I3(NlwRenamedSig_OI_dout_2[26]), + .O(\blk00000003/sig0000054d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000495 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000118 ), + .I3(NlwRenamedSig_OI_dout_2[27]), + .O(\blk00000003/sig0000054e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000494 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011a ), + .I3(NlwRenamedSig_OI_dout_2[25]), + .O(\blk00000003/sig0000054c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000493 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011c ), + .I3(NlwRenamedSig_OI_dout_2[23]), + .O(\blk00000003/sig0000054a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000492 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011b ), + .I3(NlwRenamedSig_OI_dout_2[24]), + .O(\blk00000003/sig0000054b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000491 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011d ), + .I3(NlwRenamedSig_OI_dout_2[22]), + .O(\blk00000003/sig00000549 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000490 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011f ), + .I3(NlwRenamedSig_OI_dout_2[20]), + .O(\blk00000003/sig00000547 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000011e ), + .I3(NlwRenamedSig_OI_dout_2[21]), + .O(\blk00000003/sig00000548 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000120 ), + .I3(NlwRenamedSig_OI_dout_2[19]), + .O(\blk00000003/sig00000546 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000122 ), + .I3(NlwRenamedSig_OI_dout_2[17]), + .O(\blk00000003/sig00000544 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000121 ), + .I3(NlwRenamedSig_OI_dout_2[18]), + .O(\blk00000003/sig00000545 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000123 ), + .I3(NlwRenamedSig_OI_dout_2[16]), + .O(\blk00000003/sig00000543 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000048a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000125 ), + .I3(NlwRenamedSig_OI_dout_2[14]), + .O(\blk00000003/sig00000541 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000489 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000124 ), + .I3(NlwRenamedSig_OI_dout_2[15]), + .O(\blk00000003/sig00000542 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000488 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000126 ), + .I3(NlwRenamedSig_OI_dout_2[13]), + .O(\blk00000003/sig00000540 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000487 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000128 ), + .I3(NlwRenamedSig_OI_dout_2[11]), + .O(\blk00000003/sig0000053e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000486 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000127 ), + .I3(NlwRenamedSig_OI_dout_2[12]), + .O(\blk00000003/sig0000053f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000485 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000129 ), + .I3(NlwRenamedSig_OI_dout_2[10]), + .O(\blk00000003/sig0000053d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000484 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012b ), + .I3(NlwRenamedSig_OI_dout_2[8]), + .O(\blk00000003/sig0000053b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000483 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012a ), + .I3(NlwRenamedSig_OI_dout_2[9]), + .O(\blk00000003/sig0000053c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000482 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012c ), + .I3(NlwRenamedSig_OI_dout_2[7]), + .O(\blk00000003/sig0000053a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000481 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012e ), + .I3(NlwRenamedSig_OI_dout_2[5]), + .O(\blk00000003/sig00000538 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000480 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012d ), + .I3(NlwRenamedSig_OI_dout_2[6]), + .O(\blk00000003/sig00000539 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000012f ), + .I3(NlwRenamedSig_OI_dout_2[4]), + .O(\blk00000003/sig00000537 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000131 ), + .I3(NlwRenamedSig_OI_dout_2[2]), + .O(\blk00000003/sig00000535 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000130 ), + .I3(NlwRenamedSig_OI_dout_2[3]), + .O(\blk00000003/sig00000536 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000132 ), + .I3(NlwRenamedSig_OI_dout_2[1]), + .O(\blk00000003/sig00000534 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000133 ), + .I3(NlwRenamedSig_OI_dout_2[0]), + .O(\blk00000003/sig00000533 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000047a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017c ), + .I3(NlwRenamedSig_OI_dout_1[47]), + .O(\blk00000003/sig00000532 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000479 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017e ), + .I3(NlwRenamedSig_OI_dout_1[45]), + .O(\blk00000003/sig00000530 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000478 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017d ), + .I3(NlwRenamedSig_OI_dout_1[46]), + .O(\blk00000003/sig00000531 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000477 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000017f ), + .I3(NlwRenamedSig_OI_dout_1[44]), + .O(\blk00000003/sig0000052f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000476 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000181 ), + .I3(NlwRenamedSig_OI_dout_1[42]), + .O(\blk00000003/sig0000052d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000475 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000180 ), + .I3(NlwRenamedSig_OI_dout_1[43]), + .O(\blk00000003/sig0000052e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000474 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000182 ), + .I3(NlwRenamedSig_OI_dout_1[41]), + .O(\blk00000003/sig0000052c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000473 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000184 ), + .I3(NlwRenamedSig_OI_dout_1[39]), + .O(\blk00000003/sig0000052a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000472 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000183 ), + .I3(NlwRenamedSig_OI_dout_1[40]), + .O(\blk00000003/sig0000052b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000471 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000185 ), + .I3(NlwRenamedSig_OI_dout_1[38]), + .O(\blk00000003/sig00000529 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000470 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000187 ), + .I3(NlwRenamedSig_OI_dout_1[36]), + .O(\blk00000003/sig00000527 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000186 ), + .I3(NlwRenamedSig_OI_dout_1[37]), + .O(\blk00000003/sig00000528 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000188 ), + .I3(NlwRenamedSig_OI_dout_1[35]), + .O(\blk00000003/sig00000526 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018a ), + .I3(NlwRenamedSig_OI_dout_1[33]), + .O(\blk00000003/sig00000524 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000189 ), + .I3(NlwRenamedSig_OI_dout_1[34]), + .O(\blk00000003/sig00000525 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018b ), + .I3(NlwRenamedSig_OI_dout_1[32]), + .O(\blk00000003/sig00000523 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000046a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018d ), + .I3(NlwRenamedSig_OI_dout_1[30]), + .O(\blk00000003/sig00000521 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000469 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018c ), + .I3(NlwRenamedSig_OI_dout_1[31]), + .O(\blk00000003/sig00000522 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000468 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018e ), + .I3(NlwRenamedSig_OI_dout_1[29]), + .O(\blk00000003/sig00000520 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000467 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000190 ), + .I3(NlwRenamedSig_OI_dout_1[27]), + .O(\blk00000003/sig0000051e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000466 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000018f ), + .I3(NlwRenamedSig_OI_dout_1[28]), + .O(\blk00000003/sig0000051f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000465 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000191 ), + .I3(NlwRenamedSig_OI_dout_1[26]), + .O(\blk00000003/sig0000051d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000464 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000193 ), + .I3(NlwRenamedSig_OI_dout_1[24]), + .O(\blk00000003/sig0000051b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000463 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000192 ), + .I3(NlwRenamedSig_OI_dout_1[25]), + .O(\blk00000003/sig0000051c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000462 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000194 ), + .I3(NlwRenamedSig_OI_dout_1[23]), + .O(\blk00000003/sig0000051a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000461 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000196 ), + .I3(NlwRenamedSig_OI_dout_1[21]), + .O(\blk00000003/sig00000518 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000460 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000195 ), + .I3(NlwRenamedSig_OI_dout_1[22]), + .O(\blk00000003/sig00000519 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000197 ), + .I3(NlwRenamedSig_OI_dout_1[20]), + .O(\blk00000003/sig00000517 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000199 ), + .I3(NlwRenamedSig_OI_dout_1[18]), + .O(\blk00000003/sig00000515 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig00000198 ), + .I3(NlwRenamedSig_OI_dout_1[19]), + .O(\blk00000003/sig00000516 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019a ), + .I3(NlwRenamedSig_OI_dout_1[17]), + .O(\blk00000003/sig00000514 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019c ), + .I3(NlwRenamedSig_OI_dout_1[15]), + .O(\blk00000003/sig00000512 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000045a ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019b ), + .I3(NlwRenamedSig_OI_dout_1[16]), + .O(\blk00000003/sig00000513 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000459 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019d ), + .I3(NlwRenamedSig_OI_dout_1[14]), + .O(\blk00000003/sig00000511 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000458 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019f ), + .I3(NlwRenamedSig_OI_dout_1[12]), + .O(\blk00000003/sig0000050f ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000457 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig0000019e ), + .I3(NlwRenamedSig_OI_dout_1[13]), + .O(\blk00000003/sig00000510 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000456 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a0 ), + .I3(NlwRenamedSig_OI_dout_1[11]), + .O(\blk00000003/sig0000050e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000455 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a2 ), + .I3(NlwRenamedSig_OI_dout_1[9]), + .O(\blk00000003/sig0000050c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000454 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a1 ), + .I3(NlwRenamedSig_OI_dout_1[10]), + .O(\blk00000003/sig0000050d ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000453 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a3 ), + .I3(NlwRenamedSig_OI_dout_1[8]), + .O(\blk00000003/sig0000050b ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000452 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a5 ), + .I3(NlwRenamedSig_OI_dout_1[6]), + .O(\blk00000003/sig00000509 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000451 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a4 ), + .I3(NlwRenamedSig_OI_dout_1[7]), + .O(\blk00000003/sig0000050a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000450 ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a6 ), + .I3(NlwRenamedSig_OI_dout_1[5]), + .O(\blk00000003/sig00000508 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044f ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a8 ), + .I3(NlwRenamedSig_OI_dout_1[3]), + .O(\blk00000003/sig00000506 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044e ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a7 ), + .I3(NlwRenamedSig_OI_dout_1[4]), + .O(\blk00000003/sig00000507 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044d ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001a9 ), + .I3(NlwRenamedSig_OI_dout_1[2]), + .O(\blk00000003/sig00000505 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044c ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001ab ), + .I3(NlwRenamedSig_OI_dout_1[0]), + .O(\blk00000003/sig00000503 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk0000044b ( + .I0(\blk00000003/sig000001cd ), + .I1(\blk00000003/sig000001df ), + .I2(\blk00000003/sig000001aa ), + .I3(NlwRenamedSig_OI_dout_1[1]), + .O(\blk00000003/sig00000504 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000044a ( + .I0(\blk00000003/sig00000501 ), + .I1(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000004ef ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000449 ( + .I0(ce), + .I1(\blk00000003/sig000001e1 ), + .O(\blk00000003/sig00000582 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000448 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/sig000004ee ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000447 ( + .I0(ce), + .I1(\blk00000003/sig00000581 ), + .O(\blk00000003/sig000004ed ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000446 ( + .I0(\blk00000003/sig000002cf ), + .I1(\blk00000003/sig000002de ), + .O(\blk00000003/sig000002ca ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000445 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d1 ), + .O(\blk00000003/sig000002c7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000444 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig000002d0 ), + .O(\blk00000003/sig000002cd ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000443 ( + .I0(\blk00000003/sig000002de ), + .I1(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002c3 ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk00000442 ( + .I0(\blk00000003/sig000002c4 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig00000580 ), + .O(\blk00000003/sig000002be ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000441 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c5 ), + .O(\blk00000003/sig000002c1 ) + ); + LUT3 #( + .INIT ( 8'hBC )) + \blk00000003/blk00000440 ( + .I0(\blk00000003/sig00000580 ), + .I1(\blk00000003/sig000002de ), + .I2(\blk00000003/sig000002c6 ), + .O(\blk00000003/sig000002bb ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000043f ( + .I0(sclr), + .I1(\blk00000003/sig0000057f ), + .O(\blk00000003/sig000002b8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000043e ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000001d8 ), + .O(\blk00000003/sig000002b4 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000043d ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002b0 ) + ); + LUT4 #( + .INIT ( 16'hEAAA )) + \blk00000003/blk0000043c ( + .I0(\blk00000003/sig000001e8 ), + .I1(nd), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000002a9 ), + .O(\blk00000003/sig000002ae ) + ); + LUT4 #( + .INIT ( 16'hDFA0 )) + \blk00000003/blk0000043b ( + .I0(nd), + .I1(\blk00000003/sig000002a9 ), + .I2(NlwRenamedSig_OI_rfd), + .I3(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002ab ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000043a ( + .I0(nd), + .I1(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000002a4 ) + ); + LUT3 #( + .INIT ( 8'h09 )) + \blk00000003/blk00000439 ( + .I0(\blk00000003/sig0000057e ), + .I1(\blk00000003/sig000001e8 ), + .I2(\blk00000003/sig000001e9 ), + .O(\blk00000003/sig000002a6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000438 ( + .I0(\blk00000003/sig000002a0 ), + .I1(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig0000029a ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000437 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000297 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000436 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig0000023c ), + .O(\blk00000003/sig00000294 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000435 ( + .I0(\blk00000003/sig00000244 ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000292 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000434 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000024a ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028d ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk00000433 ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig0000028f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000432 ( + .I0(\blk00000003/sig0000023d ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000286 ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk00000431 ( + .I0(\blk00000003/sig0000023c ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig00000284 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000430 ( + .I0(\blk00000003/sig0000023a ), + .I1(\blk00000003/sig00000244 ), + .I2(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027f ) + ); + LUT2 #( + .INIT ( 4'h7 )) + \blk00000003/blk0000042f ( + .I0(\blk00000003/sig0000023f ), + .I1(\blk00000003/sig00000240 ), + .O(\blk00000003/sig0000027b ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042e ( + .I0(\blk00000003/sig0000023e ), + .I1(\blk00000003/sig00000240 ), + .I2(\blk00000003/sig0000024a ), + .O(\blk00000003/sig0000027d ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk0000042d ( + .I0(\blk00000003/sig0000024d ), + .I1(\blk00000003/sig0000057d ), + .O(\blk00000003/sig00000276 ) + ); + LUT3 #( + .INIT ( 8'h7F )) + \blk00000003/blk0000042c ( + .I0(coef_we), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000268 ) + ); + LUT4 #( + .INIT ( 16'hDAAA )) + \blk00000003/blk0000042b ( + .I0(\blk00000003/sig00000267 ), + .I1(\blk00000003/sig00000224 ), + .I2(\blk00000003/sig0000022c ), + .I3(coef_we), + .O(\blk00000003/sig00000265 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000042a ( + .I0(\blk00000003/sig00000263 ), + .I1(\blk00000003/sig000001c4 ), + .O(\blk00000003/sig00000261 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000429 ( + .I0(\blk00000003/sig00000258 ), + .I1(coef_we), + .O(\blk00000003/sig00000256 ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk00000428 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .O(\blk00000003/sig00000243 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000427 ( + .I0(coef_we), + .I1(\blk00000003/sig0000022c ), + .O(\blk00000003/sig00000225 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000426 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(coef_ld), + .O(\blk00000003/sig0000024b ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000425 ( + .I0(\blk00000003/sig00000254 ), + .I1(\blk00000003/sig00000255 ), + .I2(\blk00000003/sig00000258 ), + .O(\blk00000003/sig0000022e ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000424 ( + .I0(coef_ld), + .I1(\blk00000003/sig0000024d ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig00000222 ) + ); + LUT3 #( + .INIT ( 8'hDF )) + \blk00000003/blk00000423 ( + .I0(coef_we), + .I1(\blk00000003/sig00000238 ), + .I2(\blk00000003/sig00000236 ), + .O(\blk00000003/sig0000021f ) + ); + LUT5 #( + .INIT ( 32'hFFFF2AAA )) + \blk00000003/blk00000422 ( + .I0(\blk00000003/sig00000238 ), + .I1(coef_we), + .I2(\blk00000003/sig0000022c ), + .I3(\blk00000003/sig00000224 ), + .I4(coef_ld), + .O(\blk00000003/sig00000237 ) + ); + LUT4 #( + .INIT ( 16'hFF8A )) + \blk00000003/blk00000421 ( + .I0(\blk00000003/sig00000236 ), + .I1(\blk00000003/sig00000238 ), + .I2(coef_we), + .I3(coef_ld), + .O(\blk00000003/sig00000235 ) + ); + LUT3 #( + .INIT ( 8'h80 )) + \blk00000003/blk00000420 ( + .I0(nd), + .I1(\blk00000003/sig000002a2 ), + .I2(NlwRenamedSig_OI_rfd), + .O(\blk00000003/sig000001e7 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000041f ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000001df ), + .O(\blk00000003/sig000001e5 ) + ); + LUT3 #( + .INIT ( 8'h10 )) + \blk00000003/blk0000041e ( + .I0(\blk00000003/sig000000be ), + .I1(\blk00000003/sig000004fd ), + .I2(\blk00000003/sig0000057c ), + .O(\blk00000003/sig000000bf ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk0000041d ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/sig000004fd ), + .O(\blk00000003/sig000001e0 ) + ); + LUT2 #( + .INIT ( 4'hD )) + \blk00000003/blk0000041c ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .O(\blk00000003/sig000001cb ) + ); + LUT2 #( + .INIT ( 4'h2 )) + \blk00000003/blk0000041b ( + .I0(\blk00000003/sig0000029f ), + .I1(\blk00000003/sig000002a0 ), + .O(\blk00000003/sig000001c8 ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk0000041a ( + .I0(\blk00000003/sig0000025f ), + .I1(\blk00000003/sig00000260 ), + .I2(\blk00000003/sig00000263 ), + .O(\blk00000003/sig000001c5 ) + ); + LUT5 #( + .INIT ( 32'h00008000 )) + \blk00000003/blk00000419 ( + .I0(\blk00000003/sig00000573 ), + .I1(\blk00000003/sig00000574 ), + .I2(\blk00000003/sig00000575 ), + .I3(\blk00000003/sig00000576 ), + .I4(\blk00000003/sig00000577 ), + .O(\blk00000003/sig000000c1 ) + ); + LUT3 #( + .INIT ( 8'hF4 )) + \blk00000003/blk00000418 ( + .I0(\blk00000003/sig000001d8 ), + .I1(\blk00000003/sig000001c4 ), + .I2(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000417 ( + .I0(\blk00000003/sig000002b7 ), + .I1(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001dd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000416 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b4 ), + .O(\blk00000003/sig000000b3 ) + ); + LUT3 #( + .INIT ( 8'h72 )) + \blk00000003/blk00000415 ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig000000b2 ), + .O(\blk00000003/sig000000b1 ) + ); + LUT4 #( + .INIT ( 16'h8F88 )) + \blk00000003/blk00000414 ( + .I0(NlwRenamedSig_OI_rfd), + .I1(nd), + .I2(\blk00000003/sig000001da ), + .I3(\blk00000003/sig000001c7 ), + .O(\blk00000003/sig000001d9 ) + ); + LUT5 #( + .INIT ( 32'hCEEE8AAA )) + \blk00000003/blk00000413 ( + .I0(\blk00000003/sig000001c4 ), + .I1(\blk00000003/sig000001e6 ), + .I2(\blk00000003/sig000001d6 ), + .I3(\blk00000003/sig000001d8 ), + .I4(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d5 ) + ); + LUT4 #( + .INIT ( 16'h8808 )) + \blk00000003/blk00000412 ( + .I0(\blk00000003/sig000001d6 ), + .I1(\blk00000003/sig0000057b ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001e6 ), + .O(\blk00000003/sig000001d1 ) + ); + LUT4 #( + .INIT ( 16'h5540 )) + \blk00000003/blk00000411 ( + .I0(\blk00000003/sig000001e6 ), + .I1(\blk00000003/sig000001d6 ), + .I2(\blk00000003/sig000001d8 ), + .I3(\blk00000003/sig000001d4 ), + .O(\blk00000003/sig000001d3 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00000410 ( + .I0(\blk00000003/sig000002b6 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig000001e4 ), + .O(\blk00000003/sig000001db ) + ); + LUT4 #( + .INIT ( 16'hFDA8 )) + \blk00000003/blk0000040f ( + .I0(ce), + .I1(\blk00000003/sig00000579 ), + .I2(\blk00000003/sig0000057a ), + .I3(\blk00000003/sig000000b0 ), + .O(\blk00000003/sig000000af ) + ); + MUXCY \blk00000003/blk0000040e ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000578 ), + .O(\blk00000003/sig00000570 ) + ); + MUXCY_L \blk00000003/blk0000040d ( + .CI(\blk00000003/sig00000570 ), + .DI(\blk00000003/sig00000577 ), + .S(\blk00000003/sig00000571 ), + .LO(\blk00000003/sig0000056d ) + ); + MUXCY_L \blk00000003/blk0000040c ( + .CI(\blk00000003/sig0000056d ), + .DI(\blk00000003/sig00000576 ), + .S(\blk00000003/sig0000056e ), + .LO(\blk00000003/sig0000056a ) + ); + MUXCY_L \blk00000003/blk0000040b ( + .CI(\blk00000003/sig0000056a ), + .DI(\blk00000003/sig00000575 ), + .S(\blk00000003/sig0000056b ), + .LO(\blk00000003/sig00000567 ) + ); + MUXCY_L \blk00000003/blk0000040a ( + .CI(\blk00000003/sig00000567 ), + .DI(\blk00000003/sig00000574 ), + .S(\blk00000003/sig00000568 ), + .LO(\blk00000003/sig00000564 ) + ); + MUXCY_D \blk00000003/blk00000409 ( + .CI(\blk00000003/sig00000564 ), + .DI(\blk00000003/sig00000573 ), + .S(\blk00000003/sig00000565 ), + .O(\NLW_blk00000003/blk00000409_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk00000409_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk00000408 ( + .CI(\blk00000003/sig00000570 ), + .LI(\blk00000003/sig00000571 ), + .O(\blk00000003/sig00000572 ) + ); + XORCY \blk00000003/blk00000407 ( + .CI(\blk00000003/sig0000056d ), + .LI(\blk00000003/sig0000056e ), + .O(\blk00000003/sig0000056f ) + ); + XORCY \blk00000003/blk00000406 ( + .CI(\blk00000003/sig0000056a ), + .LI(\blk00000003/sig0000056b ), + .O(\blk00000003/sig0000056c ) + ); + XORCY \blk00000003/blk00000405 ( + .CI(\blk00000003/sig00000567 ), + .LI(\blk00000003/sig00000568 ), + .O(\blk00000003/sig00000569 ) + ); + XORCY \blk00000003/blk00000404 ( + .CI(\blk00000003/sig00000564 ), + .LI(\blk00000003/sig00000565 ), + .O(\blk00000003/sig00000566 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000563 ), + .R(sclr), + .Q(\blk00000003/sig0000004a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000562 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000561 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000400 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000560 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000055a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000559 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000558 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000557 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000556 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000555 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000554 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000553 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000552 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000551 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000550 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000054a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000549 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000548 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000547 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000546 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000545 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000544 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000543 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000542 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000541 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000540 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003de ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003db ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000053a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000539 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000538 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000537 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000536 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000535 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000534 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000533 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_2[0]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000532 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[47]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000531 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[46]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000530 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[45]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[44]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[43]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[42]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[41]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[40]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000052a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[39]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000529 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[38]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000528 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[37]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000527 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[36]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000526 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[35]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000525 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[34]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000524 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[33]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000523 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[32]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000522 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[31]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000521 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[30]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000520 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[29]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[28]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003be ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[27]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[26]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[25]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[24]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000051a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[23]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000519 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000518 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[21]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000517 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[20]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000516 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[19]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000515 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[18]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000514 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[17]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000513 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[16]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000512 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[15]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000511 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[14]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000510 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[13]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003af ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050f ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[12]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050e ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[11]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050d ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[10]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050c ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[9]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050b ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[8]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000050a ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[7]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000509 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[6]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000508 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000507 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000506 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000505 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000504 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000503 ), + .R(sclr), + .Q(NlwRenamedSig_OI_dout_1[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000502 ), + .Q(\blk00000003/sig000001df ) + ); + MUXCY_L \blk00000003/blk000003a1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000501 ), + .S(\blk00000003/sig000004ef ), + .LO(\blk00000003/sig000004fa ) + ); + MUXCY_L \blk00000003/blk000003a0 ( + .CI(\blk00000003/sig000004fa ), + .DI(\blk00000003/sig00000500 ), + .S(\blk00000003/sig000004fb ), + .LO(\blk00000003/sig000004f7 ) + ); + MUXCY_L \blk00000003/blk0000039f ( + .CI(\blk00000003/sig000004f7 ), + .DI(\blk00000003/sig000004ff ), + .S(\blk00000003/sig000004f8 ), + .LO(\blk00000003/sig000004f4 ) + ); + MUXCY_L \blk00000003/blk0000039e ( + .CI(\blk00000003/sig000004f4 ), + .DI(\blk00000003/sig000004fe ), + .S(\blk00000003/sig000004f5 ), + .LO(\blk00000003/sig000004f1 ) + ); + MUXCY_D \blk00000003/blk0000039d ( + .CI(\blk00000003/sig000004f1 ), + .DI(\blk00000003/sig000004fd ), + .S(\blk00000003/sig000004f2 ), + .O(\NLW_blk00000003/blk0000039d_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk0000039d_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk0000039c ( + .CI(\blk00000003/sig000004fa ), + .LI(\blk00000003/sig000004fb ), + .O(\blk00000003/sig000004fc ) + ); + XORCY \blk00000003/blk0000039b ( + .CI(\blk00000003/sig000004f7 ), + .LI(\blk00000003/sig000004f8 ), + .O(\blk00000003/sig000004f9 ) + ); + XORCY \blk00000003/blk0000039a ( + .CI(\blk00000003/sig000004f4 ), + .LI(\blk00000003/sig000004f5 ), + .O(\blk00000003/sig000004f6 ) + ); + XORCY \blk00000003/blk00000399 ( + .CI(\blk00000003/sig000004f1 ), + .LI(\blk00000003/sig000004f2 ), + .O(\blk00000003/sig000004f3 ) + ); + XORCY \blk00000003/blk00000398 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000004ef ), + .O(\blk00000003/sig000004f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000370 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dd ), + .R(sclr), + .Q(\blk00000003/sig00000450 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003dc ), + .R(sclr), + .Q(\blk00000003/sig0000044f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003db ), + .R(sclr), + .Q(\blk00000003/sig0000044e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003da ), + .R(sclr), + .Q(\blk00000003/sig0000044d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d9 ), + .R(sclr), + .Q(\blk00000003/sig0000044c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d8 ), + .R(sclr), + .Q(\blk00000003/sig0000044b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d7 ), + .R(sclr), + .Q(\blk00000003/sig0000044a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d6 ), + .R(sclr), + .Q(\blk00000003/sig00000449 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000368 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d5 ), + .R(sclr), + .Q(\blk00000003/sig00000448 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000367 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d4 ), + .R(sclr), + .Q(\blk00000003/sig00000447 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000366 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d3 ), + .R(sclr), + .Q(\blk00000003/sig00000446 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000365 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d2 ), + .R(sclr), + .Q(\blk00000003/sig00000445 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000364 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d1 ), + .R(sclr), + .Q(\blk00000003/sig00000444 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000363 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003d0 ), + .R(sclr), + .Q(\blk00000003/sig00000443 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000362 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cf ), + .R(sclr), + .Q(\blk00000003/sig00000442 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000361 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ce ), + .R(sclr), + .Q(\blk00000003/sig00000441 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000360 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cd ), + .R(sclr), + .Q(\blk00000003/sig00000440 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cc ), + .R(sclr), + .Q(\blk00000003/sig0000043f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003cb ), + .R(sclr), + .Q(\blk00000003/sig0000043e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ca ), + .R(sclr), + .Q(\blk00000003/sig0000043d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c9 ), + .R(sclr), + .Q(\blk00000003/sig0000043c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c8 ), + .R(sclr), + .Q(\blk00000003/sig0000043b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000035a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c7 ), + .R(sclr), + .Q(\blk00000003/sig0000043a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000359 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003c6 ), + .R(sclr), + .Q(\blk00000003/sig00000439 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000358 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040d ), + .R(sclr), + .Q(\blk00000003/sig00000468 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000357 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040c ), + .R(sclr), + .Q(\blk00000003/sig00000467 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000356 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040b ), + .R(sclr), + .Q(\blk00000003/sig00000466 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000355 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig0000040a ), + .R(sclr), + .Q(\blk00000003/sig00000465 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000354 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000409 ), + .R(sclr), + .Q(\blk00000003/sig00000464 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000353 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000408 ), + .R(sclr), + .Q(\blk00000003/sig00000463 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000352 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000407 ), + .R(sclr), + .Q(\blk00000003/sig00000462 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000351 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000406 ), + .R(sclr), + .Q(\blk00000003/sig00000461 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000350 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000405 ), + .R(sclr), + .Q(\blk00000003/sig00000460 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034f ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000404 ), + .R(sclr), + .Q(\blk00000003/sig0000045f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034e ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000403 ), + .R(sclr), + .Q(\blk00000003/sig0000045e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034d ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000402 ), + .R(sclr), + .Q(\blk00000003/sig0000045d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034c ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000401 ), + .R(sclr), + .Q(\blk00000003/sig0000045c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034b ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig00000400 ), + .R(sclr), + .Q(\blk00000003/sig0000045b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000034a ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003ff ), + .R(sclr), + .Q(\blk00000003/sig0000045a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000349 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fe ), + .R(sclr), + .Q(\blk00000003/sig00000459 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000348 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fd ), + .R(sclr), + .Q(\blk00000003/sig00000458 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000347 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fc ), + .R(sclr), + .Q(\blk00000003/sig00000457 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000346 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fb ), + .R(sclr), + .Q(\blk00000003/sig00000456 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000345 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003fa ), + .R(sclr), + .Q(\blk00000003/sig00000455 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000344 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f9 ), + .R(sclr), + .Q(\blk00000003/sig00000454 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000343 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f8 ), + .R(sclr), + .Q(\blk00000003/sig00000453 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000342 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f7 ), + .R(sclr), + .Q(\blk00000003/sig00000452 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000341 ( + .C(clk), + .CE(\blk00000003/sig000004ee ), + .D(\blk00000003/sig000003f6 ), + .R(sclr), + .Q(\blk00000003/sig00000451 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000340 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f5 ), + .R(sclr), + .Q(\blk00000003/sig00000498 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f4 ), + .R(sclr), + .Q(\blk00000003/sig00000497 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f3 ), + .R(sclr), + .Q(\blk00000003/sig00000496 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f2 ), + .R(sclr), + .Q(\blk00000003/sig00000495 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f1 ), + .R(sclr), + .Q(\blk00000003/sig00000494 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003f0 ), + .R(sclr), + .Q(\blk00000003/sig00000493 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000033a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ef ), + .R(sclr), + .Q(\blk00000003/sig00000492 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000339 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ee ), + .R(sclr), + .Q(\blk00000003/sig00000491 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000338 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ed ), + .R(sclr), + .Q(\blk00000003/sig00000490 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000337 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ec ), + .R(sclr), + .Q(\blk00000003/sig0000048f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000336 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003eb ), + .R(sclr), + .Q(\blk00000003/sig0000048e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000335 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003ea ), + .R(sclr), + .Q(\blk00000003/sig0000048d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000334 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e9 ), + .R(sclr), + .Q(\blk00000003/sig0000048c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000333 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e8 ), + .R(sclr), + .Q(\blk00000003/sig0000048b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000332 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e7 ), + .R(sclr), + .Q(\blk00000003/sig0000048a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000331 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e6 ), + .R(sclr), + .Q(\blk00000003/sig00000489 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000330 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e5 ), + .R(sclr), + .Q(\blk00000003/sig00000488 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e4 ), + .R(sclr), + .Q(\blk00000003/sig00000487 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e3 ), + .R(sclr), + .Q(\blk00000003/sig00000486 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e2 ), + .R(sclr), + .Q(\blk00000003/sig00000485 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e1 ), + .R(sclr), + .Q(\blk00000003/sig00000484 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003e0 ), + .R(sclr), + .Q(\blk00000003/sig00000483 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000032a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003df ), + .R(sclr), + .Q(\blk00000003/sig00000482 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000329 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig000003de ), + .R(sclr), + .Q(\blk00000003/sig00000481 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000328 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000425 ), + .R(sclr), + .Q(\blk00000003/sig000004c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000327 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000424 ), + .R(sclr), + .Q(\blk00000003/sig000004c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000326 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000423 ), + .R(sclr), + .Q(\blk00000003/sig000004c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000325 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000422 ), + .R(sclr), + .Q(\blk00000003/sig000004c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000324 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000421 ), + .R(sclr), + .Q(\blk00000003/sig000004c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000323 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000420 ), + .R(sclr), + .Q(\blk00000003/sig000004c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000322 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041f ), + .R(sclr), + .Q(\blk00000003/sig000004c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000321 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041e ), + .R(sclr), + .Q(\blk00000003/sig000004c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000320 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041d ), + .R(sclr), + .Q(\blk00000003/sig000004c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031f ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041c ), + .R(sclr), + .Q(\blk00000003/sig000004bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031e ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041b ), + .R(sclr), + .Q(\blk00000003/sig000004be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031d ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000041a ), + .R(sclr), + .Q(\blk00000003/sig000004bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031c ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000419 ), + .R(sclr), + .Q(\blk00000003/sig000004bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031b ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000418 ), + .R(sclr), + .Q(\blk00000003/sig000004bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000031a ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000417 ), + .R(sclr), + .Q(\blk00000003/sig000004ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000319 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000416 ), + .R(sclr), + .Q(\blk00000003/sig000004b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000318 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000415 ), + .R(sclr), + .Q(\blk00000003/sig000004b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000317 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000414 ), + .R(sclr), + .Q(\blk00000003/sig000004b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000316 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000413 ), + .R(sclr), + .Q(\blk00000003/sig000004b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000315 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000412 ), + .R(sclr), + .Q(\blk00000003/sig000004b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000314 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000411 ), + .R(sclr), + .Q(\blk00000003/sig000004b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000313 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig00000410 ), + .R(sclr), + .Q(\blk00000003/sig000004b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000312 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040f ), + .R(sclr), + .Q(\blk00000003/sig000004b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000311 ( + .C(clk), + .CE(\blk00000003/sig000004ed ), + .D(\blk00000003/sig0000040e ), + .R(sclr), + .Q(\blk00000003/sig000004b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d1 ), + .R(sclr), + .Q(\blk00000003/sig00000438 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d0 ), + .R(sclr), + .Q(\blk00000003/sig00000437 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002cf ), + .R(sclr), + .Q(\blk00000003/sig00000436 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000434 ), + .R(sclr), + .Q(\blk00000003/sig00000435 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d3 ), + .R(sclr), + .Q(\blk00000003/sig00000433 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000113 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002d7 ), + .R(sclr), + .Q(\blk00000003/sig00000432 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002da ), + .R(sclr), + .Q(\blk00000003/sig00000431 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000111 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002e1 ), + .R(sclr), + .Q(\blk00000003/sig00000430 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000110 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000042e ), + .R(sclr), + .Q(\blk00000003/sig0000042f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c6 ), + .R(sclr), + .Q(\blk00000003/sig0000042d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c5 ), + .R(sclr), + .Q(\blk00000003/sig0000042c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002c4 ), + .R(sclr), + .Q(\blk00000003/sig0000042b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000234 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000042a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000275 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000429 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000271 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000428 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000427 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000026a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000426 ) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000107 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000107_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000107_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000107_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000107_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000107_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000107_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000107_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000107_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000107_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000107_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000107_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003f6 , \blk00000003/sig000003f6 , \blk00000003/sig000003f7 , \blk00000003/sig000003f8 , \blk00000003/sig000003f9 , +\blk00000003/sig000003fa , \blk00000003/sig000003fb , \blk00000003/sig000003fc , \blk00000003/sig000003fd , \blk00000003/sig000003fe , +\blk00000003/sig000003ff , \blk00000003/sig00000400 , \blk00000003/sig00000401 , \blk00000003/sig00000402 , \blk00000003/sig00000403 , +\blk00000003/sig00000404 , \blk00000003/sig00000405 , \blk00000003/sig00000406 , \blk00000003/sig00000407 , \blk00000003/sig00000408 , +\blk00000003/sig00000409 , \blk00000003/sig0000040a , \blk00000003/sig0000040b , \blk00000003/sig0000040c , \blk00000003/sig0000040d }), + .P({\NLW_blk00000003/blk00000107_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000107_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000107_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040e , +\blk00000003/sig0000040e , \blk00000003/sig0000040e , \blk00000003/sig0000040f , \blk00000003/sig00000410 , \blk00000003/sig00000411 , +\blk00000003/sig00000412 , \blk00000003/sig00000413 , \blk00000003/sig00000414 , \blk00000003/sig00000415 , \blk00000003/sig00000416 , +\blk00000003/sig00000417 , \blk00000003/sig00000418 , \blk00000003/sig00000419 , \blk00000003/sig0000041a , \blk00000003/sig0000041b , +\blk00000003/sig0000041c , \blk00000003/sig0000041d , \blk00000003/sig0000041e , \blk00000003/sig0000041f , \blk00000003/sig00000420 , +\blk00000003/sig00000421 , \blk00000003/sig00000422 , \blk00000003/sig00000423 , \blk00000003/sig00000424 , \blk00000003/sig00000425 }), + .PCOUT({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000106 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000106_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000106_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000106_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000106_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000106_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000106_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000106_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000106_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000003b4 , \blk00000003/sig000003b5 , \blk00000003/sig000003b6 , \blk00000003/sig000003b7 , \blk00000003/sig000003b8 , +\blk00000003/sig000003b9 , \blk00000003/sig000003ba , \blk00000003/sig000003bb , \blk00000003/sig000003bc , \blk00000003/sig000003bd , +\blk00000003/sig000003be , \blk00000003/sig000003bf , \blk00000003/sig000003c0 , \blk00000003/sig000003c1 , \blk00000003/sig000003c2 , +\blk00000003/sig000003c3 , \blk00000003/sig000003c4 , \blk00000003/sig000003c5 }), + .BCOUT({\NLW_blk00000003/blk00000106_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000106_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000106_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000003c6 , \blk00000003/sig000003c6 , \blk00000003/sig000003c7 , \blk00000003/sig000003c8 , \blk00000003/sig000003c9 , +\blk00000003/sig000003ca , \blk00000003/sig000003cb , \blk00000003/sig000003cc , \blk00000003/sig000003cd , \blk00000003/sig000003ce , +\blk00000003/sig000003cf , \blk00000003/sig000003d0 , \blk00000003/sig000003d1 , \blk00000003/sig000003d2 , \blk00000003/sig000003d3 , +\blk00000003/sig000003d4 , \blk00000003/sig000003d5 , \blk00000003/sig000003d6 , \blk00000003/sig000003d7 , \blk00000003/sig000003d8 , +\blk00000003/sig000003d9 , \blk00000003/sig000003da , \blk00000003/sig000003db , \blk00000003/sig000003dc , \blk00000003/sig000003dd }), + .P({\NLW_blk00000003/blk00000106_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000106_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000106_P<0>_UNCONNECTED }), + .A({\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003de , +\blk00000003/sig000003de , \blk00000003/sig000003de , \blk00000003/sig000003df , \blk00000003/sig000003e0 , \blk00000003/sig000003e1 , +\blk00000003/sig000003e2 , \blk00000003/sig000003e3 , \blk00000003/sig000003e4 , \blk00000003/sig000003e5 , \blk00000003/sig000003e6 , +\blk00000003/sig000003e7 , \blk00000003/sig000003e8 , \blk00000003/sig000003e9 , \blk00000003/sig000003ea , \blk00000003/sig000003eb , +\blk00000003/sig000003ec , \blk00000003/sig000003ed , \blk00000003/sig000003ee , \blk00000003/sig000003ef , \blk00000003/sig000003f0 , +\blk00000003/sig000003f1 , \blk00000003/sig000003f2 , \blk00000003/sig000003f3 , \blk00000003/sig000003f4 , \blk00000003/sig000003f5 }), + .PCOUT({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000105 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000105_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000105_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000105_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000105_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000105_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000105_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000105_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000105_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000105_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000105_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000105_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000354 , \blk00000003/sig00000354 , \blk00000003/sig00000355 , \blk00000003/sig00000356 , \blk00000003/sig00000357 , +\blk00000003/sig00000358 , \blk00000003/sig00000359 , \blk00000003/sig0000035a , \blk00000003/sig0000035b , \blk00000003/sig0000035c , +\blk00000003/sig0000035d , \blk00000003/sig0000035e , \blk00000003/sig0000035f , \blk00000003/sig00000360 , \blk00000003/sig00000361 , +\blk00000003/sig00000362 , \blk00000003/sig00000363 , \blk00000003/sig00000364 , \blk00000003/sig00000365 , \blk00000003/sig00000366 , +\blk00000003/sig00000367 , \blk00000003/sig00000368 , \blk00000003/sig00000369 , \blk00000003/sig0000036a , \blk00000003/sig0000036b }), + .P({\NLW_blk00000003/blk00000105_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000105_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000105_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036c , +\blk00000003/sig0000036c , \blk00000003/sig0000036c , \blk00000003/sig0000036d , \blk00000003/sig0000036e , \blk00000003/sig0000036f , +\blk00000003/sig00000370 , \blk00000003/sig00000371 , \blk00000003/sig00000372 , \blk00000003/sig00000373 , \blk00000003/sig00000374 , +\blk00000003/sig00000375 , \blk00000003/sig00000376 , \blk00000003/sig00000377 , \blk00000003/sig00000378 , \blk00000003/sig00000379 , +\blk00000003/sig0000037a , \blk00000003/sig0000037b , \blk00000003/sig0000037c , \blk00000003/sig0000037d , \blk00000003/sig0000037e , +\blk00000003/sig0000037f , \blk00000003/sig00000380 , \blk00000003/sig00000381 , \blk00000003/sig00000382 , \blk00000003/sig00000383 }), + .PCOUT({\blk00000003/sig00000384 , \blk00000003/sig00000385 , \blk00000003/sig00000386 , \blk00000003/sig00000387 , \blk00000003/sig00000388 , +\blk00000003/sig00000389 , \blk00000003/sig0000038a , \blk00000003/sig0000038b , \blk00000003/sig0000038c , \blk00000003/sig0000038d , +\blk00000003/sig0000038e , \blk00000003/sig0000038f , \blk00000003/sig00000390 , \blk00000003/sig00000391 , \blk00000003/sig00000392 , +\blk00000003/sig00000393 , \blk00000003/sig00000394 , \blk00000003/sig00000395 , \blk00000003/sig00000396 , \blk00000003/sig00000397 , +\blk00000003/sig00000398 , \blk00000003/sig00000399 , \blk00000003/sig0000039a , \blk00000003/sig0000039b , \blk00000003/sig0000039c , +\blk00000003/sig0000039d , \blk00000003/sig0000039e , \blk00000003/sig0000039f , \blk00000003/sig000003a0 , \blk00000003/sig000003a1 , +\blk00000003/sig000003a2 , \blk00000003/sig000003a3 , \blk00000003/sig000003a4 , \blk00000003/sig000003a5 , \blk00000003/sig000003a6 , +\blk00000003/sig000003a7 , \blk00000003/sig000003a8 , \blk00000003/sig000003a9 , \blk00000003/sig000003aa , \blk00000003/sig000003ab , +\blk00000003/sig000003ac , \blk00000003/sig000003ad , \blk00000003/sig000003ae , \blk00000003/sig000003af , \blk00000003/sig000003b0 , +\blk00000003/sig000003b1 , \blk00000003/sig000003b2 , \blk00000003/sig000003b3 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 1 ), + .ADREG ( 1 ), + .ALUMODEREG ( 0 ), + .AREG ( 1 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 1 ), + .BREG ( 1 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 1 ), + .INMODEREG ( 1 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "TRUE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk00000104 ( + .PATTERNBDETECT(\NLW_blk00000003/blk00000104_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(\blk00000003/sig00000049 ), + .CEAD(ce), + .MULTSIGNOUT(\NLW_blk00000003/blk00000104_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk00000104_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk00000104_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk00000104_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(ce), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(\blk00000003/sig00000049 ), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk00000104_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk00000104_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig000000ae , +\blk00000003/sig00000049 , \blk00000003/sig000000ae }), + .PCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk00000104_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000002e2 , \blk00000003/sig000002e3 , \blk00000003/sig000002e4 , \blk00000003/sig000002e5 , \blk00000003/sig000002e6 , +\blk00000003/sig000002e7 , \blk00000003/sig000002e8 , \blk00000003/sig000002e9 , \blk00000003/sig000002ea , \blk00000003/sig000002eb , +\blk00000003/sig000002ec , \blk00000003/sig000002ed , \blk00000003/sig000002ee , \blk00000003/sig000002ef , \blk00000003/sig000002f0 , +\blk00000003/sig000002f1 , \blk00000003/sig000002f2 , \blk00000003/sig000002f3 }), + .BCOUT({\NLW_blk00000003/blk00000104_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000104_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000104_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig000002f4 , \blk00000003/sig000002f4 , \blk00000003/sig000002f5 , \blk00000003/sig000002f6 , \blk00000003/sig000002f7 , +\blk00000003/sig000002f8 , \blk00000003/sig000002f9 , \blk00000003/sig000002fa , \blk00000003/sig000002fb , \blk00000003/sig000002fc , +\blk00000003/sig000002fd , \blk00000003/sig000002fe , \blk00000003/sig000002ff , \blk00000003/sig00000300 , \blk00000003/sig00000301 , +\blk00000003/sig00000302 , \blk00000003/sig00000303 , \blk00000003/sig00000304 , \blk00000003/sig00000305 , \blk00000003/sig00000306 , +\blk00000003/sig00000307 , \blk00000003/sig00000308 , \blk00000003/sig00000309 , \blk00000003/sig0000030a , \blk00000003/sig0000030b }), + .P({\NLW_blk00000003/blk00000104_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000104_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000104_P<0>_UNCONNECTED }), + .A({\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030c , +\blk00000003/sig0000030c , \blk00000003/sig0000030c , \blk00000003/sig0000030d , \blk00000003/sig0000030e , \blk00000003/sig0000030f , +\blk00000003/sig00000310 , \blk00000003/sig00000311 , \blk00000003/sig00000312 , \blk00000003/sig00000313 , \blk00000003/sig00000314 , +\blk00000003/sig00000315 , \blk00000003/sig00000316 , \blk00000003/sig00000317 , \blk00000003/sig00000318 , \blk00000003/sig00000319 , +\blk00000003/sig0000031a , \blk00000003/sig0000031b , \blk00000003/sig0000031c , \blk00000003/sig0000031d , \blk00000003/sig0000031e , +\blk00000003/sig0000031f , \blk00000003/sig00000320 , \blk00000003/sig00000321 , \blk00000003/sig00000322 , \blk00000003/sig00000323 }), + .PCOUT({\blk00000003/sig00000324 , \blk00000003/sig00000325 , \blk00000003/sig00000326 , \blk00000003/sig00000327 , \blk00000003/sig00000328 , +\blk00000003/sig00000329 , \blk00000003/sig0000032a , \blk00000003/sig0000032b , \blk00000003/sig0000032c , \blk00000003/sig0000032d , +\blk00000003/sig0000032e , \blk00000003/sig0000032f , \blk00000003/sig00000330 , \blk00000003/sig00000331 , \blk00000003/sig00000332 , +\blk00000003/sig00000333 , \blk00000003/sig00000334 , \blk00000003/sig00000335 , \blk00000003/sig00000336 , \blk00000003/sig00000337 , +\blk00000003/sig00000338 , \blk00000003/sig00000339 , \blk00000003/sig0000033a , \blk00000003/sig0000033b , \blk00000003/sig0000033c , +\blk00000003/sig0000033d , \blk00000003/sig0000033e , \blk00000003/sig0000033f , \blk00000003/sig00000340 , \blk00000003/sig00000341 , +\blk00000003/sig00000342 , \blk00000003/sig00000343 , \blk00000003/sig00000344 , \blk00000003/sig00000345 , \blk00000003/sig00000346 , +\blk00000003/sig00000347 , \blk00000003/sig00000348 , \blk00000003/sig00000349 , \blk00000003/sig0000034a , \blk00000003/sig0000034b , +\blk00000003/sig0000034c , \blk00000003/sig0000034d , \blk00000003/sig0000034e , \blk00000003/sig0000034f , \blk00000003/sig00000350 , +\blk00000003/sig00000351 , \blk00000003/sig00000352 , \blk00000003/sig00000353 }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000103 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000002e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000102 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002df ), + .Q(\blk00000003/sig000002e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000002d2 ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig000002d9 ), + .LI(\blk00000003/sig000002db ), + .O(\blk00000003/sig000002dd ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig000002d5 ), + .LI(\blk00000003/sig000002d8 ), + .O(\blk00000003/sig000002dc ) + ); + MUXCY_D \blk00000003/blk000000fe ( + .CI(\blk00000003/sig000002d9 ), + .DI(\blk00000003/sig000002da ), + .S(\blk00000003/sig000002db ), + .O(\NLW_blk00000003/blk000000fe_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000fe_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000fd ( + .CI(\blk00000003/sig000002d5 ), + .DI(\blk00000003/sig000002d7 ), + .S(\blk00000003/sig000002d8 ), + .LO(\blk00000003/sig000002d9 ) + ); + XORCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig000002d2 ), + .LI(\blk00000003/sig000002d4 ), + .O(\blk00000003/sig000002d6 ) + ); + MUXCY_L \blk00000003/blk000000fb ( + .CI(\blk00000003/sig000002d2 ), + .DI(\blk00000003/sig000002d3 ), + .S(\blk00000003/sig000002d4 ), + .LO(\blk00000003/sig000002d5 ) + ); + MUXCY_L \blk00000003/blk000000fa ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002d1 ), + .S(\blk00000003/sig000002c7 ), + .LO(\blk00000003/sig000002cc ) + ); + MUXCY_L \blk00000003/blk000000f9 ( + .CI(\blk00000003/sig000002cc ), + .DI(\blk00000003/sig000002d0 ), + .S(\blk00000003/sig000002cd ), + .LO(\blk00000003/sig000002c9 ) + ); + MUXCY_D \blk00000003/blk000000f8 ( + .CI(\blk00000003/sig000002c9 ), + .DI(\blk00000003/sig000002cf ), + .S(\blk00000003/sig000002ca ), + .O(\NLW_blk00000003/blk000000f8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000f7 ( + .CI(\blk00000003/sig000002cc ), + .LI(\blk00000003/sig000002cd ), + .O(\blk00000003/sig000002ce ) + ); + XORCY \blk00000003/blk000000f6 ( + .CI(\blk00000003/sig000002c9 ), + .LI(\blk00000003/sig000002ca ), + .O(\blk00000003/sig000002cb ) + ); + XORCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002c7 ), + .O(\blk00000003/sig000002c8 ) + ); + MUXCY_L \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig000002ba ), + .DI(\blk00000003/sig000002c6 ), + .S(\blk00000003/sig000002bb ), + .LO(\blk00000003/sig000002c0 ) + ); + MUXCY_L \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig000002c0 ), + .DI(\blk00000003/sig000002c5 ), + .S(\blk00000003/sig000002c1 ), + .LO(\blk00000003/sig000002bd ) + ); + MUXCY_D \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig000002bd ), + .DI(\blk00000003/sig000002c4 ), + .S(\blk00000003/sig000002be ), + .O(\NLW_blk00000003/blk000000f2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000f2_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002c3 ), + .O(\blk00000003/sig000002ba ) + ); + XORCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig000002c0 ), + .LI(\blk00000003/sig000002c1 ), + .O(\blk00000003/sig000002c2 ) + ); + XORCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig000002bd ), + .LI(\blk00000003/sig000002be ), + .O(\blk00000003/sig000002bf ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig000002ba ), + .LI(\blk00000003/sig000002bb ), + .O(\blk00000003/sig000002bc ) + ); + FDE \blk00000003/blk000000ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002b8 ), + .Q(\blk00000003/sig000002b9 ) + ); + MUXCY_L \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002b7 ), + .S(\blk00000003/sig000002b1 ), + .LO(\blk00000003/sig000002b3 ) + ); + MUXCY_D \blk00000003/blk000000eb ( + .CI(\blk00000003/sig000002b3 ), + .DI(\blk00000003/sig000002b6 ), + .S(\blk00000003/sig000002b4 ), + .O(\NLW_blk00000003/blk000000eb_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000eb_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000ea ( + .CI(\blk00000003/sig000002b3 ), + .LI(\blk00000003/sig000002b4 ), + .O(\blk00000003/sig000002b5 ) + ); + XORCY \blk00000003/blk000000e9 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig000002b1 ), + .O(\blk00000003/sig000002b2 ) + ); + MUXCY_L \blk00000003/blk000000e8 ( + .CI(\blk00000003/sig000002aa ), + .DI(\blk00000003/sig000001e9 ), + .S(\blk00000003/sig000002ab ), + .LO(\blk00000003/sig000002ad ) + ); + MUXCY_D \blk00000003/blk000000e7 ( + .CI(\blk00000003/sig000002ad ), + .DI(\blk00000003/sig000001e8 ), + .S(\blk00000003/sig000002ae ), + .O(\NLW_blk00000003/blk000000e7_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000e7_LO_UNCONNECTED ) + ); + MUXCY \blk00000003/blk000000e6 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000002b0 ), + .O(\blk00000003/sig000002aa ) + ); + XORCY \blk00000003/blk000000e5 ( + .CI(\blk00000003/sig000002ad ), + .LI(\blk00000003/sig000002ae ), + .O(\blk00000003/sig000002af ) + ); + XORCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig000002aa ), + .LI(\blk00000003/sig000002ab ), + .O(\blk00000003/sig000002ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a8 ), + .R(sclr), + .Q(\blk00000003/sig000002a9 ) + ); + MUXCY_D \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig000002a5 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a7 ), + .O(\NLW_blk00000003/blk000000e2_O_UNCONNECTED ), + .LO(\blk00000003/sig000002a8 ) + ); + MUXCY_D \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000002a6 ), + .O(\blk00000003/sig000002a3 ), + .LO(\NLW_blk00000003/blk000000e1_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig000002a3 ), + .DI(\blk00000003/sig000002a2 ), + .S(\blk00000003/sig000002a4 ), + .O(\blk00000003/sig000002a5 ), + .LO(\blk00000003/sig000002a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000002a1 ), + .R(sclr), + .Q(\blk00000003/sig000002a2 ) + ); + MUXCY_L \blk00000003/blk000000de ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000002a0 ), + .S(\blk00000003/sig0000029a ), + .LO(\blk00000003/sig0000029c ) + ); + MUXCY_D \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000029c ), + .DI(\blk00000003/sig0000029f ), + .S(\blk00000003/sig0000029d ), + .O(\NLW_blk00000003/blk000000dd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000dd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000dc ( + .CI(\blk00000003/sig0000029c ), + .LI(\blk00000003/sig0000029d ), + .O(\blk00000003/sig0000029e ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig0000029a ), + .O(\blk00000003/sig0000029b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028b ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000221 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000028a ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021e ) + ); + MUXCY_D \blk00000003/blk000000d8 ( + .CI(\blk00000003/sig0000021e ), + .DI(\blk00000003/sig00000298 ), + .S(\blk00000003/sig00000299 ), + .O(\blk00000003/sig00000295 ), + .LO(\NLW_blk00000003/blk000000d8_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d7 ( + .CI(\blk00000003/sig00000295 ), + .DI(\blk00000003/sig00000296 ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000293 ), + .LO(\NLW_blk00000003/blk000000d7_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d6 ( + .CI(\blk00000003/sig00000293 ), + .DI(\blk00000003/sig00000289 ), + .S(\blk00000003/sig00000294 ), + .O(\blk00000003/sig00000290 ), + .LO(\NLW_blk00000003/blk000000d6_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d5 ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig00000291 ), + .S(\blk00000003/sig00000292 ), + .O(\blk00000003/sig0000028e ), + .LO(\NLW_blk00000003/blk000000d5_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d4 ( + .CI(\blk00000003/sig0000028e ), + .DI(\blk00000003/sig00000246 ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig0000028c ), + .LO(\NLW_blk00000003/blk000000d4_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000d3 ( + .CI(\blk00000003/sig0000028c ), + .DI(\blk00000003/sig0000021b ), + .S(\blk00000003/sig0000028d ), + .O(\NLW_blk00000003/blk000000d3_O_UNCONNECTED ), + .LO(\blk00000003/sig0000028a ) + ); + XORCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig0000028a ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000028b ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000279 ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000289 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000278 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig000001ce ) + ); + MUXCY_D \blk00000003/blk000000cf ( + .CI(\blk00000003/sig000001ce ), + .DI(\blk00000003/sig00000287 ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig00000285 ), + .LO(\NLW_blk00000003/blk000000cf_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000285 ), + .DI(\blk00000003/sig000001cf ), + .S(\blk00000003/sig00000286 ), + .O(\blk00000003/sig00000283 ), + .LO(\NLW_blk00000003/blk000000ce_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cd ( + .CI(\blk00000003/sig00000283 ), + .DI(\blk00000003/sig000001ce ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000280 ), + .LO(\NLW_blk00000003/blk000000cd_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cc ( + .CI(\blk00000003/sig00000280 ), + .DI(\blk00000003/sig00000281 ), + .S(\blk00000003/sig00000282 ), + .O(\blk00000003/sig0000027e ), + .LO(\NLW_blk00000003/blk000000cc_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000cb ( + .CI(\blk00000003/sig0000027e ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027f ), + .O(\blk00000003/sig0000027a ), + .LO(\NLW_blk00000003/blk000000cb_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000027c ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig0000027d ), + .O(\NLW_blk00000003/blk000000ca_O_UNCONNECTED ), + .LO(\blk00000003/sig00000278 ) + ); + MUXCY_D \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig0000027a ), + .DI(\blk00000003/sig0000023b ), + .S(\blk00000003/sig0000027b ), + .O(\blk00000003/sig0000027c ), + .LO(\NLW_blk00000003/blk000000c9_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000278 ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig00000279 ) + ); + FDE \blk00000003/blk000000c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000276 ), + .Q(\blk00000003/sig00000277 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000275 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000269 ) + ); + XORCY \blk00000003/blk000000c4 ( + .CI(\blk00000003/sig00000270 ), + .LI(\blk00000003/sig00000272 ), + .O(\blk00000003/sig00000274 ) + ); + XORCY \blk00000003/blk000000c3 ( + .CI(\blk00000003/sig0000026c ), + .LI(\blk00000003/sig0000026f ), + .O(\blk00000003/sig00000273 ) + ); + MUXCY_D \blk00000003/blk000000c2 ( + .CI(\blk00000003/sig00000270 ), + .DI(\blk00000003/sig00000271 ), + .S(\blk00000003/sig00000272 ), + .O(\NLW_blk00000003/blk000000c2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000c2_LO_UNCONNECTED ) + ); + MUXCY_L \blk00000003/blk000000c1 ( + .CI(\blk00000003/sig0000026c ), + .DI(\blk00000003/sig0000026e ), + .S(\blk00000003/sig0000026f ), + .LO(\blk00000003/sig00000270 ) + ); + XORCY \blk00000003/blk000000c0 ( + .CI(\blk00000003/sig00000269 ), + .LI(\blk00000003/sig0000026b ), + .O(\blk00000003/sig0000026d ) + ); + MUXCY_L \blk00000003/blk000000bf ( + .CI(\blk00000003/sig00000269 ), + .DI(\blk00000003/sig0000026a ), + .S(\blk00000003/sig0000026b ), + .LO(\blk00000003/sig0000026c ) + ); + MUXCY \blk00000003/blk000000be ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig00000268 ), + .O(\blk00000003/sig00000264 ) + ); + MUXCY_D \blk00000003/blk000000bd ( + .CI(\blk00000003/sig00000264 ), + .DI(\blk00000003/sig00000267 ), + .S(\blk00000003/sig00000265 ), + .O(\NLW_blk00000003/blk000000bd_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000bd_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000bc ( + .CI(\blk00000003/sig00000264 ), + .LI(\blk00000003/sig00000265 ), + .O(\blk00000003/sig00000266 ) + ); + MUXCY_L \blk00000003/blk000000bb ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000263 ), + .S(\blk00000003/sig00000261 ), + .LO(\blk00000003/sig0000025c ) + ); + XORCY \blk00000003/blk000000ba ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000262 ) + ); + MUXCY_L \blk00000003/blk000000b9 ( + .CI(\blk00000003/sig0000025c ), + .DI(\blk00000003/sig00000260 ), + .S(\blk00000003/sig0000025d ), + .LO(\blk00000003/sig00000259 ) + ); + MUXCY_D \blk00000003/blk000000b8 ( + .CI(\blk00000003/sig00000259 ), + .DI(\blk00000003/sig0000025f ), + .S(\blk00000003/sig0000025a ), + .O(\NLW_blk00000003/blk000000b8_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b8_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b7 ( + .CI(\blk00000003/sig0000025c ), + .LI(\blk00000003/sig0000025d ), + .O(\blk00000003/sig0000025e ) + ); + XORCY \blk00000003/blk000000b6 ( + .CI(\blk00000003/sig00000259 ), + .LI(\blk00000003/sig0000025a ), + .O(\blk00000003/sig0000025b ) + ); + MUXCY_L \blk00000003/blk000000b5 ( + .CI(\blk00000003/sig00000049 ), + .DI(\blk00000003/sig00000258 ), + .S(\blk00000003/sig00000256 ), + .LO(\blk00000003/sig00000251 ) + ); + XORCY \blk00000003/blk000000b4 ( + .CI(\blk00000003/sig00000049 ), + .LI(\blk00000003/sig00000256 ), + .O(\blk00000003/sig00000257 ) + ); + MUXCY_L \blk00000003/blk000000b3 ( + .CI(\blk00000003/sig00000251 ), + .DI(\blk00000003/sig00000255 ), + .S(\blk00000003/sig00000252 ), + .LO(\blk00000003/sig0000024e ) + ); + MUXCY_D \blk00000003/blk000000b2 ( + .CI(\blk00000003/sig0000024e ), + .DI(\blk00000003/sig00000254 ), + .S(\blk00000003/sig0000024f ), + .O(\NLW_blk00000003/blk000000b2_O_UNCONNECTED ), + .LO(\NLW_blk00000003/blk000000b2_LO_UNCONNECTED ) + ); + XORCY \blk00000003/blk000000b1 ( + .CI(\blk00000003/sig00000251 ), + .LI(\blk00000003/sig00000252 ), + .O(\blk00000003/sig00000253 ) + ); + XORCY \blk00000003/blk000000b0 ( + .CI(\blk00000003/sig0000024e ), + .LI(\blk00000003/sig0000024f ), + .O(\blk00000003/sig00000250 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000af ( + .C(clk), + .CE(ce), + .D(coef_ld), + .Q(\blk00000003/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ae ( + .C(clk), + .CE(ce), + .D(coef_we), + .Q(\blk00000003/sig0000024c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e2 ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000024b ), + .Q(\blk00000003/sig00000233 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000249 ), + .Q(\blk00000003/sig0000024a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000248 ), + .Q(\blk00000003/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000247 ), + .Q(\blk00000003/sig0000023e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000245 ), + .Q(\blk00000003/sig00000246 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000241 ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000240 ), + .Q(\blk00000003/sig0000023c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000023c ), + .Q(\blk00000003/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021d ), + .Q(\blk00000003/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000236 ), + .Q(\blk00000003/sig0000023a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000230 ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk000000a0_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022d ), + .R(coef_ld), + .Q(\blk00000003/sig0000022c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000022a ), + .R(coef_ld), + .Q(\NLW_blk00000003/blk0000009e_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000226 ), + .R(coef_ld), + .Q(\blk00000003/sig00000224 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021e ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000239 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000237 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000238 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000235 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000236 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000233 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000234 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig00000231 ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig00000232 ) + ); + MUXCY_D \blk00000003/blk00000097 ( + .CI(coef_we), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022f ), + .O(\blk00000003/sig00000228 ), + .LO(\blk00000003/sig00000230 ) + ); + MUXCY_D \blk00000003/blk00000096 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig0000022e ), + .O(\blk00000003/sig0000022b ), + .LO(\NLW_blk00000003/blk00000096_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000095 ( + .CI(\blk00000003/sig0000022b ), + .DI(\blk00000003/sig0000022c ), + .S(coef_we), + .O(\NLW_blk00000003/blk00000095_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022d ) + ); + MUXCY_D \blk00000003/blk00000094 ( + .CI(\blk00000003/sig00000228 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000229 ), + .O(\NLW_blk00000003/blk00000094_O_UNCONNECTED ), + .LO(\blk00000003/sig0000022a ) + ); + MUXCY_D \blk00000003/blk00000093 ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig00000227 ), + .O(\blk00000003/sig00000223 ), + .LO(\NLW_blk00000003/blk00000093_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk00000092 ( + .CI(\blk00000003/sig00000223 ), + .DI(\blk00000003/sig00000224 ), + .S(\blk00000003/sig00000225 ), + .O(\NLW_blk00000003/blk00000092_O_UNCONNECTED ), + .LO(\blk00000003/sig00000226 ) + ); + XORCY \blk00000003/blk00000091 ( + .CI(\blk00000003/sig0000021c ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig0000021a ) + ); + MUXCY_D \blk00000003/blk00000090 ( + .CI(\blk00000003/sig00000220 ), + .DI(\blk00000003/sig00000221 ), + .S(\blk00000003/sig00000222 ), + .O(\NLW_blk00000003/blk00000090_O_UNCONNECTED ), + .LO(\blk00000003/sig0000021c ) + ); + MUXCY_D \blk00000003/blk0000008f ( + .CI(\blk00000003/sig0000021d ), + .DI(\blk00000003/sig0000021e ), + .S(\blk00000003/sig0000021f ), + .O(\blk00000003/sig00000220 ), + .LO(\NLW_blk00000003/blk0000008f_LO_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021c ), + .R(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021d ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk0000008d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig0000021a ), + .S(\blk00000003/sig00000049 ), + .Q(\blk00000003/sig0000021b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e7 ), + .R(sclr), + .Q(\blk00000003/sig000001e6 ) + ); + FDR #( + .INIT ( 1'b1 )) + \blk00000003/blk00000028 ( + .C(clk), + .D(\blk00000003/sig000000b6 ), + .R(sclr), + .Q(\blk00000003/sig000000b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e6 ), + .R(sclr), + .Q(\blk00000003/sig000001e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e5 ), + .R(\blk00000003/sig000001e0 ), + .Q(data_valid) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e3 ), + .R(sclr), + .Q(\blk00000003/sig000001e4 ) + ); + FDRE \blk00000003/blk00000024 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001e1 ), + .R(sclr), + .Q(\blk00000003/sig000001e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001df ), + .R(\blk00000003/sig000001e0 ), + .Q(rdy) + ); + FDSE \blk00000003/blk00000022 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001dd ), + .S(sclr), + .Q(\blk00000003/sig000001de ) + ); + FDRE \blk00000003/blk00000021 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001db ), + .R(sclr), + .Q(\blk00000003/sig000001dc ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000020 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cc ), + .S(sclr), + .Q(NlwRenamedSig_OI_rfd) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ca ), + .R(sclr), + .Q(\blk00000003/sig000001da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d9 ), + .R(sclr), + .Q(\blk00000003/sig000001c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001c6 ), + .R(sclr), + .Q(\blk00000003/sig000001d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d7 ), + .R(sclr), + .Q(\blk00000003/sig000001c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d5 ), + .R(sclr), + .Q(\blk00000003/sig000001d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d3 ), + .R(sclr), + .Q(\blk00000003/sig000001d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000019_Q_UNCONNECTED ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001d1 ), + .R(sclr), + .Q(\blk00000003/sig000001d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001cf ), + .Q(\blk00000003/sig000001d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000001ce ), + .Q(\blk00000003/sig000001cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000c0 ), + .R(sclr), + .Q(\blk00000003/sig000000be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000014 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bb ), + .R(sclr), + .Q(\NLW_blk00000003/blk00000014_Q_UNCONNECTED ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000013 ( + .C(clk), + .CE(ce), + .D(\blk00000003/sig000000bc ), + .S(sclr), + .Q(\blk00000003/sig000001cd ) + ); + MUXCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig000001c9 ), + .DI(\blk00000003/sig000000ae ), + .S(\blk00000003/sig000001cb ), + .O(\blk00000003/sig000001cc ) + ); + MUXCY_D \blk00000003/blk00000011 ( + .CI(\blk00000003/sig000001c7 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c8 ), + .O(\blk00000003/sig000001c9 ), + .LO(\blk00000003/sig000001ca ) + ); + MUXCY_D \blk00000003/blk00000010 ( + .CI(\blk00000003/sig000001c4 ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000001c5 ), + .O(\NLW_blk00000003/blk00000010_O_UNCONNECTED ), + .LO(\blk00000003/sig000001c6 ) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000f ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000f_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000f_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000f_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000f_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000f_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000f_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000f_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig0000014c , \blk00000003/sig0000014d , \blk00000003/sig0000014e , \blk00000003/sig0000014f , \blk00000003/sig00000150 , +\blk00000003/sig00000151 , \blk00000003/sig00000152 , \blk00000003/sig00000153 , \blk00000003/sig00000154 , \blk00000003/sig00000155 , +\blk00000003/sig00000156 , \blk00000003/sig00000157 , \blk00000003/sig00000158 , \blk00000003/sig00000159 , \blk00000003/sig0000015a , +\blk00000003/sig0000015b , \blk00000003/sig0000015c , \blk00000003/sig0000015d , \blk00000003/sig0000015e , \blk00000003/sig0000015f , +\blk00000003/sig00000160 , \blk00000003/sig00000161 , \blk00000003/sig00000162 , \blk00000003/sig00000163 , \blk00000003/sig00000164 , +\blk00000003/sig00000165 , \blk00000003/sig00000166 , \blk00000003/sig00000167 , \blk00000003/sig00000168 , \blk00000003/sig00000169 , +\blk00000003/sig0000016a , \blk00000003/sig0000016b , \blk00000003/sig0000016c , \blk00000003/sig0000016d , \blk00000003/sig0000016e , +\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000f_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000f_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig0000017c , \blk00000003/sig0000017d , \blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 , +\blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , \blk00000003/sig00000185 , +\blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , \blk00000003/sig0000018a , +\blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , \blk00000003/sig0000018f , +\blk00000003/sig00000190 , \blk00000003/sig00000191 , \blk00000003/sig00000192 , \blk00000003/sig00000193 , \blk00000003/sig00000194 , +\blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , \blk00000003/sig00000198 , \blk00000003/sig00000199 , +\blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , \blk00000003/sig0000019d , \blk00000003/sig0000019e , +\blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , \blk00000003/sig000001a2 , \blk00000003/sig000001a3 , +\blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , \blk00000003/sig000001a7 , \blk00000003/sig000001a8 , +\blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab }), + .A({\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ac , +\blk00000003/sig000001ac , \blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , +\blk00000003/sig000001b0 , \blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , +\blk00000003/sig000001b5 , \blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , +\blk00000003/sig000001ba , \blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , +\blk00000003/sig000001bf , \blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 , \blk00000003/sig000001c3 }), + .PCOUT({\NLW_blk00000003/blk0000000f_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000f_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000f_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + DSP48E1 #( + .ACASCREG ( 2 ), + .ADREG ( 0 ), + .ALUMODEREG ( 1 ), + .AREG ( 2 ), + .AUTORESET_PATDET ( "NO_RESET" ), + .A_INPUT ( "DIRECT" ), + .BCASCREG ( 2 ), + .BREG ( 2 ), + .B_INPUT ( "DIRECT" ), + .CARRYINREG ( 1 ), + .CARRYINSELREG ( 1 ), + .CREG ( 1 ), + .DREG ( 0 ), + .INMODEREG ( 0 ), + .MASK ( 48'hFFFFFFFFFFFE ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PATTERN ( 48'h000000000000 ), + .PREG ( 1 ), + .SEL_MASK ( "MASK" ), + .SEL_PATTERN ( "PATTERN" ), + .USE_DPORT ( "FALSE" ), + .USE_MULT ( "MULTIPLY" ), + .USE_PATTERN_DETECT ( "NO_PATDET" ), + .USE_SIMD ( "ONE48" )) + \blk00000003/blk0000000e ( + .PATTERNBDETECT(\NLW_blk00000003/blk0000000e_PATTERNBDETECT_UNCONNECTED ), + .RSTC(\blk00000003/sig00000049 ), + .CEB1(ce), + .CEAD(\blk00000003/sig00000049 ), + .MULTSIGNOUT(\NLW_blk00000003/blk0000000e_MULTSIGNOUT_UNCONNECTED ), + .CEC(ce), + .RSTM(\blk00000003/sig00000049 ), + .MULTSIGNIN(\blk00000003/sig00000049 ), + .CEB2(ce), + .RSTCTRL(\blk00000003/sig00000049 ), + .CEP(ce), + .CARRYCASCOUT(\NLW_blk00000003/blk0000000e_CARRYCASCOUT_UNCONNECTED ), + .RSTA(\blk00000003/sig00000049 ), + .CECARRYIN(ce), + .UNDERFLOW(\NLW_blk00000003/blk0000000e_UNDERFLOW_UNCONNECTED ), + .PATTERNDETECT(\NLW_blk00000003/blk0000000e_PATTERNDETECT_UNCONNECTED ), + .RSTALUMODE(\blk00000003/sig00000049 ), + .RSTALLCARRYIN(\blk00000003/sig00000049 ), + .CED(\blk00000003/sig00000049 ), + .RSTD(\blk00000003/sig00000049 ), + .CEALUMODE(ce), + .CEA2(ce), + .CLK(clk), + .CEA1(ce), + .RSTB(\blk00000003/sig00000049 ), + .OVERFLOW(\NLW_blk00000003/blk0000000e_OVERFLOW_UNCONNECTED ), + .CECTRL(ce), + .CEM(ce), + .CARRYIN(\blk00000003/sig00000049 ), + .CARRYCASCIN(\blk00000003/sig00000049 ), + .RSTINMODE(\blk00000003/sig00000049 ), + .CEINMODE(ce), + .RSTP(\blk00000003/sig00000049 ), + .ACOUT({\NLW_blk00000003/blk0000000e_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_ACOUT<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000b0 , \blk00000003/sig00000049 , \blk00000003/sig000000b4 , +\blk00000003/sig000000b2 , \blk00000003/sig000000b4 }), + .PCIN({\blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , \blk00000003/sig000000c6 , +\blk00000003/sig000000c7 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d0 , +\blk00000003/sig000000d1 , \blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , +\blk00000003/sig000000d6 , \blk00000003/sig000000d7 , \blk00000003/sig000000d8 , \blk00000003/sig000000d9 , \blk00000003/sig000000da , +\blk00000003/sig000000db , \blk00000003/sig000000dc , \blk00000003/sig000000dd , \blk00000003/sig000000de , \blk00000003/sig000000df , +\blk00000003/sig000000e0 , \blk00000003/sig000000e1 , \blk00000003/sig000000e2 , \blk00000003/sig000000e3 , \blk00000003/sig000000e4 , +\blk00000003/sig000000e5 , \blk00000003/sig000000e6 , \blk00000003/sig000000e7 , \blk00000003/sig000000e8 , \blk00000003/sig000000e9 , +\blk00000003/sig000000ea , \blk00000003/sig000000eb , \blk00000003/sig000000ec , \blk00000003/sig000000ed , \blk00000003/sig000000ee , +\blk00000003/sig000000ef , \blk00000003/sig000000f0 , \blk00000003/sig000000f1 }), + .ALUMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .C({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYOUT({\NLW_blk00000003/blk0000000e_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_CARRYOUT<0>_UNCONNECTED }), + .INMODE({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig000000ae , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .BCIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .B({\blk00000003/sig000000f2 , \blk00000003/sig000000f3 , \blk00000003/sig000000f4 , \blk00000003/sig000000f5 , \blk00000003/sig000000f6 , +\blk00000003/sig000000f7 , \blk00000003/sig000000f8 , \blk00000003/sig000000f9 , \blk00000003/sig000000fa , \blk00000003/sig000000fb , +\blk00000003/sig000000fc , \blk00000003/sig000000fd , \blk00000003/sig000000fe , \blk00000003/sig000000ff , \blk00000003/sig00000100 , +\blk00000003/sig00000101 , \blk00000003/sig00000102 , \blk00000003/sig00000103 }), + .BCOUT({\NLW_blk00000003/blk0000000e_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_BCOUT<0>_UNCONNECTED }), + .D({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .P({\blk00000003/sig00000104 , \blk00000003/sig00000105 , \blk00000003/sig00000106 , \blk00000003/sig00000107 , \blk00000003/sig00000108 , +\blk00000003/sig00000109 , \blk00000003/sig0000010a , \blk00000003/sig0000010b , \blk00000003/sig0000010c , \blk00000003/sig0000010d , +\blk00000003/sig0000010e , \blk00000003/sig0000010f , \blk00000003/sig00000110 , \blk00000003/sig00000111 , \blk00000003/sig00000112 , +\blk00000003/sig00000113 , \blk00000003/sig00000114 , \blk00000003/sig00000115 , \blk00000003/sig00000116 , \blk00000003/sig00000117 , +\blk00000003/sig00000118 , \blk00000003/sig00000119 , \blk00000003/sig0000011a , \blk00000003/sig0000011b , \blk00000003/sig0000011c , +\blk00000003/sig0000011d , \blk00000003/sig0000011e , \blk00000003/sig0000011f , \blk00000003/sig00000120 , \blk00000003/sig00000121 , +\blk00000003/sig00000122 , \blk00000003/sig00000123 , \blk00000003/sig00000124 , \blk00000003/sig00000125 , \blk00000003/sig00000126 , +\blk00000003/sig00000127 , \blk00000003/sig00000128 , \blk00000003/sig00000129 , \blk00000003/sig0000012a , \blk00000003/sig0000012b , +\blk00000003/sig0000012c , \blk00000003/sig0000012d , \blk00000003/sig0000012e , \blk00000003/sig0000012f , \blk00000003/sig00000130 , +\blk00000003/sig00000131 , \blk00000003/sig00000132 , \blk00000003/sig00000133 }), + .A({\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000134 , +\blk00000003/sig00000134 , \blk00000003/sig00000134 , \blk00000003/sig00000135 , \blk00000003/sig00000136 , \blk00000003/sig00000137 , +\blk00000003/sig00000138 , \blk00000003/sig00000139 , \blk00000003/sig0000013a , \blk00000003/sig0000013b , \blk00000003/sig0000013c , +\blk00000003/sig0000013d , \blk00000003/sig0000013e , \blk00000003/sig0000013f , \blk00000003/sig00000140 , \blk00000003/sig00000141 , +\blk00000003/sig00000142 , \blk00000003/sig00000143 , \blk00000003/sig00000144 , \blk00000003/sig00000145 , \blk00000003/sig00000146 , +\blk00000003/sig00000147 , \blk00000003/sig00000148 , \blk00000003/sig00000149 , \blk00000003/sig0000014a , \blk00000003/sig0000014b }), + .PCOUT({\NLW_blk00000003/blk0000000e_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk0000000e_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk0000000e_PCOUT<0>_UNCONNECTED }), + .ACIN({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , +\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }), + .CARRYINSEL({\blk00000003/sig00000049 , \blk00000003/sig00000049 , \blk00000003/sig00000049 }) + ); + MUXCY_D \blk00000003/blk0000000d ( + .CI(\blk00000003/sig000000ae ), + .DI(\blk00000003/sig00000049 ), + .S(\blk00000003/sig000000c1 ), + .O(\blk00000003/sig000000bd ), + .LO(\NLW_blk00000003/blk0000000d_LO_UNCONNECTED ) + ); + MUXCY_D \blk00000003/blk0000000c ( + .CI(\blk00000003/sig000000bd ), + .DI(\blk00000003/sig000000be ), + .S(\blk00000003/sig000000bf ), + .O(\blk00000003/sig000000b5 ), + .LO(\blk00000003/sig000000c0 ) + ); + XORCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig000000bb ), + .LI(\blk00000003/sig000000ae ), + .O(\blk00000003/sig000000bc ) + ); + MUXCY_D \blk00000003/blk0000000a ( + .CI(\blk00000003/sig000000b8 ), + .DI(\blk00000003/sig000000b9 ), + .S(\blk00000003/sig000000ba ), + .O(\NLW_blk00000003/blk0000000a_O_UNCONNECTED ), + .LO(\blk00000003/sig000000bb ) + ); + MUXCY_D \blk00000003/blk00000009 ( + .CI(\blk00000003/sig000000b5 ), + .DI(\blk00000003/sig000000b6 ), + .S(\blk00000003/sig000000b7 ), + .O(\blk00000003/sig000000b8 ), + .LO(\NLW_blk00000003/blk00000009_LO_UNCONNECTED ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000008 ( + .C(clk), + .D(\blk00000003/sig000000b3 ), + .Q(\blk00000003/sig000000b4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000007 ( + .C(clk), + .D(\blk00000003/sig000000b1 ), + .Q(\blk00000003/sig000000b2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000006 ( + .C(clk), + .D(\blk00000003/sig000000af ), + .Q(\blk00000003/sig000000b0 ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig000000ae ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000049 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000002a/blk0000008c ( + .I0(nd), + .I1(ce), + .O(\blk00000003/blk0000002a/sig000006fd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000008a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000008a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fa ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000089 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000089_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006fc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000088 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000088_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000087 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000087_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000086 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000086_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000085 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000085_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000084 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000084_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000083 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000083_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000082 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000082_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000081 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000081_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000080 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000080_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ef ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ee ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006f0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ec ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006eb ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000007a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000007a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ed ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000079 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000079_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000078 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000078_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000077 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000077_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ea ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000076 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000076_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000075 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000075_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000074 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_2_2[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000074_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000073 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[22]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000073_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000072 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[21]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000072_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000071 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[23]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000071_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000070 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[19]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000070_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[18]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006df ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[20]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[16]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[15]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006dc ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006b ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[17]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006de ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000006a ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[13]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000006a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006da ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000069 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[12]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000069_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d9 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000068 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[14]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000068_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006db ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000067 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[10]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000067_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000066 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[9]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000066_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000065 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[11]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000065_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d8 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000064 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[7]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000064_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000063 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[6]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000063_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000062 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[8]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000062_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000061 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[4]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000061_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk00000060 ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[3]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk00000060_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005f ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[5]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005e ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[1]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006ce ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005d ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[0]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cd ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk0000002a/blk0000005c ( + .A0(\blk00000003/sig000001e9 ), + .A1(\blk00000003/sig000001e8 ), + .A2(\blk00000003/blk0000002a/sig000006cc ), + .A3(\blk00000003/blk0000002a/sig000006cc ), + .A4(\blk00000003/blk0000002a/sig000006cc ), + .D(din_1_1[2]), + .DPRA0(\blk00000003/sig000001de ), + .DPRA1(\blk00000003/sig000001dc ), + .DPRA2(\blk00000003/blk0000002a/sig000006cc ), + .DPRA3(\blk00000003/blk0000002a/sig000006cc ), + .DPRA4(\blk00000003/blk0000002a/sig000006cc ), + .WCLK(clk), + .WE(\blk00000003/blk0000002a/sig000006fd ), + .SPO(\NLW_blk00000003/blk0000002a/blk0000005c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk0000002a/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fc ), + .Q(\blk00000003/sig000001ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fb ), + .Q(\blk00000003/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006fa ), + .Q(\blk00000003/sig000001ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f9 ), + .Q(\blk00000003/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f8 ), + .Q(\blk00000003/sig000001ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f7 ), + .Q(\blk00000003/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f6 ), + .Q(\blk00000003/sig000001f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f5 ), + .Q(\blk00000003/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f4 ), + .Q(\blk00000003/sig000001f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f3 ), + .Q(\blk00000003/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f2 ), + .Q(\blk00000003/sig000001f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f1 ), + .Q(\blk00000003/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006f0 ), + .Q(\blk00000003/sig000001f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ef ), + .Q(\blk00000003/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ee ), + .Q(\blk00000003/sig000001f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ed ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ec ), + .Q(\blk00000003/sig000001fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006eb ), + .Q(\blk00000003/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ea ), + .Q(\blk00000003/sig000001fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e9 ), + .Q(\blk00000003/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e8 ), + .Q(\blk00000003/sig000001fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e7 ), + .Q(\blk00000003/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e6 ), + .Q(\blk00000003/sig00000200 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e5 ), + .Q(\blk00000003/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e4 ), + .Q(\blk00000003/sig00000202 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e3 ), + .Q(\blk00000003/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e2 ), + .Q(\blk00000003/sig00000204 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e1 ), + .Q(\blk00000003/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006e0 ), + .Q(\blk00000003/sig00000206 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006df ), + .Q(\blk00000003/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006de ), + .Q(\blk00000003/sig00000208 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dd ), + .Q(\blk00000003/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006dc ), + .Q(\blk00000003/sig0000020a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006db ), + .Q(\blk00000003/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006da ), + .Q(\blk00000003/sig0000020c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d9 ), + .Q(\blk00000003/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d8 ), + .Q(\blk00000003/sig0000020e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d7 ), + .Q(\blk00000003/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d6 ), + .Q(\blk00000003/sig00000210 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d5 ), + .Q(\blk00000003/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d4 ), + .Q(\blk00000003/sig00000212 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d3 ), + .Q(\blk00000003/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d2 ), + .Q(\blk00000003/sig00000214 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d1 ), + .Q(\blk00000003/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006d0 ), + .Q(\blk00000003/sig00000216 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cf ), + .Q(\blk00000003/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006ce ), + .Q(\blk00000003/sig00000218 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000002a/sig000006cd ), + .Q(\blk00000003/sig00000219 ) + ); + GND \blk00000003/blk0000002a/blk0000002b ( + .G(\blk00000003/blk0000002a/sig000006cc ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000119/blk0000014b ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk00000119/sig0000074d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000014a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f5 ), + .Q(\blk00000003/blk00000119/sig0000074b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000014a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000149 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f6 ), + .Q(\blk00000003/blk00000119/sig0000074a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000149_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000148 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f4 ), + .Q(\blk00000003/blk00000119/sig0000074c ), + .Q15(\NLW_blk00000003/blk00000119/blk00000148_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000147 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f8 ), + .Q(\blk00000003/blk00000119/sig00000748 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000147_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000146 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f9 ), + .Q(\blk00000003/blk00000119/sig00000747 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000146_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000145 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002f7 ), + .Q(\blk00000003/blk00000119/sig00000749 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000145_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000144 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fb ), + .Q(\blk00000003/blk00000119/sig00000745 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000144_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000143 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fc ), + .Q(\blk00000003/blk00000119/sig00000744 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000143_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000142 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fa ), + .Q(\blk00000003/blk00000119/sig00000746 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000142_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000141 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fe ), + .Q(\blk00000003/blk00000119/sig00000742 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000141_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000140 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002ff ), + .Q(\blk00000003/blk00000119/sig00000741 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000140_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig000002fd ), + .Q(\blk00000003/blk00000119/sig00000743 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000301 ), + .Q(\blk00000003/blk00000119/sig0000073f ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000302 ), + .Q(\blk00000003/blk00000119/sig0000073e ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000300 ), + .Q(\blk00000003/blk00000119/sig00000740 ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000304 ), + .Q(\blk00000003/blk00000119/sig0000073c ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk0000013a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000305 ), + .Q(\blk00000003/blk00000119/sig0000073b ), + .Q15(\NLW_blk00000003/blk00000119/blk0000013a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000139 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000303 ), + .Q(\blk00000003/blk00000119/sig0000073d ), + .Q15(\NLW_blk00000003/blk00000119/blk00000139_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000138 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000307 ), + .Q(\blk00000003/blk00000119/sig00000739 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000138_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000137 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000308 ), + .Q(\blk00000003/blk00000119/sig00000738 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000137_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000136 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000306 ), + .Q(\blk00000003/blk00000119/sig0000073a ), + .Q15(\NLW_blk00000003/blk00000119/blk00000136_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000135 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030a ), + .Q(\blk00000003/blk00000119/sig00000736 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000135_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000134 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig0000030b ), + .Q(\blk00000003/blk00000119/sig00000735 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000134_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000119/blk00000133 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk00000119/sig00000734 ), + .CE(\blk00000003/blk00000119/sig0000074d ), + .CLK(clk), + .D(\blk00000003/sig00000309 ), + .Q(\blk00000003/blk00000119/sig00000737 ), + .Q15(\NLW_blk00000003/blk00000119/blk00000133_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000132 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074c ), + .Q(\blk00000003/sig000003c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000131 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074b ), + .Q(\blk00000003/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000130 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000074a ), + .Q(\blk00000003/sig000003c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000749 ), + .Q(\blk00000003/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000748 ), + .Q(\blk00000003/sig000003ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000747 ), + .Q(\blk00000003/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000746 ), + .Q(\blk00000003/sig000003cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000745 ), + .Q(\blk00000003/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000012a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000744 ), + .Q(\blk00000003/sig000003ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000129 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000743 ), + .Q(\blk00000003/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000128 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000742 ), + .Q(\blk00000003/sig000003d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000127 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000741 ), + .Q(\blk00000003/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000126 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000740 ), + .Q(\blk00000003/sig000003d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000125 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073f ), + .Q(\blk00000003/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000124 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073e ), + .Q(\blk00000003/sig000003d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000123 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073d ), + .Q(\blk00000003/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000122 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073c ), + .Q(\blk00000003/sig000003d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073b ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig0000073a ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000739 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000738 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000737 ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000736 ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000119/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000119/sig00000735 ), + .Q(\blk00000003/sig000003dd ) + ); + GND \blk00000003/blk00000119/blk0000011a ( + .G(\blk00000003/blk00000119/sig00000734 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000014c/blk0000017e ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk0000014c/sig0000079d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043a ), + .Q(\blk00000003/blk0000014c/sig0000079b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043b ), + .Q(\blk00000003/blk0000014c/sig0000079a ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000439 ), + .Q(\blk00000003/blk0000014c/sig0000079c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000017a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043d ), + .Q(\blk00000003/blk0000014c/sig00000798 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000017a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000179 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043e ), + .Q(\blk00000003/blk0000014c/sig00000797 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000179_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000178 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043c ), + .Q(\blk00000003/blk0000014c/sig00000799 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000178_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000177 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000440 ), + .Q(\blk00000003/blk0000014c/sig00000795 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000177_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000176 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000441 ), + .Q(\blk00000003/blk0000014c/sig00000794 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000176_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000175 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000043f ), + .Q(\blk00000003/blk0000014c/sig00000796 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000175_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000174 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000443 ), + .Q(\blk00000003/blk0000014c/sig00000792 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000174_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000173 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/blk0000014c/sig00000791 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000173_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000172 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000442 ), + .Q(\blk00000003/blk0000014c/sig00000793 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000172_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000171 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000446 ), + .Q(\blk00000003/blk0000014c/sig0000078f ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000171_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000170 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/blk0000014c/sig0000078e ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000170_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016f ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000445 ), + .Q(\blk00000003/blk0000014c/sig00000790 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016e ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000449 ), + .Q(\blk00000003/blk0000014c/sig0000078c ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016d ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/blk0000014c/sig0000078b ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016c ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000448 ), + .Q(\blk00000003/blk0000014c/sig0000078d ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016b ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044c ), + .Q(\blk00000003/blk0000014c/sig00000789 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk0000016a ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044d ), + .Q(\blk00000003/blk0000014c/sig00000788 ), + .Q15(\NLW_blk00000003/blk0000014c/blk0000016a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000169 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044b ), + .Q(\blk00000003/blk0000014c/sig0000078a ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000169_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000168 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044f ), + .Q(\blk00000003/blk0000014c/sig00000786 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000168_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000167 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig00000450 ), + .Q(\blk00000003/blk0000014c/sig00000785 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000167_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000014c/blk00000166 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk0000014c/sig00000784 ), + .CE(\blk00000003/blk0000014c/sig0000079d ), + .CLK(clk), + .D(\blk00000003/sig0000044e ), + .Q(\blk00000003/blk0000014c/sig00000787 ), + .Q15(\NLW_blk00000003/blk0000014c/blk00000166_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000165 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079c ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000164 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079b ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000163 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000079a ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000162 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000799 ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000798 ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000797 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000796 ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000795 ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000794 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000793 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000792 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000015a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000791 ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000159 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000790 ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000158 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078f ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000157 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078e ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000156 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078d ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000155 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078c ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000154 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078b ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000153 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig0000078a ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000152 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000789 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000788 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000787 ), + .Q(\blk00000003/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000786 ), + .Q(\blk00000003/sig000003f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014c/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000014c/sig00000785 ), + .Q(\blk00000003/sig000003f5 ) + ); + GND \blk00000003/blk0000014c/blk0000014d ( + .G(\blk00000003/blk0000014c/sig00000784 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000017f/blk000001b1 ( + .I0(ce), + .I1(\blk00000003/sig00000435 ), + .O(\blk00000003/blk0000017f/sig000007ed ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001b0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000355 ), + .Q(\blk00000003/blk0000017f/sig000007eb ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001b0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001af ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000356 ), + .Q(\blk00000003/blk0000017f/sig000007ea ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ae ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000354 ), + .Q(\blk00000003/blk0000017f/sig000007ec ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ad ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000358 ), + .Q(\blk00000003/blk0000017f/sig000007e8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ac ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000359 ), + .Q(\blk00000003/blk0000017f/sig000007e7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001ab ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000357 ), + .Q(\blk00000003/blk0000017f/sig000007e9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001aa ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035b ), + .Q(\blk00000003/blk0000017f/sig000007e5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a9 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035c ), + .Q(\blk00000003/blk0000017f/sig000007e4 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a8 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035a ), + .Q(\blk00000003/blk0000017f/sig000007e6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a7 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035e ), + .Q(\blk00000003/blk0000017f/sig000007e2 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a6 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035f ), + .Q(\blk00000003/blk0000017f/sig000007e1 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a5 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000035d ), + .Q(\blk00000003/blk0000017f/sig000007e3 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a4 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000361 ), + .Q(\blk00000003/blk0000017f/sig000007df ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a3 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000362 ), + .Q(\blk00000003/blk0000017f/sig000007de ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a2 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000360 ), + .Q(\blk00000003/blk0000017f/sig000007e0 ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a1 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000364 ), + .Q(\blk00000003/blk0000017f/sig000007dc ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk000001a0 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000365 ), + .Q(\blk00000003/blk0000017f/sig000007db ), + .Q15(\NLW_blk00000003/blk0000017f/blk000001a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019f ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000363 ), + .Q(\blk00000003/blk0000017f/sig000007dd ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019e ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000367 ), + .Q(\blk00000003/blk0000017f/sig000007d9 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019d ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000368 ), + .Q(\blk00000003/blk0000017f/sig000007d8 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019c ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000366 ), + .Q(\blk00000003/blk0000017f/sig000007da ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019b ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036a ), + .Q(\blk00000003/blk0000017f/sig000007d6 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk0000019a ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig0000036b ), + .Q(\blk00000003/blk0000017f/sig000007d5 ), + .Q15(\NLW_blk00000003/blk0000017f/blk0000019a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017f/blk00000199 ( + .A0(\blk00000003/sig0000042d ), + .A1(\blk00000003/sig0000042c ), + .A2(\blk00000003/sig0000042b ), + .A3(\blk00000003/blk0000017f/sig000007d4 ), + .CE(\blk00000003/blk0000017f/sig000007ed ), + .CLK(clk), + .D(\blk00000003/sig00000369 ), + .Q(\blk00000003/blk0000017f/sig000007d7 ), + .Q15(\NLW_blk00000003/blk0000017f/blk00000199_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ec ), + .Q(\blk00000003/sig000003f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007eb ), + .Q(\blk00000003/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007ea ), + .Q(\blk00000003/sig000003f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e9 ), + .Q(\blk00000003/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e8 ), + .Q(\blk00000003/sig000003fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e7 ), + .Q(\blk00000003/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e6 ), + .Q(\blk00000003/sig000003fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e5 ), + .Q(\blk00000003/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e4 ), + .Q(\blk00000003/sig000003fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e3 ), + .Q(\blk00000003/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e2 ), + .Q(\blk00000003/sig00000400 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e1 ), + .Q(\blk00000003/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007e0 ), + .Q(\blk00000003/sig00000402 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007df ), + .Q(\blk00000003/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk0000018a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007de ), + .Q(\blk00000003/sig00000404 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000189 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dd ), + .Q(\blk00000003/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000188 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007dc ), + .Q(\blk00000003/sig00000406 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000187 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007db ), + .Q(\blk00000003/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000186 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007da ), + .Q(\blk00000003/sig00000408 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000185 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d9 ), + .Q(\blk00000003/sig00000409 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d8 ), + .Q(\blk00000003/sig0000040a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d7 ), + .Q(\blk00000003/sig0000040b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d6 ), + .Q(\blk00000003/sig0000040c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017f/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000017f/sig000007d5 ), + .Q(\blk00000003/sig0000040d ) + ); + GND \blk00000003/blk0000017f/blk00000180 ( + .G(\blk00000003/blk0000017f/sig000007d4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001b2/blk000001e4 ( + .I0(ce), + .I1(\blk00000003/sig0000042f ), + .O(\blk00000003/blk000001b2/sig0000083d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000452 ), + .Q(\blk00000003/blk000001b2/sig0000083b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000453 ), + .Q(\blk00000003/blk000001b2/sig0000083a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000451 ), + .Q(\blk00000003/blk000001b2/sig0000083c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001e0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000455 ), + .Q(\blk00000003/blk000001b2/sig00000838 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001e0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001df ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000456 ), + .Q(\blk00000003/blk000001b2/sig00000837 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001df_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001de ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000454 ), + .Q(\blk00000003/blk000001b2/sig00000839 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001de_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000458 ), + .Q(\blk00000003/blk000001b2/sig00000835 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001dc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000459 ), + .Q(\blk00000003/blk000001b2/sig00000834 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001dc_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001db ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000457 ), + .Q(\blk00000003/blk000001b2/sig00000836 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001db_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001da ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045b ), + .Q(\blk00000003/blk000001b2/sig00000832 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001da_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d9 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045c ), + .Q(\blk00000003/blk000001b2/sig00000831 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d8 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045a ), + .Q(\blk00000003/blk000001b2/sig00000833 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d7 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045e ), + .Q(\blk00000003/blk000001b2/sig0000082f ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d6 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045f ), + .Q(\blk00000003/blk000001b2/sig0000082e ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d5 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig0000045d ), + .Q(\blk00000003/blk000001b2/sig00000830 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d4 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000461 ), + .Q(\blk00000003/blk000001b2/sig0000082c ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d3 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000462 ), + .Q(\blk00000003/blk000001b2/sig0000082b ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d2 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000460 ), + .Q(\blk00000003/blk000001b2/sig0000082d ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d1 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000464 ), + .Q(\blk00000003/blk000001b2/sig00000829 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001d0 ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000465 ), + .Q(\blk00000003/blk000001b2/sig00000828 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001d0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cf ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000463 ), + .Q(\blk00000003/blk000001b2/sig0000082a ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cf_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001ce ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000467 ), + .Q(\blk00000003/blk000001b2/sig00000826 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001ce_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cd ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/blk000001b2/sig00000825 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cd_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001b2/blk000001cc ( + .A0(\blk00000003/sig00000438 ), + .A1(\blk00000003/sig00000437 ), + .A2(\blk00000003/sig00000436 ), + .A3(\blk00000003/blk000001b2/sig00000824 ), + .CE(\blk00000003/blk000001b2/sig0000083d ), + .CLK(clk), + .D(\blk00000003/sig00000466 ), + .Q(\blk00000003/blk000001b2/sig00000827 ), + .Q15(\NLW_blk00000003/blk000001b2/blk000001cc_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083c ), + .Q(\blk00000003/sig0000040e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083b ), + .Q(\blk00000003/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000083a ), + .Q(\blk00000003/sig00000410 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000839 ), + .Q(\blk00000003/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000838 ), + .Q(\blk00000003/sig00000412 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000837 ), + .Q(\blk00000003/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000836 ), + .Q(\blk00000003/sig00000414 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000835 ), + .Q(\blk00000003/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000834 ), + .Q(\blk00000003/sig00000416 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000833 ), + .Q(\blk00000003/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000832 ), + .Q(\blk00000003/sig00000418 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000831 ), + .Q(\blk00000003/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000830 ), + .Q(\blk00000003/sig0000041a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082f ), + .Q(\blk00000003/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082e ), + .Q(\blk00000003/sig0000041c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082d ), + .Q(\blk00000003/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082c ), + .Q(\blk00000003/sig0000041e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082b ), + .Q(\blk00000003/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig0000082a ), + .Q(\blk00000003/sig00000420 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000829 ), + .Q(\blk00000003/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000828 ), + .Q(\blk00000003/sig00000422 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000827 ), + .Q(\blk00000003/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000826 ), + .Q(\blk00000003/sig00000424 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001b2/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001b2/sig00000825 ), + .Q(\blk00000003/sig00000425 ) + ); + GND \blk00000003/blk000001b2/blk000001b3 ( + .G(\blk00000003/blk000001b2/sig00000824 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000001e5/blk00000217 ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk000001e5/sig0000088d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000216 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046a ), + .Q(\blk00000003/blk000001e5/sig0000088b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000216_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000215 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046b ), + .Q(\blk00000003/blk000001e5/sig0000088a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000215_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000214 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000469 ), + .Q(\blk00000003/blk000001e5/sig0000088c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000214_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000213 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046d ), + .Q(\blk00000003/blk000001e5/sig00000888 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000213_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000212 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046e ), + .Q(\blk00000003/blk000001e5/sig00000887 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000212_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000211 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046c ), + .Q(\blk00000003/blk000001e5/sig00000889 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000211_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000210 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000470 ), + .Q(\blk00000003/blk000001e5/sig00000885 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000210_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000471 ), + .Q(\blk00000003/blk000001e5/sig00000884 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000046f ), + .Q(\blk00000003/blk000001e5/sig00000886 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000473 ), + .Q(\blk00000003/blk000001e5/sig00000882 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000474 ), + .Q(\blk00000003/blk000001e5/sig00000881 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000472 ), + .Q(\blk00000003/blk000001e5/sig00000883 ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk0000020a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000476 ), + .Q(\blk00000003/blk000001e5/sig0000087f ), + .Q15(\NLW_blk00000003/blk000001e5/blk0000020a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000209 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000477 ), + .Q(\blk00000003/blk000001e5/sig0000087e ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000209_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000208 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000475 ), + .Q(\blk00000003/blk000001e5/sig00000880 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000208_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000207 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000479 ), + .Q(\blk00000003/blk000001e5/sig0000087c ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000207_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000206 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047a ), + .Q(\blk00000003/blk000001e5/sig0000087b ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000206_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000205 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000478 ), + .Q(\blk00000003/blk000001e5/sig0000087d ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000205_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000204 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047c ), + .Q(\blk00000003/blk000001e5/sig00000879 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000204_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000203 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/blk000001e5/sig00000878 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000203_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000202 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047b ), + .Q(\blk00000003/blk000001e5/sig0000087a ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000202_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000201 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047f ), + .Q(\blk00000003/blk000001e5/sig00000876 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000201_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk00000200 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig00000480 ), + .Q(\blk00000003/blk000001e5/sig00000875 ), + .Q15(\NLW_blk00000003/blk000001e5/blk00000200_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001e5/blk000001ff ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk000001e5/sig00000874 ), + .CE(\blk00000003/blk000001e5/sig0000088d ), + .CLK(clk), + .D(\blk00000003/sig0000047e ), + .Q(\blk00000003/blk000001e5/sig00000877 ), + .Q15(\NLW_blk00000003/blk000001e5/blk000001ff_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088c ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088b ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000088a ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000889 ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000888 ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000887 ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000886 ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000885 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000884 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000883 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000882 ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000881 ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000880 ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087f ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087e ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087d ), + .Q(\blk00000003/sig00000303 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087c ), + .Q(\blk00000003/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087b ), + .Q(\blk00000003/sig00000305 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig0000087a ), + .Q(\blk00000003/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000879 ), + .Q(\blk00000003/sig00000307 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000878 ), + .Q(\blk00000003/sig00000308 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000877 ), + .Q(\blk00000003/sig00000309 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000876 ), + .Q(\blk00000003/sig0000030a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e5/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000001e5/sig00000875 ), + .Q(\blk00000003/sig0000030b ) + ); + GND \blk00000003/blk000001e5/blk000001e6 ( + .G(\blk00000003/blk000001e5/sig00000874 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000218/blk0000024a ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk00000218/sig000008dd ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000249 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000482 ), + .Q(\blk00000003/blk00000218/sig000008db ), + .Q15(\NLW_blk00000003/blk00000218/blk00000249_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000248 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000483 ), + .Q(\blk00000003/blk00000218/sig000008da ), + .Q15(\NLW_blk00000003/blk00000218/blk00000248_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000247 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/blk00000218/sig000008dc ), + .Q15(\NLW_blk00000003/blk00000218/blk00000247_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000246 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000485 ), + .Q(\blk00000003/blk00000218/sig000008d8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000246_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000245 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000486 ), + .Q(\blk00000003/blk00000218/sig000008d7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000245_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000244 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000484 ), + .Q(\blk00000003/blk00000218/sig000008d9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000244_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000243 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000488 ), + .Q(\blk00000003/blk00000218/sig000008d5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000243_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000242 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000489 ), + .Q(\blk00000003/blk00000218/sig000008d4 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000242_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000241 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000487 ), + .Q(\blk00000003/blk00000218/sig000008d6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000241_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000240 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048b ), + .Q(\blk00000003/blk00000218/sig000008d2 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000240_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048c ), + .Q(\blk00000003/blk00000218/sig000008d1 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048a ), + .Q(\blk00000003/blk00000218/sig000008d3 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048e ), + .Q(\blk00000003/blk00000218/sig000008cf ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048f ), + .Q(\blk00000003/blk00000218/sig000008ce ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig0000048d ), + .Q(\blk00000003/blk00000218/sig000008d0 ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk0000023a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000491 ), + .Q(\blk00000003/blk00000218/sig000008cc ), + .Q15(\NLW_blk00000003/blk00000218/blk0000023a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000239 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000492 ), + .Q(\blk00000003/blk00000218/sig000008cb ), + .Q15(\NLW_blk00000003/blk00000218/blk00000239_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000238 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000490 ), + .Q(\blk00000003/blk00000218/sig000008cd ), + .Q15(\NLW_blk00000003/blk00000218/blk00000238_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000237 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000494 ), + .Q(\blk00000003/blk00000218/sig000008c9 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000237_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000236 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000495 ), + .Q(\blk00000003/blk00000218/sig000008c8 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000236_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000235 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000493 ), + .Q(\blk00000003/blk00000218/sig000008ca ), + .Q15(\NLW_blk00000003/blk00000218/blk00000235_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000234 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000497 ), + .Q(\blk00000003/blk00000218/sig000008c6 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000234_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000233 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000498 ), + .Q(\blk00000003/blk00000218/sig000008c5 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000233_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000218/blk00000232 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk00000218/sig000008c4 ), + .CE(\blk00000003/blk00000218/sig000008dd ), + .CLK(clk), + .D(\blk00000003/sig00000496 ), + .Q(\blk00000003/blk00000218/sig000008c7 ), + .Q15(\NLW_blk00000003/blk00000218/blk00000232_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008dc ), + .Q(\blk00000003/sig0000030c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008db ), + .Q(\blk00000003/sig0000030d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008da ), + .Q(\blk00000003/sig0000030e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d9 ), + .Q(\blk00000003/sig0000030f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d8 ), + .Q(\blk00000003/sig00000310 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d7 ), + .Q(\blk00000003/sig00000311 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d6 ), + .Q(\blk00000003/sig00000312 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d5 ), + .Q(\blk00000003/sig00000313 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d4 ), + .Q(\blk00000003/sig00000314 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d3 ), + .Q(\blk00000003/sig00000315 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d2 ), + .Q(\blk00000003/sig00000316 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d1 ), + .Q(\blk00000003/sig00000317 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008d0 ), + .Q(\blk00000003/sig00000318 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cf ), + .Q(\blk00000003/sig00000319 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ce ), + .Q(\blk00000003/sig0000031a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cd ), + .Q(\blk00000003/sig0000031b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cc ), + .Q(\blk00000003/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008cb ), + .Q(\blk00000003/sig0000031d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008ca ), + .Q(\blk00000003/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c9 ), + .Q(\blk00000003/sig0000031f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c8 ), + .Q(\blk00000003/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c7 ), + .Q(\blk00000003/sig00000321 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c6 ), + .Q(\blk00000003/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000218/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000218/sig000008c5 ), + .Q(\blk00000003/sig00000323 ) + ); + GND \blk00000003/blk00000218/blk00000219 ( + .G(\blk00000003/blk00000218/sig000008c4 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000024b/blk0000027d ( + .I0(ce), + .I1(\blk00000003/sig00000434 ), + .O(\blk00000003/blk0000024b/sig0000092d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049a ), + .Q(\blk00000003/blk0000024b/sig0000092b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049b ), + .Q(\blk00000003/blk0000024b/sig0000092a ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000027a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig00000499 ), + .Q(\blk00000003/blk0000024b/sig0000092c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000027a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000279 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049d ), + .Q(\blk00000003/blk0000024b/sig00000928 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000279_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000278 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049e ), + .Q(\blk00000003/blk0000024b/sig00000927 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000278_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000277 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049c ), + .Q(\blk00000003/blk0000024b/sig00000929 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000277_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000276 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a0 ), + .Q(\blk00000003/blk0000024b/sig00000925 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000276_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000275 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a1 ), + .Q(\blk00000003/blk0000024b/sig00000924 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000275_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000274 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig0000049f ), + .Q(\blk00000003/blk0000024b/sig00000926 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000274_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000273 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a3 ), + .Q(\blk00000003/blk0000024b/sig00000922 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000273_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000272 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a4 ), + .Q(\blk00000003/blk0000024b/sig00000921 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000272_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000271 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a2 ), + .Q(\blk00000003/blk0000024b/sig00000923 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000271_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000270 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a6 ), + .Q(\blk00000003/blk0000024b/sig0000091f ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000270_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026f ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a7 ), + .Q(\blk00000003/blk0000024b/sig0000091e ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026e ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a5 ), + .Q(\blk00000003/blk0000024b/sig00000920 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026d ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a9 ), + .Q(\blk00000003/blk0000024b/sig0000091c ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026c ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004aa ), + .Q(\blk00000003/blk0000024b/sig0000091b ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026b ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004a8 ), + .Q(\blk00000003/blk0000024b/sig0000091d ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk0000026a ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/blk0000024b/sig00000919 ), + .Q15(\NLW_blk00000003/blk0000024b/blk0000026a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000269 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ad ), + .Q(\blk00000003/blk0000024b/sig00000918 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000269_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000268 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ab ), + .Q(\blk00000003/blk0000024b/sig0000091a ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000268_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000267 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/blk0000024b/sig00000916 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000267_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000266 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004b0 ), + .Q(\blk00000003/blk0000024b/sig00000915 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000266_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000024b/blk00000265 ( + .A0(\blk00000003/sig000002c6 ), + .A1(\blk00000003/sig000002c5 ), + .A2(\blk00000003/sig000002c4 ), + .A3(\blk00000003/blk0000024b/sig00000914 ), + .CE(\blk00000003/blk0000024b/sig0000092d ), + .CLK(clk), + .D(\blk00000003/sig000004ae ), + .Q(\blk00000003/blk0000024b/sig00000917 ), + .Q15(\NLW_blk00000003/blk0000024b/blk00000265_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092c ), + .Q(\blk00000003/sig00000354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092b ), + .Q(\blk00000003/sig00000355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000092a ), + .Q(\blk00000003/sig00000356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000929 ), + .Q(\blk00000003/sig00000357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000928 ), + .Q(\blk00000003/sig00000358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000927 ), + .Q(\blk00000003/sig00000359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000926 ), + .Q(\blk00000003/sig0000035a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000925 ), + .Q(\blk00000003/sig0000035b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000924 ), + .Q(\blk00000003/sig0000035c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000923 ), + .Q(\blk00000003/sig0000035d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000922 ), + .Q(\blk00000003/sig0000035e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000921 ), + .Q(\blk00000003/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000920 ), + .Q(\blk00000003/sig00000360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091f ), + .Q(\blk00000003/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091e ), + .Q(\blk00000003/sig00000362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091d ), + .Q(\blk00000003/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091c ), + .Q(\blk00000003/sig00000364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091b ), + .Q(\blk00000003/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig0000091a ), + .Q(\blk00000003/sig00000366 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000919 ), + .Q(\blk00000003/sig00000367 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000918 ), + .Q(\blk00000003/sig00000368 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000917 ), + .Q(\blk00000003/sig00000369 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000916 ), + .Q(\blk00000003/sig0000036a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000024b/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000024b/sig00000915 ), + .Q(\blk00000003/sig0000036b ) + ); + GND \blk00000003/blk0000024b/blk0000024c ( + .G(\blk00000003/blk0000024b/sig00000914 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000027e/blk000002b0 ( + .I0(ce), + .I1(\blk00000003/sig0000042e ), + .O(\blk00000003/blk0000027e/sig0000097d ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002af ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/blk0000027e/sig0000097b ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002af_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ae ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b3 ), + .Q(\blk00000003/blk0000027e/sig0000097a ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ae_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ad ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b1 ), + .Q(\blk00000003/blk0000027e/sig0000097c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ad_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ac ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/blk0000027e/sig00000978 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ac_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002ab ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b6 ), + .Q(\blk00000003/blk0000027e/sig00000977 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002ab_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002aa ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b4 ), + .Q(\blk00000003/blk0000027e/sig00000979 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002aa_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a9 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/blk0000027e/sig00000975 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a9_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a8 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b9 ), + .Q(\blk00000003/blk0000027e/sig00000974 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a8_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a7 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004b7 ), + .Q(\blk00000003/blk0000027e/sig00000976 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a7_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a6 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/blk0000027e/sig00000972 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a6_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a5 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bc ), + .Q(\blk00000003/blk0000027e/sig00000971 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a5_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a4 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004ba ), + .Q(\blk00000003/blk0000027e/sig00000973 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a4_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a3 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/blk0000027e/sig0000096f ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a3_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a2 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bf ), + .Q(\blk00000003/blk0000027e/sig0000096e ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a2_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a1 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004bd ), + .Q(\blk00000003/blk0000027e/sig00000970 ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a1_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk000002a0 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/blk0000027e/sig0000096c ), + .Q15(\NLW_blk00000003/blk0000027e/blk000002a0_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029f ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c2 ), + .Q(\blk00000003/blk0000027e/sig0000096b ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029f_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029e ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c0 ), + .Q(\blk00000003/blk0000027e/sig0000096d ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029e_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029d ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c4 ), + .Q(\blk00000003/blk0000027e/sig00000969 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029d_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029c ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c5 ), + .Q(\blk00000003/blk0000027e/sig00000968 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029c_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029b ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c3 ), + .Q(\blk00000003/blk0000027e/sig0000096a ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029b_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk0000029a ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c7 ), + .Q(\blk00000003/blk0000027e/sig00000966 ), + .Q15(\NLW_blk00000003/blk0000027e/blk0000029a_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000299 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c8 ), + .Q(\blk00000003/blk0000027e/sig00000965 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000299_Q15_UNCONNECTED ) + ); + SRLC16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000027e/blk00000298 ( + .A0(\blk00000003/sig000002d1 ), + .A1(\blk00000003/sig000002d0 ), + .A2(\blk00000003/sig000002cf ), + .A3(\blk00000003/blk0000027e/sig00000964 ), + .CE(\blk00000003/blk0000027e/sig0000097d ), + .CLK(clk), + .D(\blk00000003/sig000004c6 ), + .Q(\blk00000003/blk0000027e/sig00000967 ), + .Q15(\NLW_blk00000003/blk0000027e/blk00000298_Q15_UNCONNECTED ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097c ), + .Q(\blk00000003/sig0000036c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097b ), + .Q(\blk00000003/sig0000036d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000097a ), + .Q(\blk00000003/sig0000036e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000979 ), + .Q(\blk00000003/sig0000036f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000978 ), + .Q(\blk00000003/sig00000370 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000977 ), + .Q(\blk00000003/sig00000371 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000976 ), + .Q(\blk00000003/sig00000372 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000975 ), + .Q(\blk00000003/sig00000373 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000974 ), + .Q(\blk00000003/sig00000374 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000973 ), + .Q(\blk00000003/sig00000375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000972 ), + .Q(\blk00000003/sig00000376 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000971 ), + .Q(\blk00000003/sig00000377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000970 ), + .Q(\blk00000003/sig00000378 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096f ), + .Q(\blk00000003/sig00000379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096e ), + .Q(\blk00000003/sig0000037a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096d ), + .Q(\blk00000003/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096c ), + .Q(\blk00000003/sig0000037c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096b ), + .Q(\blk00000003/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig0000096a ), + .Q(\blk00000003/sig0000037e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000969 ), + .Q(\blk00000003/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000968 ), + .Q(\blk00000003/sig00000380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000967 ), + .Q(\blk00000003/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000966 ), + .Q(\blk00000003/sig00000382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000027e/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk0000027e/sig00000965 ), + .Q(\blk00000003/sig00000383 ) + ); + GND \blk00000003/blk0000027e/blk0000027f ( + .G(\blk00000003/blk0000027e/sig00000964 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002b1/blk000002e9 ( + .I0(ce), + .I1(\blk00000003/sig00000234 ), + .O(\blk00000003/blk000002b1/sig000009e4 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d1 ), + .DPO(\blk00000003/blk000002b1/sig000009e3 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009d0 ), + .DPO(\blk00000003/blk000002b1/sig000009e2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e6 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cf ), + .DPO(\blk00000003/blk000002b1/sig000009e1 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e5 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ce ), + .DPO(\blk00000003/blk000002b1/sig000009e0 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e4 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cd ), + .DPO(\blk00000003/blk000002b1/sig000009df ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e3 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cc ), + .DPO(\blk00000003/blk000002b1/sig000009de ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002b1/blk000002e2 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009ca ), + .DPO(\blk00000003/blk000002b1/sig000009dc ) + ); + RAM32X1D #( + .INIT ( 32'h000000E5 )) + \blk00000003/blk000002b1/blk000002e1 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c9 ), + .DPO(\blk00000003/blk000002b1/sig000009db ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002b1/blk000002e0 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009cb ), + .DPO(\blk00000003/blk000002b1/sig000009dd ) + ); + RAM32X1D #( + .INIT ( 32'h000000BD )) + \blk00000003/blk000002b1/blk000002df ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c8 ), + .DPO(\blk00000003/blk000002b1/sig000009da ) + ); + RAM32X1D #( + .INIT ( 32'h000000F1 )) + \blk00000003/blk000002b1/blk000002de ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c7 ), + .DPO(\blk00000003/blk000002b1/sig000009d9 ) + ); + RAM32X1D #( + .INIT ( 32'h0000000B )) + \blk00000003/blk000002b1/blk000002dd ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c6 ), + .DPO(\blk00000003/blk000002b1/sig000009d8 ) + ); + RAM32X1D #( + .INIT ( 32'h000000DC )) + \blk00000003/blk000002b1/blk000002dc ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c5 ), + .DPO(\blk00000003/blk000002b1/sig000009d7 ) + ); + RAM32X1D #( + .INIT ( 32'h00000057 )) + \blk00000003/blk000002b1/blk000002db ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c4 ), + .DPO(\blk00000003/blk000002b1/sig000009d6 ) + ); + RAM32X1D #( + .INIT ( 32'h00000037 )) + \blk00000003/blk000002b1/blk000002da ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c3 ), + .DPO(\blk00000003/blk000002b1/sig000009d5 ) + ); + RAM32X1D #( + .INIT ( 32'h00000072 )) + \blk00000003/blk000002b1/blk000002d9 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c1 ), + .DPO(\blk00000003/blk000002b1/sig000009d3 ) + ); + RAM32X1D #( + .INIT ( 32'h000000A7 )) + \blk00000003/blk000002b1/blk000002d8 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c0 ), + .DPO(\blk00000003/blk000002b1/sig000009d2 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002b1/blk000002d7 ( + .A0(\blk00000003/sig0000026a ), + .A1(\blk00000003/sig0000026e ), + .A2(\blk00000003/sig00000271 ), + .A3(\blk00000003/sig00000275 ), + .A4(\blk00000003/blk000002b1/sig000009bf ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000002d3 ), + .DPRA1(\blk00000003/sig000002d7 ), + .DPRA2(\blk00000003/sig000002da ), + .DPRA3(\blk00000003/sig000002e1 ), + .DPRA4(\blk00000003/blk000002b1/sig000009bf ), + .WCLK(clk), + .WE(\blk00000003/blk000002b1/sig000009e4 ), + .SPO(\blk00000003/blk000002b1/sig000009c2 ), + .DPO(\blk00000003/blk000002b1/sig000009d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e3 ), + .Q(\blk00000003/sig000002e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e2 ), + .Q(\blk00000003/sig000002e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e1 ), + .Q(\blk00000003/sig000002e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009e0 ), + .Q(\blk00000003/sig000002e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009df ), + .Q(\blk00000003/sig000002e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009de ), + .Q(\blk00000003/sig000002e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dd ), + .Q(\blk00000003/sig000002e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009dc ), + .Q(\blk00000003/sig000002e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009db ), + .Q(\blk00000003/sig000002ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009da ), + .Q(\blk00000003/sig000002eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d9 ), + .Q(\blk00000003/sig000002ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d8 ), + .Q(\blk00000003/sig000002ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d7 ), + .Q(\blk00000003/sig000002ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d6 ), + .Q(\blk00000003/sig000002ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d5 ), + .Q(\blk00000003/sig000002f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d4 ), + .Q(\blk00000003/sig000002f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d3 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d2 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d1 ), + .Q(\blk00000003/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009d0 ), + .Q(\blk00000003/sig000004dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cf ), + .Q(\blk00000003/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ce ), + .Q(\blk00000003/sig000004de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cd ), + .Q(\blk00000003/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cc ), + .Q(\blk00000003/sig000004e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009cb ), + .Q(\blk00000003/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009ca ), + .Q(\blk00000003/sig000004e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c9 ), + .Q(\blk00000003/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c8 ), + .Q(\blk00000003/sig000004e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c7 ), + .Q(\blk00000003/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c6 ), + .Q(\blk00000003/sig000004e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c5 ), + .Q(\blk00000003/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c4 ), + .Q(\blk00000003/sig000004e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c3 ), + .Q(\blk00000003/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c2 ), + .Q(\blk00000003/sig000004ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c1 ), + .Q(\blk00000003/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002b1/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002b1/sig000009c0 ), + .Q(\blk00000003/sig000004ec ) + ); + GND \blk00000003/blk000002b1/blk000002b2 ( + .G(\blk00000003/blk000002b1/sig000009bf ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000002ea/blk00000310 ( + .I0(ce), + .I1(\blk00000003/sig0000042a ), + .O(\blk00000003/blk000002ea/sig00000a27 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030f ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004db ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a26 ) + ); + RAM32X1D #( + .INIT ( 32'h000000D5 )) + \blk00000003/blk000002ea/blk0000030e ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dc ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a25 ) + ); + RAM32X1D #( + .INIT ( 32'h00000055 )) + \blk00000003/blk000002ea/blk0000030d ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004dd ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a24 ) + ); + RAM32X1D #( + .INIT ( 32'h00000095 )) + \blk00000003/blk000002ea/blk0000030c ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004de ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a23 ) + ); + RAM32X1D #( + .INIT ( 32'h00000025 )) + \blk00000003/blk000002ea/blk0000030b ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004df ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a22 ) + ); + RAM32X1D #( + .INIT ( 32'h00000079 )) + \blk00000003/blk000002ea/blk0000030a ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e0 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk0000030a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a21 ) + ); + RAM32X1D #( + .INIT ( 32'h000000FB )) + \blk00000003/blk000002ea/blk00000309 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e2 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000309_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1f ) + ); + RAM32X1D #( + .INIT ( 32'h00000056 )) + \blk00000003/blk000002ea/blk00000308 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e3 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000308_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1e ) + ); + RAM32X1D #( + .INIT ( 32'h0000002E )) + \blk00000003/blk000002ea/blk00000307 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e1 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000307_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a20 ) + ); + RAM32X1D #( + .INIT ( 32'h00000015 )) + \blk00000003/blk000002ea/blk00000306 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e4 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000306_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1d ) + ); + RAM32X1D #( + .INIT ( 32'h000000B2 )) + \blk00000003/blk000002ea/blk00000305 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e5 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000305_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1c ) + ); + RAM32X1D #( + .INIT ( 32'h0000009F )) + \blk00000003/blk000002ea/blk00000304 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e6 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000304_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1b ) + ); + RAM32X1D #( + .INIT ( 32'h000000CE )) + \blk00000003/blk000002ea/blk00000303 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e7 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000303_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a1a ) + ); + RAM32X1D #( + .INIT ( 32'h000000C4 )) + \blk00000003/blk000002ea/blk00000302 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e8 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000302_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a19 ) + ); + RAM32X1D #( + .INIT ( 32'h00000094 )) + \blk00000003/blk000002ea/blk00000301 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004e9 ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000301_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a18 ) + ); + RAM32X1D #( + .INIT ( 32'h00000024 )) + \blk00000003/blk000002ea/blk00000300 ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004eb ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk00000300_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a16 ) + ); + RAM32X1D #( + .INIT ( 32'h00000047 )) + \blk00000003/blk000002ea/blk000002ff ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ec ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002ff_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a15 ) + ); + RAM32X1D #( + .INIT ( 32'h000000E6 )) + \blk00000003/blk000002ea/blk000002fe ( + .A0(\blk00000003/sig00000426 ), + .A1(\blk00000003/sig00000427 ), + .A2(\blk00000003/sig00000428 ), + .A3(\blk00000003/sig00000429 ), + .A4(\blk00000003/blk000002ea/sig00000a14 ), + .D(\blk00000003/sig000004ea ), + .DPRA0(\blk00000003/sig00000433 ), + .DPRA1(\blk00000003/sig00000432 ), + .DPRA2(\blk00000003/sig00000431 ), + .DPRA3(\blk00000003/sig00000430 ), + .DPRA4(\blk00000003/blk000002ea/sig00000a14 ), + .WCLK(clk), + .WE(\blk00000003/blk000002ea/sig00000a27 ), + .SPO(\NLW_blk00000003/blk000002ea/blk000002fe_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk000002ea/sig00000a17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a26 ), + .Q(\blk00000003/sig000003b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a25 ), + .Q(\blk00000003/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a24 ), + .Q(\blk00000003/sig000003b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a23 ), + .Q(\blk00000003/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a22 ), + .Q(\blk00000003/sig000003b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a21 ), + .Q(\blk00000003/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a20 ), + .Q(\blk00000003/sig000003ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1f ), + .Q(\blk00000003/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1e ), + .Q(\blk00000003/sig000003bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1d ), + .Q(\blk00000003/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1c ), + .Q(\blk00000003/sig000003be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1b ), + .Q(\blk00000003/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a1a ), + .Q(\blk00000003/sig000003c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a19 ), + .Q(\blk00000003/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a18 ), + .Q(\blk00000003/sig000003c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a17 ), + .Q(\blk00000003/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a16 ), + .Q(\blk00000003/sig000003c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk000002ea/sig00000a15 ), + .Q(\blk00000003/sig000003c5 ) + ); + GND \blk00000003/blk000002ea/blk000002eb ( + .G(\blk00000003/blk000002ea/sig00000a14 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000371/blk00000397 ( + .I0(ce), + .I1(\blk00000003/sig00000232 ), + .O(\blk00000003/blk00000371/sig00000a64 ) + ); + RAM32X1D #( + .INIT ( 32'h00000000 )) + \blk00000003/blk00000371/blk00000396 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004c9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000396_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a63 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000395 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ca ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000395_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a62 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000394 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cb ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000394_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a61 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000393 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cc ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000393_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a60 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000392 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cd ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000392_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5f ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000391 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004ce ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000391_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5e ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000390 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d0 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000390_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5c ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038f ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d1 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038f_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5b ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038e ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004cf ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038e_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5d ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038d ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d2 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038d_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a5a ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038c ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d3 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038c_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a59 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038b ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d4 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038b_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a58 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk0000038a ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d5 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk0000038a_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a57 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000389 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d6 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000389_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a56 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000388 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d7 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000388_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a55 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000387 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d9 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000387_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a53 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000386 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004da ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000386_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a52 ) + ); + RAM32X1D #( + .INIT ( 32'h00000001 )) + \blk00000003/blk00000371/blk00000385 ( + .A0(\blk00000003/sig00000239 ), + .A1(\blk00000003/blk00000371/sig00000a51 ), + .A2(\blk00000003/blk00000371/sig00000a51 ), + .A3(\blk00000003/blk00000371/sig00000a51 ), + .A4(\blk00000003/blk00000371/sig00000a51 ), + .D(\blk00000003/sig000004d8 ), + .DPRA0(\blk00000003/sig000001d0 ), + .DPRA1(\blk00000003/blk00000371/sig00000a51 ), + .DPRA2(\blk00000003/blk00000371/sig00000a51 ), + .DPRA3(\blk00000003/blk00000371/sig00000a51 ), + .DPRA4(\blk00000003/blk00000371/sig00000a51 ), + .WCLK(clk), + .WE(\blk00000003/blk00000371/sig00000a64 ), + .SPO(\NLW_blk00000003/blk00000371/blk00000385_SPO_UNCONNECTED ), + .DPO(\blk00000003/blk00000371/sig00000a54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000384 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a63 ), + .Q(\blk00000003/sig000000f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000383 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a62 ), + .Q(\blk00000003/sig000000f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000382 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a61 ), + .Q(\blk00000003/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000381 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a60 ), + .Q(\blk00000003/sig000000f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000380 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5f ), + .Q(\blk00000003/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5e ), + .Q(\blk00000003/sig000000f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5d ), + .Q(\blk00000003/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5c ), + .Q(\blk00000003/sig000000f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5b ), + .Q(\blk00000003/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a5a ), + .Q(\blk00000003/sig000000fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk0000037a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a59 ), + .Q(\blk00000003/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000379 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a58 ), + .Q(\blk00000003/sig000000fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000378 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a57 ), + .Q(\blk00000003/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000377 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a56 ), + .Q(\blk00000003/sig000000ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000376 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a55 ), + .Q(\blk00000003/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000375 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a54 ), + .Q(\blk00000003/sig00000101 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000374 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a53 ), + .Q(\blk00000003/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000371/blk00000373 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000371/sig00000a52 ), + .Q(\blk00000003/sig00000103 ) + ); + GND \blk00000003/blk00000371/blk00000372 ( + .G(\blk00000003/blk00000371/sig00000a51 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.veo b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.veo new file mode 100644 index 000000000..41d2ac4ee --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.veo @@ -0,0 +1,79 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ + +// Generated from component ID: xilinx.com:ip:fir_compiler:5.0 + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +hbdec3 YourInstanceName ( + .sclr(sclr), // input sclr + .clk(clk), // input clk + .ce(ce), // input ce + .nd(nd), // input nd + .coef_ld(coef_ld), // input coef_ld + .coef_we(coef_we), // input coef_we + .coef_din(coef_din), // input [17 : 0] coef_din + .rfd(rfd), // output rfd + .rdy(rdy), // output rdy + .data_valid(data_valid), // output data_valid + .din_1(din_1), // input [23 : 0] din_1 + .din_2(din_2), // input [23 : 0] din_2 + .dout_1(dout_1), // output [47 : 0] dout_1 + .dout_2(dout_2)); // output [47 : 0] dout_2 + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file hbdec3.v when simulating +// the core, hbdec3. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xco b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xco new file mode 100644 index 000000000..86db05cdd --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3.xco @@ -0,0 +1,102 @@ +############################################################## +# +# Xilinx Core Generator version 14.4 +# Date: Wed Dec 4 21:31:43 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fir_compiler:5.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc7k325t +SET devicefamily = kintex7 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ffg900 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT FIR_Compiler family Xilinx,_Inc. 5.0 +# END Select +# BEGIN Parameters +CSET allow_rounding_approximation=false +CSET bestprecision=false +CSET chan_in_adv=0 +CSET clock_frequency=200 +CSET coefficient_buffer_type=Automatic +CSET coefficient_file=./hb63.coe +CSET coefficient_fractional_bits=0 +CSET coefficient_reload=true +CSET coefficient_sets=1 +CSET coefficient_sign=Signed +CSET coefficient_structure=Half_Band +CSET coefficient_width=18 +CSET coefficientsource=COE_File +CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6 +CSET columnconfig=3 +CSET component_name=hbdec3 +CSET data_buffer_type=Automatic +CSET data_fractional_bits=0 +CSET data_sign=Signed +CSET data_width=24 +CSET decimation_rate=2 +CSET displayreloadorder=false +CSET filter_architecture=Systolic_Multiply_Accumulate +CSET filter_selection=1 +CSET filter_type=Decimation +CSET gui_behaviour=Coregen +CSET hardwareoversamplingrate=1 +CSET has_ce=true +CSET has_data_valid=true +CSET has_nd=true +CSET has_sclr=true +CSET input_buffer_type=Automatic +CSET inter_column_pipe_length=4 +CSET interpolation_rate=1 +CSET multi_column_support=Disabled +CSET number_channels=1 +CSET number_paths=2 +CSET optimization_goal=Area +CSET output_buffer_type=Automatic +CSET output_rounding_mode=Full_Precision +CSET output_width=48 +CSET passband_max=0.5 +CSET passband_min=0.0 +CSET preference_for_other_storage=Automatic +CSET quantization=Integer_Coefficients +CSET rate_change_type=Integer +CSET ratespecification=Frequency_Specification +CSET registered_output=true +CSET sample_frequency=50 +CSET sampleperiod=1 +CSET sclr_deterministic=true +CSET stopband_max=1.0 +CSET stopband_min=0.5 +CSET usechan_in_adv=false +CSET zero_pack_factor=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-12-18T05:23:34Z +# END Extra information +GENERATE +# CRC: 86e0fdc7 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_0.mif new file mode 100644 index 000000000..35823f684 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_0.mif @@ -0,0 +1,17 @@ +111111111111011101 +000000000001011111 +111111111100111101 +000000000101100000 +111111110110111010 +000000001110001011 +111111101010110110 +000000011110100001 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_1.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_1.mif new file mode 100644 index 000000000..a8b11a750 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto0_1.mif @@ -0,0 +1,17 @@ +111111010101000001 +000000111011100101 +111110101101111111 +000001110001100000 +111101011111001000 +000011110010000110 +111001011000110101 +010100010011111100 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto_HALFBAND_CENTRE0.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto_HALFBAND_CENTRE0.mif new file mode 100644 index 000000000..ca072e0fc --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3COEFF_auto_HALFBAND_CENTRE0.mif @@ -0,0 +1,3 @@ +011111111111111111 +000000000000000000 +000000000000000000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3_flist.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_flist.txt new file mode 100644 index 000000000..99e5ce3e9 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_flist.txt @@ -0,0 +1,18 @@ +# Output products list for +hbdec3.asy +hbdec3.gise +hbdec3.mif +hbdec3.ngc +hbdec3.v +hbdec3.veo +hbdec3.xco +hbdec3.xise +hbdec3COEFF_auto0_0.mif +hbdec3COEFF_auto0_1.mif +hbdec3COEFF_auto_HALFBAND_CENTRE0.mif +hbdec3_flist.txt +hbdec3_readme.txt +hbdec3_reload_addrfilt_decode_rom.mif +hbdec3_reload_order.txt +hbdec3_xmdf.tcl +hbdec3filt_decode_rom.mif diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3_readme.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_readme.txt new file mode 100644 index 000000000..9b6db7222 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_readme.txt @@ -0,0 +1,63 @@ +The following files were generated for 'hbdec3' in directory +/home/matt/fpgadev/usrp3/top/b250/coregen_dsp/ + +Opens the IP Customization GUI: + Allows the user to customize or recustomize the IP instance. + + * hbdec3.mif + * hbdec3_reload_order.txt + +XCO file generator: + Generate an XCO file for compatibility with legacy flows. + + * hbdec3.xco + +Creates an implementation netlist: + Creates an implementation netlist for the IP. + + * hbdec3.ngc + * hbdec3.v + * hbdec3.veo + * hbdec3COEFF_auto0_0.mif + * hbdec3COEFF_auto0_1.mif + * hbdec3COEFF_auto_HALFBAND_CENTRE0.mif + * hbdec3_reload_addrfilt_decode_rom.mif + * hbdec3filt_decode_rom.mif + +Creates an HDL instantiation template: + Creates an HDL instantiation template for the IP. + + * hbdec3.veo + +IP Symbol Generator: + Generate an IP symbol based on the current project options'. + + * hbdec3.asy + * hbdec3.mif + * hbdec3_reload_order.txt + +Generate ISE metadata: + Create a metadata file for use when including this core in ISE designs + + * hbdec3_xmdf.tcl + +Generate ISE subproject: + Create an ISE subproject for use when including this core in ISE designs + + * hbdec3.gise + * hbdec3.xise + +Deliver Readme: + Readme file for the IP. + + * hbdec3_readme.txt + +Generate FLIST file: + Text file listing all of the output files produced when a customized core was + generated in the CORE Generator. + + * hbdec3_flist.txt + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_addrfilt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_addrfilt_decode_rom.mif new file mode 100644 index 000000000..d0fb6f12b --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_addrfilt_decode_rom.mif @@ -0,0 +1,17 @@ +0000 +1000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_order.txt b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_order.txt new file mode 100644 index 000000000..cf70f3816 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_reload_order.txt @@ -0,0 +1,33 @@ +Reload index 0 = Index 16 +Reload index 1 = Index 18 +Reload index 2 = Index 20 +Reload index 3 = Index 22 +Reload index 4 = Index 24 +Reload index 5 = Index 26 +Reload index 6 = Index 28 +Reload index 7 = Index 30 +Reload index 8 = Index 0 +Reload index 9 = Index 2 +Reload index 10 = Index 4 +Reload index 11 = Index 6 +Reload index 12 = Index 8 +Reload index 13 = Index 10 +Reload index 14 = Index 12 +Reload index 15 = Index 14 +Reload index 16 = Index 31 +Reload index 17 = Index 0 +Reload index 18 = Index 0 +Reload index 19 = Index 0 +Reload index 20 = Index 0 +Reload index 21 = Index 0 +Reload index 22 = Index 0 +Reload index 23 = Index 0 +Reload index 24 = Index 0 +Reload index 25 = Index 0 +Reload index 26 = Index 0 +Reload index 27 = Index 0 +Reload index 28 = Index 0 +Reload index 29 = Index 0 +Reload index 30 = Index 0 +Reload index 31 = Index 0 + diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3_xmdf.tcl b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_xmdf.tcl new file mode 100644 index 000000000..dfb3fd075 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3_xmdf.tcl @@ -0,0 +1,95 @@ +# The package naming convention is _xmdf +package provide hbdec3_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::hbdec3_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::hbdec3_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name hbdec3 +} +# ::hbdec3_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::hbdec3_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto0_1.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3COEFF_auto_HALFBAND_CENTRE0.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_addrfilt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_reload_order.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path hbdec3filt_decode_rom.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module hbdec3 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/usrp3/top/x300/coregen_dsp/hbdec3filt_decode_rom.mif b/fpga/usrp3/top/x300/coregen_dsp/hbdec3filt_decode_rom.mif new file mode 100644 index 000000000..d0fb6f12b --- /dev/null +++ b/fpga/usrp3/top/x300/coregen_dsp/hbdec3filt_decode_rom.mif @@ -0,0 +1,17 @@ +0000 +1000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 diff --git a/fpga/usrp3/top/x300/dev_config.json b/fpga/usrp3/top/x300/dev_config.json new file mode 100644 index 000000000..eb6ce9dc0 --- /dev/null +++ b/fpga/usrp3/top/x300/dev_config.json @@ -0,0 +1,3 @@ +{ + "warning": { "ignore": ["."]} +} diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v new file mode 100644 index 000000000..5773b296c --- /dev/null +++ b/fpga/usrp3/top/x300/gen_ddrlvds.v @@ -0,0 +1,106 @@ + + +module gen_ddrlvds + ( + // 1X Radio Clock + input tx_clk_1x, + // 2X Radio clock + input tx_clk_2x, + // Clk to drive DCI ODDR. This is a phase shifted version of + // tx_clk_2x. The phase shift is to center the DCI edge in the + // valid window of the data in the DAC. + input tx_dci_clk, + // Reset signal synchronous to radio clock + input reset, + // Source synchronous differential clocks to DAC + output tx_clk_2x_p, + output tx_clk_2x_n, + // Differential frame sync to DAC + output tx_frame_p, + output tx_frame_n, + // Differential byte wide data to DAC. + // Alternates I[15:8],I[7:0],Q[15:8],Q[7:0] + output [7:0] tx_d_p, + output [7:0] tx_d_n, + // Input data + input [15:0] i, + input [15:0] q, + // Rising edge sampled on sync_dacs triggers frame sync sequence + input sync_dacs + ); + + reg [15:0] i_reg, q_reg; + reg [15:0] i_2x, q_2x; + reg rising_edge; + wire [15:0] i_and_q_2x; + reg sync_2x; + + genvar z; + wire [7:0] tx_int; + wire tx_clk_2x_int; + wire tx_frame_int; + + // Keep constraint to ensure these signals are not resource shared which can cause timing failures + (* keep = "true" *) reg phase, phase_2x, sync_dacs_reg; + + wire phase_eq_phase2x = (phase == phase_2x); + + always @(posedge tx_clk_1x) + if (reset) + phase <= 1'b0; + else + phase <= ~phase; + + + // + // Pipeline input data so that 1x to 2x clock domain jump includes no logic external to this module. + // + always @(posedge tx_clk_1x) + begin + i_reg <= i; + q_reg <= q; + sync_dacs_reg <= sync_dacs; + end + + always @(posedge tx_clk_2x) + begin + // Move 1x data to 2x domain, mostly just to add pipeline regs + // for timing closure. + i_2x <= i_reg; + q_2x <= q_reg; + // Sample phase to determine when 1x clock edges occur. + // To sync multiple AD9146 DAC's an extended assertion of FRAME is required, + // when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME, + // also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for. + sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */; + rising_edge <= (phase_eq_phase2x && ~sync_2x); + phase_2x <= phase; + end + + // Interleave I and Q as SDR signals + assign i_and_q_2x = rising_edge ? q_2x : i_2x; + + generate + for(z = 0; z < 8; z = z + 1) + begin : gen_pins + OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z])); + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr + (.Q(tx_int[z]), .C(tx_clk_2x), + .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0)); + end + endgenerate + + // Generate framing signal to identify I and Q + OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n)); + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame + (.Q(tx_frame_int), .C(tx_clk_2x), + .CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0)); + + // Source synchronous clk + OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n)); + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk + (.Q(tx_clk_2x_int), .C(tx_dci_clk), + .CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0)); + +endmodule // gen_ddrlvds + diff --git a/fpga/usrp3/top/x300/ip/Makefile.inc b/fpga/usrp3/top/x300/ip/Makefile.inc new file mode 100644 index 000000000..2b53823e4 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/Makefile.inc @@ -0,0 +1,81 @@ +# +# Copyright 2014 Ettus Research +# + +include $(IP_DIR)/axi4_dualport_sram/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi64_8k_2clk_fifo/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc +include $(IP_DIR)/bootram/Makefile.inc +include $(IP_DIR)/bus_clk_gen/Makefile.inc +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/input_sample_fifo/Makefile.inc +include $(IP_DIR)/one_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/pcie_clk_gen/Makefile.inc +include $(IP_DIR)/radio_clk_gen/Makefile.inc +include $(IP_DIR)/ten_gig_eth_pcs_pma/Makefile.inc +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc + +IP_XCI_SRCS = \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_AXI64_8K_2CLK_FIFO_SRCS) \ +$(IP_BOOTRAM_SRCS) \ +$(IP_BUS_CLK_GEN_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_PCIE_CLK_GEN_SRCS) \ +$(IP_RADIO_CLK_GEN_SRCS) +# $(IP_AXI4_BRAM_SRCS) \ + +BD_SRCS = \ +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) + +IP_ONE_GIGE_PHY_XCI_SRCS = \ +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) \ + +IP_TEN_GIGE_PHY_XCI_SRCS = \ +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) + +IP_AURORA_XCI_SRCS = \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) + +IP_DRAM_XCI_SRCS = \ +$(IP_DDR3_32BIT_SRCS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_SRCS) \ +# $(IP_AXI_INTERCON_4X64_128_SRCS) \ +# $(IP_AXI_INTERCON_2X64_128_SRCS) \ + +IP_CODEGEN_SRCS = \ +$(ONE_GIGE_PHY_SRCS) \ +$(TEN_GIGE_PHY_SRCS) + +IP_SYNTH_OUTPUTS = \ +$(IP_AXI64_4K_2CLK_FIFO_OUTS) \ +$(IP_AXI64_8K_2CLK_FIFO_OUTS) \ +$(IP_BOOTRAM_OUTS) \ +$(IP_BUS_CLK_GEN_OUTS) \ +$(IP_FIFO_4K_2CLK_OUTS) \ +$(IP_FIFO_SHORT_2CLK_OUTS) \ +$(IP_ONE_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_PCIE_CLK_GEN_OUTS) \ +$(IP_RADIO_CLK_GEN_OUTS) \ +$(IP_TEN_GIG_ETH_PCS_PMA_OUTS) \ +$(IP_AURORA_64B66B_PCS_PMA_OUTS) +# $(IP_AXI4_BRAM_OUTS) \ + +BD_OUTPUTS = \ +$(IP_AXI_INTERCON_2X64_128_BD_OUTS) + +# Currently unused +# $(IP_INPUT_SAMPLE_FIFO_OUTS) \ +# $(IP_AXI_INTERCON_4X64_128_OUTS) \ +# $(IP_AXI_INTERCON_2X64_128_OUTS) \ + +ip: $(IP_SYNTH_OUTPUTS) $(IP_CODEGEN_SRCS) $(BD_OUTPUTS) + +.PHONY: ip + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc new file mode 100644 index 000000000..49e58dbc0 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc @@ -0,0 +1,34 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma_ex/, \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_clock_module.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_gt_common_wrapper.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support_reset_logic.v \ +aurora_64b66b_pcs_pma_ex.srcs/shared_logic/aurora_64b66b_pcs_pma_support.v \ +imports/aurora_64b66b_pcs_pma_cdc_sync_exdes.v \ +imports/aurora_64b66b_pcs_pma_example_axi_to_ll.v \ +imports/aurora_64b66b_pcs_pma_example_ll_to_axi.v \ +imports/aurora_64b66b_pcs_pma_exdes.v \ +imports/aurora_64b66b_pcs_pma_exdes.xdc \ +imports/aurora_64b66b_pcs_pma_frame_check.v \ +imports/aurora_64b66b_pcs_pma_frame_gen.v \ +) + +AURORA_PHY_SRCS = \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_x1.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v \ +$(IP_DIR)/aurora_64b66b_pcs_pma/aurora_axis_mac.v \ +$(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS) + +IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + +IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \ +aurora_64b66b_pcs_pma.xci.out \ +) + +$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci + $(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci new file mode 100644 index 000000000..0bfdcb8b0 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci @@ -0,0 +1,1780 @@ + + + xilinx.com + xci + unknown + 1.0 + + + aurora_64b66b_pcs_pma + + + 32 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + 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false + GTXQ0 + None + None + None + None + 1 + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + X + gtx + 78.125 + 10.3125 + LCPLL + none + none + none + none + 156.250 + 156.250 + 156.250 + none + X0Y0 + X0Y0 + right + false + true + false + 1 + aurora_64b66b_pcs_pma + 78.125 + 20 + AC + AUTO + 0 + PROGRAMMABLE + 800 + false + false + 0 + false + false + Duplex + AXI4_LITE + None + Streaming + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 0 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v new file mode 100644 index 000000000..1ee89c030 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v @@ -0,0 +1,329 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_axis_mac #( + parameter PHY_ENDIANNESS = "LITTLE", //{"LITTLE, "BIG"} + parameter PACKET_MODE = 0, + parameter MAX_PACKET_SIZE = 512, + parameter BIST_ENABLED = 1 +) ( + // Clocks and resets + input phy_clk, + input phy_rst, + input sys_clk, + input sys_rst, + input clear, + // PHY TX Interface (Synchronous to phy_clk) + output [63:0] phy_m_axis_tdata, + output phy_m_axis_tvalid, + input phy_m_axis_tready, + // PHY RX Interface (Synchronous to phy_clk) + input [63:0] phy_s_axis_tdata, + input phy_s_axis_tvalid, + // User TX Interface (Synchronous to sys_clk) + input [63:0] s_axis_tdata, + input s_axis_tlast, + input s_axis_tvalid, + output s_axis_tready, + // User RX Interface (Synchronous to sys_clk) + output [63:0] m_axis_tdata, + output m_axis_tlast, + output m_axis_tvalid, + input m_axis_tready, + // PHY Status Inputs (Synchronous to phy_clk) + input channel_up, + input hard_err, + input soft_err, + // Status and Error Outputs (Synchronous to sys_clk) + output [31:0] overruns, + output [31:0] soft_errors, + output reg [31:0] checksum_errors, + output critical_err, + // BIST Interface (Synchronous to sys_clk) + input bist_gen_en, + input [5:0] bist_gen_rate, + input bist_checker_en, + input bist_loopback_en, + output reg bist_checker_locked, + output reg [47:0] bist_checker_samps, + output reg [47:0] bist_checker_errors +); + + // ---------------------------------------------- + // Resets, Clears, Clock crossings + // ---------------------------------------------- + + wire phy_s_axis_tready; // Internal only. The PHY has no backpressure signal. + + // Stay idle if the PHY is not up or if it experiences a fatal error + wire clear_sysclk, clear_phyclk; + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i ( + .clk(phy_clk), .rst(1'b0 /* no reset */), .in((~channel_up) | hard_err | clear), .out(clear_phyclk)); + synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i ( + .clk(sys_clk), .rst(1'b0 /* no reset */), .in(clear_phyclk), .out(clear_sysclk)); + + // ---------------------------------------------- + // Counters + // ---------------------------------------------- + + reg [31:0] overruns_reg; + reg [31:0] soft_errors_reg; + + // Counter for recoverable errors. For reporting only. + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + soft_errors_reg <= 32'd0; + else if (soft_err) + soft_errors_reg <= soft_errors_reg + 32'd1; + + // Tag an overrun if the FIFO is full. Samples will get dropped + always @(posedge phy_clk) + if (phy_rst | clear_phyclk) + overruns_reg <= 32'd0; + else if (phy_s_axis_tvalid & ~phy_s_axis_tready) + overruns_reg <= overruns_reg + 32'd1; + + wire [7:0] dummy0; + fifo_short_2clk status_counters_2clk_i ( + .rst(phy_rst), + .wr_clk(phy_clk), .din({8'h00, soft_errors_reg, overruns_reg}), .wr_en(1'b1), .full(), .wr_data_count(), + .rd_clk(sys_clk), .dout({dummy0, soft_errors, overruns}), .rd_en(1'b1), .empty(), .rd_data_count() + ); + + // ---------------------------------------------- + // BIST Wires + // ---------------------------------------------- + + wire [63:0] bist_o_tdata; + wire bist_o_tvalid, bist_o_tready; + wire [63:0] bist_i_tdata; + wire bist_i_tvalid, bist_i_tready; + wire [63:0] loopback_tdata; + wire loopback_tvalid, loopback_tready; + reg bist_gen_en_reg = 1'b0, bist_checker_en_reg = 1'b0, bist_loopback_en_reg = 1'b0; + reg [5:0] bist_gen_rate_reg = 'd0; + + generate if (BIST_ENABLED == 1) begin + // Pipeline control signals + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) begin + bist_gen_en_reg <= 1'b0; + bist_checker_en_reg <= 1'b0; + bist_loopback_en_reg <= 1'b0; + bist_gen_rate_reg <= 'd0; + end else begin + bist_gen_en_reg <= bist_gen_en; + bist_checker_en_reg <= bist_checker_en; + bist_loopback_en_reg <= bist_loopback_en; + bist_gen_rate_reg <= bist_gen_rate; + end + end + end endgenerate + // ---------------------------------------------- + // RX Data Path + // ---------------------------------------------- + + wire [63:0] i_raw_tdata; + wire i_raw_tvalid, i_raw_tready; + + wire [63:0] i_pip_tdata; + wire i_pip_tvalid, i_pip_tready; + + wire [63:0] i_pkt_tdata; + wire i_pkt_tlast, i_pkt_tvalid, i_pkt_tready; + + wire [63:0] i_gt_tdata; + wire i_gt_tlast, i_gt_tvalid, i_gt_tready; + + wire checksum_err; + + wire [63:0] phy_s_axis_tdata_endian, phy_m_axis_tdata_endian; + + generate if (PHY_ENDIANNESS == "BIG") begin + assign phy_s_axis_tdata_endian = { + phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24], + phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56] + }; + assign phy_m_axis_tdata = { + phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24], + phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56] + }; + end else begin + assign phy_s_axis_tdata_endian = phy_s_axis_tdata; + assign phy_m_axis_tdata = phy_m_axis_tdata_endian; + end endgenerate + + // Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx. + axi64_4k_2clk_fifo ingress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(phy_clk), + .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(), + .m_aclk(sys_clk), + .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count() + ); + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready), + .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid), + .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)), + .space(), .occupied() + ); + + assign bist_i_tdata = i_pip_tdata; + assign bist_i_tvalid = i_pip_tvalid & bist_checker_en_reg; + + assign loopback_tdata = i_pip_tdata; + assign loopback_tvalid = i_pip_tvalid & bist_loopback_en_reg; + + axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready), + .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready), + .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err) + ); + + axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready), + .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), + .space(), .occupied() + ); + + always @(posedge sys_clk) + if (sys_rst | clear_sysclk) + checksum_errors <= 32'd0; + else if (checksum_err) + checksum_errors <= checksum_errors + 32'd1; + + // ---------------------------------------------- + // TX Data Path + // ---------------------------------------------- + + wire [63:0] o_pkt_tdata; + wire o_pkt_tlast, o_pkt_tvalid, o_pkt_tready; + + wire [63:0] o_pip_tdata; + wire o_pip_tvalid, o_pip_tready; + + wire [63:0] o_raw_tdata; + wire o_raw_tvalid, o_raw_tready; + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready), + .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready), + .space(), .occupied() + ); + + // Insert preamble and EOP + axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready), + .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg) + ); + + // AXI-Flop to ease timing + axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 ( + .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk), + .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)), + .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)), + .i_tready(o_pip_tready), + .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready), + .space(), .occupied() + ); + + assign bist_o_tready = o_pip_tready; + assign loopback_tready = o_pip_tready; + + // Egress FIFO + axi64_4k_2clk_fifo egress_fifo_i ( + .s_aresetn(~phy_rst), .s_aclk(sys_clk), + .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0), + .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(), + .m_aclk(phy_clk), + .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(), + .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count() + ); + + // ------------------------------------------------- + // BIST: Generator and checker for a LFSR polynomial + // ------------------------------------------------- + localparam LFSR_LEN = 32; + localparam LFSR_SEED = {LFSR_LEN{1'b1}}; + + function [LFSR_LEN-1:0] compute_lfsr_next; + input [LFSR_LEN-1:0] current; + // Maximal length polynomial: x^32 + x^22 + x^2 + x^1 + 1 + compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]}; + endfunction + + function [63:0] lfsr_to_axis; + input [LFSR_LEN-1:0] lfsr; + lfsr_to_axis = {~lfsr, lfsr}; + endfunction + + function [LFSR_LEN-1:0] axis_to_lfsr; + input [63:0] axis; + axis_to_lfsr = axis[LFSR_LEN-1:0]; + endfunction + + generate if (BIST_ENABLED == 1) begin + // Throttle outgoing LFSR to based on the specified rate + // BIST Throughput = sys_clk BW * (bist_gen_rate+1)/64 + reg [5:0] throttle_cnt; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk) + throttle_cnt <= 6'd0; + else if (bist_gen_en_reg) + throttle_cnt <= throttle_cnt + 6'd1; + end + // NOTE: This techinically violates AXIS spec (valid revocation) + assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg); + + // Unsynchronized LFSR generator (for BIST output) + reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_gen_en_reg) + lfsr_gen <= LFSR_SEED; + else if (bist_o_tready & bist_o_tvalid) + lfsr_gen <= compute_lfsr_next(lfsr_gen); + end + assign bist_o_tdata = lfsr_to_axis(lfsr_gen); + + // Synchronized LFSR checker (for BIST input) + wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);; + always @(posedge sys_clk) begin + if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin + bist_checker_locked <= 1'b0; + lfsr_check <= LFSR_SEED; + end else if (bist_i_tvalid && bist_i_tready) begin + lfsr_check <= axis_to_lfsr(bist_i_tdata); + if (bist_i_tdata == lfsr_to_axis(LFSR_SEED)) + bist_checker_locked <= 1'b1; + end + end + + // LFSR checker + always @(posedge sys_clk) begin + if (bist_checker_locked) begin + if (bist_i_tvalid & bist_i_tready) begin + bist_checker_samps <= bist_checker_samps + 48'd1; + if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin + bist_checker_errors <= bist_checker_errors + 48'd1; + end + end + end else begin + bist_checker_samps <= 48'd0; + bist_checker_errors <= 48'd0; + end + end + assign bist_i_tready = 1'b1; + end endgenerate + +endmodule + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v new file mode 100644 index 000000000..9e994aefe --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_clk_gen.v @@ -0,0 +1,51 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_clk_gen +( + input areset, + input refclk_p, + input refclk_n, + + output refclk, + output clk156, + output init_clk +); + + wire clk156_buf; + wire init_clk_buf; + wire clkfbout; + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG clk156_bufg_inst ( + .I (refclk), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (init_clk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (init_clk_buf), + .O (init_clk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v new file mode 100644 index 000000000..c3fc89749 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_phy_x1.v @@ -0,0 +1,370 @@ +// +// Copyright 2016 Ettus Research LLC +// + +module aurora_phy_x1 #( + parameter SIMULATION = 0 +)( + // Clocks and Resets + input areset, + input refclk, + input init_clk, + output user_clk, + output user_rst, + // GTX Serial I/O + input rx_p, + input rx_n, + output tx_p, + output tx_n, + // AXI4-Stream TX Interface + input [63:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + // AXI4-Stream RX Interface + output [63:0] m_axis_tdata, + output m_axis_tvalid, + // AXI4-Lite Config Interface + input [31:0] s_axi_awaddr, + input [31:0] s_axi_araddr, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + input s_axi_awvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output s_axi_awready, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + output [1:0] s_axi_rresp, + input s_axi_bready, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_arvalid, + input s_axi_wvalid, + // Status and Error Reporting Interface + output reg channel_up, + output reg hard_err, + output reg soft_err +); + + //-------------------------------------------------------------- + // Status and Error Signals + //-------------------------------------------------------------- + wire hard_err_i, soft_err_i, channel_up_i, lane_up_i; + always @(posedge user_clk) begin + hard_err <= hard_err_i; + soft_err <= soft_err_i; + channel_up <= channel_up_i && lane_up_i; + end + + //-------------------------------------------------------------- + // Reset and PMA Init Sequence + //-------------------------------------------------------------- + // Requirements from PG074: + // - It is expected that user_clock is stable when the reset_pb signal is applied. + // - During the board power-on sequence, both the pma_init and reset_pb signals are + // expected to be High. INIT_CLK and GT_REFCLK are expected to be stable during + // power-on for the proper functioning of the Aurora 64B/66B core. When both clocks are + // stable, pma_init is deasserted followed by the deassertion of reset_pb. + // - Normal Operation Reset Sequence: + // 1. Assert reset. Wait for a minimum time equal to 128*user_clk's time-period. + // 2. Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent + // the transmission of CC characters and ensure that the remote agent detects a hot plug event. + // 3. Deassert pma_init. + // 4. Deassert reset_pb. + + localparam PWRON_PMA_INIT_CYC = 32'd1024; + localparam SYSRST_ASSERT_CYC = 32'd128; + localparam PMA_INIT_ASSERT_CYC_LOG2 = (SIMULATION == 1) ? 4 : 26; + localparam SYSRST_DEASSERT_CYC = 32'd20; + + wire reset_iclk, pma_init, reset_pb; + wire gt_pll_lock, gt_pll_lock_iclk, mmcm_locked, mmcm_locked_iclk; + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b1) ) input_rst_sync_i ( + .clk(init_clk), .rst(1'b0), .in(areset), .out(reset_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) gt_pll_lock_sync_i ( + .clk(init_clk), .rst(1'b0), .in(gt_pll_lock), .out(gt_pll_lock_iclk) + ); + + synchronizer #( .STAGES(3), .INITIAL_VAL(1'b0) ) mmcm_locked_sync_i ( + .clk(init_clk), .rst(1'b0), .in(mmcm_locked), .out(mmcm_locked_iclk) + ); + + localparam [2:0] RST_ST_PWRON_PMA_INIT = 3'd0; + localparam [2:0] RST_ST_PWRON_PMA_SYSRST = 3'd1; + localparam [2:0] RST_ST_IDLE = 3'd2; + localparam [2:0] RST_ST_SYSRST_PRE = 3'd3; + localparam [2:0] RST_ST_PMA_INIT = 3'd4; + localparam [2:0] RST_ST_SYSRST_POST = 3'd5; + + reg [2:0] rst_state = RST_ST_PWRON_PMA_INIT; + reg [31:0] rst_counter = PWRON_PMA_INIT_CYC; + + always @(posedge init_clk) begin + case (rst_state) + RST_ST_PWRON_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PWRON_PMA_SYSRST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PWRON_PMA_SYSRST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_IDLE: begin + if (reset_iclk) begin + rst_state <= RST_ST_SYSRST_PRE; + rst_counter <= SYSRST_ASSERT_CYC; + end + end + RST_ST_SYSRST_PRE: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_PMA_INIT; + rst_counter <= {{(32-PMA_INIT_ASSERT_CYC_LOG2){1'b0}}, {PMA_INIT_ASSERT_CYC_LOG2{1'b1}}}; + end else if (mmcm_locked_iclk) begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_PMA_INIT: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_SYSRST_POST; + rst_counter <= SYSRST_DEASSERT_CYC; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + RST_ST_SYSRST_POST: begin + if (rst_counter == 32'd0) begin + rst_state <= RST_ST_IDLE; + end else begin + rst_counter <= rst_counter - 32'd1; + end + end + endcase + end + + assign reset_pb = (rst_state != RST_ST_IDLE); + assign pma_init = (rst_state == RST_ST_PMA_INIT || rst_state == RST_ST_PWRON_PMA_INIT); + + //-------------------------------------------------------------- + // Clocking + //-------------------------------------------------------------- + + wire tx_out_clk, tx_out_clk_bufg; + wire sync_clk_i; + wire user_clk_i; + wire mmcm_fb_clk; + wire sync_clk; + + localparam MULT = 10; + localparam DIVIDE = 5; + localparam CLK_PERIOD = 3.103; + localparam OUT0_DIVIDE = 4; + localparam OUT1_DIVIDE = 2; + localparam OUT2_DIVIDE = 6; + localparam OUT3_DIVIDE = 8; + + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (DIVIDE), + .CLKFBOUT_MULT_F (MULT), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLK_PERIOD), + .CLKOUT1_DIVIDE (OUT1_DIVIDE), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (OUT2_DIVIDE), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (OUT3_DIVIDE), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .REF_JITTER1 (0.010) + ) mmcm_adv_inst ( + .CLKFBOUT (mmcm_fb_clk), + .CLKFBOUTB (), + .CLKOUT0 (user_clk_i), + .CLKOUT0B (), + .CLKOUT1 (sync_clk_i), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_fb_clk), + .CLKIN1 (tx_out_clk_bufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (!gt_pll_lock) + ); + + // BUFG for the feedback clock. The feedback signal is phase aligned to the input + // and must come from the CLK0 or CLK2X output of the PLL. In this case, we use + // the CLK0 output. + BUFG txout_clock_net_i ( + .I(tx_out_clk), + .O(tx_out_clk_bufg) + ); + BUFG user_clk_net_i ( + .I(user_clk_i), + .O(user_clk) + ); + BUFG sync_clock_net_i ( + .I(sync_clk_i), + .O(sync_clk) + ); + + //-------------------------------------------------------------- + // GT Common + //-------------------------------------------------------------- + + wire gt_qpllclk_quad1_i; + wire gt_qpllrefclk_quad1_i; + wire gt_to_common_qpllreset_i; + wire gt_qpllrefclklost_i; + wire gt_qplllock_i; + + wire [7:0] qpll_drpaddr_in_i = 8'h0; + wire [15:0] qpll_drpdi_in_i = 16'h0; + wire qpll_drpen_in_i = 1'b0; + wire qpll_drpwe_in_i = 1'b0; + wire [15:0] qpll_drpdo_out_i; + wire qpll_drprdy_out_i; + + aurora_64b66b_pcs_pma_gt_common_wrapper gt_common_support ( + .gt_qpllclk_quad1_out (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_out (gt_qpllrefclk_quad1_i), + .GT0_GTREFCLK0_COMMON_IN (refclk), + //----------------------- Common Block - QPLL Ports ------------------------ + .GT0_QPLLLOCK_OUT (gt_qplllock_i), + .GT0_QPLLRESET_IN (gt_to_common_qpllreset_i), + .GT0_QPLLLOCKDETCLK_IN (init_clk), + .GT0_QPLLREFCLKLOST_OUT (gt_qpllrefclklost_i), + //---------------------- Common DRP Ports ---------------------- + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpclk_in (init_clk), + .qpll_drpdo_out (qpll_drpdo_out_i), + .qpll_drprdy_out (qpll_drprdy_out_i), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i) + ); + + //-------------------------------------------------------------- + // IP Instantiation + //-------------------------------------------------------------- + + wire gt_rxcdrovrden_i = 1'b0; + wire [2:0] loopback_i = 3'b000; + wire power_down_i = 1'b0; + + aurora_64b66b_pcs_pma aurora_64b66b_pcs_pma_i ( + .refclk1_in (refclk), + // TX AXI4-S Interface + .s_axi_tx_tdata (s_axis_tdata), + .s_axi_tx_tvalid (s_axis_tvalid), + .s_axi_tx_tready (s_axis_tready), + // RX AXI4-S Interface + .m_axi_rx_tdata (m_axis_tdata), + .m_axi_rx_tvalid (m_axis_tvalid), + // GTX Serial I/O + .rxp (rx_p), + .rxn (rx_n), + .txp (tx_p), + .txn (tx_n), + // Status and Error + .hard_err (hard_err_i), + .soft_err (soft_err_i), + .channel_up (channel_up_i), + .lane_up (lane_up_i), + // System Interface + .mmcm_not_locked (!mmcm_locked), + .user_clk (user_clk), + .sync_clk (sync_clk), + .reset_pb (reset_pb), + .gt_rxcdrovrden_in (gt_rxcdrovrden_i), + .power_down (power_down_i), + .loopback (loopback_i), + .pma_init (pma_init), + .gt_pll_lock (gt_pll_lock), + .drp_clk_in (init_clk), + .gt_qpllclk_quad1_in (gt_qpllclk_quad1_i), + .gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_i), + .gt_to_common_qpllreset_out(gt_to_common_qpllreset_i), + .gt_qplllock_in (gt_qplllock_i), + .gt_qpllrefclklost_in (gt_qpllrefclklost_i), + // AXI4-Lite config + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rdata (s_axi_rdata), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rready (s_axi_rready), + // GTXE2 COMMON DRP Ports + .qpll_drpaddr_in (qpll_drpaddr_in_i), + .qpll_drpdi_in (qpll_drpdi_in_i), + .qpll_drpdo_out (), + .qpll_drprdy_out (), + .qpll_drpen_in (qpll_drpen_in_i), + .qpll_drpwe_in (qpll_drpwe_in_i), + .init_clk (init_clk), + .link_reset_out (), + .sys_reset_out (user_rst), + .tx_out_clk (tx_out_clk) + ); + + endmodule diff --git a/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc new file mode 100644 index 000000000..8fe97ec5a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI4_BRAM_SRCS = $(IP_BUILD_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci + +IP_AXI4_BRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_dualport_sram/, \ +axi4_dualport_sram.xci.out \ +synth/axi4_dualport_sram.vhd \ +) + +$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS) : $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci + $(call BUILD_VIVADO_IP,axi4_dualport_sram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci new file mode 100644 index 000000000..f06d744aa --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci @@ -0,0 +1,314 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi4_dualport_sram + + + 4096 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + + 64 + 100000000 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 256 + 2 + 1 + 2 + 1 + 0.000 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 18 + 18 + 1 + 1 + 0 + 1 + 8 + 1 + 0 + 512 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 42.036212 mW + kintex7 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + axi4_dualport_sram.mem + no_coe_file_loaded + 1 + 0 + 1 + 0 + 1 + 262144 + 262144 + 1 + 1 + 64 + 64 + 0 + 0 + CE + CE + ALL + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 8 + 8 + 262144 + 262144 + READ_FIRST + READ_FIRST + 64 + 64 + kintex7 + 1 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 8 + NONE + no_coe_file_loaded + ALL + axi4_dualport_sram + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + AXI4 + false + no_Mem_file_loaded + Simple_Dual_Port_RAM + READ_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 0 + 8kx2 + false + false + 1 + 1 + 64 + 64 + false + false + false + false + 0 + false + false + CE + CE + ASYNC + true + true + false + false + false + false + true + 262144 + 64 + 64 + No_ECC + false + false + false + Stand_Alone + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..75bdf99c3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + +IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \ +axi64_4k_2clk_fifo.xci.out \ +synth/axi64_4k_2clk_fifo.vhd \ +) + +$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci new file mode 100644 index 000000000..3747f059f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -0,0 +1,584 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_4k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 512x72 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 9 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_4k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 509 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 511 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 512 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc new file mode 100644 index 000000000..647ca003b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + +IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \ +axi64_8k_2clk_fifo.xci.out \ +synth/axi64_8k_2clk_fifo.vhd \ +) + +$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci + $(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci new file mode 100644 index 000000000..8c3264cb7 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci @@ -0,0 +1,582 @@ + + + xilinx.com + xci + unknown + 1.0 + + + axi64_8k_2clk_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 1 + 1 + 0 + 0 + undef + 0.000 + 8 + 0 + 0 + 4 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 64 + 1 + 1 + 8 + 8 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 10 + BlankString + 18 + 69 + 32 + 64 + 32 + 64 + 2 + 0 + 18 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 12 + 11 + 12 + 11 + 12 + 0 + 1 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 4kx4 + 1kx36 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 10 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Independent_Clock + axi64_8k_2clk_fifo + 64 + false + 10 + false + false + 0 + 2 + 1021 + 13 + 1021 + 13 + 1021 + 13 + 3 + false + false + true + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + true + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Independent_Clocks_Block_RAM + Independent_Clocks_Distributed_RAM + Common_Clock_Block_RAM + 1 + 1022 + 1023 + 15 + 1023 + 15 + 1023 + 15 + 1021 + false + false + false + 0 + AXI_STREAM + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 18 + 1024 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 18 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 8 + 0 + 0 + 8 + 8 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc new file mode 100644 index 000000000..51dd6135e --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc @@ -0,0 +1,19 @@ +# +# Copyright 2016 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_AXI_INTERCON_2X64_128_BD_SRCS = $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml \ +$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v + +BD_AXI_INTERCON_2X64_128_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/, \ +axi_intercon_2x64_128_bd.bd.out \ +axi_intercon_2x64_128_bd_ooc.xdc \ +) + +# The cp below is a workaround for a Vivado issue where it is pulling in wrong sources +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd + $(call BUILD_VIVADO_BD,axi_intercon_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) + cp -f $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/synth/axi_intercon_2x64_128_bd.v $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/hdl/axi_intercon_2x64_128_bd.v diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd new file mode 100755 index 000000000..962d94246 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd @@ -0,0 +1,1326 @@ + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_128_bd + 1.00.a + + + isTop + true + + + + + S01_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 100000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + + + + + + + + S00_AXI + + + + + + DATA_WIDTH + 64 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 1000000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + + + + + + + + M00_AXI + + + + + + DATA_WIDTH + 256 + + + + + + + + PROTOCOL + AXI4 + + + + + + + + FREQ_HZ + 100000000 + + + + + + + + ID_WIDTH + 1 + + + + + + + + ADDR_WIDTH + 32 + + + + + + + + AWUSER_WIDTH + 0 + + + + + + + + ARUSER_WIDTH + 0 + + + + + + + + WUSER_WIDTH + 0 + + + + + + + + RUSER_WIDTH + 0 + + + + + + + + BUSER_WIDTH + 0 + + + + + + + + READ_WRITE_MODE + READ_WRITE + + + + + + + + HAS_BURST + 1 + + + + + + + + HAS_LOCK + 1 + + + + + + + + HAS_PROT + 1 + + + + + + + + HAS_CACHE + 1 + + + + + + + + HAS_QOS + 1 + + + + + + + + HAS_REGION + 1 + + + + + + + + HAS_WSTRB + 1 + + + + + + + + HAS_BRESP + 1 + + + + + + + + HAS_RRESP + 1 + + + + + + + + SUPPORTS_NARROW_BURST + 1 + + + + + + + + NUM_READ_OUTSTANDING + 2 + + + + + + + + NUM_WRITE_OUTSTANDING + 2 + + + + + + + + MAX_BURST_LENGTH + 256 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + + + + + + CLK.S00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S00_AXI_ACLK + + + + + + FREQ_HZ + 1000000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S00_ACLK + + + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + + + + + + ASSOCIATED_RESET + S00_AXI_ARESETN + + + + + + + + + + RST.S00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.S01_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + S01_AXI_ACLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_S01_ACLK + + + + + + + + ASSOCIATED_BUSIF + S01_AXI + + + + + + + + ASSOCIATED_RESET + S01_AXI_ARESETN + + + + + + + + + + RST.S01_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + S01_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + CLK.M00_AXI_ACLK + Clk + Clock + + + + + + + CLK + + + M00_AXI_ACLK + + + + + + FREQ_HZ + 100000000 + + + + + + + + PHASE + 0.000 + + + + + + + + CLK_DOMAIN + axi_intercon_2x64_128_bd_M00_ACLK + + + + + + + + ASSOCIATED_BUSIF + M00_AXI + + + + + + + + ASSOCIATED_RESET + M00_AXI_ARESETN + + + + + + + + + + RST.M00_AXI_ARESETN + Reset + Reset + + + + + + + RST + + + M00_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + S00_AXI_ACLK + + in + + + + S00_AXI_ARESETN + + in + + + + S01_AXI_ACLK + + in + + + + S01_AXI_ARESETN + + in + + + + M00_AXI_ACLK + + in + + + + M00_AXI_ARESETN + + in + + + + + + + S01_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x02000000 + 32M + + + + + S00_AXI + 4G + 32 + + + SEG_M00_AXI_Reg + /M00_AXI/Reg + 0x00000000 + 32M + + + + + + + M00_AXI + + Reg + 0 + 64K + 32 + register + + + + + + + xilinx.com + BlockDiagram + axi_intercon_2x64_128_bd_imp + 1.00.a + + + s00_width_conv + + + axi_intercon_2x64_128_bd_s00_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + s01_width_conv + + + axi_intercon_2x64_128_bd_s01_width_conv_0 + 64 + 256 + 2 + 1 + 2 + + + + xbar + + + axi_intercon_2x64_128_bd_xbar_0 + 2 + 1 + 2 + 256 + 1 + 0x00000001 + 0x00000002 + 0x00000003 + 0x00000004 + 0x00000005 + 0x00000006 + 0x00000007 + 0x00000008 + 0x00000009 + 0x0000000a + 0x0000000b + 0x0000000c + 0x0000000d + 0x0000000e + 0x0000000f + + + + m00_rs + + + axi_intercon_2x64_128_bd_m00_rs_0 + 1 + 1 + 1 + + + + s01_rs_0 + + + axi_intercon_2x64_128_bd_s01_rs_0_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_0 + + + axi_intercon_2x64_128_bd_s00_rs_0_0 + 1 + 1 + 1 + 1 + 1 + + + + s00_rs_1 + + + axi_intercon_2x64_128_bd_s00_rs_1_0 + 1 + 1 + 1 + 1 + 1 + + + + s01_rs_1 + + + axi_intercon_2x64_128_bd_s01_rs_1_0 + 1 + 1 + 1 + 1 + 1 + + + + + + xbar_M00_AXI + + + + + s01_rs_M_AXI + + + + + s00_rs_M_AXI + + + + + s00_width_conv_M_AXI + + + + + s01_width_conv_M_AXI + + + + + s00_rs_1_M_AXI + + + + + s01_rs_1_M_AXI + + + + + + + M00_AXI_ACLK_1 + + + + + + + + + + M00_AXI_ARESETN_1 + + + + + + + + + + S01_AXI_ACLK_1 + + + + + + S01_AXI_ARESETN_1 + + + + + + S00_AXI_ACLK_1 + + + + + + S00_AXI_ARESETN_1 + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml new file mode 100755 index 000000000..e26003603 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bxml @@ -0,0 +1,132 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v new file mode 100644 index 000000000..0a6fbf6cf --- /dev/null +++ b/fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd_wrapper.v @@ -0,0 +1,508 @@ +//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 +//Date : Mon Oct 24 19:58:35 2016 +//Host : ubuntu-VM running 64-bit Ubuntu 14.04.5 LTS +//Command : generate_target axi_intercon_2x64_128_bd_wrapper.bd +//Design : axi_intercon_2x64_128_bd_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module axi_intercon_2x64_128_bd_wrapper + (M00_AXI_ACLK, + M00_AXI_ARESETN, + M00_AXI_ARADDR, + M00_AXI_ARBURST, + M00_AXI_ARCACHE, + M00_AXI_ARID, + M00_AXI_ARLEN, + M00_AXI_ARLOCK, + M00_AXI_ARPROT, + M00_AXI_ARQOS, + M00_AXI_ARREADY, + M00_AXI_ARREGION, + M00_AXI_ARSIZE, + M00_AXI_ARVALID, + M00_AXI_AWADDR, + M00_AXI_AWBURST, + M00_AXI_AWCACHE, + M00_AXI_AWID, + M00_AXI_AWLEN, + M00_AXI_AWLOCK, + M00_AXI_AWPROT, + M00_AXI_AWQOS, + M00_AXI_AWREADY, + M00_AXI_AWREGION, + M00_AXI_AWSIZE, + M00_AXI_AWVALID, + M00_AXI_BID, + M00_AXI_BREADY, + M00_AXI_BRESP, + M00_AXI_BVALID, + M00_AXI_RDATA, + M00_AXI_RID, + M00_AXI_RLAST, + M00_AXI_RREADY, + M00_AXI_RRESP, + M00_AXI_RVALID, + M00_AXI_WDATA, + M00_AXI_WLAST, + M00_AXI_WREADY, + M00_AXI_WSTRB, + M00_AXI_WVALID, + S00_AXI_ACLK, + S00_AXI_ARESETN, + S00_AXI_ARADDR, + S00_AXI_ARBURST, + S00_AXI_ARCACHE, + S00_AXI_ARID, + S00_AXI_ARLEN, + S00_AXI_ARLOCK, + S00_AXI_ARPROT, + S00_AXI_ARQOS, + S00_AXI_ARREADY, + S00_AXI_ARREGION, + S00_AXI_ARSIZE, + S00_AXI_ARVALID, + S00_AXI_AWADDR, + S00_AXI_AWBURST, + S00_AXI_AWCACHE, + S00_AXI_AWID, + S00_AXI_AWLEN, + S00_AXI_AWLOCK, + S00_AXI_AWPROT, + S00_AXI_AWQOS, + S00_AXI_AWREADY, + S00_AXI_AWREGION, + S00_AXI_AWSIZE, + S00_AXI_AWVALID, + S00_AXI_BID, + S00_AXI_BREADY, + S00_AXI_BRESP, + S00_AXI_BVALID, + S00_AXI_RDATA, + S00_AXI_RID, + S00_AXI_RLAST, + S00_AXI_RREADY, + S00_AXI_RRESP, + S00_AXI_RVALID, + S00_AXI_WDATA, + S00_AXI_WLAST, + S00_AXI_WREADY, + S00_AXI_WSTRB, + S00_AXI_WVALID, + S01_AXI_ACLK, + S01_AXI_ARESETN, + S01_AXI_ARADDR, + S01_AXI_ARBURST, + S01_AXI_ARCACHE, + S01_AXI_ARID, + S01_AXI_ARLEN, + S01_AXI_ARLOCK, + S01_AXI_ARPROT, + S01_AXI_ARQOS, + S01_AXI_ARREADY, + S01_AXI_ARREGION, + S01_AXI_ARSIZE, + S01_AXI_ARVALID, + S01_AXI_AWADDR, + S01_AXI_AWBURST, + S01_AXI_AWCACHE, + S01_AXI_AWID, + S01_AXI_AWLEN, + S01_AXI_AWLOCK, + S01_AXI_AWPROT, + S01_AXI_AWQOS, + S01_AXI_AWREADY, + S01_AXI_AWREGION, + S01_AXI_AWSIZE, + S01_AXI_AWVALID, + S01_AXI_BID, + S01_AXI_BREADY, + S01_AXI_BRESP, + S01_AXI_BVALID, + S01_AXI_RDATA, + S01_AXI_RID, + S01_AXI_RLAST, + S01_AXI_RREADY, + S01_AXI_RRESP, + S01_AXI_RVALID, + S01_AXI_WDATA, + S01_AXI_WLAST, + S01_AXI_WREADY, + S01_AXI_WSTRB, + S01_AXI_WVALID); + input M00_AXI_ACLK; + input M00_AXI_ARESETN; + output [31:0]M00_AXI_ARADDR; + output [1:0]M00_AXI_ARBURST; + output [3:0]M00_AXI_ARCACHE; + output [0:0]M00_AXI_ARID; + output [7:0]M00_AXI_ARLEN; + output [0:0]M00_AXI_ARLOCK; + output [2:0]M00_AXI_ARPROT; + output [3:0]M00_AXI_ARQOS; + input M00_AXI_ARREADY; + output [3:0]M00_AXI_ARREGION; + output [2:0]M00_AXI_ARSIZE; + output M00_AXI_ARVALID; + output [31:0]M00_AXI_AWADDR; + output [1:0]M00_AXI_AWBURST; + output [3:0]M00_AXI_AWCACHE; + output [0:0]M00_AXI_AWID; + output [7:0]M00_AXI_AWLEN; + output [0:0]M00_AXI_AWLOCK; + output [2:0]M00_AXI_AWPROT; + output [3:0]M00_AXI_AWQOS; + input M00_AXI_AWREADY; + output [3:0]M00_AXI_AWREGION; + output [2:0]M00_AXI_AWSIZE; + output M00_AXI_AWVALID; + input [0:0]M00_AXI_BID; + output M00_AXI_BREADY; + input [1:0]M00_AXI_BRESP; + input M00_AXI_BVALID; + input [255:0]M00_AXI_RDATA; + input [0:0]M00_AXI_RID; + input M00_AXI_RLAST; + output M00_AXI_RREADY; + input [1:0]M00_AXI_RRESP; + input M00_AXI_RVALID; + output [255:0]M00_AXI_WDATA; + output M00_AXI_WLAST; + input M00_AXI_WREADY; + output [31:0]M00_AXI_WSTRB; + output M00_AXI_WVALID; + input S00_AXI_ACLK; + input S00_AXI_ARESETN; + input [31:0]S00_AXI_ARADDR; + input [1:0]S00_AXI_ARBURST; + input [3:0]S00_AXI_ARCACHE; + input [0:0]S00_AXI_ARID; + input [7:0]S00_AXI_ARLEN; + input [0:0]S00_AXI_ARLOCK; + input [2:0]S00_AXI_ARPROT; + input [3:0]S00_AXI_ARQOS; + output S00_AXI_ARREADY; + input [3:0]S00_AXI_ARREGION; + input [2:0]S00_AXI_ARSIZE; + input S00_AXI_ARVALID; + input [31:0]S00_AXI_AWADDR; + input [1:0]S00_AXI_AWBURST; + input [3:0]S00_AXI_AWCACHE; + input [0:0]S00_AXI_AWID; + input [7:0]S00_AXI_AWLEN; + input [0:0]S00_AXI_AWLOCK; + input [2:0]S00_AXI_AWPROT; + input [3:0]S00_AXI_AWQOS; + output S00_AXI_AWREADY; + input [3:0]S00_AXI_AWREGION; + input [2:0]S00_AXI_AWSIZE; + input S00_AXI_AWVALID; + output [0:0]S00_AXI_BID; + input S00_AXI_BREADY; + output [1:0]S00_AXI_BRESP; + output S00_AXI_BVALID; + output [63:0]S00_AXI_RDATA; + output [0:0]S00_AXI_RID; + output S00_AXI_RLAST; + input S00_AXI_RREADY; + output [1:0]S00_AXI_RRESP; + output S00_AXI_RVALID; + input [63:0]S00_AXI_WDATA; + input S00_AXI_WLAST; + output S00_AXI_WREADY; + input [7:0]S00_AXI_WSTRB; + input S00_AXI_WVALID; + input S01_AXI_ACLK; + input S01_AXI_ARESETN; + input [31:0]S01_AXI_ARADDR; + input [1:0]S01_AXI_ARBURST; + input [3:0]S01_AXI_ARCACHE; + input [0:0]S01_AXI_ARID; + input [7:0]S01_AXI_ARLEN; + input [0:0]S01_AXI_ARLOCK; + input [2:0]S01_AXI_ARPROT; + input [3:0]S01_AXI_ARQOS; + output S01_AXI_ARREADY; + input [3:0]S01_AXI_ARREGION; + input [2:0]S01_AXI_ARSIZE; + input S01_AXI_ARVALID; + input [31:0]S01_AXI_AWADDR; + input [1:0]S01_AXI_AWBURST; + input [3:0]S01_AXI_AWCACHE; + input [0:0]S01_AXI_AWID; + input [7:0]S01_AXI_AWLEN; + input [0:0]S01_AXI_AWLOCK; + input [2:0]S01_AXI_AWPROT; + input [3:0]S01_AXI_AWQOS; + output S01_AXI_AWREADY; + input [3:0]S01_AXI_AWREGION; + input [2:0]S01_AXI_AWSIZE; + input S01_AXI_AWVALID; + output [0:0]S01_AXI_BID; + input S01_AXI_BREADY; + output [1:0]S01_AXI_BRESP; + output S01_AXI_BVALID; + output [63:0]S01_AXI_RDATA; + output [0:0]S01_AXI_RID; + output S01_AXI_RLAST; + input S01_AXI_RREADY; + output [1:0]S01_AXI_RRESP; + output S01_AXI_RVALID; + input [63:0]S01_AXI_WDATA; + input S01_AXI_WLAST; + output S01_AXI_WREADY; + input [7:0]S01_AXI_WSTRB; + input S01_AXI_WVALID; + + wire M00_AXI_ACLK; + wire M00_AXI_ARESETN; + wire [31:0]M00_AXI_ARADDR; + wire [1:0]M00_AXI_ARBURST; + wire [3:0]M00_AXI_ARCACHE; + wire [0:0]M00_AXI_ARID; + wire [7:0]M00_AXI_ARLEN; + wire [0:0]M00_AXI_ARLOCK; + wire [2:0]M00_AXI_ARPROT; + wire [3:0]M00_AXI_ARQOS; + wire M00_AXI_ARREADY; + wire [3:0]M00_AXI_ARREGION; + wire [2:0]M00_AXI_ARSIZE; + wire M00_AXI_ARVALID; + wire [31:0]M00_AXI_AWADDR; + wire [1:0]M00_AXI_AWBURST; + wire [3:0]M00_AXI_AWCACHE; + wire [0:0]M00_AXI_AWID; + wire [7:0]M00_AXI_AWLEN; + wire [0:0]M00_AXI_AWLOCK; + wire [2:0]M00_AXI_AWPROT; + wire [3:0]M00_AXI_AWQOS; + wire M00_AXI_AWREADY; + wire [3:0]M00_AXI_AWREGION; + wire [2:0]M00_AXI_AWSIZE; + wire M00_AXI_AWVALID; + wire [0:0]M00_AXI_BID; + wire M00_AXI_BREADY; + wire [1:0]M00_AXI_BRESP; + wire M00_AXI_BVALID; + wire [255:0]M00_AXI_RDATA; + wire [0:0]M00_AXI_RID; + wire M00_AXI_RLAST; + wire M00_AXI_RREADY; + wire [1:0]M00_AXI_RRESP; + wire M00_AXI_RVALID; + wire [255:0]M00_AXI_WDATA; + wire M00_AXI_WLAST; + wire M00_AXI_WREADY; + wire [31:0]M00_AXI_WSTRB; + wire M00_AXI_WVALID; + wire S00_AXI_ACLK; + wire S00_AXI_ARESETN; + wire [31:0]S00_AXI_ARADDR; + wire [1:0]S00_AXI_ARBURST; + wire [3:0]S00_AXI_ARCACHE; + wire [0:0]S00_AXI_ARID; + wire [7:0]S00_AXI_ARLEN; + wire [0:0]S00_AXI_ARLOCK; + wire [2:0]S00_AXI_ARPROT; + wire [3:0]S00_AXI_ARQOS; + wire S00_AXI_ARREADY; + wire [3:0]S00_AXI_ARREGION; + wire [2:0]S00_AXI_ARSIZE; + wire S00_AXI_ARVALID; + wire [31:0]S00_AXI_AWADDR; + wire [1:0]S00_AXI_AWBURST; + wire [3:0]S00_AXI_AWCACHE; + wire [0:0]S00_AXI_AWID; + wire [7:0]S00_AXI_AWLEN; + wire [0:0]S00_AXI_AWLOCK; + wire [2:0]S00_AXI_AWPROT; + wire [3:0]S00_AXI_AWQOS; + wire S00_AXI_AWREADY; + wire [3:0]S00_AXI_AWREGION; + wire [2:0]S00_AXI_AWSIZE; + wire S00_AXI_AWVALID; + wire [0:0]S00_AXI_BID; + wire S00_AXI_BREADY; + wire [1:0]S00_AXI_BRESP; + wire S00_AXI_BVALID; + wire [63:0]S00_AXI_RDATA; + wire [0:0]S00_AXI_RID; + wire S00_AXI_RLAST; + wire S00_AXI_RREADY; + wire [1:0]S00_AXI_RRESP; + wire S00_AXI_RVALID; + wire [63:0]S00_AXI_WDATA; + wire S00_AXI_WLAST; + wire S00_AXI_WREADY; + wire [7:0]S00_AXI_WSTRB; + wire S00_AXI_WVALID; + wire S01_AXI_ACLK; + wire S01_AXI_ARESETN; + wire [31:0]S01_AXI_ARADDR; + wire [1:0]S01_AXI_ARBURST; + wire [3:0]S01_AXI_ARCACHE; + wire [0:0]S01_AXI_ARID; + wire [7:0]S01_AXI_ARLEN; + wire [0:0]S01_AXI_ARLOCK; + wire [2:0]S01_AXI_ARPROT; + wire [3:0]S01_AXI_ARQOS; + wire S01_AXI_ARREADY; + wire [3:0]S01_AXI_ARREGION; + wire [2:0]S01_AXI_ARSIZE; + wire S01_AXI_ARVALID; + wire [31:0]S01_AXI_AWADDR; + wire [1:0]S01_AXI_AWBURST; + wire [3:0]S01_AXI_AWCACHE; + wire [0:0]S01_AXI_AWID; + wire [7:0]S01_AXI_AWLEN; + wire [0:0]S01_AXI_AWLOCK; + wire [2:0]S01_AXI_AWPROT; + wire [3:0]S01_AXI_AWQOS; + wire S01_AXI_AWREADY; + wire [3:0]S01_AXI_AWREGION; + wire [2:0]S01_AXI_AWSIZE; + wire S01_AXI_AWVALID; + wire [0:0]S01_AXI_BID; + wire S01_AXI_BREADY; + wire [1:0]S01_AXI_BRESP; + wire S01_AXI_BVALID; + wire [63:0]S01_AXI_RDATA; + wire [0:0]S01_AXI_RID; + wire S01_AXI_RLAST; + wire S01_AXI_RREADY; + wire [1:0]S01_AXI_RRESP; + wire S01_AXI_RVALID; + wire [63:0]S01_AXI_WDATA; + wire S01_AXI_WLAST; + wire S01_AXI_WREADY; + wire [7:0]S01_AXI_WSTRB; + wire S01_AXI_WVALID; + + axi_intercon_2x64_128_bd axi_intercon_2x64_128_bd_i + (.M00_AXI_ACLK(M00_AXI_ACLK), + .M00_AXI_ARESETN(M00_AXI_ARESETN), + .M00_AXI_araddr(M00_AXI_ARADDR), + .M00_AXI_arburst(M00_AXI_ARBURST), + .M00_AXI_arcache(M00_AXI_ARCACHE), + .M00_AXI_arid(M00_AXI_ARID), + .M00_AXI_arlen(M00_AXI_ARLEN), + .M00_AXI_arlock(M00_AXI_ARLOCK), + .M00_AXI_arprot(M00_AXI_ARPROT), + .M00_AXI_arqos(M00_AXI_ARQOS), + .M00_AXI_arready(M00_AXI_ARREADY), + .M00_AXI_arregion(M00_AXI_ARREGION), + .M00_AXI_arsize(M00_AXI_ARSIZE), + .M00_AXI_arvalid(M00_AXI_ARVALID), + .M00_AXI_awaddr(M00_AXI_AWADDR), + .M00_AXI_awburst(M00_AXI_AWBURST), + .M00_AXI_awcache(M00_AXI_AWCACHE), + .M00_AXI_awid(M00_AXI_AWID), + .M00_AXI_awlen(M00_AXI_AWLEN), + .M00_AXI_awlock(M00_AXI_AWLOCK), + .M00_AXI_awprot(M00_AXI_AWPROT), + .M00_AXI_awqos(M00_AXI_AWQOS), + .M00_AXI_awready(M00_AXI_AWREADY), + .M00_AXI_awregion(M00_AXI_AWREGION), + .M00_AXI_awsize(M00_AXI_AWSIZE), + .M00_AXI_awvalid(M00_AXI_AWVALID), + .M00_AXI_bid(M00_AXI_BID), + .M00_AXI_bready(M00_AXI_BREADY), + .M00_AXI_bresp(M00_AXI_BRESP), + .M00_AXI_bvalid(M00_AXI_BVALID), + .M00_AXI_rdata(M00_AXI_RDATA), + .M00_AXI_rid(M00_AXI_RID), + .M00_AXI_rlast(M00_AXI_RLAST), + .M00_AXI_rready(M00_AXI_RREADY), + .M00_AXI_rresp(M00_AXI_RRESP), + .M00_AXI_rvalid(M00_AXI_RVALID), + .M00_AXI_wdata(M00_AXI_WDATA), + .M00_AXI_wlast(M00_AXI_WLAST), + .M00_AXI_wready(M00_AXI_WREADY), + .M00_AXI_wstrb(M00_AXI_WSTRB), + .M00_AXI_wvalid(M00_AXI_WVALID), + .S00_AXI_ACLK(S00_AXI_ACLK), + .S00_AXI_ARESETN(S00_AXI_ARESETN), + .S00_AXI_araddr(S00_AXI_ARADDR), + .S00_AXI_arburst(S00_AXI_ARBURST), + .S00_AXI_arcache(S00_AXI_ARCACHE), + .S00_AXI_arid(S00_AXI_ARID), + .S00_AXI_arlen(S00_AXI_ARLEN), + .S00_AXI_arlock(S00_AXI_ARLOCK), + .S00_AXI_arprot(S00_AXI_ARPROT), + .S00_AXI_arqos(S00_AXI_ARQOS), + .S00_AXI_arready(S00_AXI_ARREADY), + .S00_AXI_arregion(S00_AXI_ARREGION), + .S00_AXI_arsize(S00_AXI_ARSIZE), + .S00_AXI_arvalid(S00_AXI_ARVALID), + .S00_AXI_awaddr(S00_AXI_AWADDR), + .S00_AXI_awburst(S00_AXI_AWBURST), + .S00_AXI_awcache(S00_AXI_AWCACHE), + .S00_AXI_awid(S00_AXI_AWID), + .S00_AXI_awlen(S00_AXI_AWLEN), + .S00_AXI_awlock(S00_AXI_AWLOCK), + .S00_AXI_awprot(S00_AXI_AWPROT), + .S00_AXI_awqos(S00_AXI_AWQOS), + .S00_AXI_awready(S00_AXI_AWREADY), + .S00_AXI_awregion(S00_AXI_AWREGION), + .S00_AXI_awsize(S00_AXI_AWSIZE), + .S00_AXI_awvalid(S00_AXI_AWVALID), + .S00_AXI_bid(S00_AXI_BID), + .S00_AXI_bready(S00_AXI_BREADY), + .S00_AXI_bresp(S00_AXI_BRESP), + .S00_AXI_bvalid(S00_AXI_BVALID), + .S00_AXI_rdata(S00_AXI_RDATA), + .S00_AXI_rid(S00_AXI_RID), + .S00_AXI_rlast(S00_AXI_RLAST), + .S00_AXI_rready(S00_AXI_RREADY), + .S00_AXI_rresp(S00_AXI_RRESP), + .S00_AXI_rvalid(S00_AXI_RVALID), + .S00_AXI_wdata(S00_AXI_WDATA), + .S00_AXI_wlast(S00_AXI_WLAST), + .S00_AXI_wready(S00_AXI_WREADY), + .S00_AXI_wstrb(S00_AXI_WSTRB), + .S00_AXI_wvalid(S00_AXI_WVALID), + .S01_AXI_ACLK(S01_AXI_ACLK), + .S01_AXI_ARESETN(S01_AXI_ARESETN), + .S01_AXI_araddr(S01_AXI_ARADDR), + .S01_AXI_arburst(S01_AXI_ARBURST), + .S01_AXI_arcache(S01_AXI_ARCACHE), + .S01_AXI_arid(S01_AXI_ARID), + .S01_AXI_arlen(S01_AXI_ARLEN), + .S01_AXI_arlock(S01_AXI_ARLOCK), + .S01_AXI_arprot(S01_AXI_ARPROT), + .S01_AXI_arqos(S01_AXI_ARQOS), + .S01_AXI_arready(S01_AXI_ARREADY), + .S01_AXI_arregion(S01_AXI_ARREGION), + .S01_AXI_arsize(S01_AXI_ARSIZE), + .S01_AXI_arvalid(S01_AXI_ARVALID), + .S01_AXI_awaddr(S01_AXI_AWADDR), + .S01_AXI_awburst(S01_AXI_AWBURST), + .S01_AXI_awcache(S01_AXI_AWCACHE), + .S01_AXI_awid(S01_AXI_AWID), + .S01_AXI_awlen(S01_AXI_AWLEN), + .S01_AXI_awlock(S01_AXI_AWLOCK), + .S01_AXI_awprot(S01_AXI_AWPROT), + .S01_AXI_awqos(S01_AXI_AWQOS), + .S01_AXI_awready(S01_AXI_AWREADY), + .S01_AXI_awregion(S01_AXI_AWREGION), + .S01_AXI_awsize(S01_AXI_AWSIZE), + .S01_AXI_awvalid(S01_AXI_AWVALID), + .S01_AXI_bid(S01_AXI_BID), + .S01_AXI_bready(S01_AXI_BREADY), + .S01_AXI_bresp(S01_AXI_BRESP), + .S01_AXI_bvalid(S01_AXI_BVALID), + .S01_AXI_rdata(S01_AXI_RDATA), + .S01_AXI_rid(S01_AXI_RID), + .S01_AXI_rlast(S01_AXI_RLAST), + .S01_AXI_rready(S01_AXI_RREADY), + .S01_AXI_rresp(S01_AXI_RRESP), + .S01_AXI_rvalid(S01_AXI_RVALID), + .S01_AXI_wdata(S01_AXI_WDATA), + .S01_AXI_wlast(S01_AXI_WLAST), + .S01_AXI_wready(S01_AXI_WREADY), + .S01_AXI_wstrb(S01_AXI_WSTRB), + .S01_AXI_wvalid(S01_AXI_WVALID)); +endmodule diff --git a/fpga/usrp3/top/x300/ip/bootram/Makefile.inc b/fpga/usrp3/top/x300/ip/bootram/Makefile.inc new file mode 100644 index 000000000..a42639f25 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_BOOTRAM_SRCS = $(IP_BUILD_DIR)/bootram/bootram.xci + +IP_BOOTRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/bootram/, \ +bootram.xci.out \ +synth/bootram.vhd \ +) + +$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS) : $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe + $(call BUILD_VIVADO_IP,bootram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/bootram/bootram.coe b/fpga/usrp3/top/x300/ip/bootram/bootram.coe new file mode 100644 index 000000000..253a292b1 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/bootram.coe @@ -0,0 +1,8194 @@ +memory_initialization_radix=16; +memory_initialization_vector= +0b0b80e4, +c9040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +0b0b0b89, +92040000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +71fd0608, +72830609, +81058205, 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+00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000, +00000000; \ No newline at end of file diff --git a/fpga/usrp3/top/x300/ip/bootram/bootram.xci b/fpga/usrp3/top/x300/ip/bootram/bootram.xci new file mode 100644 index 000000000..ec46d7a5f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bootram/bootram.xci @@ -0,0 +1,318 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bootram + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 13 + 13 + 1 + 4 + 0 + 1 + 8 + 0 + 0 + 8 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 20.388 mW + kintex7 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bootram.mem + bootram.mif + 0 + 1 + 0 + 0 + 1 + 8192 + 8192 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 1 + 1 + 1 + 0 + 0 + 0 + 4 + 4 + 8192 + 8192 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + kintex7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 8 + NONE + bootram.coe + ALL + bootram + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Always_Enabled + Single_Bit_Error_Injection + true + Native + true + no_Mem_file_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + true + false + false + false + false + false + 8192 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc new file mode 100644 index 000000000..e05a173c3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bus_clk_gen/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci + +IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \ +bus_clk_gen.xci.out \ +bus_clk_gen.v \ +) + +$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS) : $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci + $(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci b/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci new file mode 100644 index 000000000..dd1f688fb --- /dev/null +++ b/fpga/usrp3/top/x300/ip/bus_clk_gen/bus_clk_gen.xci @@ -0,0 +1,786 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bus_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 80.0 + 100.0 + 0000 + 0000 + 187.500 + 0000 + 0000 + 125.000 + BUFG + 50.0 + false + 187.500 + 0.000 + 50.000 + 187.5 + 0.00 + 1 + 0000 + 0000 + 93.750 + No_buffer + 50.0 + false + 125.000 + 0.000 + 50.000 + 125.000 + 0.000 + 1 + 1 + 0000 + 0000 + 214.286 + BUFG + 50.0 + false + 93.750 + 0.000 + 50.000 + 93.75 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 214.286 + 0.000 + 50.000 + 215 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2_UNBUF + CLK_OUT3 + CLK_OUT4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 1.5 + 2.0 + 0.872093023255814 + 1.875 + 1.875 + 1.875 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_ONCHIP + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________125.000____________0.010 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 12.000 + 0.000 + FALSE + 8.000 + 10.000 + 8.000 + 0.500 + 0.000 + FALSE + 12 + 0.500 + 0.000 + FALSE + 16 + 0.500 + 0.000 + FALSE + 7 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 4 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940 + CLK_OUT2_UNBUF___125.000______0.000______50.0_______91.831_____73.940 + CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940 + CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940 + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + CLK_IN1 + PLL + AUTO + 125.000 + 0.010 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + bus_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 80.0 + 0.010 + 100.0 + 0.010 + BUFG + 85.263 + false + 73.940 + 50.000 + 187.5 + 0.00 + 1 + true + No_buffer + 91.831 + false + 73.940 + 50.000 + 125.000 + 0.000 + 1 + true + BUFG + 96.813 + false + 73.940 + 50.000 + 93.75 + 0.000 + 1 + true + BUFG + 83.210 + false + 73.940 + 50.000 + 215 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2_UNBUF + false + CLK_OUT3 + false + CLK_OUT4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + bus_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_ONCHIP + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 12 + 0.000 + false + 8.000 + 10.000 + 8 + 0.500 + 0.000 + false + 12 + 0.500 + 0.000 + false + 16 + 0.500 + 0.000 + false + 7 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 4 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + CLK_IN1 + PLL + MMCM_ADV + 125.000 + 0.010 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + false + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc b/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc new file mode 100644 index 000000000..90b0be153 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/Makefile.inc @@ -0,0 +1,26 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR3_32BIT_SRCS = \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit.xci \ +$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + +IP_DDR3_32BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit.xci.out \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/rtl/ddr3_32bit_mig.v \ +) + +IP_DDR3_32BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_32bit/, \ +ddr3_32bit/example_design/sim/ddr3_model.sv \ +ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \ +) + + +$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj + cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds + $(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci b/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci new file mode 100644 index 000000000..58fad4f82 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/ddr3_32bit.xci @@ -0,0 +1,2645 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3_32bit + + + 0 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + 0 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0.000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj new file mode 100644 index 000000000..ed5c3dcaa --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj @@ -0,0 +1,163 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7k325t-ffg900/-2 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + 7k/xc7k325t-ffg900 + + + DDR3_SDRAM/Components/MT41J256m16XX-125 + 1666 + 1.8V + 4:1 + 100.04 + 1 + 1200 + 4.000 + 6 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 30 + 256 + 1 + 1 + + + + diff --git a/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj new file mode 100644 index 000000000..00c7fa345 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj @@ -0,0 +1,163 @@ + + + + ddr3_32bit + 1 + 1 + OFF + 1024 + ON + Disabled + xc7k410t-ffg900/-2 + 4.0 + Single-Ended + No Buffer + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + 7k/xc7k325t-ffg900 + + + DDR3_SDRAM/Components/MT41J256m16XX-125 + 1666 + 1.8V + 4:1 + 100.04 + 1 + 1200 + 4.000 + 6 + 1 + 1 + 1 + 32 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + ROW_BANK_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 9 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 7 + Enabled + Normal + Dynamic ODT off + AXI + + ROUND_ROBIN + 30 + 256 + 1 + 1 + + + + diff --git a/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc new file mode 100644 index 000000000..e022d9a1c --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + +IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \ +fifo_4k_2clk.xci.out \ +synth/fifo_4k_2clk.vhd \ +) + +$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci + $(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci new file mode 100644 index 000000000..dddfacc1e --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -0,0 +1,576 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4k_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 9 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 0 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1 + 9 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4k_2clk + 64 + false + 9 + true + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 1 + 511 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 510 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 512 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 10 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc b/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc new file mode 100644 index 000000000..8c5c54213 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_short_2clk/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci + +IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \ +fifo_short_2clk.xci.out \ +synth/fifo_short_2clk.vhd \ +) + +$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci + $(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci b/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci new file mode 100644 index 000000000..49761459c --- /dev/null +++ b/fpga/usrp3/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -0,0 +1,578 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_short_2clk + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 5 + BlankString + 72 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 72 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x72 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 5 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_short_2clk + 64 + false + 5 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 31 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 30 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 72 + 32 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 72 + 32 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 6 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + true + false + Active_High + 0 + false + Active_High + 1 + true + 6 + false + FIFO + false + false + false + false + FIFO + FIFO + 3 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc b/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc new file mode 100644 index 000000000..d79a40e91 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/input_sample_fifo/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_INPUT_SAMPLE_FIFO_SRCS = $(IP_BUILD_DIR)/input_sample_fifo/input_sample_fifo.xci + +IP_INPUT_SAMPLE_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/input_sample_fifo/, \ +nput_sample_fifo.xci.out \ +synth/input_sample_fifo.vhd \ +) + +$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS) : $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci + $(call BUILD_VIVADO_IP,input_sample_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci b/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci new file mode 100644 index 000000000..1f3e58e2d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/input_sample_fifo/input_sample_fifo.xci @@ -0,0 +1,575 @@ + + + xilinx.com + xci + unknown + 1.0 + + + input_sample_fifo + + + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + 100000000 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 28 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 28 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintex7 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 2 + BlankString + 1 + 0 + 0 + 0 + 0 + 1 + 512x36 + 1kx18 + 512x36 + 1kx36 + 512x36 + 1kx36 + 512x36 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 16 + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 4 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + true + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + input_sample_fifo + 64 + false + 4 + false + false + 0 + 4 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 5 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 15 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 14 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 28 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 28 + 16 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + First_Word_Fall_Through + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 4 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 0 + 0 + 0 + 0 + 0 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 4 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..9c14cc13a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,50 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +ONE_GIGE_PHY_SRCS = \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v \ +$(IP_DIR)/one_gig_eth_pcs_pma/one_gige_phy.v \ +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/, \ +one_gig_eth_pcs_pma_example_design.v \ +one_gig_eth_pcs_pma_reset_sync_ex.v \ +one_gig_eth_pcs_pma_sync_block_ex.v \ +one_gig_eth_pcs_pma_tx_elastic_buffer.v \ +one_gig_eth_pcs_pma_clocking.v \ +one_gig_eth_pcs_pma_gt_common.v \ +one_gig_eth_pcs_pma_resets.v \ +one_gig_eth_pcs_pma_support.v \ +) + +IP_ONE_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + +IP_ONE_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/one_gig_eth_pcs_pma/, \ +one_gig_eth_pcs_pma.xci.out \ +synth/one_gig_eth_pcs_pma_block.v \ +synth/one_gig_eth_pcs_pma_reset_sync.v \ +synth/one_gig_eth_pcs_pma.v \ +synth/one_gig_eth_pcs_pma_ooc.xdc \ +synth/one_gig_eth_pcs_pma_sync_block.v \ +synth/one_gig_eth_pcs_pma.xdc \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard.v \ +synth/transceiver/one_gig_eth_pcs_pma_transceiver.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_init.v \ +synth/transceiver/one_gig_eth_pcs_pma_reset_wtd_timer.v \ +synth/transceiver/one_gig_eth_pcs_pma_tx_startup_fsm.v \ +synth/transceiver/one_gig_eth_pcs_pma_gtwizard_multi_gt.v \ +synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \ +) + +$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) + +$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch + cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v.orig + patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_support.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..245a6dd8b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci @@ -0,0 +1,353 @@ + + + xilinx.com + xci + unknown + 1.0 + + + one_gig_eth_pcs_pma + + + 1 + 1 + 1 + 1 + + + + 0 + + + + 0 + + + 0 + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + + + + 0 + + + + 0 + false + 100000000 + + + + 0 + + + + 0 + + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + + + 100000000 + 0 + 0.000 + false + false + false + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + false + false + false + + + + 100000000 + 0 + 0.000 + 0 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + ACTIVE_LOW + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + + 100000000 + 0 + 0.000 + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + + + + 0 + true + 0 + 0 + false + false + DIFF_PAIR_0 + DIFF_PAIR_1 + false + DIFF_PAIR_0 + DIFF_PAIR_1 + kintex7 + 0 + one_gig_eth_pcs_pma + 50 + false + . + false + false + false + false + kintex7 + 8 + 9 + X0Y0 + 7 + 4 + GTH + false + false + false + false + true + false + false + 1 + clk0 + 125 + TXOUTCLK + true + false + one_gig_eth_pcs_pma_gt + false + GTXE2 + false + 1 + false + false + true + xc7k410t + false + 1 + false + false + Sync + one_gig_eth_pcs_pma + Custom + 50 + TEMAC + Custom + 0 + false + false + false + false + X0Y0 + GTH + false + false + 125 + Custom + true + 1G + 1 + Transceiver + 125 + clk0 + TXOUTCLK + DIFF_PAIR_0 + DIFF_PAIR_1 + false + 10_100_1000 + false + 1000BASEX + Include_Shared_Logic_in_Example_Design + Time_of_day + false + DIFF_PAIR_0 + DIFF_PAIR_1 + 1 + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 6 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch new file mode 100644 index 000000000..41f963797 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch @@ -0,0 +1,25 @@ +65,66d64 +< input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality. +< input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality. +70,71d67 +< output gtrefclk, // gtrefclk routed through an IBUFG. +< output gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +88d83 +< wire gtrefclk_i; +93,108d87 +< // Clock circuitry for the Transceiver uses a differential input clock. +< // gtrefclk is routed to the tranceiver. +< IBUFDS_GTE2 ibufds_gtrefclk ( +< .I (gtrefclk_p), +< .IB (gtrefclk_n), +< .CEB (1'b0), +< .O (gtrefclk_i), +< .ODIV2 () +< ); +< +< assign gtrefclk = gtrefclk_i; +< +< BUFG bufg_gtrefclk ( +< .I (gtrefclk_i), +< .O (gtrefclk_bufg) +< ); diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch new file mode 100644 index 000000000..277c890f1 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_support.v.patch @@ -0,0 +1,17 @@ +70,73c70,71 +< input gtrefclk_p, // differential clock +< input gtrefclk_n, // differential clock +< output gtrefclk_out, // Very high quality clock for GT transceiver. +< output gtrefclk_bufg_out, +--- +> input gtrefclk, // gtrefclk routed through an IBUFG. +> input gtrefclk_bufg, // gtrefclk routed through a BUFG for driving logic. +125,126d122 +< wire gtrefclk; // High quality clock +< wire gtrefclk_bufg; +205,206d200 +< .gtrefclk_p (gtrefclk_p), +< .gtrefclk_n (gtrefclk_n), +210,211d203 +< .gtrefclk (gtrefclk), +< .gtrefclk_bufg (gtrefclk_bufg), diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v new file mode 100644 index 000000000..0b02b1942 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.v @@ -0,0 +1,100 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy +( + input independent_clock, + + // Tranceiver Interface + //--------------------- + input gtrefclk, // Reference clock for MGT: 125MHz, very high quality. + input gtrefclk_bufg, // Reference clock routed through a BUFG + output txp, // Differential +ve of serial transmission from PMA to PMD. + output txn, // Differential -ve of serial transmission from PMA to PMD. + input rxp, // Differential +ve for serial reception from PMD to PMA. + input rxn, // Differential -ve for serial reception from PMD to PMA. + + // GMII Interface (client MAC <=> PCS) + //------------------------------------ + output gmii_clk, // Receive clock to client MAC. + input [7:0] gmii_txd, // Transmit data from client MAC. + input gmii_tx_en, // Transmit control signal from client MAC. + input gmii_tx_er, // Transmit control signal from client MAC. + output reg [7:0] gmii_rxd, // Received Data to client MAC. + output reg gmii_rx_dv, // Received control signal to client MAC. + output reg gmii_rx_er, // Received control signal to client MAC. + + // Management: MDIO Interface + //--------------------------- + input mdc, // Management Data Clock + input mdio_i, // Management Data In + output mdio_o, // Management Data Out + output mdio_t, // Management Data Tristate + input [4:0] configuration_vector, // Alternative to MDIO interface. + input configuration_valid, // Validation signal for Config vector + + // General IO's + //------------- + output [15:0] status_vector, // Core status. + input reset, // Asynchronous reset for entire core. + input signal_detect // Input from PMD to indicate presence of optical input. +); + + wire resetdone; // To indicate that the GT transceiver has completed its reset cycle + wire userclk; // 62.5MHz clock for GT transceiver Tx/Rx user clocks + wire userclk2; // 125MHz clock for core reference clock. + wire rxuserclk2; + wire gmii_isolate; // internal gmii_isolate signal. + + wire [7:0] gmii_rxd_int; + wire gmii_rx_dv_int; + wire gmii_rx_er_int; + + always @(posedge gmii_clk) begin + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + end + + //---------------------------------------------------------------------------- + // Instantiate core wrapper + //---------------------------------------------------------------------------- + one_gig_eth_pcs_pma_support core_support_i ( + .gtrefclk (gtrefclk), + .gtrefclk_bufg (gtrefclk_bufg), + .txp (txp), + .txn (txn), + .rxp (rxp), + .rxn (rxn), + .mmcm_locked_out (), + .userclk_out (userclk), + .userclk2_out (userclk2), + .rxuserclk_out (), + .rxuserclk2_out (rxuserclk2), + .independent_clock_bufg(independent_clock), + .pma_reset_out (), + .resetdone (resetdone), + .gmii_txd (gmii_txd), + .gmii_tx_en (gmii_tx_en), + .gmii_tx_er (gmii_tx_er), + .gmii_rxd (gmii_rxd_int), + .gmii_rx_dv (gmii_rx_dv_int), + .gmii_rx_er (gmii_rx_er_int), + .gmii_isolate (gmii_isolate), + .mdc (mdc), + .mdio_i (mdio_i), + .mdio_o (mdio_o), + .mdio_t (mdio_t), + .configuration_vector (configuration_vector), + .configuration_valid (configuration_valid), + .status_vector (status_vector), + .reset (reset), + .signal_detect (signal_detect), + .gt0_qplloutclk_out (), + .gt0_qplloutrefclk_out () + ); + + assign gmii_clk = userclk2; + +endmodule // one_gige_phy diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc new file mode 100644 index 000000000..4dadace3b --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy.xdc @@ -0,0 +1,164 @@ + + +#*********************************************************** +# The following constraints target the Transceiver Physical* +# Interface which is instantiated in the Example Design. * +#*********************************************************** +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i] + + +#----------------------------------------------------------- +# Clock source used for the IDELAY Controller (if present) - +# and for the transceiver reset circuitry - +#----------------------------------------------------------- + + +create_clock -name independent_clock -period 5.000 [get_ports independent_clock] + +#----------------------------------------------------------- +# PCS/PMA Clock period Constraints: please do not relax - +#----------------------------------------------------------- + +create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p] + + +#----------------------------------------------------------- +# Transceiver I/O placement: - +#----------------------------------------------------------- + +# Place the transceiver components, chosen for this example design +# *** These values should be modified according to your specific design *** + +#set_property LOC H6 [get_ports gtrefclk_p] +#set_property LOC H5 [get_ports gtrefclk_n] + + +#*********************************************************** +# The following constraints target the GMII implemented in * +# the Example Design. * +#*********************************************************** +# If the GMII is intended to be an internal interface, * +# the GMII signals can be connected directly to user * +# logic and all of the following constraints in this file * +# should be removed. * +# * +# If the GMII is intended to be an external interface, * +# all of the following constraints in this file should be * +# maintained. * +#*********************************************************** + +#----------------------------------------------------------- +# GMII IOSTANDARD Constraints: please select an I/O - +# Standard (LVTTL is suggested). - +#----------------------------------------------------------- + +# Please update the IOSTANDARD according to that available in the device + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[4]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd[7]}] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er] + +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_clk] +#set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_clk] + +#----------------------------------------------------------- +# Lock down the GMII Tx signals to the same bank for low - +# skew. This is an example placement only. - +#----------------------------------------------------------- + + +#----------------------------------------------------------- +# To Adjust GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- +# These constraints will be set at a later date when device speed files have matured + +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en] +#set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er] + +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[7].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[6].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[5].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[4].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[3].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[2].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[1].delay_gmii_txd}] +#set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus[0].delay_gmii_txd}] + + + +#----------------------------------------------------------- +# To check (analyze) GMII Tx Input Setup/Hold Timing - +#----------------------------------------------------------- + +create_clock -name gmii_tx_clk -period 8.000 [get_ports gmii_tx_clk] + + + +#----------------------------------------------------------- +# Fast Skew maximises output setup and hold timing - +#----------------------------------------------------------- +set_property SLEW FAST [get_ports {gmii_rxd[*]}] +set_property SLEW FAST [get_ports gmii_rx_dv] +set_property SLEW FAST [get_ports gmii_rx_er] +set_property SLEW FAST [get_ports gmii_rx_clk] + + +#----------------------------------------------------------- +# GMII Transmitter Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_txd_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_en_IBUF*] +#set_property IOB TRUE [get_cells gmii_tx_er_IBUF*] + +#----------------------------------------------------------- +# GMII Receiver Constraints: place flip-flops in IOB - +#----------------------------------------------------------- +#set_property IOB TRUE [get_cells gmii_rxd_obuf_reg*] +#set_property IOB TRUE [get_cells gmii_rx_dv_obuf_reg] +#set_property IOB TRUE [get_cells gmii_rx_er_obuf_reg] + + + +#----------------------------------------------------------- +# GMII Tx Elastic Buffer Constraints - +#----------------------------------------------------------- + +# Control Gray Code delay and skew across clock boundary +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/data_sync*/D}] +set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/data_sync*/D}] + +# Constrain between Distributed Memory (output data) and the 1st set of flip-flops +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_en_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/tx_er_fifo_reg1*/D}] +set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffer_inst/txd_fifo_reg1*/D}] + +set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }] + +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}] diff --git a/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v new file mode 100644 index 000000000..347a0e550 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/one_gige_phy_clk_gen.v @@ -0,0 +1,29 @@ +// +// Copyright 2014 Ettus Research LLC +// + +module one_gige_phy_clk_gen +( + input refclk_p, + input refclk_n, + output refclk, + output refclk_bufg +); + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG bufg_gtrefclk_inst ( + .I(refclk), + .O(refclk_bufg) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc new file mode 100644 index 000000000..72ddc140d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/pcie_clk_gen/Makefile.inc @@ -0,0 +1,15 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_PCIE_CLK_GEN_SRCS = $(IP_BUILD_DIR)/pcie_clk_gen/pcie_clk_gen.xci + +IP_PCIE_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/pcie_clk_gen/, \ +pcie_clk_gen.xci.out \ +pcie_clk_gen.v \ +) + +$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS) : $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci + $(call BUILD_VIVADO_IP,pcie_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci b/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci new file mode 100644 index 000000000..a36035616 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci @@ -0,0 +1,752 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 800.0 + 100.0 + 0000 + 0000 + 40.000 + 0000 + 0000 + 200.000 + BUFH + 50.0 + false + 40.000 + 0.000 + 50.000 + 40 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFH + 50.0 + false + 200.000 + 0.000 + 50.000 + 200 + 0.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 0.2 + 0.4 + 0.4 + 0.4 + 0.4 + 0.4 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________125.000____________0.100 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 8.000 + 0.000 + FALSE + 8.000 + 10.0 + 25.000 + 0.500 + 0.000 + FALSE + 5 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.100 + 0.010 + FALSE + 2 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1____40.000______0.000______50.0______353.417_____96.948 + CLK_OUT2___200.000______0.000______50.0______192.299_____96.948 + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + CLK_IN1 + PLL + AUTO + 125.000 + 0.100 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + pcie_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 800.0 + 0.100 + 100.0 + 0.010 + BUFH + 1181.857 + false + 265.359 + 50.000 + 40 + 0.000 + 1 + true + BUFH + 440.890 + false + 265.359 + 50.000 + 200 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + pcie_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_AUTO + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 8 + 0.000 + false + 8.000 + 10.0 + 25 + 0.500 + 0.000 + false + 5 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.100 + 0.010 + false + 2 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + CLK_IN1 + PLL + MMCM_ADV + 125.000 + 0.100 + 10.000 + No_buffer + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc b/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc new file mode 100644 index 000000000..f96bc9d7d --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/Makefile.inc @@ -0,0 +1,19 @@ +# +# Copyright 2014 Ettus Research +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_RADIO_CLK_GEN_SRCS = $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xci + +IP_RADIO_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/radio_clk_gen/, \ +radio_clk_gen.xci.out \ +radio_clk_gen.v \ +) + +# We have to patch the XDC file to remove constraints on the source clock for the module +# All timing constraints are handled in one place (timing.xdc) +$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS) : $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci + $(call BUILD_VIVADO_IP,radio_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) + patch $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xdc $(IP_DIR)/radio_clk_gen/radio_clk_gen.xdc.patch + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci new file mode 100644 index 000000000..9c68fcee3 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xci @@ -0,0 +1,755 @@ + + + xilinx.com + xci + unknown + 1.0 + + + radio_clk_gen + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 1 + LEVEL_HIGH + + + + 100000000 + 0 + 0.000 + 0 + 0 + + 100000000 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 50.0 + 100.0 + 0000 + 0000 + 200.000 + 0000 + 0000 + 400.000 + BUFG + 50.0 + false + 200.000 + 0.000 + 50.000 + 200.000 + 0.000 + 1 + 0000 + 0000 + 400.000 + BUFG + 50.0 + false + 400.000 + -45.000 + 50.000 + 400.000 + -45.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 400.000 + 60.000 + 50.000 + 400.000 + 60.000 + 1 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + CLK_IN_SEL + CLK_OUT1 + CLK_OUT2 + CLK_OUT3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + DADDR + DCLK + DEN + DIN + 0000 + 1 + 0.5 + 0.5 + 2.0 + 2.0 + 2.0 + 2.0 + DOUT + DRDY + DWE + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________200.000____________0.010 + no_secondary_input_clock + INPUT_CLK_STOPPED + 0 + Units_MHz + No_Jitter + LOCKED + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 6.000 + 0.000 + FALSE + 5.000 + 10.0 + 6.000 + 0.500 + 0.000 + FALSE + 3 + 0.500 + -45.000 + FALSE + 3 + 0.500 + 60.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + ZHOLD + 1 + None + 0.010 + 0.010 + FALSE + 3 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + CLK_OUT1___200.000______0.000______50.0_______92.799_____82.655 + CLK_OUT2___400.000____-45.000______50.0_______81.254_____82.655 + CLK_OUT3___400.000_____60.000______50.0_______81.254_____82.655 + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + WAVEFORM + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + POWER_DOWN + 0000 + 1 + clk_in1 + MMCM + AUTO + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + 0 + RESET + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + radio_clk_gen + MMCM + false + DONE + cddcdone + cddcreq + CLKFB_IN_N + CLKFB_IN + CLKFB_IN_P + SINGLE + CLKFB_OUT_N + CLKFB_OUT + CLKFB_OUT_P + CLKFB_STOPPED + 50.0 + 0.010 + 100.0 + 0.010 + BUFG + 92.799 + false + 82.655 + 50.000 + 200.000 + 0.000 + 1 + true + BUFG + 81.254 + false + 82.655 + 50.000 + 400.000 + -45.000 + 1 + true + BUFG + 81.254 + false + 82.655 + 50.000 + 400.000 + 60.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + CLK_IN_SEL + CLK_OUT1 + false + CLK_OUT2 + false + CLK_OUT3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + MANUAL + radio_clk_gen + DADDR + DCLK + DEN + Custom + Custom + DIN + DOUT + DRDY + DWE + false + false + false + false + false + false + false + false + false + FDBK_AUTO + INPUT_CLK_STOPPED + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + LOCKED + OPTIMIZED + 6.000 + 0.000 + false + 5.000 + 10.0 + 6.000 + 0.500 + 0.000 + false + 3 + 0.500 + -45.000 + false + 3 + 0.500 + 60.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 1 + None + 0.010 + 0.010 + false + 3 + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + POWER_DOWN + 1 + clk_in1 + MMCM + MMCM_ADV + 200.000 + 0.010 + 10.000 + Differential_clock_capable_pin + PSCLK + PSDONE + PSEN + PSINCDEC + 100.0 + REL_PRIMARY + Custom + RESET + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 3 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch new file mode 100644 index 000000000..d4a0c072f --- /dev/null +++ b/fpga/usrp3/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch @@ -0,0 +1,4 @@ +56,58d55 +< create_clock -period 5.000 [get_ports clk_in1_p] +< set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05 +< diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc new file mode 100644 index 000000000..3c3d99107 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc @@ -0,0 +1,42 @@ +# +# Copyright 2008-2013 Ettus Research LLC +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +TEN_GIGE_PHY_SRCS = \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v \ +$(IP_DIR)/ten_gig_eth_pcs_pma/ten_gige_phy.v \ +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) + +IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma_ex/imports/, \ +ten_gig_eth_pcs_pma_example_design.v \ +ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \ +ten_gig_eth_pcs_pma_gt_common.v \ +ten_gig_eth_pcs_pma_shared_clock_and_reset.v \ +ten_gig_eth_pcs_pma_support.v \ +) + +IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + +IP_TEN_GIG_ETH_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/, \ +ten_gig_eth_pcs_pma.xci.out \ +synth/ten_gig_eth_pcs_pma_block.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_multi_gt.v \ +synth/ten_gig_eth_pcs_pma_cable_pull_logic.v \ +synth/ten_gig_eth_pcs_pma_local_clock_and_reset.v \ +synth/ten_gig_eth_pcs_pma_clocks.xdc \ +synth/ten_gig_eth_pcs_pma_ooc.xdc \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer_rst.v \ +synth/ten_gig_eth_pcs_pma_sim_speedup_controller.v \ +synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \ +synth/ten_gig_eth_pcs_pma.v \ +synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +synth/ten_gig_eth_pcs_pma.xdc \ +) + +$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) + +$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci + $(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci new file mode 100644 index 000000000..453f49cd9 --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci @@ -0,0 +1,192 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ten_gig_eth_pcs_pma + + + 0 + 0 + 0 + 0 + 0 + + + 0 + 0.000 + + + + 0 + 0.000 + + + 100000000 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + 0 + false + 0 + 0 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + + + 0 + 0.000 + false + 0 + 0 + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + 0 + + + + 0 + 0.000 + + + + 0 + 0.000 + + 0 + 0.000 + + + + 0 + 0.000 + 0 + ten_gig_eth_pcs_pma + 100.00 + kintex7 + X0Y0 + 32 + 0 + false + false + true + false + false + false + clk0 + 156 + 10 + ten_gig_eth_pcs_pma_gt + ten_gig_eth_pcs_pma + 100.00 + None + X0Y0 + true + clk0 + 156.25 + 0 + Time_of_day + false + false + false + BASE-R + 64bit + false + false + 10Gig + GTH + kintex7 + + + xc7k410t + ffg900 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 15 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v new file mode 100644 index 000000000..de98ea53a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.v @@ -0,0 +1,249 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy +( + input refclk, + input clk156, + input dclk, + input areset, + input sim_speedup_control, + input [63:0] xgmii_txd, + input [7:0] xgmii_txc, + output reg [63:0] xgmii_rxd, + output reg [7:0] xgmii_rxc, + output txp, + output txn, + input rxp, + input rxn, + input mdc, + input mdio_in, + output reg mdio_out, + output reg mdio_tri, + input [4:0] prtad, + output [7:0] core_status, + output resetdone, + input signal_detect, + input tx_fault, + output tx_disable +); + + reg [63:0] xgmii_txd_reg; + reg [7:0] xgmii_txc_reg; + wire [63:0] xgmii_rxd_int; + wire [7:0] xgmii_rxc_int; + + // Add a pipeline to the xmgii_tx inputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_txd_reg <= xgmii_txd; + xgmii_txc_reg <= xgmii_txc; + end + + // Add a pipeline to the xmgii_rx outputs, to aid timing closure + always @(posedge clk156) + begin + xgmii_rxd <= xgmii_rxd_int; + xgmii_rxc <= xgmii_rxc_int; + end + + wire mdio_out_int; + wire mdio_tri_int; + reg mdc_reg; + reg mdio_in_reg; + + // Add a pipeline to the mdio in/outputs, to aid timing closure + // This is safe because the mdio clock is running so slowly + always @(posedge clk156) + begin + mdio_out <= mdio_out_int; + mdio_tri <= mdio_tri_int; + mdc_reg <= mdc; + mdio_in_reg <= mdio_in; + end + + // Signal declarations + wire txclk322; + wire qplloutclk; + wire qplloutrefclk; + wire qplllock; + + wire drp_gnt; + wire drp_req; + wire drp_den_o; + wire drp_dwe_o; + wire [15:0] drp_daddr_o; + wire [15:0] drp_di_o; + wire drp_drdy_o; + wire [15:0] drp_drpdo_o; + wire drp_den_i; + wire drp_dwe_i; + wire [15:0] drp_daddr_i; + wire [15:0] drp_di_i; + wire drp_drdy_i; + wire [15:0] drp_drpdo_i; + + wire tx_resetdone_int; + wire rx_resetdone_int; + + wire areset_clk156; + wire gttxreset; + wire gtrxreset; + wire qpllreset; + wire qplllock_txusrclk2; + wire gttxreset_txusrclk2; + wire reset_counter_done; + wire txusrclk; + wire txusrclk2; + reg txuserrdy; + + assign resetdone = tx_resetdone_int && rx_resetdone_int; + + // If no arbitration is required on the GT DRP ports then connect REQ to GNT + // and connect other signals i <= o; + assign drp_gnt = drp_req; + assign drp_den_i = drp_den_o; + assign drp_dwe_i = drp_dwe_o; + assign drp_daddr_i = drp_daddr_o; + assign drp_di_i = drp_di_o; + assign drp_drdy_i = drp_drdy_o; + assign drp_drpdo_i = drp_drpdo_o; + + // Instantiate the 10GBASER/KR GT Common block + ten_gig_eth_pcs_pma_gt_common # ( + .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware + ) ten_gig_eth_pcs_pma_gt_common_block ( + .refclk(refclk), + .qpllreset(qpllreset), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk) + ); + + // Asynch reset synchronizers... + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) areset_clk156_sync_i ( + .clk(clk156), + .rst(areset), + .data_in(1'b0), + .data_out(areset_clk156) + ); + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b0) + ) qplllock_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(!qplllock), + .data_in(1'b1), + .data_out(qplllock_txusrclk2) + ); + + reg [7:0] reset_counter = 8'h00; + reg [3:0] reset_pulse = 4'b1110; + assign reset_counter_done = reset_counter[7]; + + // Hold off the GT resets until 500ns after configuration. + // 128 ticks at 6.4ns period will be >> 500 ns. + always @(posedge clk156) + begin + if (!reset_counter[7]) + reset_counter <= reset_counter + 1'b1; + else + reset_counter <= reset_counter; + end + + always @(posedge clk156) + begin + if (areset_clk156 == 1'b1) + reset_pulse <= 4'b1110; + else if(reset_counter[7]) + reset_pulse <= {1'b0, reset_pulse[3:1]}; + end + + assign qpllreset = reset_pulse[0]; + assign gttxreset = reset_pulse[0]; + assign gtrxreset = reset_pulse[0]; + + ten_gig_eth_pcs_pma_ff_synchronizer_rst2 #( + .C_NUM_SYNC_REGS(4), + .C_RVAL(1'b1) + ) gttxreset_txusrclk2_sync_i ( + .clk(txusrclk2), + .rst(gttxreset), + .data_in(1'b0), + .data_out(gttxreset_txusrclk2) + ); + + always @(posedge txusrclk2 or posedge gttxreset_txusrclk2) + begin + if(gttxreset_txusrclk2) + txuserrdy <= 1'b0; + else + txuserrdy <= qplllock_txusrclk2; + end + + BUFG tx322clk_bufg_i ( + .I (txclk322), + .O (txusrclk) + ); + + assign txusrclk2 = txusrclk; + + // Instantiate the 10GBASER/KR Block Level + ten_gig_eth_pcs_pma ten_gig_eth_pcs_pma_i ( + .coreclk(clk156), + .dclk(dclk), + .txusrclk(txusrclk), + .txusrclk2(txusrclk2), + .txoutclk(txclk322), + .areset_coreclk(areset_clk156), + .txuserrdy(txuserrdy), + .areset(areset), + .gttxreset(gttxreset), + .gtrxreset(gtrxreset), + .sim_speedup_control(sim_speedup_control), + .qplllock(qplllock), + .qplloutclk(qplloutclk), + .qplloutrefclk(qplloutrefclk), + .reset_counter_done(reset_counter_done), + .xgmii_txd(xgmii_txd_reg), + .xgmii_txc(xgmii_txc_reg), + .xgmii_rxd(xgmii_rxd_int), + .xgmii_rxc(xgmii_rxc_int), + .txp(txp), + .txn(txn), + .rxp(rxp), + .rxn(rxn), + .mdc(mdc_reg), + .mdio_in(mdio_in_reg), + .mdio_out(mdio_out_int), + .mdio_tri(mdio_tri_int), + .prtad(prtad), + .core_status(core_status), + .tx_resetdone(tx_resetdone_int), + .rx_resetdone(rx_resetdone_int), + .signal_detect(signal_detect), + .tx_fault(tx_fault), + .drp_req(drp_req), + .drp_gnt(drp_gnt), + .drp_den_o(drp_den_o), + .drp_dwe_o(drp_dwe_o), + .drp_daddr_o(drp_daddr_o), + .drp_di_o(drp_di_o), + .drp_drdy_o(drp_drdy_o), + .drp_drpdo_o(drp_drpdo_o), + .drp_den_i(drp_den_i), + .drp_dwe_i(drp_dwe_i), + .drp_daddr_i(drp_daddr_i), + .drp_di_i(drp_di_i), + .drp_drdy_i(drp_drdy_i), + .drp_drpdo_i(drp_drpdo_i), + .pma_pmd_type(3'b101), + .tx_disable(tx_disable) + ); + +endmodule diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc new file mode 100644 index 000000000..c8656e43a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy.xdc @@ -0,0 +1,91 @@ +## (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. + +create_clock -period 6.400 [get_ports {dclk}] + +create_clock -period 6.400 [get_ports refclk_p] + +create_generated_clock -name ddrclock -divide_by 1 -invert -source [get_pins *rx_clk_ddr/C] [get_ports xgmii_rx_clk] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxd*}] +set_output_delay -max 1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] +set_output_delay -min -1.500 -clock [get_clocks ddrclock] [get_ports * -filter {NAME =~ *xgmii_rxc*}] + +# False paths for async reset removal synchronizers +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hierarchical -filter {NAME =~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*sync1_r_reg*}] -filter {NAME =~ *CLR}] + + +## Sample constraint for GT location +#set_property LOC GTXE2_CHANNEL_X0Y18 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_i/*/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i] +#set_property LOC GTXE2_COMMON_X0Y4 [get_cells ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_txd[*]}] + +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxc[*]}] +set_property IOSTANDARD HSTL_I [get_ports {xgmii_rxd[*]}] + +set_property IOB TRUE [get_cells {xgmii_rxc_reg[*]}] +set_property IOB TRUE [get_cells {xgmii_rxd_reg[*]}] + +set_property IOSTANDARD HSTL_I [get_ports xgmii_rx_clk] + + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_out*reg*}] +set_property IOB TRUE [get_cells * -filter {NAME =~ *mdio_tri*reg*}] +################################################################### + +################################################################## +# MDIO-related constraints # +################################################################## +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdc_reg_reg}] +set_property IOB TRUE [get_cells * -hierarchical -filter {NAME =~ mdio_in_reg_reg}] +################################################################### + diff --git a/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v new file mode 100644 index 000000000..27655571a --- /dev/null +++ b/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ten_gige_phy_clk_gen.v @@ -0,0 +1,51 @@ +// +// Copyright 2008-2013 Ettus Research LLC +// + +module ten_gige_phy_clk_gen +( + input areset, + input refclk_p, + input refclk_n, + + output refclk, + output clk156, + output dclk +); + + wire clk156_buf; + wire dclk_buf; + wire clkfbout; + + IBUFDS_GTE2 ibufds_inst ( + .O (refclk), + .ODIV2 (), + .CEB (1'b0), + .I (refclk_p), + .IB (refclk_n) + ); + + BUFG clk156_bufg_inst ( + .I (refclk), + .O (clk156) + ); + + // Divding independent clock by 2 as source for DRP clock + BUFR # ( + .BUFR_DIVIDE ("2") + ) dclk_divide_by_2_buf ( + .I (clk156), + .O (dclk_buf), + .CE (1'b1), + .CLR (1'b0) + ); + + BUFG dclk_bufg_i ( + .I (dclk_buf), + .O (dclk) + ); + +endmodule + + + diff --git a/fpga/usrp3/top/x300/nirio_chdr64_adapter.v b/fpga/usrp3/top/x300/nirio_chdr64_adapter.v new file mode 100644 index 000000000..05976105b --- /dev/null +++ b/fpga/usrp3/top/x300/nirio_chdr64_adapter.v @@ -0,0 +1,106 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: nirio_chdr64_adapter +// +// Description: A transport adapter specific to connecting an NI-RIO streaming +// interface to CHDR. It assumes to be connected to x300_pcie_int. +// See also chdr_xport_adapter_generic. +// +// The tuser inputs/outputs used for routing are the index of the DMA channel. +// Because we have 6 DMA channels on NI-RIO on the X300, these are always 3 +// bits wide. +// +// Parameters: +// - PROTOVER: RFNoC protocol version {8'd, 8'd} +// - MTU: Log2 of the MTU of the packet in 64-bit words +// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table +// - NODE_INST: The node type to return for a node-info discovery +// +// Signals: +// - device_id : The ID of the device that has instantiated this module +// - s_dma_*: The input Ethernet stream from the MAC (plus tuser for source DMA engine ID) +// - m_dma_*: The output Ethernet stream to the MAC (plus tuser for dest DMA engine ID) +// - s_chdr_*: The input CHDR stream from the rfnoc infrastructure +// - m_chdr_*: The output CHDR stream to the rfnoc infrastructure +// + +module nirio_chdr64_adapter #( + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter MTU = 10, + parameter RT_TBL_SIZE = 6, + parameter NODE_INST = 0, + parameter DMA_ID_WIDTH = 3 +)( + // Clocking and reset interface + input wire clk, + input wire rst, + // Device info + input wire [15:0] device_id, + // AXI-Stream interface to/from DMA engines + input wire [63:0] s_dma_tdata, + input wire [DMA_ID_WIDTH-1:0] s_dma_tuser, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [63:0] m_dma_tdata, + output wire [DMA_ID_WIDTH-1:0] m_dma_tuser, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready, + // AXI-Stream interface to/from CHDR infrastructure + input wire [63:0] s_chdr_tdata, + input wire s_chdr_tlast, + input wire s_chdr_tvalid, + output wire s_chdr_tready, + output wire [63:0] m_chdr_tdata, + output wire m_chdr_tlast, + output wire m_chdr_tvalid, + input wire m_chdr_tready +); + + `include "../../lib/rfnoc/core/rfnoc_chdr_utils.vh" + `include "../../lib/rfnoc/core/rfnoc_chdr_internal_utils.vh" + `include "../../lib/rfnoc/xport/rfnoc_xport_types.vh" + + //--------------------------------------- + // CHDR Transport Adapter + //--------------------------------------- + + chdr_xport_adapter_generic #( + .PROTOVER(PROTOVER), .CHDR_W(64), + .USER_W(DMA_ID_WIDTH), .TBL_SIZE(RT_TBL_SIZE), + .NODE_SUBTYPE(NODE_SUBTYPE_XPORT_NIRIO_CHDR64), .NODE_INST(NODE_INST) + ) xport_adapter_gen_i ( + .clk (clk), + .rst (rst), + .device_id (device_id), + .s_axis_xport_tdata (s_dma_tdata), + .s_axis_xport_tuser (s_dma_tuser), + .s_axis_xport_tlast (s_dma_tlast), + .s_axis_xport_tvalid(s_dma_tvalid), + .s_axis_xport_tready(s_dma_tready), + .m_axis_xport_tdata (m_dma_tdata), + .m_axis_xport_tuser (m_dma_tuser), + .m_axis_xport_tlast (m_dma_tlast), + .m_axis_xport_tvalid(m_dma_tvalid), + .m_axis_xport_tready(m_dma_tready), + .s_axis_rfnoc_tdata (s_chdr_tdata), + .s_axis_rfnoc_tlast (s_chdr_tlast), + .s_axis_rfnoc_tvalid(s_chdr_tvalid), + .s_axis_rfnoc_tready(s_chdr_tready), + .m_axis_rfnoc_tdata (m_chdr_tdata), + .m_axis_rfnoc_tlast (m_chdr_tlast), + .m_axis_rfnoc_tvalid(m_chdr_tvalid), + .m_axis_rfnoc_tready(m_chdr_tready), + .ctrlport_req_wr (/* unused */), + .ctrlport_req_rd (/* unused */), + .ctrlport_req_addr (/* unused */), + .ctrlport_req_data (/* unused */), + .ctrlport_resp_ack (/* unused */ 1'b0), + .ctrlport_resp_data (/* unused */ 32'd0) + ); + +endmodule // liberio_chdr64_adapter diff --git a/fpga/usrp3/top/x300/setupenv.sh b/fpga/usrp3/top/x300/setupenv.sh new file mode 100644 index 000000000..829628690 --- /dev/null +++ b/fpga/usrp3/top/x300/setupenv.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +VIVADO_VER=2019.1 +DISPLAY_NAME="USRP-X3x0" +REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) + +declare -A PRODUCT_ID_MAP +PRODUCT_ID_MAP["X300"]="kintex7/xc7k325t/ffg900/-2" +PRODUCT_ID_MAP["X310"]="kintex7/xc7k410t/ffg900/-2" + +source $REPO_BASE_PATH/tools/scripts/setupenv_base.sh diff --git a/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile new file mode 100644 index 000000000..eb135ef4e --- /dev/null +++ b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile @@ -0,0 +1,77 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = kintex7 +PART_ID = xc7k410t/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(RFNOC_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/aurora_64b66b_pcs_pma/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_AURORA_64B66B_PCS_PMA_SRCS) \ +$(IP_AXI64_4K_2CLK_FIFO_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(AURORA_PHY_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs +include $(BASE_DIR)/../sim/control/Makefile.srcs +include $(BASE_DIR)/../sim/axi/Makefile.srcs + +# Define only one toplevel module +SIM_TOP = aurora_loopback_tb +# Simulation runtime in microseconds +SIM_RUNTIME_US = 70 + +SIM_SRCS = \ +$(abspath aurora_loopback_tb.sv) \ +$(SIM_GENERAL_SRCS) \ +$(SIM_CONTROL_SRCS) \ +$(SIM_AXI_SRCS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/x300/sim/aurora_loopback/aurora_loopback_tb.sv b/fpga/usrp3/top/x300/sim/aurora_loopback/aurora_loopback_tb.sv new file mode 100644 index 000000000..75c07dd09 --- /dev/null +++ b/fpga/usrp3/top/x300/sim/aurora_loopback/aurora_loopback_tb.sv @@ -0,0 +1,310 @@ +// +// Copyright 2016 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 13 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +module aurora_loopback_tb(); + `TEST_BENCH_INIT("aurora_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(XG_CLK_P, 1000/156.25, 50) //156.25MHz GT transceiver clock + `DEFINE_RESET(GSR, 0, 100) //100ns for GSR to deassert + + wire XG_CLK_N = ~XG_CLK_P; + wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N; + + localparam PACKET_MODE = 1; + + // Aurora Loopback Topology: + // + // TB Simulus ====> |------------| |----------------| + // | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // TB Checker <==== |------------| |----------------| || Loopback through + // || + // ====> |------------| |----------------| || perfect serial channel + // Loopback | | Aurora MAC | <===> | Aurora PCS/PMA | <====>|| + // <==== |------------| |----------------| + + // Initialize DUT + wire aurora_refclk, aurora_init_clk; + wire m_user_clk, s_user_clk; + wire m_user_rst, s_user_rst; + wire m_channel_up, s_channel_up; + wire m_hard_err, s_hard_err; + wire m_soft_err, s_soft_err; + + aurora_phy_clk_gen aurora_clk_gen_i ( + .areset(GSR), + .refclk_p(XG_CLK_P), + .refclk_n(XG_CLK_N), + .refclk(aurora_refclk), + .clk156(), + .init_clk(aurora_init_clk) + ); + + wire [63:0] m_i_tdata, m_o_tdata; + wire m_i_tvalid, m_i_tready, m_o_tvalid; + wire [63:0] s_i_tdata, s_o_tdata; + wire s_i_tvalid, s_i_tready, s_o_tvalid; + wire [63:0] loop_tdata; + wire loop_tlast, loop_tvalid, loop_tready; + wire [31:0] m_overruns, s_overruns; + wire [31:0] m_soft_errors, s_soft_errors; + reg m_bist_gen, m_bist_check, s_bist_loopback; + reg [5:0] m_bist_rate; + wire m_bist_locked; + wire [47:0] m_bist_samps, m_bist_errors; + + + cvita_master m_tx_chdr (.clk(m_user_clk)); + cvita_slave m_rx_chdr (.clk(s_user_clk)); + + aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_master_i ( + // Resets + .areset(GSR), + // Clocks + .refclk(aurora_refclk), + .user_clk(m_user_clk), + .init_clk(aurora_init_clk), + .user_rst(m_user_rst), + // GTX Serial I/O + .tx_p(SFP_LN0_P), .tx_n(SFP_LN0_N), + .rx_p(SFP_LN1_P), .rx_n(SFP_LN1_N), + // AXI4-Stream TX Interface + .s_axis_tdata(m_i_tdata), .s_axis_tvalid(m_i_tvalid), .s_axis_tready(m_i_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(m_o_tdata), .m_axis_tvalid(m_o_tvalid), + // AXI4-Lite Config Interface + .s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(), + .s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(), + .s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1), + .s_axi_arready(), .s_axi_arvalid(1'b0), + .s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err) + ); + + aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_master_i ( + // Clocks and resets + .phy_clk(m_user_clk), .phy_rst(m_user_rst), + .sys_clk(m_user_clk), .sys_rst(m_user_rst), + .clear(1'b0), + // PHY Interface + .phy_s_axis_tdata(m_o_tdata), .phy_s_axis_tvalid(m_o_tvalid), + .phy_m_axis_tdata(m_i_tdata), .phy_m_axis_tvalid(m_i_tvalid), .phy_m_axis_tready(m_i_tready), + // User Interface + .s_axis_tdata(m_tx_chdr.axis.tdata), .s_axis_tlast(m_tx_chdr.axis.tlast), + .s_axis_tvalid(m_tx_chdr.axis.tvalid), .s_axis_tready(m_tx_chdr.axis.tready), + .m_axis_tdata(m_rx_chdr.axis.tdata), .m_axis_tlast(m_rx_chdr.axis.tlast), + .m_axis_tvalid(m_rx_chdr.axis.tvalid), .m_axis_tready(m_rx_chdr.axis.tready), + // Misc PHY + .channel_up(m_channel_up), .hard_err(m_hard_err), .soft_err(m_soft_err), + .overruns(m_overruns), .soft_errors(m_soft_errors), + //BIST + .bist_gen_en(m_bist_gen), .bist_checker_en(m_bist_check), .bist_loopback_en(1'b0), .bist_gen_rate(m_bist_rate), + .bist_checker_locked(m_bist_locked), .bist_checker_samps(m_bist_samps), .bist_checker_errors(m_bist_errors) + ); + + aurora_phy_x1 #(.SIMULATION(1)) aurora_phy_slave_i ( + // Resets + .areset(GSR), + // Clocks + .refclk(aurora_refclk), + .user_clk(s_user_clk), + .init_clk(aurora_init_clk), + .user_rst(s_user_rst), + // GTX Serial I/O + .tx_p(SFP_LN1_P), .tx_n(SFP_LN1_N), + .rx_p(SFP_LN0_P), .rx_n(SFP_LN0_N), + // AXI4-Stream TX Interface + .s_axis_tdata(s_i_tdata), .s_axis_tvalid(s_i_tvalid), .s_axis_tready(s_i_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(s_o_tdata), .m_axis_tvalid(s_o_tvalid), + // AXI4-Lite Config Interface + // AXI4-Lite Config Interface + .s_axi_awaddr(32'h0), .s_axi_araddr(32'h0), .s_axi_awvalid(1'b0), .s_axi_awready(), + .s_axi_wdata(32'h0), .s_axi_wvalid(1'b0), .s_axi_wstrb(1'b0), .s_axi_wready(), + .s_axi_bvalid(), .s_axi_bresp(), .s_axi_bready(1'b1), + .s_axi_arready(), .s_axi_arvalid(1'b0), + .s_axi_rdata(), .s_axi_rvalid(), .s_axi_rresp(), .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(s_channel_up), .hard_err(s_hard_err), .soft_err(s_soft_err) + ); + + aurora_axis_mac #(.PACKET_MODE(PACKET_MODE), .BIST_ENABLED(1)) aurora_mac_slave_i ( + // Clocks and resets + .phy_clk(s_user_clk), .phy_rst(s_user_rst), + .sys_clk(s_user_clk), .sys_rst(s_user_rst), + .clear(1'b0), + // PHY Interface + .phy_s_axis_tdata(s_o_tdata), .phy_s_axis_tvalid(s_o_tvalid), + .phy_m_axis_tdata(s_i_tdata), .phy_m_axis_tvalid(s_i_tvalid), .phy_m_axis_tready(s_i_tready), + // User Interface + .s_axis_tdata(loop_tdata), .s_axis_tlast(loop_tlast), + .s_axis_tvalid(~s_bist_loopback & loop_tvalid), .s_axis_tready(loop_tready), + .m_axis_tdata(loop_tdata), .m_axis_tlast(loop_tlast), + .m_axis_tvalid(loop_tvalid), .m_axis_tready(~s_bist_loopback & loop_tready), + // Misc PHY + .channel_up(s_channel_up), .hard_err(s_hard_err), .soft_err(s_soft_err), + .overruns(s_overruns), .soft_errors(s_soft_errors), + //BIST + .bist_gen_en(1'b0), .bist_checker_en(1'b0), .bist_loopback_en(s_bist_loopback), .bist_gen_rate(6'd0), + .bist_checker_locked(), .bist_checker_samps(), .bist_checker_errors() + ); + + //Testbench variables + cvita_hdr_t header, header_out; + cvita_stats_t stats; + logic [63:0] crc_cache; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + `TEST_CASE_START("Wait for reset"); + while (GSR) @(posedge XG_CLK_P); + `TEST_CASE_DONE((~GSR)); + + m_bist_gen <= 1'b0; + m_bist_rate <= 6'd0; + m_bist_check <= 1'b0; + s_bist_loopback <= 1'b0; + + m_tx_chdr.push_bubble(); + + `TEST_CASE_START("Wait for master channel to come up"); + while (m_channel_up !== 1'b1) @(posedge m_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Wait for slave channel to come up"); + while (s_channel_up !== 1'b1) @(posedge s_user_clk); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Run PRBS BIST"); + s_bist_loopback <= PACKET_MODE; + @(posedge m_user_clk); + m_bist_rate <= 6'd60; + m_bist_gen <= 1'b1; + m_bist_check <= 1'b1; + @(posedge m_user_clk); + while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + repeat (512) @(posedge m_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge m_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge m_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==16, "Bad packet: Length mismatch"); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{header_out.src_sid,header_out.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={header_out.src_sid,header_out.dst_sid}, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + m_rx_chdr.axis.tready = 0; + m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header); + m_rx_chdr.axis.tready = 1; + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==256, "Bad packet: Length mismatch"); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{header_out.src_sid,header_out.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={header_out.src_sid,header_out.dst_sid}, s); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + repeat (10) @(posedge m_user_clk); //Wait for clear to go low + m_rx_chdr.axis.tready = 1; + fork + begin + m_tx_chdr.push_ramp_pkt(200, 64'd0, 64'h100, header); + end + begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + end + join + crc_cache = stats.crc; //Cache CRC for future test cases + `ASSERT_ERROR(stats.count==200, "Bad packet: Length mismatch"); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + m_rx_chdr.axis.tready = 1; + fork + begin + repeat (20) begin + m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header); + m_tx_chdr.push_bubble(); + end + end + begin + repeat (20) begin + m_rx_chdr.wait_for_pkt_get_info(header_out, stats); + `ASSERT_ERROR(stats.count==20, "Bad packet: Length mismatch"); + `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC"); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + `TEST_CASE_DONE((s_overruns === 32'd0)); + + s_bist_loopback <= 1'b1; + + `TEST_CASE_START("Run PRBS BIST (Loopback Mode)"); + @(posedge m_user_clk); + m_bist_gen <= 1'b1; + m_bist_rate <= 6'd60; + m_bist_check <= 1'b1; + @(posedge m_user_clk); + while (m_bist_locked !== 1'b1) @(posedge m_user_clk); + repeat (512) @(posedge m_user_clk); + `ASSERT_ERROR(m_bist_samps>256, "BIST: Num samples incorrect"); + `ASSERT_ERROR(m_bist_errors===36'd0, "BIST: Errors!"); + @(posedge m_user_clk); + m_bist_gen <= 1'b0; + repeat (256) @(posedge m_user_clk); + m_bist_check <= 1'b0; + `TEST_CASE_DONE(1'b1); + + s_bist_loopback <= 1'b0; + + `TEST_CASE_START("Validate no drops (master)"); + `TEST_CASE_DONE((m_overruns === 32'd0)); + + `TEST_CASE_START("Validate no drops (slave)"); + `TEST_CASE_DONE((s_overruns === 32'd0)); + + `TEST_BENCH_DONE; + end + +endmodule diff --git a/fpga/usrp3/top/x300/sim/dram_fifo/Makefile b/fpga/usrp3/top/x300/sim/dram_fifo/Makefile new file mode 100644 index 000000000..8cc56331c --- /dev/null +++ b/fpga/usrp3/top/x300/sim/dram_fifo/Makefile @@ -0,0 +1,72 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = kintex7 +PART_ID = xc7k410t/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/axi4_dualport_sram/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_2X64_128_SRCS) \ +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI4_BRAM_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_tb + +SIM_SRCS = \ +$(abspath dram_fifo_tb.sv) \ +$(abspath axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/x300/sim/dram_fifo/axis_dram_fifo_single.sv b/fpga/usrp3/top/x300/sim/dram_fifo/axis_dram_fifo_single.sv new file mode 100644 index 000000000..d4aae6dd0 --- /dev/null +++ b/fpga/usrp3/top/x300/sim/dram_fifo/axis_dram_fifo_single.sv @@ -0,0 +1,589 @@ +// +// Copyright 2015 Ettus Research LLC +// + +`timescale 1ns/1ps + +module axis_dram_fifo_single +#( + parameter USE_SRAM_MEMORY = 0, + parameter USE_BD_INTERCON = 0, + parameter SR_BASE = 0 +) ( + input bus_clk, + input bus_rst, + input sys_clk, + input sys_rst, + + input [63:0] i_tdata, + input i_tlast, + input i_tvalid, + output i_tready, + + output [63:0] o_tdata, + output o_tlast, + output o_tvalid, + input o_tready, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + output [31:0] rb_data, + + input [63:0] forced_bit_err, + + output init_calib_complete +); + + // Misc declarations + axi4_rd_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_rd(.clk(sys_clk)); + axi4_wr_t #(.DWIDTH(64), .AWIDTH(32), .IDWIDTH(1)) dma_axi_wr(.clk(sys_clk)); + axi4_rd_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_rd(.clk(sys_clk)); + axi4_wr_t #(.DWIDTH(256), .AWIDTH(32), .IDWIDTH(1)) mig_axi_wr(.clk(sys_clk)); + + wire [31:0] ddr3_dq; // Data pins. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_n; // Data Strobes. Input for Reads; Output for Writes. + wire [3:0] ddr3_dqs_p; + wire [14:0] ddr3_addr; // Address + wire [2:0] ddr3_ba; // Bank Address + wire ddr3_ras_n; // Row Address Strobe. + wire ddr3_cas_n; // Column address select + wire ddr3_we_n; // Write Enable + wire ddr3_reset_n; // SDRAM reset pin. + wire [0:0] ddr3_ck_p; // Differential clock + wire [0:0] ddr3_ck_n; + wire [0:0] ddr3_cke; // Clock Enable + wire [0:0] ddr3_cs_n; // Chip Select + wire [3:0] ddr3_dm; // Data Mask [3] = UDM.U26; [2] = LDM.U26; ... + wire [0:0] ddr3_odt; // On-Die termination enable. + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (250MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + reg ddr3_axi_rst_reg_n; // Synchronized to ddr_sys_clk + wire ddr3_axi_clk_x2; + + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + axi_dma_fifo #( + .DEFAULT_BASE(30'h00010000), + .DEFAULT_MASK(30'hFFFF0000), + .DEFAULT_TIMEOUT(280), + .SR_BASE(SR_BASE), + .EXT_BIST(1), + .SIMULATION(1) + ) axi_dma_fifo_i0 ( + // + // Clocks and reset + .bus_clk (bus_clk), + .bus_reset (bus_rst), + .dram_clk (ddr3_axi_clk_x2), + .dram_reset (ddr3_axi_rst), + // + // AXI Write address channel + .m_axi_awid (dma_axi_wr.addr.id), + .m_axi_awaddr (dma_axi_wr.addr.addr), + .m_axi_awlen (dma_axi_wr.addr.len), + .m_axi_awsize (dma_axi_wr.addr.size), + .m_axi_awburst (dma_axi_wr.addr.burst), + .m_axi_awlock (dma_axi_wr.addr.lock), + .m_axi_awcache (dma_axi_wr.addr.cache), + .m_axi_awprot (dma_axi_wr.addr.prot), + .m_axi_awqos (dma_axi_wr.addr.qos), + .m_axi_awregion (dma_axi_wr.addr.region), + .m_axi_awuser (dma_axi_wr.addr.user), + .m_axi_awvalid (dma_axi_wr.addr.valid), + .m_axi_awready (dma_axi_wr.addr.ready), + // + // AXI Write data channel. + .m_axi_wdata (dma_axi_wr.data.data), + .m_axi_wstrb (dma_axi_wr.data.strb), + .m_axi_wlast (dma_axi_wr.data.last), + .m_axi_wuser (dma_axi_wr.data.user), + .m_axi_wvalid (dma_axi_wr.data.valid), + .m_axi_wready (dma_axi_wr.data.ready), + // + // AXI Write response channel signals + .m_axi_bid (dma_axi_wr.resp.id), + .m_axi_bresp (dma_axi_wr.resp.resp), + .m_axi_buser (dma_axi_wr.resp.user), + .m_axi_bvalid (dma_axi_wr.resp.valid), + .m_axi_bready (dma_axi_wr.resp.ready), + // + // AXI Read address channel + .m_axi_arid (dma_axi_rd.addr.id), + .m_axi_araddr (dma_axi_rd.addr.addr), + .m_axi_arlen (dma_axi_rd.addr.len), + .m_axi_arsize (dma_axi_rd.addr.size), + .m_axi_arburst (dma_axi_rd.addr.burst), + .m_axi_arlock (dma_axi_rd.addr.lock), + .m_axi_arcache (dma_axi_rd.addr.cache), + .m_axi_arprot (dma_axi_rd.addr.prot), + .m_axi_arqos (dma_axi_rd.addr.qos), + .m_axi_arregion (dma_axi_rd.addr.region), + .m_axi_aruser (dma_axi_rd.addr.user), + .m_axi_arvalid (dma_axi_rd.addr.valid), + .m_axi_arready (dma_axi_rd.addr.ready), + // + // AXI Read data channel + .m_axi_rid (dma_axi_rd.data.id), + .m_axi_rdata (dma_axi_rd.data.data), + .m_axi_rresp (dma_axi_rd.data.resp), + .m_axi_rlast (dma_axi_rd.data.last), + .m_axi_ruser (dma_axi_rd.data.user), + .m_axi_rvalid (dma_axi_rd.data.valid), + .m_axi_rready (dma_axi_rd.data.ready), + // + // CHDR friendly AXI stream input + .i_tdata (i_tdata), + .i_tlast (i_tlast), + .i_tvalid (i_tvalid), + .i_tready (i_tready), + // + // CHDR friendly AXI Stream output + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .o_tready (o_tready), + // + // Settings + .set_stb (set_stb), + .set_addr (set_addr), + .set_data (set_data), + .rb_data (rb_data), + + .debug() + ); + + generate if (USE_SRAM_MEMORY) begin + assign init_calib_complete = 1; + assign ddr3_axi_clk = bus_clk; + assign ddr3_axi_clk_x2 = bus_clk; + assign ddr3_axi_rst = bus_rst; + + axi4_dualport_sram axi4_dualport_sram_i1 ( + .s_aclk (ddr3_axi_clk_x2), // input s_aclk + .s_aresetn (~ddr3_axi_rst), // input s_aresetn + .s_axi_awid (dma_axi_wr.addr.id), // input [0 : 0] s_axi_awid + .s_axi_awaddr (dma_axi_wr.addr.addr), // input [31 : 0] s_axi_awaddr + .s_axi_awlen (dma_axi_wr.addr.len), // input [7 : 0] s_axi_awlen + .s_axi_awsize (dma_axi_wr.addr.size), // input [2 : 0] s_axi_awsize + .s_axi_awburst (dma_axi_wr.addr.burst), // input [1 : 0] s_axi_awburst + .s_axi_awvalid (dma_axi_wr.addr.valid), // input s_axi_awvalid + .s_axi_awready (dma_axi_wr.addr.ready), // output s_axi_awready + .s_axi_wdata (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] s_axi_wdata + .s_axi_wstrb (dma_axi_wr.data.strb), // input [7 : 0] s_axi_wstrb + .s_axi_wlast (dma_axi_wr.data.last), // input s_axi_wlast + .s_axi_wvalid (dma_axi_wr.data.valid), // input s_axi_wvalid + .s_axi_wready (dma_axi_wr.data.ready), // output s_axi_wready + .s_axi_bid (dma_axi_wr.resp.id), // output [0 : 0] s_axi_bid + .s_axi_bresp (dma_axi_wr.resp.resp), // output [1 : 0] s_axi_bresp + .s_axi_bvalid (dma_axi_wr.resp.valid), // output s_axi_bvalid + .s_axi_bready (dma_axi_wr.resp.ready), // input s_axi_bready + .s_axi_arid (dma_axi_rd.addr.id), // input [0 : 0] s_axi_arid + .s_axi_araddr (dma_axi_rd.addr.addr), // input [31 : 0] s_axi_araddr + .s_axi_arlen (dma_axi_rd.addr.len), // input [7 : 0] s_axi_arlen + .s_axi_arsize (dma_axi_rd.addr.size), // input [2 : 0] s_axi_arsize + .s_axi_arburst (dma_axi_rd.addr.burst), // input [1 : 0] s_axi_arburst + .s_axi_arvalid (dma_axi_rd.addr.valid), // input s_axi_arvalid + .s_axi_arready (dma_axi_rd.addr.ready), // output s_axi_arready + .s_axi_rid (dma_axi_rd.data.id), // output [0 : 0] s_axi_rid + .s_axi_rdata (dma_axi_rd.data.data), // output [63 : 0] s_axi_rdata + .s_axi_rresp (dma_axi_rd.data.resp), // output [1 : 0] s_axi_rresp + .s_axi_rlast (dma_axi_rd.data.last), // output s_axi_rlast + .s_axi_rvalid (dma_axi_rd.data.valid), // output s_axi_rvalid + .s_axi_rready (dma_axi_rd.data.ready) // input s_axi_rready + ); + + end else begin //generate if (USE_SRAM_MEMORY) begin + //--------------------------------------------------- + // We use an interconnect to connect to FIFOs. + //--------------------------------------------------- + if (USE_BD_INTERCON) begin + // Vivado Block Diagram interconnect. + axi_intercon_2x64_128_bd_wrapper axi_intercon_2x64_128_i ( + .S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK + .S00_AXI_ARESETN (~ddr3_axi_rst), // input S00_AXI_ARESETN + .S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID + .S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR + .S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN + .S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE + .S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST + .S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK + .S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE + .S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT + .S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS + .S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID + .S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY + .S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA + .S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB + .S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST + .S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID + .S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY + .S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID + .S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP + .S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID + .S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY + .S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID + .S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR + .S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN + .S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE + .S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST + .S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK + .S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE + .S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT + .S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS + .S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID + .S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY + .S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID + .S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA + .S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP + .S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST + .S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID + .S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY + // + //.S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N + .S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK + .S01_AXI_ARESETN (~ddr3_axi_rst), // input S01_AXI_ARESETN + .S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S01_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S01_AXI_AWREADY (), // output S01_AXI_AWREADY + .S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S01_AXI_WLAST (0), // input S01_AXI_WLAST + .S01_AXI_WVALID (0), // input S01_AXI_WVALID + .S01_AXI_WREADY (), // output S01_AXI_WREADY + .S01_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S01_AXI_BVALID (), // output S01_AXI_BVALID + .S01_AXI_BREADY (0), // input S01_AXI_BREADY + .S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S01_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S01_AXI_ARREADY (), // output S01_AXI_ARREADY + .S01_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S01_AXI_RLAST (), // output S01_AXI_RLAST + .S01_AXI_RVALID (), // output S01_AXI_RVALID + .S01_AXI_RREADY (0), // input S01_AXI_RREADY + // + //.M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N + .M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK + .M00_AXI_ARESETN (~ddr3_axi_rst), // input M00_AXI_ARESETN + .M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID + .M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR + .M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN + .M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE + .M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST + .M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK + .M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE + .M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT + .M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS + .M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID + .M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY + .M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA + .M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB + .M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST + .M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID + .M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY + .M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID + .M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP + .M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID + .M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY + .M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID + .M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR + .M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN + .M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE + .M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST + .M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK + .M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE + .M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT + .M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS + .M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID + .M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY + .M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID + .M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA + .M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP + .M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST + .M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID + .M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY + ); + end else begin + //Original IP interconnect + axi_intercon_2x64_128 axi_intercon_2x64_128_i ( + .INTERCONNECT_ACLK(ddr3_axi_clk_x2), // input INTERCONNECT_ACLK + .INTERCONNECT_ARESETN(~ddr3_axi_rst), // input INTERCONNECT_ARESETN + // + .S00_AXI_ARESET_OUT_N (), // output S00_AXI_ARESET_OUT_N + .S00_AXI_ACLK (ddr3_axi_clk_x2), // input S00_AXI_ACLK + .S00_AXI_AWID (dma_axi_wr.addr.id), // input [0 : 0] S00_AXI_AWID + .S00_AXI_AWADDR (dma_axi_wr.addr.addr), // input [31 : 0] S00_AXI_AWADDR + .S00_AXI_AWLEN (dma_axi_wr.addr.len), // input [7 : 0] S00_AXI_AWLEN + .S00_AXI_AWSIZE (dma_axi_wr.addr.size), // input [2 : 0] S00_AXI_AWSIZE + .S00_AXI_AWBURST (dma_axi_wr.addr.burst), // input [1 : 0] S00_AXI_AWBURST + .S00_AXI_AWLOCK (dma_axi_wr.addr.lock), // input S00_AXI_AWLOCK + .S00_AXI_AWCACHE (dma_axi_wr.addr.cache), // input [3 : 0] S00_AXI_AWCACHE + .S00_AXI_AWPROT (dma_axi_wr.addr.prot), // input [2 : 0] S00_AXI_AWPROT + .S00_AXI_AWQOS (dma_axi_wr.addr.qos), // input [3 : 0] S00_AXI_AWQOS + .S00_AXI_AWVALID (dma_axi_wr.addr.valid), // input S00_AXI_AWVALID + .S00_AXI_AWREADY (dma_axi_wr.addr.ready), // output S00_AXI_AWREADY + .S00_AXI_WDATA (dma_axi_wr.data.data ^ forced_bit_err), // input [63 : 0] S00_AXI_WDATA + .S00_AXI_WSTRB (dma_axi_wr.data.strb), // input [7 : 0] S00_AXI_WSTRB + .S00_AXI_WLAST (dma_axi_wr.data.last), // input S00_AXI_WLAST + .S00_AXI_WVALID (dma_axi_wr.data.valid), // input S00_AXI_WVALID + .S00_AXI_WREADY (dma_axi_wr.data.ready), // output S00_AXI_WREADY + .S00_AXI_BID (dma_axi_wr.resp.id), // output [0 : 0] S00_AXI_BID + .S00_AXI_BRESP (dma_axi_wr.resp.resp), // output [1 : 0] S00_AXI_BRESP + .S00_AXI_BVALID (dma_axi_wr.resp.valid), // output S00_AXI_BVALID + .S00_AXI_BREADY (dma_axi_wr.resp.ready), // input S00_AXI_BREADY + .S00_AXI_ARID (dma_axi_rd.addr.id), // input [0 : 0] S00_AXI_ARID + .S00_AXI_ARADDR (dma_axi_rd.addr.addr), // input [31 : 0] S00_AXI_ARADDR + .S00_AXI_ARLEN (dma_axi_rd.addr.len), // input [7 : 0] S00_AXI_ARLEN + .S00_AXI_ARSIZE (dma_axi_rd.addr.size), // input [2 : 0] S00_AXI_ARSIZE + .S00_AXI_ARBURST (dma_axi_rd.addr.burst), // input [1 : 0] S00_AXI_ARBURST + .S00_AXI_ARLOCK (dma_axi_rd.addr.lock), // input S00_AXI_ARLOCK + .S00_AXI_ARCACHE (dma_axi_rd.addr.cache), // input [3 : 0] S00_AXI_ARCACHE + .S00_AXI_ARPROT (dma_axi_rd.addr.prot), // input [2 : 0] S00_AXI_ARPROT + .S00_AXI_ARQOS (dma_axi_rd.addr.qos), // input [3 : 0] S00_AXI_ARQOS + .S00_AXI_ARVALID (dma_axi_rd.addr.valid), // input S00_AXI_ARVALID + .S00_AXI_ARREADY (dma_axi_rd.addr.ready), // output S00_AXI_ARREADY + .S00_AXI_RID (dma_axi_rd.data.id), // output [0 : 0] S00_AXI_RID + .S00_AXI_RDATA (dma_axi_rd.data.data), // output [63 : 0] S00_AXI_RDATA + .S00_AXI_RRESP (dma_axi_rd.data.resp), // output [1 : 0] S00_AXI_RRESP + .S00_AXI_RLAST (dma_axi_rd.data.last), // output S00_AXI_RLAST + .S00_AXI_RVALID (dma_axi_rd.data.valid), // output S00_AXI_RVALID + .S00_AXI_RREADY (dma_axi_rd.data.ready), // input S00_AXI_RREADY + // + .S01_AXI_ARESET_OUT_N (), // output S01_AXI_ARESET_OUT_N + .S01_AXI_ACLK (ddr3_axi_clk_x2), // input S01_AXI_ACLK + .S01_AXI_AWID (0), // input [0 : 0] S01_AXI_AWID + .S01_AXI_AWADDR (0), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWLEN (0), // input [7 : 0] S01_AXI_AWLEN + .S01_AXI_AWSIZE (0), // input [2 : 0] S01_AXI_AWSIZE + .S01_AXI_AWBURST (0), // input [1 : 0] S01_AXI_AWBURST + .S01_AXI_AWLOCK (0), // input S01_AXI_AWLOCK + .S01_AXI_AWCACHE (0), // input [3 : 0] S01_AXI_AWCACHE + .S01_AXI_AWPROT (0), // input [2 : 0] S01_AXI_AWPROT + .S01_AXI_AWQOS (0), // input [3 : 0] S01_AXI_AWQOS + .S01_AXI_AWVALID (0), // input S01_AXI_AWVALID + .S01_AXI_AWREADY (), // output S01_AXI_AWREADY + .S01_AXI_WDATA (0), // input [63 : 0] S01_AXI_WDATA + .S01_AXI_WSTRB (0), // input [7 : 0] S01_AXI_WSTRB + .S01_AXI_WLAST (0), // input S01_AXI_WLAST + .S01_AXI_WVALID (0), // input S01_AXI_WVALID + .S01_AXI_WREADY (), // output S01_AXI_WREADY + .S01_AXI_BID (), // output [0 : 0] S01_AXI_BID + .S01_AXI_BRESP (), // output [1 : 0] S01_AXI_BRESP + .S01_AXI_BVALID (), // output S01_AXI_BVALID + .S01_AXI_BREADY (0), // input S01_AXI_BREADY + .S01_AXI_ARID (0), // input [0 : 0] S01_AXI_ARID + .S01_AXI_ARADDR (0), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARLEN (0), // input [7 : 0] S01_AXI_ARLEN + .S01_AXI_ARSIZE (0), // input [2 : 0] S01_AXI_ARSIZE + .S01_AXI_ARBURST (0), // input [1 : 0] S01_AXI_ARBURST + .S01_AXI_ARLOCK (0), // input S01_AXI_ARLOCK + .S01_AXI_ARCACHE (0), // input [3 : 0] S01_AXI_ARCACHE + .S01_AXI_ARPROT (0), // input [2 : 0] S01_AXI_ARPROT + .S01_AXI_ARQOS (0), // input [3 : 0] S01_AXI_ARQOS + .S01_AXI_ARVALID (0), // input S01_AXI_ARVALID + .S01_AXI_ARREADY (), // output S01_AXI_ARREADY + .S01_AXI_RID (), // output [0 : 0] S01_AXI_RID + .S01_AXI_RDATA (), // output [63 : 0] S01_AXI_RDATA + .S01_AXI_RRESP (), // output [1 : 0] S01_AXI_RRESP + .S01_AXI_RLAST (), // output S01_AXI_RLAST + .S01_AXI_RVALID (), // output S01_AXI_RVALID + .S01_AXI_RREADY (0), // input S01_AXI_RREADY + // + .M00_AXI_ARESET_OUT_N (), // output M00_AXI_ARESET_OUT_N + .M00_AXI_ACLK (ddr3_axi_clk), // input M00_AXI_ACLK + .M00_AXI_AWID (mig_axi_wr.addr.id), // output [3 : 0] M00_AXI_AWID + .M00_AXI_AWADDR (mig_axi_wr.addr.addr), // output [31 : 0] M00_AXI_AWADDR + .M00_AXI_AWLEN (mig_axi_wr.addr.len), // output [7 : 0] M00_AXI_AWLEN + .M00_AXI_AWSIZE (mig_axi_wr.addr.size), // output [2 : 0] M00_AXI_AWSIZE + .M00_AXI_AWBURST (mig_axi_wr.addr.burst), // output [1 : 0] M00_AXI_AWBURST + .M00_AXI_AWLOCK (mig_axi_wr.addr.lock), // output M00_AXI_AWLOCK + .M00_AXI_AWCACHE (mig_axi_wr.addr.cache), // output [3 : 0] M00_AXI_AWCACHE + .M00_AXI_AWPROT (mig_axi_wr.addr.prot), // output [2 : 0] M00_AXI_AWPROT + .M00_AXI_AWQOS (mig_axi_wr.addr.qos), // output [3 : 0] M00_AXI_AWQOS + .M00_AXI_AWVALID (mig_axi_wr.addr.valid), // output M00_AXI_AWVALID + .M00_AXI_AWREADY (mig_axi_wr.addr.ready), // input M00_AXI_AWREADY + .M00_AXI_WDATA (mig_axi_wr.data.data), // output [127 : 0] M00_AXI_WDATA + .M00_AXI_WSTRB (mig_axi_wr.data.strb), // output [15 : 0] M00_AXI_WSTRB + .M00_AXI_WLAST (mig_axi_wr.data.last), // output M00_AXI_WLAST + .M00_AXI_WVALID (mig_axi_wr.data.valid), // output M00_AXI_WVALID + .M00_AXI_WREADY (mig_axi_wr.data.ready), // input M00_AXI_WREADY + .M00_AXI_BID (mig_axi_wr.resp.id), // input [3 : 0] M00_AXI_BID + .M00_AXI_BRESP (mig_axi_wr.resp.resp), // input [1 : 0] M00_AXI_BRESP + .M00_AXI_BVALID (mig_axi_wr.resp.valid), // input M00_AXI_BVALID + .M00_AXI_BREADY (mig_axi_wr.resp.ready), // output M00_AXI_BREADY + .M00_AXI_ARID (mig_axi_rd.addr.id), // output [3 : 0] M00_AXI_ARID + .M00_AXI_ARADDR (mig_axi_rd.addr.addr), // output [31 : 0] M00_AXI_ARADDR + .M00_AXI_ARLEN (mig_axi_rd.addr.len), // output [7 : 0] M00_AXI_ARLEN + .M00_AXI_ARSIZE (mig_axi_rd.addr.size), // output [2 : 0] M00_AXI_ARSIZE + .M00_AXI_ARBURST (mig_axi_rd.addr.burst), // output [1 : 0] M00_AXI_ARBURST + .M00_AXI_ARLOCK (mig_axi_rd.addr.lock), // output M00_AXI_ARLOCK + .M00_AXI_ARCACHE (mig_axi_rd.addr.cache), // output [3 : 0] M00_AXI_ARCACHE + .M00_AXI_ARPROT (mig_axi_rd.addr.prot), // output [2 : 0] M00_AXI_ARPROT + .M00_AXI_ARQOS (mig_axi_rd.addr.qos), // output [3 : 0] M00_AXI_ARQOS + .M00_AXI_ARVALID (mig_axi_rd.addr.valid), // output M00_AXI_ARVALID + .M00_AXI_ARREADY (mig_axi_rd.addr.ready), // input M00_AXI_ARREADY + .M00_AXI_RID (mig_axi_rd.data.id), // input [3 : 0] M00_AXI_RID + .M00_AXI_RDATA (mig_axi_rd.data.data), // input [127 : 0] M00_AXI_RDATA + .M00_AXI_RRESP (mig_axi_rd.data.resp), // input [1 : 0] M00_AXI_RRESP + .M00_AXI_RLAST (mig_axi_rd.data.last), // input M00_AXI_RLAST + .M00_AXI_RVALID (mig_axi_rd.data.valid), // input M00_AXI_RVALID + .M00_AXI_RREADY (mig_axi_rd.data.ready) // output M00_AXI_RREADY + ); + end + + //--------------------------------------------------- + // MIG + //--------------------------------------------------- + wire ddr3_idelay_refclk; + + ddr3_32bit ddr_mig_i ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .init_calib_complete (init_calib_complete), + + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 150MHz clock out + .ui_addn_clk_0 (ddr3_axi_clk_x2), // 300MHz clock out + .ui_addn_clk_1 (ddr3_idelay_refclk), + .ui_addn_clk_2 (), + .ui_addn_clk_3 (), + .ui_addn_clk_4 (), + .clk_ref_i (ddr3_idelay_refclk), + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + .device_temp_i (12'd0), + // Slave Interface Write Address Ports + .s_axi_awid (mig_axi_wr.addr.id), + .s_axi_awaddr (mig_axi_wr.addr.addr), + .s_axi_awlen (mig_axi_wr.addr.len), + .s_axi_awsize (mig_axi_wr.addr.size), + .s_axi_awburst (mig_axi_wr.addr.burst), + .s_axi_awlock (mig_axi_wr.addr.lock), + .s_axi_awcache (mig_axi_wr.addr.cache), + .s_axi_awprot (mig_axi_wr.addr.prot), + .s_axi_awqos (mig_axi_wr.addr.qos), + .s_axi_awvalid (mig_axi_wr.addr.valid), + .s_axi_awready (mig_axi_wr.addr.ready), + // Slave Interface Write Data Ports + .s_axi_wdata (mig_axi_wr.data.data), + .s_axi_wstrb (mig_axi_wr.data.strb), + .s_axi_wlast (mig_axi_wr.data.last), + .s_axi_wvalid (mig_axi_wr.data.valid), + .s_axi_wready (mig_axi_wr.data.ready), + // Slave Interface Write Response Ports + .s_axi_bid (mig_axi_wr.resp.id), + .s_axi_bresp (mig_axi_wr.resp.resp), + .s_axi_bvalid (mig_axi_wr.resp.valid), + .s_axi_bready (mig_axi_wr.resp.ready), + // Slave Interface Read Address Ports + .s_axi_arid (mig_axi_rd.addr.id), + .s_axi_araddr (mig_axi_rd.addr.addr), + .s_axi_arlen (mig_axi_rd.addr.len), + .s_axi_arsize (mig_axi_rd.addr.size), + .s_axi_arburst (mig_axi_rd.addr.burst), + .s_axi_arlock (mig_axi_rd.addr.lock), + .s_axi_arcache (mig_axi_rd.addr.cache), + .s_axi_arprot (mig_axi_rd.addr.prot), + .s_axi_arqos (mig_axi_rd.addr.qos), + .s_axi_arvalid (mig_axi_rd.addr.valid), + .s_axi_arready (mig_axi_rd.addr.ready), + // Slave Interface Read Data Ports + .s_axi_rid (mig_axi_rd.data.id), + .s_axi_rdata (mig_axi_rd.data.data), + .s_axi_rresp (mig_axi_rd.data.resp), + .s_axi_rlast (mig_axi_rd.data.last), + .s_axi_rvalid (mig_axi_rd.data.valid), + .s_axi_rready (mig_axi_rd.data.ready), + // System Clock Ports + .sys_clk_i (sys_clk), // From external 100MHz source. + .sys_rst (sys_rst) + ); + + //--------------------------------------------------- + // DDR3 SDRAM Models + //--------------------------------------------------- + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i0 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[1:0]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[15:0]), + .dqs (ddr3_dqs_p[1:0]), + .dqs_n (ddr3_dqs_n[1:0]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + + ddr3_model #( + .DEBUG(0) //Disable verbose prints + ) sdram_i1 ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p), + .ck_n (ddr3_ck_n), + .cke (ddr3_cke), + .cs_n (ddr3_cs_n), + .ras_n (ddr3_ras_n), + .cas_n (ddr3_cas_n), + .we_n (ddr3_we_n), + .dm_tdqs (ddr3_dm[3:2]), + .ba (ddr3_ba), + .addr (ddr3_addr), + .dq (ddr3_dq[31:16]), + .dqs (ddr3_dqs_p[3:2]), + .dqs_n (ddr3_dqs_n[3:2]), + .tdqs_n (), // Unused on x16 + .odt (ddr3_odt) + ); + end endgenerate + +endmodule diff --git a/fpga/usrp3/top/x300/sim/dram_fifo/dram_fifo_tb.sv b/fpga/usrp3/top/x300/sim/dram_fifo/dram_fifo_tb.sv new file mode 100644 index 000000000..0be9dc9dd --- /dev/null +++ b/fpga/usrp3/top/x300/sim/dram_fifo/dram_fifo_tb.sv @@ -0,0 +1,184 @@ +// +// Copyright 2016 Ettus Research +// + + +`timescale 1ns/1ps +`define SIM_TIMEOUT_US 120 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 7 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +//`define USE_SRAM_FIFO //Use an AXI-Stream SRAM FIFO (for testing) +`define USE_SRAM_MIG 0 //Use the DMA engine from the DRAM FIFO but SRAM as the base memory +`define USE_BD_INTERCON 1 //Use the Block Design Axi Interconnect + +module dram_fifo_tb(); + `TEST_BENCH_INIT("dram_fifo_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(sys_clk, 10, 50) //100MHz sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/166.6667, 50) //166MHz bus_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET(sys_rst, 0, 100) //100ns for GSR to deassert + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master chdr_i (.clk(bus_clk)); + cvita_slave chdr_o (.clk(bus_clk)); + + // Initialize DUT + wire calib_complete; +`ifdef USE_SRAM_FIFO + + axi_fifo #(.WIDTH(65), .SIZE(18)) dut_single ( + .clk(bus_clk), + .reset(bus_rst), + .clear(1'b0), + + .i_tdata({chdr_i.axis.tlast, chdr_i.axis.tdata}), + .i_tvalid(chdr_i.axis.tvalid), + .i_tready(chdr_i.axis.tready), + + .o_tdata({chdr_o.axis.tlast, chdr_o.axis.tdata}), + .o_tvalid(chdr_o.axis.tvalid), + .o_tready(chdr_o.axis.tready), + + .space(), + .occupied() + ); + assign calib_complete = 1; + +`else + + axis_dram_fifo_single #( + .USE_SRAM_MEMORY(`USE_SRAM_MIG), + .USE_BD_INTERCON(`USE_BD_INTERCON) + ) dut_single + ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .i_tdata(chdr_i.axis.tdata), + .i_tlast(chdr_i.axis.tlast), + .i_tvalid(chdr_i.axis.tvalid), + .i_tready(chdr_i.axis.tready), + + .o_tdata(chdr_o.axis.tdata), + .o_tlast(chdr_o.axis.tlast), + .o_tvalid(chdr_o.axis.tvalid), + .o_tready(chdr_o.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(), + + .forced_bit_err(64'h0), + .init_calib_complete(calib_complete) + ); +`endif + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (sys_rst) @(posedge sys_clk); + `TEST_CASE_DONE((~bus_rst & ~sys_rst)); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (short packet)"); + chdr_i.push_ramp_pkt(16, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",16,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==16, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + chdr_i.push_ramp_pkt(1024, 64'd0, 64'h100, header); + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",1024,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==1024, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + `TEST_CASE_DONE(1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Concurrent read and write (single packet)"); + fork + begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + chdr_o.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + i = 0; + repeat (20) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Concurrent read and write (multiple packets)"); + fork + begin + repeat (10) begin + chdr_i.push_ramp_pkt(20, 64'd0, 64'h100, header); + repeat (30) @(posedge bus_clk); + end + end + begin + repeat (10) begin + chdr_o.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + end + end + join + `TEST_CASE_DONE(1); + + `TEST_BENCH_DONE; + + end + +endmodule diff --git a/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile new file mode 100644 index 000000000..8e75817b1 --- /dev/null +++ b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile @@ -0,0 +1,72 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = kintex7 +PART_ID = xc7k410t/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/axi/Makefile.srcs +include $(BASE_DIR)/../lib/control/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/ddr3_32bit/Makefile.inc +include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc +include $(IP_DIR)/axi4_dualport_sram/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_DDR3_32BIT_SRCS) \ +$(IP_AXI_INTERCON_2X64_128_SRCS) \ +$(IP_AXI_INTERCON_2X64_128_BD_SRCS) \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +$(IP_AXI4_BRAM_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = dram_fifo_bist_tb + +SIM_SRCS = \ +$(abspath dram_fifo_bist_tb.sv) \ +$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \ +$(IP_DDR3_32BIT_SIM_OUTS) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/x300/sim/dram_fifo_bist/dram_fifo_bist_tb.sv b/fpga/usrp3/top/x300/sim/dram_fifo_bist/dram_fifo_bist_tb.sv new file mode 100644 index 000000000..33fb93332 --- /dev/null +++ b/fpga/usrp3/top/x300/sim/dram_fifo_bist/dram_fifo_bist_tb.sv @@ -0,0 +1,349 @@ +// +// Copyright 2015 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define SIM_RUNTIME_US 3000 +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 25 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" +`include "sim_cvita_lib.svh" +`include "sim_axi4_lib.svh" +`include "sim_set_rb_lib.svh" + +//`define USE_SRAM_FIFO //Use an AXI-Stream SRAM FIFO (for testing) +`define USE_SRAM_MIG 1 //Use the DMA engine from the DRAM FIFO but SRAM as the base memory +`define USE_BD_INTERCON 1 //Use the Block Design Axi Interconnect + + +module dram_fifo_bist_tb(); + `TEST_BENCH_INIT("dram_fifo_bist_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + // Define all clocks and resets + `DEFINE_CLK(sys_clk, 10, 50) //100MHz sys_clk to generate DDR3 clocking + `DEFINE_CLK(bus_clk, 1000/166.6667, 50) //166MHz bus_clk + `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert + `DEFINE_RESET(sys_rst, 0, 100) //100ns for GSR to deassert + + // Initialize DUT + wire calib_complete; + wire running, done; + wire [1:0] error; + wire [31:0] rb_data; + reg [63:0] forced_bit_err; + + settings_bus_master #(.SR_AWIDTH(8),.SR_DWIDTH(32)) tst_set (.clk(bus_clk)); + cvita_master cvita_fifo_in (.clk(bus_clk)); + cvita_slave cvita_fifo_out (.clk(bus_clk)); + + // AXI DRAM FIFO Topology (Inline production BIST for DRAM FIFO): + // + // User Data ====> |---------| |---------------| |-----------| ====> User Data Out + // | AXI MUX | ====> | AXI DRAM FIFO | ====> | AXI DEMUX | + // BIST Data ====> |---------| |---------------| |-----------| ====> BIST Data Out + // || + // |--------------| + // | MIG (D/S)RAM | + // |--------------| + + localparam SR_FIFO_BASE = 0; + localparam SR_BIST_BASE = SR_FIFO_BASE + 4; + + axis_dram_fifo_single #( + .USE_SRAM_MEMORY(`USE_SRAM_MIG), + .USE_BD_INTERCON(`USE_BD_INTERCON), + .SR_BASE(SR_FIFO_BASE) + ) dut_single ( + .bus_clk(bus_clk), + .bus_rst(bus_rst), + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .i_tdata(cvita_fifo_in.axis.tdata), + .i_tlast(cvita_fifo_in.axis.tlast), + .i_tvalid(cvita_fifo_in.axis.tvalid), + .i_tready(cvita_fifo_in.axis.tready), + + .o_tdata(cvita_fifo_out.axis.tdata), + .o_tlast(cvita_fifo_out.axis.tlast), + .o_tvalid(cvita_fifo_out.axis.tvalid), + .o_tready(cvita_fifo_out.axis.tready), + + .set_stb(tst_set.settings_bus.set_stb), + .set_addr(tst_set.settings_bus.set_addr), + .set_data(tst_set.settings_bus.set_data), + .rb_data(rb_data), + + .forced_bit_err(forced_bit_err), + .init_calib_complete(calib_complete) + ); + + assign {error, done, running} = rb_data[3:0]; + + //Testbench variables + cvita_hdr_t header; + cvita_pkt_t pkt_out; + integer i; + integer single_run_time; + integer xfer_cnt, cyc_cnt; + + //------------------------------------------ + //Main thread for testbench execution + //------------------------------------------ + initial begin : tb_main + string s; + + `TEST_CASE_START("Wait for reset"); + while (bus_rst) @(posedge bus_clk); + while (sys_rst) @(posedge sys_clk); + `TEST_CASE_DONE(~bus_rst & ~sys_rst); + + forced_bit_err <= 64'h0; + repeat (200) @(posedge sys_clk); + + `TEST_CASE_START("Wait for initial calibration to complete"); + while (calib_complete !== 1'b1) @(posedge bus_clk); + `TEST_CASE_DONE(calib_complete); + + `TEST_CASE_START("Clear FIFO"); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b1}); + repeat (200) @(posedge bus_clk); + tst_set.write(SR_FIFO_BASE + 1, {16'h0, 12'd280, 2'b00, 1'b0, 1'b0}); + repeat (200) @(posedge bus_clk); + `TEST_CASE_DONE(1); + + //Select BIST status as the readback output + tst_set.write(SR_FIFO_BASE + 0, 3'd1); + + header = '{ + pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666, + length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0}; + + `TEST_CASE_START("Fill up empty FIFO then drain (long packet)"); + cvita_fifo_in.push_ramp_pkt(100, 64'd0, 64'h100, header); + cvita_fifo_out.pull_pkt(pkt_out); + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",100,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==100, s); + $sformat(s, "Bad packet: Wrong SID. Expected: %08x, Actual: %08x", + {header.src_sid,header.dst_sid},{pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}); + `ASSERT_ERROR({header.src_sid,header.dst_sid}=={pkt_out.hdr.src_sid,pkt_out.hdr.dst_sid}, s); + i = 0; + repeat (100) begin + $sformat(s, "Bad packet: Wrong payload. Index: %d, Expected: %08x, Actual: %08x", + i,(i * 64'h100),pkt_out.payload[i]); + `ASSERT_ERROR(pkt_out.payload[i]==(i * 64'h100), s); + end + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 10 x 40byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd40, 18'd10}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... again (should fail)"); + forced_bit_err <= 64'h8000000000000000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + forced_bit_err <= 64'h0; + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Run BIST ... and again (should pass)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 8000 x 40byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd40, 18'd8000}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd3, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 256 x 1000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd4, 16'd256}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd1000, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("User Data: Concurrent read and write"); + cvita_fifo_out.axis.tready = 1; + fork + begin + cvita_fifo_in.push_ramp_pkt(20, 64'd0, 64'h100, header); + end + begin + cvita_fifo_out.pull_pkt(pkt_out); + end + join + $sformat(s, "Bad packet: Length mismatch. Expected: %0d, Actual: %0d",20,pkt_out.payload.size()); + `ASSERT_ERROR(pkt_out.payload.size()==20, s); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Setup BIST: 256 x 600byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h01234567); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd600, 18'd256}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b1}); + while (~done) @(posedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 30 x 8000byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd8000, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 100 x 8000byte ramping packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'h0ABCDEF0); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b1, 13'd8000, 18'd100}); + `TEST_CASE_DONE(~done & ~running); + + `TEST_CASE_START("Run BIST"); + tst_set.write(SR_BIST_BASE + 0, {2'd1, 2'd0, 1'b0, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + + `TEST_CASE_START("Setup BIST: 10 x 256byte packets"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 3, 32'hFFFFFFFF); + tst_set.write(SR_BIST_BASE + 2, {8'd0, 16'd0}); + tst_set.write(SR_BIST_BASE + 1, {1'b0, 13'd256, 18'd30}); + `TEST_CASE_DONE(~done & ~running); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous (Early interrupt)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + single_run_time = $time - curr_time; + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #2000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + fork + begin + `TEST_CASE_START("Run BIST Continuous (Force error)"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b01, "BIST passed when it should have failed!"); + @(posedge bus_clk); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then force error + #10000; + forced_bit_err <= 64'h1; + end + join + //Recover from failure + forced_bit_err <= 64'h0; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + repeat (2000) @(posedge bus_clk); + + fork + begin + integer curr_time = $time; + `TEST_CASE_START("Run BIST Continuous"); + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + tst_set.write(SR_BIST_BASE + 0, {2'd2, 2'd0, 1'b1, 1'b1}); + while (~done) @(negedge bus_clk); + `ASSERT_ERROR(error==2'b00, "BIST failed!"); + @(posedge bus_clk); + `ASSERT_ERROR((($time - curr_time) > 2 * single_run_time), "Continuous test most likely stopped early!"); + `TEST_CASE_DONE(done & ~running); + end + begin + //Wait then clear + #100000; + tst_set.write(SR_BIST_BASE + 0, {2'd0, 2'd0, 1'b0, 1'b0}); + end + join + + `TEST_CASE_START("Validate Throughput"); + tst_set.write(SR_FIFO_BASE + 0, 3'd2); + xfer_cnt = rb_data; + tst_set.write(SR_FIFO_BASE + 0, 3'd3); + cyc_cnt = rb_data; + `ASSERT_ERROR(xfer_cnt>0, "Transfer count was not >0"); + `ASSERT_ERROR(cyc_cnt>0, "Cycle count was not >0"); + $display("Measured Throughput = %0d%% of bus_clk throughput", ((xfer_cnt*100)/cyc_cnt)); + `ASSERT_ERROR(((xfer_cnt*100)/cyc_cnt)>80, "Throughput was less than 80%%"); + tst_set.write(SR_FIFO_BASE + 0, 3'd1); //Restore + `TEST_CASE_DONE(done & ~running); + `TEST_BENCH_DONE; + + end +endmodule diff --git a/fpga/usrp3/top/x300/sim/x300_pcie_int/Makefile b/fpga/usrp3/top/x300/sim/x300_pcie_int/Makefile new file mode 100644 index 000000000..02aaef59c --- /dev/null +++ b/fpga/usrp3/top/x300/sim/x300_pcie_int/Makefile @@ -0,0 +1,66 @@ +# +# Copyright 2015 Ettus Research LLC +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir +BASE_DIR = $(abspath ../../..) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = kintex7 +PART_ID = xc7k410t/ffg900/-2 + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs +include $(BASE_DIR)/../lib/fifo/Makefile.srcs +include $(BASE_DIR)/../lib/io_port2/Makefile.srcs + +DESIGN_SRCS = $(abspath \ +$(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(PACKET_PROC_SRCS) \ +$(IOPORT2_SRCS) \ +../../x300_pcie_int.v \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = ../../ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +include $(IP_DIR)/fifo_short_2clk/Makefile.inc +include $(IP_DIR)/fifo_4k_2clk/Makefile.inc + +DESIGN_SRCS += $(abspath \ +$(IP_FIFO_4K_2CLK_SRCS) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +# Define only one toplevel module +SIM_TOP = x300_pcie_int_tb + +SIM_SRCS = \ +$(abspath x300_pcie_int_tb.sv) + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/fpga/usrp3/top/x300/sim/x300_pcie_int/x300_pcie_int_tb.sv b/fpga/usrp3/top/x300/sim/x300_pcie_int/x300_pcie_int_tb.sv new file mode 100644 index 000000000..0093e4315 --- /dev/null +++ b/fpga/usrp3/top/x300/sim/x300_pcie_int/x300_pcie_int_tb.sv @@ -0,0 +1,596 @@ +// +// Copyright 2013 Ettus Research LLC +// + + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 23 + +`define SIM_TIMEOUT_US 1000 // 1ms + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" + +module x300_pcie_int_tb(); + `DEFINE_CLK(clk, 8.000, 50) + `DEFINE_RESET(reset, 0, 10) + + `TEST_BENCH_INIT("x300_pcie_int_tb",`NUM_TEST_CASES,`NS_PER_TICK) + + reg temp_pass = 0; + reg pkt_swap = 0; + reg [15:0] it = 0; + reg [15:0] tx_ch, rx_ch = 0; + + reg [31:0] dma_sample_cnt = 0; + reg [31:0] dma_packet_cnt = 0; + reg [31:0] dma_out_sample_cnt[0:5]; + reg [63:0] dma_out_last_sample[0:5]; + + reg pcie_usr_reg_wr, pcie_usr_reg_rd; + reg [1:0] pcie_usr_reg_len; + reg [19:0] pcie_usr_reg_addr; + reg [31:0] pcie_usr_reg_data_in, pcie_usr_data; + wire pcie_usr_reg_rc, pcie_usr_reg_rdy; + wire [31:0] pcie_usr_reg_data_out; + + wire chinch_reg_wr, chinch_reg_rd; + wire [1:0] chinch_reg_len; + wire [19:0] chinch_reg_addr; + wire [31:0] chinch_reg_data_out; + reg chinch_reg_rc, chinch_reg_rdy; + reg [31:0] chinch_reg_data_in; + + reg [2:0] i_chan, o_chan; + reg [383:0] i_tdata_par; + reg [5:0] i_tvalid_par = 6'b000000, o_tready_par = 6'b111111; + wire [383:0] o_tdata_par; + wire [5:0] o_tvalid_par, i_tready_par; + + reg i_tvalid, i_tready, o_tvalid, o_tready; + reg [63:0] i_tdata, o_tdata; + + localparam READ = 2'b01; + localparam WRITE = 2'b10; + + task usr_regport_request; + input [1:0] operation; + input [19:0] address; + input [31:0] data; + begin + pcie_usr_reg_data_in <= data; + pcie_usr_reg_addr <= address; + pcie_usr_reg_wr <= operation[1]; + pcie_usr_reg_rd <= operation[0]; + pcie_usr_reg_len <= 2'b10; + + @(posedge clk); + while (~pcie_usr_reg_rdy) @(posedge clk); + + pcie_usr_reg_wr <= 1'b0; + pcie_usr_reg_rd <= 1'b0; + @(posedge clk); + end + endtask // usr_regport_request + + task usr_regport_response; + begin + @(posedge clk); + while (~pcie_usr_reg_rc) @(posedge clk); + pcie_usr_data <= pcie_usr_reg_data_out; + @(posedge clk); + end + endtask // usr_regport_response + + task chinch_regport_request; + input [1:0] operation; + input [19:0] address; + input [31:0] data; + begin + @(posedge clk); + while (~(chinch_reg_rdy && + chinch_reg_addr == address && + {chinch_reg_wr,chinch_reg_rd} == operation && + chinch_reg_len == 2'b10 && + (operation == WRITE || chinch_reg_data_out == data) + )) @(posedge clk); + + @(posedge clk); + end + endtask // chinch_regport_request + + task chinch_regport_response; + input [31:0] data; + begin + @(posedge clk); + chinch_reg_data_in <= data; + chinch_reg_rc <= 1'b1; + @(posedge clk); + chinch_reg_rc <= 1'b0; + end + endtask // chinch_regport_response + + task send_packet; + input [63:0] sid; + input [31:0] len; + input [31:0] quant; + begin + if(quant < 2) begin + i_tdata <= { sid[63:32],len[15:0], sid[15:0] }; + i_tvalid <= 1; + @(posedge clk); + i_tvalid <= 0; + @(posedge clk); + end else begin + i_tdata <= { sid[63:32],len[15:0], sid[15:0] }; + i_tvalid <= 1; + @(posedge clk); + i_tdata <= 64'h0000_0001_0000_0000; + repeat(quant - 2) begin + i_tdata <= i_tdata + 64'h0000_0002_0000_0002; + @(posedge clk); + end + i_tdata <= i_tdata + 64'h0000_0002_0000_0002; + @(posedge clk); + i_tvalid <= 1'b0; + @(posedge clk); + end // else: !if(len < 3) + end + endtask // send_packet + + task reset_dma_counts; + begin + dma_sample_cnt <= 32'd0; + dma_packet_cnt <= 32'd0; + dma_out_sample_cnt[0] <= 32'd0; + dma_out_sample_cnt[1] <= 32'd0; + dma_out_sample_cnt[2] <= 32'd0; + dma_out_sample_cnt[3] <= 32'd0; + dma_out_sample_cnt[4] <= 32'd0; + dma_out_sample_cnt[5] <= 32'd0; + dma_out_last_sample[0] <= 64'd0; + dma_out_last_sample[1] <= 64'd0; + dma_out_last_sample[2] <= 64'd0; + dma_out_last_sample[3] <= 64'd0; + dma_out_last_sample[4] <= 64'd0; + dma_out_last_sample[5] <= 64'd0; + @(posedge clk); + end + endtask // reset_dma_counts + + task select_channels; + input [2:0] tx_ch; + input [2:0] rx_ch; + begin + i_chan <= tx_ch; + o_chan <= rx_ch; + @(posedge clk); + end + endtask // select_channels + + task wait_for_pkt_loopback; + begin + while (i_tvalid & i_tready) @(posedge clk); //Wait for outbound pkt to pad and send + while (~o_tvalid) @(posedge clk); //Wait for inbound pkt to arrive + while (o_tvalid & o_tready) @(posedge clk); //Wait for inbound pkt to finish + end + endtask // wait_for_pkt_loopback + + wire [63:0] dma_loop_tdata ; + wire [ 2:0] dma_loop_tuser ; + wire dma_loop_tvalid, dma_loop_tlast, dma_loop_tready; + + wire [63:0] iop2_msg_tdata ; + wire iop2_msg_tvalid, iop2_msg_tlast, iop2_msg_tready; + + + initial begin : tb_main + while (reset) @(posedge clk); + + chinch_reg_rdy <= 1'b1; + chinch_reg_rc <= 1'b0; + + `TEST_CASE_START("Verify signature register"); + usr_regport_request(READ, 20'h40000, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE((pcie_usr_data == "X300")) + + `TEST_CASE_START("Verify counter frequency register"); + usr_regport_request(READ, 20'h4000C, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE((pcie_usr_data == 166666667)); + + `TEST_CASE_START("Verify scratch registers"); + usr_regport_request(WRITE, 20'h40010, 32'hDEAD); + usr_regport_request(WRITE, 20'h40014, 32'hBEEF); + usr_regport_request(READ, 20'h40014, 32'h0); + usr_regport_response(); + temp_pass <= (pcie_usr_data == 32'hBEEF); + usr_regport_request(READ, 20'h40010, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE((pcie_usr_data == 32'hDEAD) & temp_pass); + + `TEST_CASE_START("Client register port write 1"); + usr_regport_request(WRITE, 20'h60000, 32'h12345678); + chinch_regport_request(WRITE, 20'h60000, 32'h12345678); + + usr_regport_request(WRITE, 20'h7FFFC, 32'h1357); + chinch_regport_request(WRITE, 20'h7FFFC, 32'h1357); + + usr_regport_request(WRITE, 20'h70000, 32'h2468); + chinch_regport_request(WRITE, 20'h70000, 32'h2468); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Client register port read 1"); + usr_regport_request(READ, 20'h60000, 32'h0); + chinch_regport_request(READ, 20'h60000, 32'h0); + chinch_regport_response(32'hACE0BA51); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32'hACE0BA51),""); + + usr_regport_request(READ, 20'h7FFFC, 32'h0); + chinch_regport_request(READ, 20'h7FFFC, 32'h0); + chinch_regport_response(32'hACE0BA52); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32'hACE0BA52),""); + + usr_regport_request(READ, 20'h70000, 32'h0); + chinch_regport_request(READ, 20'h70000, 32'h0); + chinch_regport_response(32'hACE0BA53); + usr_regport_response(); + `TEST_CASE_DONE((pcie_usr_data == 32'hACE0BA53)); + + `TEST_CASE_START("Configure RX DMA routing table"); + usr_regport_request(WRITE, 20'h40500, 32'h0000_0000); + usr_regport_request(WRITE, 20'h40500, 32'h0001_0001); + usr_regport_request(WRITE, 20'h40500, 32'h0002_0002); + usr_regport_request(WRITE, 20'h40500, 32'h0003_0003); + usr_regport_request(WRITE, 20'h40500, 32'h00D3_0000); + usr_regport_request(WRITE, 20'h40500, 32'h00D2_0001); + usr_regport_request(WRITE, 20'h40500, 32'h00D1_0002); + usr_regport_request(WRITE, 20'h40500, 32'h00D0_0003); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Frame size register read"); + usr_regport_request(READ, 20'h40204, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [TX0]."); + usr_regport_request(READ, 20'h40214, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [TX1]."); + usr_regport_request(READ, 20'h40404, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [RX0]."); + usr_regport_request(READ, 20'h40414, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 32), "Frame size register read (Default) [RX1]."); + `TEST_CASE_DONE(1); + + o_tready <= 1'b1; + + `TEST_CASE_START("Loopback packet"); + reset_dma_counts(); + usr_regport_request(WRITE, 20'h40200, 32'h0000_0012); + usr_regport_request(WRITE, 20'h40400, 32'h0000_0012); + select_channels(0,0); + send_packet(16'h00D2, 80, 32); + wait_for_pkt_loopback(); + `TEST_CASE_DONE((dma_sample_cnt==10 && dma_packet_cnt==1 && dma_out_sample_cnt[0]==32)); + + reset_dma_counts(); + select_channels(1,0); + send_packet(16'h00D3, 80, 32); + wait_for_pkt_loopback(); + `TEST_CASE_DONE(dma_sample_cnt==10 && dma_packet_cnt==1 && dma_out_sample_cnt[0]==32); + + `TEST_CASE_START("Frame size register write."); + usr_regport_request(WRITE, 20'h40224, 32'd16); + usr_regport_request(WRITE, 20'h40234, 32'd16); + usr_regport_request(WRITE, 20'h40424, 32'd16); + usr_regport_request(WRITE, 20'h40434, 32'd16); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Frame size register read"); + usr_regport_request(READ, 20'h40224, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [TX2]."); + usr_regport_request(READ, 20'h40234, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [TX3]."); + usr_regport_request(READ, 20'h40424, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [RX2]."); + usr_regport_request(READ, 20'h40434, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 16), "Frame size register read [RX3]."); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("Loopback packet"); + reset_dma_counts(); + select_channels(2,2); + send_packet(16'h0002, 32, 16); + wait_for_pkt_loopback(); + `TEST_CASE_DONE(dma_sample_cnt==4 && dma_packet_cnt==1 && dma_out_sample_cnt[2]==16); + + reset_dma_counts(); + select_channels(3,3); + send_packet(16'h0003, 32, 16); + wait_for_pkt_loopback(); + `TEST_CASE_DONE((dma_sample_cnt==4 && dma_packet_cnt==1 && dma_out_sample_cnt[3]==16)); + + `TEST_CASE_START("Loopback multiple packets"); + reset_dma_counts(); + select_channels(3,2); + send_packet(16'h0002, 128, 16); + send_packet(16'h0002, 128, 16); + send_packet(16'h0002, 128, 16); + send_packet(16'h0002, 128, 16); + wait_for_pkt_loopback(); + repeat(64) @(posedge clk); + `TEST_CASE_DONE(dma_sample_cnt==64 && dma_packet_cnt==4 && dma_out_sample_cnt[2]==64 && o_tdata==64'h0000009e00000020); + + `TEST_CASE_START("Loopback multiple packets (RX Swapped)"); + reset_dma_counts(); + select_channels(3,2); + + usr_regport_request(WRITE, 20'h40230, 32'h10); + usr_regport_request(WRITE, 20'h40420, 32'h00); + repeat(16) @(posedge clk); + + send_packet(16'h0002, 128, 16); + send_packet(16'h0002, 128, 16); + wait_for_pkt_loopback(); + repeat(64) @(posedge clk); + `TEST_CASE_DONE(dma_sample_cnt==32 && dma_packet_cnt==2 && dma_out_sample_cnt[2]==32 && o_tdata==64'h000000200000009e); + + /* @TODO: Need to implement data swapping in TB + `TEST_CASE_START(); + reset_dma_counts(); + select_channels(3,2); + + usr_regport_request(WRITE, 20'h40230, 32'h00); + usr_regport_request(WRITE, 20'h40420, 32'h10); + repeat(16) @(posedge clk); + + send_packet(16'h0002, 128, 16); + send_packet(16'h0002, 128, 16); + wait_for_pkt_loopback(); + repeat(64) @(posedge clk); + `TEST_CASE_DONE(dma_sample_cnt==32 && dma_packet_cnt==2 && dma_out_sample_cnt[2]==32 && o_tdata[7:0]==32, + "Loopback multiple packets (TX Swapped)."); + */ + + `TEST_CASE_START("Good DMA status."); + reset_dma_counts(); + select_channels(3,2); + usr_regport_request(READ, 20'h40230, 32'h0); + usr_regport_response(); + temp_pass <= (pcie_usr_data == 32'h0); + usr_regport_request(READ, 20'h40420, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE(temp_pass && (pcie_usr_data == 32'h0)); + + `TEST_CASE_START("Bad DMA status."); + send_packet(16'h0002, 160, 20); + repeat(64) @(posedge clk); + usr_regport_request(READ, 20'h40230, 32'h0); + usr_regport_response(); + temp_pass <= (pcie_usr_data == 32'h1); + usr_regport_request(READ, 20'h40420, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE(temp_pass || (pcie_usr_data == 32'h1)); + + `TEST_CASE_START("DMA Status reset."); + usr_regport_request(WRITE, 20'h40230, 32'h1); + usr_regport_request(READ, 20'h40230, 32'h0); + usr_regport_response(); + temp_pass <= (pcie_usr_data == 32'h0); + usr_regport_request(WRITE, 20'h40420, 32'h1); + usr_regport_request(READ, 20'h40420, 32'h0); + usr_regport_response(); + `TEST_CASE_DONE(temp_pass && (pcie_usr_data == 32'h0)); + + `TEST_CASE_START("Packet count register reset"); + select_channels(2,1); + reset_dma_counts(); + usr_regport_request(WRITE, 20'h4022C, 32'h0); + usr_regport_request(READ, 20'h4022C, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 0), "TX Packet count register reset."); + usr_regport_request(WRITE, 20'h4041C, 32'h0); + usr_regport_request(READ, 20'h4041C, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 0), "RX Packet count register reset."); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("TX Packet count register read"); + send_packet(16'h0001, 80, 16); + send_packet(16'h0001, 24, 16); + send_packet(16'h0001, 48, 16); + repeat(64) @(posedge clk); + usr_regport_request(READ, 20'h4022C, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 3), "TX Packet count register read."); + usr_regport_request(READ, 20'h4041C, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 3), "RX Packet count register read."); + `TEST_CASE_DONE(1); + + `TEST_CASE_START("TX Sample count register reset"); + select_channels(1,2); + reset_dma_counts(); + usr_regport_request(WRITE, 20'h40218, 32'h0); + usr_regport_request(READ, 20'h40218, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 0), "TX Sample count register reset."); + usr_regport_request(WRITE, 20'h40428, 32'h0); + usr_regport_request(READ, 20'h40428, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 0), "RX Sample count register reset."); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("TX Sample count register read"); + send_packet(16'h0002, 28, 16); + wait_for_pkt_loopback(); + usr_regport_request(READ, 20'h40218, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 4), "TX Sample count register read."); + usr_regport_request(READ, 20'h40428, 32'h0); + usr_regport_response(); + `ASSERT_ERROR((pcie_usr_data == 4), "RX Sample count register read."); + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Setup for NxN DMA test"); + for (it = 0; it < 16'd6; it = it + 16'd1) begin + usr_regport_request(WRITE, 20'h40204 + (it * 16), 32'h4); + usr_regport_request(WRITE, 20'h40404 + (it * 16), 32'h4); + usr_regport_request(WRITE, 20'h40500, {it, it}); + end + `TEST_CASE_DONE(1'b1); + + `TEST_CASE_START("Setup for NxN DMA test"); + for (tx_ch = 0; tx_ch < 6; tx_ch = tx_ch + 16'd2) begin + for (rx_ch = 1; rx_ch < 6; rx_ch = rx_ch + 16'd1) begin + select_channels(tx_ch,rx_ch); + reset_dma_counts(); + @(posedge clk); + send_packet(rx_ch, 16, 4); + wait_for_pkt_loopback(); + if (dma_sample_cnt==2 && dma_packet_cnt==1 && dma_out_sample_cnt[rx_ch]==4) begin + $display("[TEST%d]: NxN DMA Test [TX=%d, RX=%d]...Passed",tc_run_count,tx_ch[3:0],rx_ch[3:0]); + end else begin + $display("[TEST%d]: NxN DMA Test [TX=%d, RX=%d]...FAILED!!!",tc_run_count,tx_ch[3:0],rx_ch[3:0]); + end + @(posedge clk); + end + end + `TEST_CASE_DONE(1'b1); + end // initial begin + + + x300_pcie_int #( + .DMA_STREAM_WIDTH (64), + .NUM_TX_STREAMS (6 ), + .NUM_RX_STREAMS (6 ), + .REGPORT_ADDR_WIDTH(20), + .REGPORT_DATA_WIDTH(32), + .IOP2_MSG_WIDTH (64) + ) x300_pcie_int ( + .ioport2_clk (clk ), + .bus_clk (clk ), + .bus_rst (reset ), + + //DMA TX FIFOs (IoPort2 Clock Domain) + .dmatx_tdata_iop2 (i_tdata_par ), + .dmatx_tvalid_iop2 (i_tvalid_par ), + .dmatx_tready_iop2 (i_tready_par ), + + //DMA TX FIFOs (IoPort2 Clock Domain) + .dmarx_tdata_iop2 (o_tdata_par ), + .dmarx_tvalid_iop2 (o_tvalid_par ), + .dmarx_tready_iop2 (o_tready_par ), + + //PCIe User Regport + .pcie_usr_reg_wr (pcie_usr_reg_wr ), + .pcie_usr_reg_rd (pcie_usr_reg_rd ), + .pcie_usr_reg_addr (pcie_usr_reg_addr ), + .pcie_usr_reg_data_in (pcie_usr_reg_data_in ), + .pcie_usr_reg_len (pcie_usr_reg_len ), + .pcie_usr_reg_data_out(pcie_usr_reg_data_out), + .pcie_usr_reg_rc (pcie_usr_reg_rc ), + .pcie_usr_reg_rdy (pcie_usr_reg_rdy ), + + //Chinch Regport + .chinch_reg_wr (chinch_reg_wr ), + .chinch_reg_rd (chinch_reg_rd ), + .chinch_reg_addr (chinch_reg_addr ), + .chinch_reg_data_out (chinch_reg_data_out ), + .chinch_reg_len (chinch_reg_len ), + .chinch_reg_data_in (chinch_reg_data_in ), + .chinch_reg_rc (chinch_reg_rc ), + .chinch_reg_rdy (chinch_reg_rdy ), + + //DMA TX FIFO (Bus Clock Domain) + .dmatx_tdata (dma_loop_tdata ), + .dmatx_tuser (dma_loop_tuser ), + .dmatx_tlast (dma_loop_tlast ), + .dmatx_tvalid (dma_loop_tvalid ), + .dmatx_tready (dma_loop_tready ), + + //DMA RX FIFO (Bus Clock Domain) + .dmarx_tdata (dma_loop_tdata ), + .dmarx_tuser (dma_loop_tuser ), + .dmarx_tlast (dma_loop_tlast ), + .dmarx_tvalid (dma_loop_tvalid ), + .dmarx_tready (dma_loop_tready ), + + //Message FIFO Out (Bus Clock Domain) + .rego_tdata (iop2_msg_tdata ), + .rego_tvalid (iop2_msg_tvalid ), + .rego_tlast (iop2_msg_tlast ), + .rego_tready (iop2_msg_tready ), + + //Message FIFO In (Bus Clock Domain) + .regi_tdata (iop2_msg_tdata ), + .regi_tvalid (iop2_msg_tvalid ), + .regi_tlast (iop2_msg_tlast ), + .regi_tready (iop2_msg_tready ), + + .debug ( ) + ); + + always @(posedge clk) begin + if (dma_loop_tvalid & dma_loop_tready) begin + dma_sample_cnt <= dma_sample_cnt + 32'd1; + if (dma_loop_tlast) dma_packet_cnt <= dma_packet_cnt + 32'd1; + end + end + + always @(posedge clk) begin + case (i_chan) + 3'd5: + {i_tdata_par[383:320], i_tvalid_par[5], i_tready} <= {i_tdata, i_tvalid, i_tready_par[5]}; + 3'd4: + {i_tdata_par[319:256], i_tvalid_par[4], i_tready} <= {i_tdata, i_tvalid, i_tready_par[4]}; + 3'd3: + {i_tdata_par[255:192], i_tvalid_par[3], i_tready} <= {i_tdata, i_tvalid, i_tready_par[3]}; + 3'd2: + {i_tdata_par[191:128], i_tvalid_par[2], i_tready} <= {i_tdata, i_tvalid, i_tready_par[2]}; + 3'd1: + {i_tdata_par[127:64], i_tvalid_par[1], i_tready} <= {i_tdata, i_tvalid, i_tready_par[1]}; + default: + {i_tdata_par[63:0], i_tvalid_par[0], i_tready} <= {i_tdata, i_tvalid, i_tready_par[0]}; + endcase + end + + always @(posedge clk) begin + case (o_chan) + 3'd5: + {o_tdata, o_tvalid, o_tready_par[5]} <= {o_tdata_par[383:320], o_tvalid_par[5], o_tready}; + 3'd4: + {o_tdata, o_tvalid, o_tready_par[4]} <= {o_tdata_par[319:256], o_tvalid_par[4], o_tready}; + 3'd3: + {o_tdata, o_tvalid, o_tready_par[3]} <= {o_tdata_par[255:192], o_tvalid_par[3], o_tready}; + 3'd2: + {o_tdata, o_tvalid, o_tready_par[2]} <= {o_tdata_par[191:128], o_tvalid_par[2], o_tready}; + 3'd1: + {o_tdata, o_tvalid, o_tready_par[1]} <= {o_tdata_par[127:64], o_tvalid_par[1], o_tready}; + default: + {o_tdata, o_tvalid, o_tready_par[0]} <= {o_tdata_par[63:0], o_tvalid_par[0], o_tready}; + endcase + end + + genvar i; + generate + for (i=0; i<6; i=i+1) begin: dma_counter_generator + always @(posedge clk) begin + if (o_tvalid_par[i] & o_tready_par[i]) begin + dma_out_sample_cnt[i] <= dma_out_sample_cnt[i] + 32'd1; + dma_out_last_sample[i] <= o_tdata_par[(64*i)+63:64*i]; + end + end + end + endgenerate + +endmodule diff --git a/fpga/usrp3/top/x300/soft_ctrl.v b/fpga/usrp3/top/x300/soft_ctrl.v new file mode 100644 index 000000000..3c45a3dd2 --- /dev/null +++ b/fpga/usrp3/top/x300/soft_ctrl.v @@ -0,0 +1,482 @@ +// +// Copyright 2012 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module soft_ctrl +#( + parameter SB_ADDRW = 8, + parameter RB_ADDRW = 8, + parameter dw = 32, // Data bus width + parameter aw = 16, // Address bus width, for byte addressibility, 16 = 64K byte memory space + parameter sw = 4 // Select width -- 32-bit data bus with 8-bit granularity. +) +( + input clk, input rst, + input clk_div2, input rst_div2, + + //------------------------------------------------------------------ + // I2C interfaces + //------------------------------------------------------------------ + inout scl0, inout sda0, + inout scl1, inout sda1, + inout scl2, inout sda2, + + //------------------------------------------------------------------ + // UARTs + //------------------------------------------------------------------ + input gps_rxd, + output gps_txd, + input debug_rxd, + output debug_txd, + + //------------------------------------------------------------------ + // settings bus interface + //------------------------------------------------------------------ + output [31:0] set_data, + output [SB_ADDRW-1:0] set_addr, + output set_stb, + + //------------------------------------------------------------------ + // settings bus interface for crossbar router + //------------------------------------------------------------------ + output [31:0] set_data_xb, + output [8:0] set_addr_xb, + output set_stb_xb, + + //------------------------------------------------------------------ + // readback bus interface + //------------------------------------------------------------------ + input [31:0] rb_data, + output [RB_ADDRW-1:0] rb_addr, + output rb_rd_stb, + + //------------------------------------------------------------------ + // packet interface in + //------------------------------------------------------------------ + input [63:0] rx_tdata, + input [3:0] rx_tuser, + input rx_tlast, + input rx_tvalid, + output rx_tready, + + //------------------------------------------------------------------ + // packet interface out + //------------------------------------------------------------------ + output [63:0] tx_tdata, + output [3:0] tx_tuser, + output tx_tlast, + output tx_tvalid, + input tx_tready, + + //------------------------------------------------------------------ + // PCIe endpoint interface + //------------------------------------------------------------------ + output [63:0] o_iop2_msg_tdata, + output o_iop2_msg_tvalid, + output o_iop2_msg_tlast, + input o_iop2_msg_tready, + input [63:0] i_iop2_msg_tdata, + input i_iop2_msg_tvalid, + input i_iop2_msg_tlast, + output i_iop2_msg_tready, + + //------------------------------------------------------------------ + // Debug + //------------------------------------------------------------------ + output [127:0] debug0, + output [31:0] debug1, + + //------------------------------------------------------------------ + // Wishbone Slave Interface(s) + //------------------------------------------------------------------ + input [dw-1:0] s4_dat_i, + output [dw-1:0] s4_dat_o, + output [aw-1:0] s4_adr, + output [sw-1:0] s4_sel, + input s4_ack, + output s4_stb, + output s4_cyc, + output s4_we, + input s4_int, // Nothing to connect this too!! No IRQ controller on x300. + + input [dw-1:0] s5_dat_i, + output [dw-1:0] s5_dat_o, + output [aw-1:0] s5_adr, + output [sw-1:0] s5_sel, + input s5_ack, + output s5_stb, + output s5_cyc, + output s5_we, + input s5_int // Nothing to connect this too!! No IRQ controller on x300. + + +); + + //////////////////////////////////////////////////////////////////// + // WB interconnect - ZPU, RAM, settings... + //////////////////////////////////////////////////////////////////// + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + /* s4_dat_o,s5_dat_o,s4_dat_i,s5_dat_i, */s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,/*s4_adr,s5_adr,*/s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr,sd_adr,se_adr,sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,/*s4_sel,s5_sel,*/s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel,sd_sel,se_sel,sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,/*s4_ack,s5_ack,*/s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack,sd_ack,se_ack,sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,/*s4_stb,s5_stb,*/s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb,sd_stb,se_stb,sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,/*s4_cyc,s5_cyc,*/s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc,sd_cyc,se_cyc,sf_cyc; + wire m0_we,s0_we,s1_we,s2_we,s3_we,/*s4_we,s5_we,*/s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1000_0000), // 0x0000 - Main RAM 32k + .s1_addr(8'b1000_0000),.s1_mask(8'b1110_0000), // 0x8000 - PKT RAM 8k + .s2_addr(8'b1010_0000),.s2_mask(8'b1111_0000), // 0xa000 - Settings/Readback - misc + .s3_addr(8'b1011_0000),.s3_mask(8'b1111_0000), // 0xb000 - Settings/Readback - crossbar + .s4_addr(8'b1100_0000),.s4_mask(8'b1111_0000), // 0xc000 - 10GE MAC 0 + .s5_addr(8'b1101_0000),.s5_mask(8'b1111_0000), // 0xd000 - 10GE MAC 1 + .s6_addr(8'b1111_0110),.s6_mask(8'b1111_1111), // 0xf600 - Unused + .s7_addr(8'b1111_0111),.s7_mask(8'b1111_1111), // 0xf700 - Unused + .s8_addr(8'b1111_1000),.s8_mask(8'b1111_1111), // 0xf800 - Unused + .s9_addr(8'b1111_1001),.s9_mask(8'b1111_1111), // 0xf900 - UART1 (Debug on GPIO) + .sa_addr(8'b1111_1010),.sa_mask(8'b1111_1111), // 0xfa00 - FW Programmer + .sb_addr(8'b1111_1011),.sb_mask(8'b1111_1111), // 0xfb00 - PCIe Endpoint + .sc_addr(8'b1111_1100),.sc_mask(8'b1111_1111), // 0xfc00 - I2C2 + .sd_addr(8'b1111_1101),.sd_mask(8'b1111_1111), // 0xfd00 - UART0 (GPS) + .se_addr(8'b1111_1110),.se_mask(8'b1111_1111), // 0xfe00 - I2C0 + .sf_addr(8'b1111_1111),.sf_mask(8'b1111_1111), // 0xff00 - I2C1 + .dw(dw),.aw(aw),.sw(sw)) + wb_1master + (.clk_i(clk_div2),.rst_i(rst_div2), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(),.m0_rty_o(),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(1'b0),.s0_rty_i(1'b0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(1'b0),.s1_rty_i(1'b0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(1'b0),.s2_rty_i(1'b0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(1'b0),.s3_rty_i(1'b0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(1'b0),.s4_rty_i(1'b0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(1'b0),.s5_rty_i(1'b0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(1'b0),.s6_rty_i(1'b0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(1'b0),.s7_rty_i(1'b0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(1'b0),.s8_rty_i(1'b0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(1'b0),.s9_rty_i(1'b0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(1'b0),.sa_rty_i(1'b0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(1'b0),.sb_rty_i(1'b0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(1'b0),.sc_rty_i(1'b0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(1'b0),.sd_rty_i(1'b0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(1'b0),.se_rty_i(1'b0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(1'b0),.sf_rty_i(1'b0) ); + + //assign {s0_dat_i, s0_ack} = 33'b0; + //assign {s1_dat_i, s1_ack} = 33'b0; + //assign {s2_dat_i, s2_ack} = 33'b0; + //assign {s3_dat_i, s3_ack} = 33'b0; + //assign {s4_dat_i, s4_ack} = 33'b0; + //assign {s5_dat_i, s5_ack} = 33'b0; + assign {s6_dat_i, s6_ack} = 33'b0; + assign {s7_dat_i, s7_ack} = 33'b0; + assign {s8_dat_i, s8_ack} = 33'b0; + //assign {s9_dat_i, s9_ack} = 33'b0; + //assign {sa_dat_i, sa_ack} = 33'b0; + assign sa_dat_i = 32'b0; + //assign {sb_dat_i, sb_ack} = 33'b0; + //assign {sc_dat_i, sc_ack} = 33'b0; + //assign {sd_dat_i, sd_ack} = 33'b0; + //assign {se_dat_i, se_ack} = 33'b0; + //assign {sf_dat_i, sf_ack} = 33'b0; + + + //////////////////////////////////////////////////////////////////// + // Processor + //////////////////////////////////////////////////////////////////// + wire zpu_rst; + + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(clk_div2), .rst(zpu_rst), .enb(~zpu_rst), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(), .interrupt(1'b0)); + + //assign {debug1, debug0} = {bank_swap, zpu_rst, swap_addr, s0_we, s0_stb, s3_ack, s2_ack, s1_ack, s0_ack, txd, clk, rst, m0_we, m0_stb, m0_ack, m0_cyc, m0_adr, m0_dat_i}; + + //////////////////////////////////////////////////////////////////// + // Double buffered system RAM (Slave #0) and Bootloader (Slave #A) + //////////////////////////////////////////////////////////////////// + zpu_bootram #(.ADDR_WIDTH(aw), .DATA_WIDTH(dw), .MAX_ADDR(16'h7FFC)) sys_ram + ( + .clk(clk_div2), .rst(rst_div2), + .mem_stb(s0_stb), .mem_wea(&({4{s0_we}} & s0_sel)), .mem_acka(s0_ack), + .mem_addra(s0_adr), .mem_dina(s0_dat_o), .mem_douta(s0_dat_i), + .ldr_stb(sa_stb), .ldr_wea(&({4{sa_we}} & sa_sel)), + .ldr_addra(sa_adr), .ldr_dina(sa_dat_o), .ldr_acka(sa_ack), + .zpu_rst(zpu_rst) + ); + + //////////////////////////////////////////////////////////////////// + // Packet RAM -- Slave #1 + //////////////////////////////////////////////////////////////////// + + //------------------------------------------------------------------ + // packet interface in div2 + //------------------------------------------------------------------ + wire [63:0] rx_tdata_div2; + wire [3:0] rx_tuser_div2; + wire rx_tlast_div2; + wire rx_tvalid_div2; + wire rx_tready_div2; + + //------------------------------------------------------------------ + // packet interface out div2 + //------------------------------------------------------------------ + wire [63:0] tx_tdata_div2; + wire [3:0] tx_tuser_div2; + wire tx_tlast_div2; + wire tx_tvalid_div2; + wire tx_tready_div2; + + //clock cross fifo between bus_clk and bus_clk_div2 for axi stream input + //WIDTH = tdata+tuser+tlast = 69 + axi_fifo_2clk #(.WIDTH(69), .SIZE(5)) axi_stream_rx_fifo_2clk + (.reset(rst), + .i_aclk(clk), .i_tdata({rx_tdata, rx_tuser, rx_tlast}), .i_tvalid(rx_tvalid), .i_tready(rx_tready), + .o_aclk(clk_div2), .o_tdata({rx_tdata_div2, rx_tuser_div2, rx_tlast_div2}), .o_tvalid(rx_tvalid_div2), .o_tready(rx_tready_div2)); + + //clock cross fifo between bus_clk_div2 and bus_clk for axi stream output + //WIDTH = tdata+tuser+tlast = 69 + axi_fifo_2clk #(.WIDTH(69), .SIZE(5)) axi_stream_tx_fifo_2clk + (.reset(reset), + .i_aclk(clk_div2), .i_tdata({tx_tdata_div2, tx_tuser_div2, tx_tlast_div2}), .i_tvalid(tx_tvalid_div2), .i_tready(tx_tready_div2), + .o_aclk(clk), .o_tdata({tx_tdata, tx_tuser, tx_tlast}), .o_tvalid(tx_tvalid), .o_tready(tx_tready)); + + axi_stream_to_wb #(.AWIDTH(13), .CTRL_ADDR(13'h1ffc)) axi_stream_to_wb + ( + .clk_i(clk_div2), .rst_i(rst_div2), + + //wb interface + .we_i(s1_we), .stb_i(s1_stb), .cyc_i(s1_cyc), .ack_o(s1_ack), + .adr_i(s1_adr[12:0]), .dat_i(s1_dat_o), .dat_o(s1_dat_i), + + //axi stream in + .rx_tdata(rx_tdata_div2), .rx_tuser(rx_tuser_div2), .rx_tlast(rx_tlast_div2), + .rx_tvalid(rx_tvalid_div2), .rx_tready(rx_tready_div2), + + //axi stream out + .tx_tdata(tx_tdata_div2), .tx_tuser(tx_tuser_div2), .tx_tlast(tx_tlast_div2), + .tx_tvalid(tx_tvalid_div2), .tx_tready(tx_tready_div2), + + .debug_rx(), .debug_tx() + ); + + + + //////////////////////////////////////////////////////////////////// + // Settings and readback bus -- Slave #2 + //////////////////////////////////////////////////////////////////// + settings_bus #(.AWIDTH(aw), .DWIDTH(dw), .SWIDTH(SB_ADDRW)) settings_bus + ( + .wb_clk(clk_div2), .wb_rst(rst_div2), + .wb_adr_i(s2_adr), .wb_dat_i(s2_dat_o), + .wb_stb_i(s2_stb), .wb_we_i(s2_we), .wb_ack_o(s2_ack), + .strobe(set_stb), .addr(set_addr), .data(set_data) + ); + + settings_readback #(.AWIDTH(aw),.DWIDTH(dw), .RB_ADDRW(RB_ADDRW)) settings_readback + ( + .wb_clk(clk_div2), + .wb_rst(rst_div2), + .wb_adr_i(s2_adr), + .wb_stb_i(s2_stb), + .wb_we_i(s2_we), + .rb_data(rb_data), + .rb_addr(rb_addr), + .wb_dat_o(s2_dat_i), + .rb_rd_stb(rb_rd_stb) + ); + + // assign rb_addr = s2_adr[RB_ADDRW+1:2]; + // assign s2_dat_i = rb_data; + + //////////////////////////////////////////////////////////////////// + // Settings bus for cross bar -- Slave #3 + //////////////////////////////////////////////////////////////////// + settings_bus #(.AWIDTH(aw), .DWIDTH(dw), .SWIDTH(9)) settings_bus_xb + ( + .wb_clk(clk), .wb_rst(rst), + .wb_adr_i(s3_adr), .wb_dat_i(s3_dat_o), + .wb_stb_i(s3_stb), .wb_we_i(s3_we), .wb_ack_o(s3_ack), + .strobe(set_stb_xb), .addr(set_addr_xb), .data(set_data_xb) + ); + + assign s3_dat_i = 32'b0; + + //////////////////////////////////////////////////////////////////// + // 10GE MAC 0 -- Slave #4 + //////////////////////////////////////////////////////////////////// + // External to this Heirarchy. + + //////////////////////////////////////////////////////////////////// + // 10GE MAC 1 -- Slave #5 + //////////////////////////////////////////////////////////////////// + // External to this Heirarchy. + + + //////////////////////////////////////////////////////////////////// + // UART0 -- Slave #9 + //////////////////////////////////////////////////////////////////// + simple_uart zpu_debug_uart + ( + .clk_i(clk_div2), .rst_i(rst_div2), + .we_i(s9_we), .stb_i(s9_stb), .cyc_i(s9_cyc), .ack_o(s9_ack), + .adr_i(s9_adr[4:2]), .dat_i(s9_dat_o), .dat_o(s9_dat_i), + .rx_int_o(), .tx_int_o(), .tx_o(debug_txd), .rx_i(debug_rxd), .baud_o() + ); + + //////////////////////////////////////////////////////////////////// + // PCIe endpoint -- Slave #b + //////////////////////////////////////////////////////////////////// + + //------------------------------------------------------------------ + // PCIe endpoint interface in div2 + //------------------------------------------------------------------ + wire [63:0] o_iop2_msg_tdata_div2; + wire o_iop2_msg_tvalid_div2; + wire o_iop2_msg_tlast_div2; + wire o_iop2_msg_tready_div2; + wire [63:0] i_iop2_msg_tdata_div2; + wire i_iop2_msg_tvalid_div2; + wire i_iop2_msg_tlast_div2; + wire i_iop2_msg_tready_div2; + + + //clock cross fifo between bus_clk and bus_clk_div2 for i_iop2_msg + //WIDTH = tdata+tuser+tlast = 69 + axi_fifo_2clk #(.WIDTH(65), .SIZE(5)) i_iop2_msg_fifo_2clk + (.reset(reset), + .i_aclk(clk), .i_tdata({i_iop2_msg_tdata, i_iop2_msg_tlast}), .i_tvalid(i_iop2_msg_tvalid), .i_tready(i_iop2_msg_tready), + .o_aclk(clk_div2), .o_tdata({i_iop2_msg_tdata_div2, iop2_msg_tlast_div2}), .o_tvalid(i_iop2_msg_tvalid_div2), .o_tready(i_iop2_msg_tready_div2)); + + //clock cross fifo between bus_clk_div2 and bus_clk for o_iop2_msg + //WIDTH = tdata+tuser+tlast = 69 + axi_fifo_2clk #(.WIDTH(65), .SIZE(5)) o_iop2_msg_fifo_2clk + (.reset(reset), + .i_aclk(clk_div2), .i_tdata({o_iop2_msg_tdata_div2, 1'b1}), .i_tvalid(o_iop2_msg_tvalid_div2), .i_tready(o_iop2_msg_tready_div2), + .o_aclk(clk), .o_tdata({o_iop2_msg_tdata, o_iop2_msg_tlast}), .o_tvalid(o_iop2_msg_tvalid), .o_tready(o_iop2_msg_tready)); + + pcie_wb_reg_core #(.WB_ADDRW(aw), .WB_DATAW(dw)) pcie_reg_core + ( + .clk(clk_div2), .rst(rst_div2), + .wb_stb_i(sb_stb), .wb_we_i(sb_we), .wb_adr_i(sb_adr), + .wb_dat_i(sb_dat_o), .wb_ack_o(sb_ack), .wb_dat_o(sb_dat_i), + .msgi_tdata(i_iop2_msg_tdata_div2), .msgi_tvalid(i_iop2_msg_tvalid_div2), .msgi_tready(i_iop2_msg_tready_div2), + .msgo_tdata(o_iop2_msg_tdata_div2), .msgo_tvalid(o_iop2_msg_tvalid_div2), .msgo_tready(o_iop2_msg_tready_div2), + .debug(debug0) + ); + + //////////////////////////////////////////////////////////////////// + // I2C2 -- Slave #c + //////////////////////////////////////////////////////////////////// + wire scl2_pad_i, scl2_pad_o, scl2_pad_oen_o; + wire sda2_pad_i, sda2_pad_o, sda2_pad_oen_o; + + i2c_master_top #(.ARST_LVL(1)) i2c2 + ( + .wb_clk_i(clk_div2),.wb_rst_i(rst_div2),.arst_i(1'b0), + .wb_adr_i(sc_adr[4:2]),.wb_dat_i(sc_dat_o[7:0]),.wb_dat_o(sc_dat_i[7:0]), + .wb_we_i(sc_we),.wb_stb_i(sc_stb),.wb_cyc_i(sc_cyc), + .wb_ack_o(sc_ack),.wb_inta_o(), + .scl_pad_i(scl2_pad_i),.scl_pad_o(scl2_pad_o),.scl_padoen_o(scl2_pad_oen_o), + .sda_pad_i(sda2_pad_i),.sda_pad_o(sda2_pad_o),.sda_padoen_o(sda2_pad_oen_o) + ); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl2_pin(.O(scl2_pad_i), .IO(scl2), .I(scl2_pad_o), .T(scl2_pad_oen_o)); + IOBUF sda2_pin(.O(sda2_pad_i), .IO(sda2), .I(sda2_pad_o), .T(sda2_pad_oen_o)); + + assign sc_dat_i[31:8] = 24'd0; + + + //////////////////////////////////////////////////////////////////// + // UART0 -- Slave #d + //////////////////////////////////////////////////////////////////// + simple_uart gps_uart + ( + .clk_i(clk_div2), .rst_i(rst_div2), + .we_i(sd_we), .stb_i(sd_stb), .cyc_i(sd_cyc), .ack_o(sd_ack), + .adr_i(sd_adr[4:2]), .dat_i(sd_dat_o), .dat_o(sd_dat_i), + .rx_int_o(), .tx_int_o(), .tx_o(gps_txd), .rx_i(gps_rxd), .baud_o() + ); + + //////////////////////////////////////////////////////////////////// + // I2C0 -- Slave #e + //////////////////////////////////////////////////////////////////// + wire scl0_pad_i, scl0_pad_o, scl0_pad_oen_o; + wire sda0_pad_i, sda0_pad_o, sda0_pad_oen_o; + + i2c_master_top #(.ARST_LVL(1)) i2c0 + ( + .wb_clk_i(clk_div2),.wb_rst_i(rst_div2),.arst_i(1'b0), + .wb_adr_i(se_adr[4:2]),.wb_dat_i(se_dat_o[7:0]),.wb_dat_o(se_dat_i[7:0]), + .wb_we_i(se_we),.wb_stb_i(se_stb),.wb_cyc_i(se_cyc), + .wb_ack_o(se_ack),.wb_inta_o(), + .scl_pad_i(scl0_pad_i),.scl_pad_o(scl0_pad_o),.scl_padoen_o(scl0_pad_oen_o), + .sda_pad_i(sda0_pad_i),.sda_pad_o(sda0_pad_o),.sda_padoen_o(sda0_pad_oen_o) + ); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl0_pin(.O(scl0_pad_i), .IO(scl0), .I(scl0_pad_o), .T(scl0_pad_oen_o)); + IOBUF sda0_pin(.O(sda0_pad_i), .IO(sda0), .I(sda0_pad_o), .T(sda0_pad_oen_o)); + + assign se_dat_i[31:8] = 24'd0; + + //////////////////////////////////////////////////////////////////// + // I2C1 -- Slave #f + //////////////////////////////////////////////////////////////////// + wire scl1_pad_i, scl1_pad_o, scl1_pad_oen_o; + wire sda1_pad_i, sda1_pad_o, sda1_pad_oen_o; + + i2c_master_top #(.ARST_LVL(1)) i2c1 + ( + .wb_clk_i(clk_div2),.wb_rst_i(rst_div2),.arst_i(1'b0), + .wb_adr_i(sf_adr[4:2]),.wb_dat_i(sf_dat_o[7:0]),.wb_dat_o(sf_dat_i[7:0]), + .wb_we_i(sf_we),.wb_stb_i(sf_stb),.wb_cyc_i(sf_cyc), + .wb_ack_o(sf_ack),.wb_inta_o(), + .scl_pad_i(scl1_pad_i),.scl_pad_o(scl1_pad_o),.scl_padoen_o(scl1_pad_oen_o), + .sda_pad_i(sda1_pad_i),.sda_pad_o(sda1_pad_o),.sda_padoen_o(sda1_pad_oen_o) + ); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl1_pin(.O(scl1_pad_i), .IO(scl1), .I(scl1_pad_o), .T(scl1_pad_oen_o)); + IOBUF sda1_pin(.O(sda1_pad_i), .IO(sda1), .I(sda1_pad_o), .T(sda1_pad_oen_o)); + + assign sf_dat_i[31:8] = 24'd0; + + + +endmodule //soft_ctrl diff --git a/fpga/usrp3/top/x300/timing.xdc b/fpga/usrp3/top/x300/timing.xdc new file mode 100644 index 000000000..1b913456c --- /dev/null +++ b/fpga/usrp3/top/x300/timing.xdc @@ -0,0 +1,603 @@ +# +# Copyright 2014 Ettus Research LLC +# + +#******************************************************************************* +## Primary clock definitions + +# Define clocks +create_clock -name FPGA_CLK -period 5.000 -waveform {0.000 2.500} [get_ports FPGA_CLK_p] +create_clock -name FPGA_REFCLK -period 32.563 -waveform {0.000 16.281} [get_ports FPGA_REFCLK_10MHz_p] +create_clock -name FPGA_125MHz_CLK -period 8.000 -waveform {0.000 4.000} [get_ports FPGA_125MHz_CLK] +create_clock -name DB0_ADC_DCLK -period 5.000 -waveform {0.000 2.500} [get_ports DB0_ADC_DCLK_P] +create_clock -name DB1_ADC_DCLK -period 5.000 -waveform {0.000 2.500} [get_ports DB1_ADC_DCLK_P] +create_clock -name IoRxClock -period 4.000 -waveform {0.000 2.000} [get_ports IoRxClock] +# Create virtual clock aligned with FPGA_CLK that is twice the frequency for DAC IO Timing. +create_clock -name VIRT_DAC_CLK -period 2.500 -waveform {0.000 1.250} + +# Set clock properties +set_input_jitter [get_clocks FPGA_CLK] 0.05 + +set var_fpga_clk_delay 1.545 ;# LMK_Delay=0.900ns, LMK->FPGA=0.645ns +set var_fpga_clk_skew 0.100 +set_clock_latency -source -early [expr $var_fpga_clk_delay - $var_fpga_clk_skew/2] [get_clocks FPGA_CLK] +set_clock_latency -source -late [expr $var_fpga_clk_delay + $var_fpga_clk_skew/2] [get_clocks FPGA_CLK] + +set var_adc_clk_delay 8.440 ;# LMK->ADC=1.04ns, ADC->FPGA=0.750ns, ADC=6.65ns=(0.69*5ns)+5.7-2.5 +set var_adc_clk_skew 0.500 ;# The real skew is ~3.5ns with which we will not meet static timing. Ignore skew by temp variations. +set_clock_latency -source -early [expr $var_adc_clk_delay - $var_adc_clk_skew/2] [get_clocks DB0_ADC_DCLK] +set_clock_latency -source -late [expr $var_adc_clk_delay + $var_adc_clk_skew/2] [get_clocks DB0_ADC_DCLK] +set_clock_latency -source -early [expr $var_adc_clk_delay - $var_adc_clk_skew/2] [get_clocks DB1_ADC_DCLK] +set_clock_latency -source -late [expr $var_adc_clk_delay + $var_adc_clk_skew/2] [get_clocks DB1_ADC_DCLK] + +# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain +# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent, +# lock the locations of the MMCM and BUFG to generate radio_clk. +set_property LOC MMCME2_ADV_X0Y0 [get_cells -hierarchical -filter {NAME =~ "*radio_clk_gen/*mmcm_adv_inst"}] +set_property LOC BUFGCTRL_X0Y8 [get_cells -hierarchical -filter {NAME =~ "*radio_clk_gen/*clkout1_buf"}] + +# The PCIe specific 40MHz and 200MHz clocks are only active in clock regious X0Y0 and X1Y0 so we use BUFHs +# to distribute them. To do so, we have to use a PLL because the MMCM in that region is used by radio_clk_gen +# Since that MMCM is LOC constrained, we must LOC constrain this PLL as well. +set_property LOC PLLE2_ADV_X0Y0 [get_cells -hierarchical -filter {NAME =~ "*pcie_clk_gen/*plle2_adv_inst"}] + + +#******************************************************************************* +## Generated clock definitions + +create_generated_clock -name DB0_DAC_DCI -source [get_pins gen_db0/oddr_clk/C] -divide_by 1 [get_ports DB0_DAC_DCI_P] +create_generated_clock -name DB1_DAC_DCI -source [get_pins gen_db1/oddr_clk/C] -divide_by 1 [get_ports DB1_DAC_DCI_P] +create_generated_clock -name IoTxClock -multiply_by 1 \ + -source [get_pins -hier -filter {NAME =~ lvfpga_chinch_inst/*/TxClockGenx/TxUseMmcm.TxMmcm/CLKOUT0}] \ + [get_ports {IoTxClock}] + + +#******************************************************************************* +## Aliases for auto-generated clocks + +create_generated_clock -name radio_clk [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen/*/CLKOUT0"}] +create_generated_clock -name radio_clk_2x [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen/*/CLKOUT1"}] +#create_generated_clock -name dac_dci_clk [get_pins -hierarchical -filter {NAME =~ "*radio_clk_gen/*/CLKOUT2"}] +create_generated_clock -name bus_clk [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen/*/CLKOUT0"}] +create_generated_clock -name bus_clk_div2 [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen/*/CLKOUT2"}] +create_generated_clock -name ce_clk [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen/*/CLKOUT3"}] +create_generated_clock -name ioport2_clk [get_pins -hierarchical -filter {NAME =~ "*bus_clk_gen/*/CLKFBOUT"}] +create_generated_clock -name rio40_clk [get_pins -hierarchical -filter {NAME =~ "*pcie_clk_gen/*/CLKOUT0"}] +create_generated_clock -name ioport2_idelay_ref_clk [get_pins -hierarchical -filter {NAME =~ "*pcie_clk_gen/*/CLKOUT1"}] + + +#******************************************************************************* +## Asynchronous clock groups + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ioport2_clk] +set_clock_groups -asynchronous -group [get_clocks ioport2_clk] -group [get_clocks rio40_clk] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks radio_clk] +set_clock_groups -asynchronous -group [get_clocks bus_clk_div2] -group [get_clocks radio_clk] +set_clock_groups -asynchronous -group [get_clocks ioport2_clk] -group [get_clocks IoPort2Wrapperx/RxLowSpeedClk] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks FPGA_REFCLK] +set_clock_groups -asynchronous -group [get_clocks ce_clk] -group [get_clocks bus_clk] +set_clock_groups -asynchronous -group [get_clocks ce_clk] -group [get_clocks radio_clk] + + +#******************************************************************************* +## ADC Interface + +# At 200 MHz, static timing cannot be closed so we tune data delays on the capture +# interface from software at device creation time. +# The data is center aligned wrt to the SS Clock when it is launched from the ADC +# So we tune the data IDELAYS to half the range (16) so we have slack in both directions +# In the constraints we capture this by padding the dv_before and dv_after by half the +# tuning range of the IDELAY. + +# Using typical values for ADC +set adc_clk_delay_wrt_center 0.000 ;# Possible {-1.340, -0.769, 0, 0.769} +set adc_in_dv_before_clk_edge 0.550 ;# Typical: 0.90ns +set adc_in_dv_after_clk_edge 0.550 ;# Typical: 0.95ns +set idelay_tune_range 2.500 ;# Refclk for IDELAY is 200MHz. Range of idelay is 0.5*period + +set adc_in_delay_max [expr 2.500 - $adc_in_dv_before_clk_edge - $idelay_tune_range + $adc_clk_delay_wrt_center] +set adc_in_delay_min [expr $adc_in_dv_after_clk_edge + $idelay_tune_range - $adc_clk_delay_wrt_center] + +set_input_delay -clock DB0_ADC_DCLK -max $adc_in_delay_max [get_ports {DB0_ADC_DA*}] +set_input_delay -clock DB0_ADC_DCLK -min $adc_in_delay_min [get_ports {DB0_ADC_DA*}] +set_input_delay -clock DB0_ADC_DCLK -max $adc_in_delay_max -clock_fall -add_delay [get_ports {DB0_ADC_DA*}] +set_input_delay -clock DB0_ADC_DCLK -min $adc_in_delay_min -clock_fall -add_delay [get_ports {DB0_ADC_DA*}] + +set_input_delay -clock DB0_ADC_DCLK -max $adc_in_delay_max [get_ports {DB0_ADC_DB*}] +set_input_delay -clock DB0_ADC_DCLK -min $adc_in_delay_min [get_ports {DB0_ADC_DB*}] +set_input_delay -clock DB0_ADC_DCLK -max $adc_in_delay_max -clock_fall -add_delay [get_ports {DB0_ADC_DB*}] +set_input_delay -clock DB0_ADC_DCLK -min $adc_in_delay_min -clock_fall -add_delay [get_ports {DB0_ADC_DB*}] + +set_input_delay -clock DB1_ADC_DCLK -max $adc_in_delay_max [get_ports {DB1_ADC_DA*}] +set_input_delay -clock DB1_ADC_DCLK -min $adc_in_delay_min [get_ports {DB1_ADC_DA*}] +set_input_delay -clock DB1_ADC_DCLK -max $adc_in_delay_max -clock_fall -add_delay [get_ports {DB1_ADC_DA*}] +set_input_delay -clock DB1_ADC_DCLK -min $adc_in_delay_min -clock_fall -add_delay [get_ports {DB1_ADC_DA*}] + +set_input_delay -clock DB1_ADC_DCLK -max $adc_in_delay_max [get_ports {DB1_ADC_DB*}] +set_input_delay -clock DB1_ADC_DCLK -min $adc_in_delay_min [get_ports {DB1_ADC_DB*}] +set_input_delay -clock DB1_ADC_DCLK -max $adc_in_delay_max -clock_fall -add_delay [get_ports {DB1_ADC_DB*}] +set_input_delay -clock DB1_ADC_DCLK -min $adc_in_delay_min -clock_fall -add_delay [get_ports {DB1_ADC_DB*}] + +# We use a simple synchronizer to cross ADC data over from the ADC_CLK domain to the radio_clk domain +# Use max delay constraints to ensure that the transition happens safely +set_min_delay 0.700 -from [get_cells {cap_db0/gen_lvds_pins[*].iddr_i}] \ + -to [get_cells {cap_db0/adc_data_rclk_reg*[*]}] +set_min_delay 0.700 -from [get_cells {cap_db1/gen_lvds_pins[*].iddr_i}] \ + -to [get_cells {cap_db1/adc_data_rclk_reg*[*]}] +set_max_delay -datapath_only 0.950 -from [get_cells {cap_db0/gen_lvds_pins[*].iddr_i}] \ + -to [get_cells {cap_db0/adc_data_rclk_reg*[*]}] +set_max_delay -datapath_only 0.950 -from [get_cells {cap_db1/gen_lvds_pins[*].iddr_i}] \ + -to [get_cells {cap_db1/adc_data_rclk_reg*[*]}] + +# We also need to location constrain the first flops in the synchronizer to help the tools +# meet timing reliably + +# ADC0 +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[0]}] +set_property LOC SLICE_X1Y192 [get_cells {cap_db0/adc_data_rclk_reg*[0]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[1]}] +set_property LOC SLICE_X1Y192 [get_cells {cap_db0/adc_data_rclk_reg*[1]}] +set_property BEL AFF [get_cells {cap_db0/adc_data_rclk_reg*[2]}] +set_property LOC SLICE_X1Y190 [get_cells {cap_db0/adc_data_rclk_reg*[2]}] +set_property BEL BFF [get_cells {cap_db0/adc_data_rclk_reg*[3]}] +set_property LOC SLICE_X1Y190 [get_cells {cap_db0/adc_data_rclk_reg*[3]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[4]}] +set_property LOC SLICE_X1Y188 [get_cells {cap_db0/adc_data_rclk_reg*[4]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[5]}] +set_property LOC SLICE_X1Y188 [get_cells {cap_db0/adc_data_rclk_reg*[5]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[6]}] +set_property LOC SLICE_X1Y186 [get_cells {cap_db0/adc_data_rclk_reg*[6]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[7]}] +set_property LOC SLICE_X1Y186 [get_cells {cap_db0/adc_data_rclk_reg*[7]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[8]}] +set_property LOC SLICE_X1Y184 [get_cells {cap_db0/adc_data_rclk_reg*[8]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[9]}] +set_property LOC SLICE_X1Y184 [get_cells {cap_db0/adc_data_rclk_reg*[9]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[10]}] +set_property LOC SLICE_X1Y182 [get_cells {cap_db0/adc_data_rclk_reg*[10]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[11]}] +set_property LOC SLICE_X1Y182 [get_cells {cap_db0/adc_data_rclk_reg*[11]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[12]}] +set_property LOC SLICE_X1Y180 [get_cells {cap_db0/adc_data_rclk_reg*[12]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[13]}] +set_property LOC SLICE_X1Y180 [get_cells {cap_db0/adc_data_rclk_reg*[13]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[14]}] +set_property LOC SLICE_X1Y178 [get_cells {cap_db0/adc_data_rclk_reg*[14]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[15]}] +set_property LOC SLICE_X1Y178 [get_cells {cap_db0/adc_data_rclk_reg*[15]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[16]}] +set_property LOC SLICE_X1Y174 [get_cells {cap_db0/adc_data_rclk_reg*[16]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[17]}] +set_property LOC SLICE_X1Y174 [get_cells {cap_db0/adc_data_rclk_reg*[17]}] +set_property BEL AFF [get_cells {cap_db0/adc_data_rclk_reg*[18]}] +set_property LOC SLICE_X1Y172 [get_cells {cap_db0/adc_data_rclk_reg*[18]}] +set_property BEL BFF [get_cells {cap_db0/adc_data_rclk_reg*[19]}] +set_property LOC SLICE_X1Y172 [get_cells {cap_db0/adc_data_rclk_reg*[19]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[20]}] +set_property LOC SLICE_X1Y218 [get_cells {cap_db0/adc_data_rclk_reg*[20]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[21]}] +set_property LOC SLICE_X1Y218 [get_cells {cap_db0/adc_data_rclk_reg*[21]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[22]}] +set_property LOC SLICE_X1Y198 [get_cells {cap_db0/adc_data_rclk_reg*[22]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[23]}] +set_property LOC SLICE_X1Y198 [get_cells {cap_db0/adc_data_rclk_reg*[23]}] +set_property BEL AFF [get_cells {cap_db0/adc_data_rclk_reg*[24]}] +set_property LOC SLICE_X1Y196 [get_cells {cap_db0/adc_data_rclk_reg*[24]}] +set_property BEL BFF [get_cells {cap_db0/adc_data_rclk_reg*[25]}] +set_property LOC SLICE_X1Y196 [get_cells {cap_db0/adc_data_rclk_reg*[25]}] +set_property BEL A5FF [get_cells {cap_db0/adc_data_rclk_reg*[26]}] +set_property LOC SLICE_X1Y194 [get_cells {cap_db0/adc_data_rclk_reg*[26]}] +set_property BEL B5FF [get_cells {cap_db0/adc_data_rclk_reg*[27]}] +set_property LOC SLICE_X1Y194 [get_cells {cap_db0/adc_data_rclk_reg*[27]}] + +# ADC1 +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[0]}] +set_property LOC SLICE_X1Y298 [get_cells {cap_db1/adc_data_rclk_reg*[0]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[1]}] +set_property LOC SLICE_X1Y298 [get_cells {cap_db1/adc_data_rclk_reg*[1]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[2]}] +set_property LOC SLICE_X1Y284 [get_cells {cap_db1/adc_data_rclk_reg*[2]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[3]}] +set_property LOC SLICE_X1Y284 [get_cells {cap_db1/adc_data_rclk_reg*[3]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[4]}] +set_property LOC SLICE_X1Y288 [get_cells {cap_db1/adc_data_rclk_reg*[4]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[5]}] +set_property LOC SLICE_X1Y288 [get_cells {cap_db1/adc_data_rclk_reg*[5]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[6]}] +set_property LOC SLICE_X1Y282 [get_cells {cap_db1/adc_data_rclk_reg*[6]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[7]}] +set_property LOC SLICE_X1Y282 [get_cells {cap_db1/adc_data_rclk_reg*[7]}] +set_property BEL AFF [get_cells {cap_db1/adc_data_rclk_reg*[8]}] +set_property LOC SLICE_X1Y296 [get_cells {cap_db1/adc_data_rclk_reg*[8]}] +set_property BEL BFF [get_cells {cap_db1/adc_data_rclk_reg*[9]}] +set_property LOC SLICE_X1Y296 [get_cells {cap_db1/adc_data_rclk_reg*[9]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[10]}] +set_property LOC SLICE_X1Y280 [get_cells {cap_db1/adc_data_rclk_reg*[10]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[11]}] +set_property LOC SLICE_X1Y280 [get_cells {cap_db1/adc_data_rclk_reg*[11]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[12]}] +set_property LOC SLICE_X1Y286 [get_cells {cap_db1/adc_data_rclk_reg*[12]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[13]}] +set_property LOC SLICE_X1Y286 [get_cells {cap_db1/adc_data_rclk_reg*[13]}] +set_property BEL AFF [get_cells {cap_db1/adc_data_rclk_reg*[14]}] +set_property LOC SLICE_X1Y274 [get_cells {cap_db1/adc_data_rclk_reg*[14]}] +set_property BEL BFF [get_cells {cap_db1/adc_data_rclk_reg*[15]}] +set_property LOC SLICE_X1Y274 [get_cells {cap_db1/adc_data_rclk_reg*[15]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[16]}] +set_property LOC SLICE_X1Y272 [get_cells {cap_db1/adc_data_rclk_reg*[16]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[17]}] +set_property LOC SLICE_X1Y272 [get_cells {cap_db1/adc_data_rclk_reg*[17]}] +set_property BEL AFF [get_cells {cap_db1/adc_data_rclk_reg*[18]}] +set_property LOC SLICE_X1Y290 [get_cells {cap_db1/adc_data_rclk_reg*[18]}] +set_property BEL BFF [get_cells {cap_db1/adc_data_rclk_reg*[19]}] +set_property LOC SLICE_X1Y290 [get_cells {cap_db1/adc_data_rclk_reg*[19]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[20]}] +set_property LOC SLICE_X1Y342 [get_cells {cap_db1/adc_data_rclk_reg*[20]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[21]}] +set_property LOC SLICE_X1Y342 [get_cells {cap_db1/adc_data_rclk_reg*[21]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[22]}] +set_property LOC SLICE_X1Y294 [get_cells {cap_db1/adc_data_rclk_reg*[22]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[23]}] +set_property LOC SLICE_X1Y294 [get_cells {cap_db1/adc_data_rclk_reg*[23]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[24]}] +set_property LOC SLICE_X1Y268 [get_cells {cap_db1/adc_data_rclk_reg*[24]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[25]}] +set_property LOC SLICE_X1Y268 [get_cells {cap_db1/adc_data_rclk_reg*[25]}] +set_property BEL A5FF [get_cells {cap_db1/adc_data_rclk_reg*[26]}] +set_property LOC SLICE_X1Y292 [get_cells {cap_db1/adc_data_rclk_reg*[26]}] +set_property BEL B5FF [get_cells {cap_db1/adc_data_rclk_reg*[27]}] +set_property LOC SLICE_X1Y292 [get_cells {cap_db1/adc_data_rclk_reg*[27]}] + +# IODELAY constraints +set_property IODELAY_GROUP ADC_CAP_IODELAY_GRP [get_cells adc_cap_idelayctrl_i] +set_property IODELAY_GROUP ADC_CAP_IODELAY_GRP [get_cells {cap_db0/gen_lvds_pins[*].idelay_i}] +set_property IODELAY_GROUP ADC_CAP_IODELAY_GRP [get_cells {cap_db1/gen_lvds_pins[*].idelay_i}] + + +#******************************************************************************* +## DAC Interface + +# DCI System-Sync Timing + +# The DCI clock driven to the DACs must obey setup and hold timing with respect to +# the reference clock driven to the DACs (same as the FPGA_CLK, driven by the LMK). +# Define the minimum and maximum clock propagation delays through the FPGA in order to +# meet this system-wide timing. +set dac0_clk_offset_out_max 1.350 +set dac0_clk_offset_out_min 0.225 +set dac1_clk_offset_out_max 1.350 +set dac1_clk_offset_out_min 0.225 + +# The absolute latest the DCI clock should change is the sum of the maximum delay through +# the FPGA and the latest the sourcing clock (FPGA_CLK) can arrive at the FPGA. This is an +# artifact of the set_clock_latency constraints and doing system-wide timing. Typically, +# these Early/Late delays are automatically compensated for by the analyzer. However this +# is only the case for signals that start and end in the same PRIMARY clock domain. In +# our case, VIRT_DAC_CLK and radio_clk are not the same clock domain and +# therefore we have to manually remove the added Early/Late values from analysis. +set dac0_dci_out_delay_max [expr $dac0_clk_offset_out_max + $var_fpga_clk_delay + $var_fpga_clk_skew/2] +set dac0_dci_out_delay_min [expr $dac0_clk_offset_out_min + $var_fpga_clk_delay - $var_fpga_clk_skew/2] +set dac1_dci_out_delay_max [expr $dac1_clk_offset_out_max + $var_fpga_clk_delay + $var_fpga_clk_skew/2] +set dac1_dci_out_delay_min [expr $dac1_clk_offset_out_min + $var_fpga_clk_delay - $var_fpga_clk_skew/2] + +# The min set_output_delay is the earliest the DCI clock should change BEFORE the current +# edge of interest. Here it is inverted (negated) because the earliest the clock should +# change is dac0_dci_out_delay_min AFTER the launch edge of the virtual clock. +set_output_delay -clock VIRT_DAC_CLK -min [expr - $dac0_dci_out_delay_min] [get_ports {DB0_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -min [expr - $dac0_dci_out_delay_min] -clock_fall -add_delay [get_ports {DB0_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -min [expr - $dac1_dci_out_delay_min] [get_ports {DB1_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -min [expr - $dac1_dci_out_delay_min] -clock_fall -add_delay [get_ports {DB1_DAC_DCI_*}] + +# The max set_output_delay is the time the data should be stable before the next +# edge of interest. Since we are DDR, this is the falling edge. Hence we subtract +# latest time the data should change, dac0_dci_out_delay_max, from the falling edge +# time, dci_period/2 = 1.25ns. +set_output_delay -clock VIRT_DAC_CLK -max [expr 1.25 - $dac0_dci_out_delay_max] [get_ports {DB0_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -max [expr 1.25 - $dac0_dci_out_delay_max] -clock_fall -add_delay [get_ports {DB0_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -max [expr 1.25 - $dac1_dci_out_delay_max] [get_ports {DB1_DAC_DCI_*}] +set_output_delay -clock VIRT_DAC_CLK -max [expr 1.25 - $dac1_dci_out_delay_max] -clock_fall -add_delay [get_ports {DB1_DAC_DCI_*}] + + +# Data to DCI Source-Sync Timing + +# The data setup and hold values must be modified in order to pass timing in +# the FPGA. The correct values are 0.270 and 0.090 for setup and hold, respectively. +# The interface fails by around 390 ps in both directions, so we subtract the failing +# amount from the actual amount to get a passing constraint. +# NOTE: Any changes to the adjustment margin below would need to be validated over +# multiple builds, process and temperature. Try not to change it! +set dac_data_setup 0.270 +set dac_data_hold 0.090 +set dac_setup_adj 0.390 +set dac_hold_adj 0.390 + +# These are real trace delays from the timing spreadsheet. Note that we are assuming +# no variability in our clock delay. +set dac0_data_delay_max 1.036 +set dac0_data_delay_min 0.898 +set dac0_clk_delay_max 0.974 +set dac0_clk_delay_min 0.974 + +set dac1_data_delay_max 0.941 +set dac1_data_delay_min 0.833 +set dac1_clk_delay_max 0.930 +set dac1_clk_delay_min 0.930 + +set dac0_out_delay_max [expr $dac0_data_delay_max - $dac0_clk_delay_min + $dac_data_setup - $dac_setup_adj] +set dac0_out_delay_min [expr $dac0_data_delay_min - $dac0_clk_delay_max - $dac_data_hold + $dac_hold_adj] +set dac1_out_delay_max [expr $dac1_data_delay_max - $dac1_clk_delay_min + $dac_data_setup - $dac_setup_adj] +set dac1_out_delay_min [expr $dac1_data_delay_min - $dac1_clk_delay_max - $dac_data_hold + $dac_hold_adj] + +set_output_delay -clock [get_clocks DB0_DAC_DCI] -max $dac0_out_delay_max [get_ports -regexp {DB0_DAC_D._. DB0_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB0_DAC_DCI] -max $dac0_out_delay_max -clock_fall -add_delay [get_ports -regexp {DB0_DAC_D._. DB0_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB0_DAC_DCI] -min $dac0_out_delay_min [get_ports -regexp {DB0_DAC_D._. DB0_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB0_DAC_DCI] -min $dac0_out_delay_min -clock_fall -add_delay [get_ports -regexp {DB0_DAC_D._. DB0_DAC_FRAME_.}] + +set_output_delay -clock [get_clocks DB1_DAC_DCI] -max $dac1_out_delay_max [get_ports -regexp {DB1_DAC_D._. DB1_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB1_DAC_DCI] -max $dac1_out_delay_max -clock_fall -add_delay [get_ports -regexp {DB1_DAC_D._. DB1_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB1_DAC_DCI] -min $dac1_out_delay_min [get_ports -regexp {DB1_DAC_D._. DB1_DAC_FRAME_.}] +set_output_delay -clock [get_clocks DB1_DAC_DCI] -min $dac1_out_delay_min -clock_fall -add_delay [get_ports -regexp {DB1_DAC_D._. DB1_DAC_FRAME_.}] + + +#******************************************************************************* +## IoPort2 + +# Constrain the location of the IDELAYCTERL associated with the interface trainer IDELAYs +set_property LOC IDELAYCTRL_X1Y0 [get_cells lvfpga_chinch_inst/IDELAYCTRLx] + +# RX Pad Input constraints +set_input_delay -clock [get_clocks IoRxClock] -max 2.580 [get_ports {irIoRx*}] +set_input_delay -clock [get_clocks IoRxClock] -min 2.280 [get_ports {irIoRx*}] +set_input_delay -clock [get_clocks IoRxClock] -max 2.580 -clock_fall -add_delay [get_ports {irIoRx*}] +set_input_delay -clock [get_clocks IoRxClock] -min 2.280 -clock_fall -add_delay [get_ports {irIoRx*}] + +# Note: The input clock N-Side ISERDES is not constrained for IO timing since +# adding an input delay does not work as the clock and data are the same. +# Since the architecture requires dedicated routes, the build-to-build +# variablilty will be zero and therefore, no separate timing constraint +# is necessary for the N-Side pin. The RxClock delay is constrained because +# of the input delay constraints on the rest of the bus. This path does, however, +# require a max delay constraint in order to override the default analysis: +set_max_delay -from [get_ports {IoRxClock*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Wrapperx/RxClockGenx/RxClockSerdes*}] \ + 2.0 -datapath_only + +# TX Pad Output constraints +set_output_delay -clock [get_clocks IoTxClock] -max 1.600 [get_ports {itIoTx*}] +set_output_delay -clock [get_clocks IoTxClock] -min 0.400 [get_ports {itIoTx*}] +set_output_delay -clock [get_clocks IoTxClock] -max 1.600 -clock_fall -add_delay [get_ports {itIoTx*}] +set_output_delay -clock [get_clocks IoTxClock] -min 0.400 -clock_fall -add_delay [get_ports {itIoTx*}] + +# These signals are all treated as async signals so no stringent timing requirements are needed. +set_max_delay -to [get_ports aIrq*] 10.000 +set_max_delay -from [get_ports aIoResetIn_n] 10.000 +set_max_delay -from [get_ports aIoReadyIn] 10.000 +set_max_delay -to [get_ports aIoReadyOut] 10.000 +set_max_delay -to [get_ports aIoPort2Restart] 10.000 +set_false_path -from [get_ports aStc3Gpio7] + +# Async reset +set_false_path -from [get_cells -hier -filter {NAME =~ lvfpga_chinch_inst/*StartupFsmx/aResetLcl*}] + +# Double Sync +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Wrapperx/tIoResetSync/DoubleSyncBasex/iDlySig*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Wrapperx/tIoResetSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Wrapperx/bIoResetAckSync/DoubleSyncBasex/iDlySig*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Wrapperx/bIoResetAckSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_ms*}] \ + 6.0 -datapath_only + +# Constrains HandshakeSLVx and IClkToPushClkHs in ControlIoDelayClockCross +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*iLclStoredData*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*ODataFlop*}] \ + 8.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/iPushToggle}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/BlkOut.oPushToggle0_ms*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/BlkOut.oPushToggle0_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/BlkOut.oPushToggle1*}] \ + 4.0 + +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*oPushToggleToReady*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*iRdyPushToggle_ms*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*iRdyPushToggle_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/*ControlIoDelayClockCrossx/*/HBx/*iRdyPushToggle*}] \ + 4.0 + +# SamplerResultsHandshake and SamplerControlHandshake +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*iLclStoredData*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*ODataFlop*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/iPushToggle}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/BlkOut.oPushToggle0_ms*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/BlkOut.oPushToggle0_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/BlkOut.oPushToggle1*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*oPushToggleToReady*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*iRdyPushToggle_ms*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*iRdyPushToggle_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/ClockSamplerBlock.Sampler*Handshake/HBx/*iRdyPushToggle*}] \ + 4.0 + +# Constrain PhyResetSync PulseSync +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/iHoldSigInx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/oHoldSigIn_msx*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/oHoldSigIn_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/oLocalSigOutCEx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/oLocalSigOutCEx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/iSigOut_msx*}] \ + 4.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/iSigOut_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPortClkDelayTrainerx/TrainerBlock.PhyResetSync/PulseSyncBasex/iSigOutx*}] \ + 4.0 + +# IoPort2 Core Clock Crossings +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoPort2Receiverx/PacketReceivedDoublesync*iDlySigx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoPort2Receiverx/PacketReceivedDoublesync*DoubleSyncAsyncInBasex*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoPort2Receiverx/PacketReceivedDoublesync*DoubleSyncAsyncInBasex/oSig_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoPort2Receiverx/PacketReceivedDoublesync*DoubleSyncAsyncInBasex/oSigx*}] \ + 6.0 + +# Handshake +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*iLclStoredData*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*ODataFlop*}] \ + 10.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/iPushToggle}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/BlkOut.oPushToggle0_ms*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/BlkOut.oPushToggle0_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/BlkOut.oPushToggle1*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*oPushToggleToReady*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*iRdyPushToggle_ms*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*iRdyPushToggle_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/CreditManager*/HBx/*iRdyPushToggle*}] \ + 4.0 + +# FIFO Clock Crossings +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/FifoFlags/ieInputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/FifoFlags/oInputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/FifoFlags/oInputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/FifoFlags/oInputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/PacketFullyReceived/ieInputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/PacketFullyReceived/oInputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/PacketFullyReceived/oInputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/PacketFullyReceived/oInputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/ieInputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/oInputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/oInputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/oInputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/oeOutputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/iOutputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/iOutputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/iOutputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/ieInputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/oInputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/oInputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/oInputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/oeOutputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/iOutputCountGray_msx*}] \ + 5.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/iOutputCountGray_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/iOutputCountGrayx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.FifoFlags/oeOutputCountGrayx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo*DualPortRAMx*oDlyAddr*}] \ + 5.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*iLclStoredData*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*ODataFlop*}] \ + 10.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/iPushToggle}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/BlkOut.oPushToggle0_ms*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/BlkOut.oPushToggle0_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/BlkOut.oPushToggle1*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*oPushToggleToReady*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*iRdyPushToggle_ms*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*iRdyPushToggle_ms*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/TransmitSide.IoTransmitFifox/CreditManager.HandshakeCredits/HBx/*iRdyPushToggle*}] \ + 4.0 + +# Double Sync +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/Startup.DoubleSyncEnableTransmit/iDlySigx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/Startup.DoubleSyncEnableTransmit/*DoubleSyncAsyncInBasex/oSig_msx*}] \ + 6.0 -datapath_only +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/Startup.DoubleSyncEnableTransmit/*DoubleSyncAsyncInBasex/oSig_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2x/IoPort2Basex/Startup.DoubleSyncEnableTransmit/*DoubleSyncAsyncInBasex/oSigx*}] \ + 4.0 +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/DoubleSyncWidePortMode.DoubleSync*WidePortMode/iDlySigx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/DoubleSyncWidePortMode.DoubleSync*WidePortMode/DoubleSyncAsyncInBasex*}] \ + 6.0 -datapath_only -quiet +set_max_delay -from [get_cells -hier -filter {NAME =~ *IoPort2Basex/DoubleSyncWidePortMode.DoubleSync*WidePortMode/DoubleSyncAsyncInBasex/oSig_msx*}] \ + -to [get_cells -hier -filter {NAME =~ *IoPort2Basex/DoubleSyncWidePortMode.DoubleSync*WidePortMode/DoubleSyncAsyncInBasex/oSigx*}] \ + 5.0 -quiet + + +#******************************************************************************* +## PPS Timing + +# Constrain delay from PPS input pins to the first stage synchronizer flip-flop +set_max_delay 5.000 -from [get_ports EXT_PPS_IN] \ + -to [get_pins -hier -filter {NAME =~ */pps_sync_refclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] \ + -datapath_only +set_min_delay 2.500 -from [get_ports EXT_PPS_IN] \ + -to [get_pins -hier -filter {NAME =~ */pps_sync_refclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] +set_max_delay 5.000 -from [get_ports GPS_PPS_OUT] \ + -to [get_pins -hier -filter {NAME =~ */pps_sync_refclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] \ + -datapath_only +set_min_delay 2.500 -from [get_ports GPS_PPS_OUT] \ + -to [get_pins -hier -filter {NAME =~ */pps_sync_refclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] + +# Constrain input-output delay for external PPS +set_max_delay 10.000 -from [get_ports EXT_PPS_IN] -to [get_ports {EXT_PPS_OUT}] -datapath_only +set_min_delay 5.000 -from [get_ports EXT_PPS_IN] -to [get_ports {EXT_PPS_OUT}] + +# Constrain delay to the first flop in radio_clk with about 1ns of slack +set_max_delay 6.500 -to [get_pins -hier -filter {NAME =~ */pps_sync_tbclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] +set_min_delay 0.500 -to [get_pins -hier -filter {NAME =~ */pps_sync_tbclk_inst/synchronizer_constrained/stages[0].value_reg[*]/D}] + +#******************************************************************************* +## Miscellaneous Interfaces + +# Dboard and Front-Panel GPIO Interfaces +# We force the registers closest to the PADs into the IOB to achieve lowest skew between individual bits +# in the parallel bus. However, as a sanity check we add the following constraints that will fail if the +# registers don't get placed in the IOB for whatever reason. +set_max_delay 6.000 -to [get_ports * -filter {(DIRECTION == OUT || DIRECTION == INOUT) && NAME =~ "DB*_*X_IO*"}] +set_max_delay 3.000 -from [get_ports * -filter {(DIRECTION == IN || DIRECTION == INOUT) && NAME =~ "DB*_*X_IO*"}] +set_max_delay 6.000 -to [get_ports * -filter {(DIRECTION == OUT || DIRECTION == INOUT) && NAME =~ "FrontPanelGpio[*]"}] +set_max_delay 3.000 -from [get_ports * -filter {(DIRECTION == IN || DIRECTION == INOUT) && NAME =~ "FrontPanelGpio[*]"}] + +# SPI Lines +set_max_delay 10.000 -datapath_only \ + -from [get_ports {DB*_*X*MISO*}] +set_max_delay 10.000 -to [get_ports {DB*_*SCLK DB*_*SEN DB*_*MOSI}] +set_max_delay 10.000 -to [get_ports {DB_SCL DB_SDA DB0_DAC_ENABLE DB1_DAC_ENABLE DB_ADC_RESET DB_DAC_RESET}] +set_max_delay 10.000 -from [get_ports {DB_SCL DB_SDA DB_DAC_MOSI}] + +# Clock distribution chip control +set_max_delay -from [get_ports {LMK_Status[*] LMK_Holdover LMK_Lock LMK_Sync}] 10.000 +set_max_delay -to [get_ports {LMK_SEN LMK_MOSI LMK_SCLK}] 10.000 +set_max_delay -to [get_ports {ClockRefSelect*}] 10.000 +set_max_delay -to [get_ports {TCXO_ENA}] 10.000 + +# GPS UART +set_max_delay -from [get_ports {GPS_SER_OUT}] 6.000 +set_max_delay -to [get_ports {GPS_SER_IN}] 6.000 +set_max_delay -from [get_ports {GPS_LOCK_OK}] 25.000 + +# Reset paths +# All asynchronous resets must be held for at least 20ns +# which is 2+2 radio_clk cycles @200MHz or 2+2 bus_clk cycles @166MHz +set_max_delay -to [get_pins {int_reset_sync/reset_int*/PRE}] 12.000 +set_max_delay -to [get_pins {int_div2_reset_sync/reset_int*/PRE}] 12.000 +set_max_delay -to [get_pins {ce_reset_sync/reset_int*/PRE}] 12.000 +set_max_delay -to [get_pins {radio_reset_sync/reset_int*/PRE}] 10.000 + +#******************************************************************************* +## Asynchronous paths + +set_false_path -to [get_pins -hier -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[*]/D}] +set_false_path -to [get_ports LED_*] +set_false_path -to [get_ports {SFPP*_RS0 SFPP*_RS1 SFPP*_SCL SFPP*_SDA SFPP*_TxDisable}] +set_false_path -from [get_ports {SFPP*_ModAbs SFPP*_RxLOS SFPP*_SCL SFPP*_SDA SFPP*_TxFault}] +set_false_path -to [get_ports GPSDO_PWR_ENA] diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v new file mode 100644 index 000000000..8fbfa39b9 --- /dev/null +++ b/fpga/usrp3/top/x300/x300.v @@ -0,0 +1,1483 @@ +/////////////////////////////////// +// +// Copyright 2016-2017 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// NOTE: A set of precompiler directives configure the features in an FPGA build +// and are listed here. These should be set exclusively using the Makefile mechanism provided. +// +// SFP0_10GBE - Ethernet Port0 is configured for 10G (default is 1G) +// SFP1_10GBE - Ethernet Port1 is configured for 10G (default is 1G) +// DEBUG_UART - Adds 115kbaud UART to GPIO pins 10 & 11 for firmware debug +// +/////////////////////////////////// + +//Defines `LVFPGA_IFACE constants +`include "../../lib/io_port2/LvFpga_Chinch_Interface.vh" + +module x300 + + ( + /////////////////////////////////// + // + // Clock sources for main FPGA clocks + // + /////////////////////////////////// + input FPGA_CLK_p, input FPGA_CLK_n, + input FPGA_125MHz_CLK, + + /////////////////////////////////// + // + // High Speed SPF+ signals and clocking + // + /////////////////////////////////// + +`ifdef BUILD_1G + input ETH_CLK_p, input ETH_CLK_n, +`endif + +`ifdef BUILD_10G + `define BUILD_10G_OR_AURORA +`endif +`ifdef BUILD_AURORA + `define BUILD_10G_OR_AURORA +`endif +`ifdef BUILD_10G_OR_AURORA + input XG_CLK_p, input XG_CLK_n, +`endif + + input SFP0_RX_p, input SFP0_RX_n, + output SFP0_TX_p, output SFP0_TX_n, + input SFP1_RX_p, input SFP1_RX_n, + output SFP1_TX_p, output SFP1_TX_n, + + /////////////////////////////////// + // + // DRAM Interface + // + /////////////////////////////////// + inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. + inout [3:0] ddr3_dqs_p, + // + output [14:0] ddr3_addr, // Address + output [2:0] ddr3_ba, // Bank Address + output ddr3_ras_n, // Row Address Strobe. + output ddr3_cas_n, // Column address select + output ddr3_we_n, // Write Enable + output ddr3_reset_n, // SDRAM reset pin. + output [0:0] ddr3_ck_p, // Differential clock + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, // Clock Enable + output [0:0] ddr3_cs_n, // Chip Select + output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... + output [0:0] ddr3_odt, // On-Die termination enable. + // + input sys_clk_i, // 100MHz clock source to generate DDR3 clocking. + /////////////////////////////////// + // + // IOPORT2 + // + /////////////////////////////////// + + //-- The IO_Port2 asynchronous handshaking pins + input aIoResetIn_n, + output aIoReadyOut, + input aIoReadyIn, + output aIoPort2Restart, + input aStc3Gpio7, + + //-- The IO_Port2 high speed receiver pins + input IoRxClock, + input IoRxClock_n, + input [15:0] irIoRxData, + input [15:0] irIoRxData_n, + input irIoRxHeader, + input irIoRxHeader_n, + + //-- The IO_Port2 high speed transmitter interface pins + output IoTxClock, + output IoTxClock_n, + output [15:0] itIoTxData, + output [15:0] itIoTxData_n, + output itIoTxHeader, + output itIoTxHeader_n, + + output aIrq, + + /////////////////////////////////// + // + // ADC and DAC interfaces + // + /////////////////////////////////// + + input DB0_ADC_DCLK_P, input DB0_ADC_DCLK_N, + input DB0_ADC_DA0_P, input DB0_ADC_DA0_N, input DB0_ADC_DB0_P, input DB0_ADC_DB0_N, + input DB0_ADC_DA1_P, input DB0_ADC_DA1_N, input DB0_ADC_DB1_P, input DB0_ADC_DB1_N, + input DB0_ADC_DA2_P, input DB0_ADC_DA2_N, input DB0_ADC_DB2_P, input DB0_ADC_DB2_N, + input DB0_ADC_DA3_P, input DB0_ADC_DA3_N, input DB0_ADC_DB3_P, input DB0_ADC_DB3_N, + input DB0_ADC_DA4_P, input DB0_ADC_DA4_N, input DB0_ADC_DB4_P, input DB0_ADC_DB4_N, + input DB0_ADC_DA5_P, input DB0_ADC_DA5_N, input DB0_ADC_DB5_P, input DB0_ADC_DB5_N, + input DB0_ADC_DA6_P, input DB0_ADC_DA6_N, input DB0_ADC_DB6_P, input DB0_ADC_DB6_N, + + input DB1_ADC_DCLK_P, input DB1_ADC_DCLK_N, + input DB1_ADC_DA0_P, input DB1_ADC_DA0_N, input DB1_ADC_DB0_P, input DB1_ADC_DB0_N, + input DB1_ADC_DA1_P, input DB1_ADC_DA1_N, input DB1_ADC_DB1_P, input DB1_ADC_DB1_N, + input DB1_ADC_DA2_P, input DB1_ADC_DA2_N, input DB1_ADC_DB2_P, input DB1_ADC_DB2_N, + input DB1_ADC_DA3_P, input DB1_ADC_DA3_N, input DB1_ADC_DB3_P, input DB1_ADC_DB3_N, + input DB1_ADC_DA4_P, input DB1_ADC_DA4_N, input DB1_ADC_DB4_P, input DB1_ADC_DB4_N, + input DB1_ADC_DA5_P, input DB1_ADC_DA5_N, input DB1_ADC_DB5_P, input DB1_ADC_DB5_N, + input DB1_ADC_DA6_P, input DB1_ADC_DA6_N, input DB1_ADC_DB6_P, input DB1_ADC_DB6_N, + + output DB0_DAC_DCI_P, output DB0_DAC_DCI_N, + output DB0_DAC_FRAME_P, output DB0_DAC_FRAME_N, + output DB0_DAC_D0_P, output DB0_DAC_D0_N, output DB0_DAC_D1_P, output DB0_DAC_D1_N, + output DB0_DAC_D2_P, output DB0_DAC_D2_N, output DB0_DAC_D3_P, output DB0_DAC_D3_N, + output DB0_DAC_D4_P, output DB0_DAC_D4_N, output DB0_DAC_D5_P, output DB0_DAC_D5_N, + output DB0_DAC_D6_P, output DB0_DAC_D6_N, output DB0_DAC_D7_P, output DB0_DAC_D7_N, + output DB0_DAC_ENABLE, + + output DB1_DAC_DCI_P, output DB1_DAC_DCI_N, + output DB1_DAC_FRAME_P, output DB1_DAC_FRAME_N, + output DB1_DAC_D0_P, output DB1_DAC_D0_N, output DB1_DAC_D1_P, output DB1_DAC_D1_N, + output DB1_DAC_D2_P, output DB1_DAC_D2_N, output DB1_DAC_D3_P, output DB1_DAC_D3_N, + output DB1_DAC_D4_P, output DB1_DAC_D4_N, output DB1_DAC_D5_P, output DB1_DAC_D5_N, + output DB1_DAC_D6_P, output DB1_DAC_D6_N, output DB1_DAC_D7_P, output DB1_DAC_D7_N, + output DB1_DAC_ENABLE, + + output DB0_SCLK, output DB0_MOSI, + output DB0_ADC_SEN, output DB0_DAC_SEN, output DB0_TX_SEN, output DB0_RX_SEN, + output DB0_RX_LSADC_SEN, output DB0_RX_LSDAC_SEN, output DB0_TX_LSADC_SEN, output DB0_TX_LSDAC_SEN, + input DB0_RX_LSADC_MISO, input DB0_RX_MISO, input DB0_TX_LSADC_MISO, input DB0_TX_MISO, + + output DB1_SCLK, output DB1_MOSI, + output DB1_ADC_SEN, output DB1_DAC_SEN, output DB1_TX_SEN, output DB1_RX_SEN, + output DB1_RX_LSADC_SEN, output DB1_RX_LSDAC_SEN, output DB1_TX_LSADC_SEN, output DB1_TX_LSDAC_SEN, + input DB1_RX_LSADC_MISO, input DB1_RX_MISO, input DB1_TX_LSADC_MISO, input DB1_TX_MISO, + output DB_DAC_SCLK, inout DB_DAC_MOSI, + + output DB_ADC_RESET, output DB_DAC_RESET, + + inout DB_SCL, inout DB_SDA, + + /////////////////////////////////// + // + // GPIO/LEDS/Etc + // + /////////////////////////////////// + + inout [11:0] FrontPanelGpio, + + output LED_ACT1, output LED_ACT2, + output LED_LINK1, output LED_LINK2, + + output LED_PPS, output LED_REFLOCK, output LED_GPSLOCK, + output LED_LINKSTAT, output LED_LINKACT, + output LED_RX1_RX, output LED_RX2_RX, + output LED_TXRX1_RX, output LED_TXRX1_TX, + output LED_TXRX2_RX, output LED_TXRX2_TX, + inout [15:0] DB0_TX_IO, + inout [15:0] DB0_RX_IO, + inout [15:0] DB1_TX_IO, + inout [15:0] DB1_RX_IO, + + /////////////////////////////////// + // + // LMK CLock chip + // + /////////////////////////////////// + + input [1:0] LMK_Status, + input LMK_Holdover, + input LMK_Lock, + input LMK_Sync, //not used, we do soft sync + output LMK_SEN, output LMK_MOSI, output LMK_SCLK, + + /////////////////////////////////// + // + // GPSDO and Clock Refs + // + /////////////////////////////////// + + output [1:0] ClockRefSelect, + output GPS_SER_IN, input GPS_SER_OUT, + input GPS_PPS_OUT, input EXT_PPS_IN, + output EXT_PPS_OUT, input GPS_LOCK_OK, + output GPSDO_PWR_ENA, output TCXO_ENA, + + output CPRI_CLK_OUT_P, output CPRI_CLK_OUT_N, + + input FPGA_REFCLK_10MHz_p, input FPGA_REFCLK_10MHz_n, + + /////////////////////////////////// + // + // Supporting I/O for SPF+ interfaces + // (non high speed stuff) + // + /////////////////////////////////// + + inout SFPP0_SCL, inout SFPP0_SDA, + input SFPP0_ModAbs, + input SFPP0_RxLOS, // High if module asserts Loss of Signal + input SFPP0_TxFault, // Current 10G PMA/PCS apparently ignores this signal. + output SFPP0_RS0, // These are actually open drain outputs + output SFPP0_RS1, // CAUTION! Take great care, this signal shorted to VeeR on SFP module. + output SFPP0_TxDisable, // These are actually open drain outputs + + inout SFPP1_SCL, inout SFPP1_SDA, + input SFPP1_ModAbs, + input SFPP1_RxLOS, // High if module asserts Loss of Signal + input SFPP1_TxFault, // Current 10G PMA/PCS apparently ignores this signal. + output SFPP1_RS0, // These are actually open drain outputs + output SFPP1_RS1, // CAUTION! Take great care, this signal shorted to VeeR on SFP module. + output SFPP1_TxDisable, // These are actually open drain outputs + + /////////////////////////////////// + // + // Misc. + // + /////////////////////////////////// + + input FPGA_PUDC_B +); + + wire radio_clk, radio_clk_2x, dac_dci_clk; + wire global_rst, radio_rst, bus_rst, bus_rst_div2, ce_rst, adc_idlyctrl_rst; + wire [3:0] sw_rst; + wire [2:0] led0, led1; + + //////////////////////////////////////////////////////////////////// + // + // Generate Bus Clock and PCIe Clocks. + // Source clock comes from U19 which is fixed freq + // and bufferd to be used by STC3 also (Page17 schematics). + // + //////////////////////////////////////////////////////////////////// + + wire fpga_clk125, bus_clk, bus_clk_div2, ce_clk, ioport2_clk, rio40_clk, ioport2_idelay_ref_clk; + wire bus_clk_locked, rio40_clk_locked, rio40_clk_reset; + + IBUFG fpga_125MHz_clk_buf ( + .I(FPGA_125MHz_CLK), + .O(fpga_clk125)); + + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940 + // CLK_OUT2___125.000______0.000______50.0_______91.831_____73.940 + // CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940 + // CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940 + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary_________125.000____________0.010 + + localparam BUS_CLK_RATE = 32'd187500000; + + wire ioport2_clk_unbuf; + + bus_clk_gen bus_clk_gen ( + .CLK_IN1(fpga_clk125), + .CLKFB_IN(ioport2_clk), + .CLK_OUT1(bus_clk), + .CLK_OUT2_UNBUF(/* unused */), //This exists to make the IP generate a 125MHz FB clock + .CLK_OUT3(bus_clk_div2), //bus_clk divided by 2. used by sc/zpu + .CLK_OUT4(ce_clk), + .CLKFB_OUT(ioport2_clk_unbuf), + .LOCKED(bus_clk_locked)); + + BUFG ioport2_clk_bufg_i ( + .O(ioport2_clk), + .I(ioport2_clk_unbuf)); + + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // CLK_OUT1____40.000______0.000______50.0______353.417_____96.948 + // CLK_OUT2___200.000______0.000______50.0______192.299_____96.948 + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary_________125.000____________0.100 + + //rio40_clk and ioport2_idelay_ref_clk cannot share a PLL/MMCM reset with ioport2_clk + //so they have to come from a different clocking primitive instance + pcie_clk_gen pcie_clk_gen ( + .CLK_IN1(fpga_clk125), + .CLK_OUT1(rio40_clk), + .CLK_OUT2(ioport2_idelay_ref_clk), + .RESET(rio40_clk_reset), + .LOCKED(rio40_clk_locked)); + + ///////////////////////////////////////////////////////////////////// + // + // 10MHz Reference clock + // + ////////////////////////////////////////////////////////////////////// + wire ref_clk; + IBUFDS IBUFDS_ref_clk ( + .O(ref_clk), + .I(FPGA_REFCLK_10MHz_p), + .IB(FPGA_REFCLK_10MHz_n) + ); + + ////////////////////////////////////////////////////////////////////// + // CPRI Clock output -- this is the dirty recovered clock from the MGT + // This goes to the LMK04816 which locks to it and cleans it up + // We get the clean versions back as CPRI_CLK (for the CPRI MGT) + // and FPGA_CLK (for our main rfclk) + ////////////////////////////////////////////////////////////////////// + + wire cpri_clk_out = 1'b0; // FIXME - connect to CPRI clock recovery when implemented + OBUFDS OBUFDS_cpri (.I(cpri_clk_out), .O(CPRI_CLK_OUT_P), .OB(CPRI_CLK_OUT_N)); + + ///////////////////////////////////////////////////////////////////// + // + // power-on-reset logic. + // + ////////////////////////////////////////////////////////////////////// + por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); + + ////////////////////////////////////////////////////////////////////// + wire [31:0] rx0, rx1; + wire [31:0] tx0, tx1; + wire sclk0, mosi0, miso0, sclk1, mosi1, miso1; + wire [7:0] sen0, sen1; + + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + //////////////////////////////////////////////////////////////////// + // + // Generate Radio Clocks from LMK04816 + // Radio clock is normally 200MHz, radio_clk_2x 400MHz. + // In CPRI or LTE mode, radio clock is 184.32 MHz. + // radio_clk_2x is only to be used for clocking out TX samples to DAC + // + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // CLK_OUT1___200.000______0.000______50.0_______92.799_____82.655 + // CLK_OUT2___400.000____-45.000______50.0_______81.254_____82.655 + // CLK_OUT3___400.000_____60.000______50.0_______81.254_____82.655 + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary_________200.000____________0.010 + // + //////////////////////////////////////////////////////////////////// + + wire radio_clk_locked; + radio_clk_gen radio_clk_gen ( + .clk_in1_p(FPGA_CLK_p), .clk_in1_n(FPGA_CLK_n), + .CLK_OUT1(radio_clk), .CLK_OUT2(radio_clk_2x), .CLK_OUT3(dac_dci_clk), + .RESET(sw_rst[2]), .LOCKED(radio_clk_locked)); + + //////////////////////////////////////////////////////////////////// + // + // IJB. Radio PLL doesn't seem to lock at power up. + // Probably needs AD9610 to be programmed to 120 or 200MHz to get + // an input clock thats in the ball park for PLL configuration. + // Currently use busclk PLL lock signal to control this reset, + // but we should find a better solution, perhaps a S/W controllable + // reset like the ETH PHY uses so that we can reset this clock domain + // after programming the AD9610. + // + //////////////////////////////////////////////////////////////////// + + reset_sync radio_reset_sync ( + .clk(radio_clk), + .reset_in(global_rst || !bus_clk_locked || sw_rst[1]), + .reset_out(radio_rst) + ); + + reset_sync int_reset_sync ( + .clk(bus_clk), + .reset_in(global_rst || !bus_clk_locked), + .reset_out(bus_rst) + ); + + reset_sync int_div2_reset_sync ( + .clk(bus_clk_div2), + .reset_in(global_rst || !bus_clk_locked), + .reset_out(bus_rst_div2) + ); + + reset_sync adc_idlyctrl_reset_sync ( + .clk(bus_clk), + .reset_in(global_rst || !bus_clk_locked || sw_rst[3]), + .reset_out(adc_idlyctrl_rst) + ); + + reset_sync ce_reset_sync ( + .clk(ce_clk), + .reset_in(global_rst || !bus_clk_locked), + .reset_out(ce_rst) + ); + + //////////////////////////////////////////////////////////////////// + // PPS + // Support for internal, external, and GPSDO PPS inputs + // Every attempt to minimize propagation between the external PPS + // input and outputs to support daisy-chaining the signal. + //////////////////////////////////////////////////////////////////// + + wire int_pps; + wire [31:0] ref_freq; + wire ref_freq_changed; + wire ref_freq_sync_empty; + wire [71:0] ref_freq_sync_out; + reg new_ref_freq = 0; + reg [31:0] ref_freq_refclk = 10_000_000; // Default to 10 MHz reference + + // Synchronize ref_freq to ref_clk + fifo_short_2clk ref_freq_sync + ( + .rst(bus_rst), + .wr_clk(bus_clk), + .rd_clk(ref_clk), + .din({40'd0,ref_freq}), + .wr_en(ref_freq_changed), + .rd_en(new_ref_freq), + .dout(ref_freq_sync_out), + .full( /* unused */ ), + .empty(ref_freq_sync_empty), + .rd_data_count( /* unused */ ), + .wr_data_count( /* unused */ ) + ); + + // Capture the new reference frequency + always @(posedge ref_clk) begin + if (~ref_freq_sync_empty) begin + ref_freq_refclk <= ref_freq_sync_out[31:0]; + new_ref_freq <= 1'b1; + end else + new_ref_freq <= 1'b0; + end + + // Generate an internal PPS signal with a 25% duty cycle + pulse_generator #(.WIDTH(32)) pps_gen + ( + .clk(ref_clk), + .reset(new_ref_freq), + .period(ref_freq_refclk), + //shift frequency by 2 bits (divide by 4) for a 25% duty cycle + .pulse_width({2'b00,ref_freq_refclk[31:2]}), + .pulse(int_pps) + ); + + // PPS MUX - selects internal, external, or gpsdo PPS + reg pps; + wire [1:0] pps_select; + wire pps_out_enb; + always @(*) begin + case(pps_select) + 2'b00 : pps = EXT_PPS_IN; + 2'b01 : pps = 1'b0; + 2'b10 : pps = int_pps; + 2'b11 : pps = GPS_PPS_OUT; + default: pps = 1'b0; + endcase + end + + // PPS out and LED + assign EXT_PPS_OUT = pps & pps_out_enb; + assign LED_PPS = ~pps; // active low LED driver + + assign LED_GPSLOCK = ~GPS_LOCK_OK; + assign LED_REFLOCK = ~LMK_Lock; + assign {LED_RX1_RX,LED_TXRX1_TX,LED_TXRX1_RX} = ~led0; // active low LED driver + assign {LED_RX2_RX,LED_TXRX2_TX,LED_TXRX2_RX} = ~led1; // active low LED driver + // Allocate SPI chip selects to various slaves. + assign {DB1_DAC_SEN, DB1_ADC_SEN, DB1_RX_LSADC_SEN, DB1_RX_LSDAC_SEN, DB1_TX_LSADC_SEN, DB1_TX_LSDAC_SEN, DB1_RX_SEN, DB1_TX_SEN} = sen1; + assign {DB0_DAC_SEN, DB0_ADC_SEN, DB0_RX_LSADC_SEN, DB0_RX_LSDAC_SEN, DB0_TX_LSADC_SEN, DB0_TX_LSDAC_SEN, DB0_RX_SEN, DB0_TX_SEN} = sen0; + + wire db_dac_mosi_int, db_dac_miso; + wire drive_dac_pin; + reg drop_dac_pin; + reg [5:0] bitcount; + reg sclk_d1; + + // Register copy of outgoing DAC clock to do synchronous edge detect. + always @(posedge radio_clk) sclk_d1 <= DB_DAC_SCLK; + + always @(posedge radio_clk) + // If neither DAC is selected keep counter reset + if(DB0_DAC_SEN & DB1_DAC_SEN) + begin + bitcount <= 6'd0; + drop_dac_pin <= 1'b0; + end + else if(~DB_DAC_SCLK & sclk_d1) + // Falling edge of SCLK detected. + begin + bitcount <= bitcount + 6'd1; + end + else if(bitcount == 0 & DB_DAC_SCLK & ~sclk_d1) + // On first rising edge store R/W bit to determine if we tristate after 8bits for a Read. + drop_dac_pin <= db_dac_mosi_int; + + assign drive_dac_pin = (bitcount < 8) | ~drop_dac_pin; + + // Both DAC's use a single SPI bus on PCB. Select appriate Radio to drive the SPi bus by looking at chip selects. + assign { DB_DAC_SCLK, db_dac_mosi_int } = ~DB0_DAC_SEN ? {sclk0, mosi0} : ~DB1_DAC_SEN ? {sclk1,mosi1} : 2'b0; + // Data to/from DAC's is bi-dir so tristate driver when reading. + assign DB_DAC_MOSI = drive_dac_pin ? db_dac_mosi_int : 1'bz; + // I/O Input buffer + assign db_dac_miso = DB_DAC_MOSI; + + // If any SPI Slave is selected (except DAC) then drive SPI clk and MOSI out onto duaghterboard. + assign { DB0_SCLK, DB0_MOSI } = (~&sen0[6:0]) ? {sclk0,mosi0} : 2'b0; + assign { DB1_SCLK, DB1_MOSI } = (~&sen1[6:0]) ? {sclk1,mosi1} : 2'b0; + + // Wired OR Mux together the possible sources of read data from SPI devices. + assign miso0 = (~DB0_RX_LSADC_SEN & DB0_RX_LSADC_MISO) | + (~DB0_RX_SEN & DB0_RX_MISO) | + (~DB0_TX_LSADC_SEN & DB0_TX_LSADC_MISO) | + (~DB0_TX_SEN & DB0_TX_MISO) | + (~DB0_DAC_SEN & db_dac_miso); + + assign miso1 = (~DB1_RX_LSADC_SEN & DB1_RX_LSADC_MISO) | + (~DB1_RX_SEN & DB1_RX_MISO) | + (~DB1_TX_LSADC_SEN & DB1_TX_LSADC_MISO) | + (~DB1_TX_SEN & DB1_TX_MISO) | + (~DB1_DAC_SEN & db_dac_miso); + + + wire [31:0] radio0_misc_out, radio1_misc_out; + wire [31:0] radio0_misc_in, radio1_misc_in; + + ///////////////////////////////////////////////////////////////////// + // + // ADC Interface for ADS62P48 + // + ///////////////////////////////////////////////////////////////////// + wire [13:0] rx0_q_inv, rx1_q_inv, rx0_i, rx1_i; + // Analog diff pairs on I side of ADC are inverted for layout reasons, but data diff pairs are all swapped as well + // so I gets a double negative, and is unchanged. Q must be inverted. + + capture_ddrlvds #( + .WIDTH(14), + .PATT_CHECKER("TRUE"), + .DATA_IDELAY_MODE("DYNAMIC"), .DATA_IDELAY_VAL(16), .DATA_IDELAY_FREF(200.0) + ) cap_db0 ( + .adc_clk_p(DB0_ADC_DCLK_P), .adc_clk_n(DB0_ADC_DCLK_N), + .adc_data_p( + {{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P}, + {DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}), + .adc_data_n( + {{DB0_ADC_DA6_N, DB0_ADC_DA5_N, DB0_ADC_DA4_N, DB0_ADC_DA3_N, DB0_ADC_DA2_N, DB0_ADC_DA1_N, DB0_ADC_DA0_N}, + {DB0_ADC_DB6_N, DB0_ADC_DB5_N, DB0_ADC_DB4_N, DB0_ADC_DB3_N, DB0_ADC_DB2_N, DB0_ADC_DB1_N, DB0_ADC_DB0_N}}), + .radio_clk(radio_clk), + .data_delay_stb(radio0_misc_out[3]), .data_delay_val(radio0_misc_out[8:4]), + .adc_cap_clk(), + .data_out({rx0_i,rx0_q_inv}), + .checker_en(radio0_misc_out[9]), .checker_locked(radio0_misc_in[3:0]), .checker_failed(radio0_misc_in[7:4]) + ); + assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 }; + + capture_ddrlvds #( + .WIDTH(14), + .PATT_CHECKER("TRUE"), + .DATA_IDELAY_MODE("DYNAMIC"), .DATA_IDELAY_VAL(16), .DATA_IDELAY_FREF(200.0) + ) cap_db1 ( + .adc_clk_p(DB1_ADC_DCLK_P), .adc_clk_n(DB1_ADC_DCLK_N), + .adc_data_p( + {{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P}, + {DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}), + .adc_data_n( + {{DB1_ADC_DA6_N, DB1_ADC_DA5_N, DB1_ADC_DA4_N, DB1_ADC_DA3_N, DB1_ADC_DA2_N, DB1_ADC_DA1_N, DB1_ADC_DA0_N}, + {DB1_ADC_DB6_N, DB1_ADC_DB5_N, DB1_ADC_DB4_N, DB1_ADC_DB3_N, DB1_ADC_DB2_N, DB1_ADC_DB1_N, DB1_ADC_DB0_N}}), + .radio_clk(radio_clk), + .data_delay_stb(radio1_misc_out[3]), .data_delay_val(radio1_misc_out[8:4]), + .adc_cap_clk(), + .data_out({rx1_i,rx1_q_inv}), + .checker_en(radio1_misc_out[9]), .checker_locked(radio1_misc_in[3:0]), .checker_failed(radio1_misc_in[7:4]) + ); + assign rx1[31:0] = { rx1_i, 2'b00, ~rx1_q_inv, 2'b00 }; + + // IDELAYCTRL to calibrate all IDELAYE2 instances in capture_ddrlvds for both sides + wire adc_idlyctrl_rdy; + IDELAYCTRL adc_cap_idelayctrl_i (.RDY(adc_idlyctrl_rdy), .REFCLK(radio_clk), .RST(adc_idlyctrl_rst)); + + ///////////////////////////////////////////////////////////////////// + // + // DAC Interface for AD9146 + // + ///////////////////////////////////////////////////////////////////// + gen_ddrlvds gen_db0 + ( + .reset(radio_rst), + .tx_clk_2x_p(DB0_DAC_DCI_P), .tx_clk_2x_n(DB0_DAC_DCI_N), + .tx_frame_p(DB0_DAC_FRAME_P), .tx_frame_n(DB0_DAC_FRAME_N), + .tx_d_p({DB0_DAC_D7_P,DB0_DAC_D6_P,DB0_DAC_D5_P,DB0_DAC_D4_P,DB0_DAC_D3_P,DB0_DAC_D2_P,DB0_DAC_D1_P,DB0_DAC_D0_P}), + .tx_d_n({DB0_DAC_D7_N,DB0_DAC_D6_N,DB0_DAC_D5_N,DB0_DAC_D4_N,DB0_DAC_D3_N,DB0_DAC_D2_N,DB0_DAC_D1_N,DB0_DAC_D0_N}), + .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk), + .i(~tx0[31:16]), .q(~tx0[15:0]), // invert b/c Analog diff pairs are swapped for layout + .sync_dacs(radio0_misc_out[10]|radio1_misc_out[10]) + ); + + + gen_ddrlvds gen_db1 + ( + .reset(radio_rst), + .tx_clk_2x_p(DB1_DAC_DCI_P), .tx_clk_2x_n(DB1_DAC_DCI_N), + .tx_frame_p(DB1_DAC_FRAME_P), .tx_frame_n(DB1_DAC_FRAME_N), + .tx_d_p({DB1_DAC_D7_P,DB1_DAC_D6_P,DB1_DAC_D5_P,DB1_DAC_D4_P,DB1_DAC_D3_P,DB1_DAC_D2_P,DB1_DAC_D1_P,DB1_DAC_D0_P}), + .tx_d_n({DB1_DAC_D7_N,DB1_DAC_D6_N,DB1_DAC_D5_N,DB1_DAC_D4_N,DB1_DAC_D3_N,DB1_DAC_D2_N,DB1_DAC_D1_N,DB1_DAC_D0_N}), + .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk), + .i(~tx1[31:16]), .q(~tx1[15:0]), // invert b/c Analog diff pairs are swapped for layout + .sync_dacs(radio0_misc_out[10]|radio1_misc_out[10]) + ); + + + wire [1:0] leds; + assign {LED_LINKSTAT, LED_LINKACT} = ~leds; + + wire [31:0] debug; + + ////////////////////////////////////////////////////////////////////// + // + // PCIe Stuff + // + ////////////////////////////////////////////////////////////////////// + + localparam IOP2_MSG_WIDTH = 64; + localparam DMA_STREAM_WIDTH = `LVFPGA_IFACE_DMA_CHAN_WIDTH; + localparam DMA_COUNT_WIDTH = `LVFPGA_IFACE_DMA_SIZE_WIDTH; + localparam NUM_TX_STREAMS = `LVFPGA_IFACE_NUM_TX_DMA_CNT; + localparam NUM_RX_STREAMS = `LVFPGA_IFACE_NUM_RX_DMA_CNT; + localparam TX_STREAM_START_IDX = `LVFPGA_IFACE_TX_DMA_INDEX; + localparam RX_STREAM_START_IDX = `LVFPGA_IFACE_RX_DMA_INDEX; + localparam DMA_DEST_WIDTH = 3; + + wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata, pcii_tdata, pcio_tdata; + wire [DMA_DEST_WIDTH-1:0] dmatx_tuser, dmarx_tuser, pcii_tuser, pcio_tuser; + wire dmatx_tvalid, dmarx_tvalid, pcii_tvalid, pcio_tvalid; + wire dmatx_tlast, dmarx_tlast, pcii_tlast, pcio_tlast; + wire dmatx_tready, dmarx_tready, pcii_tready, pcio_tready; + + wire [IOP2_MSG_WIDTH-1:0] o_iop2_msg_tdata, i_iop2_msg_tdata; + wire o_iop2_msg_tvalid, o_iop2_msg_tlast, o_iop2_msg_tready; + wire i_iop2_msg_tvalid, i_iop2_msg_tlast, i_iop2_msg_tready; + + wire pcie_usr_reg_wr, pcie_usr_reg_rd, pcie_usr_reg_rc, pcie_usr_reg_rdy; + wire [1:0] pcie_usr_reg_len; + wire [19:0] pcie_usr_reg_addr; + wire [31:0] pcie_usr_reg_data_in, pcie_usr_reg_data_out; + + wire chinch_reg_wr, chinch_reg_rd, chinch_reg_rc, chinch_reg_rdy; + wire [1:0] chinch_reg_len; + wire [19:0] chinch_reg_addr; + wire [31:0] chinch_reg_data_out; + wire [63:0] chinch_reg_data_in; + + wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2; + wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2, dmatx_tready_iop2; + + wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2; + wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2, dmarx_tready_iop2; + + //PCIe Express "Physical" DMA and Register logic + LvFpga_Chinch_Interface lvfpga_chinch_inst + ( + .aIoResetIn_n(aIoResetIn_n), + .bBusReset(), //Output + + // Clocks + .BusClk(ioport2_clk), + .Rio40Clk(rio40_clk), + .IDelayRefClk(ioport2_idelay_ref_clk), + .aRioClkPllLocked(rio40_clk_locked), + .aRioClkPllReset(rio40_clk_reset), + + // The IO_Port2 asynchronous handshaking pins + .aIoReadyOut(aIoReadyOut), + .aIoReadyIn(aIoReadyIn), + .aIoPort2Restart(aIoPort2Restart), + + // The IO_Port2 high speed receiver pins + .IoRxClock(IoRxClock), + .IoRxClock_n(IoRxClock_n), + .irIoRxData(irIoRxData), + .irIoRxData_n(irIoRxData_n), + .irIoRxHeader(irIoRxHeader), + .irIoRxHeader_n(irIoRxHeader_n), + + // The IO_Port2 high speed transmitter interface pins + .IoTxClock(IoTxClock), + .IoTxClock_n(IoTxClock_n), + .itIoTxData(itIoTxData), + .itIoTxData_n(itIoTxData_n), + .itIoTxHeader(itIoTxHeader), + .itIoTxHeader_n(itIoTxHeader_n), + + // DMA TX Fifos + .bDmaTxData(dmatx_tdata_iop2), + .bDmaTxValid(dmatx_tvalid_iop2), + .bDmaTxReady(dmatx_tready_iop2), + .bDmaTxEnabled(), + .bDmaTxFifoFullCnt(), + + // DMA RX Fifos + .bDmaRxData(dmarx_tdata_iop2), + .bDmaRxValid(dmarx_tvalid_iop2), + .bDmaRxReady(dmarx_tready_iop2), + .bDmaRxEnabled(), + .bDmaRxFifoFreeCnt(), + + // User Register Port In + .bUserRegPortInWt(pcie_usr_reg_wr), + .bUserRegPortInRd(pcie_usr_reg_rd), + .bUserRegPortInAddr(pcie_usr_reg_addr), + .bUserRegPortInData(pcie_usr_reg_data_in), + .bUserRegPortInSize(pcie_usr_reg_len), + + // User Register Port Out + .bUserRegPortOutData(pcie_usr_reg_data_out), + .bUserRegPortOutDataValid(pcie_usr_reg_rc), + .bUserRegPortOutReady(pcie_usr_reg_rdy), + + // Chinch Register Port Out + .bChinchRegPortOutWt(chinch_reg_wr), + .bChinchRegPortOutRd(chinch_reg_rd), + .bChinchRegPortOutAddr({12'h0, chinch_reg_addr}), + .bChinchRegPortOutData({32'h0, chinch_reg_data_out}), + .bChinchRegPortOutSize(chinch_reg_len), + + // User Register Port In + .bChinchRegPortInData(chinch_reg_data_in), + .bChinchRegPortInDataValid(chinch_reg_rc), + .bChinchRegPortInReady(chinch_reg_rdy), + + // Level interrupt + .aIrq(aIrq) + ); + + //PCIe Express adapter logic to link to the AXI crossbar and the WB bus + x300_pcie_int #( + .DMA_STREAM_WIDTH(DMA_STREAM_WIDTH), + .NUM_TX_STREAMS(NUM_TX_STREAMS), + .NUM_RX_STREAMS(NUM_RX_STREAMS), + .REGPORT_ADDR_WIDTH(20), + .REGPORT_DATA_WIDTH(32), + .IOP2_MSG_WIDTH(IOP2_MSG_WIDTH), + .BUS_CLK_RATE(BUS_CLK_RATE) + ) x300_pcie_int ( + .ioport2_clk(ioport2_clk), + .bus_clk(bus_clk), + .bus_rst(bus_rst), + + //DMA TX FIFOs (IoPort2 Clock Domain) + .dmatx_tdata_iop2(dmatx_tdata_iop2), + .dmatx_tvalid_iop2(dmatx_tvalid_iop2), + .dmatx_tready_iop2(dmatx_tready_iop2), + + //DMA TX FIFOs (IoPort2 Clock Domain) + .dmarx_tdata_iop2(dmarx_tdata_iop2), + .dmarx_tvalid_iop2(dmarx_tvalid_iop2), + .dmarx_tready_iop2(dmarx_tready_iop2), + + //PCIe User Regport + .pcie_usr_reg_wr(pcie_usr_reg_wr), + .pcie_usr_reg_rd(pcie_usr_reg_rd), + .pcie_usr_reg_addr(pcie_usr_reg_addr), + .pcie_usr_reg_data_in(pcie_usr_reg_data_in), + .pcie_usr_reg_len(pcie_usr_reg_len), + .pcie_usr_reg_data_out(pcie_usr_reg_data_out), + .pcie_usr_reg_rc(pcie_usr_reg_rc), + .pcie_usr_reg_rdy(pcie_usr_reg_rdy), + + //Chinch Regport + .chinch_reg_wr(chinch_reg_wr), + .chinch_reg_rd(chinch_reg_rd), + .chinch_reg_addr(chinch_reg_addr), + .chinch_reg_data_out(chinch_reg_data_out), + .chinch_reg_len(chinch_reg_len), + .chinch_reg_data_in(chinch_reg_data_in[31:0]), + .chinch_reg_rc(chinch_reg_rc), + .chinch_reg_rdy(chinch_reg_rdy), + + //DMA TX FIFO (Bus Clock Domain). Note: tuser is used for muxing. + .dmatx_tdata(dmatx_tdata), + .dmatx_tuser(dmatx_tuser), + .dmatx_tlast(dmatx_tlast), + .dmatx_tvalid(dmatx_tvalid), + .dmatx_tready(dmatx_tready), + + //DMA RX FIFO (Bus Clock Domain). Note: tuser is used for muxing. + .dmarx_tdata(dmarx_tdata), + .dmarx_tuser(dmarx_tuser), + .dmarx_tlast(dmarx_tlast), + .dmarx_tvalid(dmarx_tvalid), + .dmarx_tready(dmarx_tready), + + //Message FIFO Out (Bus Clock Domain) + .rego_tdata(o_iop2_msg_tdata), + .rego_tvalid(o_iop2_msg_tvalid), + .rego_tlast(o_iop2_msg_tlast), + .rego_tready(o_iop2_msg_tready), + + //Message FIFO In (Bus Clock Domain) + .regi_tdata(i_iop2_msg_tdata), + .regi_tvalid(i_iop2_msg_tvalid), + .regi_tlast(i_iop2_msg_tlast), + .regi_tready(i_iop2_msg_tready), + + //Misc + .misc_status({15'h0, aStc3Gpio7}), + .debug() + ); + + // The PCIe logic will tend to stay close to the physical IoPort2 pins + // so add an additional stage of pipelining to give the tool more routing + // slack. This is significantly help timing closure. + + axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcii_pipeline_srl ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({dmatx_tuser, dmatx_tlast, dmatx_tdata}), .i_tvalid(dmatx_tvalid), .i_tready(dmatx_tready), + .o_tdata({pcii_tuser, pcii_tlast, pcii_tdata}), .o_tvalid(pcii_tvalid), .o_tready(pcii_tready), + .space(), .occupied()); + + axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1+DMA_DEST_WIDTH)) pcio_pipeline_srl ( + .clk(bus_clk), .reset(bus_rst), .clear(1'b0), + .i_tdata({pcio_tuser, pcio_tlast, pcio_tdata}), .i_tvalid(pcio_tvalid), .i_tready(pcio_tready), + .o_tdata({dmarx_tuser, dmarx_tlast, dmarx_tdata}), .o_tvalid(dmarx_tvalid), .o_tready(dmarx_tready), + .space(), .occupied()); + + ////////////////////////////////////////////////////////////////////// + // + // Configure SFP+ clocking + // + ////////////////////////////////////////////////////////////////////// +`ifdef BUILD_1G + wire gige_refclk, gige_refclk_bufg; + + one_gige_phy_clk_gen gige_clk_gen_i ( + .refclk_p(ETH_CLK_p), + .refclk_n(ETH_CLK_n), + .refclk(gige_refclk), + .refclk_bufg(gige_refclk_bufg) + ); +`endif +`ifdef BUILD_10G + wire xgige_refclk; + wire xgige_clk156; + wire xgige_dclk; + + ten_gige_phy_clk_gen xgige_clk_gen_i ( + .areset(global_rst | sw_rst[0]), + .refclk_p(XG_CLK_p), + .refclk_n(XG_CLK_n), + .refclk(xgige_refclk), + .clk156(xgige_clk156), + .dclk(xgige_dclk) + ); + `ifdef BUILD_AURORA + wire aurora_refclk = xgige_refclk; + wire aurora_refclk_bufg = xgige_clk156; + wire aurora_init_clk = xgige_dclk; + `endif +`else + `ifdef BUILD_AURORA + wire aurora_refclk; + wire aurora_refclk_bufg; + wire aurora_init_clk; + + aurora_phy_clk_gen aurora_clk_gen_i ( + .areset(global_rst | sw_rst[0]), + .refclk_p(XG_CLK_p), + .refclk_n(XG_CLK_n), + .refclk(aurora_refclk), + .clk156(aurora_refclk_bufg), + .init_clk(aurora_init_clk) + ); + `endif +`endif + + wire sfp0_gt_refclk, sfp1_gt_refclk; + wire sfp0_gb_refclk, sfp1_gb_refclk; + wire sfp0_misc_clk, sfp1_misc_clk; + +`ifdef SFP0_10GBE + assign sfp0_gt_refclk = xgige_refclk; + assign sfp0_gb_refclk = xgige_clk156; + assign sfp0_misc_clk = xgige_dclk; +`endif +`ifdef SFP0_1GBE + assign sfp0_gt_refclk = gige_refclk; + assign sfp0_gb_refclk = gige_refclk_bufg; + assign sfp0_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP0_AURORA + assign sfp0_gt_refclk = aurora_refclk; + assign sfp0_gb_refclk = aurora_refclk_bufg; + assign sfp0_misc_clk = aurora_init_clk; +`endif + +`ifdef SFP1_10GBE + assign sfp1_gt_refclk = xgige_refclk; + assign sfp1_gb_refclk = xgige_clk156; + assign sfp1_misc_clk = xgige_dclk; +`endif +`ifdef SFP1_1GBE + assign sfp1_gt_refclk = gige_refclk; + assign sfp1_gb_refclk = gige_refclk_bufg; + assign sfp1_misc_clk = gige_refclk_bufg; +`endif +`ifdef SFP1_AURORA + assign sfp1_gt_refclk = aurora_refclk; + assign sfp1_gb_refclk = aurora_refclk_bufg; + assign sfp1_misc_clk = aurora_init_clk; +`endif + + ////////////////////////////////////////////////////////////////////// + // + // SFP+ PORT0 + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] sfp0_rx_tdata, sfp0_tx_tdata; + wire [3:0] sfp0_rx_tuser, sfp0_tx_tuser; + wire sfp0_rx_tlast, sfp0_tx_tlast, sfp0_rx_tvalid, sfp0_tx_tvalid, sfp0_rx_tready, sfp0_tx_tready; + wire [15:0] sfp0_phy_status; + + wire [31:0] sfp0_wb_dat_i; + wire [31:0] sfp0_wb_dat_o; + wire [15:0] sfp0_wb_adr; + wire sfp0_wb_ack, sfp0_wb_stb, sfp0_wb_cyc, sfp0_wb_we, sfp0_wb_int; + + wire sfp0_link_up, sfp0_activity; + + x300_sfpp_io_core #( +`ifdef SFP0_10GBE + .PROTOCOL("10GbE"), +`endif +`ifdef SFP0_1GBE + .PROTOCOL("1GbE"), +`endif +`ifdef SFP0_AURORA + .PROTOCOL("Aurora"), +`endif + .PORTNUM(8'd0) + ) sfpp_io_i0 ( + .areset(global_rst | sw_rst[0]), + .gt_refclk(sfp0_gt_refclk), + .gb_refclk(sfp0_gb_refclk), + .misc_clk(sfp0_misc_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + .bus_rst_div2(bus_rst_div2), + .bus_clk_div2(bus_clk_div2), + + .txp(SFP0_TX_p), + .txn(SFP0_TX_n), + .rxp(SFP0_RX_p), + .rxn(SFP0_RX_n), + + .sfpp_rxlos(SFPP0_RxLOS), + .sfpp_tx_fault(SFPP0_TxFault), + .sfpp_tx_disable(SFPP0_TxDisable), + + .s_axis_tdata(sfp0_tx_tdata), + .s_axis_tuser(sfp0_tx_tuser), + .s_axis_tlast(sfp0_tx_tlast), + .s_axis_tvalid(sfp0_tx_tvalid), + .s_axis_tready(sfp0_tx_tready), + + .m_axis_tdata(sfp0_rx_tdata), + .m_axis_tuser(sfp0_rx_tuser), + .m_axis_tlast(sfp0_rx_tlast), + .m_axis_tvalid(sfp0_rx_tvalid), + .m_axis_tready(sfp0_rx_tready), + + .wb_adr_i(sfp0_wb_adr), + .wb_cyc_i(sfp0_wb_cyc), + .wb_dat_i(sfp0_wb_dat_o), + .wb_stb_i(sfp0_wb_stb), + .wb_we_i(sfp0_wb_we), + .wb_ack_o(sfp0_wb_ack), + .wb_dat_o(sfp0_wb_dat_i), + .wb_int_o(sfp0_wb_int), + + .phy_status(sfp0_phy_status), + .link_up(sfp0_link_up), + .activity(sfp0_activity) + ); + + // LEDs are driven with negative logic. + assign LED_LINK2 = ~sfp0_link_up; + assign LED_ACT2 = ~sfp0_activity; + + + ////////////////////////////////////////////////////////////////////// + // + // SFP+ PORT1 + // + ////////////////////////////////////////////////////////////////////// + + wire [63:0] sfp1_rx_tdata, sfp1_tx_tdata; + wire [3:0] sfp1_rx_tuser, sfp1_tx_tuser; + wire sfp1_rx_tlast, sfp1_tx_tlast, sfp1_rx_tvalid, sfp1_tx_tvalid, sfp1_rx_tready, sfp1_tx_tready; + wire [15:0] sfp1_phy_status; + + wire [31:0] sfp1_wb_dat_i; + wire [31:0] sfp1_wb_dat_o; + wire [15:0] sfp1_wb_adr; + wire sfp1_wb_ack, sfp1_wb_stb, sfp1_wb_cyc, sfp1_wb_we, sfp1_wb_int; + + wire sfp1_link_up, sfp1_activity; + + x300_sfpp_io_core #( +`ifdef SFP1_10GBE + .PROTOCOL("10GbE"), +`endif +`ifdef SFP1_1GBE + .PROTOCOL("1GbE"), +`endif +`ifdef SFP1_AURORA + .PROTOCOL("Aurora"), +`endif + .PORTNUM(8'd1) + ) sfpp_io_i1 ( + .areset(global_rst | sw_rst[0]), + .gt_refclk(sfp1_gt_refclk), + .gb_refclk(sfp1_gb_refclk), + .misc_clk(sfp1_misc_clk), + + .bus_rst(bus_rst), + .bus_clk(bus_clk), + .bus_rst_div2(bus_rst_div2), + .bus_clk_div2(bus_clk_div2), + + .txp(SFP1_TX_p), + .txn(SFP1_TX_n), + .rxp(SFP1_RX_p), + .rxn(SFP1_RX_n), + + .sfpp_rxlos(SFPP1_RxLOS), + .sfpp_tx_fault(SFPP1_TxFault), + .sfpp_tx_disable(SFPP1_TxDisable), + + .s_axis_tdata(sfp1_tx_tdata), + .s_axis_tuser(sfp1_tx_tuser), + .s_axis_tlast(sfp1_tx_tlast), + .s_axis_tvalid(sfp1_tx_tvalid), + .s_axis_tready(sfp1_tx_tready), + + .m_axis_tdata(sfp1_rx_tdata), + .m_axis_tuser(sfp1_rx_tuser), + .m_axis_tlast(sfp1_rx_tlast), + .m_axis_tvalid(sfp1_rx_tvalid), + .m_axis_tready(sfp1_rx_tready), + + .wb_adr_i(sfp1_wb_adr), + .wb_cyc_i(sfp1_wb_cyc), + .wb_dat_i(sfp1_wb_dat_o), + .wb_stb_i(sfp1_wb_stb), + .wb_we_i(sfp1_wb_we), + .wb_ack_o(sfp1_wb_ack), + .wb_dat_o(sfp1_wb_dat_i), + .wb_int_o(sfp1_wb_int), + + .phy_status(sfp1_phy_status), + .link_up(sfp1_link_up), + .activity(sfp1_activity) + ); + + // LEDs are driven with negative logic. + assign LED_LINK1 = ~sfp1_link_up; + assign LED_ACT1 = ~sfp1_activity; + + /////////////////////////////////////////////////////////////////////////////////// + // + // Synchronize misc asynchronous signals + // + /////////////////////////////////////////////////////////////////////////////////// + wire LMK_Holdover_sync, LMK_Lock_sync, LMK_Sync_sync; + wire LMK_Status0_sync, LMK_Status1_sync; + wire radio_clk_locked_sync; + wire adc_idlyctrl_rdy_sync; + + //Sync all LMK_* signals to bus_clk + synchronizer #(.INITIAL_VAL(1'b0)) LMK_Holdover_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Holdover), .out(LMK_Holdover_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) LMK_Lock_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Lock), .out(LMK_Lock_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) LMK_Sync_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Sync), .out(LMK_Sync_sync)); + //The status bits (although in a bus) are really independent + synchronizer #(.INITIAL_VAL(1'b0)) LMK_Status0_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Status[0]), .out(LMK_Status0_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) LMK_Status1_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(LMK_Status[1]), .out(LMK_Status1_sync)); + + synchronizer #(.INITIAL_VAL(1'b0)) radio_clk_locked_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(radio_clk_locked), .out(radio_clk_locked_sync)); + synchronizer #(.INITIAL_VAL(1'b0)) adc_idlyctrl_rdy_sync_inst ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(adc_idlyctrl_rdy), .out(adc_idlyctrl_rdy_sync)); + + /////////////////////////////////////////////////////////////////////////////////// + // + // Xilinx DDR3 Controller and PHY. + // + /////////////////////////////////////////////////////////////////////////////////// + + + wire ddr3_axi_clk; // 1/4 DDR external clock rate (150MHz) + wire ddr3_axi_clk_x2; // 1/2 DDR external clock rate (300MHz) + wire ddr3_axi_rst; // Synchronized to ddr_sys_clk + wire ddr3_running; // DRAM calibration complete. + wire [11:0] device_temp; + + // Slave Interface Write Address Ports + wire s_axi_awid; + wire [31:0] s_axi_awaddr; + wire [7:0] s_axi_awlen; + wire [2:0] s_axi_awsize; + wire [1:0] s_axi_awburst; + wire [0:0] s_axi_awlock; + wire [3:0] s_axi_awcache; + wire [2:0] s_axi_awprot; + wire [3:0] s_axi_awqos; + wire s_axi_awvalid; + wire s_axi_awready; + // Slave Interface Write Data Ports + wire [255:0] s_axi_wdata; + wire [31:0] s_axi_wstrb; + wire s_axi_wlast; + wire s_axi_wvalid; + wire s_axi_wready; + // Slave Interface Write Response Ports + wire s_axi_bready; + wire s_axi_bid; + wire [1:0] s_axi_bresp; + wire s_axi_bvalid; + // Slave Interface Read Address Ports + wire s_axi_arid; + wire [31:0] s_axi_araddr; + wire [7:0] s_axi_arlen; + wire [2:0] s_axi_arsize; + wire [1:0] s_axi_arburst; + wire [0:0] s_axi_arlock; + wire [3:0] s_axi_arcache; + wire [2:0] s_axi_arprot; + wire [3:0] s_axi_arqos; + wire s_axi_arvalid; + wire s_axi_arready; + // Slave Interface Read Data Ports + wire s_axi_rready; + wire s_axi_rid; + wire [255:0] s_axi_rdata; + wire [1:0] s_axi_rresp; + wire s_axi_rlast; + wire s_axi_rvalid; + + wire ddr3_idelay_refclk; + reg ddr3_axi_rst_reg_n; + + // Copied this reset circuit from example design. + always @(posedge ddr3_axi_clk) + ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; + + // Instantiate the DDR3 MIG core + ddr3_32bit u_ddr3_32bit ( + // Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), + .init_calib_complete (ddr3_running), + .device_temp_i (device_temp), + // Application interface ports + .ui_clk (ddr3_axi_clk), // 150MHz clock out + .ui_addn_clk_0 (ddr3_axi_clk_x2), // 300MHz clock out + .ui_addn_clk_1 (ddr3_idelay_refclk), + .ui_addn_clk_2 (), + .ui_addn_clk_3 (), + .ui_addn_clk_4 (), + .clk_ref_i (ddr3_idelay_refclk), + .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 150MHz + .aresetn (ddr3_axi_rst_reg_n), + .app_sr_req (1'b0), + .app_sr_active (), + .app_ref_req (1'b0), + .app_ref_ack (), + .app_zq_req (1'b0), + .app_zq_ack (), + + // Slave Interface Write Address Ports + .s_axi_awid (s_axi_awid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awlen (s_axi_awlen), + .s_axi_awsize (s_axi_awsize), + .s_axi_awburst (s_axi_awburst), + .s_axi_awlock (s_axi_awlock), + .s_axi_awcache (s_axi_awcache), + .s_axi_awprot (s_axi_awprot), + .s_axi_awqos (s_axi_awqos), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + // Slave Interface Write Data Ports + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wlast (s_axi_wlast), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + // Slave Interface Write Response Ports + .s_axi_bid (s_axi_bid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + // Slave Interface Read Address Ports + .s_axi_arid (s_axi_arid), + .s_axi_araddr (s_axi_araddr), + .s_axi_arlen (s_axi_arlen), + .s_axi_arsize (s_axi_arsize), + .s_axi_arburst (s_axi_arburst), + .s_axi_arlock (s_axi_arlock), + .s_axi_arcache (s_axi_arcache), + .s_axi_arprot (s_axi_arprot), + .s_axi_arqos (s_axi_arqos), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + // Slave Interface Read Data Ports + .s_axi_rid (s_axi_rid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rlast (s_axi_rlast), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + // System Clock Ports + .sys_clk_i (sys_clk_i), // From external 100MHz source. + .sys_rst (global_rst) + ); + + // Temperature monitor module + mig_7series_v4_2_tempmon #( + .TEMP_MON_CONTROL("INTERNAL"), .XADC_CLK_PERIOD(8000 /* 125MHz clock period in ps */) + ) tempmon_i ( + .clk(bus_clk), .xadc_clk(ioport2_clk), .rst(bus_rst), + .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) + ); + + ///////////////////////////////////////////////////////////////////// + // + // Daughterboard GPIO and Debug UART + // + ////////////////////////////////////////////////////////////////////// + + wire [31:0] db0_gpio_in, db0_gpio_out, db0_gpio_ddr; + wire [31:0] db1_gpio_in, db1_gpio_out, db1_gpio_ddr; + wire [31:0] fp_gpio_in, fp_gpio_out, fp_gpio_ddr; + wire debug_txd, debug_rxd; + + gpio_atr_io #(.WIDTH(32)) gpio_atr_db0_inst ( + .clk(radio_clk), .gpio_pins({DB0_TX_IO,DB0_RX_IO}), + .gpio_ddr(db0_gpio_ddr), .gpio_out(db0_gpio_out), .gpio_in(db0_gpio_in) + ); + + gpio_atr_io #(.WIDTH(32)) gpio_atr_db1_inst ( + .clk(radio_clk), .gpio_pins({DB1_TX_IO,DB1_RX_IO}), + .gpio_ddr(db1_gpio_ddr), .gpio_out(db1_gpio_out), .gpio_in(db1_gpio_in) + ); + +`ifdef DEBUG_UART + gpio_atr_io #(.WIDTH(10)) fp_gpio_atr_inst ( + .clk(radio_clk), .gpio_pins(FrontPanelGpio[9:0]), + .gpio_ddr(fp_gpio_ddr[9:0]), .gpio_out(fp_gpio_out[9:0]), .gpio_in(fp_gpio_in[9:0]) + ); + assign FrontPanelGpio[11] = debug_txd; + assign debug_rxd = FrontPanelGpio[10]; +`else + gpio_atr_io #(.WIDTH(12)) fp_gpio_atr_inst ( + .clk(radio_clk), .gpio_pins(FrontPanelGpio[11:0]), + .gpio_ddr(fp_gpio_ddr[11:0]), .gpio_out(fp_gpio_out[11:0]), .gpio_in(fp_gpio_in[11:0]) + ); + assign debug_rxd = 1'b0; +`endif + assign fp_gpio_in[31:12] = 20'h0; + + /////////////////////////////////////////////////////////////////////////////////// + // + // X300 Core + // + /////////////////////////////////////////////////////////////////////////////////// + + x300_core #( .BUS_CLK_RATE(BUS_CLK_RATE) ) x300_core ( + .radio_clk(radio_clk), .radio_rst(radio_rst), + .bus_clk(bus_clk), .bus_rst(bus_rst), .sw_rst(sw_rst), + .bus_clk_div2(bus_clk_div2), + .ce_clk(ce_clk), + .ce_rst(ce_rst), + // Radio0 signals + .rx0(rx0), .tx0(tx0), + .db0_gpio_in(db0_gpio_in), .db0_gpio_out(db0_gpio_out), .db0_gpio_ddr(db0_gpio_ddr), + .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), + .sen0(sen0), .sclk0(sclk0), .mosi0(mosi0), .miso0(miso0), + .radio_led0(led0), .radio0_misc_out(radio0_misc_out), .radio0_misc_in(radio0_misc_in), + // Radio1 signals + .rx1(rx1), .tx1(tx1), + .db1_gpio_in(db1_gpio_in), .db1_gpio_out(db1_gpio_out), .db1_gpio_ddr(db1_gpio_ddr), + .sen1(sen1), .sclk1(sclk1), .mosi1(mosi1), .miso1(miso1), + .radio_led1(led1), .radio1_misc_out(radio1_misc_out), .radio1_misc_in(radio1_misc_in), + // I2C bus + .db_scl(DB_SCL), .db_sda(DB_SDA), + // External clock gen + .ext_ref_clk(ref_clk), + .clock_ref_sel(ClockRefSelect), + .clock_misc_opt({GPSDO_PWR_ENA, TCXO_ENA}), + .LMK_Status({LMK_Status1_sync, LMK_Status0_sync}), .LMK_Holdover(LMK_Holdover_sync), .LMK_Lock(LMK_Lock_sync), .LMK_Sync(LMK_Sync_sync), + .LMK_SEN(LMK_SEN), .LMK_SCLK(LMK_SCLK), .LMK_MOSI(LMK_MOSI), + .misc_clock_status({1'b0, adc_idlyctrl_rdy_sync, radio_clk_locked_sync}), + // SFP+ 0 flags + .SFPP0_SCL(SFPP0_SCL), .SFPP0_SDA(SFPP0_SDA), .SFPP0_ModAbs(SFPP0_ModAbs), .SFPP0_TxFault(SFPP0_TxFault), + .SFPP0_RxLOS(SFPP0_RxLOS), .SFPP0_RS1(SFPP0_RS1), .SFPP0_RS0(SFPP0_RS0), + // SFP+ 1 flags + .SFPP1_SCL(SFPP1_SCL), .SFPP1_SDA(SFPP1_SDA), .SFPP1_ModAbs(SFPP1_ModAbs), .SFPP1_TxFault(SFPP1_TxFault), + .SFPP1_RxLOS(SFPP1_RxLOS), .SFPP1_RS1(SFPP1_RS1), .SFPP1_RS0(SFPP1_RS0), + // SFP+ 0 data stream + .sfp0_tx_tdata(sfp0_tx_tdata), .sfp0_tx_tuser(sfp0_tx_tuser), .sfp0_tx_tlast(sfp0_tx_tlast), + .sfp0_tx_tvalid(sfp0_tx_tvalid), .sfp0_tx_tready(sfp0_tx_tready), + .sfp0_rx_tdata(sfp0_rx_tdata), .sfp0_rx_tuser(sfp0_rx_tuser), .sfp0_rx_tlast(sfp0_rx_tlast), + .sfp0_rx_tvalid(sfp0_rx_tvalid), .sfp0_rx_tready(sfp0_rx_tready), + .sfp0_phy_status(sfp0_phy_status), + // SFP+ 1 data stream + .sfp1_tx_tdata(sfp1_tx_tdata), .sfp1_tx_tuser(sfp1_tx_tuser), .sfp1_tx_tlast(sfp1_tx_tlast), + .sfp1_tx_tvalid(sfp1_tx_tvalid), .sfp1_tx_tready(sfp1_tx_tready), + .sfp1_rx_tdata(sfp1_rx_tdata), .sfp1_rx_tuser(sfp1_rx_tuser), .sfp1_rx_tlast(sfp1_rx_tlast), + .sfp1_rx_tvalid(sfp1_rx_tvalid), .sfp1_rx_tready(sfp1_rx_tready), + .sfp1_phy_status(sfp1_phy_status), + // Wishbone Slave Interface(s) + .sfp0_wb_dat_i(sfp0_wb_dat_i), .sfp0_wb_dat_o(sfp0_wb_dat_o), .sfp0_wb_adr(sfp0_wb_adr), + .sfp0_wb_sel(), .sfp0_wb_ack(sfp0_wb_ack), .sfp0_wb_stb(sfp0_wb_stb), + .sfp0_wb_cyc(sfp0_wb_cyc), .sfp0_wb_we(sfp0_wb_we), .sfp0_wb_int(sfp0_wb_int), + .sfp1_wb_dat_i(sfp1_wb_dat_i), .sfp1_wb_dat_o(sfp1_wb_dat_o), .sfp1_wb_adr(sfp1_wb_adr), + .sfp1_wb_sel(), .sfp1_wb_ack(sfp1_wb_ack), .sfp1_wb_stb(sfp1_wb_stb), + .sfp1_wb_cyc(sfp1_wb_cyc), .sfp1_wb_we(sfp1_wb_we), .sfp1_wb_int(sfp1_wb_int), + // Time + .pps(pps),.pps_select(pps_select), .pps_out_enb(pps_out_enb), + .ref_freq(ref_freq), .ref_freq_changed(ref_freq_changed), + // GPS Signals + .gps_txd(GPS_SER_IN), .gps_rxd(GPS_SER_OUT), + // Debug UART + .debug_rxd(debug_rxd), .debug_txd(debug_txd), + // Misc. + .led_misc(leds), + .xadc_readback({20'h0, device_temp}), + .debug0(), .debug1(), .debug2(), + // DRAM signals. + .ddr3_axi_clk (ddr3_axi_clk), + .ddr3_axi_clk_x2 (ddr3_axi_clk_x2), + .ddr3_axi_rst (ddr3_axi_rst), + // Slave Interface Write Address Ports + .ddr3_axi_awid (s_axi_awid), + .ddr3_axi_awaddr (s_axi_awaddr), + .ddr3_axi_awlen (s_axi_awlen), + .ddr3_axi_awsize (s_axi_awsize), + .ddr3_axi_awburst (s_axi_awburst), + .ddr3_axi_awlock (s_axi_awlock), + .ddr3_axi_awcache (s_axi_awcache), + .ddr3_axi_awprot (s_axi_awprot), + .ddr3_axi_awqos (s_axi_awqos), + .ddr3_axi_awvalid (s_axi_awvalid), + .ddr3_axi_awready (s_axi_awready), + // Slave Interface Write Data Ports + .ddr3_axi_wdata (s_axi_wdata), + .ddr3_axi_wstrb (s_axi_wstrb), + .ddr3_axi_wlast (s_axi_wlast), + .ddr3_axi_wvalid (s_axi_wvalid), + .ddr3_axi_wready (s_axi_wready), + // Slave Interface Write Response Ports + .ddr3_axi_bid (s_axi_bid), + .ddr3_axi_bresp (s_axi_bresp), + .ddr3_axi_bvalid (s_axi_bvalid), + .ddr3_axi_bready (s_axi_bready), + // Slave Interface Read Address Ports + .ddr3_axi_arid (s_axi_arid), + .ddr3_axi_araddr (s_axi_araddr), + .ddr3_axi_arlen (s_axi_arlen), + .ddr3_axi_arsize (s_axi_arsize), + .ddr3_axi_arburst (s_axi_arburst), + .ddr3_axi_arlock (s_axi_arlock), + .ddr3_axi_arcache (s_axi_arcache), + .ddr3_axi_arprot (s_axi_arprot), + .ddr3_axi_arqos (s_axi_arqos), + .ddr3_axi_arvalid (s_axi_arvalid), + .ddr3_axi_arready (s_axi_arready), + // Slave Interface Read Data Ports + .ddr3_axi_rid (s_axi_rid), + .ddr3_axi_rdata (s_axi_rdata), + .ddr3_axi_rresp (s_axi_rresp), + .ddr3_axi_rlast (s_axi_rlast), + .ddr3_axi_rvalid (s_axi_rvalid), + .ddr3_axi_rready (s_axi_rready), + // IoPort2 Message FIFOs + .o_iop2_msg_tdata (o_iop2_msg_tdata), + .o_iop2_msg_tvalid (o_iop2_msg_tvalid), + .o_iop2_msg_tlast (o_iop2_msg_tlast), + .o_iop2_msg_tready (o_iop2_msg_tready), + .i_iop2_msg_tdata (i_iop2_msg_tdata), + .i_iop2_msg_tvalid (i_iop2_msg_tvalid), + .i_iop2_msg_tlast (i_iop2_msg_tlast), + .i_iop2_msg_tready (i_iop2_msg_tready), + // PCIe DMA Data + .pcio_tdata (pcio_tdata), + .pcio_tuser (pcio_tuser), + .pcio_tlast (pcio_tlast), + .pcio_tvalid (pcio_tvalid), + .pcio_tready (pcio_tready), + .pcii_tdata (pcii_tdata), + .pcii_tuser (pcii_tuser), + .pcii_tlast (pcii_tlast), + .pcii_tvalid (pcii_tvalid), + .pcii_tready (pcii_tready) + ); + + assign {DB_ADC_RESET, DB_DAC_RESET,DB0_DAC_ENABLE} = radio0_misc_out[2:0]; + assign {DB1_DAC_ENABLE} = radio1_misc_out[0]; //[2:1] unused + + ///////////////////////////////////////////////////////////////////// + // + // PUDC Workaround + // + ////////////////////////////////////////////////////////////////////// + // This is a workaround for a silicon bug in Series 7 FPGA where a + // race condition with the reading of PUDC during the erase of the FPGA + // image cause glitches on output IO pins. This glitch happens even if + // you have PUDC correctly pulled high!!  When PUDC is high the pull up + // resistor should never be enabled on the IO lines, however there is a + // race condition that causes this to not be the case. + // + // Workaround: + // - Define the PUDC pin in the XDC file with a pullup. + // - Implements an IBUF on the PUDC input and make sure that it does + // not get optimized out. + (* dont_touch = "true" *) wire fpga_pudc_b_buf; + IBUF pudc_ibuf_i ( + .I(FPGA_PUDC_B), + .O(fpga_pudc_b_buf)); + +endmodule // x300 diff --git a/fpga/usrp3/top/x300/x300.xdc b/fpga/usrp3/top/x300/x300.xdc new file mode 100644 index 000000000..11290b79f --- /dev/null +++ b/fpga/usrp3/top/x300/x300.xdc @@ -0,0 +1,710 @@ +# +# Copyright 2014 Ettus Research LLC +# + +#******************************************************************************* +# X3x0 Pin Mapping +#******************************************************************************* + +#******************************************************************************* +## SFP Lanes + +# SFP clock pins now come from their own ucf files. See _10ge.ucf, _1ge.ucf, and _cpri.ucf +# NOTE: In the schematic SFP0 signals are prefixed SFP1 and SFP1 signals are prefixed SFP2 +set_property PACKAGE_PIN AA3 [get_ports SFP0_RX_n] +set_property PACKAGE_PIN AA4 [get_ports SFP0_RX_p] +# set_property IOSTANDARD LVDS [get_ports {SFP0_RX_*}] + +set_property PACKAGE_PIN Y1 [get_ports SFP0_TX_n] +set_property PACKAGE_PIN Y2 [get_ports SFP0_TX_p] +# set_property IOSTANDARD LVDS [get_ports {SFP0_TX_*}] + +set_property PACKAGE_PIN T5 [get_ports SFP1_RX_n] +set_property PACKAGE_PIN T6 [get_ports SFP1_RX_p] +# set_property IOSTANDARD LVDS [get_ports {SFP1_RX_*}] + +set_property PACKAGE_PIN P1 [get_ports SFP1_TX_n] +set_property PACKAGE_PIN P2 [get_ports SFP1_TX_p] +# set_property IOSTANDARD LVDS [get_ports {SFP1_TX_*}] + +#******************************************************************************* +## ADC 0 + +set_property PACKAGE_PIN L27 [get_ports DB0_ADC_DA0_N] +set_property PACKAGE_PIN L26 [get_ports DB0_ADC_DA0_P] +set_property PACKAGE_PIN K29 [get_ports DB0_ADC_DA1_N] +set_property PACKAGE_PIN K28 [get_ports DB0_ADC_DA1_P] +set_property PACKAGE_PIN L28 [get_ports DB0_ADC_DA2_N] +set_property PACKAGE_PIN M28 [get_ports DB0_ADC_DA2_P] +set_property PACKAGE_PIN C30 [get_ports DB0_ADC_DA3_N] ;# In 3.3V bank +set_property PACKAGE_PIN D29 [get_ports DB0_ADC_DA3_P] ;# In 3.3V bank +set_property PACKAGE_PIN J24 [get_ports DB0_ADC_DA4_N] +set_property PACKAGE_PIN J23 [get_ports DB0_ADC_DA4_P] +set_property PACKAGE_PIN L23 [get_ports DB0_ADC_DA5_N] +set_property PACKAGE_PIN L22 [get_ports DB0_ADC_DA5_P] +set_property PACKAGE_PIN K24 [get_ports DB0_ADC_DA6_N] +set_property PACKAGE_PIN K23 [get_ports DB0_ADC_DA6_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_ADC_DA*}] + +set_property DIFF_TERM TRUE [get_ports {DB0_ADC_DA*}] +# Bit 3 is in the 3.3V bank and does no support diff termination +set_property DIFF_TERM FALSE [get_ports DB0_ADC_DA3_*] + +set_property PACKAGE_PIN K21 [get_ports DB0_ADC_DB0_N] +set_property PACKAGE_PIN L21 [get_ports DB0_ADC_DB0_P] +set_property PACKAGE_PIN J22 [get_ports DB0_ADC_DB1_N] +set_property PACKAGE_PIN J21 [get_ports DB0_ADC_DB1_P] +set_property PACKAGE_PIN L20 [get_ports DB0_ADC_DB2_N] +set_property PACKAGE_PIN M20 [get_ports DB0_ADC_DB2_P] +set_property PACKAGE_PIN H29 [get_ports DB0_ADC_DB3_N] +set_property PACKAGE_PIN J29 [get_ports DB0_ADC_DB3_P] +set_property PACKAGE_PIN J28 [get_ports DB0_ADC_DB4_N] +set_property PACKAGE_PIN J27 [get_ports DB0_ADC_DB4_P] +set_property PACKAGE_PIN K30 [get_ports DB0_ADC_DB5_N] +set_property PACKAGE_PIN L30 [get_ports DB0_ADC_DB5_P] +set_property PACKAGE_PIN J26 [get_ports DB0_ADC_DB6_N] +set_property PACKAGE_PIN K26 [get_ports DB0_ADC_DB6_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_ADC_DB*}] + +set_property DIFF_TERM TRUE [get_ports {DB0_ADC_DB*}] + +set_property PACKAGE_PIN K25 [get_ports DB0_ADC_DCLK_N] +set_property PACKAGE_PIN L25 [get_ports DB0_ADC_DCLK_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_ADC_DCLK_*}] + +#******************************************************************************* +## ADC 1 + +set_property PACKAGE_PIN D18 [get_ports DB1_ADC_DA0_N] +set_property PACKAGE_PIN D17 [get_ports DB1_ADC_DA0_P] +set_property PACKAGE_PIN D19 [get_ports DB1_ADC_DA1_N] +set_property PACKAGE_PIN E19 [get_ports DB1_ADC_DA1_P] +set_property PACKAGE_PIN L18 [get_ports DB1_ADC_DA2_N] +set_property PACKAGE_PIN L17 [get_ports DB1_ADC_DA2_P] +set_property PACKAGE_PIN J13 [get_ports DB1_ADC_DA3_N] ;# In 3.3V bank +set_property PACKAGE_PIN K13 [get_ports DB1_ADC_DA3_P] ;# In 3.3V bank +set_property PACKAGE_PIN H17 [get_ports DB1_ADC_DA4_N] +set_property PACKAGE_PIN J17 [get_ports DB1_ADC_DA4_P] +set_property PACKAGE_PIN F18 [get_ports DB1_ADC_DA5_N] +set_property PACKAGE_PIN G18 [get_ports DB1_ADC_DA5_P] +set_property PACKAGE_PIN H19 [get_ports DB1_ADC_DA6_N] +set_property PACKAGE_PIN J19 [get_ports DB1_ADC_DA6_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_ADC_DA*}] + +set_property DIFF_TERM TRUE [get_ports {DB1_ADC_DA*}] +# Bit 3 is in the 3.3V bank and does no support diff termination +set_property DIFF_TERM FALSE [get_ports DB1_ADC_DA3_*] + +set_property PACKAGE_PIN J18 [get_ports DB1_ADC_DB0_N] +set_property PACKAGE_PIN K18 [get_ports DB1_ADC_DB0_P] +set_property PACKAGE_PIN C21 [get_ports DB1_ADC_DB1_N] +set_property PACKAGE_PIN D21 [get_ports DB1_ADC_DB1_P] +set_property PACKAGE_PIN K20 [get_ports DB1_ADC_DB2_N] +set_property PACKAGE_PIN K19 [get_ports DB1_ADC_DB2_P] +set_property PACKAGE_PIN F22 [get_ports DB1_ADC_DB3_N] +set_property PACKAGE_PIN G22 [get_ports DB1_ADC_DB3_P] +set_property PACKAGE_PIN G20 [get_ports DB1_ADC_DB4_N] +set_property PACKAGE_PIN H20 [get_ports DB1_ADC_DB4_P] +set_property PACKAGE_PIN C22 [get_ports DB1_ADC_DB5_N] +set_property PACKAGE_PIN D22 [get_ports DB1_ADC_DB5_P] +set_property PACKAGE_PIN H22 [get_ports DB1_ADC_DB6_N] +set_property PACKAGE_PIN H21 [get_ports DB1_ADC_DB6_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_ADC_DB*}] + +set_property DIFF_TERM TRUE [get_ports {DB1_ADC_DB*}] + +set_property PACKAGE_PIN E20 [get_ports DB1_ADC_DCLK_N] +set_property PACKAGE_PIN F20 [get_ports DB1_ADC_DCLK_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_ADC_DCLK_*}] + +#******************************************************************************* +## DAC 0 + +set_property PACKAGE_PIN M30 [get_ports DB0_DAC_D0_N] +set_property PACKAGE_PIN M29 [get_ports DB0_DAC_D0_P] +set_property PACKAGE_PIN M27 [get_ports DB0_DAC_D1_N] +set_property PACKAGE_PIN N27 [get_ports DB0_DAC_D1_P] +set_property PACKAGE_PIN N30 [get_ports DB0_DAC_D2_N] +set_property PACKAGE_PIN N29 [get_ports DB0_DAC_D2_P] +set_property PACKAGE_PIN N26 [get_ports DB0_DAC_D3_N] +set_property PACKAGE_PIN N25 [get_ports DB0_DAC_D3_P] +set_property PACKAGE_PIN N20 [get_ports DB0_DAC_D4_N] +set_property PACKAGE_PIN N19 [get_ports DB0_DAC_D4_P] +set_property PACKAGE_PIN N22 [get_ports DB0_DAC_D5_N] +set_property PACKAGE_PIN N21 [get_ports DB0_DAC_D5_P] +set_property PACKAGE_PIN N24 [get_ports DB0_DAC_D6_N] +set_property PACKAGE_PIN P23 [get_ports DB0_DAC_D6_P] +set_property PACKAGE_PIN P22 [get_ports DB0_DAC_D7_N] +set_property PACKAGE_PIN P21 [get_ports DB0_DAC_D7_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_DAC_D*}] + +set_property PACKAGE_PIN M23 [get_ports DB0_DAC_DCI_N] +set_property PACKAGE_PIN M22 [get_ports DB0_DAC_DCI_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_DAC_DCI_*}] + +set_property PACKAGE_PIN M25 [get_ports DB0_DAC_FRAME_N] +set_property PACKAGE_PIN M24 [get_ports DB0_DAC_FRAME_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB0_DAC_FRAME_*}] + +#******************************************************************************* +## DAC 1 + +set_property PACKAGE_PIN B17 [get_ports DB1_DAC_D0_N] +set_property PACKAGE_PIN C17 [get_ports DB1_DAC_D0_P] +set_property PACKAGE_PIN F17 [get_ports DB1_DAC_D1_N] +set_property PACKAGE_PIN G17 [get_ports DB1_DAC_D1_P] +set_property PACKAGE_PIN A17 [get_ports DB1_DAC_D2_N] +set_property PACKAGE_PIN A16 [get_ports DB1_DAC_D2_P] +set_property PACKAGE_PIN A18 [get_ports DB1_DAC_D3_N] +set_property PACKAGE_PIN B18 [get_ports DB1_DAC_D3_P] +set_property PACKAGE_PIN A21 [get_ports DB1_DAC_D4_N] +set_property PACKAGE_PIN A20 [get_ports DB1_DAC_D4_P] +set_property PACKAGE_PIN B20 [get_ports DB1_DAC_D5_N] +set_property PACKAGE_PIN C20 [get_ports DB1_DAC_D5_P] +set_property PACKAGE_PIN A22 [get_ports DB1_DAC_D6_N] +set_property PACKAGE_PIN B22 [get_ports DB1_DAC_D6_P] +set_property PACKAGE_PIN B19 [get_ports DB1_DAC_D7_N] +set_property PACKAGE_PIN C19 [get_ports DB1_DAC_D7_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_DAC_D*}] + +set_property PACKAGE_PIN E21 [get_ports DB1_DAC_DCI_N] +set_property PACKAGE_PIN F21 [get_ports DB1_DAC_DCI_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_DAC_DCI_*}] + +set_property PACKAGE_PIN C16 [get_ports DB1_DAC_FRAME_N] +set_property PACKAGE_PIN D16 [get_ports DB1_DAC_FRAME_P] +set_property IOSTANDARD LVDS_25 [get_ports {DB1_DAC_FRAME_*}] + +#******************************************************************************* +## DB0 GPIO + +set_property PACKAGE_PIN G25 [get_ports {DB0_RX_IO[0]}] +set_property PACKAGE_PIN G30 [get_ports {DB0_RX_IO[1]}] +set_property PACKAGE_PIN H30 [get_ports {DB0_RX_IO[2]}] +set_property PACKAGE_PIN H27 [get_ports {DB0_RX_IO[3]}] +set_property PACKAGE_PIN H26 [get_ports {DB0_RX_IO[4]}] +set_property PACKAGE_PIN F30 [get_ports {DB0_RX_IO[5]}] +set_property PACKAGE_PIN G29 [get_ports {DB0_RX_IO[6]}] +set_property PACKAGE_PIN F27 [get_ports {DB0_RX_IO[7]}] +set_property PACKAGE_PIN G27 [get_ports {DB0_RX_IO[8]}] +set_property PACKAGE_PIN F28 [get_ports {DB0_RX_IO[9]}] +set_property PACKAGE_PIN G28 [get_ports {DB0_RX_IO[10]}] +set_property PACKAGE_PIN H25 [get_ports {DB0_RX_IO[11]}] +set_property PACKAGE_PIN H24 [get_ports {DB0_RX_IO[12]}] +set_property PACKAGE_PIN E30 [get_ports {DB0_RX_IO[13]}] +set_property PACKAGE_PIN E29 [get_ports {DB0_RX_IO[14]}] +set_property PACKAGE_PIN A30 [get_ports {DB0_RX_IO[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB0_RX_IO*}] + +set_property PACKAGE_PIN B25 [get_ports {DB0_TX_IO[0]}] +set_property PACKAGE_PIN C25 [get_ports {DB0_TX_IO[1]}] +set_property PACKAGE_PIN C26 [get_ports {DB0_TX_IO[2]}] +set_property PACKAGE_PIN D26 [get_ports {DB0_TX_IO[3]}] +set_property PACKAGE_PIN A26 [get_ports {DB0_TX_IO[4]}] +set_property PACKAGE_PIN A25 [get_ports {DB0_TX_IO[5]}] +set_property PACKAGE_PIN A28 [get_ports {DB0_TX_IO[6]}] +set_property PACKAGE_PIN B28 [get_ports {DB0_TX_IO[7]}] +set_property PACKAGE_PIN B24 [get_ports {DB0_TX_IO[8]}] +set_property PACKAGE_PIN C24 [get_ports {DB0_TX_IO[9]}] +set_property PACKAGE_PIN A27 [get_ports {DB0_TX_IO[10]}] +set_property PACKAGE_PIN B27 [get_ports {DB0_TX_IO[11]}] +set_property PACKAGE_PIN G24 [get_ports {DB0_TX_IO[12]}] +set_property PACKAGE_PIN G23 [get_ports {DB0_TX_IO[13]}] +set_property PACKAGE_PIN E26 [get_ports {DB0_TX_IO[14]}] +set_property PACKAGE_PIN F26 [get_ports {DB0_TX_IO[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB0_TX_IO*}] + +#******************************************************************************* +## DB1 GPIO + +set_property PACKAGE_PIN F16 [get_ports {DB1_RX_IO[0]}] +set_property PACKAGE_PIN A15 [get_ports {DB1_RX_IO[1]}] +set_property PACKAGE_PIN B14 [get_ports {DB1_RX_IO[2]}] +set_property PACKAGE_PIN B15 [get_ports {DB1_RX_IO[3]}] +set_property PACKAGE_PIN C15 [get_ports {DB1_RX_IO[4]}] +set_property PACKAGE_PIN A13 [get_ports {DB1_RX_IO[5]}] +set_property PACKAGE_PIN B13 [get_ports {DB1_RX_IO[6]}] +set_property PACKAGE_PIN C14 [get_ports {DB1_RX_IO[7]}] +set_property PACKAGE_PIN D14 [get_ports {DB1_RX_IO[8]}] +set_property PACKAGE_PIN E15 [get_ports {DB1_RX_IO[9]}] +set_property PACKAGE_PIN E14 [get_ports {DB1_RX_IO[10]}] +set_property PACKAGE_PIN E16 [get_ports {DB1_RX_IO[11]}] +set_property PACKAGE_PIN F15 [get_ports {DB1_RX_IO[12]}] +set_property PACKAGE_PIN C11 [get_ports {DB1_RX_IO[13]}] +set_property PACKAGE_PIN D11 [get_ports {DB1_RX_IO[14]}] +set_property PACKAGE_PIN A12 [get_ports {DB1_RX_IO[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB1_RX_IO*}] + +set_property PACKAGE_PIN F13 [get_ports {DB1_TX_IO[0]}] +set_property PACKAGE_PIN G13 [get_ports {DB1_TX_IO[1]}] +set_property PACKAGE_PIN G14 [get_ports {DB1_TX_IO[2]}] +set_property PACKAGE_PIN H14 [get_ports {DB1_TX_IO[3]}] +set_property PACKAGE_PIN H12 [get_ports {DB1_TX_IO[4]}] +set_property PACKAGE_PIN H11 [get_ports {DB1_TX_IO[5]}] +set_property PACKAGE_PIN H16 [get_ports {DB1_TX_IO[6]}] +set_property PACKAGE_PIN J16 [get_ports {DB1_TX_IO[7]}] +set_property PACKAGE_PIN J12 [get_ports {DB1_TX_IO[8]}] +set_property PACKAGE_PIN J11 [get_ports {DB1_TX_IO[9]}] +set_property PACKAGE_PIN G15 [get_ports {DB1_TX_IO[10]}] +set_property PACKAGE_PIN H15 [get_ports {DB1_TX_IO[11]}] +set_property PACKAGE_PIN K11 [get_ports {DB1_TX_IO[12]}] +set_property PACKAGE_PIN L11 [get_ports {DB1_TX_IO[13]}] +set_property PACKAGE_PIN J14 [get_ports {DB1_TX_IO[14]}] +set_property PACKAGE_PIN K14 [get_ports {DB1_TX_IO[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DB1_TX_IO*}] + +#******************************************************************************* +## DB0 SPI + +set_property PACKAGE_PIN AE14 [get_ports DB0_DAC_SEN] +set_property IOSTANDARD LVCMOS18 [get_ports DB0_DAC_SEN] + +set_property PACKAGE_PIN B29 [get_ports DB0_ADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_ADC_SEN] + +set_property PACKAGE_PIN E24 [get_ports DB0_MOSI] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_MOSI] + +set_property PACKAGE_PIN C27 [get_ports DB0_RX_LSADC_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_RX_LSADC_MISO] + +set_property PACKAGE_PIN E28 [get_ports DB0_RX_LSADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_RX_LSADC_SEN] + +set_property PACKAGE_PIN D27 [get_ports DB0_RX_LSDAC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_RX_LSDAC_SEN] + +set_property PACKAGE_PIN C29 [get_ports DB0_RX_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_RX_MISO] + +set_property PACKAGE_PIN D28 [get_ports DB0_RX_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_RX_SEN] + +set_property PACKAGE_PIN D24 [get_ports DB0_SCLK] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_SCLK] + +set_property PACKAGE_PIN B23 [get_ports DB0_TX_LSADC_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_TX_LSADC_MISO] + +set_property PACKAGE_PIN A23 [get_ports DB0_TX_LSADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_TX_LSADC_SEN] + +set_property PACKAGE_PIN F23 [get_ports DB0_TX_LSDAC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_TX_LSDAC_SEN] + +set_property PACKAGE_PIN E23 [get_ports DB0_TX_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_TX_MISO] + +set_property PACKAGE_PIN D23 [get_ports DB0_TX_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB0_TX_SEN] + +#******************************************************************************* +# DB1 SPI + +set_property PACKAGE_PIN AE15 [get_ports DB1_DAC_SEN] +set_property IOSTANDARD LVCMOS18 [get_ports DB1_DAC_SEN] + +set_property PACKAGE_PIN B12 [get_ports DB1_ADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_ADC_SEN] + +set_property PACKAGE_PIN L12 [get_ports DB1_MOSI] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_MOSI] + +set_property PACKAGE_PIN D13 [get_ports DB1_RX_LSADC_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_RX_LSADC_MISO] + +set_property PACKAGE_PIN F12 [get_ports DB1_RX_LSADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_RX_LSADC_SEN] + +set_property PACKAGE_PIN D12 [get_ports DB1_RX_LSDAC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_RX_LSDAC_SEN] + +set_property PACKAGE_PIN C12 [get_ports DB1_RX_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_RX_MISO] + +set_property PACKAGE_PIN E13 [get_ports DB1_RX_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_RX_SEN] + +set_property PACKAGE_PIN L13 [get_ports DB1_SCLK] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_SCLK] + +set_property PACKAGE_PIN L16 [get_ports DB1_TX_LSADC_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_TX_LSADC_MISO] + +set_property PACKAGE_PIN K16 [get_ports DB1_TX_LSADC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_TX_LSADC_SEN] + +set_property PACKAGE_PIN G12 [get_ports DB1_TX_LSDAC_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_TX_LSDAC_SEN] + +set_property PACKAGE_PIN L15 [get_ports DB1_TX_MISO] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_TX_MISO] + +set_property PACKAGE_PIN K15 [get_ports DB1_TX_SEN] +set_property IOSTANDARD LVCMOS33 [get_ports DB1_TX_SEN] + +#******************************************************************************* +## DB Misc + +set_property PACKAGE_PIN AB15 [get_ports DB_DAC_MOSI] +set_property IOSTANDARD LVCMOS18 [get_ports DB_DAC_MOSI] + +set_property PACKAGE_PIN AA15 [get_ports DB_DAC_SCLK] +set_property IOSTANDARD LVCMOS18 [get_ports DB_DAC_SCLK] + +set_property PACKAGE_PIN F25 [get_ports DB_SCL] +set_property IOSTANDARD LVCMOS33 [get_ports DB_SCL] + +set_property PACKAGE_PIN E25 [get_ports DB_SDA] +set_property IOSTANDARD LVCMOS33 [get_ports DB_SDA] + +set_property PACKAGE_PIN B30 [get_ports DB_ADC_RESET] +set_property IOSTANDARD LVCMOS33 [get_ports DB_ADC_RESET] + +set_property PACKAGE_PIN AC16 [get_ports DB_DAC_RESET] +set_property IOSTANDARD LVCMOS18 [get_ports DB_DAC_RESET] + +set_property PACKAGE_PIN AC14 [get_ports DB0_DAC_ENABLE] +set_property IOSTANDARD LVCMOS18 [get_ports DB0_DAC_ENABLE] + +set_property PACKAGE_PIN AC15 [get_ports DB1_DAC_ENABLE] +set_property IOSTANDARD LVCMOS18 [get_ports DB1_DAC_ENABLE] + +#******************************************************************************* +## STC3 Pin Mapping + +set_property PACKAGE_PIN AC27 [get_ports aIoResetIn_n] +set_property IOSTANDARD LVTTL [get_ports aIoResetIn_n] + +set_property PACKAGE_PIN AH29 [get_ports aIoReadyIn] +set_property IOSTANDARD LVTTL [get_ports aIoReadyIn] + +set_property PACKAGE_PIN AE28 [get_ports aIoReadyOut] +set_property IOSTANDARD LVTTL [get_ports aIoReadyOut] + +set_property PACKAGE_PIN AD18 [get_ports IoRxClock] +set_property PACKAGE_PIN AE18 [get_ports IoRxClock_n] +set_property IOSTANDARD LVDS [get_ports {IoRxClock*}] +set_property DIFF_TERM TRUE [get_ports {IoRxClock*}] + +set_property PACKAGE_PIN AK18 [get_ports {irIoRxData_n[0]}] +set_property PACKAGE_PIN AJ17 [get_ports {irIoRxData_n[1]}] +set_property PACKAGE_PIN AK19 [get_ports {irIoRxData_n[2]}] +set_property PACKAGE_PIN AG14 [get_ports {irIoRxData_n[3]}] +set_property PACKAGE_PIN AH15 [get_ports {irIoRxData_n[4]}] +set_property PACKAGE_PIN Y18 [get_ports {irIoRxData_n[5]}] +set_property PACKAGE_PIN AG17 [get_ports {irIoRxData_n[6]}] +set_property PACKAGE_PIN AE19 [get_ports {irIoRxData_n[7]}] +set_property PACKAGE_PIN AC17 [get_ports {irIoRxData_n[8]}] +set_property PACKAGE_PIN AD16 [get_ports {irIoRxData_n[9]}] +set_property PACKAGE_PIN AJ16 [get_ports {irIoRxData_n[10]}] +set_property PACKAGE_PIN AC19 [get_ports {irIoRxData_n[11]}] +set_property PACKAGE_PIN AB18 [get_ports {irIoRxData_n[12]}] +set_property PACKAGE_PIN AF16 [get_ports {irIoRxData_n[13]}] +set_property PACKAGE_PIN AH19 [get_ports {irIoRxData_n[14]}] +set_property PACKAGE_PIN AK15 [get_ports {irIoRxData_n[15]}] + +set_property PACKAGE_PIN AJ18 [get_ports {irIoRxData[0]}] +set_property PACKAGE_PIN AH17 [get_ports {irIoRxData[1]}] +set_property PACKAGE_PIN AJ19 [get_ports {irIoRxData[2]}] +set_property PACKAGE_PIN AF15 [get_ports {irIoRxData[3]}] +set_property PACKAGE_PIN AG15 [get_ports {irIoRxData[4]}] +set_property PACKAGE_PIN Y19 [get_ports {irIoRxData[5]}] +set_property PACKAGE_PIN AF17 [get_ports {irIoRxData[6]}] +set_property PACKAGE_PIN AD19 [get_ports {irIoRxData[7]}] +set_property PACKAGE_PIN AB17 [get_ports {irIoRxData[8]}] +set_property PACKAGE_PIN AD17 [get_ports {irIoRxData[9]}] +set_property PACKAGE_PIN AH16 [get_ports {irIoRxData[10]}] +set_property PACKAGE_PIN AB19 [get_ports {irIoRxData[11]}] +set_property PACKAGE_PIN AA18 [get_ports {irIoRxData[12]}] +set_property PACKAGE_PIN AE16 [get_ports {irIoRxData[13]}] +set_property PACKAGE_PIN AG19 [get_ports {irIoRxData[14]}] +set_property PACKAGE_PIN AK16 [get_ports {irIoRxData[15]}] + +set_property IOSTANDARD LVDS [get_ports {irIoRxData*}] +set_property DIFF_TERM TRUE [get_ports {irIoRxData*}] + +set_property IOSTANDARD LVDS [get_ports {irIoRxHeader*}] +set_property DIFF_TERM TRUE [get_ports {irIoRxHeader*}] +set_property PACKAGE_PIN AF18 [get_ports irIoRxHeader] +set_property PACKAGE_PIN AG18 [get_ports irIoRxHeader_n] + +set_property IOSTANDARD LVDS_25 [get_ports {IoTxClock*}] +set_property PACKAGE_PIN AE24 [get_ports IoTxClock_n] +set_property PACKAGE_PIN AD23 [get_ports IoTxClock] + +set_property IOSTANDARD LVDS_25 [get_ports {itIoTxData*}] +set_property PACKAGE_PIN AF25 [get_ports {itIoTxData_n[0]}] +set_property PACKAGE_PIN AC25 [get_ports {itIoTxData_n[1]}] +set_property PACKAGE_PIN AH22 [get_ports {itIoTxData_n[2]}] +set_property PACKAGE_PIN AF21 [get_ports {itIoTxData_n[3]}] +set_property PACKAGE_PIN AD24 [get_ports {itIoTxData_n[4]}] +set_property PACKAGE_PIN AB20 [get_ports {itIoTxData_n[5]}] +set_property PACKAGE_PIN AA21 [get_ports {itIoTxData_n[6]}] +set_property PACKAGE_PIN AH25 [get_ports {itIoTxData_n[7]}] +set_property PACKAGE_PIN AB23 [get_ports {itIoTxData_n[8]}] +set_property PACKAGE_PIN AK25 [get_ports {itIoTxData_n[9]}] +set_property PACKAGE_PIN AK24 [get_ports {itIoTxData_n[10]}] +set_property PACKAGE_PIN AD22 [get_ports {itIoTxData_n[11]}] +set_property PACKAGE_PIN AF23 [get_ports {itIoTxData_n[12]}] +set_property PACKAGE_PIN AE21 [get_ports {itIoTxData_n[13]}] +set_property PACKAGE_PIN AC21 [get_ports {itIoTxData_n[14]}] +set_property PACKAGE_PIN AA23 [get_ports {itIoTxData_n[15]}] +set_property PACKAGE_PIN AE25 [get_ports {itIoTxData[0]}] +set_property PACKAGE_PIN AB24 [get_ports {itIoTxData[1]}] +set_property PACKAGE_PIN AG22 [get_ports {itIoTxData[2]}] +set_property PACKAGE_PIN AF20 [get_ports {itIoTxData[3]}] +set_property PACKAGE_PIN AC24 [get_ports {itIoTxData[4]}] +set_property PACKAGE_PIN AA20 [get_ports {itIoTxData[5]}] +set_property PACKAGE_PIN Y21 [get_ports {itIoTxData[6]}] +set_property PACKAGE_PIN AG25 [get_ports {itIoTxData[7]}] +set_property PACKAGE_PIN AB22 [get_ports {itIoTxData[8]}] +set_property PACKAGE_PIN AJ24 [get_ports {itIoTxData[9]}] +set_property PACKAGE_PIN AK23 [get_ports {itIoTxData[10]}] +set_property PACKAGE_PIN AC22 [get_ports {itIoTxData[11]}] +set_property PACKAGE_PIN AE23 [get_ports {itIoTxData[12]}] +set_property PACKAGE_PIN AD21 [get_ports {itIoTxData[13]}] +set_property PACKAGE_PIN AC20 [get_ports {itIoTxData[14]}] +set_property PACKAGE_PIN AA22 [get_ports {itIoTxData[15]}] + +set_property IOSTANDARD LVDS_25 [get_ports {itIoTxHeader*}] +set_property PACKAGE_PIN Y24 [get_ports itIoTxHeader_n] +set_property PACKAGE_PIN Y23 [get_ports itIoTxHeader] + +set_property IOSTANDARD LVTTL [get_ports aIrq] +set_property PACKAGE_PIN AF28 [get_ports aIrq] + +set_property IOSTANDARD LVCMOS33 [get_ports aIoPort2Restart] +set_property PULLUP TRUE [get_ports aIoPort2Restart] +set_property PACKAGE_PIN AE30 [get_ports aIoPort2Restart] + +set_property IOSTANDARD LVCMOS33 [get_ports aStc3Gpio7] +set_property PACKAGE_PIN AF30 [get_ports aStc3Gpio7] + +#******************************************************************************* +## Front Panel LEDs + +set_property PACKAGE_PIN AJ26 [get_ports LED_ACT1] +set_property PACKAGE_PIN AE26 [get_ports LED_ACT2] +set_property PACKAGE_PIN AF27 [get_ports LED_LINK1] +set_property PACKAGE_PIN AK26 [get_ports LED_LINK2] +set_property PACKAGE_PIN AF26 [get_ports LED_PPS] +set_property PACKAGE_PIN AH27 [get_ports LED_REFLOCK] +set_property PACKAGE_PIN U30 [get_ports LED_GPSLOCK] +set_property PACKAGE_PIN V27 [get_ports LED_LINKSTAT] +set_property PACKAGE_PIN V29 [get_ports LED_LINKACT] +set_property PACKAGE_PIN AD29 [get_ports LED_RX1_RX] +set_property PACKAGE_PIN AB30 [get_ports LED_RX2_RX] +set_property PACKAGE_PIN AA30 [get_ports LED_TXRX1_RX] +set_property PACKAGE_PIN Y30 [get_ports LED_TXRX1_TX] +set_property PACKAGE_PIN AB29 [get_ports LED_TXRX2_RX] +set_property PACKAGE_PIN AE29 [get_ports LED_TXRX2_TX] +set_property IOSTANDARD LVCMOS33 [get_ports {LED_*}] + +#******************************************************************************* +## Front panel GPIO on DB15 + +set_property PACKAGE_PIN Y25 [get_ports {FrontPanelGpio[0]}] +set_property PACKAGE_PIN AD27 [get_ports {FrontPanelGpio[1]}] +set_property PACKAGE_PIN AD28 [get_ports {FrontPanelGpio[2]}] +set_property PACKAGE_PIN AG30 [get_ports {FrontPanelGpio[3]}] +set_property PACKAGE_PIN AH30 [get_ports {FrontPanelGpio[4]}] +set_property PACKAGE_PIN AC26 [get_ports {FrontPanelGpio[5]}] +set_property PACKAGE_PIN AD26 [get_ports {FrontPanelGpio[6]}] +set_property PACKAGE_PIN AJ27 [get_ports {FrontPanelGpio[7]}] +set_property PACKAGE_PIN AK28 [get_ports {FrontPanelGpio[8]}] +set_property PACKAGE_PIN AG27 [get_ports {FrontPanelGpio[9]}] +set_property PACKAGE_PIN AG28 [get_ports {FrontPanelGpio[10]}] +set_property PACKAGE_PIN AH26 [get_ports {FrontPanelGpio[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FrontPanelGpio*}] +set_property PULLDOWN TRUE [get_ports {FrontPanelGpio*}] + +#******************************************************************************* +## LMK04816 Clock Control + +set_property PACKAGE_PIN Y26 [get_ports {LMK_Status[0]}] +set_property PACKAGE_PIN AA26 [get_ports {LMK_Status[1]}] +set_property PACKAGE_PIN W27 [get_ports LMK_Holdover] +set_property PACKAGE_PIN W28 [get_ports LMK_Lock] +set_property PACKAGE_PIN T27 [get_ports LMK_Sync] +set_property PACKAGE_PIN U19 [get_ports LMK_SEN] +set_property PACKAGE_PIN Y28 [get_ports LMK_MOSI] +set_property PACKAGE_PIN AA28 [get_ports LMK_SCLK] +set_property IOSTANDARD LVCMOS33 [get_ports {LMK_*}] + +#******************************************************************************* +# Micrel chip control + +set_property PACKAGE_PIN W29 [get_ports {ClockRefSelect[0]}] +set_property PACKAGE_PIN Y29 [get_ports {ClockRefSelect[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ClockRefSelect*}] + +#******************************************************************************* +## PPS, GPS and Timing + +set_property PACKAGE_PIN AB28 [get_ports GPS_LOCK_OK] +# set_property PACKAGE_PIN AA25 [get_ports GPS_NMEA_TX] +set_property PACKAGE_PIN AB25 [get_ports GPS_SER_IN] +set_property PACKAGE_PIN AC29 [get_ports GPS_SER_OUT] +set_property PACKAGE_PIN AA27 [get_ports GPS_PPS_OUT] +set_property IOSTANDARD LVCMOS33 [get_ports {GPS_*}] + +set_property PACKAGE_PIN AC30 [get_ports EXT_PPS_IN] +set_property PACKAGE_PIN T25 [get_ports EXT_PPS_OUT] +set_property IOSTANDARD LVCMOS33 [get_ports {EXT_PPS_*}] + +#******************************************************************************* +## Clocks + +set_property PACKAGE_PIN AB27 [get_ports FPGA_125MHz_CLK] +set_property IOSTANDARD LVCMOS33 [get_ports FPGA_125MHz_CLK] + +set_property PACKAGE_PIN AG23 [get_ports FPGA_CLK_n] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_CLK_n] +set_property DIFF_TERM TRUE [get_ports FPGA_CLK_n] + +set_property PACKAGE_PIN AF22 [get_ports FPGA_CLK_p] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_CLK_p] +set_property DIFF_TERM TRUE [get_ports FPGA_CLK_p] + +set_property PACKAGE_PIN E11 [get_ports GPSDO_PWR_ENA] +set_property IOSTANDARD LVCMOS33 [get_ports GPSDO_PWR_ENA] + +set_property PACKAGE_PIN A11 [get_ports TCXO_ENA] +set_property IOSTANDARD LVCMOS33 [get_ports TCXO_ENA] + +set_property PACKAGE_PIN AG24 [get_ports FPGA_REFCLK_10MHz_p] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_REFCLK_10MHz_p] + +set_property PACKAGE_PIN AH24 [get_ports FPGA_REFCLK_10MHz_n] +set_property IOSTANDARD LVDS_25 [get_ports FPGA_REFCLK_10MHz_n] + +set_property PACKAGE_PIN AA17 [get_ports CPRI_CLK_OUT_P] +set_property IOSTANDARD LVDS [get_ports CPRI_CLK_OUT_P] + +set_property PACKAGE_PIN AA16 [get_ports CPRI_CLK_OUT_N] +set_property IOSTANDARD LVDS [get_ports CPRI_CLK_OUT_N] + +#******************************************************************************* +## SFP low-speed IO + +set_property PACKAGE_PIN U24 [get_ports SFPP0_SCL] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_SCL] + +set_property PACKAGE_PIN V22 [get_ports SFPP0_SDA] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_SDA] + +set_property PACKAGE_PIN W22 [get_ports SFPP0_RS0] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_RS0] + +set_property PACKAGE_PIN W19 [get_ports SFPP0_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_RS1] + +set_property PACKAGE_PIN V21 [get_ports SFPP0_TxDisable] ;# Open drain output +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_TxDisable] + +set_property PACKAGE_PIN V24 [get_ports SFPP0_ModAbs] ;# (IJB) Should pullup on pcb +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_ModAbs] + +set_property PACKAGE_PIN W21 [get_ports SFPP0_RxLOS] ;# Input +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_RxLOS] + +set_property PACKAGE_PIN U23 [get_ports SFPP0_TxFault] ;# Input +set_property IOSTANDARD LVCMOS33 [get_ports SFPP0_TxFault] + +set_property PACKAGE_PIN V19 [get_ports SFPP1_SCL] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_SCL] + +set_property PACKAGE_PIN W26 [get_ports SFPP1_SDA] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_SDA] + +set_property PACKAGE_PIN W24 [get_ports SFPP1_RS0] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_RS0] + +set_property PACKAGE_PIN U22 [get_ports SFPP1_RS1] +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_RS1] + +set_property PACKAGE_PIN V25 [get_ports SFPP1_TxDisable] ;# Open drain output +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_TxDisable] + +set_property PACKAGE_PIN V20 [get_ports SFPP1_ModAbs] ;# (IJB) Should pullup on pcb +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_ModAbs] + +set_property PACKAGE_PIN W23 [get_ports SFPP1_RxLOS] ;# Input +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_RxLOS] + +set_property PACKAGE_PIN V30 [get_ports SFPP1_TxFault] ;# Input +set_property IOSTANDARD LVCMOS33 [get_ports SFPP1_TxFault] + +#******************************************************************************* +## Config Flash Interface + +set_property PROHIBIT TRUE [get_sites {P24}] +set_property PROHIBIT TRUE [get_sites {R25}] +set_property PROHIBIT TRUE [get_sites {R20}] +set_property PROHIBIT TRUE [get_sites {R21}] +set_property PROHIBIT TRUE [get_sites {T20}] +set_property PROHIBIT TRUE [get_sites {T21}] +set_property PROHIBIT TRUE [get_sites {T22}] +set_property PROHIBIT TRUE [get_sites {T23}] +set_property PROHIBIT TRUE [get_sites {U20}] +set_property PROHIBIT TRUE [get_sites {P29}] +set_property PROHIBIT TRUE [get_sites {R29}] +set_property PROHIBIT TRUE [get_sites {P27}] +set_property PROHIBIT TRUE [get_sites {P28}] +set_property PROHIBIT TRUE [get_sites {T30}] +set_property PROHIBIT TRUE [get_sites {P26}] +set_property PROHIBIT TRUE [get_sites {R26}] + +#******************************************************************************* +# Miscellaneous + +# Expose this pin to work around a silicon bug in Series 7 FPGA where +# race condition with the reading of PUDC during the erase of the FPGA +# image cause glitches on output IO pins +set_property PACKAGE_PIN R23 [get_ports FPGA_PUDC_B] +set_property IOSTANDARD LVCMOS33 [get_ports FPGA_PUDC_B] +set_property PULLUP TRUE [get_ports FPGA_PUDC_B] + + +#******************************************************************************* +# UNUSED or DEPOPULATED) + +# Security Chip +# set_property PACKAGE_PIN U27 [get_ports AUTH_SDA] +# set_property IOSTANDARD LVCMOS33 [get_ports AUTH_SDA] + +# set_property PACKAGE_PIN U28 [get_ports FPGA_RESET_N] +# set_property IOSTANDARD LVCMOS33 [get_ports FPGA_RESET_N] + +# UART, new on Rev B +#NET uart_tx IOSTANDARD = LVCMOS33 | LOC = R28; +#NET uart_rx IOSTANDARD = LVCMOS33 | LOC = T28; +#NET uart_wat IOSTANDARD = LVCMOS33 | LOC = T26; + +#NET aIO_Interrupt_0 IOSTANDARD = LVCMOS33 | LOC = AF28; +#NET aIO_Interrupt_1 IOSTANDARD = LVCMOS33 | LOC = AK29; +#NET aStcIO_Reset_n IOSTANDARD = LVCMOS33 | LOC = AC27; +#NET 0V75_VTT_REF IOSTANDARD = DDR15 | LOC = AD7; +#NET 0V75_VTT_REF IOSTANDARD = DDR15 | LOC = AG8; +#NET XSIG030149 IOSTANDARD = DDR15 | LOC = Y13; +#NET XSIG030150 IOSTANDARD = DDR15 | LOC = AD13; +#NET XSIG030154 IOSTANDARD = DDR15 | LOC = AB7; +#NET XSIG030186 IOSTANDARD = DDR15 | LOC = AC6; +#NET XSIG051113 IOSTANDARD = LVCMOS25 | LOC = E18; +#NET XSIG051117 IOSTANDARD = LVCMOS25 | LOC = M19; +#NET XSIG051118 IOSTANDARD = LVCMOS25 | LOC = P19; +#NET XSIG051203 IOSTANDARD = LVCMOS25 | LOC = G19; +#NET XSIG051347 IOSTANDARD = LVCMOS33 | LOC = F11; +#NET XSIG080308 IOSTANDARD = LVCMOS33 | LOC = R19; +#NET XSIG080310 IOSTANDARD = LVCMOS33 | LOC = R24; +#NET XSIG130242 IOSTANDARD = LVCMOS18 | LOC = Y14; +#NET XSIG130243 IOSTANDARD = LVCMOS18 | LOC = AB14; +#NET XSIG130258 IOSTANDARD = LVCMOS18 | LOC = AD14; +#NET XSIG130261 IOSTANDARD = LVCMOS18 | LOC = Y16; +#NET XSIG130262 IOSTANDARD = LVCMOS18 | LOC = Y15; +#NET XSIG130263 IOSTANDARD = LVCMOS25 | LOC = AH20; +#NET XSIG130265 IOSTANDARD = LVCMOS25 | LOC = AG20; + +#NET CPRI_CLK_p IOSTANDARD = LVDS_25 | LOC = U8; +#NET CPRI_CLK_n IOSTANDARD = LVDS_25 | LOC = U7; diff --git a/fpga/usrp3/top/x300/x300_10ge.xdc b/fpga/usrp3/top/x300/x300_10ge.xdc new file mode 100644 index 000000000..fef9e1fa6 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_10ge.xdc @@ -0,0 +1,19 @@ +# +# Copyright 2014 Ettus Research LLC +# + +set_property PACKAGE_PIN R8 [get_ports XG_CLK_p] +set_property PACKAGE_PIN R7 [get_ports XG_CLK_n] + +#IOSTANDARD not required because this is a GT terminal +#set_property IOSTANDARD LVDS_25 [get_ports {XG_CLK_*}] + +create_clock -name XG_CLK -period 6.400 -waveform {0.000 3.200} [get_ports XG_CLK_p] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks XG_CLK] +set_clock_groups -asynchronous -group [get_clocks bus_clk_div2] -group [get_clocks XG_CLK] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}] -group [get_clocks XG_CLK] +set_clock_groups -asynchronous -group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}] -group [get_clocks XG_CLK] + +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *PRE}] +set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/*sync1_r_reg*}] -filter {NAME =~ *CLR}] diff --git a/fpga/usrp3/top/x300/x300_10ge_port0.xdc b/fpga/usrp3/top/x300/x300_10ge_port0.xdc new file mode 100644 index 000000000..1599f3124 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_10ge_port0.xdc @@ -0,0 +1,6 @@ +# +# Copyright 2014 Ettus Research LLC +# + +set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells -hierarchical -filter {NAME =~ "*sfpp_io_i0/ten_gige_phy_i/*gtxe2_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_CHANNEL}] +set_property LOC GTXE2_COMMON_X0Y0 [get_cells -hierarchical -filter {NAME =~ "*sfpp_io_i0/ten_gige_phy_i/*gtxe2_common_0_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_COMMON}] diff --git a/fpga/usrp3/top/x300/x300_10ge_port1.xdc b/fpga/usrp3/top/x300/x300_10ge_port1.xdc new file mode 100644 index 000000000..27f1a250c --- /dev/null +++ b/fpga/usrp3/top/x300/x300_10ge_port1.xdc @@ -0,0 +1,6 @@ +# +# Copyright 2014 Ettus Research LLC +# + +set_property LOC GTXE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {NAME =~ "*sfpp_io_i1/ten_gige_phy_i/*gtxe2_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_CHANNEL}] +set_property LOC GTXE2_COMMON_X0Y1 [get_cells -hierarchical -filter {NAME =~ "*sfpp_io_i1/ten_gige_phy_i/*gtxe2_common_0_i*" && PRIMITIVE_TYPE == IO.gt.GTXE2_COMMON}] diff --git a/fpga/usrp3/top/x300/x300_1ge.xdc b/fpga/usrp3/top/x300/x300_1ge.xdc new file mode 100644 index 000000000..1aa6e0825 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_1ge.xdc @@ -0,0 +1,19 @@ +# +# Copyright 2014 Ettus Research LLC +# + +set_property PACKAGE_PIN L8 [get_ports ETH_CLK_p] +set_property PACKAGE_PIN L7 [get_ports ETH_CLK_n] + +#IOSTANDARD not required because this is a GT terminal +#set_property IOSTANDARD LVDS_25 [get_ports {ETH_CLK_*}] + +create_clock -name ETH_CLK -period 8.000 -waveform {0.000 4.000} [get_ports ETH_CLK_p] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ETH_CLK] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks -of_objects [get_pins *sfpp_io_*/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT0]] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks -of_objects [get_pins *sfpp_io_*/one_gige_phy_i/*/core_clocking_i/mmcm_*/CLKOUT1]] + +set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*reset_sync*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe_reg*/PRE}] +set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe*[0]/D}] \ No newline at end of file diff --git a/fpga/usrp3/top/x300/x300_aurora.xdc b/fpga/usrp3/top/x300/x300_aurora.xdc new file mode 100644 index 000000000..7b524a5be --- /dev/null +++ b/fpga/usrp3/top/x300/x300_aurora.xdc @@ -0,0 +1,16 @@ +# +# Copyright 2016 Ettus Research LLC +# + +set_property PACKAGE_PIN R8 [get_ports XG_CLK_p] +set_property PACKAGE_PIN R7 [get_ports XG_CLK_n] + +#IOSTANDARD not required because this is a GT terminal +#set_property IOSTANDARD LVDS_25 [get_ports {XG_CLK_*}] + +create_clock -name AUR_CLK -period 6.400 -waveform {0.000 3.200} [get_ports XG_CLK_p] +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*sfpp_io_*/*/rst_sync_sys_rst_i/*aurora_64b66b_pcs_pma_cdc_to_reg/D"}] \ No newline at end of file diff --git a/fpga/usrp3/top/x300/x300_core.v b/fpga/usrp3/top/x300/x300_core.v new file mode 100644 index 000000000..0a721e06b --- /dev/null +++ b/fpga/usrp3/top/x300/x300_core.v @@ -0,0 +1,680 @@ +// +// Copyright 2014 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +module x300_core #( + parameter BUS_CLK_RATE = 32'd166666666 +)( + //Clocks and resets + input radio_clk, + input radio_rst, + input bus_clk, + input bus_rst, + input ce_clk, + input ce_rst, + output [3:0] sw_rst, + input bus_clk_div2, + input bus_rst_div2, + // Radio 0 + input [31:0] rx0, output [31:0] tx0, + input [31:0] db0_gpio_in, output [31:0] db0_gpio_out, output [31:0] db0_gpio_ddr, + input [31:0] fp_gpio_in, output [31:0] fp_gpio_out, output [31:0] fp_gpio_ddr, + output [7:0] sen0, output sclk0, output mosi0, input miso0, + output [2:0] radio_led0, + output reg [31:0] radio0_misc_out, input [31:0] radio0_misc_in, + // Radio 1 + input [31:0] rx1, output [31:0] tx1, + input [31:0] db1_gpio_in, output [31:0] db1_gpio_out, output [31:0] db1_gpio_ddr, + output [7:0] sen1, output sclk1, output mosi1, input miso1, + output [2:0] radio_led1, + output reg [31:0] radio1_misc_out, input [31:0] radio1_misc_in, + // Radio shared misc + inout db_scl, + inout db_sda, + // Clock control + input ext_ref_clk, + output [1:0] clock_ref_sel, + output [1:0] clock_misc_opt, + input [1:0] LMK_Status, + input LMK_Holdover, input LMK_Lock, output LMK_Sync, + output LMK_SEN, output LMK_SCLK, output LMK_MOSI, + input [2:0] misc_clock_status, + // SFP+ pins + inout SFPP0_SCL, + inout SFPP0_SDA, + inout SFPP0_RS0, + inout SFPP0_RS1, + input SFPP0_ModAbs, + input SFPP0_TxFault, + input SFPP0_RxLOS, + output SFPP0_TxDisable, // Assert low to enable transmitter. + + inout SFPP1_SCL, + inout SFPP1_SDA, + inout SFPP1_RS0, + inout SFPP1_RS1, + input SFPP1_ModAbs, + input SFPP1_TxFault, + input SFPP1_RxLOS, + output SFPP1_TxDisable, // Assert low to enable transmitter. + + // SFP+ 0 data stream + output [63:0] sfp0_tx_tdata, + output [3:0] sfp0_tx_tuser, + output sfp0_tx_tlast, + output sfp0_tx_tvalid, + input sfp0_tx_tready, + + input [63:0] sfp0_rx_tdata, + input [3:0] sfp0_rx_tuser, + input sfp0_rx_tlast, + input sfp0_rx_tvalid, + output sfp0_rx_tready, + + input [15:0] sfp0_phy_status, + + // SFP+ 1 data stream + output [63:0] sfp1_tx_tdata, + output [3:0] sfp1_tx_tuser, + output sfp1_tx_tlast, + output sfp1_tx_tvalid, + input sfp1_tx_tready, + + input [63:0] sfp1_rx_tdata, + input [3:0] sfp1_rx_tuser, + input sfp1_rx_tlast, + input sfp1_rx_tvalid, + output sfp1_rx_tready, + + input [15:0] sfp1_phy_status, + + input [31:0] sfp0_wb_dat_i, + output [31:0] sfp0_wb_dat_o, + output [15:0] sfp0_wb_adr, + output [3:0] sfp0_wb_sel, + input sfp0_wb_ack, + output sfp0_wb_stb, + output sfp0_wb_cyc, + output sfp0_wb_we, + input sfp0_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300. + + input [31:0] sfp1_wb_dat_i, + output [31:0] sfp1_wb_dat_o, + output [15:0] sfp1_wb_adr, + output [3:0] sfp1_wb_sel, + input sfp1_wb_ack, + output sfp1_wb_stb, + output sfp1_wb_cyc, + output sfp1_wb_we, + input sfp1_wb_int, // IJB. Nothing to connect this too!! No IRQ controller on x300. + + input [31:0] xadc_readback, + + // Time + input pps, + output [1:0] pps_select, + output pps_out_enb, + output [31:0] ref_freq, + output ref_freq_changed, + output gps_txd, + input gps_rxd, + // Debug UART + input debug_rxd, + output debug_txd, + + // + // AXI4 (128b@250MHz) interface to DDR3 controller + // + input ddr3_axi_clk, + input ddr3_axi_clk_x2, + input ddr3_axi_rst, + // Write Address Ports + output ddr3_axi_awid, + output [31:0] ddr3_axi_awaddr, + output [7:0] ddr3_axi_awlen, + output [2:0] ddr3_axi_awsize, + output [1:0] ddr3_axi_awburst, + output [0:0] ddr3_axi_awlock, + output [3:0] ddr3_axi_awcache, + output [2:0] ddr3_axi_awprot, + output [3:0] ddr3_axi_awqos, + output ddr3_axi_awvalid, + input ddr3_axi_awready, + // Write Data Ports + output [255:0] ddr3_axi_wdata, + output [31:0] ddr3_axi_wstrb, + output ddr3_axi_wlast, + output ddr3_axi_wvalid, + input ddr3_axi_wready, + // Write Response Ports + output ddr3_axi_bready, + input ddr3_axi_bid, + input [1:0] ddr3_axi_bresp, + input ddr3_axi_bvalid, + // Read Address Ports + output ddr3_axi_arid, + output [31:0] ddr3_axi_araddr, + output [7:0] ddr3_axi_arlen, + output [2:0] ddr3_axi_arsize, + output [1:0] ddr3_axi_arburst, + output [0:0] ddr3_axi_arlock, + output [3:0] ddr3_axi_arcache, + output [2:0] ddr3_axi_arprot, + output [3:0] ddr3_axi_arqos, + output ddr3_axi_arvalid, + input ddr3_axi_arready, + // Read Data Ports + output ddr3_axi_rready, + input ddr3_axi_rid, + input [255:0] ddr3_axi_rdata, + input [1:0] ddr3_axi_rresp, + input ddr3_axi_rlast, + input ddr3_axi_rvalid, + + //iop2 message fifos + output [63:0] o_iop2_msg_tdata, + output o_iop2_msg_tvalid, + output o_iop2_msg_tlast, + input o_iop2_msg_tready, + input [63:0] i_iop2_msg_tdata, + input i_iop2_msg_tvalid, + input i_iop2_msg_tlast, + output i_iop2_msg_tready, + + //PCIe + output [63:0] pcio_tdata, + output [2:0] pcio_tuser, + output pcio_tlast, + output pcio_tvalid, + input pcio_tready, + input [63:0] pcii_tdata, + input [2:0] pcii_tuser, + input pcii_tlast, + input pcii_tvalid, + output pcii_tready, + + // Debug + output [1:0] led_misc, + output [31:0] debug0, + output [31:0] debug1, + output [127:0] debug2 +); + + // Memory Controller AXI4 MM buses + wire s00_axi_awready, s01_axi_awready; + wire [0:0] s00_axi_awid, s01_axi_awid; + wire [31:0] s00_axi_awaddr, s01_axi_awaddr; + wire [7:0] s00_axi_awlen, s01_axi_awlen; + wire [2:0] s00_axi_awsize, s01_axi_awsize; + wire [1:0] s00_axi_awburst, s01_axi_awburst; + wire [0:0] s00_axi_awlock, s01_axi_awlock; + wire [3:0] s00_axi_awcache, s01_axi_awcache; + wire [2:0] s00_axi_awprot, s01_axi_awprot; + wire [3:0] s00_axi_awqos, s01_axi_awqos; + wire [3:0] s00_axi_awregion, s01_axi_awregion; + wire [0:0] s00_axi_awuser, s01_axi_awuser; + wire s00_axi_wready, s01_axi_wready; + wire [63:0] s00_axi_wdata, s01_axi_wdata; + wire [7:0] s00_axi_wstrb, s01_axi_wstrb; + wire [0:0] s00_axi_wuser, s01_axi_wuser; + wire s00_axi_bvalid, s01_axi_bvalid; + wire [0:0] s00_axi_bid, s01_axi_bid; + wire [1:0] s00_axi_bresp, s01_axi_bresp; + wire [0:0] s00_axi_buser, s01_axi_buser; + wire s00_axi_arready, s01_axi_arready; + wire [0:0] s00_axi_arid, s01_axi_arid; + wire [31:0] s00_axi_araddr, s01_axi_araddr; + wire [7:0] s00_axi_arlen, s01_axi_arlen; + wire [2:0] s00_axi_arsize, s01_axi_arsize; + wire [1:0] s00_axi_arburst, s01_axi_arburst; + wire [0:0] s00_axi_arlock, s01_axi_arlock; + wire [3:0] s00_axi_arcache, s01_axi_arcache; + wire [2:0] s00_axi_arprot, s01_axi_arprot; + wire [3:0] s00_axi_arqos, s01_axi_arqos; + wire [3:0] s00_axi_arregion, s01_axi_arregion; + wire [0:0] s00_axi_aruser, s01_axi_aruser; + wire s00_axi_rlast, s01_axi_rlast; + wire s00_axi_rvalid, s01_axi_rvalid; + wire s00_axi_awvalid, s01_axi_awvalid; + wire s00_axi_wlast, s01_axi_wlast; + wire s00_axi_wvalid, s01_axi_wvalid; + wire s00_axi_bready, s01_axi_bready; + wire s00_axi_arvalid, s01_axi_arvalid; + wire s00_axi_rready, s01_axi_rready; + wire [0:0] s00_axi_rid, s01_axi_rid; + wire [63:0] s00_axi_rdata, s01_axi_rdata; + wire [1:0] s00_axi_rresp, s01_axi_rresp; + wire [0:0] s00_axi_ruser, s01_axi_ruser; + + + ///////////////////////////////////////////////////////////////////////////////// + // PPS synchronization logic + ///////////////////////////////////////////////////////////////////////////////// + wire pps_rclk, pps_detect; + pps_synchronizer pps_sync_inst ( + .ref_clk(ext_ref_clk), .timebase_clk(radio_clk), + .pps_in(pps), .pps_out(pps_rclk), .pps_count(pps_detect) + ); + + ///////////////////////////////////////////////////////////////////////////////// + // Bus Int containing soft CPU control, routing fabric + ///////////////////////////////////////////////////////////////////////////////// + + // Number of Radio Cores Instantiated + localparam NUM_RADIOS = 2; + localparam NUM_DBOARDS = NUM_RADIOS; + localparam NUM_CHANNELS_PER_RADIO = 2; + localparam NUM_CHANNELS = NUM_CHANNELS_PER_RADIO * NUM_RADIOS; + localparam NUM_CHANNELS_PER_DBOARD = NUM_CHANNELS_PER_RADIO; + + bus_int #( + .NUM_RADIOS(NUM_RADIOS), + .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), + .NUM_CHANNELS(NUM_CHANNELS) + ) bus_int_i ( + .clk(bus_clk), .clk_div2(bus_clk_div2), .reset(bus_rst), .reset_div2(bus_rst_div2), + .sen(LMK_SEN), .sclk(LMK_SCLK), .mosi(LMK_MOSI), .miso(1'b0), + .scl0(SFPP0_SCL), .sda0(SFPP0_SDA), + .scl1(db_scl), .sda1(db_sda), + .scl2(SFPP1_SCL), .sda2(SFPP1_SDA), + .gps_txd(gps_txd), .gps_rxd(gps_rxd), + .debug_txd(debug_txd), .debug_rxd(debug_rxd), + .leds(led_misc), .sw_rst(sw_rst), + // Timekeeper + .pps(pps_rclk), + // Block connections + .ce_clk (ce_clk), + .ce_rst (ce_rst), + + // Radio connections + .radio_clk (radio_clk), + .radio_rst (radio_rst), + .radio_rx_stb ({ rx_stb[3], rx_stb[2], rx_stb[1], rx_stb[0]}), + .radio_rx_data ({ rx_data[3], rx_data[2], rx_data[1], rx_data[0]}), + .radio_rx_running ({ rx_running[3], rx_running[2], rx_running[1], rx_running[0]}), + .radio_tx_stb ({ tx_stb[3], tx_stb[2], tx_stb[1], tx_stb[0]}), + .radio_tx_data ({ tx_data[3], tx_data[2], tx_data[1], tx_data[0]}), + .radio_tx_running ({ tx_running[3], tx_running[2], tx_running[1], tx_running[0]}), + // Daughter board settings buses + .db_fe_set_stb ({ db_fe_set_stb[1], db_fe_set_stb[0]}), + .db_fe_set_addr({db_fe_set_addr[1], db_fe_set_addr[0]}), + .db_fe_set_data({db_fe_set_data[1], db_fe_set_data[0]}), + .db_fe_rb_stb ({ db_fe_rb_stb[1], db_fe_rb_stb[0]}), + .db_fe_rb_addr ({ db_fe_rb_addr[1], db_fe_rb_addr[0]}), + .db_fe_rb_data ({ db_fe_rb_data[1], db_fe_rb_data[0]}), + // SFP 0 + .SFPP0_ModAbs(SFPP0_ModAbs),.SFPP0_TxFault(SFPP0_TxFault),.SFPP0_RxLOS(SFPP0_RxLOS), + .SFPP0_RS0(SFPP0_RS0), .SFPP0_RS1(SFPP0_RS1), + // SFP 1 + .SFPP1_ModAbs(SFPP1_ModAbs),.SFPP1_TxFault(SFPP1_TxFault),.SFPP1_RxLOS(SFPP1_RxLOS), + .SFPP1_RS0(SFPP1_RS0), .SFPP1_RS1(SFPP1_RS1), + //clocky locky misc + .clock_status({misc_clock_status, pps_detect, LMK_Holdover, LMK_Lock, LMK_Status}), + .clock_control({1'b0, clock_misc_opt[1:0], pps_out_enb, pps_select[1:0], clock_ref_sel[1:0]}), + .ref_freq(ref_freq), .ref_freq_changed(ref_freq_changed), + // Eth0 + .sfp0_tx_tdata(sfp0_tx_tdata), .sfp0_tx_tuser(sfp0_tx_tuser), .sfp0_tx_tlast(sfp0_tx_tlast), + .sfp0_tx_tvalid(sfp0_tx_tvalid), .sfp0_tx_tready(sfp0_tx_tready), + .sfp0_rx_tdata(sfp0_rx_tdata), .sfp0_rx_tuser(sfp0_rx_tuser), .sfp0_rx_tlast(sfp0_rx_tlast), + .sfp0_rx_tvalid(sfp0_rx_tvalid), .sfp0_rx_tready(sfp0_rx_tready), + // Eth1 + .sfp1_tx_tdata(sfp1_tx_tdata), .sfp1_tx_tuser(sfp1_tx_tuser), .sfp1_tx_tlast(sfp1_tx_tlast), + .sfp1_tx_tvalid(sfp1_tx_tvalid), .sfp1_tx_tready(sfp1_tx_tready), + .sfp1_rx_tdata(sfp1_rx_tdata), .sfp1_rx_tuser(sfp1_rx_tuser), .sfp1_rx_tlast(sfp1_rx_tlast), + .sfp1_rx_tvalid(sfp1_rx_tvalid), .sfp1_rx_tready(sfp1_rx_tready), + // IoP2 Msgs + .o_iop2_msg_tdata(o_iop2_msg_tdata), .o_iop2_msg_tvalid(o_iop2_msg_tvalid), .o_iop2_msg_tlast(o_iop2_msg_tlast), .o_iop2_msg_tready(o_iop2_msg_tready), + .i_iop2_msg_tdata(i_iop2_msg_tdata), .i_iop2_msg_tvalid(i_iop2_msg_tvalid), .i_iop2_msg_tlast(i_iop2_msg_tlast), .i_iop2_msg_tready(i_iop2_msg_tready), + // PCIe + .pcio_tdata(pcio_tdata), .pcio_tuser(pcio_tuser), .pcio_tlast(pcio_tlast), .pcio_tvalid(pcio_tvalid), .pcio_tready(pcio_tready), + .pcii_tdata(pcii_tdata), .pcii_tuser(pcii_tuser), .pcii_tlast(pcii_tlast), .pcii_tvalid(pcii_tvalid), .pcii_tready(pcii_tready), + // Wishbone Slave Interface(s) + .sfp0_wb_dat_i(sfp0_wb_dat_i), .sfp0_wb_dat_o(sfp0_wb_dat_o), .sfp0_wb_adr(sfp0_wb_adr), + .sfp0_wb_sel(sfp0_wb_sel), .sfp0_wb_ack(sfp0_wb_ack), .sfp0_wb_stb(sfp0_wb_stb), + .sfp0_wb_cyc(sfp0_wb_cyc), .sfp0_wb_we(sfp0_wb_we), .sfp0_wb_int(sfp0_wb_int), + .sfp1_wb_dat_i(sfp1_wb_dat_i), .sfp1_wb_dat_o(sfp1_wb_dat_o), .sfp1_wb_adr(sfp1_wb_adr), + .sfp1_wb_sel(sfp1_wb_sel), .sfp1_wb_ack(sfp1_wb_ack), .sfp1_wb_stb(sfp1_wb_stb), + .sfp1_wb_cyc(sfp1_wb_cyc), .sfp1_wb_we(sfp1_wb_we), .sfp1_wb_int(sfp1_wb_int), + //Status signals + .sfp0_phy_status(sfp0_phy_status), + .sfp1_phy_status(sfp1_phy_status), + .xadc_readback(xadc_readback), + + // DRAM interface + .ddr3_axi_clk_x2 (ddr3_axi_clk_x2), + .ddr3_axi_rst (ddr3_axi_rst), + // Slave Interface Write Address Ports + .ddr3_axi_awid ({s01_axi_awid, s00_axi_awid}), + .ddr3_axi_awaddr ({s01_axi_awaddr, s00_axi_awaddr}), + .ddr3_axi_awlen ({s01_axi_awlen, s00_axi_awlen}), + .ddr3_axi_awsize ({s01_axi_awsize, s00_axi_awsize}), + .ddr3_axi_awburst ({s01_axi_awburst, s00_axi_awburst}), + .ddr3_axi_awlock ({s01_axi_awlock, s00_axi_awlock}), + .ddr3_axi_awcache ({s01_axi_awcache, s00_axi_awcache}), + .ddr3_axi_awprot ({s01_axi_awprot, s00_axi_awprot}), + .ddr3_axi_awqos ({s01_axi_awqos, s00_axi_awqos}), + .ddr3_axi_awvalid ({s01_axi_awvalid, s00_axi_awvalid}), + .ddr3_axi_awready ({s01_axi_awready, s00_axi_awready}), + // Slave Interface Write Data Ports + .ddr3_axi_wdata ({s01_axi_wdata, s00_axi_wdata}), + .ddr3_axi_wstrb ({s01_axi_wstrb, s00_axi_wstrb}), + .ddr3_axi_wlast ({s01_axi_wlast, s00_axi_wlast}), + .ddr3_axi_wvalid ({s01_axi_wvalid, s00_axi_wvalid}), + .ddr3_axi_wready ({s01_axi_wready, s00_axi_wready}), + // Slave Interface Write Response Ports + .ddr3_axi_bid ({s01_axi_bid, s00_axi_bid}), + .ddr3_axi_bresp ({s01_axi_bresp, s00_axi_bresp}), + .ddr3_axi_bvalid ({s01_axi_bvalid, s00_axi_bvalid}), + .ddr3_axi_bready ({s01_axi_bready, s00_axi_bready}), + // Slave Interface Read Address Ports + .ddr3_axi_arid ({s01_axi_arid, s00_axi_arid}), + .ddr3_axi_araddr ({s01_axi_araddr, s00_axi_araddr}), + .ddr3_axi_arlen ({s01_axi_arlen, s00_axi_arlen}), + .ddr3_axi_arsize ({s01_axi_arsize, s00_axi_arsize}), + .ddr3_axi_arburst ({s01_axi_arburst, s00_axi_arburst}), + .ddr3_axi_arlock ({s01_axi_arlock, s00_axi_arlock}), + .ddr3_axi_arcache ({s01_axi_arcache, s00_axi_arcache}), + .ddr3_axi_arprot ({s01_axi_arprot, s00_axi_arprot}), + .ddr3_axi_arqos ({s01_axi_arqos, s00_axi_arqos}), + .ddr3_axi_arvalid ({s01_axi_arvalid, s00_axi_arvalid}), + .ddr3_axi_arready ({s01_axi_arready, s00_axi_arready}), + // Slave Interface Read Data Ports + .ddr3_axi_rid ({s01_axi_rid, s00_axi_rid}), + .ddr3_axi_rdata ({s01_axi_rdata, s00_axi_rdata}), + .ddr3_axi_rresp ({s01_axi_rresp, s00_axi_rresp}), + .ddr3_axi_rlast ({s01_axi_rlast, s00_axi_rlast}), + .ddr3_axi_rvalid ({s01_axi_rvalid, s00_axi_rvalid}), + .ddr3_axi_rready ({s01_axi_rready, s00_axi_rready}), + // Debug + .debug0(debug0), .debug1(debug1), .debug2(debug2) + ); + + axi_intercon_2x64_128_bd_wrapper axi_intercon_2x64_128_bd_i ( + .S00_AXI_ACLK(ddr3_axi_clk_x2), // input S00_AXI_ACLK + .S00_AXI_ARESETN(~ddr3_axi_rst), // input S00_AXI_ARESETN + .S00_AXI_AWID(s00_axi_awid), // input [0 : 0] S00_AXI_AWID + .S00_AXI_AWADDR(s00_axi_awaddr), // input [31 : 0] S00_AXI_AWADDR + .S00_AXI_AWLEN(s00_axi_awlen), // input [7 : 0] S00_AXI_AWLEN + .S00_AXI_AWSIZE(s00_axi_awsize), // input [2 : 0] S00_AXI_AWSIZE + .S00_AXI_AWBURST(s00_axi_awburst), // input [1 : 0] S00_AXI_AWBURST + .S00_AXI_AWLOCK(s00_axi_awlock), // input S00_AXI_AWLOCK + .S00_AXI_AWCACHE(s00_axi_awcache), // input [3 : 0] S00_AXI_AWCACHE + .S00_AXI_AWPROT(s00_axi_awprot), // input [2 : 0] S00_AXI_AWPROT + .S00_AXI_AWQOS(s00_axi_awqos), // input [3 : 0] S00_AXI_AWQOS + .S00_AXI_AWVALID(s00_axi_awvalid), // input S00_AXI_AWVALID + .S00_AXI_AWREADY(s00_axi_awready), // output S00_AXI_AWREADY + .S00_AXI_WDATA(s00_axi_wdata), // input [63 : 0] S00_AXI_WDATA + .S00_AXI_WSTRB(s00_axi_wstrb), // input [7 : 0] S00_AXI_WSTRB + .S00_AXI_WLAST(s00_axi_wlast), // input S00_AXI_WLAST + .S00_AXI_WVALID(s00_axi_wvalid), // input S00_AXI_WVALID + .S00_AXI_WREADY(s00_axi_wready), // output S00_AXI_WREADY + .S00_AXI_BID(s00_axi_bid), // output [0 : 0] S00_AXI_BID + .S00_AXI_BRESP(s00_axi_bresp), // output [1 : 0] S00_AXI_BRESP + .S00_AXI_BVALID(s00_axi_bvalid), // output S00_AXI_BVALID + .S00_AXI_BREADY(s00_axi_bready), // input S00_AXI_BREADY + .S00_AXI_ARID(s00_axi_arid), // input [0 : 0] S00_AXI_ARID + .S00_AXI_ARADDR(s00_axi_araddr), // input [31 : 0] S00_AXI_ARADDR + .S00_AXI_ARLEN(s00_axi_arlen), // input [7 : 0] S00_AXI_ARLEN + .S00_AXI_ARSIZE(s00_axi_arsize), // input [2 : 0] S00_AXI_ARSIZE + .S00_AXI_ARBURST(s00_axi_arburst), // input [1 : 0] S00_AXI_ARBURST + .S00_AXI_ARLOCK(s00_axi_arlock), // input S00_AXI_ARLOCK + .S00_AXI_ARCACHE(s00_axi_arcache), // input [3 : 0] S00_AXI_ARCACHE + .S00_AXI_ARPROT(s00_axi_arprot), // input [2 : 0] S00_AXI_ARPROT + .S00_AXI_ARQOS(s00_axi_arqos), // input [3 : 0] S00_AXI_ARQOS + .S00_AXI_ARVALID(s00_axi_arvalid), // input S00_AXI_ARVALID + .S00_AXI_ARREADY(s00_axi_arready), // output S00_AXI_ARREADY + .S00_AXI_RID(s00_axi_rid), // output [0 : 0] S00_AXI_RID + .S00_AXI_RDATA(s00_axi_rdata), // output [63 : 0] S00_AXI_RDATA + .S00_AXI_RRESP(s00_axi_rresp), // output [1 : 0] S00_AXI_RRESP + .S00_AXI_RLAST(s00_axi_rlast), // output S00_AXI_RLAST + .S00_AXI_RVALID(s00_axi_rvalid), // output S00_AXI_RVALID + .S00_AXI_RREADY(s00_axi_rready), // input S00_AXI_RREADY + // + .S01_AXI_ACLK(ddr3_axi_clk_x2), // input S01_AXI_ACLK + .S01_AXI_ARESETN(~ddr3_axi_rst), // input S00_AXI_ARESETN + .S01_AXI_AWID(s01_axi_awid), // input [0 : 0] S01_AXI_AWID + .S01_AXI_AWADDR(s01_axi_awaddr), // input [31 : 0] S01_AXI_AWADDR + .S01_AXI_AWLEN(s01_axi_awlen), // input [7 : 0] S01_AXI_AWLEN + .S01_AXI_AWSIZE(s01_axi_awsize), // input [2 : 0] S01_AXI_AWSIZE + .S01_AXI_AWBURST(s01_axi_awburst), // input [1 : 0] S01_AXI_AWBURST + .S01_AXI_AWLOCK(s01_axi_awlock), // input S01_AXI_AWLOCK + .S01_AXI_AWCACHE(s01_axi_awcache), // input [3 : 0] S01_AXI_AWCACHE + .S01_AXI_AWPROT(s01_axi_awprot), // input [2 : 0] S01_AXI_AWPROT + .S01_AXI_AWQOS(s01_axi_awqos), // input [3 : 0] S01_AXI_AWQOS + .S01_AXI_AWVALID(s01_axi_awvalid), // input S01_AXI_AWVALID + .S01_AXI_AWREADY(s01_axi_awready), // output S01_AXI_AWREADY + .S01_AXI_WDATA(s01_axi_wdata), // input [63 : 0] S01_AXI_WDATA + .S01_AXI_WSTRB(s01_axi_wstrb), // input [7 : 0] S01_AXI_WSTRB + .S01_AXI_WLAST(s01_axi_wlast), // input S01_AXI_WLAST + .S01_AXI_WVALID(s01_axi_wvalid), // input S01_AXI_WVALID + .S01_AXI_WREADY(s01_axi_wready), // output S01_AXI_WREADY + .S01_AXI_BID(s01_axi_bid), // output [0 : 0] S01_AXI_BID + .S01_AXI_BRESP(s01_axi_bresp), // output [1 : 0] S01_AXI_BRESP + .S01_AXI_BVALID(s01_axi_bvalid), // output S01_AXI_BVALID + .S01_AXI_BREADY(s01_axi_bready), // input S01_AXI_BREADY + .S01_AXI_ARID(s01_axi_arid), // input [0 : 0] S01_AXI_ARID + .S01_AXI_ARADDR(s01_axi_araddr), // input [31 : 0] S01_AXI_ARADDR + .S01_AXI_ARLEN(s01_axi_arlen), // input [7 : 0] S01_AXI_ARLEN + .S01_AXI_ARSIZE(s01_axi_arsize), // input [2 : 0] S01_AXI_ARSIZE + .S01_AXI_ARBURST(s01_axi_arburst), // input [1 : 0] S01_AXI_ARBURST + .S01_AXI_ARLOCK(s01_axi_arlock), // input S01_AXI_ARLOCK + .S01_AXI_ARCACHE(s01_axi_arcache), // input [3 : 0] S01_AXI_ARCACHE + .S01_AXI_ARPROT(s01_axi_arprot), // input [2 : 0] S01_AXI_ARPROT + .S01_AXI_ARQOS(s01_axi_arqos), // input [3 : 0] S01_AXI_ARQOS + .S01_AXI_ARVALID(s01_axi_arvalid), // input S01_AXI_ARVALID + .S01_AXI_ARREADY(s01_axi_arready), // output S01_AXI_ARREADY + .S01_AXI_RID(s01_axi_rid), // output [0 : 0] S01_AXI_RID + .S01_AXI_RDATA(s01_axi_rdata), // output [63 : 0] S01_AXI_RDATA + .S01_AXI_RRESP(s01_axi_rresp), // output [1 : 0] S01_AXI_RRESP + .S01_AXI_RLAST(s01_axi_rlast), // output S01_AXI_RLAST + .S01_AXI_RVALID(s01_axi_rvalid), // output S01_AXI_RVALID + .S01_AXI_RREADY(s01_axi_rready), // input S01_AXI_RREADY + // + .M00_AXI_ACLK(ddr3_axi_clk), // input M00_AXI_ACLK + .M00_AXI_ARESETN(~ddr3_axi_rst), // input S00_AXI_ARESETN + .M00_AXI_AWID(ddr3_axi_awid), // output [3 : 0] M00_AXI_AWID + .M00_AXI_AWADDR(ddr3_axi_awaddr), // output [31 : 0] M00_AXI_AWADDR + .M00_AXI_AWLEN(ddr3_axi_awlen), // output [7 : 0] M00_AXI_AWLEN + .M00_AXI_AWSIZE(ddr3_axi_awsize), // output [2 : 0] M00_AXI_AWSIZE + .M00_AXI_AWBURST(ddr3_axi_awburst), // output [1 : 0] M00_AXI_AWBURST + .M00_AXI_AWLOCK(ddr3_axi_awlock), // output M00_AXI_AWLOCK + .M00_AXI_AWCACHE(ddr3_axi_awcache), // output [3 : 0] M00_AXI_AWCACHE + .M00_AXI_AWPROT(ddr3_axi_awprot), // output [2 : 0] M00_AXI_AWPROT + .M00_AXI_AWQOS(ddr3_axi_awqos), // output [3 : 0] M00_AXI_AWQOS + .M00_AXI_AWVALID(ddr3_axi_awvalid), // output M00_AXI_AWVALID + .M00_AXI_AWREADY(ddr3_axi_awready), // input M00_AXI_AWREADY + .M00_AXI_WDATA(ddr3_axi_wdata), // output [255 : 0] M00_AXI_WDATA + .M00_AXI_WSTRB(ddr3_axi_wstrb), // output [15 : 0] M00_AXI_WSTRB + .M00_AXI_WLAST(ddr3_axi_wlast), // output M00_AXI_WLAST + .M00_AXI_WVALID(ddr3_axi_wvalid), // output M00_AXI_WVALID + .M00_AXI_WREADY(ddr3_axi_wready), // input M00_AXI_WREADY + .M00_AXI_BID(ddr3_axi_bid), // input [3 : 0] M00_AXI_BID + .M00_AXI_BRESP(ddr3_axi_bresp), // input [1 : 0] M00_AXI_BRESP + .M00_AXI_BVALID(ddr3_axi_bvalid), // input M00_AXI_BVALID + .M00_AXI_BREADY(ddr3_axi_bready), // output M00_AXI_BREADY + .M00_AXI_ARID(ddr3_axi_arid), // output [3 : 0] M00_AXI_ARID + .M00_AXI_ARADDR(ddr3_axi_araddr), // output [31 : 0] M00_AXI_ARADDR + .M00_AXI_ARLEN(ddr3_axi_arlen), // output [7 : 0] M00_AXI_ARLEN + .M00_AXI_ARSIZE(ddr3_axi_arsize), // output [2 : 0] M00_AXI_ARSIZE + .M00_AXI_ARBURST(ddr3_axi_arburst), // output [1 : 0] M00_AXI_ARBURST + .M00_AXI_ARLOCK(ddr3_axi_arlock), // output M00_AXI_ARLOCK + .M00_AXI_ARCACHE(ddr3_axi_arcache), // output [3 : 0] M00_AXI_ARCACHE + .M00_AXI_ARPROT(ddr3_axi_arprot), // output [2 : 0] M00_AXI_ARPROT + .M00_AXI_ARQOS(ddr3_axi_arqos), // output [3 : 0] M00_AXI_ARQOS + .M00_AXI_ARVALID(ddr3_axi_arvalid), // output M00_AXI_ARVALID + .M00_AXI_ARREADY(ddr3_axi_arready), // input M00_AXI_ARREADY + .M00_AXI_RID(ddr3_axi_rid), // input [3 : 0] M00_AXI_RID + .M00_AXI_RDATA(ddr3_axi_rdata), // input [255 : 0] M00_AXI_RDATA + .M00_AXI_RRESP(ddr3_axi_rresp), // input [1 : 0] M00_AXI_RRESP + .M00_AXI_RLAST(ddr3_axi_rlast), // input M00_AXI_RLAST + .M00_AXI_RVALID(ddr3_axi_rvalid), // input M00_AXI_RVALID + .M00_AXI_RREADY(ddr3_axi_rready) // output M00_AXI_RREADY + ); + + + + ///////////////////////////////////////////////////////////////////////////////////////////// + // + // Radios + // + ///////////////////////////////////////////////////////////////////////////////////////////// + + // Daughter board I/O + wire [31:0] leds[0:NUM_DBOARDS-1]; + wire [31:0] fp_gpio_r_in[0:NUM_DBOARDS-1], fp_gpio_r_out[0:NUM_DBOARDS-1], fp_gpio_r_ddr[0:NUM_DBOARDS-1]; + wire [31:0] db_gpio_in[0:NUM_DBOARDS-1], db_gpio_out[0:NUM_DBOARDS-1], db_gpio_ddr[0:NUM_DBOARDS-1]; + wire [31:0] misc_outs[0:NUM_DBOARDS-1]; + reg [31:0] misc_ins[0:NUM_DBOARDS-1]; + wire [7:0] sen[0:NUM_DBOARDS-1]; + wire sclk[0:NUM_DBOARDS-1], mosi[0:NUM_DBOARDS-1], miso[0:NUM_DBOARDS-1]; + wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1]; + wire [63:0] rx_data_in_r[0:NUM_DBOARDS-1], rx_data_r[0:NUM_DBOARDS-1]; + wire [63:0] tx_data_r[0:NUM_DBOARDS-1], tx_data_out_r[0:NUM_DBOARDS-1]; + wire [1:0] rx_stb_r[0:NUM_DBOARDS-1], tx_stb_r[0:NUM_DBOARDS-1]; + + + // Data + wire [31:0] rx_data_in[0:NUM_CHANNELS-1], rx_data[0:NUM_CHANNELS-1]; + wire [31:0] tx_data[0:NUM_CHANNELS-1], tx_data_out[0:NUM_CHANNELS-1]; + wire rx_stb[0:NUM_CHANNELS-1], tx_stb[0:NUM_CHANNELS-1]; + wire db_fe_set_stb[0:NUM_DBOARDS-1]; + wire [7:0] db_fe_set_addr[0:NUM_DBOARDS-1]; + wire [31:0] db_fe_set_data[0:NUM_DBOARDS-1]; + wire db_fe_rb_stb[0:NUM_DBOARDS-1]; + wire [7:0] db_fe_rb_addr[0:NUM_DBOARDS-1]; + wire [63:0] db_fe_rb_data[0:NUM_DBOARDS-1]; + + + //------------------------------------ + // Daughterboard Control + // ----------------------------------- + + localparam [7:0] SR_DB_BASE = 8'd160; + localparam [7:0] RB_DB_BASE = 8'd16; + + genvar i; + generate for (i = 0; i < NUM_DBOARDS; i = i + 1) + begin + db_control #( + .USE_SPI_CLK(0), + .SR_BASE(SR_DB_BASE), + .RB_BASE(RB_DB_BASE) + ) db_control_i ( + .clk(radio_clk), .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]), + .rb_stb(db_fe_rb_stb[i]), .rb_addr(db_fe_rb_addr[i]), .rb_data(db_fe_rb_data[i]), + .run_rx(rx_running[i*2]), .run_tx(tx_running[i*2]), + .misc_ins(misc_ins[i]), .misc_outs(misc_outs[i]), + .fp_gpio_in(fp_gpio_r_in[i]), .fp_gpio_out(fp_gpio_r_out[i]), .fp_gpio_ddr(fp_gpio_r_ddr[i]), .fp_gpio_fab(), + .db_gpio_in(db_gpio_in[i]), .db_gpio_out(db_gpio_out[i]), .db_gpio_ddr(db_gpio_ddr[i]), .db_gpio_fab(), + .leds(leds[i]), + .spi_clk(radio_clk), .spi_rst(radio_rst), .sen(sen[i]), .sclk(sclk[i]), .mosi(mosi[i]), .miso(miso[i]) + ); + end + endgenerate + + //------------------------------------ + // Front End Control + // ----------------------------------- + + localparam [7:0] SR_FE_CHAN_OFFSET = 8'd16; + localparam [7:0] SR_TX_FE_BASE = SR_DB_BASE + 8'd48; + localparam [7:0] SR_RX_FE_BASE = SR_DB_BASE + 8'd64; + + generate for (i = 0; i < NUM_DBOARDS; i = i + 1) + begin + fe_control #( + .NUM_CHANNELS(NUM_CHANNELS_PER_DBOARD), + .SR_FE_CHAN_OFFSET(SR_FE_CHAN_OFFSET), + .SR_TX_FE_BASE(SR_TX_FE_BASE), + .SR_RX_FE_BASE(SR_RX_FE_BASE) + ) x300_fe_core_i ( + .clk(radio_clk), .reset(radio_rst), + .set_stb(db_fe_set_stb[i]), .set_addr(db_fe_set_addr[i]), .set_data(db_fe_set_data[i]), + .time_sync(), + .tx_stb(tx_stb_r[i]), .tx_data_in(tx_data_r[i]), .tx_data_out(tx_data_out_r[i]), + .rx_stb(rx_stb_r[i]), .rx_data_in(rx_data_in_r[i]), .rx_data_out(rx_data_r[i]) + ); + end + endgenerate + + //------------------------------------ + // Radio to ADC,DAC and IO Mapping + //------------------------------------ + + // Data + assign tx_data_r[0][31:0] = tx_data[0]; + assign tx_data_r[0][63:32] = tx_data[1]; + assign tx_data_r[1][31:0] = tx_data[2]; + assign tx_data_r[1][63:32] = tx_data[3]; + + assign tx_data_out[0] = tx_data_out_r[0][31:0] ; + assign tx_data_out[1] = tx_data_out_r[0][63:32]; + assign tx_data_out[2] = tx_data_out_r[1][31:0] ; + assign tx_data_out[3] = tx_data_out_r[1][63:32]; + + assign tx_stb_r[0][0] = tx_stb[0]; + assign tx_stb_r[0][1] = tx_stb[1]; + assign tx_stb_r[1][0] = tx_stb[2]; + assign tx_stb_r[1][1] = tx_stb[3]; + + assign rx_data_in_r[0][31:0] = rx_data_in[0]; + assign rx_data_in_r[0][63:32] = rx_data_in[1]; + assign rx_data_in_r[1][31:0] = rx_data_in[2]; + assign rx_data_in_r[1][63:32] = rx_data_in[3]; + + assign rx_data[0] = rx_data_r[0][31:0] ; + assign rx_data[1] = rx_data_r[0][63:32]; + assign rx_data[2] = rx_data_r[1][31:0] ; + assign rx_data[3] = rx_data_r[1][63:32]; + + assign rx_stb[0] = rx_stb_r[0][0]; + assign rx_stb[1] = rx_stb_r[0][1]; + assign rx_stb[2] = rx_stb_r[1][0]; + assign rx_stb[3] = rx_stb_r[1][1]; + + assign {rx_data_in[1], rx_data_in[0]} = {rx0, rx0}; + assign {rx_data_in[3], rx_data_in[2]} = {rx1, rx1}; + + assign tx0 = tx_data_out[0]; //tx_data_out[1] unused + assign tx1 = tx_data_out[2]; //tx_data_out[3] unused + assign tx_stb[0] = 1'b1; + assign tx_stb[1] = 1'b0; + assign tx_stb[2] = 1'b1; + assign tx_stb[3] = 1'b0; + + //Daughter board GPIO + assign {db_gpio_in[1], db_gpio_in[0]} = {db1_gpio_in, db0_gpio_in}; + assign db0_gpio_out = db_gpio_out[0]; + assign db1_gpio_out = db_gpio_out[1]; + assign db0_gpio_ddr = db_gpio_ddr[0]; + assign db1_gpio_ddr = db_gpio_ddr[1]; + + //Front-panel board GPIO + assign {fp_gpio_r_in[1], fp_gpio_r_in[0]} = {32'b0, fp_gpio_in}; + assign fp_gpio_out = fp_gpio_r_out[0]; //fp_gpio_r_out[1] unused + assign fp_gpio_ddr = fp_gpio_r_ddr[0]; //fp_gpio_ddr[1] unused + + //SPI + assign {sen0, sclk0, mosi0} = {sen[0], sclk[0], mosi[0]}; + assign miso[0] = miso0; + assign {sen1, sclk1, mosi1} = {sen[1], sclk[1], mosi[1]}; + assign miso[1] = miso1; + + //LEDs + // Reminder: radio_ledX = {RX, TXRX_TX, TXRX_RX} + assign radio_led0 = leds[0][2:0]; + assign radio_led1 = leds[1][2:0]; + + //Misc ins and outs + always @(posedge radio_clk) begin + radio0_misc_out <= misc_outs[0]; + radio1_misc_out <= misc_outs[1]; + misc_ins[0] <= radio0_misc_in; + misc_ins[1] <= radio1_misc_in; + end + +endmodule // x300_core diff --git a/fpga/usrp3/top/x300/x300_dram.xdc b/fpga/usrp3/top/x300/x300_dram.xdc new file mode 100644 index 000000000..e5f04b1d7 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_dram.xdc @@ -0,0 +1,16 @@ +# +# Copyright 2015-2017 Ettus Research LLC +# + +create_generated_clock -name ddr3_axi_clk [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT"}] +create_generated_clock -name ddr3_axi_clk_x2 [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks mmcm_ps_clk_bufg_in] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ddr3_axi_clk] +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks ddr3_axi_clk_x2] + +# Floorplan the MIG and the primary AXI4 interconnect +# create_pblock pblock_dram_iface +# resize_pblock pblock_dram_iface -add {SLICE_X104Y0:SLICE_X153Y149 DSP48_X3Y0:DSP48_X5Y59 RAMB18_X3Y0:RAMB18_X6Y59 RAMB36_X3Y0:RAMB36_X6Y29} +# add_cells_to_pblock pblock_dram_iface [get_cells [list u_ddr3_32bit]] -clear_locs +# add_cells_to_pblock pblock_dram_iface [get_cells [list x300_core/axi_intercon_2x64_128_bd_i]] -clear_locs diff --git a/fpga/usrp3/top/x300/x300_eth_interface.v b/fpga/usrp3/top/x300/x300_eth_interface.v new file mode 100644 index 000000000..fc1cbe115 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_eth_interface.v @@ -0,0 +1,114 @@ +// +// Copyright 2014 Ettus Research LLC +// Copyright 2018 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Adapts from internal VITA to ethernet packets. Also handles ZPU and ethernet crossover interfaces. + +module x300_eth_interface #( + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter MTU = 10, + parameter NODE_INST = 0, + parameter RT_TBL_SIZE = 6, + parameter BASE = 0 +) ( + input clk, input reset, + input [15:0] device_id, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + // Eth ports + output [63:0] eth_tx_tdata, output [3:0] eth_tx_tuser, output eth_tx_tlast, output eth_tx_tvalid, input eth_tx_tready, + input [63:0] eth_rx_tdata, input [3:0] eth_rx_tuser, input eth_rx_tlast, input eth_rx_tvalid, output eth_rx_tready, + // Vita router interface + output [63:0] e2v_tdata, output e2v_tlast, output e2v_tvalid, input e2v_tready, + input [63:0] v2e_tdata, input v2e_tlast, input v2e_tvalid, output v2e_tready, + // ZPU + output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready, + input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready +); + + // UNUSED: BASE to BASE+7 + localparam MY_ETH_ADDR_LO_REG = BASE + 8; + localparam MY_ETH_ADDR_HI_REG = BASE + 9; + localparam MY_IP_ADDR_REG = BASE + 10; + localparam MY_UDP_PORT_REG = BASE + 11; + // UNUSED: BASE+12 to BASE+15 + + wire [47:0] my_eth_addr; + wire [31:0] my_ipv4_addr; + wire [15:0] my_udp_chdr_port; + + // MAC address for the dispatcher module. + // This value is used to determine if the packet is meant + // for this device should be consumed + setting_reg #(.my_addr(MY_ETH_ADDR_LO_REG), .awidth(8), .width(32)) sr_my_mac_lsb + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(my_eth_addr[31:0]),.changed()); + setting_reg #(.my_addr(MY_ETH_ADDR_HI_REG), .awidth(8), .width(16)) sr_my_mac_msb + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(my_eth_addr[47:32]),.changed()); + + // IP address for the dispatcher module. + // This value is used to determine if the packet is addressed + // to this device + setting_reg #(.my_addr(MY_IP_ADDR_REG), .awidth(8), .width(32)) sr_my_ip + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(my_ipv4_addr[31:0]),.changed()); + + // This module supports one destinatio port + setting_reg #(.my_addr(MY_UDP_PORT_REG), .awidth(8), .width(16)) sr_udp_port + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({my_udp_chdr_port[15:0]}),.changed()); + + eth_ipv4_chdr64_adapter #( + .PROTOVER (PROTOVER), + .MTU (MTU), + .CPU_FIFO_SIZE (MTU), + .RT_TBL_SIZE (RT_TBL_SIZE), + .NODE_INST (NODE_INST), + .DROP_UNKNOWN_MAC(1) + ) eth_adapter_i ( + .clk (clk ), + .rst (reset ), + .device_id (device_id ), + .s_mac_tdata (eth_rx_tdata ), + .s_mac_tuser (eth_rx_tuser ), + .s_mac_tlast (eth_rx_tlast ), + .s_mac_tvalid (eth_rx_tvalid ), + .s_mac_tready (eth_rx_tready ), + .m_mac_tdata (eth_tx_tdata ), + .m_mac_tuser (eth_tx_tuser ), + .m_mac_tlast (eth_tx_tlast ), + .m_mac_tvalid (eth_tx_tvalid ), + .m_mac_tready (eth_tx_tready ), + .s_chdr_tdata (v2e_tdata ), + .s_chdr_tlast (v2e_tlast ), + .s_chdr_tvalid (v2e_tvalid ), + .s_chdr_tready (v2e_tready ), + .m_chdr_tdata (e2v_tdata ), + .m_chdr_tlast (e2v_tlast ), + .m_chdr_tvalid (e2v_tvalid ), + .m_chdr_tready (e2v_tready ), + .s_cpu_tdata ({z2e_tdata[7:0], z2e_tdata[15:8], + z2e_tdata[23:16], z2e_tdata[31:24], + z2e_tdata[39:32], z2e_tdata[47:40], + z2e_tdata[55:48], z2e_tdata[63:56]}), + .s_cpu_tuser (z2e_tuser ), + .s_cpu_tlast (z2e_tlast ), + .s_cpu_tvalid (z2e_tvalid ), + .s_cpu_tready (z2e_tready ), + .m_cpu_tdata ({e2z_tdata[7:0], e2z_tdata[15:8], + e2z_tdata[23:16], e2z_tdata[31:24], + e2z_tdata[39:32], e2z_tdata[47:40], + e2z_tdata[55:48], e2z_tdata[63:56]}), + .m_cpu_tuser (e2z_tuser ), + .m_cpu_tlast (e2z_tlast ), + .m_cpu_tvalid (e2z_tvalid ), + .m_cpu_tready (e2z_tready ), + .my_eth_addr (my_eth_addr ), + .my_ipv4_addr (my_ipv4_addr ), + .my_udp_chdr_port(my_udp_chdr_port) + ); + + +endmodule // x300_eth_interface diff --git a/fpga/usrp3/top/x300/x300_pcie_int.v b/fpga/usrp3/top/x300/x300_pcie_int.v new file mode 100644 index 000000000..145d48283 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_pcie_int.v @@ -0,0 +1,382 @@ +// +// Copyright 2013 Ettus Research LLC +// Copyright 2017 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Parameters: +// - DMA_STREAM_WIDTH: Width of the data bus. It'll be a big suprise if this is +// anything other than 64. +// - NUM_TX_STREAMS: Number of TX FIFOs. +// - NUM_RX_STREAMS: Number of RX FIFOs. Note: Despite having two different +// parameters, NUM_TX_STREAMS and NUM_RX_STREAMS need to be +// identical. + +`define GET_DMA_BUS(parallel_bus, chan_idx) parallel_bus[(DMA_STREAM_WIDTH*(chan_idx+1))-1:(DMA_STREAM_WIDTH*chan_idx)] +`define GET_FSIZE_BUS(parallel_bus, chan_idx) parallel_bus[(DMA_FRAME_SIZE_WIDTH*(chan_idx+1))-1:(DMA_FRAME_SIZE_WIDTH*chan_idx)] +`define GET_SWAP_BUS(parallel_bus, chan_idx) parallel_bus[(3*(chan_idx+1))-1:(3*chan_idx)] + +module x300_pcie_int #( + parameter DMA_STREAM_WIDTH = 64, + parameter NUM_TX_STREAMS = 6, + parameter NUM_RX_STREAMS = 6, + parameter REGPORT_ADDR_WIDTH = 20, + parameter REGPORT_DATA_WIDTH = 32, + parameter IOP2_MSG_WIDTH = 64, + parameter BUS_CLK_RATE = 32'd166666666 +) ( + //--------------------------------------------------------- + // Clocks and Resets + //--------------------------------------------------------- + input ioport2_clk, + input bus_clk, + input bus_rst, + + //--------------------------------------------------------- + // DMA streams to/from Chinch Interface to IoPort2 (Domain: ioport2_clk) + //--------------------------------------------------------- + input [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_iop2, + input [NUM_TX_STREAMS-1:0] dmatx_tvalid_iop2, + output [NUM_TX_STREAMS-1:0] dmatx_tready_iop2, + + output [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_iop2, + output [NUM_RX_STREAMS-1:0] dmarx_tvalid_iop2, + input [NUM_RX_STREAMS-1:0] dmarx_tready_iop2, + + //--------------------------------------------------------- + // DMA stream to/from crossbar (Domain: bus_clk) + //--------------------------------------------------------- + output [DMA_STREAM_WIDTH-1:0] dmatx_tdata, + output [2:0] dmatx_tuser, + output dmatx_tvalid, + output dmatx_tlast, + input dmatx_tready, + + input [DMA_STREAM_WIDTH-1:0] dmarx_tdata, + input [2:0] dmarx_tuser, + input dmarx_tvalid, + input dmarx_tlast, + output dmarx_tready, + + //--------------------------------------------------------- + // PCIe User register port (Domain: ioport2_clk) + //--------------------------------------------------------- + input pcie_usr_reg_wr, + input pcie_usr_reg_rd, + input [REGPORT_ADDR_WIDTH-1:0] pcie_usr_reg_addr, + input [REGPORT_DATA_WIDTH-1:0] pcie_usr_reg_data_in, + input [1:0] pcie_usr_reg_len, + output [REGPORT_DATA_WIDTH-1:0] pcie_usr_reg_data_out, + output pcie_usr_reg_rc, + output pcie_usr_reg_rdy, + + //--------------------------------------------------------- + // PCIe Chinch register port (Domain: ioport2_clk) + //--------------------------------------------------------- + output chinch_reg_wr, + output chinch_reg_rd, + output [REGPORT_ADDR_WIDTH-1:0] chinch_reg_addr, + output [REGPORT_DATA_WIDTH-1:0] chinch_reg_data_out, + output [1:0] chinch_reg_len, + input [REGPORT_DATA_WIDTH-1:0] chinch_reg_data_in, + input chinch_reg_rc, + input chinch_reg_rdy, + + //--------------------------------------------------------- + // Message FIFOs to/from the core logic (Domain: bus_clk) + //--------------------------------------------------------- + input [IOP2_MSG_WIDTH-1:0] rego_tdata, + input rego_tvalid, + input rego_tlast, + output rego_tready, + + output [IOP2_MSG_WIDTH-1:0] regi_tdata, + output regi_tvalid, + output regi_tlast, + input regi_tready, + + //--------------------------------------------------------- + // Misc + //--------------------------------------------------------- + input [15:0] misc_status, + output [127:0] debug +); + + localparam REG_CLK_XING_FIFO_SIZE = 5; //Will synthesize fifo_short_2clk + localparam DMA_CLK_XING_FIFO_SIZE = 5; //Will synthesize fifo_short_2clk + localparam DMA_PKT_GATE_FIFO_SIZE = 11; //Room for 2 8k packets + localparam DMA_FRAME_SIZE_WIDTH = 16; + localparam DMA_RX_DEST_WIDTH = $clog2(NUM_RX_STREAMS); + + //******************************************************************************* + // Message FIFO translator + clock crossing + // + wire msgo_tvalid, msgi_tvalid, msgo_tready, msgi_tready; + wire [63:0] msgo_tdata, msgi_tdata; + + + wire pcie_out_valid, pcie_in_valid; + wire [63:0] pcie_out_msg, pcie_in_msg; + + //Link chinch register port and user register port to AXI message FIFOs + wire iop2_rd_response, iop2_wr_request, iop2_rd_request; + wire [31:0] iop2_data; + + wire chinch_reg_is_half_word; + ioport2_msg_decode pcie_out_msg_decoder ( + .message(pcie_out_msg), + .rd_response(iop2_rd_response), .wr_request(iop2_wr_request), .rd_request(iop2_rd_request), .half_word(chinch_reg_is_half_word), + .address(chinch_reg_addr), .data(iop2_data)); + assign chinch_reg_len = chinch_reg_is_half_word ? 2'b01 : 2'b10; + + assign pcie_usr_reg_rc = iop2_rd_response & pcie_out_valid; + assign chinch_reg_wr = iop2_wr_request & pcie_out_valid; + assign chinch_reg_rd = iop2_rd_request & pcie_out_valid; + assign chinch_reg_data_out = iop2_data; + assign pcie_usr_reg_data_out = iop2_data; + + ioport2_msg_encode pcie_in_msg_encoder ( + .rd_response(chinch_reg_rc), .wr_request(pcie_usr_reg_wr), .rd_request(pcie_usr_reg_rd), .half_word(pcie_usr_reg_len == 2'b01), + .address(pcie_usr_reg_addr), .data(chinch_reg_rc ? chinch_reg_data_in : pcie_usr_reg_data_in), + .message(pcie_in_msg)); + + assign pcie_in_valid = chinch_reg_rc | pcie_usr_reg_wr | pcie_usr_reg_rd; + + //Cross from the Ioport2 clock domain to the bus clock domain + axi_fifo_2clk #(.WIDTH(64), .SIZE(REG_CLK_XING_FIFO_SIZE)) pcie_out_msg_fifo ( + .reset(bus_rst), + .i_aclk(bus_clk), .i_tdata(msgo_tdata), .i_tvalid(msgo_tvalid), .i_tready(msgo_tready), + .o_aclk(ioport2_clk), .o_tdata(pcie_out_msg), .o_tvalid(pcie_out_valid), .o_tready(chinch_reg_rdy | pcie_usr_reg_rc)); + + axi_fifo_2clk #(.WIDTH(64), .SIZE(REG_CLK_XING_FIFO_SIZE)) pcie_in_msg_fifo ( + .reset(bus_rst), + .i_aclk(ioport2_clk), .i_tdata(pcie_in_msg), .i_tvalid(pcie_in_valid), .i_tready(pcie_usr_reg_rdy), + .o_aclk(bus_clk), .o_tdata(msgi_tdata), .o_tvalid(msgi_tvalid), .o_tready(msgi_tready)); + // + //******************************************************************************* + + wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_enabled; + wire [NUM_TX_STREAMS-1:0] dmatx_samp_stb, dmatx_pkt_stb, dmatx_busy, dmatx_error; + wire [(NUM_TX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmatx_frame_size; + + wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_enabled; + wire [NUM_RX_STREAMS-1:0] dmarx_samp_stb, dmarx_pkt_stb, dmarx_busy, dmarx_error; + wire [(NUM_RX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmarx_frame_size; + wire [DMA_STREAM_WIDTH-1:0] dmarx_header; + + //******************************************************************************* + // PCIe message/register endpoints + // + wire [63:0] basic_regi_tdata, dmatx_regi_tdata, dmarx_regi_tdata; + wire basic_regi_tvalid, dmatx_regi_tvalid, dmarx_regi_tvalid; + wire basic_regi_tready, dmatx_regi_tready, dmarx_regi_tready; + wire [63:0] basic_rego_tdata, dmatx_rego_tdata, dmarx_rego_tdata; + wire basic_rego_tvalid, dmatx_rego_tvalid, dmarx_rego_tvalid; + wire basic_rego_tready, dmatx_rego_tready, dmarx_rego_tready; + + pcie_iop2_msg_arbiter #( + //(DO NOT USE) //0x00000 - 0x3FFFC: Reserved LVFPGA Core Space + .E0_ADDR(20'h40000), .E0_MASK(20'hFFE00), //0x40000 - 0x401FC: Basic PCIe registers + .E1_ADDR(20'h40200), .E1_MASK(20'hFFE00), //0x40200 - 0x403FC: TX DMA Config/Readback registers + .E2_ADDR(20'h40400), .E2_MASK(20'hFFE00), //0x40400 - 0x405FC: RX DMA Config/Readback registers + .E3_ADDR(20'h60000), .E3_MASK(20'hE0000) //0x60000 - 0x7FFFC: Client address space + ) iop2_msg_arbiter ( + .clk(bus_clk), .reset(bus_rst), + //Master + .regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready), + .rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready), + //Endpoint 0 + .e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready), + .e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready), + //Endpoint 1 + .e1_regi_tdata(dmatx_regi_tdata), .e1_regi_tvalid(dmatx_regi_tvalid), .e1_regi_tready(dmatx_regi_tready), + .e1_rego_tdata(dmatx_rego_tdata), .e1_rego_tvalid(dmatx_rego_tvalid), .e1_rego_tready(dmatx_rego_tready), + //Endpoint 2 + .e2_regi_tdata(dmarx_regi_tdata), .e2_regi_tvalid(dmarx_regi_tvalid), .e2_regi_tready(dmarx_regi_tready), + .e2_rego_tdata(dmarx_rego_tdata), .e2_rego_tvalid(dmarx_rego_tvalid), .e2_rego_tready(dmarx_rego_tready), + //Endpoint 3 + .e3_regi_tdata(regi_tdata), .e3_regi_tvalid(regi_tvalid), .e3_regi_tready(regi_tready), + .e3_rego_tdata(rego_tdata), .e3_rego_tvalid(rego_tvalid), .e3_rego_tready(rego_tready) + ); + assign regi_tlast = regi_tvalid; + + wire [15:0] fpga_status; + assign fpga_status[7:0] = {|(dmatx_error), 1'b0, dmatx_enabled}; + assign fpga_status[15:8] = {|(dmarx_error), 1'b0, dmarx_enabled}; + + pcie_basic_regs #( + .SIGNATURE(32'h58333030 /*ASCII:"X300"*/), .CLK_FREQ(BUS_CLK_RATE) + ) basic_regs ( + .clk(bus_clk), .reset(bus_rst), + .regi_tdata(basic_regi_tdata), .regi_tvalid(basic_regi_tvalid), .regi_tready(basic_regi_tready), + .rego_tdata(basic_rego_tdata), .rego_tvalid(basic_rego_tvalid), .rego_tready(basic_rego_tready), + .misc_status({fpga_status, misc_status}) + ); + + pcie_dma_ctrl #( + .NUM_STREAMS(NUM_TX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH), + .REG_BASE_ADDR(20'h40200), .ENABLE_ROUTER(0) + ) tx_dma_ctrl_regs ( + .clk(bus_clk), .reset(bus_rst), + .regi_tdata(dmatx_regi_tdata), .regi_tvalid(dmatx_regi_tvalid), .regi_tready(dmatx_regi_tready), + .rego_tdata(dmatx_rego_tdata), .rego_tvalid(dmatx_rego_tvalid), .rego_tready(dmatx_rego_tready), + .set_enabled(dmatx_enabled), .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size), + .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb), + .stream_busy(dmatx_busy), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst() + ); + + pcie_dma_ctrl #( + .NUM_STREAMS(NUM_RX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH), + .REG_BASE_ADDR(20'h40400), .ENABLE_ROUTER(0) + ) rx_dma_ctrl_regs ( + .clk(bus_clk), .reset(bus_rst), + .regi_tdata(dmarx_regi_tdata), .regi_tvalid(dmarx_regi_tvalid), .regi_tready(dmarx_regi_tready), + .rego_tdata(dmarx_rego_tdata), .rego_tvalid(dmarx_rego_tvalid), .rego_tready(dmarx_rego_tready), + .set_enabled(dmarx_enabled), .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size), + .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb), + .stream_busy(dmarx_busy), .stream_err(dmarx_error), .rtr_sid(8'h00), .rtr_dst() + ); + // + //******************************************************************************* + + //******************************************************************************* + // TX DMA Datapath + // + wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_in, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap; + wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_in, dmatx_tvalid_trun, dmatx_tvalid_gt; + wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_in, dmatx_tready_trun, dmatx_tready_gt; + wire [NUM_TX_STREAMS-1:0] dmatx_tlast_trun, dmatx_tlast_gt; + // Output of the axi_mux8 + wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata_mux; + wire [DMA_RX_DEST_WIDTH-1:0] dmatx_tuser_mux; + wire dmatx_tvalid_mux, dmatx_tlast_mux, dmatx_tready_mux; + + genvar i; + generate + for (i=0; i PCS) + .xgmii_txd(xgmii_txd), // Transmit data from client MAC. + .xgmii_txc(xgmii_txc), // Transmit control signal from client MAC. + .xgmii_rxd(xgmii_rxd), // Received Data to client MAC. + .xgmii_rxc(xgmii_rxc), // Received control signal to client MAC. + // Tranceiver Interface + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_in(mdio_in), // Management Data In + .mdio_out(mdio_out), // Management Data Out + .mdio_tri(), // Management Data Tristate + .prtad(5'd4), // MDIO address is 4 + // General IO's + .core_status(xgmii_status), // Core status + .resetdone(xge_phy_resetdone), + .signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.) + .tx_fault(sfpp_tx_fault), + .tx_disable(sfpp_tx_disable) + ); + + xge_mac_wrapper #( + .PORTNUM(PORTNUM), + .WISHBONE(1) + ) xge_mac_wrapper_i ( + // XGMII + .xgmii_clk(gb_refclk), + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + // MDIO + .mdc(mdc), + .mdio_in(mdio_in), + .mdio_out(mdio_out), + // Wishbone I/F + .wb_clk_i(bus_clk_div2), + .wb_rst_i(bus_rst_div2), + .wb_adr_i(wb_adr_i), + .wb_cyc_i(wb_cyc_i), + .wb_dat_i(wb_dat_i), + .wb_stb_i(wb_stb_i), + .wb_we_i(wb_we_i), + .wb_ack_o(wb_ack_o), + .wb_dat_o(wb_dat_o), + .wb_int_o(wb_int_o), + // Client FIFO Interfaces + .sys_clk(bus_clk), + .sys_rst(bus_rst), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now. + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // Other + .phy_ready(xge_phy_resetdone) + ); + + assign phy_status = {8'h00, xgmii_status}; + + // Use the PCS Block Lock signal to drive the link_up LED on the FP. + // For further details, see Xilinx' PG068, Table 2-11 (core_status[0] signal). + synchronizer #(.INITIAL_VAL(1'b0)) link_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(xgmii_status[0]), .out(link_up)); + + + end else if (PROTOCOL == "1GbE") begin + + //----------------------------------------------------------------- + // 1 Gigabit Ethernet + //----------------------------------------------------------------- + wire [7:0] gmii_txd, gmii_rxd; + wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er; + wire gmii_clk; + + assign sfpp_tx_disable = 1'b0; // Always on. + + one_gige_phy one_gige_phy_i + ( + .reset(areset), // Asynchronous reset for entire core. + .independent_clock(bus_clk), + // Tranceiver Interface + .gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality. + .gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG + .txp(txp), // Differential +ve of serial transmission from PMA to PMD. + .txn(txn), // Differential -ve of serial transmission from PMA to PMD. + .rxp(rxp), // Differential +ve for serial reception from PMD to PMA. + .rxn(rxn), // Differential -ve for serial reception from PMD to PMA. + // GMII Interface (client MAC <=> PCS) + .gmii_clk(gmii_clk), // Clock to client MAC. + .gmii_txd(gmii_txd), // Transmit data from client MAC. + .gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC. + .gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC. + .gmii_rxd(gmii_rxd), // Received Data to client MAC. + .gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC. + .gmii_rx_er(gmii_rx_er), // Received control signal to client MAC. + // Management: MDIO Interface + .mdc(mdc), // Management Data Clock + .mdio_i(mdio_in), // Management Data In + .mdio_o(mdio_out), // Management Data Out + .mdio_t(), // Management Data Tristate + .configuration_vector(5'd0), // Alternative to MDIO interface. + .configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented) + // General IO's + .status_vector(phy_status), // Core status. + .signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input. + ); + + simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i + ( + .clk125(gmii_clk), + .reset(areset), + + .GMII_GTX_CLK(), + .GMII_TX_EN(gmii_tx_en), + .GMII_TX_ER(gmii_tx_er), + .GMII_TXD(gmii_txd), + .GMII_RX_CLK(gmii_clk), + .GMII_RX_DV(gmii_rx_dv), + .GMII_RX_ER(gmii_rx_er), + .GMII_RXD(gmii_rxd), + + .sys_clk(bus_clk), + .rx_tdata(m_axis_tdata), + .rx_tuser(m_axis_tuser), + .rx_tlast(m_axis_tlast), + .rx_tvalid(m_axis_tvalid), + .rx_tready(m_axis_tready), + .tx_tdata(c2mac_tdata), + .tx_tuser(c2mac_tuser), + .tx_tlast(c2mac_tlast), + .tx_tvalid(c2mac_tvalid), + .tx_tready(c2mac_tready), + // MDIO + .mdc(mdc), + .mdio_in(mdio_in), + .mdio_out(mdio_out), + .mdio_tri(), + // Wishbone I/F + .wb_clk_i(bus_clk_div2), + .wb_rst_i(bus_rst_div2), + .wb_adr_i(wb_adr_i), + .wb_cyc_i(wb_cyc_i), + .wb_dat_i(wb_dat_o), + .wb_stb_i(wb_stb_i), + .wb_we_i(wb_we_i), + .wb_ack_o(wb_ack_o), + .wb_dat_o(wb_dat_i), + .wb_int_o(wb_int_o), + // Debug + .debug_tx(), .debug_rx() + ); + + // Use the Link Status signal to drive the link_up LED on the FP. + // For further details, see Xilinx' PG047, Table 2-76 (status_vector[0]). + synchronizer #(.INITIAL_VAL(1'b0)) link_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(phy_status[0]), .out(link_up)); + + + end else if (PROTOCOL == "Aurora") begin + + //----------------------------------------------------------------- + // Aurora + //----------------------------------------------------------------- + wire au_user_clk, au_user_rst, phy_areset; + wire [63:0] i_tdata, o_tdata; + wire i_tvalid, i_tready, o_tvalid; + wire channel_up, hard_err, soft_err; + wire mac_clear; + + assign sfpp_tx_disable = 1'b0; // Always on. + + aurora_phy_x1 aurora_phy_i ( + // Resets + .areset(areset | phy_areset), + // Clocks + .refclk(gt_refclk), + .init_clk(misc_clk), + .user_clk(au_user_clk), + .user_rst(au_user_rst), + // GTX Serial I/O + .tx_p(txp), + .tx_n(txn), + .rx_p(rxp), + .rx_n(rxn), + // AXI4-Stream TX Interface + .s_axis_tdata(i_tdata), + .s_axis_tvalid(i_tvalid), + .s_axis_tready(i_tready), + // AXI4-Stream RX Interface + .m_axis_tdata(o_tdata), + .m_axis_tvalid(o_tvalid), + // AXI4-Lite Config Interface: TODO: Hook up to WB->AXI4Lite converter + .s_axi_awaddr(32'h0), + .s_axi_araddr(32'h0), + .s_axi_awvalid(1'b0), + .s_axi_awready(), + .s_axi_wdata(32'h0), + .s_axi_wvalid(1'b0), + .s_axi_wstrb(1'b0), + .s_axi_wready(), + .s_axi_bvalid(), + .s_axi_bresp(), + .s_axi_bready(1'b1), + .s_axi_arready(), + .s_axi_arvalid(1'b0), + .s_axi_rdata(), + .s_axi_rvalid(), + .s_axi_rresp(), + .s_axi_rready(1'b1), + // Status and Error Reporting Interface + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err) + ); + + assign phy_status = {14'd0, hard_err, channel_up}; + + wire bist_gen_en, bist_checker_en, bist_loopback_en; + wire bist_checker_locked; + wire [5:0] bist_gen_rate; + wire [47:0] bist_checker_samps, bist_checker_errors; + wire [31:0] overruns, checksum_errors; + + aurora_axis_mac #( + .PHY_ENDIANNESS ("LITTLE"), + .PACKET_MODE (1), + .MAX_PACKET_SIZE(1024), + .BIST_ENABLED (1) + ) aurora_mac_i ( + // Clocks and resets + .phy_clk(au_user_clk), .phy_rst(au_user_rst), + .sys_clk(bus_clk), .sys_rst(bus_rst), + .clear(mac_clear), + // PHY Interface (Synchronous to phy_clk) + .phy_s_axis_tdata(o_tdata), + .phy_s_axis_tvalid(o_tvalid), + .phy_m_axis_tdata(i_tdata), + .phy_m_axis_tvalid(i_tvalid), + .phy_m_axis_tready(i_tready), + // User Interface (Synchronous to sys_clk) + .s_axis_tdata(c2mac_tdata), + .s_axis_tlast(c2mac_tlast), + .s_axis_tvalid(c2mac_tvalid), + .s_axis_tready(c2mac_tready), + .m_axis_tdata(m_axis_tdata), + .m_axis_tlast(m_axis_tlast), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + // PHY Status Inputs (Synchronous to phy_clk) + .channel_up(channel_up), + .hard_err(hard_err), + .soft_err(soft_err), + // Status and Error Outputs (Synchronous to sys_clk) + .overruns(overruns), + .soft_errors(), + .checksum_errors(checksum_errors), + .critical_err(mac_crit_err), + // BIST Interface (Synchronous to sys_clk) + .bist_gen_en(bist_gen_en), + .bist_gen_rate(bist_gen_rate), + .bist_checker_en(bist_checker_en), + .bist_loopback_en(bist_loopback_en), + .bist_checker_locked(bist_checker_locked), + .bist_checker_samps(bist_checker_samps), + .bist_checker_errors(bist_checker_errors) + ); + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + assign m_axis_tuser = 4'd0; + + wire set_stb; + wire [3:0] set_addr, rb_addr; + wire [31:0] set_data; + reg [31:0] rb_data; + + settings_bus #(.AWIDTH(8), .DWIDTH(32), .SWIDTH(4)) settings_bus_i ( + .wb_clk(bus_clk), .wb_rst(bus_rst), + .wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), + .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_ack_o(wb_ack_o), + .strobe(set_stb), .addr(set_addr), .data(set_data) + ); + + settings_readback #(.AWIDTH(8),.DWIDTH(32), .RB_ADDRW(4)) settings_readback_i ( + .wb_clk(bus_clk), .wb_rst(bus_rst), + .wb_adr_i(wb_adr_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_dat_o(wb_dat_o), + .rb_data(rb_data), .rb_addr(rb_addr), .rb_rd_stb() + ); + + setting_reg #(.my_addr(4'd0), .awidth(4), .width(11), .at_reset(11'h000)) set_core_control_i ( + .clk(bus_clk), .rst(bus_rst), + .strobe(set_stb), .addr(set_addr), .in(set_data), + .out({mac_clear, phy_areset, bist_gen_rate, bist_loopback_en, bist_gen_en, bist_checker_en}), .changed() + ); + + wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk; + synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk)); + synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync ( + .clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk)); + + reg [19:0] bist_lock_latency; + always @(posedge bus_clk) begin + if (!bist_checker_en && !bist_checker_locked) + bist_lock_latency <= 20'd0; + else if (bist_checker_en && !bist_checker_locked) + bist_lock_latency <= bist_lock_latency + 20'd1; + end + + reg mac_crit_err_latch; + always @(posedge bus_clk) begin + if (bus_rst | mac_clear) begin + mac_crit_err_latch <= 1'b0; + end else begin + if (mac_crit_err_bclk) + mac_crit_err_latch <= 1'b1; + end + end + + wire [31:0] core_status = { + 6'h0, //[31:26] + mac_crit_err_latch, //[25] + 1, //[24] mmcm_locked_bclk + 1, //[23] gt_pll_locked_bclk + 0, //[22] qpll_refclklost_bclk + 1, //[21] qpll_lock_bclk + 0, //[20] qpll_reset_bclk + bist_lock_latency[19:4], //[19:4] + bist_checker_locked, //[3] + soft_err_bclk, //[2] + hard_err_bclk, //[1] + channel_up_bclk //[0] + }; + + assign link_up = channel_up_bclk; + + always @(*) + case (rb_addr) + 4'd0: rb_data = core_status; + 4'd1: rb_data = overruns; + 4'd2: rb_data = checksum_errors; + 4'd3: rb_data = bist_checker_samps[47:16]; //Scale num sample by 2^16 + 4'd4: rb_data = bist_checker_errors[31:0]; //Dont scale errors + default: rb_data = 32'h0; + endcase // case (rb_addr) + + end else begin + + //Invalid protocol + + end +endgenerate + + //----------------------------------------------------------------- + // Activity detector + //----------------------------------------------------------------- + + pulse_stretch act_pulse_str_i ( + .clk(bus_clk), + .rst(bus_rst | ~link_up), + .pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)), + .pulse_stretched(activity) + ); + +endmodule + diff --git a/fpga/usrp3/top/x300/x300_static_router.hex b/fpga/usrp3/top/x300/x300_static_router.hex new file mode 100644 index 000000000..53635706f --- /dev/null +++ b/fpga/usrp3/top/x300/x300_static_router.hex @@ -0,0 +1,13 @@ +0000000C +00400140 +014001c0 +01c00180 +01800040 +01c10181 +01810080 +00c00200 +02000280 +02800240 +024000c0 +02810241 +02410100 diff --git a/fpga/usrp3/top/x300/x300_zpu_config.vhd b/fpga/usrp3/top/x300/x300_zpu_config.vhd new file mode 100644 index 000000000..e19380280 --- /dev/null +++ b/fpga/usrp3/top/x300/x300_zpu_config.vhd @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +package zpu_config is + -- generate trace output or not. + constant Generate_Trace : boolean := false; + constant wordPower : integer := 5; + -- during simulation, set this to '0' to get matching trace.txt + constant DontCareValue : std_logic := '0'; + -- Clock frequency in MHz. + constant ZPU_Frequency : std_logic_vector(7 downto 0) := x"40"; + -- This is the msb address bit. bytes=2^(maxAddrBitIncIO+1) + constant maxAddrBitIncIO : integer := 15; + + -- start byte address of stack. + -- point to top of RAM - 2*words + constant spStart : std_logic_vector(maxAddrBitIncIO downto 0) := x"7ff8"; + +end zpu_config; diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v new file mode 100644 index 000000000..73124f119 --- /dev/null +++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v @@ -0,0 +1,1051 @@ +// +// Copyright 2019 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// + +// Module: rfnoc_image_core (for x300) +// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) +// Re-running that tool will overwrite this file! +// File generated on: 2019-11-14T12:14:56.022475 +// Source: ./x310_rfnoc_image_core.yml +// Source SHA256: 41b259b31e2a09272ffb146ef99afe1672a44c86dd51104fa4d1821ad24d5518 + +module rfnoc_image_core #( + parameter [15:0] PROTOVER = {8'd1, 8'd0} +)( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio_clk, + input wire ce_clk, + input wire dram_clk, + // Basic + input wire [15:0] device_id, +//// IO ports ////////////////////////////////// +// ctrlport_radio0 + output wire [ 1-1:0] m_ctrlport_radio0_req_wr, + output wire [ 1-1:0] m_ctrlport_radio0_req_rd, + output wire [ 20-1:0] m_ctrlport_radio0_req_addr, + output wire [ 32-1:0] m_ctrlport_radio0_req_data, + output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio0_req_time, + input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio0_resp_status, + input wire [ 32-1:0] m_ctrlport_radio0_resp_data, +// ctrlport_radio1 + output wire [ 1-1:0] m_ctrlport_radio1_req_wr, + output wire [ 1-1:0] m_ctrlport_radio1_req_rd, + output wire [ 20-1:0] m_ctrlport_radio1_req_addr, + output wire [ 32-1:0] m_ctrlport_radio1_req_data, + output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, + output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, + output wire [ 64-1:0] m_ctrlport_radio1_req_time, + input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, + input wire [ 2-1:0] m_ctrlport_radio1_resp_status, + input wire [ 32-1:0] m_ctrlport_radio1_resp_data, +// time_keeper + input wire [ 64-1:0] radio_time, +// x300_radio0 + input wire [ 64-1:0] radio_rx_data_radio0, + input wire [ 2-1:0] radio_rx_stb_radio0, + output wire [ 2-1:0] radio_rx_running_radio0, + output wire [ 64-1:0] radio_tx_data_radio0, + input wire [ 2-1:0] radio_tx_stb_radio0, + output wire [ 2-1:0] radio_tx_running_radio0, +// x300_radio1 + input wire [ 64-1:0] radio_rx_data_radio1, + input wire [ 2-1:0] radio_rx_stb_radio1, + output wire [ 2-1:0] radio_rx_running_radio1, + output wire [ 64-1:0] radio_tx_data_radio1, + input wire [ 2-1:0] radio_tx_stb_radio1, + output wire [ 2-1:0] radio_tx_running_radio1, +// dram + input wire [ 1-1:0] axi_rst, + output wire [ 2-1:0] m_axi_awid, + output wire [ 64-1:0] m_axi_awaddr, + output wire [ 16-1:0] m_axi_awlen, + output wire [ 6-1:0] m_axi_awsize, + output wire [ 4-1:0] m_axi_awburst, + output wire [ 2-1:0] m_axi_awlock, + output wire [ 8-1:0] m_axi_awcache, + output wire [ 6-1:0] m_axi_awprot, + output wire [ 8-1:0] m_axi_awqos, + output wire [ 8-1:0] m_axi_awregion, + output wire [ 2-1:0] m_axi_awuser, + output wire [ 2-1:0] m_axi_awvalid, + input wire [ 2-1:0] m_axi_awready, + output wire [128-1:0] m_axi_wdata, + output wire [ 16-1:0] m_axi_wstrb, + output wire [ 2-1:0] m_axi_wlast, + output wire [ 2-1:0] m_axi_wuser, + output wire [ 2-1:0] m_axi_wvalid, + input wire [ 2-1:0] m_axi_wready, + input wire [ 2-1:0] m_axi_bid, + input wire [ 4-1:0] m_axi_bresp, + input wire [ 2-1:0] m_axi_buser, + input wire [ 2-1:0] m_axi_bvalid, + output wire [ 2-1:0] m_axi_bready, + output wire [ 2-1:0] m_axi_arid, + output wire [ 64-1:0] m_axi_araddr, + output wire [ 16-1:0] m_axi_arlen, + output wire [ 6-1:0] m_axi_arsize, + output wire [ 4-1:0] m_axi_arburst, + output wire [ 2-1:0] m_axi_arlock, + output wire [ 8-1:0] m_axi_arcache, + output wire [ 6-1:0] m_axi_arprot, + output wire [ 8-1:0] m_axi_arqos, + output wire [ 8-1:0] m_axi_arregion, + output wire [ 2-1:0] m_axi_aruser, + output wire [ 2-1:0] m_axi_arvalid, + input wire [ 2-1:0] m_axi_arready, + input wire [ 2-1:0] m_axi_rid, + input wire [128-1:0] m_axi_rdata, + input wire [ 4-1:0] m_axi_rresp, + input wire [ 2-1:0] m_axi_rlast, + input wire [ 2-1:0] m_axi_ruser, + input wire [ 2-1:0] m_axi_rvalid, + output wire [ 2-1:0] m_axi_rready, + // Transport 0 (eth0 10G) + input wire [64-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [64-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1 1G) + input wire [64-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [64-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (pcie PCIe) + input wire [64-1:0] s_pcie_tdata, + input wire s_pcie_tlast, + input wire s_pcie_tvalid, + output wire s_pcie_tready, + output wire [64-1:0] m_pcie_tdata, + output wire m_pcie_tlast, + output wire m_pcie_tvalid, + input wire m_pcie_tready +); + + localparam CHDR_W = 64; + localparam MTU = 10; + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + // ---------------------------------------------------- + // CHDR Crossbar + // ---------------------------------------------------- + wire [CHDR_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [CHDR_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [CHDR_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [CHDR_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [CHDR_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [CHDR_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + + chdr_crossbar_nxn #( + .CHDR_W (CHDR_W), + .NPORTS (7), + .DEFAULT_PORT (0), + .MTU (MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (3), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_xb_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_pcie_tdata, s_eth1_tdata, s_eth0_tdata}), + .s_axis_tlast ({ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_pcie_tlast, s_eth1_tlast, s_eth0_tlast}), + .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_pcie_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_pcie_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_pcie_tdata, m_eth1_tdata, m_eth0_tdata}), + .m_axis_tlast ({xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_pcie_tlast, m_eth1_tlast, m_eth0_tlast}), + .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_pcie_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_pcie_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + // ---------------------------------------------------- + // Stream Endpoints + // ---------------------------------------------------- + + wire [CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; + wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (16), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep0_tdata ), + .s_axis_chdr_tlast (xb_to_ep0_tlast ), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), + .s_axis_chdr_tready (xb_to_ep0_tready ), + .m_axis_chdr_tdata (ep0_to_xb_tdata ), + .m_axis_chdr_tlast (ep0_to_xb_tlast ), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), + .m_axis_chdr_tready (ep0_to_xb_tready ), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; + wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (5), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep1_tdata ), + .s_axis_chdr_tlast (xb_to_ep1_tlast ), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), + .s_axis_chdr_tready (xb_to_ep1_tready ), + .m_axis_chdr_tdata (ep1_to_xb_tdata ), + .m_axis_chdr_tlast (ep1_to_xb_tlast ), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), + .m_axis_chdr_tready (ep1_to_xb_tready ), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; + wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (16), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep2_tdata ), + .s_axis_chdr_tlast (xb_to_ep2_tlast ), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), + .s_axis_chdr_tready (xb_to_ep2_tready ), + .m_axis_chdr_tdata (ep2_to_xb_tdata ), + .m_axis_chdr_tlast (ep2_to_xb_tlast ), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), + .m_axis_chdr_tready (ep2_to_xb_tready ), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + wire [CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; + wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .PROTOVER (PROTOVER), + .CHDR_W (CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (5), + .MTU (MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk ), + .rfnoc_chdr_rst (rfnoc_chdr_rst ), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), + .device_id (device_id ), + .s_axis_chdr_tdata (xb_to_ep3_tdata ), + .s_axis_chdr_tlast (xb_to_ep3_tlast ), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), + .s_axis_chdr_tready (xb_to_ep3_tready ), + .m_axis_chdr_tdata (ep3_to_xb_tdata ), + .m_axis_chdr_tlast (ep3_to_xb_tlast ), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), + .m_axis_chdr_tready (ep3_to_xb_tready ), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb ( ), + .strm_data_err_stb ( ), + .strm_route_err_stb ( ), + .signal_data_err (1'b0 ) + ); + + + + // ---------------------------------------------------- + // Control Crossbar + // ---------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; + wire m_core_ctrl_tlast , s_core_ctrl_tlast ; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_duc0_ctrl_tdata , s_duc0_ctrl_tdata ; + wire m_duc0_ctrl_tlast , s_duc0_ctrl_tlast ; + wire m_duc0_ctrl_tvalid, s_duc0_ctrl_tvalid; + wire m_duc0_ctrl_tready, s_duc0_ctrl_tready; + wire [31:0] m_ddc0_ctrl_tdata , s_ddc0_ctrl_tdata ; + wire m_ddc0_ctrl_tlast , s_ddc0_ctrl_tlast ; + wire m_ddc0_ctrl_tvalid, s_ddc0_ctrl_tvalid; + wire m_ddc0_ctrl_tready, s_ddc0_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; + wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_duc1_ctrl_tdata , s_duc1_ctrl_tdata ; + wire m_duc1_ctrl_tlast , s_duc1_ctrl_tlast ; + wire m_duc1_ctrl_tvalid, s_duc1_ctrl_tvalid; + wire m_duc1_ctrl_tready, s_duc1_ctrl_tready; + wire [31:0] m_ddc1_ctrl_tdata , s_ddc1_ctrl_tdata ; + wire m_ddc1_ctrl_tlast , s_ddc1_ctrl_tlast ; + wire m_ddc1_ctrl_tvalid, s_ddc1_ctrl_tvalid; + wire m_ddc1_ctrl_tready, s_ddc1_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; + wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (8), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_ddc1_ctrl_tdata , m_duc1_ctrl_tdata , m_radio0_ctrl_tdata , m_ddc0_ctrl_tdata , m_duc0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_ddc1_ctrl_tvalid, m_duc1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ddc0_ctrl_tvalid, m_duc0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_ddc1_ctrl_tlast , m_duc1_ctrl_tlast , m_radio0_ctrl_tlast , m_ddc0_ctrl_tlast , m_duc0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_ddc1_ctrl_tready, m_duc1_ctrl_tready, m_radio0_ctrl_tready, m_ddc0_ctrl_tready, m_duc0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_ddc1_ctrl_tdata , s_duc1_ctrl_tdata , s_radio0_ctrl_tdata , s_ddc0_ctrl_tdata , s_duc0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_ddc1_ctrl_tvalid, s_duc1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ddc0_ctrl_tvalid, s_duc0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_ddc1_ctrl_tlast , s_duc1_ctrl_tlast , s_radio0_ctrl_tlast , s_ddc0_ctrl_tlast , s_duc0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_ddc1_ctrl_tready, s_duc1_ctrl_tready, s_radio0_ctrl_tready, s_ddc0_ctrl_tready, s_duc0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + // ---------------------------------------------------- + // RFNoC Core Kernel + // ---------------------------------------------------- + wire [(512*6)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hA300), + .DEVICE_FAMILY ("7SERIES"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (6), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (3), + .NUM_EDGES (12), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata ), + .s_axis_ctrl_tlast (s_core_ctrl_tlast ), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata ), + .m_axis_ctrl_tlast (m_core_ctrl_tlast ), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + // ---------------------------------------------------- + // Blocks + // ---------------------------------------------------- + + // ---------------------------------------------------- + // duc0 + // ---------------------------------------------------- + wire duc0_ce_clk; + wire [CHDR_W-1:0] s_duc0_in_0_tdata ; + wire s_duc0_in_0_tlast ; + wire s_duc0_in_0_tvalid; + wire s_duc0_in_0_tready; + wire [CHDR_W-1:0] m_duc0_out_0_tdata ; + wire m_duc0_out_0_tlast ; + wire m_duc0_out_0_tvalid; + wire m_duc0_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(2), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + + + .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc0 + // ---------------------------------------------------- + wire ddc0_ce_clk; + wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; + wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; + wire s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid; + wire s_ddc0_in_1_tready, s_ddc0_in_0_tready; + wire [CHDR_W-1:0] m_ddc0_out_1_tdata , m_ddc0_out_0_tdata ; + wire m_ddc0_out_1_tlast , m_ddc0_out_0_tlast ; + wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; + wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(3), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc0_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc0_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + + + .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc0_in_1_tready, s_ddc0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc0_out_1_tdata , m_ddc0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc0_out_1_tready, m_ddc0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio0 + // ---------------------------------------------------- + wire radio0_radio_clk; + wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio0_m_ctrlport_req_wr; + wire [ 1-1:0] radio0_m_ctrlport_req_rd; + wire [ 20-1:0] radio0_m_ctrlport_req_addr; + wire [ 32-1:0] radio0_m_ctrlport_req_data; + wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio0_m_ctrlport_req_has_time; + wire [ 64-1:0] radio0_m_ctrlport_req_time; + wire [ 1-1:0] radio0_m_ctrlport_resp_ack; + wire [ 2-1:0] radio0_m_ctrlport_resp_status; + wire [ 32-1:0] radio0_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio0_radio_time; + // x300_radio + wire [ 64-1:0] radio0_radio_rx_data; + wire [ 2-1:0] radio0_radio_rx_stb; + wire [ 2-1:0] radio0_radio_rx_running; + wire [ 64-1:0] radio0_radio_tx_data; + wire [ 2-1:0] radio0_radio_tx_stb; + wire [ 2-1:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(4), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + + .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time(radio0_radio_time), + .radio_rx_data(radio0_radio_rx_data), + .radio_rx_stb(radio0_radio_rx_stb), + .radio_rx_running(radio0_radio_rx_running), + .radio_tx_data(radio0_radio_tx_data), + .radio_tx_stb(radio0_radio_tx_stb), + .radio_tx_running(radio0_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) + ); + + + // ---------------------------------------------------- + // duc1 + // ---------------------------------------------------- + wire duc1_ce_clk; + wire [CHDR_W-1:0] s_duc1_in_0_tdata ; + wire s_duc1_in_0_tlast ; + wire s_duc1_in_0_tvalid; + wire s_duc1_in_0_tready; + wire [CHDR_W-1:0] m_duc1_out_0_tdata ; + wire m_duc1_out_0_tlast ; + wire m_duc1_out_0_tvalid; + wire m_duc1_out_0_tready; + + + rfnoc_block_duc #( + .THIS_PORTID(5), + .CHDR_W(CHDR_W), + .NUM_PORTS(1), + .NUM_HB(3), + .CIC_MAX_INTERP(255), + .MTU(MTU) + ) b_duc1_3 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(duc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), + .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), + + + .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_duc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_duc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_duc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_duc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_duc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_duc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_duc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_duc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_duc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // ddc1 + // ---------------------------------------------------- + wire ddc1_ce_clk; + wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; + wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; + wire s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid; + wire s_ddc1_in_1_tready, s_ddc1_in_0_tready; + wire [CHDR_W-1:0] m_ddc1_out_1_tdata , m_ddc1_out_0_tdata ; + wire m_ddc1_out_1_tlast , m_ddc1_out_0_tlast ; + wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; + wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; + + + rfnoc_block_ddc #( + .THIS_PORTID(6), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .NUM_HB(3), + .CIC_MAX_DECIM(255), + .MTU(MTU) + ) b_ddc1_4 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .ce_clk(ddc1_ce_clk), + .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), + .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), + + + .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_ddc1_in_1_tready, s_ddc1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_ddc1_out_1_tdata , m_ddc1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_ddc1_out_1_tready, m_ddc1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_ddc1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_ddc1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_ddc1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_ddc1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // radio1 + // ---------------------------------------------------- + wire radio1_radio_clk; + wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrl_port + wire [ 1-1:0] radio1_m_ctrlport_req_wr; + wire [ 1-1:0] radio1_m_ctrlport_req_rd; + wire [ 20-1:0] radio1_m_ctrlport_req_addr; + wire [ 32-1:0] radio1_m_ctrlport_req_data; + wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; + wire [ 1-1:0] radio1_m_ctrlport_req_has_time; + wire [ 64-1:0] radio1_m_ctrlport_req_time; + wire [ 1-1:0] radio1_m_ctrlport_resp_ack; + wire [ 2-1:0] radio1_m_ctrlport_resp_status; + wire [ 32-1:0] radio1_m_ctrlport_resp_data; + // time_keeper + wire [ 64-1:0] radio1_radio_time; + // x300_radio + wire [ 64-1:0] radio1_radio_rx_data; + wire [ 2-1:0] radio1_radio_rx_stb; + wire [ 2-1:0] radio1_radio_rx_running; + wire [ 64-1:0] radio1_radio_tx_data; + wire [ 2-1:0] radio1_radio_tx_stb; + wire [ 2-1:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID(7), + .CHDR_W(CHDR_W), + .NUM_PORTS(2), + .MTU(MTU) + ) b_radio1_5 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk(radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), + .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), + + .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data(radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time(radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time(radio1_radio_time), + .radio_rx_data(radio1_radio_rx_data), + .radio_rx_stb(radio1_radio_rx_stb), + .radio_rx_running(radio1_radio_rx_running), + .radio_tx_data(radio1_radio_tx_data), + .radio_tx_stb(radio1_radio_tx_stb), + .radio_tx_running(radio1_radio_tx_running), + + .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), + .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), + .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) + ); + + + // ---------------------------------------------------- + // Static Router + // ---------------------------------------------------- + assign s_duc0_in_0_tdata = m_ep0_out0_tdata ; + assign s_duc0_in_0_tlast = m_ep0_out0_tlast ; + assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_duc0_in_0_tready; + + assign s_radio0_in_0_tdata = m_duc0_out_0_tdata ; + assign s_radio0_in_0_tlast = m_duc0_out_0_tlast ; + assign s_radio0_in_0_tvalid = m_duc0_out_0_tvalid; + assign m_duc0_out_0_tready = s_radio0_in_0_tready; + + assign s_ddc0_in_0_tdata = m_radio0_out_0_tdata ; + assign s_ddc0_in_0_tlast = m_radio0_out_0_tlast ; + assign s_ddc0_in_0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ddc0_in_0_tready; + + assign s_ep0_in0_tdata = m_ddc0_out_0_tdata ; + assign s_ep0_in0_tlast = m_ddc0_out_0_tlast ; + assign s_ep0_in0_tvalid = m_ddc0_out_0_tvalid; + assign m_ddc0_out_0_tready = s_ep0_in0_tready; + + assign s_ddc0_in_1_tdata = m_radio0_out_1_tdata ; + assign s_ddc0_in_1_tlast = m_radio0_out_1_tlast ; + assign s_ddc0_in_1_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ddc0_in_1_tready; + + assign s_ep1_in0_tdata = m_ddc0_out_1_tdata ; + assign s_ep1_in0_tlast = m_ddc0_out_1_tlast ; + assign s_ep1_in0_tvalid = m_ddc0_out_1_tvalid; + assign m_ddc0_out_1_tready = s_ep1_in0_tready; + + assign s_duc1_in_0_tdata = m_ep2_out0_tdata ; + assign s_duc1_in_0_tlast = m_ep2_out0_tlast ; + assign s_duc1_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_duc1_in_0_tready; + + assign s_radio1_in_0_tdata = m_duc1_out_0_tdata ; + assign s_radio1_in_0_tlast = m_duc1_out_0_tlast ; + assign s_radio1_in_0_tvalid = m_duc1_out_0_tvalid; + assign m_duc1_out_0_tready = s_radio1_in_0_tready; + + assign s_ddc1_in_0_tdata = m_radio1_out_0_tdata ; + assign s_ddc1_in_0_tlast = m_radio1_out_0_tlast ; + assign s_ddc1_in_0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ddc1_in_0_tready; + + assign s_ep2_in0_tdata = m_ddc1_out_0_tdata ; + assign s_ep2_in0_tlast = m_ddc1_out_0_tlast ; + assign s_ep2_in0_tvalid = m_ddc1_out_0_tvalid; + assign m_ddc1_out_0_tready = s_ep2_in0_tready; + + assign s_ddc1_in_1_tdata = m_radio1_out_1_tdata ; + assign s_ddc1_in_1_tlast = m_radio1_out_1_tlast ; + assign s_ddc1_in_1_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ddc1_in_1_tready; + + assign s_ep3_in0_tdata = m_ddc1_out_1_tdata ; + assign s_ep3_in0_tlast = m_ddc1_out_1_tlast ; + assign s_ep3_in0_tvalid = m_ddc1_out_1_tvalid; + assign m_ddc1_out_1_tready = s_ep3_in0_tready; + + + // ---------------------------------------------------- + // Unused Ports + // ---------------------------------------------------- + assign s_radio0_in_1_tdata = {CHDR_W{1'b0}}; + assign s_radio0_in_1_tlast = 1'b0; + assign s_radio0_in_1_tvalid = 1'b0; + assign s_radio1_in_1_tdata = {CHDR_W{1'b0}}; + assign s_radio1_in_1_tlast = 1'b0; + assign s_radio1_in_1_tvalid = 1'b0; + assign m_ep1_out0_tready = 1'b1; + assign m_ep3_out0_tready = 1'b1; + + // ---------------------------------------------------- + // Clock Domains + // ---------------------------------------------------- + assign radio0_radio_clk = radio_clk; + assign ddc0_ce_clk = ce_clk; + assign duc0_ce_clk = ce_clk; + assign radio1_radio_clk = radio_clk; + assign ddc1_ce_clk = ce_clk; + assign duc1_ce_clk = ce_clk; + + + // ---------------------------------------------------- + // IO Port Connection + // ---------------------------------------------------- + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time; + + assign radio1_radio_time = radio_time; + +endmodule diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml new file mode 100644 index 000000000..5d6a98c7d --- /dev/null +++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml @@ -0,0 +1,113 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers +license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers +version: 1.0 # File version +rfnoc_version: 1.0 # RFNoC protocol version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'x310' +default_target: 'X310_HG' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 65536 # Ingress buffer size for data + ep1: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 0 # Ingress buffer size for data + ep2: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 65536 # Ingress buffer size for data + ep3: # Stream endpoint name + ctrl: False # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 0 # Ingress buffer size for data + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + duc0: # NoC block name + block_desc: 'duc.yml' # Block device descriptor file + parameters: + NUM_PORTS: 1 + ddc0: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio0: + block_desc: 'radio_2x64.yml' + duc1: + block_desc: 'duc.yml' + parameters: + NUM_PORTS: 1 + ddc1: + block_desc: 'ddc.yml' + parameters: + NUM_PORTS: 2 + radio1: + block_desc: 'radio_2x64.yml' + # These parameters are for reference, in case a DRAM FIFO is required + #fifo0: + #block_desc: 'axi_ram_fifo_2x64.yml' + #parameters: + ## These parameters match the interface on the x300/X310 + #MEM_DATA_W: 64 + #MEM_ADDR_W: 30 + #FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}" + #FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}" + #MEM_CLK_RATE: "300e6" + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # ep0 to radio0(0) - RFA TX + - { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 } + - { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 } + # radio0(0) to ep0 - RFA RX + - { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 } + - { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 } + # radio0(1) to ep1 - RFA RX + - { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 } + - { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 } + # ep2 to radio1(0) - RFB TX + - { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 } + - { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 } + # radio1(0) to ep2 - RFB RX + - { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 } + - { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 } + # radio1(1) to ep3 - RFB RX + - { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 } + - { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 } + # BSP Connections + - { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: x300_radio0, dstblk: radio0, dstport: x300_radio } + - { srcblk: _device_, srcport: x300_radio1, dstblk: radio1, dstport: x300_radio } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper } + - { srcblk: _device_, srcport: time_keeper, dstblk: radio1, dstport: time_keeper } + +# A list of all clock domain connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce } diff --git a/fpga/usrp3/top/x300/x310_static_router.hex b/fpga/usrp3/top/x300/x310_static_router.hex new file mode 100644 index 000000000..53635706f --- /dev/null +++ b/fpga/usrp3/top/x300/x310_static_router.hex @@ -0,0 +1,13 @@ +0000000C +00400140 +014001c0 +01c00180 +01800040 +01c10181 +01810080 +00c00200 +02000280 +02800240 +024000c0 +02810241 +02410100 diff --git a/fpga/usrp3/top/x300/x3x0_base.lvbitx b/fpga/usrp3/top/x300/x3x0_base.lvbitx new file mode 100644 index 000000000..c264e7157 --- /dev/null +++ b/fpga/usrp3/top/x300/x3x0_base.lvbitx @@ -0,0 +1,469 @@ + + + 4.0 + + + + + 97C6D9F4F4829001B83378F93CAB0C94 + 7BAD6AEB9741248079F13147B3F8AD94 + AE54C47F787D92DB46F7DC973338D786 + + + 2 + + USRP_X3x0_Top.vi + + + ViSignature + true + true + + + + 4 + + + + + + + + + + 262132 + 128 + 0 + true + + + 0 + false + false + Switch When Pressed + false + false + + + + DiagramReset + false + false + + + + + + + + 262140 + 32 + 0 + true + + + 0 + true + false + Switch When Pressed + false + false + + + + ViControl + false + false + + + + + + + + 262136 + 32 + 0 + true + + + 0 + true + false + Switch When Pressed + false + false + + + + InterruptEnable + false + false + + + + + + + + 262116 + 32 + 0 + true + + + 0 + true + false + Switch When Pressed + false + false + + + + InterruptMask + false + false + + + + + + + + 262124 + 32 + 0 + true + + + 0 + true + false + Switch When Pressed + false + false + + + + InterruptStatus + false + false + + + + + + + + 262128 + 32 + 0 + true + + + 0 + true + false + Switch When Pressed + false + false + + + + + 0 + 8 + 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18446744073709551600.00000000000000000000000000000000000 + 0.000000000000000000000000000000000000000000000000000000 + false + U64 + 64 + + HostToTarget + niFpgaHostToTarget + 10 + 1029 + true + + + NiLvFpgaFIFO 11 + 11 + + 1.000000000000000000000000000000000000000000000000000000 + 64 + 18446744073709551600.00000000000000000000000000000000000 + 0.000000000000000000000000000000000000000000000000000000 + false + U64 + 64 + + HostToTarget + niFpgaHostToTarget + 11 + 1029 + true + + + + + 0xFF80 + + + 0xFF40 + + + 0xFF00 + + + 0xFEC0 + + + 0xFE80 + + + 0xFE40 + + + 0xFE00 + + + 0xFDC0 + + + 0xFD80 + + + 0xFD40 + + + 0xFD00 + + + 0xFCC0 + + + + + + + + + + + 1 + + + + false + false + + + a72ba1716893a0bd02f88dac3ab28e1b + a72ba1716893a0bd02f88dac3ab28e1b + -- cgit v1.2.3 


+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+